X-Git-Url: http://git.openwrt.org/?p=openwrt%2Fopenwrt.git;a=blobdiff_plain;f=target%2Flinux%2Fbrcm47xx%2Fpatches-4.14%2F159-cpu_fixes.patch;h=3de77b1afd8e1f541c84f2ec5fc5c9a89c869db3;hp=96917f82a63df859627a1413ec6082c763207a61;hb=939fa07b041fef58196fba8dd4b5184adb7b4d3f;hpb=cae263227ffdec1bd0d005b7752f25b6ebc6f8fa diff --git a/target/linux/brcm47xx/patches-4.14/159-cpu_fixes.patch b/target/linux/brcm47xx/patches-4.14/159-cpu_fixes.patch index 96917f82a6..3de77b1afd 100644 --- a/target/linux/brcm47xx/patches-4.14/159-cpu_fixes.patch +++ b/target/linux/brcm47xx/patches-4.14/159-cpu_fixes.patch @@ -1,6 +1,6 @@ --- a/arch/mips/include/asm/r4kcache.h +++ b/arch/mips/include/asm/r4kcache.h -@@ -25,6 +25,38 @@ +@@ -26,6 +26,38 @@ extern void (*r4k_blast_dcache)(void); extern void (*r4k_blast_icache)(void); @@ -39,7 +39,7 @@ /* * This macro return a properly sign-extended address suitable as base address * for indexed cache operations. Two issues here: -@@ -98,6 +130,7 @@ static inline void flush_icache_line_ind +@@ -99,6 +131,7 @@ static inline void flush_icache_line_ind static inline void flush_dcache_line_indexed(unsigned long addr) { __dflush_prologue @@ -47,7 +47,7 @@ cache_op(Index_Writeback_Inv_D, addr); __dflush_epilogue } -@@ -125,6 +158,7 @@ static inline void flush_icache_line(uns +@@ -126,6 +159,7 @@ static inline void flush_icache_line(uns static inline void flush_dcache_line(unsigned long addr) { __dflush_prologue @@ -55,7 +55,7 @@ cache_op(Hit_Writeback_Inv_D, addr); __dflush_epilogue } -@@ -132,6 +166,7 @@ static inline void flush_dcache_line(uns +@@ -133,6 +167,7 @@ static inline void flush_dcache_line(uns static inline void invalidate_dcache_line(unsigned long addr) { __dflush_prologue @@ -63,7 +63,7 @@ cache_op(Hit_Invalidate_D, addr); __dflush_epilogue } -@@ -205,6 +240,7 @@ static inline int protected_flush_icache +@@ -206,6 +241,7 @@ static inline int protected_flush_icache #ifdef CONFIG_EVA return protected_cachee_op(Hit_Invalidate_I, addr); #else @@ -71,7 +71,7 @@ return protected_cache_op(Hit_Invalidate_I, addr); #endif } -@@ -218,6 +254,7 @@ static inline int protected_flush_icache +@@ -219,6 +255,7 @@ static inline int protected_flush_icache */ static inline int protected_writeback_dcache_line(unsigned long addr) { @@ -79,7 +79,7 @@ #ifdef CONFIG_EVA return protected_cachee_op(Hit_Writeback_Inv_D, addr); #else -@@ -575,8 +612,51 @@ static inline void invalidate_tcache_pag +@@ -576,8 +613,51 @@ static inline void invalidate_tcache_pag : "r" (base), \ "i" (op)); @@ -132,7 +132,7 @@ static inline void extra##blast_##pfx##cache##lsize(void) \ { \ unsigned long start = INDEX_BASE; \ -@@ -588,6 +668,7 @@ static inline void extra##blast_##pfx##c +@@ -589,6 +669,7 @@ static inline void extra##blast_##pfx##c \ __##pfx##flush_prologue \ \ @@ -140,7 +140,7 @@ for (ws = 0; ws < ws_end; ws += ws_inc) \ for (addr = start; addr < end; addr += lsize * 32) \ cache##lsize##_unroll32(addr|ws, indexop); \ -@@ -602,6 +683,7 @@ static inline void extra##blast_##pfx##c +@@ -603,6 +684,7 @@ static inline void extra##blast_##pfx##c \ __##pfx##flush_prologue \ \ @@ -148,7 +148,7 @@ do { \ cache##lsize##_unroll32(start, hitop); \ start += lsize * 32; \ -@@ -620,6 +702,8 @@ static inline void extra##blast_##pfx##c +@@ -621,6 +703,8 @@ static inline void extra##blast_##pfx##c current_cpu_data.desc.waybit; \ unsigned long ws, addr; \ \ @@ -157,7 +157,7 @@ __##pfx##flush_prologue \ \ for (ws = 0; ws < ws_end; ws += ws_inc) \ -@@ -629,26 +713,26 @@ static inline void extra##blast_##pfx##c +@@ -630,26 +714,26 @@ static inline void extra##blast_##pfx##c __##pfx##flush_epilogue \ } @@ -204,7 +204,7 @@ #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \ static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \ -@@ -677,53 +761,23 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde +@@ -678,53 +762,23 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) /* build blast_xxx_range, protected_blast_xxx_range */ @@ -266,7 +266,7 @@ } \ \ __##pfx##flush_epilogue \ -@@ -731,8 +785,8 @@ static inline void prot##extra##blast_## +@@ -732,8 +786,8 @@ static inline void prot##extra##blast_## #ifndef CONFIG_EVA @@ -277,7 +277,7 @@ #else -@@ -769,14 +823,14 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache +@@ -770,15 +824,15 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache __BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I) #endif @@ -298,7 +298,8 @@ +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();) +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , ) - #endif /* _ASM_R4KCACHE_H */ + /* Currently, this is very specific to Loongson-3 */ + #define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize) \ --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -428,6 +428,10 @@ @@ -396,7 +397,7 @@ if (dc_lsize == 0) r4k_blast_dcache = (void *)cache_noop; else if (dc_lsize == 16) -@@ -957,6 +969,8 @@ static void local_r4k_flush_cache_sigtra +@@ -986,6 +998,8 @@ static void local_r4k_flush_cache_sigtra } R4600_HIT_CACHEOP_WAR_IMPL; @@ -405,7 +406,7 @@ if (!cpu_has_ic_fills_f_dc) { if (dc_lsize) vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1)) -@@ -1851,6 +1865,17 @@ static void coherency_setup(void) +@@ -1880,6 +1894,17 @@ static void coherency_setup(void) * silly idea of putting something else there ... */ switch (current_cpu_type()) { @@ -423,7 +424,7 @@ case CPU_R4000PC: case CPU_R4000SC: case CPU_R4000MC: -@@ -1897,6 +1922,15 @@ void r4k_cache_init(void) +@@ -1926,6 +1951,15 @@ void r4k_cache_init(void) extern void build_copy_page(void); struct cpuinfo_mips *c = ¤t_cpu_data; @@ -439,7 +440,7 @@ probe_pcache(); probe_vcache(); setup_scache(); -@@ -1974,7 +2008,15 @@ void r4k_cache_init(void) +@@ -2004,7 +2038,15 @@ void r4k_cache_init(void) */ local_r4k___flush_cache_all(NULL);