X-Git-Url: http://git.openwrt.org/?p=openwrt%2Fopenwrt.git;a=blobdiff_plain;f=target%2Flinux%2Fgeneric%2Ffiles%2Fdrivers%2Fnet%2Fphy%2Far8216.h;h=6a3fd8db0110187f9c6f315572f6b85d6569975d;hp=eb553b489d552d21a2e86fd8261eaef8161e2c60;hb=7eeb254cc49c4e9f837c980826ec112b9404f341;hpb=a17a58e310e41829a634ac507477a0f6457a65d0 diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.h b/target/linux/generic/files/drivers/net/phy/ar8216.h index eb553b489d..6a3fd8db01 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8216.h +++ b/target/linux/generic/files/drivers/net/phy/ar8216.h @@ -1,7 +1,7 @@ /* * ar8216.h: AR8216 switch driver * - * Copyright (C) 2009 Felix Fietkau + * Copyright (C) 2009 Felix Fietkau * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -19,11 +19,23 @@ #define BITS(_s, _n) (((1UL << (_n)) - 1) << _s) +#define AR8XXX_CAP_GIGE BIT(0) +#define AR8XXX_CAP_MIB_COUNTERS BIT(1) + +#define AR8XXX_NUM_PHYS 5 #define AR8216_PORT_CPU 0 #define AR8216_NUM_PORTS 6 #define AR8216_NUM_VLANS 16 #define AR8316_NUM_VLANS 4096 +/* size of the vlan table */ +#define AR8X16_MAX_VLANS 128 +#define AR8X16_PROBE_RETRIES 10 +#define AR8X16_MAX_PORTS 8 + +#define AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS 7 +#define AR8XXX_DEFAULT_ARL_AGE_TIME 300 + /* Atheros specific MII registers */ #define MII_ATH_MMD_ADDR 0x0d #define MII_ATH_MMD_DATA 0x0e @@ -40,6 +52,8 @@ #define AR8216_REG_FLOOD_MASK 0x002C #define AR8216_FM_UNI_DEST_PORTS BITS(0, 6) #define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6) +#define AR8236_FM_CPU_BROADCAST_EN BIT(26) +#define AR8236_FM_CPU_BCAST_FWD_EN BIT(25) #define AR8216_REG_GLOBAL_CTRL 0x0030 #define AR8216_GCTRL_MTU BITS(0, 11) @@ -68,31 +82,50 @@ #define AR8236_VTUDATA_MEMBER BITS(0, 7) #define AR8216_VTUDATA_VALID BIT(11) -#define AR8216_REG_ATU 0x0050 +#define AR8216_REG_ATU_FUNC0 0x0050 #define AR8216_ATU_OP BITS(0, 3) #define AR8216_ATU_OP_NOOP 0x0 #define AR8216_ATU_OP_FLUSH 0x1 #define AR8216_ATU_OP_LOAD 0x2 #define AR8216_ATU_OP_PURGE 0x3 -#define AR8216_ATU_OP_FLUSH_LOCKED 0x4 -#define AR8216_ATU_OP_FLUSH_UNICAST 0x5 +#define AR8216_ATU_OP_FLUSH_UNLOCKED 0x4 +#define AR8216_ATU_OP_FLUSH_PORT 0x5 #define AR8216_ATU_OP_GET_NEXT 0x6 #define AR8216_ATU_ACTIVE BIT(3) #define AR8216_ATU_PORT_NUM BITS(8, 4) +#define AR8216_ATU_PORT_NUM_S 8 #define AR8216_ATU_FULL_VIO BIT(12) -#define AR8216_ATU_ADDR4 BITS(16, 8) -#define AR8216_ATU_ADDR5 BITS(24, 8) +#define AR8216_ATU_ADDR5 BITS(16, 8) +#define AR8216_ATU_ADDR5_S 16 +#define AR8216_ATU_ADDR4 BITS(24, 8) +#define AR8216_ATU_ADDR4_S 24 -#define AR8216_REG_ATU_DATA 0x0054 +#define AR8216_REG_ATU_FUNC1 0x0054 #define AR8216_ATU_ADDR3 BITS(0, 8) +#define AR8216_ATU_ADDR3_S 0 #define AR8216_ATU_ADDR2 BITS(8, 8) +#define AR8216_ATU_ADDR2_S 8 #define AR8216_ATU_ADDR1 BITS(16, 8) +#define AR8216_ATU_ADDR1_S 16 #define AR8216_ATU_ADDR0 BITS(24, 8) +#define AR8216_ATU_ADDR0_S 24 + +#define AR8216_REG_ATU_FUNC2 0x0058 +#define AR8216_ATU_PORTS BITS(0, 6) +#define AR8216_ATU_PORT0 BIT(0) +#define AR8216_ATU_PORT1 BIT(1) +#define AR8216_ATU_PORT2 BIT(2) +#define AR8216_ATU_PORT3 BIT(3) +#define AR8216_ATU_PORT4 BIT(4) +#define AR8216_ATU_PORT5 BIT(5) +#define AR8216_ATU_STATUS BITS(16, 4) +#define AR8216_ATU_STATUS_S 16 #define AR8216_REG_ATU_CTRL 0x005C #define AR8216_ATU_CTRL_AGE_EN BIT(17) #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16) #define AR8216_ATU_CTRL_AGE_TIME_S 0 +#define AR8236_ATU_CTRL_RES BIT(20) #define AR8216_REG_MIB_FUNC 0x0080 #define AR8216_MIB_TIMER BITS(0, 16) @@ -164,8 +197,6 @@ #define AR8216_REG_PORT_RATE(_i) (AR8216_PORT_OFFSET(_i) + 0x000c) #define AR8216_REG_PORT_PRIO(_i) (AR8216_PORT_OFFSET(_i) + 0x0010) -#define AR8216_REG_PORT_STATS_BASE(_i) (0x19000 + (_i) * 0xa0) - #define AR8216_STATS_RXBROAD 0x00 #define AR8216_STATS_RXPAUSE 0x04 #define AR8216_STATS_RXMULTI 0x08 @@ -217,8 +248,6 @@ #define AR8236_PORT_VLAN2_VLAN_MODE BITS(30, 2) #define AR8236_PORT_VLAN2_VLAN_MODE_S 30 -#define AR8236_REG_PORT_STATS_BASE(_i) (0x20000 + (_i) * 0x100) - #define AR8236_STATS_RXBROAD 0x00 #define AR8236_STATS_RXPAUSE 0x04 #define AR8236_STATS_RXMULTI 0x08 @@ -289,177 +318,6 @@ #define AR8316_POSTRIP_RXDELAY_S1 BIT(26) #define AR8316_POSTRIP_POWER_ON_SEL BIT(31) -#define AR8327_NUM_PORTS 7 -#define AR8327_NUM_LEDS 15 -#define AR8327_NUM_PHYS 5 -#define AR8327_PORTS_ALL 0x7f -#define AR8327_NUM_LED_CTRL_REGS 4 - -#define AR8327_REG_MASK 0x000 - -#define AR8327_REG_PAD0_MODE 0x004 -#define AR8327_REG_PAD5_MODE 0x008 -#define AR8327_REG_PAD6_MODE 0x00c -#define AR8327_PAD_MAC_MII_RXCLK_SEL BIT(0) -#define AR8327_PAD_MAC_MII_TXCLK_SEL BIT(1) -#define AR8327_PAD_MAC_MII_EN BIT(2) -#define AR8327_PAD_MAC_GMII_RXCLK_SEL BIT(4) -#define AR8327_PAD_MAC_GMII_TXCLK_SEL BIT(5) -#define AR8327_PAD_MAC_GMII_EN BIT(6) -#define AR8327_PAD_SGMII_EN BIT(7) -#define AR8327_PAD_PHY_MII_RXCLK_SEL BIT(8) -#define AR8327_PAD_PHY_MII_TXCLK_SEL BIT(9) -#define AR8327_PAD_PHY_MII_EN BIT(10) -#define AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL BIT(11) -#define AR8327_PAD_PHY_GMII_RXCLK_SEL BIT(12) -#define AR8327_PAD_PHY_GMII_TXCLK_SEL BIT(13) -#define AR8327_PAD_PHY_GMII_EN BIT(14) -#define AR8327_PAD_PHYX_GMII_EN BIT(16) -#define AR8327_PAD_PHYX_RGMII_EN BIT(17) -#define AR8327_PAD_PHYX_MII_EN BIT(18) -#define AR8327_PAD_SGMII_DELAY_EN BIT(19) -#define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2) -#define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20 -#define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2) -#define AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S 22 -#define AR8327_PAD_RGMII_RXCLK_DELAY_EN BIT(24) -#define AR8327_PAD_RGMII_TXCLK_DELAY_EN BIT(25) -#define AR8327_PAD_RGMII_EN BIT(26) - -#define AR8327_REG_POWER_ON_STRIP 0x010 -#define AR8327_POWER_ON_STRIP_POWER_ON_SEL BIT(31) -#define AR8327_POWER_ON_STRIP_LED_OPEN_EN BIT(24) -#define AR8327_POWER_ON_STRIP_SERDES_AEN BIT(7) - -#define AR8327_REG_INT_STATUS0 0x020 -#define AR8327_INT0_VT_DONE BIT(20) - -#define AR8327_REG_INT_STATUS1 0x024 -#define AR8327_REG_INT_MASK0 0x028 -#define AR8327_REG_INT_MASK1 0x02c - -#define AR8327_REG_MODULE_EN 0x030 -#define AR8327_MODULE_EN_MIB BIT(0) - -#define AR8327_REG_MIB_FUNC 0x034 -#define AR8327_MIB_CPU_KEEP BIT(20) - -#define AR8327_REG_SERVICE_TAG 0x048 -#define AR8327_REG_LED_CTRL(_i) (0x050 + (_i) * 4) -#define AR8327_REG_LED_CTRL0 0x050 -#define AR8327_REG_LED_CTRL1 0x054 -#define AR8327_REG_LED_CTRL2 0x058 -#define AR8327_REG_LED_CTRL3 0x05c -#define AR8327_REG_MAC_ADDR0 0x060 -#define AR8327_REG_MAC_ADDR1 0x064 - -#define AR8327_REG_MAX_FRAME_SIZE 0x078 -#define AR8327_MAX_FRAME_SIZE_MTU BITS(0, 14) - -#define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) - -#define AR8327_REG_HEADER_CTRL 0x098 -#define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4) - -#define AR8327_REG_SGMII_CTRL 0x0e0 -#define AR8327_SGMII_CTRL_EN_PLL BIT(1) -#define AR8327_SGMII_CTRL_EN_RX BIT(2) -#define AR8327_SGMII_CTRL_EN_TX BIT(3) - -#define AR8327_REG_EEE_CTRL 0x100 -#define AR8327_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2) - -#define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8) -#define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12) -#define AR8327_PORT_VLAN0_DEF_SVID_S 0 -#define AR8327_PORT_VLAN0_DEF_CVID BITS(16, 12) -#define AR8327_PORT_VLAN0_DEF_CVID_S 16 - -#define AR8327_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8) -#define AR8327_PORT_VLAN1_PORT_VLAN_PROP BIT(6) -#define AR8327_PORT_VLAN1_OUT_MODE BITS(12, 2) -#define AR8327_PORT_VLAN1_OUT_MODE_S 12 -#define AR8327_PORT_VLAN1_OUT_MODE_UNMOD 0 -#define AR8327_PORT_VLAN1_OUT_MODE_UNTAG 1 -#define AR8327_PORT_VLAN1_OUT_MODE_TAG 2 -#define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3 - -#define AR8327_REG_ATU_DATA0 0x600 -#define AR8327_REG_ATU_DATA1 0x604 -#define AR8327_REG_ATU_DATA2 0x608 - -#define AR8327_REG_ATU_FUNC 0x60c -#define AR8327_ATU_FUNC_OP BITS(0, 4) -#define AR8327_ATU_FUNC_OP_NOOP 0x0 -#define AR8327_ATU_FUNC_OP_FLUSH 0x1 -#define AR8327_ATU_FUNC_OP_LOAD 0x2 -#define AR8327_ATU_FUNC_OP_PURGE 0x3 -#define AR8327_ATU_FUNC_OP_FLUSH_LOCKED 0x4 -#define AR8327_ATU_FUNC_OP_FLUSH_UNICAST 0x5 -#define AR8327_ATU_FUNC_OP_GET_NEXT 0x6 -#define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7 -#define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8 -#define AR8327_ATU_FUNC_BUSY BIT(31) - -#define AR8327_REG_VTU_FUNC0 0x0610 -#define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14) -#define AR8327_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) -#define AR8327_VTU_FUNC0_EG_MODE_KEEP 0 -#define AR8327_VTU_FUNC0_EG_MODE_UNTAG 1 -#define AR8327_VTU_FUNC0_EG_MODE_TAG 2 -#define AR8327_VTU_FUNC0_EG_MODE_NOT 3 -#define AR8327_VTU_FUNC0_IVL BIT(19) -#define AR8327_VTU_FUNC0_VALID BIT(20) - -#define AR8327_REG_VTU_FUNC1 0x0614 -#define AR8327_VTU_FUNC1_OP BITS(0, 3) -#define AR8327_VTU_FUNC1_OP_NOOP 0 -#define AR8327_VTU_FUNC1_OP_FLUSH 1 -#define AR8327_VTU_FUNC1_OP_LOAD 2 -#define AR8327_VTU_FUNC1_OP_PURGE 3 -#define AR8327_VTU_FUNC1_OP_REMOVE_PORT 4 -#define AR8327_VTU_FUNC1_OP_GET_NEXT 5 -#define AR8327_VTU_FUNC1_OP_GET_ONE 6 -#define AR8327_VTU_FUNC1_FULL BIT(4) -#define AR8327_VTU_FUNC1_PORT BIT(8, 4) -#define AR8327_VTU_FUNC1_PORT_S 8 -#define AR8327_VTU_FUNC1_VID BIT(16, 12) -#define AR8327_VTU_FUNC1_VID_S 16 -#define AR8327_VTU_FUNC1_BUSY BIT(31) - -#define AR8327_REG_FWD_CTRL0 0x620 -#define AR8327_FWD_CTRL0_CPU_PORT_EN BIT(10) -#define AR8327_FWD_CTRL0_MIRROR_PORT BITS(4, 4) -#define AR8327_FWD_CTRL0_MIRROR_PORT_S 4 - -#define AR8327_REG_FWD_CTRL1 0x624 -#define AR8327_FWD_CTRL1_UC_FLOOD BITS(0, 7) -#define AR8327_FWD_CTRL1_UC_FLOOD_S 0 -#define AR8327_FWD_CTRL1_MC_FLOOD BITS(8, 7) -#define AR8327_FWD_CTRL1_MC_FLOOD_S 8 -#define AR8327_FWD_CTRL1_BC_FLOOD BITS(16, 7) -#define AR8327_FWD_CTRL1_BC_FLOOD_S 16 -#define AR8327_FWD_CTRL1_IGMP BITS(24, 7) -#define AR8327_FWD_CTRL1_IGMP_S 24 - -#define AR8327_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc) -#define AR8327_PORT_LOOKUP_MEMBER BITS(0, 7) -#define AR8327_PORT_LOOKUP_IN_MODE BITS(8, 2) -#define AR8327_PORT_LOOKUP_IN_MODE_S 8 -#define AR8327_PORT_LOOKUP_STATE BITS(16, 3) -#define AR8327_PORT_LOOKUP_STATE_S 16 -#define AR8327_PORT_LOOKUP_LEARN BIT(20) -#define AR8327_PORT_LOOKUP_ING_MIRROR_EN BIT(25) - -#define AR8327_REG_PORT_PRIO(_i) (0x664 + (_i) * 0xc) - -#define AR8327_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) -#define AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16) - -#define AR8327_REG_PORT_STATS_BASE(_i) (0x1000 + (_i) * 0x100) - -#define AR8337_PAD_MAC06_EXCHANGE_EN BIT(31) - /* port speed */ enum { AR8216_PORT_SPEED_10M = 0, @@ -492,4 +350,293 @@ enum { AR8216_PORT_STATE_FORWARD = 4 }; +enum { + AR8XXX_VER_AR8216 = 0x01, + AR8XXX_VER_AR8236 = 0x03, + AR8XXX_VER_AR8316 = 0x10, + AR8XXX_VER_AR8327 = 0x12, + AR8XXX_VER_AR8337 = 0x13, +}; + +#define AR8XXX_NUM_ARL_RECORDS 100 + +enum arl_op { + AR8XXX_ARL_INITIALIZE, + AR8XXX_ARL_GET_NEXT +}; + +struct arl_entry { + u8 port; + u8 mac[6]; +}; + +struct ar8xxx_priv; + +struct ar8xxx_mib_desc { + unsigned int size; + unsigned int offset; + const char *name; +}; + +struct ar8xxx_chip { + unsigned long caps; + bool config_at_probe; + bool mii_lo_first; + + /* parameters to calculate REG_PORT_STATS_BASE */ + unsigned reg_port_stats_start; + unsigned reg_port_stats_length; + + unsigned reg_arl_ctrl; + + int (*hw_init)(struct ar8xxx_priv *priv); + void (*cleanup)(struct ar8xxx_priv *priv); + + const char *name; + int vlans; + int ports; + const struct switch_dev_ops *swops; + + void (*init_globals)(struct ar8xxx_priv *priv); + void (*init_port)(struct ar8xxx_priv *priv, int port); + void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members); + u32 (*read_port_status)(struct ar8xxx_priv *priv, int port); + u32 (*read_port_eee_status)(struct ar8xxx_priv *priv, int port); + int (*atu_flush)(struct ar8xxx_priv *priv); + int (*atu_flush_port)(struct ar8xxx_priv *priv, int port); + void (*vtu_flush)(struct ar8xxx_priv *priv); + void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask); + void (*phy_fixup)(struct ar8xxx_priv *priv, int phy); + void (*set_mirror_regs)(struct ar8xxx_priv *priv); + void (*get_arl_entry)(struct ar8xxx_priv *priv, struct arl_entry *a, + u32 *status, enum arl_op op); + int (*sw_hw_apply)(struct switch_dev *dev); + + const struct ar8xxx_mib_desc *mib_decs; + unsigned num_mibs; + unsigned mib_func; +}; + +struct ar8xxx_priv { + struct switch_dev dev; + struct mii_bus *mii_bus; + struct phy_device *phy; + + int (*get_port_link)(unsigned port); + + const struct net_device_ops *ndo_old; + struct net_device_ops ndo; + struct mutex reg_mutex; + u8 chip_ver; + u8 chip_rev; + const struct ar8xxx_chip *chip; + void *chip_data; + bool initialized; + bool port4_phy; + char buf[2048]; + struct arl_entry arl_table[AR8XXX_NUM_ARL_RECORDS]; + char arl_buf[AR8XXX_NUM_ARL_RECORDS * 32 + 256]; + bool link_up[AR8X16_MAX_PORTS]; + + bool init; + + struct mutex mib_lock; + struct delayed_work mib_work; + int mib_next_port; + u64 *mib_stats; + + struct list_head list; + unsigned int use_count; + + /* all fields below are cleared on reset */ + bool vlan; + u16 vlan_id[AR8X16_MAX_VLANS]; + u8 vlan_table[AR8X16_MAX_VLANS]; + u8 vlan_tagged; + u16 pvid[AR8X16_MAX_PORTS]; + int arl_age_time; + + /* mirroring */ + bool mirror_rx; + bool mirror_tx; + int source_port; + int monitor_port; +}; + +u32 +ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum); +void +ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val); +u32 +ar8xxx_read(struct ar8xxx_priv *priv, int reg); +void +ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val); +u32 +ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val); + +void +ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr, + u16 dbg_addr, u16 dbg_data); +void +ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data); +u16 +ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg); +void +ar8xxx_phy_init(struct ar8xxx_priv *priv); +int +ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_reset_mibs(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan); +int +ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan); +int +ar8xxx_sw_hw_apply(struct switch_dev *dev); +int +ar8xxx_sw_reset_switch(struct switch_dev *dev); +int +ar8xxx_sw_get_port_link(struct switch_dev *dev, int port, + struct switch_port_link *link); +int +ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_port_mib(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_arl_table(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val); + +static inline struct ar8xxx_priv * +swdev_to_ar8xxx(struct switch_dev *swdev) +{ + return container_of(swdev, struct ar8xxx_priv, dev); +} + +static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv) +{ + return priv->chip->caps & AR8XXX_CAP_GIGE; +} + +static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv) +{ + return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS; +} + +static inline bool chip_is_ar8216(struct ar8xxx_priv *priv) +{ + return priv->chip_ver == AR8XXX_VER_AR8216; +} + +static inline bool chip_is_ar8236(struct ar8xxx_priv *priv) +{ + return priv->chip_ver == AR8XXX_VER_AR8236; +} + +static inline bool chip_is_ar8316(struct ar8xxx_priv *priv) +{ + return priv->chip_ver == AR8XXX_VER_AR8316; +} + +static inline bool chip_is_ar8327(struct ar8xxx_priv *priv) +{ + return priv->chip_ver == AR8XXX_VER_AR8327; +} + +static inline bool chip_is_ar8337(struct ar8xxx_priv *priv) +{ + return priv->chip_ver == AR8XXX_VER_AR8337; +} + +static inline void +ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val) +{ + ar8xxx_rmw(priv, reg, 0, val); +} + +static inline void +ar8xxx_reg_clear(struct ar8xxx_priv *priv, int reg, u32 val) +{ + ar8xxx_rmw(priv, reg, val, 0); +} + +static inline void +split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page) +{ + regaddr >>= 1; + *r1 = regaddr & 0x1e; + + regaddr >>= 5; + *r2 = regaddr & 0x7; + + regaddr >>= 3; + *page = regaddr & 0x1ff; +} + +static inline void +wait_for_page_switch(void) +{ + udelay(5); +} + #endif