X-Git-Url: http://git.openwrt.org/?p=openwrt%2Fopenwrt.git;a=blobdiff_plain;f=target%2Flinux%2Framips%2Fdts%2FZBT-WG2626.dts;h=469977bb4525dd63a0aa46375b14197906c79dd9;hp=c1124295d3984f66c5a7d281082b2a48875c8cb4;hb=772b27c20736;hpb=02f815d1907cdd7e042415a2b4a749c819087168 diff --git a/target/linux/ramips/dts/ZBT-WG2626.dts b/target/linux/ramips/dts/ZBT-WG2626.dts index c1124295d3..469977bb45 100644 --- a/target/linux/ramips/dts/ZBT-WG2626.dts +++ b/target/linux/ramips/dts/ZBT-WG2626.dts @@ -9,6 +9,10 @@ compatible = "zbtlink,zbt-wg2626", "mediatek,mt7621-soc"; model = "ZBT-WG2626"; + aliases { + led-status = &led_status; + }; + memory@0 { device_type = "memory"; reg = <0x0 0x1c000000>, <0x20000000 0x4000000>; @@ -26,8 +30,6 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <20>; reset { @@ -40,7 +42,7 @@ gpio-leds { compatible = "gpio-leds"; - status { + led_status: status { label = "zbt-wg2626:green:status"; gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; }; @@ -55,53 +57,59 @@ status = "okay"; m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; m25p,chunked-io = <32>; - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; }; }; }; &pcie { status = "okay"; +}; - pcie0 { - mt76@0,0 { - mediatek,mtd-eeprom = <&factory 0x8000>; - ieee80211-freq-limit = <5000000 6000000>; - }; +&pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x8000>; + ieee80211-freq-limit = <5000000 6000000>; }; +}; - pcie1 { - mt76@1,0 { - mediatek,mtd-eeprom = <&factory 0x0000>; - ieee80211-freq-limit = <2400000 2500000>; - }; +&pcie1 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x0000>; + ieee80211-freq-limit = <2400000 2500000>; }; };