X-Git-Url: http://git.openwrt.org/?p=openwrt%2Fopenwrt.git;a=blobdiff_plain;f=target%2Flinux%2Framips%2Fdts%2Fmt7621.dtsi;h=77841a61d297cf2ccb32429d6bc6d4f7994bce86;hp=772f0aabfab9677c21acae7ab5999de6ad7f5085;hb=0599cd90e185860bbddd7dea8899f29b82368050;hpb=011ce1fad6d7048a3fa9015ce8b8f8c64cb2f022 diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi index 772f0aabfa..77841a61d2 100644 --- a/target/linux/ramips/dts/mt7621.dtsi +++ b/target/linux/ramips/dts/mt7621.dtsi @@ -1,21 +1,29 @@ #include +#include / { #address-cells = <1>; #size-cells = <1>; - compatible = "mediatek,mtk7621-soc"; + compatible = "mediatek,mt7621-soc"; cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; compatible = "mips,mips1004Kc"; + reg = <0>; }; cpu@1 { + device_type = "cpu"; compatible = "mips,mips1004Kc"; + reg = <1>; }; }; - cpuintc: cpuintc@0 { + cpuintc: cpuintc { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; @@ -26,15 +34,14 @@ serial0 = &uartlite; }; - cpuclock: cpuclock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; + pll: pll { + compatible = "mediatek,mt7621-pll", "syscon"; - /* FIXME: there should be way to detect this */ - clock-frequency = <880000000>; + #clock-cells = <1>; + clock-output-names = "cpu", "bus"; }; - sysclock: sysclock@0 { + sysclock: sysclock { #clock-cells = <0>; compatible = "fixed-clock"; @@ -42,6 +49,8 @@ clock-frequency = <50000000>; }; + + palmbus: palmbus@1E000000 { compatible = "palmbus"; reg = <0x1E000000 0x100000>; @@ -56,7 +65,7 @@ }; wdt: wdt@100 { - compatible = "mtk,mt7621-wdt"; + compatible = "mediatek,mt7621-wdt"; reg = <0x100 0x100>; }; @@ -107,26 +116,58 @@ pinctrl-0 = <&i2c_pins>; }; + i2s: i2s@a00 { + compatible = "mediatek,mt7621-i2s"; + reg = <0xa00 0x100>; + + clocks = <&sysclock>; + + resets = <&rstctrl 17>; + reset-names = "i2s"; + + interrupt-parent = <&gic>; + interrupts = ; + + txdma-req = <2>; + rxdma-req = <3>; + + dmas = <&gdma 4>, + <&gdma 6>; + dma-names = "tx", "rx"; + + status = "disabled"; + }; + + systick: systick@500 { + compatible = "ralink,mt7621-systick", "ralink,cevt-systick"; + reg = <0x500 0x10>; + + resets = <&rstctrl 28>; + reset-names = "intc"; + + interrupt-parent = <&gic>; + interrupts = ; + }; + memc: memc@5000 { compatible = "mtk,mt7621-memc"; - reg = <0x300 0x100>; + reg = <0x5000 0x1000>; }; cpc: cpc@1fbf0000 { - compatible = "mtk,mt7621-cpc"; - reg = <0x1fbf0000 0x8000>; + compatible = "mtk,mt7621-cpc"; + reg = <0x1fbf0000 0x8000>; }; mc: mc@1fbf8000 { - compatible = "mtk,mt7621-mc"; - reg = <0x1fbf8000 0x8000>; - }; + compatible = "mtk,mt7621-mc"; + reg = <0x1fbf8000 0x8000>; + }; uartlite: uartlite@c00 { compatible = "ns16550a"; reg = <0xc00 0x100>; - clocks = <&sysclock>; clock-frequency = <50000000>; interrupt-parent = <&gic>; @@ -137,13 +178,49 @@ no-loopback-test; }; + uartlite2: uartlite2@d00 { + compatible = "ns16550a"; + reg = <0xd00 0x100>; + + clock-frequency = <50000000>; + + interrupt-parent = <&gic>; + interrupts = ; + + reg-shift = <2>; + reg-io-width = <4>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + status = "disabled"; + }; + + uartlite3: uartlite3@e00 { + compatible = "ns16550a"; + reg = <0xe00 0x100>; + + clock-frequency = <50000000>; + + interrupt-parent = <&gic>; + interrupts = ; + + reg-shift = <2>; + reg-io-width = <4>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + + status = "disabled"; + }; + spi0: spi@b00 { - status = "okay"; + status = "disabled"; compatible = "ralink,mt7621-spi"; reg = <0xb00 0x100>; - clocks = <&sysclock>; + clocks = <&pll MT7621_CLK_BUS>; resets = <&rstctrl 18>; reset-names = "spi"; @@ -153,14 +230,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_pins>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <10000000>; - m25p,chunked-io = <32>; - }; }; gdma: gdma@2800 { @@ -206,15 +275,15 @@ state_default: pinctrl0 { }; - i2c_pins: i2c { - i2c { + i2c_pins: i2c_pins { + i2c_pins { ralink,group = "i2c"; ralink,function = "i2c"; }; }; - spi_pins: spi { - spi { + spi_pins: spi_pins { + spi_pins { ralink,group = "spi"; ralink,function = "spi"; }; @@ -300,25 +369,52 @@ }; sdhci: sdhci@1E130000 { + status = "disabled"; + compatible = "ralink,mt7620-sdhci"; reg = <0x1E130000 0x4000>; interrupt-parent = <&gic>; interrupts = ; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; }; xhci: xhci@1E1C0000 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; compatible = "mediatek,mt8173-xhci"; reg = <0x1e1c0000 0x1000 0x1e1d0700 0x0100>; + reg-names = "mac", "ippc"; clocks = <&sysclock>; clock-names = "sys_ck"; interrupt-parent = <&gic>; interrupts = ; + + /* + * Port 1 of both hubs is one usb slot and referenced here. + * The binding doesn't allow to address individual hubs. + * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci. + */ + xhci_ehci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + /* + * Only the second usb hub has a second port. That port serves + * ehci and ohci. + */ + ehci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; }; gic: interrupt-controller@1fbc0000 { @@ -333,7 +429,7 @@ timer { compatible = "mti,gic-timer"; interrupts = ; - clocks = <&cpuclock>; + clocks = <&pll MT7621_CLK_CPU>; }; }; @@ -344,8 +440,6 @@ bank-width = <2>; reg = <0x1e003000 0x800 0x1e003800 0x800>; - #address-cells = <1>; - #size-cells = <1>; }; ethernet: ethernet@1e100000 { @@ -353,7 +447,7 @@ reg = <0x1e100000 0x10000>; #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; resets = <&rstctrl 6 &rstctrl 23>; reset-names = "fe", "eth"; @@ -372,6 +466,16 @@ phy-mode = "rgmii"; }; }; + + hnat: hnat@0 { + compatible = "mediatek,mt7623-hnat"; + reg = <0 0x10000>; + mtketh-ppd = "eth0"; + mtketh-lan = "eth0"; + mtketh-wan = "eth0"; + resets = <&rstctrl 0>; + reset-names = "mtketh"; + }; }; gsw: gsw@1e110000 { @@ -405,38 +509,38 @@ GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; + status = "disabled"; resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; reset-names = "pcie0", "pcie1", "pcie2"; clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; clock-names = "pcie0", "pcie1", "pcie2"; - pcie0 { + pcie0: pcie@0,0 { reg = <0x0000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; - device_type = "pci"; + ranges; }; - pcie1 { + pcie1: pcie@1,0 { reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; - device_type = "pci"; + ranges; }; - pcie2 { + pcie2: pcie@2,0 { reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; - device_type = "pci"; + ranges; }; }; };