X-Git-Url: http://git.openwrt.org/?p=openwrt%2Fopenwrt.git;a=blobdiff_plain;f=target%2Flinux%2Framips%2Ffiles%2Fdrivers%2Fnet%2Framips_esw.c;h=df567a7216467e6f8db21cd272c378b0642319ef;hp=f82d662ac3fe173b067700d9d5ec200000112b8b;hb=b99a637795efbb7aba2c5d4d77295c7012613759;hpb=7b878dde4b4610a7cb2460df600a76717e7544a1 diff --git a/target/linux/ramips/files/drivers/net/ramips_esw.c b/target/linux/ramips/files/drivers/net/ramips_esw.c index f82d662ac3..df567a7216 100644 --- a/target/linux/ramips/files/drivers/net/ramips_esw.c +++ b/target/linux/ramips/files/drivers/net/ramips_esw.c @@ -5,7 +5,7 @@ #define RT305X_ESW_REG_FCT0 0x08 #define RT305X_ESW_REG_PFC1 0x14 -#define RT305X_ESW_REG_PVIDC(_n) (0x48 + 4 * (_n)) +#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n)) #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n)) #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n)) #define RT305X_ESW_REG_FPA 0x84 @@ -28,9 +28,54 @@ #define RT305X_ESW_PHY_TIMEOUT (5 * HZ) +#define RT305X_ESW_PVIDC_PVID_M 0xfff +#define RT305X_ESW_PVIDC_PVID_S 12 + +#define RT305X_ESW_VLANI_VID_M 0xfff +#define RT305X_ESW_VLANI_VID_S 12 + +#define RT305X_ESW_VMSC_MSC_M 0xff +#define RT305X_ESW_VMSC_MSC_S 8 + +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25) + +#define RT305X_ESW_POC1_EN_BP_S 0 +#define RT305X_ESW_POC1_EN_FC_S 8 +#define RT305X_ESW_POC1_DIS_RMC2CPU_S 16 +#define RT305X_ESW_POC1_DIS_PORT_S 23 + +#define RT305X_ESW_POC3_UNTAG_EN_S 0 +#define RT305X_ESW_POC3_ENAGING_S 8 +#define RT305X_ESW_POC3_DIS_UC_PAUSE_S 16 + +#define RT305X_ESW_PORT0 0 +#define RT305X_ESW_PORT1 1 +#define RT305X_ESW_PORT2 2 +#define RT305X_ESW_PORT3 3 +#define RT305X_ESW_PORT4 4 +#define RT305X_ESW_PORT5 5 +#define RT305X_ESW_PORT6 6 + +#define RT305X_ESW_PORTS_INTERNAL \ + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \ + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \ + BIT(RT305X_ESW_PORT4)) + +#define RT305X_ESW_PORTS_NOCPU \ + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5)) + +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6) + +#define RT305X_ESW_PORTS_ALL \ + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU) + struct rt305x_esw { void __iomem *base; struct rt305x_esw_platform_data *pdata; + spinlock_t reg_rw_lock; }; static inline void @@ -45,6 +90,27 @@ rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg) return __raw_readl(esw->base + reg); } +static inline void +rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask, + unsigned long val) +{ + unsigned long t; + + t = __raw_readl(esw->base + reg) & ~mask; + __raw_writel(t | val, esw->base + reg); +} + +static void +rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask, + unsigned long val) +{ + unsigned long flags; + + spin_lock_irqsave(&esw->reg_rw_lock, flags); + rt305x_esw_rmw_raw(esw, reg, mask, val); + spin_unlock_irqrestore(&esw->reg_rw_lock, flags); +} + static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register, u32 write_data) @@ -86,6 +152,42 @@ out: return ret; } +static void +rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid) +{ + unsigned s; + + s = RT305X_ESW_VLANI_VID_S * (vlan % 2); + rt305x_esw_rmw(esw, + RT305X_ESW_REG_VLANI(vlan / 2), + RT305X_ESW_VLANI_VID_M << s, + (vid & RT305X_ESW_VLANI_VID_M) << s); +} + +static void +rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid) +{ + unsigned s; + + s = RT305X_ESW_PVIDC_PVID_S * (port % 2); + rt305x_esw_rmw(esw, + RT305X_ESW_REG_PVIDC(port / 2), + RT305X_ESW_PVIDC_PVID_M << s, + (pvid & RT305X_ESW_PVIDC_PVID_M) << s); +} + +static void +rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc) +{ + unsigned s; + + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4); + rt305x_esw_rmw(esw, + RT305X_ESW_REG_VMSC(vlan / 4), + RT305X_ESW_VMSC_MSC_M << s, + (msc & RT305X_ESW_VMSC_MSC_M) << s); +} + static void rt305x_esw_hw_init(struct rt305x_esw *esw) { @@ -95,13 +197,32 @@ rt305x_esw_hw_init(struct rt305x_esw *esw) rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0); rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2); rt305x_esw_wr(esw, 0x00405555, RT305X_ESW_REG_PFC1); - rt305x_esw_wr(esw, 0x00002001, RT305X_ESW_REG_VLANI(0)); - rt305x_esw_wr(esw, 0x00007f7f, RT305X_ESW_REG_POC1); - rt305x_esw_wr(esw, 0x00007f3f, RT305X_ESW_REG_POC3); + + /* Enable Back Pressure, and Flow Control */ + rt305x_esw_wr(esw, + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_BP_S) | + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_FC_S)), + RT305X_ESW_REG_POC1); + + /* Enable Aging, and VLAN TAG removal */ + rt305x_esw_wr(esw, + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC3_ENAGING_S) | + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC3_UNTAG_EN_S)), + RT305X_ESW_REG_POC3); + rt305x_esw_wr(esw, 0x00d6500c, RT305X_ESW_REG_FCT2); rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC); - rt305x_esw_wr(esw, 0x02404040, RT305X_ESW_REG_SOCPC); - rt305x_esw_wr(esw, 0x00001002, RT305X_ESW_REG_PVIDC(2)); + + /* Setup SoC Port control register */ + rt305x_esw_wr(esw, + (RT305X_ESW_SOCPC_CRC_PADDING | + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) | + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) | + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)), + RT305X_ESW_REG_SOCPC); + + rt305x_esw_set_pvid(esw, RT305X_ESW_PORT4, 2); + rt305x_esw_set_pvid(esw, RT305X_ESW_PORT5, 1); rt305x_esw_wr(esw, 0x3f502b28, RT305X_ESW_REG_FPA2); rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA); @@ -132,8 +253,16 @@ rt305x_esw_hw_init(struct rt305x_esw *esw) rt305x_mii_write(esw, 0, 31, 0x8000); /* set default vlan */ - rt305x_esw_wr(esw, 0x2001, RT305X_ESW_REG_VLANI(0)); - rt305x_esw_wr(esw, 0x504f, RT305X_ESW_REG_VMSC(0)); + rt305x_esw_set_vlan_id(esw, 0, 1); + rt305x_esw_set_vlan_id(esw, 1, 2); + rt305x_esw_set_vmsc(esw, 0, + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | + BIT(RT305X_ESW_PORT6))); + rt305x_esw_set_vmsc(esw, 1, + (BIT(RT305X_ESW_PORT4) | BIT(RT305X_ESW_PORT6))); + rt305x_esw_set_vmsc(esw, 2, 0); + rt305x_esw_set_vmsc(esw, 3, 0); } static int @@ -170,6 +299,7 @@ rt305x_esw_probe(struct platform_device *pdev) platform_set_drvdata(pdev, esw); esw->pdata = pdata; + spin_lock_init(&esw->reg_rw_lock); rt305x_esw_hw_init(esw); return 0;