+@@ -375,41 +427,6 @@ static int bcm5481_config_aneg(struct ph
+ return ret;
+ }
+
+-static int bcm54612e_config_aneg(struct phy_device *phydev)
+-{
+- int ret;
+-
+- /* First, auto-negotiate. */
+- ret = genphy_config_aneg(phydev);
+-
+- /* Clear TX internal delay unless requested. */
+- if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
+- (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
+- /* Disable TXD to GTXCLK clock delay (default set) */
+- /* Bit 9 is the only field in shadow register 00011 */
+- bcm_phy_write_shadow(phydev, 0x03, 0);
+- }
+-
+- /* Clear RX internal delay unless requested. */
+- if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
+- (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
+- u16 reg;
+-
+- /* Errata: reads require filling in the write selector field */
+- bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
+- MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
+- reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
+- /* Disable RXD to RXC delay (default set) */
+- reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
+- /* Clear shadow selector field */
+- reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
+- bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
+- MII_BCM54XX_AUXCTL_MISC_WREN | reg);
+- }
+-
+- return ret;
+-}
+-
+ static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
+ {
+ int val;
+@@ -548,6 +565,19 @@ static struct phy_driver broadcom_driver