ath79: ag71xx: apply interface mode to MII0/1_CTRL on ar71xx/ar913x
authorChuanhong Guo <gch981213@gmail.com>
Tue, 21 Aug 2018 11:39:16 +0000 (19:39 +0800)
committerJohn Crispin <john@phrozen.org>
Tue, 28 Aug 2018 09:26:53 +0000 (11:26 +0200)
We currently don't have any code configuring interface mode in ath79,
meaning that we relies on bootloader to set the correct interface mode.

This patch added code to set interface correctly so that everything works
even if bootloader configures it wrong.(e.g. on WNDR3800 u-boot set
the second GMAC mode to RMII but it should be RGMII.)

Introduced "qca,mac-idx" for the difference in MII_CTRL register value.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
target/linux/ath79/dts/ar7100.dtsi
target/linux/ath79/dts/ar9132.dtsi
target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c

index 8994a7d..6402657 100644 (file)
 
        resets = <&rst 9>;
        reset-names = "mac";
+       qca,mac-idx = <0>;
 };
 
 &mdio1 {
 
        resets = <&rst 13>;
        reset-names = "mac";
+       qca,mac-idx = <1>;
 };
index 9d8ddcf..2264994 100644 (file)
        pll-handle = <&pll>;
        resets = <&rst 9>;
        reset-names = "mac";
+       qca,mac-idx = <0>;
 };
index 377b9f8..9aac199 100644 (file)
@@ -154,6 +154,8 @@ struct ag71xx {
        struct ag71xx_ring      rx_ring ____cacheline_aligned;
        struct ag71xx_ring      tx_ring ____cacheline_aligned;
 
+       int                     mac_idx;
+
        u16                     desc_pktlen_mask;
        u16                     rx_buf_size;
        u8                      rx_buf_offset;
index 1e0bb69..d029197 100644 (file)
@@ -529,6 +529,60 @@ static void ath79_set_pll(struct ag71xx *ag)
        udelay(100);
 }
 
+static void ath79_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)
+{
+       u32 t;
+
+       t = __raw_readl(ag->mii_base);
+       t &= ~(AR71XX_MII_CTRL_IF_MASK);
+       t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
+       __raw_writel(t, ag->mii_base);
+}
+
+static void ath79_mii0_ctrl_set_if(struct ag71xx *ag)
+{
+       unsigned int mii_if;
+
+       switch (ag->phy_if_mode) {
+       case PHY_INTERFACE_MODE_MII:
+               mii_if = AR71XX_MII0_CTRL_IF_MII;
+               break;
+       case PHY_INTERFACE_MODE_GMII:
+               mii_if = AR71XX_MII0_CTRL_IF_GMII;
+               break;
+       case PHY_INTERFACE_MODE_RGMII:
+               mii_if = AR71XX_MII0_CTRL_IF_RGMII;
+               break;
+       case PHY_INTERFACE_MODE_RMII:
+               mii_if = AR71XX_MII0_CTRL_IF_RMII;
+               break;
+       default:
+               WARN(1, "Impossible PHY mode defined.\n");
+               return;
+       }
+
+       ath79_mii_ctrl_set_if(ag, mii_if);
+}
+
+static void ath79_mii1_ctrl_set_if(struct ag71xx *ag)
+{
+       unsigned int mii_if;
+
+       switch (ag->phy_if_mode) {
+       case PHY_INTERFACE_MODE_RMII:
+               mii_if = AR71XX_MII1_CTRL_IF_RMII;
+               break;
+       case PHY_INTERFACE_MODE_RGMII:
+               mii_if = AR71XX_MII1_CTRL_IF_RGMII;
+               break;
+       default:
+               WARN(1, "Impossible PHY mode defined.\n");
+               return;
+       }
+
+       ath79_mii_ctrl_set_if(ag, mii_if);
+}
+
 static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
 {
        unsigned int mii_speed;
@@ -1427,6 +1481,20 @@ static int ag71xx_probe(struct platform_device *pdev)
                goto err_free;
        }
 
+       if (of_property_read_u32(np, "qca,mac-idx", &ag->mac_idx))
+               ag->mac_idx = -1;
+       if (ag->mii_base)
+               switch (ag->mac_idx) {
+               case 0:
+                       ath79_mii0_ctrl_set_if(ag);
+                       break;
+               case 1:
+                       ath79_mii1_ctrl_set_if(ag);
+                       break;
+               default:
+                       break;
+               }
+
        netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
 
        ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);