CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ATH79 is not set
CONFIG_AUDIT=y
CONFIG_AUDIT_GENERIC=y
CONFIG_BCM63XX=y
+# CONFIG_BCM63XX_CPU_6328 is not set
CONFIG_BCM63XX_CPU_6338=y
CONFIG_BCM63XX_CPU_6345=y
CONFIG_BCM63XX_CPU_6348=y
CONFIG_IRQ_CPU=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_KEXEC=y
-# CONFIG_LANTIQ is not set
CONFIG_LEDS_GPIO=y
+CONFIG_MDIO_BOARDINFO=y
CONFIG_MIPS=y
CONFIG_MIPS_L1_CACHE_SHIFT=5
# CONFIG_MIPS_MACHINE is not set
CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_PCI=y
+# CONFIG_PCIEPORTBUS is not set
CONFIG_PCI_DOMAINS=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PHYLIB=y
--- /dev/null
+From a3f65b46e32acd29c613b35fab588e4d28e5d432 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Sun, 3 Jul 2011 13:11:19 +0200
+Subject: [PATCH 48/79] MIPS: expose PCIe drivers for MIPS
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/Kconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -2392,6 +2392,8 @@ config PCI_DOMAINS
+
+ source "drivers/pci/Kconfig"
+
++source "drivers/pci/pcie/Kconfig"
++
+ #
+ # ISA support is now enabled via select. Too many systems still have the one
+ # or other ISA chip on the board that users don't know about so don't expect
--- /dev/null
+From d831de57b1995eff51f43310b4bbfa85b1a3df42 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Fri, 30 Dec 2011 02:37:47 +0100
+Subject: [PATCH 38/79] MIPS: BCM63XX: use the Chip ID register for
+ identifying the SoC
+
+Newer BCM63XX SoCs use virtually the same cpu ID. But since they all have
+the Chip ID register at the same location, we can use that to identify
+the SoC we are running on.
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/bcm63xx/cpu.c | 20 ++++++++++++--------
+ 1 file changed, 12 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -228,17 +228,21 @@ void __init bcm63xx_cpu_init(void)
+ bcm63xx_irqs = bcm6345_irqs;
+ break;
+ case CPU_BMIPS4350:
+- switch (read_c0_prid() & 0xf0) {
+- case 0x10:
++ if ((read_c0_prid() & 0xf0) == 0x10) {
+ expected_cpu_id = BCM6358_CPU_ID;
+ bcm63xx_regs_base = bcm6358_regs_base;
+ bcm63xx_irqs = bcm6358_irqs;
+- break;
+- case 0x30:
+- expected_cpu_id = BCM6368_CPU_ID;
+- bcm63xx_regs_base = bcm6368_regs_base;
+- bcm63xx_irqs = bcm6368_irqs;
+- break;
++ } else {
++ /* all newer chips have the same chip id location */
++ u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
++
++ switch (chip_id) {
++ case BCM6368_CPU_ID:
++ expected_cpu_id = BCM6368_CPU_ID;
++ bcm63xx_regs_base = bcm6368_regs_base;
++ bcm63xx_irqs = bcm6368_irqs;
++ break;
++ }
+ }
+ break;
+ }
--- /dev/null
+From 48d3ed67982d2d1cecb5b33bf396d21f6fd7b088 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Tue, 14 Jun 2011 21:14:39 +0200
+Subject: [PATCH 39/79] MIPS: BCM63XX: add MISC register set definition
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 10 +++++++++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 2 ++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 10 ++++++++++
+ 3 files changed, 21 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -129,7 +129,8 @@ enum bcm63xx_regs_set {
+ RSET_PCMDMA,
+ RSET_PCMDMAC,
+ RSET_PCMDMAS,
+- RSET_TRNG
++ RSET_TRNG,
++ RSET_MISC
+ };
+
+ #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
+@@ -198,6 +199,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
+ #define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
+ #define BCM_6338_TRNG_BASE (0xdeadbeef)
++#define BCM_6338_MISC_BASE (0xdeadbeef)
+
+ /*
+ * 6345 register sets base address
+@@ -242,6 +244,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
+ #define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
+ #define BCM_6345_TRNG_BASE (0xdeadbeef)
++#define BCM_6345_MISC_BASE (0xdeadbeef)
+
+ /*
+ * 6348 register sets base address
+@@ -283,6 +286,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
+ #define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
+ #define BCM_6348_TRNG_BASE (0xdeadbeef)
++#define BCM_6348_MISC_BASE (0xdeadbeef)
+
+ /*
+ * 6358 register sets base address
+@@ -324,6 +328,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6358_PCMDMAC_BASE (0xfffe1900)
+ #define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
+ #define BCM_6358_TRNG_BASE (0xdeadbeef)
++#define BCM_6358_MISC_BASE (0xdeadbeef)
+
+
+ /*
+@@ -366,6 +371,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6368_PCMDMAC_BASE (0xb0005a00)
+ #define BCM_6368_PCMDMAS_BASE (0xb0005c00)
+ #define BCM_6368_TRNG_BASE (0xb0004180)
++#define BCM_6368_MISC_BASE (0xdeadbeef)
+
+
+ extern const unsigned long *bcm63xx_regs_base;
+@@ -412,6 +418,7 @@ extern const unsigned long *bcm63xx_regs
+ __GEN_RSET_BASE(__cpu, PCMDMAC) \
+ __GEN_RSET_BASE(__cpu, PCMDMAS) \
+ __GEN_RSET_BASE(__cpu, TRNG) \
++ __GEN_RSET_BASE(__cpu, MISC) \
+ }
+
+ #define __GEN_CPU_REGS_TABLE(__cpu) \
+@@ -451,6 +458,7 @@ extern const unsigned long *bcm63xx_regs
+ [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
+ [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
+ [RSET_TRNG] = BCM_## __cpu ##_TRNG_BASE, \
++ [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
+
+
+ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+@@ -91,5 +91,7 @@
+ #define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o))
+ #define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o))
+ #define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
++#define bcm_misc_readl(o) bcm_rset_readl(RSET_MISC, (o))
++#define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o))
+
+ #endif /* ! BCM63XX_IO_H_ */
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -1116,4 +1116,14 @@
+ #define TRNG_THRES 0x0c
+ #define TRNG_MASK 0x10
+
++/*************************************************************************
++ * _REG relative to RSET_MISC
++ *************************************************************************/
++
++#define MISC_STRAPBUS_6328_REG 0x240
++#define STRAPBUS_6328_FCVO_SHIFT 7
++#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
++#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
++#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
++
+ #endif /* BCM63XX_REGS_H_ */
--- /dev/null
+From e7fd2a00f5d6c5e50976ed931c26fdbfbbacf835 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Tue, 14 Jun 2011 21:14:39 +0200
+Subject: [PATCH 40/79] MIPS: BCM63XX: add basic BCM6328 CPU support
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/bcm63xx/Kconfig | 4 +
+ arch/mips/bcm63xx/boards/board_bcm963xx.c | 11 ++-
+ arch/mips/bcm63xx/cpu.c | 43 +++++++++
+ arch/mips/bcm63xx/dev-spi.c | 2 +-
+ arch/mips/bcm63xx/irq.c | 21 +++++
+ arch/mips/bcm63xx/prom.c | 4 +-
+ arch/mips/bcm63xx/setup.c | 13 ++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 101 +++++++++++++++++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 +
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 44 +++++++++
+ arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 +
+ 11 files changed, 238 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -1,6 +1,10 @@
+ menu "CPU support"
+ depends on BCM63XX
+
++config BCM63XX_CPU_6328
++ bool "support 6328 CPU"
++ select HW_HAS_PCI
++
+ config BCM63XX_CPU_6338
+ bool "support 6338 CPU"
+ select HW_HAS_PCI
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -760,9 +760,14 @@ void __init board_prom_init(void)
+ char cfe_version[32];
+ u32 val;
+
+- /* read base address of boot chip select (0) */
+- val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+- val &= MPI_CSBASE_BASE_MASK;
++ /* read base address of boot chip select (0)
++ * 6328 does not have MPI but boots from a fixed address */
++ if (BCMCPU_IS_6328())
++ val = 0x18000000;
++ else {
++ val = bcm_mpi_readl(MPI_CSBASE_REG(0));
++ val &= MPI_CSBASE_BASE_MASK;
++ }
+ boot_addr = (u8 *)KSEG1ADDR(val);
+
+ /* dump cfe version */
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -29,6 +29,14 @@ static u16 bcm63xx_cpu_rev;
+ static unsigned int bcm63xx_cpu_freq;
+ static unsigned int bcm63xx_memory_size;
+
++static const unsigned long bcm6328_regs_base[] = {
++ __GEN_CPU_REGS_TABLE(6328)
++};
++
++static const int bcm6328_irqs[] = {
++ __GEN_CPU_IRQ_TABLE(6328)
++};
++
+ static const unsigned long bcm6338_regs_base[] = {
+ __GEN_CPU_REGS_TABLE(6338)
+ };
+@@ -99,6 +107,33 @@ unsigned int bcm63xx_get_memory_size(voi
+ static unsigned int detect_cpu_clock(void)
+ {
+ switch (bcm63xx_get_cpu_id()) {
++ case BCM6328_CPU_ID:
++ {
++ unsigned int tmp, mips_pll_fcvo;
++
++ tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
++ mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK)
++ >> STRAPBUS_6328_FCVO_SHIFT;
++
++ switch (mips_pll_fcvo) {
++ case 0x12:
++ case 0x14:
++ case 0x19:
++ return 160000000;
++ case 0x1c:
++ return 192000000;
++ case 0x13:
++ case 0x15:
++ return 200000000;
++ case 0x1a:
++ return 384000000;
++ case 0x16:
++ return 400000000;
++ default:
++ return 320000000;
++ }
++
++ }
+ case BCM6338_CPU_ID:
+ /* BCM6338 has a fixed 240 Mhz frequency */
+ return 240000000;
+@@ -170,6 +205,9 @@ static unsigned int detect_memory_size(v
+ unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
+ u32 val;
+
++ if (BCMCPU_IS_6328())
++ return bcm_ddr_readl(DDR_CSEND_REG) << 24;
++
+ if (BCMCPU_IS_6345()) {
+ val = bcm_sdram_readl(SDRAM_MBASE_REG);
+ return (val * 8 * 1024 * 1024);
+@@ -237,6 +275,11 @@ void __init bcm63xx_cpu_init(void)
+ u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
+
+ switch (chip_id) {
++ case BCM6328_CPU_ID:
++ expected_cpu_id = BCM6328_CPU_ID;
++ bcm63xx_regs_base = bcm6328_regs_base;
++ bcm63xx_irqs = bcm6328_irqs;
++ break;
+ case BCM6368_CPU_ID:
+ expected_cpu_id = BCM6368_CPU_ID;
+ bcm63xx_regs_base = bcm6368_regs_base;
+--- a/arch/mips/bcm63xx/dev-spi.c
++++ b/arch/mips/bcm63xx/dev-spi.c
+@@ -87,7 +87,7 @@ int __init bcm63xx_spi_register(void)
+ {
+ struct clk *periph_clk;
+
+- if (BCMCPU_IS_6345())
++ if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
+ return -ENODEV;
+
+ periph_clk = clk_get(NULL, "periph");
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -27,6 +27,17 @@ static void __internal_irq_unmask_32(uns
+ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
+
+ #ifndef BCMCPU_RUNTIME_DETECT
++#ifdef CONFIG_BCM63XX_CPU_6328
++#define irq_stat_reg PERF_IRQSTAT_6328_REG
++#define irq_mask_reg PERF_IRQMASK_6328_REG
++#define irq_bits 64
++#define is_ext_irq_cascaded 1
++#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
++#define ext_irq_end (BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE)
++#define ext_irq_count 4
++#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6328
++#define ext_irq_cfg_reg2 0
++#endif
+ #ifdef CONFIG_BCM63XX_CPU_6338
+ #define irq_stat_reg PERF_IRQSTAT_6338_REG
+ #define irq_mask_reg PERF_IRQMASK_6338_REG
+@@ -118,6 +129,16 @@ static void bcm63xx_init_irq(void)
+ irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
+
+ switch (bcm63xx_get_cpu_id()) {
++ case BCM6328_CPU_ID:
++ irq_stat_addr += PERF_IRQSTAT_6328_REG;
++ irq_mask_addr += PERF_IRQMASK_6328_REG;
++ irq_bits = 64;
++ ext_irq_count = 4;
++ is_ext_irq_cascaded = 1;
++ ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
++ ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
++ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
++ break;
+ case BCM6338_CPU_ID:
+ irq_stat_addr += PERF_IRQSTAT_6338_REG;
+ irq_mask_addr += PERF_IRQMASK_6338_REG;
+--- a/arch/mips/bcm63xx/prom.c
++++ b/arch/mips/bcm63xx/prom.c
+@@ -26,7 +26,9 @@ void __init prom_init(void)
+ bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
+
+ /* disable all hardware blocks clock for now */
+- if (BCMCPU_IS_6338())
++ if (BCMCPU_IS_6328())
++ mask = CKCTL_6328_ALL_SAFE_EN;
++ else if (BCMCPU_IS_6338())
+ mask = CKCTL_6338_ALL_SAFE_EN;
+ else if (BCMCPU_IS_6345())
+ mask = CKCTL_6345_ALL_SAFE_EN;
+--- a/arch/mips/bcm63xx/setup.c
++++ b/arch/mips/bcm63xx/setup.c
+@@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void)
+
+ /* mask and clear all external irq */
+ switch (bcm63xx_get_cpu_id()) {
++ case BCM6328_CPU_ID:
++ perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
++ break;
+ case BCM6338_CPU_ID:
+ perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
+ break;
+@@ -101,9 +104,13 @@ void bcm63xx_machine_reboot(void)
+ bcm6348_a1_reboot();
+
+ printk(KERN_INFO "triggering watchdog soft-reset...\n");
+- reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
+- reg |= SYS_PLL_SOFT_RESET;
+- bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
++ if (BCMCPU_IS_6328()) {
++ bcm_wdt_writel(1, WDT_SOFTRESET_REG);
++ } else {
++ reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
++ reg |= SYS_PLL_SOFT_RESET;
++ bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
++ }
+ while (1)
+ ;
+ }
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -9,6 +9,7 @@
+ * compile time if only one CPU support is enabled (idea stolen from
+ * arm mach-types)
+ */
++#define BCM6328_CPU_ID 0x6328
+ #define BCM6338_CPU_ID 0x6338
+ #define BCM6345_CPU_ID 0x6345
+ #define BCM6348_CPU_ID 0x6348
+@@ -20,6 +21,19 @@ u16 __bcm63xx_get_cpu_id(void);
+ u16 bcm63xx_get_cpu_rev(void);
+ unsigned int bcm63xx_get_cpu_freq(void);
+
++#ifdef CONFIG_BCM63XX_CPU_6328
++# ifdef bcm63xx_get_cpu_id
++# undef bcm63xx_get_cpu_id
++# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
++# define BCMCPU_RUNTIME_DETECT
++# else
++# define bcm63xx_get_cpu_id() BCM6328_CPU_ID
++# endif
++# define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
++#else
++# define BCMCPU_IS_6328() (0)
++#endif
++
+ #ifdef CONFIG_BCM63XX_CPU_6338
+ # ifdef bcm63xx_get_cpu_id
+ # undef bcm63xx_get_cpu_id
+@@ -157,6 +171,49 @@ enum bcm63xx_regs_set {
+ #define RSET_TRNG_SIZE 20
+
+ /*
++ * 6328 register sets base address
++ */
++#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
++#define BCM_6328_PERF_BASE (0xb0000000)
++#define BCM_6328_TIMER_BASE (0xb0000040)
++#define BCM_6328_WDT_BASE (0xb000005c)
++#define BCM_6328_UART0_BASE (0xb0000100)
++#define BCM_6328_UART1_BASE (0xb0000120)
++#define BCM_6328_GPIO_BASE (0xb0000080)
++#define BCM_6328_SPI_BASE (0xdeadbeef)
++#define BCM_6328_UDC0_BASE (0xdeadbeef)
++#define BCM_6328_USBDMA_BASE (0xdeadbeef)
++#define BCM_6328_OHCI0_BASE (0xdeadbeef)
++#define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)
++#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef)
++#define BCM_6328_MPI_BASE (0xdeadbeef)
++#define BCM_6328_PCMCIA_BASE (0xdeadbeef)
++#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
++#define BCM_6328_DSL_BASE (0xb0001900)
++#define BCM_6328_UBUS_BASE (0xdeadbeef)
++#define BCM_6328_ENET0_BASE (0xdeadbeef)
++#define BCM_6328_ENET1_BASE (0xdeadbeef)
++#define BCM_6328_ENETDMA_BASE (0xb000d800)
++#define BCM_6328_ENETDMAC_BASE (0xb000da00)
++#define BCM_6328_ENETDMAS_BASE (0xb000dc00)
++#define BCM_6328_ENETSW_BASE (0xb0e00000)
++#define BCM_6328_EHCI0_BASE (0x10002500)
++#define BCM_6328_SDRAM_BASE (0xdeadbeef)
++#define BCM_6328_MEMC_BASE (0xdeadbeef)
++#define BCM_6328_DDR_BASE (0xb0003000)
++#define BCM_6328_M2M_BASE (0xdeadbeef)
++#define BCM_6328_ATM_BASE (0xdeadbeef)
++#define BCM_6328_XTM_BASE (0xdeadbeef)
++#define BCM_6328_XTMDMA_BASE (0xb000b800)
++#define BCM_6328_XTMDMAC_BASE (0xdeadbeef)
++#define BCM_6328_XTMDMAS_BASE (0xdeadbeef)
++#define BCM_6328_PCM_BASE (0xb000a800)
++#define BCM_6328_PCMDMA_BASE (0xdeadbeef)
++#define BCM_6328_PCMDMAC_BASE (0xdeadbeef)
++#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
++#define BCM_6328_TRNG_BASE (0xdeadbeef)
++#define BCM_6328_MISC_BASE (0xb0001800)
++/*
+ * 6338 register sets base address
+ */
+ #define BCM_6338_DSL_LMEM_BASE (0xfff00000)
+@@ -466,6 +523,9 @@ static inline unsigned long bcm63xx_regs
+ #ifdef BCMCPU_RUNTIME_DETECT
+ return bcm63xx_regs_base[set];
+ #else
++#ifdef CONFIG_BCM63XX_CPU_6328
++ __GEN_RSET(6328)
++#endif
+ #ifdef CONFIG_BCM63XX_CPU_6338
+ __GEN_RSET(6338)
+ #endif
+@@ -520,6 +580,47 @@ enum bcm63xx_irq {
+ };
+
+ /*
++ * 6328 irqs
++ */
++#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
++
++#define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)
++#define BCM_6328_SPI_IRQ 0
++#define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28)
++#define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
++#define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
++#define BCM_6328_UDC0_IRQ 0
++#define BCM_6328_ENET0_IRQ 0
++#define BCM_6328_ENET1_IRQ 0
++#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
++#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
++#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
++#define BCM_6328_PCMCIA_IRQ 0
++#define BCM_6328_ENET0_RXDMA_IRQ 0
++#define BCM_6328_ENET0_TXDMA_IRQ 0
++#define BCM_6328_ENET1_RXDMA_IRQ 0
++#define BCM_6328_ENET1_TXDMA_IRQ 0
++#define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23)
++#define BCM_6328_ATM_IRQ 0
++#define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0)
++#define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1)
++#define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2)
++#define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3)
++#define BCM_6328_ENETSW_TXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 4)
++#define BCM_6328_ENETSW_TXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 5)
++#define BCM_6328_ENETSW_TXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 6)
++#define BCM_6328_ENETSW_TXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
++#define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31)
++#define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11)
++
++#define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)
++#define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)
++#define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)
++#define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)
++#define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)
++#define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)
++
++/*
+ * 6338 irqs
+ */
+ #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+@@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void);
+ static inline unsigned long bcm63xx_gpio_count(void)
+ {
+ switch (bcm63xx_get_cpu_id()) {
++ case BCM6328_CPU_ID:
++ return 32;
+ case BCM6358_CPU_ID:
+ return 40;
+ case BCM6338_CPU_ID:
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -15,6 +15,30 @@
+ /* Clock Control register */
+ #define PERF_CKCTL_REG 0x4
+
++#define CKCTL_6328_PHYMIPS_EN (1 << 0)
++#define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
++#define CKCTL_6328_ADSL_AFE_EN (1 << 2)
++#define CKCTL_6328_ADSL_EN (1 << 3)
++#define CKCTL_6328_MIPS_EN (1 << 4)
++#define CKCTL_6328_SAR_EN (1 << 5)
++#define CKCTL_6328_PCM_EN (1 << 6)
++#define CKCTL_6328_USBD_EN (1 << 7)
++#define CKCTL_6328_USBH_EN (1 << 8)
++#define CKCTL_6328_HSSPI_EN (1 << 9)
++#define CKCTL_6328_PCIE_EN (1 << 10)
++#define CKCTL_6328_ROBOSW_EN (1 << 11)
++
++#define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \
++ CKCTL_6328_ADSL_QPROC_EN | \
++ CKCTL_6328_ADSL_AFE_EN | \
++ CKCTL_6328_ADSL_EN | \
++ CKCTL_6328_SAR_EN | \
++ CKCTL_6328_PCM_EN | \
++ CKCTL_6328_USBD_EN | \
++ CKCTL_6328_USBH_EN | \
++ CKCTL_6328_ROBOSW_EN | \
++ CKCTL_6328_PCIE_EN)
++
+ #define CKCTL_6338_ADSLPHY_EN (1 << 0)
+ #define CKCTL_6338_MPI_EN (1 << 1)
+ #define CKCTL_6338_DRAM_EN (1 << 2)
+@@ -119,6 +143,7 @@
+ #define SYS_PLL_SOFT_RESET 0x1
+
+ /* Interrupt Mask register */
++#define PERF_IRQMASK_6328_REG 0x20
+ #define PERF_IRQMASK_6338_REG 0xc
+ #define PERF_IRQMASK_6345_REG 0xc
+ #define PERF_IRQMASK_6348_REG 0xc
+@@ -126,6 +151,7 @@
+ #define PERF_IRQMASK_6368_REG 0x20
+
+ /* Interrupt Status register */
++#define PERF_IRQSTAT_6328_REG 0x28
+ #define PERF_IRQSTAT_6338_REG 0x10
+ #define PERF_IRQSTAT_6345_REG 0x10
+ #define PERF_IRQSTAT_6348_REG 0x10
+@@ -133,6 +159,7 @@
+ #define PERF_IRQSTAT_6368_REG 0x28
+
+ /* External Interrupt Configuration register */
++#define PERF_EXTIRQ_CFG_REG_6328 0x18
+ #define PERF_EXTIRQ_CFG_REG_6338 0x14
+ #define PERF_EXTIRQ_CFG_REG_6345 0x14
+ #define PERF_EXTIRQ_CFG_REG_6348 0x14
+@@ -163,8 +190,21 @@
+
+ /* Soft Reset register */
+ #define PERF_SOFTRESET_REG 0x28
++#define PERF_SOFTRESET_6328_REG 0x10
+ #define PERF_SOFTRESET_6368_REG 0x10
+
++#define SOFTRESET_6328_SPI_MASK (1 << 0)
++#define SOFTRESET_6328_EPHY_MASK (1 << 1)
++#define SOFTRESET_6328_SAR_MASK (1 << 2)
++#define SOFTRESET_6328_ENETSW_MASK (1 << 3)
++#define SOFTRESET_6328_USBS_MASK (1 << 4)
++#define SOFTRESET_6328_USBH_MASK (1 << 5)
++#define SOFTRESET_6328_PCM_MASK (1 << 6)
++#define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7)
++#define SOFTRESET_6328_PCIE_MASK (1 << 8)
++#define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9)
++#define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10)
++
+ #define SOFTRESET_6338_SPI_MASK (1 << 0)
+ #define SOFTRESET_6338_ENET_MASK (1 << 2)
+ #define SOFTRESET_6338_USBH_MASK (1 << 3)
+@@ -308,6 +348,8 @@
+ /* Watchdog reset length register */
+ #define WDT_RSTLEN_REG 0x8
+
++/* Watchdog soft reset register (BCM6328 only) */
++#define WDT_SOFTRESET_REG 0xc
+
+ /*************************************************************************
+ * _REG relative to RSET_UARTx
+@@ -934,6 +976,8 @@
+ * _REG relative to RSET_DDR
+ *************************************************************************/
+
++#define DDR_CSEND_REG 0x8
++
+ #define DDR_DMIPSPLLCFG_REG 0x18
+ #define DMIPSPLLCFG_M1_SHIFT 0
+ #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
+--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
++++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+@@ -18,6 +18,7 @@ static inline int is_bcm63xx_internal_re
+ if (offset >= 0xfff00000)
+ return 1;
+ break;
++ case BCM6328_CPU_ID:
+ case BCM6368_CPU_ID:
+ if (offset >= 0xb0000000 && offset < 0xb1000000)
+ return 1;
--- /dev/null
+From dc087ed1d9d4ae326a47e4a1eef3a079acf4a1f5 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Tue, 14 Jun 2011 21:14:39 +0200
+Subject: [PATCH 41/79] MIPS: BCM63XX: add flash type detection for BCM6328
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/bcm63xx/dev-flash.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/mips/bcm63xx/dev-flash.c
++++ b/arch/mips/bcm63xx/dev-flash.c
+@@ -59,6 +59,12 @@ static int __init bcm63xx_detect_flash_t
+ u32 val;
+
+ switch (bcm63xx_get_cpu_id()) {
++ case BCM6328_CPU_ID:
++ val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
++ if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
++ return BCM63XX_FLASH_TYPE_SERIAL;
++ else
++ return BCM63XX_FLASH_TYPE_NAND;
+ case BCM6338_CPU_ID:
+ case BCM6345_CPU_ID:
+ case BCM6348_CPU_ID:
--- /dev/null
+From c110865541e2d3782c412af9d48c016de5a64d9c Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Tue, 14 Jun 2011 21:14:39 +0200
+Subject: [PATCH 42/79] MIPS: BCM63XX: allow second UART on BCM6328
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/bcm63xx/dev-uart.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/bcm63xx/dev-uart.c
++++ b/arch/mips/bcm63xx/dev-uart.c
+@@ -54,7 +54,8 @@ int __init bcm63xx_uart_register(unsigne
+ if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
+ return -ENODEV;
+
+- if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
++ if (id == 1 && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&
++ !BCMCPU_IS_6368())
+ return -ENODEV;
+
+ if (id == 0) {
--- /dev/null
+From f7d09679600b187fcfa1d70819e53f190fb1c231 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Sun, 3 Jul 2011 03:08:11 +0200
+Subject: [PATCH 45/79] MIPS: BCM63XX: Move the PCI initialization into its
+ own function
+
+Also make the cpu check a bit more explicit.
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/pci/pci-bcm63xx.c | 25 +++++++++++++++++--------
+ 1 file changed, 17 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -88,14 +88,10 @@ static void bcm63xx_int_cfg_writel(u32 v
+
+ void __iomem *pci_iospace_start;
+
+-int __init bcm63xx_pci_register(void)
++static int __init bcm63xx_register_pci(void)
+ {
+ unsigned int mem_size;
+ u32 val;
+-
+- if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
+- return -ENODEV;
+-
+ /*
+ * configuration access are done through IO space, remap 4
+ * first bytes to access it from CPU.
+@@ -211,3 +207,16 @@ int __init bcm63xx_pci_register(void)
+ "bcm63xx PCI IO space");
+ return 0;
+ }
++
++int __init bcm63xx_pci_register(void)
++{
++ switch (bcm63xx_get_cpu_id()) {
++ case BCM6348_CPU_ID:
++ case BCM6358_CPU_ID:
++ case BCM6368_CPU_ID:
++ return bcm63xx_register_pci();
++ default:
++ return -ENODEV;
++ }
++}
++
--- /dev/null
+From 9a16718a325c1969422eb9d9b644eb89ce06692c Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Sun, 3 Jul 2011 03:41:02 +0200
+Subject: [PATCH 46/79] MIPS: BCM63XX: Add PCIe register set definitions
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 9 ++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 6 +++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 54 +++++++++++++++++++++
+ 3 files changed, 69 insertions(+)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -122,6 +122,7 @@ enum bcm63xx_regs_set {
+ RSET_USBH_PRIV,
+ RSET_MPI,
+ RSET_PCMCIA,
++ RSET_PCIE,
+ RSET_DSL,
+ RSET_ENET0,
+ RSET_ENET1,
+@@ -188,6 +189,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6328_USBH_PRIV_BASE (0xdeadbeef)
+ #define BCM_6328_MPI_BASE (0xdeadbeef)
+ #define BCM_6328_PCMCIA_BASE (0xdeadbeef)
++#define BCM_6328_PCIE_BASE (0xb0e40000)
+ #define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
+ #define BCM_6328_DSL_BASE (0xb0001900)
+ #define BCM_6328_UBUS_BASE (0xdeadbeef)
+@@ -232,6 +234,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
+ #define BCM_6338_MPI_BASE (0xfffe3160)
+ #define BCM_6338_PCMCIA_BASE (0xdeadbeef)
++#define BCM_6338_PCIE_BASE (0xdeadbeef)
+ #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
+ #define BCM_6338_DSL_BASE (0xfffe1000)
+ #define BCM_6338_UBUS_BASE (0xdeadbeef)
+@@ -279,6 +282,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6345_ENETSW_BASE (0xdeadbeef)
+ #define BCM_6345_PCMCIA_BASE (0xfffe2028)
+ #define BCM_6345_MPI_BASE (0xfffe2000)
++#define BCM_6345_PCIE_BASE (0xdeadbeef)
+ #define BCM_6345_OHCI0_BASE (0xfffe2100)
+ #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
+ #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
+@@ -320,6 +324,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
+ #define BCM_6348_MPI_BASE (0xfffe2000)
+ #define BCM_6348_PCMCIA_BASE (0xfffe2054)
++#define BCM_6348_PCIE_BASE (0xdeadbeef)
+ #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
+ #define BCM_6348_M2M_BASE (0xfffe2800)
+ #define BCM_6348_DSL_BASE (0xfffe3000)
+@@ -362,6 +367,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
+ #define BCM_6358_MPI_BASE (0xfffe1000)
+ #define BCM_6358_PCMCIA_BASE (0xfffe1054)
++#define BCM_6358_PCIE_BASE (0xdeadbeef)
+ #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
+ #define BCM_6358_M2M_BASE (0xdeadbeef)
+ #define BCM_6358_DSL_BASE (0xfffe3000)
+@@ -405,6 +411,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6368_USBH_PRIV_BASE (0xb0001700)
+ #define BCM_6368_MPI_BASE (0xb0001000)
+ #define BCM_6368_PCMCIA_BASE (0xb0001054)
++#define BCM_6368_PCIE_BASE (0xdeadbeef)
+ #define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
+ #define BCM_6368_M2M_BASE (0xdeadbeef)
+ #define BCM_6368_DSL_BASE (0xdeadbeef)
+@@ -453,6 +460,7 @@ extern const unsigned long *bcm63xx_regs
+ __GEN_RSET_BASE(__cpu, USBH_PRIV) \
+ __GEN_RSET_BASE(__cpu, MPI) \
+ __GEN_RSET_BASE(__cpu, PCMCIA) \
++ __GEN_RSET_BASE(__cpu, PCIE) \
+ __GEN_RSET_BASE(__cpu, DSL) \
+ __GEN_RSET_BASE(__cpu, ENET0) \
+ __GEN_RSET_BASE(__cpu, ENET1) \
+@@ -493,6 +501,7 @@ extern const unsigned long *bcm63xx_regs
+ [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
+ [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
+ [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
++ [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \
+ [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
+ [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
+ [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+@@ -40,6 +40,10 @@
+ #define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \
+ BCM_CB_MEM_SIZE - 1)
+
++#define BCM_PCIE_MEM_BASE_PA 0x10f00000
++#define BCM_PCIE_MEM_SIZE (16 * 1024 * 1024)
++#define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \
++ BCM_PCIE_MEM_SIZE - 1)
+
+ /*
+ * Internal registers are accessed through KSEG3
+@@ -85,6 +89,8 @@
+ #define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o))
+ #define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o))
+ #define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
++#define bcm_pcie_readl(o) bcm_rset_readl(RSET_PCIE, (o))
++#define bcm_pcie_writel(v, o) bcm_rset_writel(RSET_PCIE, (v), (o))
+ #define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o))
+ #define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o))
+ #define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o))
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -1163,6 +1163,9 @@
+ /*************************************************************************
+ * _REG relative to RSET_MISC
+ *************************************************************************/
++#define MISC_SERDES_CTRL_REG 0x0
++#define SERDES_PCIE_EN (1 << 0)
++#define SERDES_PCIE_EXD_EN (1 << 15)
+
+ #define MISC_STRAPBUS_6328_REG 0x240
+ #define STRAPBUS_6328_FCVO_SHIFT 7
+@@ -1170,4 +1173,55 @@
+ #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
+ #define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
+
++/*************************************************************************
++ * _REG relative to RSET_PCIE
++ *************************************************************************/
++
++#define PCIE_CONFIG2_REG 0x408
++#define CONFIG2_BAR1_SIZE_EN 1
++#define CONFIG2_BAR1_SIZE_MASK 0xf
++
++#define PCIE_IDVAL3_REG 0x43c
++#define IDVAL3_CLASS_CODE_MASK 0xffffff
++#define IDVAL3_SUBCLASS_SHIFT 8
++#define IDVAL3_CLASS_SHIFT 16
++
++#define PCIE_DLSTATUS_REG 0x1048
++#define DLSTATUS_PHYLINKUP (1 << 13)
++
++#define PCIE_BRIDGE_OPT1_REG 0x2820
++#define OPT1_RD_BE_OPT_EN (1 << 7)
++#define OPT1_RD_REPLY_BE_FIX_EN (1 << 9)
++#define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11)
++#define OPT1_L1_INT_STATUS_MASK_POL (1 << 12)
++
++#define PCIE_BRIDGE_OPT2_REG 0x2824
++#define OPT2_UBUS_UR_DECODE_DIS (1 << 2)
++#define OPT2_TX_CREDIT_CHK_EN (1 << 4)
++#define OPT2_CFG_TYPE1_BD_SEL (1 << 7)
++#define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16
++#define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
++
++#define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828
++#define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830
++#define BASEMASK_REMAP_EN (1 << 0)
++#define BASEMASK_SWAP_EN (1 << 1)
++#define BASEMASK_MASK_SHIFT 4
++#define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT)
++#define BASEMASK_BASE_SHIFT 20
++#define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT)
++
++#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
++#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
++#define REBASE_ADDR_BASE_SHIFT 20
++#define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT)
++
++#define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854
++#define PCIE_RC_INT_A (1 << 0)
++#define PCIE_RC_INT_B (1 << 1)
++#define PCIE_RC_INT_C (1 << 2)
++#define PCIE_RC_INT_D (1 << 3)
++
++#define PCIE_DEVICE_OFFSET 0x8000
++
+ #endif /* BCM63XX_REGS_H_ */
--- /dev/null
+From e170282d7d12f4a26f10d4b666b158d24810d2f6 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Sun, 3 Jul 2011 03:41:02 +0200
+Subject: [PATCH 47/79] MIPS: BCM63XX: Add PCIe Support for BCM6328
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/pci/ops-bcm63xx.c | 61 +++++++++++++++++++++++
+ arch/mips/pci/pci-bcm63xx.c | 112 +++++++++++++++++++++++++++++++++++++++++++
+ arch/mips/pci/pci-bcm63xx.h | 5 ++
+ 3 files changed, 178 insertions(+)
+
+--- a/arch/mips/pci/ops-bcm63xx.c
++++ b/arch/mips/pci/ops-bcm63xx.c
+@@ -465,3 +465,64 @@ static void bcm63xx_fixup(struct pci_dev
+
+ DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
+ #endif
++
++static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn)
++{
++ switch (bus->number) {
++ case PCIE_BUS_BRIDGE:
++ return (PCI_SLOT(devfn) == 0);
++ case PCIE_BUS_DEVICE:
++ if (PCI_SLOT(devfn) == 0)
++ return bcm_pcie_readl(PCIE_DLSTATUS_REG)
++ & DLSTATUS_PHYLINKUP;
++ default:
++ return false;
++ }
++}
++
++static int bcm63xx_pcie_read(struct pci_bus *bus, unsigned int devfn,
++ int where, int size, u32 *val)
++{
++ u32 data;
++ u32 reg = where & ~3;
++
++ if (!bcm63xx_pcie_can_access(bus, devfn))
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ if (bus->number == PCIE_BUS_DEVICE)
++ reg += PCIE_DEVICE_OFFSET;
++
++ data = bcm_pcie_readl(reg);
++
++ *val = postprocess_read(data, where, size);
++
++ return PCIBIOS_SUCCESSFUL;
++
++}
++
++static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn,
++ int where, int size, u32 val)
++{
++ u32 data;
++ u32 reg = where & ~3;
++
++ if (!bcm63xx_pcie_can_access(bus, devfn))
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ if (bus->number == PCIE_BUS_DEVICE)
++ reg += PCIE_DEVICE_OFFSET;
++
++
++ data = bcm_pcie_readl(reg);
++
++ data = preprocess_write(data, val, where, size);
++ bcm_pcie_writel(data, reg);
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++
++struct pci_ops bcm63xx_pcie_ops = {
++ .read = bcm63xx_pcie_read,
++ .write = bcm63xx_pcie_write
++};
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -10,6 +10,7 @@
+ #include <linux/pci.h>
+ #include <linux/kernel.h>
+ #include <linux/init.h>
++#include <linux/delay.h>
+ #include <asm/bootinfo.h>
+
+ #include "pci-bcm63xx.h"
+@@ -65,6 +66,26 @@ struct pci_controller bcm63xx_cb_control
+ };
+ #endif
+
++static struct resource bcm_pcie_mem_resource = {
++ .name = "bcm63xx PCIe memory space",
++ .start = BCM_PCIE_MEM_BASE_PA,
++ .end = BCM_PCIE_MEM_END_PA,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct resource bcm_pcie_io_resource = {
++ .name = "bcm63xx PCIe IO space",
++ .start = 0,
++ .end = 0,
++ .flags = 0,
++};
++
++struct pci_controller bcm63xx_pcie_controller = {
++ .pci_ops = &bcm63xx_pcie_ops,
++ .io_resource = &bcm_pcie_io_resource,
++ .mem_resource = &bcm_pcie_mem_resource,
++};
++
+ static u32 bcm63xx_int_cfg_readl(u32 reg)
+ {
+ u32 tmp;
+@@ -88,6 +109,95 @@ static void bcm63xx_int_cfg_writel(u32 v
+
+ void __iomem *pci_iospace_start;
+
++static void __init bcm63xx_reset_pcie(void)
++{
++ u32 val;
++
++ /* enable clock */
++ val = bcm_perf_readl(PERF_CKCTL_REG);
++ val |= CKCTL_6328_PCIE_EN;
++ bcm_perf_writel(val, PERF_CKCTL_REG);
++
++ /* enable SERDES */
++ val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
++ val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
++ bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
++
++ /* reset the PCIe core */
++ val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
++
++ val &= ~SOFTRESET_6328_PCIE_MASK;
++ val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
++ val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
++ val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
++ bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
++ mdelay(10);
++
++ val |= SOFTRESET_6328_PCIE_MASK;
++ val |= SOFTRESET_6328_PCIE_CORE_MASK;
++ val |= SOFTRESET_6328_PCIE_HARD_MASK;
++ bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
++ mdelay(10);
++
++ val |= SOFTRESET_6328_PCIE_EXT_MASK;
++ bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
++ mdelay(200);
++}
++
++static int __init bcm63xx_register_pcie(void)
++{
++ u32 val;
++
++ bcm63xx_reset_pcie();
++
++ /* configure the PCIe bridge */
++ val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
++ val |= OPT1_RD_BE_OPT_EN;
++ val |= OPT1_RD_REPLY_BE_FIX_EN;
++ val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
++ val |= OPT1_L1_INT_STATUS_MASK_POL;
++ bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG);
++
++ /* setup the interrupts */
++ val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG);
++ val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D;
++ bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG);
++
++ val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG);
++ /* enable credit checking and error checking */
++ val |= OPT2_TX_CREDIT_CHK_EN;
++ val |= OPT2_UBUS_UR_DECODE_DIS;
++
++ /* set device bus/func for the pcie device */
++ val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
++ val |= OPT2_CFG_TYPE1_BD_SEL;
++ bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
++
++ /* setup class code as bridge */
++ val = bcm_pcie_readl(PCIE_IDVAL3_REG);
++ val &= ~IDVAL3_CLASS_CODE_MASK;
++ val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
++ bcm_pcie_writel(val, PCIE_IDVAL3_REG);
++
++ /* disable bar1 size */
++ val = bcm_pcie_readl(PCIE_CONFIG2_REG);
++ val &= ~CONFIG2_BAR1_SIZE_MASK;
++ bcm_pcie_writel(val, PCIE_CONFIG2_REG);
++
++ /* set bar0 to little endian */
++ val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
++ val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
++ val |= BASEMASK_REMAP_EN;
++ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
++
++ val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
++ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
++
++ register_pci_controller(&bcm63xx_pcie_controller);
++
++ return 0;
++}
++
+ static int __init bcm63xx_register_pci(void)
+ {
+ unsigned int mem_size;
+@@ -211,6 +321,8 @@ static int __init bcm63xx_register_pci(v
+ int __init bcm63xx_pci_register(void)
+ {
+ switch (bcm63xx_get_cpu_id()) {
++ case BCM6328_CPU_ID:
++ return bcm63xx_register_pcie();
+ case BCM6348_CPU_ID:
+ case BCM6358_CPU_ID:
+ case BCM6368_CPU_ID:
+--- a/arch/mips/pci/pci-bcm63xx.h
++++ b/arch/mips/pci/pci-bcm63xx.h
+@@ -13,11 +13,16 @@
+ */
+ #define CARDBUS_PCI_IDSEL 0x8
+
++
++#define PCIE_BUS_BRIDGE 0
++#define PCIE_BUS_DEVICE 1
++
+ /*
+ * defined in ops-bcm63xx.c
+ */
+ extern struct pci_ops bcm63xx_pci_ops;
+ extern struct pci_ops bcm63xx_cb_ops;
++extern struct pci_ops bcm63xx_pcie_ops;
+
+ /*
+ * defined in pci-bcm63xx.c
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
-@@ -4,26 +4,25 @@ menu "CPU support"
+@@ -8,26 +8,25 @@ config BCM63XX_CPU_6328
config BCM63XX_CPU_6338
bool "support 6338 CPU"
select HW_HAS_PCI
#include <board_bcm963xx.h>
#include <bcm_tag.h>
-@@ -906,6 +907,9 @@ int __init board_register_devices(void)
+@@ -911,6 +912,9 @@ int __init board_register_devices(void)
!board_get_mac_address(board.enet1.mac_addr))
bcm63xx_enet_register(1, &board.enet1);
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
-@@ -18,11 +18,13 @@ config BCM63XX_CPU_6358
+@@ -22,11 +22,13 @@ config BCM63XX_CPU_6358
bool "support 6358 CPU"
select HW_HAS_PCI
select USB_ARCH_HAS_OHCI if USB_SUPPORT
#include <board_bcm963xx.h>
#include <bcm_tag.h>
-@@ -907,6 +908,9 @@ int __init board_register_devices(void)
+@@ -912,6 +913,9 @@ int __init board_register_devices(void)
!board_get_mac_address(board.enet1.mac_addr))
bcm63xx_enet_register(1, &board.enet1);
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -845,6 +845,8 @@ void __init board_prom_init(void)
+@@ -850,6 +850,8 @@ void __init board_prom_init(void)
if (BCMCPU_IS_6348())
val |= GPIO_MODE_6348_G3_EXT_MII |
GPIO_MODE_6348_G0_EXT_MII;
bcm_gpio_writel(val, GPIO_MODE_REG);
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -468,6 +468,8 @@
+@@ -510,6 +510,8 @@
#define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
#define GPIO_MODE_6358_UTOPIA (1 << 12)
if (ret)
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-@@ -140,7 +140,9 @@ enum bcm63xx_regs_set {
+@@ -156,7 +156,9 @@ enum bcm63xx_regs_set {
#define BCM_6358_RSET_SPI_SIZE 1804
#define BCM_6368_RSET_SPI_SIZE 1804
#define RSET_ENET_SIZE 2048
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -910,6 +910,10 @@ int __init board_register_devices(void)
+@@ -915,6 +915,10 @@ int __init board_register_devices(void)
!board_get_mac_address(board.enet1.mac_addr))
bcm63xx_enet_register(1, &board.enet1);
#endif /* ! BCM63XX_DEV_ENET_H_ */
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -708,10 +708,60 @@
+@@ -750,10 +750,60 @@
* _REG relative to RSET_ENETSW
*************************************************************************/
--- /dev/null
+From 37d151859e09d09a950ad3ae615db1903bcc59d3 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Sun, 13 Nov 2011 14:59:37 +0100
+Subject: [PATCH 43/79] bcm63xx_enet: fix lockup on BCM6328
+
+BCM6328 locks up on a maxburst size of 16, reduce it to 8 for BCM6328 and
+BCM6368.
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c | 14 ++++++++------
+ drivers/net/ethernet/broadcom/bcm63xx_enet.h | 4 ++++
+ 2 files changed, 12 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -261,7 +261,6 @@ static int bcm_enet_refill_rx(struct net
+ if (!skb)
+ break;
+ priv->rx_skb[desc_idx] = skb;
+-
+ p = dma_map_single(&priv->pdev->dev, skb->data,
+ priv->rx_skb_size,
+ DMA_FROM_DEVICE);
+@@ -995,9 +994,9 @@ static int bcm_enet_open(struct net_devi
+ enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
+
+ /* set dma maximum burst len */
+- enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
++ enet_dmac_writel(priv, priv->dma_maxburst,
+ ENETDMAC_MAXBURST_REG(priv->rx_chan));
+- enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
++ enet_dmac_writel(priv, priv->dma_maxburst,
+ ENETDMAC_MAXBURST_REG(priv->tx_chan));
+
+ /* set correct transmit fifo watermark */
+@@ -1593,7 +1592,7 @@ static int compute_hw_mtu(struct bcm_ene
+ * it's appended
+ */
+ priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
+- BCMENET_DMA_MAXBURST * 4);
++ priv->dma_maxburst * 4);
+ return 0;
+ }
+
+@@ -1700,6 +1699,8 @@ static int __devinit bcm_enet_probe(stru
+ return -ENOMEM;
+ priv = netdev_priv(dev);
+
++ priv->dma_maxburst = bcm_enet_is_sw(priv) ?
++ BCMENETSW_DMA_MAXBURST : BCMENET_DMA_MAXBURST;
+ ret = compute_hw_mtu(priv, dev->mtu);
+ if (ret)
+ goto out;
+@@ -2263,9 +2264,9 @@ static int bcm_enetsw_open(struct net_de
+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
+
+ /* set dma maximum burst len */
+- enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
++ enet_dmac_writel(priv, priv->dma_maxburst,
+ ENETDMAC_MAXBURST_REG(priv->rx_chan));
+- enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
++ enet_dmac_writel(priv, priv->dma_maxburst,
+ ENETDMAC_MAXBURST_REG(priv->tx_chan));
+
+ /* set flow control low/high threshold to 1/3 / 2/3 */
+@@ -2727,6 +2728,7 @@ static int __devinit bcm_enetsw_probe(st
+ priv->irq_tx = irq_tx;
+ priv->rx_ring_size = BCMENET_DEF_RX_DESC;
+ priv->tx_ring_size = BCMENET_DEF_TX_DESC;
++ priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
+
+ pd = pdev->dev.platform_data;
+ if (pd) {
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
+@@ -17,6 +17,7 @@
+
+ /* maximum burst len for dma (4 bytes unit) */
+ #define BCMENET_DMA_MAXBURST 16
++#define BCMENETSW_DMA_MAXBURST 8
+
+ /* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value
+ * must be low enough so that a DMA transfer of above burst length can
+@@ -280,6 +281,9 @@ struct bcm_enet_priv {
+ /* number of dma desc in tx ring */
+ int tx_ring_size;
+
++ /* maximum dma burst size */
++ int dma_maxburst;
++
+ /* cpu view of rx dma ring */
+ struct bcm_enet_desc *tx_desc_cpu;
+
--- /dev/null
+From 44e21f4c7c556573fff0432f7846086763df3455 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Tue, 14 Jun 2011 21:14:39 +0200
+Subject: [PATCH 44/79] MIPS: BCM63XX: add support for BCM6328 in bcm_enetsw
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/bcm63xx/clk.c | 34 +++++++++++++++++++-------
+ arch/mips/bcm63xx/dev-enet.c | 4 +--
+ drivers/net/ethernet/broadcom/bcm63xx_enet.h | 2 +-
+ 3 files changed, 28 insertions(+), 12 deletions(-)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -118,21 +118,37 @@ static struct clk clk_ephy = {
+ */
+ static void enetsw_set(struct clk *clk, int enable)
+ {
+- if (!BCMCPU_IS_6368())
++ u32 mask;
++
++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368())
+ return;
+- bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
+- CKCTL_6368_SWPKT_USB_EN |
+- CKCTL_6368_SWPKT_SAR_EN, enable);
++
++ if (BCMCPU_IS_6328())
++ mask = CKCTL_6328_ROBOSW_EN;
++ else
++ mask = CKCTL_6368_ROBOSW_EN | CKCTL_6368_SWPKT_USB_EN |
++ CKCTL_6368_SWPKT_SAR_EN;
++
++ bcm_hwclock_set(mask, enable);
+ if (enable) {
++ u32 reg;
+ u32 val;
+
++ if (BCMCPU_IS_6328()) {
++ reg = PERF_SOFTRESET_6328_REG;
++ mask = SOFTRESET_6328_ENETSW_MASK;
++ } else {
++ reg = PERF_SOFTRESET_6368_REG;
++ mask = SOFTRESET_6368_ENETSW_MASK;
++ }
++
+ /* reset switch core afer clock change */
+- val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
+- val &= ~SOFTRESET_6368_ENETSW_MASK;
+- bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
++ val = bcm_perf_readl(reg);
++ val &= ~mask;
++ bcm_perf_writel(val, reg);
+ msleep(10);
+- val |= SOFTRESET_6368_ENETSW_MASK;
+- bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
++ val |= mask;
++ bcm_perf_writel(val, reg);
+ msleep(10);
+ }
+ }
+--- a/arch/mips/bcm63xx/dev-enet.c
++++ b/arch/mips/bcm63xx/dev-enet.c
+@@ -141,7 +141,7 @@ static int __init register_shared(void)
+ shared_res[0].end = shared_res[0].start;
+ shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
+
+- if (BCMCPU_IS_6368())
++ if (BCMCPU_IS_6328() || BCMCPU_IS_6368())
+ chan_count = 32;
+ else
+ chan_count = 16;
+@@ -224,7 +224,7 @@ bcm63xx_enetsw_register(const struct bcm
+ {
+ int ret;
+
+- if (!BCMCPU_IS_6368())
++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368())
+ return -ENODEV;
+
+ ret = register_shared();
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
+@@ -368,7 +368,7 @@ struct bcm_enet_priv {
+
+ static inline int bcm_enet_is_sw(struct bcm_enet_priv *priv)
+ {
+- if (BCMCPU_IS_6368())
++ if (BCMCPU_IS_6328() || BCMCPU_IS_6368())
+ return 1;
+ else
+ return 0;
/*
* Register a sane SPROMv2 to make the on-board
* bcm4318 WLAN work
-@@ -848,6 +1368,9 @@ void __init board_prom_init(void)
+@@ -853,6 +1373,9 @@ void __init board_prom_init(void)
boardid_fixup(boot_addr);
}
#endif
#ifdef CONFIG_BCM63XX_CPU_6358
-@@ -1938,6 +1996,22 @@ void __init board_prom_init(void)
- val = bcm_mpi_readl(MPI_CSBASE_REG(0));
- val &= MPI_CSBASE_BASE_MASK;
+@@ -1943,6 +2001,22 @@ void __init board_prom_init(void)
+ val &= MPI_CSBASE_BASE_MASK;
+ }
boot_addr = (u8 *)KSEG1ADDR(val);
+ printk(KERN_INFO PFX "Boot address 0x%08x\n",(unsigned int)boot_addr);
+
#include <bcm63xx_cpu.h>
#include <bcm63xx_dev_flash.h>
#include <bcm63xx_regs.h>
-@@ -98,6 +99,13 @@ int __init bcm63xx_flash_register(void)
+@@ -104,6 +105,13 @@ int __init bcm63xx_flash_register(void)
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
val &= MPI_CSBASE_BASE_MASK;
};
static void __init nb4_nvram_fixup(void)
-@@ -2280,12 +2358,25 @@ void __init board_prom_init(void)
+@@ -2285,12 +2363,25 @@ void __init board_prom_init(void)
if (board.has_pci) {
if (BCMCPU_IS_6348())
val |= GPIO_MODE_6348_G2_PCI;
* known 6338 boards
*/
#ifdef CONFIG_BCM63XX_CPU_6338
-@@ -2490,6 +2498,7 @@ void __init board_prom_init(void)
+@@ -2495,6 +2503,7 @@ void __init board_prom_init(void)
/* extract nvram data */
memcpy(&nvram, boot_addr + BCM963XX_NVRAM_OFFSET, sizeof(nvram));
projects / openwrt / openwrt.git / commitdiff