--- /dev/null
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c u-boot/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c 2015-01-01 17:34:32.005507318 +0100
+@@ -209,6 +209,10 @@
+ .gate = SW_ONLY_GATE(0x0360, 20, 4),
+ };
+
++static struct bus_clk_data usb_otg_ahb_data = {
++ .gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
++};
++
+ static struct bus_clk_data sdio1_ahb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
+ };
+@@ -331,6 +335,17 @@
+ */
+
+ /* KPM bus clocks */
++static struct bus_clock usb_otg_ahb_clk = {
++ .clk = {
++ .name = "usb_otg_ahb_clk",
++ .parent = &kpm_ccu_clk.clk,
++ .ops = &bus_clk_ops,
++ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
++ },
++ .freq_tbl = master_ahb_freq_tbl,
++ .data = &usb_otg_ahb_data,
++};
++
+ static struct bus_clock sdio1_ahb_clk = {
+ .clk = {
+ .name = "sdio1_ahb_clk",
+@@ -541,6 +556,7 @@
+ CLK_LK(bsc2),
+ CLK_LK(bsc3),
+ /* Bus clocks */
++ CLK_LK(usb_otg_ahb),
+ CLK_LK(sdio1_ahb),
+ CLK_LK(sdio2_ahb),
+ CLK_LK(sdio3_ahb),
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c u-boot/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c 2015-01-01 17:34:32.005507318 +0100
+@@ -0,0 +1,27 @@
++/*
++ * Copyright 2014 Broadcom Corporation.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/errno.h>
++#include <asm/arch/sysmap.h>
++#include "clk-core.h"
++
++/* Enable appropriate clocks for the USB OTG port */
++int clk_usb_otg_enable(void *base)
++{
++ char *ahbstr;
++
++ switch ((u32) base) {
++ case HSOTG_BASE_ADDR:
++ ahbstr = "usb_otg_ahb_clk";
++ break;
++ default:
++ printf("%s: base 0x%p not found\n", __func__, base);
++ return -EINVAL;
++ }
++
++ return clk_get_and_enable(ahbstr);
++}
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/Makefile u-boot/arch/arm/cpu/armv7/bcm281xx/Makefile
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/Makefile 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/bcm281xx/Makefile 2015-01-01 17:34:32.005507318 +0100
+@@ -10,3 +10,4 @@
+ obj-y += clk-sdio.o
+ obj-y += clk-bsc.o
+ obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
++obj-y += clk-usb-otg.o
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/kona-common/clk-stubs.c u-boot/arch/arm/cpu/armv7/kona-common/clk-stubs.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/kona-common/clk-stubs.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/kona-common/clk-stubs.c 2015-01-01 17:34:32.009507252 +0100
+@@ -19,3 +19,8 @@
+ {
+ return 0;
+ }
++
++int __weak clk_usb_otg_enable(void *base)
++{
++ return 0;
++}
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/cpu.c u-boot/arch/arm/cpu/armv7/ls102xa/cpu.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/cpu.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/ls102xa/cpu.c 2015-01-01 17:34:32.009507252 +0100
+@@ -12,6 +12,8 @@
+ #include <netdev.h>
+ #include <fsl_esdhc.h>
+
++#include "fsl_epu.h"
++
+ DECLARE_GLOBAL_DATA_PTR;
+
+ #if defined(CONFIG_DISPLAY_CPUINFO)
+@@ -101,3 +103,35 @@
+
+ return 0;
+ }
++
++int arch_cpu_init(void)
++{
++ void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
++
++ /*
++ * After wakeup from deep sleep, Clear EPU registers
++ * as early as possible to prevent from possible issue.
++ * It's also safe to clear at normal boot.
++ */
++ fsl_epu_clean(epu_base);
++
++ return 0;
++}
++
++#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
++/* Set the address at which the secondary core starts from.*/
++void smp_set_core_boot_addr(unsigned long addr, int corenr)
++{
++ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
++
++ out_be32(&gur->scratchrw[0], addr);
++}
++
++/* Release the secondary core from holdoff state and kick it */
++void smp_kick_all_cpus(void)
++{
++ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
++
++ out_be32(&gur->brrl, 0x2);
++}
++#endif
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fdt.c u-boot/arch/arm/cpu/armv7/ls102xa/fdt.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fdt.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/ls102xa/fdt.c 2015-01-01 17:34:32.009507252 +0100
+@@ -91,7 +91,7 @@
+ }
+
+ do_fixup_by_prop_u32(blob, "device_type", "soc",
+- 4, "bus-frequency", busclk / 2, 1);
++ 4, "bus-frequency", busclk, 1);
+
+ ft_fixup_enet_phy_connect_type(blob);
+
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fsl_epu.c u-boot/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fsl_epu.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/ls102xa/fsl_epu.c 2015-01-01 17:34:32.009507252 +0100
+@@ -0,0 +1,57 @@
++/*
++ * Copyright 2014 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/io.h>
++
++#include "fsl_epu.h"
++
++/**
++ * fsl_epu_clean - Clear EPU registers
++ */
++void fsl_epu_clean(void *epu_base)
++{
++ u32 offset;
++
++ /* follow the exact sequence to clear the registers */
++ /* Clear EPACRn */
++ for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
++ out_be32(epu_base + offset, 0);
++
++ /* Clear EPEVTCRn */
++ for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
++ out_be32(epu_base + offset, 0);
++
++ /* Clear EPGCR */
++ out_be32(epu_base + EPGCR, 0);
++
++ /* Clear EPSMCRn */
++ for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
++ out_be32(epu_base + offset, 0);
++
++ /* Clear EPCCRn */
++ for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
++ out_be32(epu_base + offset, 0);
++
++ /* Clear EPCMPRn */
++ for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
++ out_be32(epu_base + offset, 0);
++
++ /* Clear EPCTRn */
++ for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
++ out_be32(epu_base + offset, 0);
++
++ /* Clear EPIMCRn */
++ for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
++ out_be32(epu_base + offset, 0);
++
++ /* Clear EPXTRIGCRn */
++ out_be32(epu_base + EPXTRIGCR, 0);
++
++ /* Clear EPECRn */
++ for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
++ out_be32(epu_base + offset, 0);
++}
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fsl_epu.h u-boot/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fsl_epu.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/ls102xa/fsl_epu.h 2015-01-01 17:34:32.009507252 +0100
+@@ -0,0 +1,68 @@
++/*
++ * Copyright 2014 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __FSL_EPU_H
++#define __FSL_EPU_H
++
++#include <asm/types.h>
++
++#define FSL_STRIDE_4B 4
++#define FSL_STRIDE_8B 8
++
++/* Block offsets */
++#define EPU_BLOCK_OFFSET 0x00000000
++
++/* EPGCR (Event Processor Global Control Register) */
++#define EPGCR 0x000
++
++/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
++#define EPEVTCR0 0x050
++#define EPEVTCR9 0x074
++#define EPEVTCR_STRIDE FSL_STRIDE_4B
++
++/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
++#define EPXTRIGCR 0x090
++
++/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
++#define EPIMCR0 0x100
++#define EPIMCR31 0x17C
++#define EPIMCR_STRIDE FSL_STRIDE_4B
++
++/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
++#define EPSMCR0 0x200
++#define EPSMCR15 0x278
++#define EPSMCR_STRIDE FSL_STRIDE_8B
++
++/* EPECR0-15 (Event Processor Event Control Registers) */
++#define EPECR0 0x300
++#define EPECR15 0x33C
++#define EPECR_STRIDE FSL_STRIDE_4B
++
++/* EPACR0-15 (Event Processor Action Control Registers) */
++#define EPACR0 0x400
++#define EPACR15 0x43C
++#define EPACR_STRIDE FSL_STRIDE_4B
++
++/* EPCCRi0-15 (Event Processor Counter Control Registers) */
++#define EPCCR0 0x800
++#define EPCCR15 0x83C
++#define EPCCR31 0x87C
++#define EPCCR_STRIDE FSL_STRIDE_4B
++
++/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
++#define EPCMPR0 0x900
++#define EPCMPR15 0x93C
++#define EPCMPR31 0x97C
++#define EPCMPR_STRIDE FSL_STRIDE_4B
++
++/* EPCTR0-31 (Event Processor Counter Register) */
++#define EPCTR0 0xA00
++#define EPCTR31 0xA7C
++#define EPCTR_STRIDE FSL_STRIDE_4B
++
++void fsl_epu_clean(void *epu_base);
++
++#endif
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/Makefile u-boot/arch/arm/cpu/armv7/ls102xa/Makefile
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/Makefile 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/ls102xa/Makefile 2015-01-01 17:34:32.009507252 +0100
+@@ -7,6 +7,8 @@
+ obj-y += cpu.o
+ obj-y += clock.o
+ obj-y += timer.o
++obj-y += fsl_epu.o
+
+ obj-$(CONFIG_OF_LIBFDT) += fdt.o
+ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
++obj-$(CONFIG_SPL) += spl.o
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/spl.c u-boot/arch/arm/cpu/armv7/ls102xa/spl.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/spl.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/ls102xa/spl.c 2015-01-01 17:34:32.009507252 +0100
+@@ -0,0 +1,33 @@
++/*
++ * Copyright 2014 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <spl.h>
++
++u32 spl_boot_device(void)
++{
++#ifdef CONFIG_SPL_MMC_SUPPORT
++ return BOOT_DEVICE_MMC1;
++#endif
++ return BOOT_DEVICE_NAND;
++}
++
++u32 spl_boot_mode(void)
++{
++ switch (spl_boot_device()) {
++ case BOOT_DEVICE_MMC1:
++#ifdef CONFIG_SPL_FAT_SUPPORT
++ return MMCSD_MODE_FAT;
++#else
++ return MMCSD_MODE_RAW;
++#endif
++ case BOOT_DEVICE_NAND:
++ return 0;
++ default:
++ puts("spl: error: unsupported device\n");
++ hang();
++ }
++}
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/Makefile u-boot/arch/arm/cpu/armv7/Makefile
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/Makefile 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/Makefile 2015-01-01 17:34:32.001507383 +0100
+@@ -56,6 +56,7 @@
+ obj-$(CONFIG_RMOBILE) += rmobile/
+ obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
+ obj-$(CONFIG_SOCFPGA) += socfpga/
++obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
+ obj-$(CONFIG_ARCH_SUNXI) += sunxi/
+ obj-$(CONFIG_TEGRA20) += tegra20/
+ obj-$(CONFIG_U8500) += u8500/
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/mx6/clock.c u-boot/arch/arm/cpu/armv7/mx6/clock.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/mx6/clock.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/mx6/clock.c 2015-01-01 17:34:32.009507252 +0100
+@@ -443,7 +443,7 @@
+ struct anatop_regs __iomem *anatop =
+ (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+
+- if (freq < ENET_25MHz || freq > ENET_125MHz)
++ if (freq < ENET_25MHZ || freq > ENET_125MHZ)
+ return -EINVAL;
+
+ reg = readl(&anatop->pll_enet);
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/nonsec_virt.S u-boot/arch/arm/cpu/armv7/nonsec_virt.S
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/nonsec_virt.S 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/nonsec_virt.S 2015-01-01 17:34:32.013507186 +0100
+@@ -169,11 +169,11 @@
+ * we do this here instead.
+ * But first check if we have the generic timer.
+ */
+-#ifdef CONFIG_SYS_CLK_FREQ
++#ifdef CONFIG_TIMER_CLK_FREQ
+ mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
+ and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
+ cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
+- ldreq r1, =CONFIG_SYS_CLK_FREQ
++ ldreq r1, =CONFIG_TIMER_CLK_FREQ
+ mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
+ #endif
+
+@@ -191,6 +191,9 @@
+ wfi
+ ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
+ ldr r1, [r1]
++#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
++ rev r1, r1
++#endif
+ cmp r0, r1 @ make sure we dont execute this code
+ beq smp_waitloop @ again (due to a spurious wakeup)
+ mov r0, r1
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/socfpga/freeze_controller.c u-boot/arch/arm/cpu/armv7/socfpga/freeze_controller.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/socfpga/freeze_controller.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/socfpga/freeze_controller.c 2015-01-01 17:34:32.021507054 +0100
+@@ -38,8 +38,7 @@
+ /* Freeze channel 0 to 2 */
+ for (channel_id = 0; channel_id <= 2; channel_id++) {
+ ioctrl_reg_offset = (u32)(
+- &freeze_controller_base->vioctrl +
+- (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
++ &freeze_controller_base->vioctrl + channel_id);
+
+ /*
+ * Assert active low enrnsl, plniotri
+@@ -120,8 +119,7 @@
+ /* Thaw channel 0 to 2 */
+ for (channel_id = 0; channel_id <= 2; channel_id++) {
+ ioctrl_reg_offset
+- = (u32)(&freeze_controller_base->vioctrl
+- + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
++ = (u32)(&freeze_controller_base->vioctrl + channel_id);
+
+ /*
+ * Assert active low bhniotri signal and
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/socfpga/reset_manager.c u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/socfpga/reset_manager.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c 2015-01-01 17:34:32.021507054 +0100
+@@ -110,6 +110,6 @@
+ {
+ const void *reset = &reset_manager_base->per_mod_reset;
+
+- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
+- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);
++ clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) |
++ (1 << RSTMGR_PERMODRST_SPIM1_LSB));
+ }
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/clock.c u-boot/arch/arm/cpu/armv7/stv0991/clock.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/clock.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/stv0991/clock.c 2015-01-01 17:34:32.025506990 +0100
+@@ -0,0 +1,41 @@
++/*
++ * (C) Copyright 2014
++ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <asm/io.h>
++#include <asm/arch/hardware.h>
++#include <asm/arch/stv0991_cgu.h>
++#include<asm/arch/stv0991_periph.h>
++
++static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
++ (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
++
++void enable_pll1(void)
++{
++ /* pll1 already configured for 1000Mhz, just need to enable it */
++ writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01),
++ &stv0991_cgu_regs->pll1_ctrl);
++}
++
++void clock_setup(int peripheral)
++{
++ switch (peripheral) {
++ case UART_CLOCK_CFG:
++ writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq);
++ break;
++ case ETH_CLOCK_CFG:
++ enable_pll1();
++ writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq);
++
++ /* Clock selection for ethernet tx_clk & rx_clk*/
++ writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK)
++ | ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl);
++
++ break;
++ default:
++ break;
++ }
++}
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/lowlevel.S u-boot/arch/arm/cpu/armv7/stv0991/lowlevel.S
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/lowlevel.S 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/stv0991/lowlevel.S 2015-01-01 17:34:32.025506990 +0100
+@@ -0,0 +1,12 @@
++/*
++ * (C) Copyright 2014 stmicroelectronics
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <config.h>
++#include <linux/linkage.h>
++
++ENTRY(lowlevel_init)
++ mov pc, lr
++ENDPROC(lowlevel_init)
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/Makefile u-boot/arch/arm/cpu/armv7/stv0991/Makefile
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/stv0991/Makefile 2015-01-01 17:34:32.025506990 +0100
+@@ -0,0 +1,9 @@
++#
++# (C) Copyright 2014
++# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y := timer.o clock.o pinmux.o reset.o
++obj-y += lowlevel.o
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/pinmux.c u-boot/arch/arm/cpu/armv7/stv0991/pinmux.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/pinmux.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/stv0991/pinmux.c 2015-01-01 17:34:32.025506990 +0100
+@@ -0,0 +1,62 @@
++/*
++ * (C) Copyright 2014
++ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <asm/io.h>
++#include <asm/arch/stv0991_creg.h>
++#include <asm/arch/stv0991_periph.h>
++#include <asm/arch/hardware.h>
++
++static struct stv0991_creg *const stv0991_creg = \
++ (struct stv0991_creg *)CREG_BASE_ADDR;
++
++int stv0991_pinmux_config(int peripheral)
++{
++ switch (peripheral) {
++ case UART_GPIOC_30_31:
++ /* SSDA/SSCL pad muxing to UART Rx/Dx */
++ writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) |
++ CFG_GPIOC_31_UART_RX,
++ &stv0991_creg->mux12);
++ writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) |
++ CFG_GPIOC_30_UART_TX,
++ &stv0991_creg->mux12);
++ /* SSDA/SSCL pad config to push pull*/
++ writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) |
++ CFG_GPIOC_31_MODE_PP,
++ &stv0991_creg->cfg_pad6);
++ writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) |
++ CFG_GPIOC_30_MODE_HIGH,
++ &stv0991_creg->cfg_pad6);
++ break;
++ case UART_GPIOB_16_17:
++ /* ethernet rx_6/7 to UART Rx/Dx */
++ writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) |
++ CFG_GPIOB_17_UART_RX,
++ &stv0991_creg->mux7);
++ writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) |
++ CFG_GPIOB_16_UART_TX,
++ &stv0991_creg->mux7);
++ break;
++ case ETH_GPIOB_10_31_C_0_4:
++ writel(readl(&stv0991_creg->mux6) & 0x000000FF,
++ &stv0991_creg->mux6);
++ writel(0x00000000, &stv0991_creg->mux7);
++ writel(0x00000000, &stv0991_creg->mux8);
++ writel(readl(&stv0991_creg->mux9) & 0xFFF00000,
++ &stv0991_creg->mux9);
++ /* Ethernet Voltage configuration to 1.8V*/
++ writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
++ ETH_VDD_CFG, &stv0991_creg->vdd_pad1);
++ writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
++ ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1);
++
++ break;
++ default:
++ break;
++ }
++ return 0;
++}
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/reset.c u-boot/arch/arm/cpu/armv7/stv0991/reset.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/reset.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/stv0991/reset.c 2015-01-01 17:34:32.025506990 +0100
+@@ -0,0 +1,26 @@
++/*
++ * (C) Copyright 2014
++ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <asm/arch/stv0991_wdru.h>
++void reset_cpu(ulong ignored)
++{
++ puts("System is going to reboot ...\n");
++ /*
++ * This 1 second delay will allow the above message
++ * to be printed before reset
++ */
++ udelay((1000 * 1000));
++
++ /* Setting bit 1 of the WDRU unit will reset the SoC */
++ writel(WDRU_RST_SYS, &stv0991_wd_ru_ptr->wdru_ctrl1);
++
++ /* system will restart */
++ while (1)
++ ;
++}
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/timer.c u-boot/arch/arm/cpu/armv7/stv0991/timer.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/timer.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/stv0991/timer.c 2015-01-01 17:34:32.025506990 +0100
+@@ -0,0 +1,114 @@
++/*
++ * (C) Copyright 2014
++ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <asm/arch-stv0991/hardware.h>
++#include <asm/arch-stv0991/stv0991_cgu.h>
++#include <asm/arch-stv0991/stv0991_gpt.h>
++
++static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
++ (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
++
++#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
++#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ)
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#define timestamp gd->arch.tbl
++#define lastdec gd->arch.lastinc
++
++int timer_init(void)
++{
++ /* Timer1 clock configuration */
++ writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq);
++ writel(readl(&stv0991_cgu_regs->cgu_enable_2) |
++ TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2);
++
++ /* Stop the timer */
++ writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
++ writel(GPT_PRESCALER_128, &gpt1_regs_ptr->psc);
++ /* Configure timer for auto-reload */
++ writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD,
++ &gpt1_regs_ptr->cr1);
++
++ /* load value for free running */
++ writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr);
++
++ /* start timer */
++ writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN,
++ &gpt1_regs_ptr->cr1);
++
++ /* Reset the timer */
++ lastdec = READ_TIMER();
++ timestamp = 0;
++
++ return 0;
++}
++
++/*
++ * timer without interrupts
++ */
++ulong get_timer(ulong base)
++{
++ return (get_timer_masked() / GPT_RESOLUTION) - base;
++}
++
++void __udelay(unsigned long usec)
++{
++ ulong tmo;
++ ulong start = get_timer_masked();
++ ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100);
++ ulong rndoff;
++
++ rndoff = (usec % 10) ? 1 : 0;
++
++ /* tenudelcnt timer tick gives 10 microsecconds delay */
++ tmo = ((usec / 10) + rndoff) * tenudelcnt;
++
++ while ((ulong) (get_timer_masked() - start) < tmo)
++ ;
++}
++
++ulong get_timer_masked(void)
++{
++ ulong now = READ_TIMER();
++
++ if (now >= lastdec) {
++ /* normal mode */
++ timestamp += now - lastdec;
++ } else {
++ /* we have an overflow ... */
++ timestamp += now + GPT_FREE_RUNNING - lastdec;
++ }
++ lastdec = now;
++
++ return timestamp;
++}
++
++void udelay_masked(unsigned long usec)
++{
++ return udelay(usec);
++}
++
++/*
++ * This function is derived from PowerPC code (read timebase as long long).
++ * On ARM it just returns the timer value.
++ */
++unsigned long long get_ticks(void)
++{
++ return get_timer(0);
++}
++
++/*
++ * This function is derived from PowerPC code (timebase clock frequency).
++ * On ARM it returns the number of timer ticks per second.
++ */
++ulong get_tbclk(void)
++{
++ return CONFIG_STV0991_HZ;
++}
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/tegra124/Kconfig u-boot/arch/arm/cpu/armv7/tegra124/Kconfig
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/tegra124/Kconfig 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/tegra124/Kconfig 2015-01-01 17:34:32.025506990 +0100
+@@ -6,6 +6,15 @@
+ config TARGET_JETSON_TK1
+ bool "NVIDIA Tegra124 Jetson TK1 board"
+
++config TARGET_NYAN_BIG
++ bool "Google/NVIDIA Nyan-big Chrombook"
++ help
++ Nyan Big is a Tegra124 clamshell board that is very similar
++ to venice2, but it has a different panel, the sdcard CD and WP
++ sense are flipped, and it has a different revision of the AS3722
++ PMIC. The retail name is the Acer Chromebook 13 CB5-311-T7NN
++ (13.3-inch HD, NVIDIA Tegra K1, 2GB).
++
+ config TARGET_VENICE2
+ bool "NVIDIA Tegra124 Venice2"
+
+@@ -15,6 +24,7 @@
+ default "tegra124"
+
+ source "board/nvidia/jetson-tk1/Kconfig"
++source "board/nvidia/nyan-big/Kconfig"
+ source "board/nvidia/venice2/Kconfig"
+
+ endif
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/uniphier/init_page_table.c u-boot/arch/arm/cpu/armv7/uniphier/init_page_table.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/uniphier/init_page_table.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/uniphier/init_page_table.c 2015-01-01 17:34:32.029506924 +0100
+@@ -17,11 +17,7 @@
+ #define REG DEVICE /* IO Register: Device */
+ #define DDR DEVICE /* DDR SDRAM: Device */
+
+-#ifdef CONFIG_SPL_BUILD
+ #define IS_SPL_TEXT_AREA(x) ((x) == ((CONFIG_SPL_TEXT_BASE) >> 20))
+-#else
+-#define IS_SPL_TEXT_AREA(x) ((x) == ((CONFIG_SYS_TEXT_BASE) >> 20))
+-#endif
+
+ #define IS_INIT_STACK_AREA(x) ((x) == ((CONFIG_SYS_INIT_SP_ADDR) >> 20))
+
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/vf610/generic.c u-boot/arch/arm/cpu/armv7/vf610/generic.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/armv7/vf610/generic.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/cpu/armv7/vf610/generic.c 2015-01-01 17:34:32.029506924 +0100
+@@ -265,20 +265,21 @@
+
+ cause = readl(&src_regs->srsr);
+ writel(cause, &src_regs->srsr);
+- cause &= 0xff;
+
+- switch (cause) {
+- case 0x08:
+- return "WDOG";
+- case 0x20:
++ if (cause & SRC_SRSR_POR_RST)
++ return "POWER ON RESET";
++ else if (cause & SRC_SRSR_WDOG_A5)
++ return "WDOG A5";
++ else if (cause & SRC_SRSR_WDOG_M4)
++ return "WDOG M4";
++ else if (cause & SRC_SRSR_JTAG_RST)
+ return "JTAG HIGH-Z";
+- case 0x80:
++ else if (cause & SRC_SRSR_SW_RST)
++ return "SW RESET";
++ else if (cause & SRC_SRSR_RESETB)
+ return "EXTERNAL RESET";
+- case 0xfd:
+- return "POR";
+- default:
++ else
+ return "unknown reset";
+- }
+ }
+
+ int print_cpuinfo(void)
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/tegra20-common/pmu.c u-boot/arch/arm/cpu/tegra20-common/pmu.c
+--- u-boot-2015.01-rc3/arch/arm/cpu/tegra20-common/pmu.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/cpu/tegra20-common/pmu.c 2015-01-01 17:34:32.037506793 +0100
+@@ -6,6 +6,7 @@
+ */
+
+ #include <common.h>
++#include <i2c.h>
+ #include <tps6586x.h>
+ #include <asm/io.h>
+ #include <asm/arch/tegra.h>
+@@ -23,9 +24,13 @@
+ #define VDD_TRANSITION_STEP 0x06 /* 150mv */
+ #define VDD_TRANSITION_RATE 0x06 /* 3.52mv/us */
+
++#define PMI_I2C_ADDRESS 0x34 /* chip requires this address */
++
+ int pmu_set_nominal(void)
+ {
+- int core, cpu, bus;
++ struct udevice *bus, *dev;
++ int core, cpu;
++ int ret;
+
+ /* by default, the table has been filled with T25 settings */
+ switch (tegra_get_chip_sku()) {
+@@ -42,12 +47,18 @@
+ return -1;
+ }
+
+- bus = tegra_i2c_get_dvc_bus_num();
+- if (bus == -1) {
++ ret = tegra_i2c_get_dvc_bus(&bus);
++ if (ret) {
+ debug("%s: Cannot find DVC I2C bus\n", __func__);
+- return -1;
++ return ret;
+ }
+- tps6586x_init(bus);
++ ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, &dev);
++ if (ret) {
++ debug("%s: Cannot find DVC I2C chip\n", __func__);
++ return ret;
++ }
++
++ tps6586x_init(dev);
+ tps6586x_set_pwm_mode(TPS6586X_PWM_SM1);
+ return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP,
+ VDD_TRANSITION_RATE, VDD_RELATION);
+diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/u-boot-spl.lds u-boot/arch/arm/cpu/u-boot-spl.lds
+--- u-boot-2015.01-rc3/arch/arm/cpu/u-boot-spl.lds 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/cpu/u-boot-spl.lds 2015-01-01 17:34:32.037506793 +0100
+@@ -32,6 +32,9 @@
+ }
+
+ . = ALIGN(4);
++ .u_boot_list : {
++ KEEP(*(SORT(.u_boot_list*_i2c_*)));
++ }
+
+ . = .;
+ #ifdef CONFIG_SPL_DM
+diff -ruN u-boot-2015.01-rc3/arch/arm/dts/cros-ec-keyboard.dtsi u-boot/arch/arm/dts/cros-ec-keyboard.dtsi
+--- u-boot-2015.01-rc3/arch/arm/dts/cros-ec-keyboard.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/dts/cros-ec-keyboard.dtsi 2015-01-01 17:34:32.037506793 +0100
+@@ -0,0 +1,105 @@
++/*
++ * Keyboard dts fragment for devices that use cros-ec-keyboard
++ *
++ * Copyright (c) 2014 Google, Inc
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++#include <dt-bindings/input/input.h>
++
++&cros_ec {
++ keyboard-controller {
++ compatible = "google,cros-ec-keyb";
++ keypad,num-rows = <8>;
++ keypad,num-columns = <13>;
++ google,needs-ghost-filter;
++
++ linux,keymap = <
++ MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
++ MATRIX_KEY(0x00, 0x02, KEY_F1)
++ MATRIX_KEY(0x00, 0x03, KEY_B)
++ MATRIX_KEY(0x00, 0x04, KEY_F10)
++ MATRIX_KEY(0x00, 0x06, KEY_N)
++ MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
++ MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
++
++ MATRIX_KEY(0x01, 0x01, KEY_ESC)
++ MATRIX_KEY(0x01, 0x02, KEY_F4)
++ MATRIX_KEY(0x01, 0x03, KEY_G)
++ MATRIX_KEY(0x01, 0x04, KEY_F7)
++ MATRIX_KEY(0x01, 0x06, KEY_H)
++ MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
++ MATRIX_KEY(0x01, 0x09, KEY_F9)
++ MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
++
++ MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
++ MATRIX_KEY(0x02, 0x01, KEY_TAB)
++ MATRIX_KEY(0x02, 0x02, KEY_F3)
++ MATRIX_KEY(0x02, 0x03, KEY_T)
++ MATRIX_KEY(0x02, 0x04, KEY_F6)
++ MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
++ MATRIX_KEY(0x02, 0x06, KEY_Y)
++ MATRIX_KEY(0x02, 0x07, KEY_102ND)
++ MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
++ MATRIX_KEY(0x02, 0x09, KEY_F8)
++
++ MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
++ MATRIX_KEY(0x03, 0x02, KEY_F2)
++ MATRIX_KEY(0x03, 0x03, KEY_5)
++ MATRIX_KEY(0x03, 0x04, KEY_F5)
++ MATRIX_KEY(0x03, 0x06, KEY_6)
++ MATRIX_KEY(0x03, 0x08, KEY_MINUS)
++ MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
++
++ MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
++ MATRIX_KEY(0x04, 0x01, KEY_A)
++ MATRIX_KEY(0x04, 0x02, KEY_D)
++ MATRIX_KEY(0x04, 0x03, KEY_F)
++ MATRIX_KEY(0x04, 0x04, KEY_S)
++ MATRIX_KEY(0x04, 0x05, KEY_K)
++ MATRIX_KEY(0x04, 0x06, KEY_J)
++ MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
++ MATRIX_KEY(0x04, 0x09, KEY_L)
++ MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
++ MATRIX_KEY(0x04, 0x0b, KEY_ENTER)
++
++ MATRIX_KEY(0x05, 0x01, KEY_Z)
++ MATRIX_KEY(0x05, 0x02, KEY_C)
++ MATRIX_KEY(0x05, 0x03, KEY_V)
++ MATRIX_KEY(0x05, 0x04, KEY_X)
++ MATRIX_KEY(0x05, 0x05, KEY_COMMA)
++ MATRIX_KEY(0x05, 0x06, KEY_M)
++ MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
++ MATRIX_KEY(0x05, 0x08, KEY_SLASH)
++ MATRIX_KEY(0x05, 0x09, KEY_DOT)
++ MATRIX_KEY(0x05, 0x0b, KEY_SPACE)
++
++ MATRIX_KEY(0x06, 0x01, KEY_1)
++ MATRIX_KEY(0x06, 0x02, KEY_3)
++ MATRIX_KEY(0x06, 0x03, KEY_4)
++ MATRIX_KEY(0x06, 0x04, KEY_2)
++ MATRIX_KEY(0x06, 0x05, KEY_8)
++ MATRIX_KEY(0x06, 0x06, KEY_7)
++ MATRIX_KEY(0x06, 0x08, KEY_0)
++ MATRIX_KEY(0x06, 0x09, KEY_9)
++ MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
++ MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
++ MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)
++
++ MATRIX_KEY(0x07, 0x01, KEY_Q)
++ MATRIX_KEY(0x07, 0x02, KEY_E)
++ MATRIX_KEY(0x07, 0x03, KEY_R)
++ MATRIX_KEY(0x07, 0x04, KEY_W)
++ MATRIX_KEY(0x07, 0x05, KEY_I)
++ MATRIX_KEY(0x07, 0x06, KEY_U)
++ MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
++ MATRIX_KEY(0x07, 0x08, KEY_P)
++ MATRIX_KEY(0x07, 0x09, KEY_O)
++ MATRIX_KEY(0x07, 0x0b, KEY_UP)
++ MATRIX_KEY(0x07, 0x0c, KEY_LEFT)
++ >;
++ };
++};
+diff -ruN u-boot-2015.01-rc3/arch/arm/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h u-boot/arch/arm/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h
+diff -ruN u-boot-2015.01-rc3/arch/arm/dts/include/dt-bindings/reset/altr,rst-mgr.h u-boot/arch/arm/dts/include/dt-bindings/reset/altr,rst-mgr.h
+diff -ruN u-boot-2015.01-rc3/arch/arm/dts/Makefile u-boot/arch/arm/dts/Makefile
+--- u-boot-2015.01-rc3/arch/arm/dts/Makefile 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/dts/Makefile 2015-01-01 17:34:32.037506793 +0100
+@@ -31,6 +31,7 @@
+ tegra30-tec-ng.dtb \
+ tegra114-dalmore.dtb \
+ tegra124-jetson-tk1.dtb \
++ tegra124-nyan-big.dtb \
+ tegra124-venice2.dtb
+ dtb-$(CONFIG_ARCH_UNIPHIER) += \
+ uniphier-ph1-sld3-ref.dtb \
+diff -ruN u-boot-2015.01-rc3/arch/arm/dts/socfpga_cyclone5.dtsi u-boot/arch/arm/dts/socfpga_cyclone5.dtsi
+--- u-boot-2015.01-rc3/arch/arm/dts/socfpga_cyclone5.dtsi 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/dts/socfpga_cyclone5.dtsi 2015-01-01 17:34:32.041506727 +0100
+@@ -1,18 +1,7 @@
+ /*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+ /dts-v1/;
+diff -ruN u-boot-2015.01-rc3/arch/arm/dts/socfpga_cyclone5_socrates.dts u-boot/arch/arm/dts/socfpga_cyclone5_socrates.dts
+--- u-boot-2015.01-rc3/arch/arm/dts/socfpga_cyclone5_socrates.dts 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/dts/socfpga_cyclone5_socrates.dts 2015-01-01 17:34:32.041506727 +0100
+@@ -1,18 +1,7 @@
+ /*
+ * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+ #include "socfpga_cyclone5.dtsi"
+@@ -25,6 +14,12 @@
+ bootargs = "console=ttyS0,115200";
+ };
+
++ aliases {
++ spi0 = "/spi@ff705000"; /* QSPI */
++ spi1 = "/spi@fff00000";
++ spi2 = "/spi@fff01000";
++ };
++
+ memory {
+ name = "memory";
+ device_type = "memory";
+@@ -48,3 +43,23 @@
+ &mmc {
+ status = "okay";
+ };
++
++&qspi {
++ status = "okay";
++
++ flash0: n25q00@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "n25q00";
++ reg = <0>; /* chip select */
++ spi-max-frequency = <50000000>;
++ m25p,fast-read;
++ page-size = <256>;
++ block-size = <16>; /* 2^16, 64KB */
++ read-delay = <4>; /* delay value in read data capture register */
++ tshsl-ns = <50>;
++ tsd2d-ns = <50>;
++ tchsh-ns = <4>;
++ tslch-ns = <4>;
++ };
++};
+diff -ruN u-boot-2015.01-rc3/arch/arm/dts/socfpga.dtsi u-boot/arch/arm/dts/socfpga.dtsi
+--- u-boot-2015.01-rc3/arch/arm/dts/socfpga.dtsi 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/dts/socfpga.dtsi 2015-01-01 17:34:32.041506727 +0100
+@@ -1,18 +1,7 @@
+ /*
+ * Copyright (C) 2012 Altera <www.altera.com>
+ *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+ #include "skeleton.dtsi"
+@@ -639,6 +628,49 @@
+ clock-names = "biu", "ciu";
+ };
+
++ qspi: spi@ff705000 {
++ compatible = "cadence,qspi";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0xff705000 0x1000>,
++ <0xffa00000 0x1000>;
++ interrupts = <0 151 4>;
++ clocks = <&qspi_clk>;
++ ext-decoder = <0>; /* external decoder */
++ num-chipselect = <4>;
++ fifo-depth = <128>;
++ bus-num = <2>;
++ status = "disabled";
++ };
++
++ spi0: spi@fff00000 {
++ compatible = "snps,dw-spi-mmio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0xfff00000 0x1000>;
++ interrupts = <0 154 4>;
++ num-chipselect = <4>;
++ bus-num = <0>;
++ tx-dma-channel = <&pdma 16>;
++ rx-dma-channel = <&pdma 17>;
++ clocks = <&per_base_clk>;
++ status = "disabled";
++ };
++
++ spi1: spi@fff01000 {
++ compatible = "snps,dw-spi-mmio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0xfff01000 0x1000>;
++ interrupts = <0 156 4>;
++ num-chipselect = <4>;
++ bus-num = <1>;
++ tx-dma-channel = <&pdma 20>;
++ rx-dma-channel = <&pdma 21>;
++ clocks = <&per_base_clk>;
++ status = "disabled";
++ };
++
+ /* Local timer */
+ timer@fffec600 {
+ compatible = "arm,cortex-a9-twd-timer";
+diff -ruN u-boot-2015.01-rc3/arch/arm/dts/tegra124.dtsi u-boot/arch/arm/dts/tegra124.dtsi
+--- u-boot-2015.01-rc3/arch/arm/dts/tegra124.dtsi 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/dts/tegra124.dtsi 2015-01-01 17:34:32.041506727 +0100
+@@ -1,5 +1,6 @@
+ #include <dt-bindings/clock/tegra124-car.h>
+ #include <dt-bindings/gpio/tegra-gpio.h>
++#include <dt-bindings/pinctrl/pinctrl-tegra.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ #include "skeleton.dtsi"
+@@ -192,6 +193,16 @@
+ status = "disabled";
+ };
+
++ pwm: pwm@7000a000 {
++ compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
++ reg = <0x7000a000 0x100>;
++ #pwm-cells = <2>;
++ clocks = <&tegra_car TEGRA124_CLK_PWM>;
++ resets = <&tegra_car 17>;
++ reset-names = "pwm";
++ status = "disabled";
++ };
++
+ spi@7000d400 {
+ compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+ reg = <0x7000d400 0x200>;
+@@ -290,6 +301,109 @@
+ status = "disabled";
+ };
+
++ ahub@70300000 {
++ compatible = "nvidia,tegra124-ahub";
++ reg = <0x70300000 0x200>,
++ <0x70300800 0x800>,
++ <0x70300200 0x600>;
++ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
++ <&tegra_car TEGRA124_CLK_APBIF>;
++ clock-names = "d_audio", "apbif";
++ resets = <&tegra_car 106>, /* d_audio */
++ <&tegra_car 107>, /* apbif */
++ <&tegra_car 30>, /* i2s0 */
++ <&tegra_car 11>, /* i2s1 */
++ <&tegra_car 18>, /* i2s2 */
++ <&tegra_car 101>, /* i2s3 */
++ <&tegra_car 102>, /* i2s4 */
++ <&tegra_car 108>, /* dam0 */
++ <&tegra_car 109>, /* dam1 */
++ <&tegra_car 110>, /* dam2 */
++ <&tegra_car 10>, /* spdif */
++ <&tegra_car 153>, /* amx */
++ <&tegra_car 185>, /* amx1 */
++ <&tegra_car 154>, /* adx */
++ <&tegra_car 180>, /* adx1 */
++ <&tegra_car 186>, /* afc0 */
++ <&tegra_car 187>, /* afc1 */
++ <&tegra_car 188>, /* afc2 */
++ <&tegra_car 189>, /* afc3 */
++ <&tegra_car 190>, /* afc4 */
++ <&tegra_car 191>; /* afc5 */
++ reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
++ "i2s3", "i2s4", "dam0", "dam1", "dam2",
++ "spdif", "amx", "amx1", "adx", "adx1",
++ "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
++ dmas = <&apbdma 1>, <&apbdma 1>,
++ <&apbdma 2>, <&apbdma 2>,
++ <&apbdma 3>, <&apbdma 3>,
++ <&apbdma 4>, <&apbdma 4>,
++ <&apbdma 6>, <&apbdma 6>,
++ <&apbdma 7>, <&apbdma 7>,
++ <&apbdma 12>, <&apbdma 12>,
++ <&apbdma 13>, <&apbdma 13>,
++ <&apbdma 14>, <&apbdma 14>,
++ <&apbdma 29>, <&apbdma 29>;
++ dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
++ "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
++ "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
++ "rx9", "tx9";
++ ranges;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ tegra_i2s0: i2s@70301000 {
++ compatible = "nvidia,tegra124-i2s";
++ reg = <0x70301000 0x100>;
++ nvidia,ahub-cif-ids = <4 4>;
++ clocks = <&tegra_car TEGRA124_CLK_I2S0>;
++ resets = <&tegra_car 30>;
++ reset-names = "i2s";
++ status = "disabled";
++ };
++
++ tegra_i2s1: i2s@70301100 {
++ compatible = "nvidia,tegra124-i2s";
++ reg = <0x70301100 0x100>;
++ nvidia,ahub-cif-ids = <5 5>;
++ clocks = <&tegra_car TEGRA124_CLK_I2S1>;
++ resets = <&tegra_car 11>;
++ reset-names = "i2s";
++ status = "disabled";
++ };
++
++ tegra_i2s2: i2s@70301200 {
++ compatible = "nvidia,tegra124-i2s";
++ reg = <0x70301200 0x100>;
++ nvidia,ahub-cif-ids = <6 6>;
++ clocks = <&tegra_car TEGRA124_CLK_I2S2>;
++ resets = <&tegra_car 18>;
++ reset-names = "i2s";
++ status = "disabled";
++ };
++
++ tegra_i2s3: i2s@70301300 {
++ compatible = "nvidia,tegra124-i2s";
++ reg = <0x70301300 0x100>;
++ nvidia,ahub-cif-ids = <7 7>;
++ clocks = <&tegra_car TEGRA124_CLK_I2S3>;
++ resets = <&tegra_car 101>;
++ reset-names = "i2s";
++ status = "disabled";
++ };
++
++ tegra_i2s4: i2s@70301400 {
++ compatible = "nvidia,tegra124-i2s";
++ reg = <0x70301400 0x100>;
++ nvidia,ahub-cif-ids = <8 8>;
++ clocks = <&tegra_car TEGRA124_CLK_I2S4>;
++ resets = <&tegra_car 102>;
++ reset-names = "i2s";
++ status = "disabled";
++ };
++ };
++
+ usb@7d000000 {
+ compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+ reg = <0x7d000000 0x4000>;
+diff -ruN u-boot-2015.01-rc3/arch/arm/dts/tegra124-jetson-tk1.dts u-boot/arch/arm/dts/tegra124-jetson-tk1.dts
+--- u-boot-2015.01-rc3/arch/arm/dts/tegra124-jetson-tk1.dts 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/dts/tegra124-jetson-tk1.dts 2015-01-01 17:34:32.041506727 +0100
+@@ -16,7 +16,6 @@
+ i2c2 = "/i2c@7000c400";
+ i2c3 = "/i2c@7000c500";
+ i2c4 = "/i2c@7000c700";
+- i2c5 = "/i2c@7000d100";
+ sdhci0 = "/sdhci@700b0600";
+ sdhci1 = "/sdhci@700b0400";
+ spi0 = "/spi@7000d400";
+diff -ruN u-boot-2015.01-rc3/arch/arm/dts/tegra124-nyan-big.dts u-boot/arch/arm/dts/tegra124-nyan-big.dts
+--- u-boot-2015.01-rc3/arch/arm/dts/tegra124-nyan-big.dts 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/dts/tegra124-nyan-big.dts 2015-01-01 17:34:32.041506727 +0100
+@@ -0,0 +1,365 @@
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include "tegra124.dtsi"
++
++/ {
++ model = "Acer Chromebook 13 CB5-311";
++ compatible = "google,nyan-big", "nvidia,tegra124";
++
++ aliases {
++ console = &uarta;
++ i2c0 = "/i2c@7000d000";
++ i2c1 = "/i2c@7000c000";
++ i2c2 = "/i2c@7000c400";
++ i2c3 = "/i2c@7000c500";
++ i2c4 = "/i2c@7000c700";
++ i2c5 = "/i2c@7000d100";
++ rtc0 = "/i2c@0,7000d000/pmic@40";
++ rtc1 = "/rtc@0,7000e000";
++ sdhci0 = "/sdhci@700b0600";
++ sdhci1 = "/sdhci@700b0400";
++ spi0 = "/spi@7000d400";
++ spi1 = "/spi@7000da00";
++ usb0 = "/usb@7d000000";
++ usb1 = "/usb@7d008000";
++ };
++
++ memory {
++ reg = <0x80000000 0x80000000>;
++ };
++
++ serial@70006000 {
++ /* Debug connector on the bottom of the board near SD card. */
++ status = "okay";
++ };
++
++ pwm@7000a000 {
++ status = "okay";
++ };
++
++ i2c@7000c000 {
++ status = "okay";
++ clock-frequency = <100000>;
++
++ acodec: audio-codec@10 {
++ compatible = "maxim,max98090";
++ reg = <0x10>;
++ interrupt-parent = <&gpio>;
++ interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
++ };
++
++ temperature-sensor@4c {
++ compatible = "ti,tmp451";
++ reg = <0x4c>;
++ interrupt-parent = <&gpio>;
++ interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
++
++ #thermal-sensor-cells = <1>;
++ };
++ };
++
++ i2c@7000c400 {
++ status = "okay";
++ clock-frequency = <100000>;
++ };
++
++ i2c@7000c500 {
++ status = "okay";
++ clock-frequency = <400000>;
++
++ tpm@20 {
++ compatible = "infineon,slb9645tt";
++ reg = <0x20>;
++ };
++ };
++
++ hdmi_ddc: i2c@7000c700 {
++ status = "okay";
++ clock-frequency = <100000>;
++ };
++
++ i2c@7000d000 {
++ status = "okay";
++ clock-frequency = <400000>;
++
++ pmic: pmic@40 {
++ compatible = "ams,as3722";
++ reg = <0x40>;
++ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
++
++ ams,system-power-controller;
++
++ #interrupt-cells = <2>;
++ interrupt-controller;
++
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ pinctrl-names = "default";
++ pinctrl-0 = <&as3722_default>;
++
++ as3722_default: pinmux {
++ gpio0 {
++ pins = "gpio0";
++ function = "gpio";
++ bias-pull-down;
++ };
++
++ gpio1 {
++ pins = "gpio1";
++ function = "gpio";
++ bias-pull-up;
++ };
++
++ gpio2_4_7 {
++ pins = "gpio2", "gpio4", "gpio7";
++ function = "gpio";
++ bias-pull-up;
++ };
++
++ gpio3_6 {
++ pins = "gpio3", "gpio6";
++ bias-high-impedance;
++ };
++
++ gpio5 {
++ pins = "gpio5";
++ function = "clk32k-out";
++ bias-pull-down;
++ };
++ };
++ };
++ };
++
++ spi@7000d400 {
++ status = "okay";
++
++ cros_ec: cros-ec@0 {
++ compatible = "google,cros-ec-spi";
++ spi-max-frequency = <3000000>;
++ interrupt-parent = <&gpio>;
++ interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
++ reg = <0>;
++
++ google,cros-ec-spi-msg-delay = <2000>;
++
++ i2c-tunnel {
++ compatible = "google,cros-ec-i2c-tunnel";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ google,remote-bus = <0>;
++
++ charger: bq24735@9 {
++ compatible = "ti,bq24735";
++ reg = <0x9>;
++ interrupt-parent = <&gpio>;
++ interrupts = <TEGRA_GPIO(J, 0)
++ GPIO_ACTIVE_HIGH>;
++ ti,ac-detect-gpios = <&gpio
++ TEGRA_GPIO(J, 0)
++ GPIO_ACTIVE_HIGH>;
++ };
++
++ battery: sbs-battery@b {
++ compatible = "sbs,sbs-battery";
++ reg = <0xb>;
++ sbs,i2c-retry-count = <2>;
++ sbs,poll-retry-count = <10>;
++ power-supplies = <&charger>;
++ };
++ };
++ };
++ };
++
++ spi@7000da00 {
++ status = "okay";
++ spi-max-frequency = <25000000>;
++
++ flash@0 {
++ compatible = "winbond,w25q32dw";
++ reg = <0>;
++ };
++ };
++
++ pmc@7000e400 {
++ nvidia,invert-interrupt;
++ nvidia,suspend-mode = <0>;
++ nvidia,cpu-pwr-good-time = <500>;
++ nvidia,cpu-pwr-off-time = <300>;
++ nvidia,core-pwr-good-time = <641 3845>;
++ nvidia,core-pwr-off-time = <61036>;
++ nvidia,core-power-req-active-high;
++ nvidia,sys-clock-req-active-high;
++ };
++
++ hda@70030000 {
++ status = "okay";
++ };
++
++ sdhci@700b0000 { /* WiFi/BT on this bus */
++ status = "okay";
++ power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
++ bus-width = <4>;
++ no-1-8-v;
++ non-removable;
++ };
++
++ sdhci@700b0400 { /* SD Card on this bus */
++ status = "okay";
++ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
++ power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
++ wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
++ bus-width = <4>;
++ no-1-8-v;
++ };
++
++ sdhci@700b0600 { /* eMMC on this bus */
++ status = "okay";
++ bus-width = <8>;
++ no-1-8-v;
++ non-removable;
++ };
++
++ ahub@70300000 {
++ i2s@70301100 {
++ status = "okay";
++ };
++ };
++
++ usb@7d000000 { /* Rear external USB port. */
++ status = "okay";
++ };
++
++ usb-phy@7d000000 {
++ status = "okay";
++ };
++
++ usb@7d004000 { /* Internal webcam. */
++ status = "okay";
++ };
++
++ usb-phy@7d004000 {
++ status = "okay";
++ };
++
++ usb@7d008000 { /* Left external USB port. */
++ status = "okay";
++ };
++
++ usb-phy@7d008000 {
++ status = "okay";
++ };
++
++ backlight: backlight {
++ compatible = "pwm-backlight";
++
++ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
++ pwms = <&pwm 1 1000000>;
++
++ default-brightness-level = <224>;
++ brightness-levels =
++ < 0 1 2 3 4 5 6 7
++ 8 9 10 11 12 13 14 15
++ 16 17 18 19 20 21 22 23
++ 24 25 26 27 28 29 30 31
++ 32 33 34 35 36 37 38 39
++ 40 41 42 43 44 45 46 47
++ 48 49 50 51 52 53 54 55
++ 56 57 58 59 60 61 62 63
++ 64 65 66 67 68 69 70 71
++ 72 73 74 75 76 77 78 79
++ 80 81 82 83 84 85 86 87
++ 88 89 90 91 92 93 94 95
++ 96 97 98 99 100 101 102 103
++ 104 105 106 107 108 109 110 111
++ 112 113 114 115 116 117 118 119
++ 120 121 122 123 124 125 126 127
++ 128 129 130 131 132 133 134 135
++ 136 137 138 139 140 141 142 143
++ 144 145 146 147 148 149 150 151
++ 152 153 154 155 156 157 158 159
++ 160 161 162 163 164 165 166 167
++ 168 169 170 171 172 173 174 175
++ 176 177 178 179 180 181 182 183
++ 184 185 186 187 188 189 190 191
++ 192 193 194 195 196 197 198 199
++ 200 201 202 203 204 205 206 207
++ 208 209 210 211 212 213 214 215
++ 216 217 218 219 220 221 222 223
++ 224 225 226 227 228 229 230 231
++ 232 233 234 235 236 237 238 239
++ 240 241 242 243 244 245 246 247
++ 248 249 250 251 252 253 254 255
++ 256>;
++ };
++
++ clocks {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ clk32k_in: clock@0 {
++ compatible = "fixed-clock";
++ reg = <0>;
++ #clock-cells = <0>;
++ clock-frequency = <32768>;
++ };
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++
++ lid {
++ label = "Lid";
++ gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
++ linux,input-type = <5>;
++ linux,code = <KEY_RESERVED>;
++ debounce-interval = <1>;
++ gpio-key,wakeup;
++ };
++
++ power {
++ label = "Power";
++ gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_POWER>;
++ debounce-interval = <30>;
++ gpio-key,wakeup;
++ };
++ };
++
++ panel: panel {
++ compatible = "auo,b133xtn01";
++
++ backlight = <&backlight>;
++ };
++
++ sound {
++ compatible = "nvidia,tegra-audio-max98090-nyan-big",
++ "nvidia,tegra-audio-max98090";
++ nvidia,model = "Acer Chromebook 13";
++
++ nvidia,audio-routing =
++ "Headphones", "HPR",
++ "Headphones", "HPL",
++ "Speakers", "SPKR",
++ "Speakers", "SPKL",
++ "Mic Jack", "MICBIAS",
++ "DMICL", "Int Mic",
++ "DMICR", "Int Mic",
++ "IN34", "Mic Jack";
++
++ nvidia,i2s-controller = <&tegra_i2s1>;
++ nvidia,audio-codec = <&acodec>;
++
++ clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
++ <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
++ <&tegra_car TEGRA124_CLK_EXTERN1>;
++ clock-names = "pll_a", "pll_a_out0", "mclk";
++
++ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
++ };
++};
++
++#include "cros-ec-keyboard.dtsi"
+diff -ruN u-boot-2015.01-rc3/arch/arm/dts/tegra30-tec-ng.dts u-boot/arch/arm/dts/tegra30-tec-ng.dts
+--- u-boot-2015.01-rc3/arch/arm/dts/tegra30-tec-ng.dts 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/dts/tegra30-tec-ng.dts 2015-01-01 17:34:32.045506662 +0100
+@@ -6,6 +6,10 @@
+ model = "Avionic Design Tamonten™ NG Evaluation Carrier";
+ compatible = "ad,tec-ng", "nvidia,tegra30";
+
++ aliases {
++ i2c0 = "/i2c@7000c400";
++ };
++
+ /* GEN2 */
+ i2c@7000c400 {
+ status = "okay";
+diff -ruN u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-ld4-ref.dts u-boot/arch/arm/dts/uniphier-ph1-ld4-ref.dts
+--- u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-ld4-ref.dts 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/dts/uniphier-ph1-ld4-ref.dts 2015-01-01 17:34:32.045506662 +0100
+@@ -25,10 +25,10 @@
+ };
+
+ aliases {
+- uart0 = &uart0;
+- uart1 = &uart1;
+- uart2 = &uart2;
+- uart3 = &uart3;
++ serial0 = &uart0;
++ serial1 = &uart1;
++ serial2 = &uart2;
++ serial3 = &uart3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+diff -ruN u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-pro4-ref.dts u-boot/arch/arm/dts/uniphier-ph1-pro4-ref.dts
+--- u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-pro4-ref.dts 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/dts/uniphier-ph1-pro4-ref.dts 2015-01-01 17:34:32.045506662 +0100
+@@ -25,10 +25,10 @@
+ };
+
+ aliases {
+- uart0 = &uart0;
+- uart1 = &uart1;
+- uart2 = &uart2;
+- uart3 = &uart3;
++ serial0 = &uart0;
++ serial1 = &uart1;
++ serial2 = &uart2;
++ serial3 = &uart3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+diff -ruN u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-sld3-ref.dts u-boot/arch/arm/dts/uniphier-ph1-sld3-ref.dts
+--- u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-sld3-ref.dts 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/dts/uniphier-ph1-sld3-ref.dts 2015-01-01 17:34:32.045506662 +0100
+@@ -25,9 +25,9 @@
+ };
+
+ aliases {
+- uart0 = &uart0;
+- uart1 = &uart1;
+- uart2 = &uart2;
++ serial0 = &uart0;
++ serial1 = &uart1;
++ serial2 = &uart2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+diff -ruN u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-sld8-ref.dts u-boot/arch/arm/dts/uniphier-ph1-sld8-ref.dts
+--- u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-sld8-ref.dts 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/dts/uniphier-ph1-sld8-ref.dts 2015-01-01 17:34:32.045506662 +0100
+@@ -25,10 +25,10 @@
+ };
+
+ aliases {
+- uart0 = &uart0;
+- uart1 = &uart1;
+- uart2 = &uart2;
+- uart3 = &uart3;
++ serial0 = &uart0;
++ serial1 = &uart1;
++ serial2 = &uart2;
++ serial3 = &uart3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+diff -ruN u-boot-2015.01-rc3/arch/arm/imx-common/cpu.c u-boot/arch/arm/imx-common/cpu.c
+--- u-boot-2015.01-rc3/arch/arm/imx-common/cpu.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/imx-common/cpu.c 2015-01-01 17:34:32.045506662 +0100
+@@ -206,6 +206,9 @@
+ {
+ #if defined(CONFIG_CMD_SATA)
+ sata_stop();
++#if defined(CONFIG_MX6)
++ disable_sata_clock();
++#endif
+ #endif
+ #if defined(CONFIG_VIDEO_IPUV3)
+ /* disable video before launching O/S */
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-bcm281xx/sysmap.h u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-bcm281xx/sysmap.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h 2015-01-01 17:34:32.053506531 +0100
+@@ -13,6 +13,8 @@
+ #define ESUB_CLK_BASE_ADDR 0x38000000
+ #define ESW_CONTRL_BASE_ADDR 0x38200000
+ #define GPIO2_BASE_ADDR 0x35003000
++#define HSOTG_BASE_ADDR 0x3f120000
++#define HSOTG_CTRL_BASE_ADDR 0x3f130000
+ #define KONA_MST_CLK_BASE_ADDR 0x3f001000
+ #define KONA_SLV_CLK_BASE_ADDR 0x3e011000
+ #define PMU_BSC_BASE_ADDR 0x3500d000
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-bcm2835/mbox.h u-boot/arch/arm/include/asm/arch-bcm2835/mbox.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-bcm2835/mbox.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-bcm2835/mbox.h 2015-01-01 17:34:32.053506531 +0100
+@@ -140,6 +140,7 @@
+ #define BCM2835_BOARD_REV_B_REV2_f 0xf
+ #define BCM2835_BOARD_REV_B_PLUS 0x10
+ #define BCM2835_BOARD_REV_CM 0x11
++#define BCM2835_BOARD_REV_A_PLUS 0x12
+
+ struct bcm2835_mbox_tag_get_board_rev {
+ struct bcm2835_mbox_tag_hdr tag_hdr;
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/config.h u-boot/arch/arm/include/asm/arch-ls102xa/config.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/config.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-ls102xa/config.h 2015-01-01 17:34:32.065506333 +0100
+@@ -11,11 +11,17 @@
+
+ #define OCRAM_BASE_ADDR 0x10000000
+ #define OCRAM_SIZE 0x00020000
++#define OCRAM_BASE_S_ADDR 0x10010000
++#define OCRAM_S_SIZE 0x00010000
+
+ #define CONFIG_SYS_IMMR 0x01000000
++#define CONFIG_SYS_DCSRBAR 0x20000000
++
++#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
+
+ #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
+ #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
++#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
+ #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
+ #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
+ #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
+@@ -52,6 +58,9 @@
+
+ #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
+
++#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
++#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
++
+ #ifdef CONFIG_DDR_SPD
+ #define CONFIG_SYS_FSL_DDR_BE
+ #define CONFIG_VERY_BIG_RAM
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h u-boot/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 2015-01-01 17:34:32.065506333 +0100
+@@ -17,6 +17,9 @@
+ #define SOC_VER_LS1021 0x11
+ #define SOC_VER_LS1022 0x12
+
++#define CCSR_BRR_OFFSET 0xe4
++#define CCSR_SCRATCHRW1_OFFSET 0x200
++
+ #define RCWSR0_SYS_PLL_RAT_SHIFT 25
+ #define RCWSR0_SYS_PLL_RAT_MASK 0x1f
+ #define RCWSR0_MEM_PLL_RAT_SHIFT 16
+@@ -29,6 +32,11 @@
+ #define ARCH_TIMER_CTRL_ENABLE (1 << 0)
+ #define SYS_COUNTER_CTRL_ENABLE (1 << 24)
+
++#define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000
++#define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000
++
++#define DCFG_DCSR_PORCR1 0
++
+ struct sys_info {
+ unsigned long freq_processor[CONFIG_MAX_CPUS];
+ unsigned long freq_systembus;
+@@ -98,6 +106,7 @@
+ #define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
+ #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
+ #define SCFG_PIXCLKCR_PXCKEN 0x80000000
++#define SCFG_QSPI_CLKSEL 0xc0100000
+
+ /* Supplemental Configuration Unit */
+ struct ccsr_scfg {
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h 2015-01-01 17:34:32.065506333 +0100
+@@ -0,0 +1,17 @@
++/*
++ * Copyright 2014 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __FSL_LS102XA_STREAM_ID_H_
++#define __FSL_LS102XA_STREAM_ID_H_
++
++struct smmu_stream_id {
++ uint16_t offset;
++ uint16_t stream_id;
++ char dev_name[32];
++};
++
++void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
++#endif
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/ns_access.h u-boot/arch/arm/include/asm/arch-ls102xa/ns_access.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/ns_access.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-ls102xa/ns_access.h 2015-01-01 17:34:32.065506333 +0100
+@@ -0,0 +1,118 @@
++/*
++ * Copyright 2014 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __FSL_NS_ACCESS_H_
++#define __FSL_NS_ACCESS_H_
++
++enum csu_cslx_access {
++ CSU_NS_SUP_R = 0x08,
++ CSU_NS_SUP_W = 0x80,
++ CSU_NS_SUP_RW = 0x88,
++ CSU_NS_USER_R = 0x04,
++ CSU_NS_USER_W = 0x40,
++ CSU_NS_USER_RW = 0x44,
++ CSU_S_SUP_R = 0x02,
++ CSU_S_SUP_W = 0x20,
++ CSU_S_SUP_RW = 0x22,
++ CSU_S_USER_R = 0x01,
++ CSU_S_USER_W = 0x10,
++ CSU_S_USER_RW = 0x11,
++ CSU_ALL_RW = 0xff,
++};
++
++enum csu_cslx_ind {
++ CSU_CSLX_PCIE2_IO = 0,
++ CSU_CSLX_PCIE1_IO,
++ CSU_CSLX_MG2TPR_IP,
++ CSU_CSLX_IFC_MEM,
++ CSU_CSLX_OCRAM,
++ CSU_CSLX_GIC,
++ CSU_CSLX_PCIE1,
++ CSU_CSLX_OCRAM2,
++ CSU_CSLX_QSPI_MEM,
++ CSU_CSLX_PCIE2,
++ CSU_CSLX_SATA,
++ CSU_CSLX_USB3,
++ CSU_CSLX_SERDES = 32,
++ CSU_CSLX_QDMA,
++ CSU_CSLX_LPUART2,
++ CSU_CSLX_LPUART1,
++ CSU_CSLX_LPUART4,
++ CSU_CSLX_LPUART3,
++ CSU_CSLX_LPUART6,
++ CSU_CSLX_LPUART5,
++ CSU_CSLX_DSPI2 = 40,
++ CSU_CSLX_DSPI1,
++ CSU_CSLX_QSPI,
++ CSU_CSLX_ESDHC,
++ CSU_CSLX_2D_ACE,
++ CSU_CSLX_IFC,
++ CSU_CSLX_I2C1,
++ CSU_CSLX_USB2,
++ CSU_CSLX_I2C3,
++ CSU_CSLX_I2C2,
++ CSU_CSLX_DUART2 = 50,
++ CSU_CSLX_DUART1,
++ CSU_CSLX_WDT2,
++ CSU_CSLX_WDT1,
++ CSU_CSLX_EDMA,
++ CSU_CSLX_SYS_CNT,
++ CSU_CSLX_DMA_MUX2,
++ CSU_CSLX_DMA_MUX1,
++ CSU_CSLX_DDR,
++ CSU_CSLX_QUICC,
++ CSU_CSLX_DCFG_CCU_RCPM = 60,
++ CSU_CSLX_SECURE_BOOTROM,
++ CSU_CSLX_SFP,
++ CSU_CSLX_TMU,
++ CSU_CSLX_SECURE_MONITOR,
++ CSU_CSLX_RESERVED0,
++ CSU_CSLX_ETSEC1,
++ CSU_CSLX_SEC5_5,
++ CSU_CSLX_ETSEC3,
++ CSU_CSLX_ETSEC2,
++ CSU_CSLX_GPIO2 = 70,
++ CSU_CSLX_GPIO1,
++ CSU_CSLX_GPIO4,
++ CSU_CSLX_GPIO3,
++ CSU_CSLX_PLATFORM_CONT,
++ CSU_CSLX_CSU,
++ CSU_CSLX_ASRC,
++ CSU_CSLX_SPDIF,
++ CSU_CSLX_FLEXCAN2,
++ CSU_CSLX_FLEXCAN1,
++ CSU_CSLX_FLEXCAN4 = 80,
++ CSU_CSLX_FLEXCAN3,
++ CSU_CSLX_SAI2,
++ CSU_CSLX_SAI1,
++ CSU_CSLX_SAI4,
++ CSU_CSLX_SAI3,
++ CSU_CSLX_FTM2,
++ CSU_CSLX_FTM1,
++ CSU_CSLX_FTM4,
++ CSU_CSLX_FTM3,
++ CSU_CSLX_FTM6 = 90,
++ CSU_CSLX_FTM5,
++ CSU_CSLX_FTM8,
++ CSU_CSLX_FTM7,
++ CSU_CSLX_COP_DCSR,
++ CSU_CSLX_EPU,
++ CSU_CSLX_GDI,
++ CSU_CSLX_DDI,
++ CSU_CSLX_RESERVED1,
++ CSU_CSLX_USB3_PHY = 117,
++ CSU_CSLX_RESERVED2,
++ CSU_CSLX_MAX,
++};
++
++struct csu_ns_dev {
++ unsigned long ind;
++ uint32_t val;
++};
++
++void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num);
++
++#endif
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/spl.h u-boot/arch/arm/include/asm/arch-ls102xa/spl.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/spl.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-ls102xa/spl.h 2015-01-01 17:34:32.065506333 +0100
+@@ -0,0 +1,20 @@
++/*
++ * Copyright 2014 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __ASM_ARCH_SPL_H__
++#define __ASM_ARCH_SPL_H__
++
++#define BOOT_DEVICE_NONE 0
++#define BOOT_DEVICE_XIP 1
++#define BOOT_DEVICE_XIPWAIT 2
++#define BOOT_DEVICE_NAND 3
++#define BOOT_DEVICE_ONENAND 4
++#define BOOT_DEVICE_MMC1 5
++#define BOOT_DEVICE_MMC2 6
++#define BOOT_DEVICE_MMC2_2 7
++#define BOOT_DEVICE_SPI 10
++
++#endif /* __ASM_ARCH_SPL_H__ */
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-mx6/clock.h u-boot/arch/arm/include/asm/arch-mx6/clock.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-mx6/clock.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-mx6/clock.h 2015-01-01 17:34:32.073506203 +0100
+@@ -43,10 +43,10 @@
+ };
+
+ enum enet_freq {
+- ENET_25MHz,
+- ENET_50MHz,
+- ENET_100MHz,
+- ENET_125MHz,
++ ENET_25MHZ,
++ ENET_50MHZ,
++ ENET_100MHZ,
++ ENET_125MHZ,
+ };
+
+ u32 imx_get_uartclk(void);
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-mx6/mx6sl_pins.h u-boot/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-mx6/mx6sl_pins.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-mx6/mx6sl_pins.h 2015-01-01 17:34:32.073506203 +0100
+@@ -53,5 +53,10 @@
+ MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
+ MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
+ MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
++
++ MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0),
++
++ MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0),
++ MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0),
+ };
+ #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/mmc.h u-boot/arch/arm/include/asm/arch-rmobile/mmc.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/mmc.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-rmobile/mmc.h 2015-01-01 17:34:32.085506005 +0100
+@@ -0,0 +1,14 @@
++/*
++ * Renesas SuperH MMCIF driver.
++ *
++ * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
++ * Copyright (C) 2014 Renesas Electronics Corporation
++ *
++ * SPDX-License-Identifier: GPL-2.0
++ */
++#ifndef _RMOBILE_MMC_H_
++#define _RMOBILE_MMC_H_
++
++int mmcif_mmc_init(void);
++
++#endif /* _RMOBILE_MMC_H_ */
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7790.h u-boot/arch/arm/include/asm/arch-rmobile/r8a7790.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7790.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-rmobile/r8a7790.h 2015-01-01 17:34:32.085506005 +0100
+@@ -15,6 +15,19 @@
+ #define CONFIG_SYS_I2C_SH_BASE2 0xE6520000
+ #define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000
+
++/* Module stop control/status register bits */
++#define MSTP0_BITS 0x00640801
++#define MSTP1_BITS 0xDB6E9BDF
++#define MSTP2_BITS 0x300DA1FC
++#define MSTP3_BITS 0xF08CF831
++#define MSTP4_BITS 0x80000184
++#define MSTP5_BITS 0x44C00046
++#define MSTP7_BITS 0x07F30718
++#define MSTP8_BITS 0x01F0FF84
++#define MSTP9_BITS 0xF5979FCF
++#define MSTP10_BITS 0xFFFEFFE0
++#define MSTP11_BITS 0x00000000
++
+ #define R8A7790_CUT_ES2X 2
+ #define IS_R8A7790_ES2() \
+ (rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7791.h u-boot/arch/arm/include/asm/arch-rmobile/r8a7791.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7791.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-rmobile/r8a7791.h 2015-01-01 17:34:32.089505941 +0100
+@@ -51,6 +51,19 @@
+ #define DBSC3_1_QOS_W15_BASE 0xE67A2F00
+ #define DBSC3_1_DBADJ2 0xE67A00C8
+
++/* Module stop control/status register bits */
++#define MSTP0_BITS 0x00640801
++#define MSTP1_BITS 0x9B6C9B5A
++#define MSTP2_BITS 0x100D21FC
++#define MSTP3_BITS 0xF08CD810
++#define MSTP4_BITS 0x800001C4
++#define MSTP5_BITS 0x44C00046
++#define MSTP7_BITS 0x05BFE618
++#define MSTP8_BITS 0x40C0FE85
++#define MSTP9_BITS 0xFF979FFF
++#define MSTP10_BITS 0xFFFEFFE0
++#define MSTP11_BITS 0x000001C0
++
+ #define R8A7791_CUT_ES2X 2
+ #define IS_R8A7791_ES2() \
+ (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7793.h u-boot/arch/arm/include/asm/arch-rmobile/r8a7793.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7793.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-rmobile/r8a7793.h 2015-01-01 17:34:32.089505941 +0100
+@@ -56,6 +56,20 @@
+ /*
+ * R8A7793 I/O Product Information
+ */
++
++/* Module stop control/status register bits */
++#define MSTP0_BITS 0x00640801
++#define MSTP1_BITS 0x9B6C9B5A
++#define MSTP2_BITS 0x100D21FC
++#define MSTP3_BITS 0xF08CD810
++#define MSTP4_BITS 0x800001C4
++#define MSTP5_BITS 0x44C00046
++#define MSTP7_BITS 0x05BFE618
++#define MSTP8_BITS 0x40C0FE85
++#define MSTP9_BITS 0xFF979FFF
++#define MSTP10_BITS 0xFFFEFFE0
++#define MSTP11_BITS 0x000001C0
++
+ #define R8A7793_CUT_ES2X 2
+ #define IS_R8A7793_ES2() \
+ (rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X)
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7794.h u-boot/arch/arm/include/asm/arch-rmobile/r8a7794.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7794.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-rmobile/r8a7794.h 2015-01-01 17:34:32.089505941 +0100
+@@ -14,4 +14,17 @@
+ /* SH-I2C */
+ #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
+
++/* Module stop control/status register bits */
++#define MSTP0_BITS 0x00440801
++#define MSTP1_BITS 0x936899DA
++#define MSTP2_BITS 0x100D21FC
++#define MSTP3_BITS 0xE084D810
++#define MSTP4_BITS 0x800001C4
++#define MSTP5_BITS 0x40C00044
++#define MSTP7_BITS 0x013FE618
++#define MSTP8_BITS 0x40803C05
++#define MSTP9_BITS 0xFB879FEE
++#define MSTP10_BITS 0xFFFEFFE0
++#define MSTP11_BITS 0x000001C0
++
+ #endif /* __ASM_ARCH_R8A7794_H */
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/rcar-base.h u-boot/arch/arm/include/asm/arch-rmobile/rcar-base.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/rcar-base.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-rmobile/rcar-base.h 2015-01-01 17:34:32.089505941 +0100
+@@ -29,6 +29,45 @@
+ #define SCIF4_BASE 0xE6EE0000
+ #define SCIF5_BASE 0xE6EE8000
+
++/* Module stop status register */
++#define MSTPSR0 0xE6150030
++#define MSTPSR1 0xE6150038
++#define MSTPSR2 0xE6150040
++#define MSTPSR3 0xE6150048
++#define MSTPSR4 0xE615004C
++#define MSTPSR5 0xE615003C
++#define MSTPSR7 0xE61501C4
++#define MSTPSR8 0xE61509A0
++#define MSTPSR9 0xE61509A4
++#define MSTPSR10 0xE61509A8
++#define MSTPSR11 0xE61509AC
++
++/* Realtime module stop control register */
++#define RMSTPCR0 0xE6150110
++#define RMSTPCR1 0xE6150114
++#define RMSTPCR2 0xE6150118
++#define RMSTPCR3 0xE615011C
++#define RMSTPCR4 0xE6150120
++#define RMSTPCR5 0xE6150124
++#define RMSTPCR7 0xE615012C
++#define RMSTPCR8 0xE6150980
++#define RMSTPCR9 0xE6150984
++#define RMSTPCR10 0xE6150988
++#define RMSTPCR11 0xE615098C
++
++/* System module stop control register */
++#define SMSTPCR0 0xE6150130
++#define SMSTPCR1 0xE6150134
++#define SMSTPCR2 0xE6150138
++#define SMSTPCR3 0xE615013C
++#define SMSTPCR4 0xE6150140
++#define SMSTPCR5 0xE6150144
++#define SMSTPCR7 0xE615014C
++#define SMSTPCR8 0xE6150990
++#define SMSTPCR9 0xE6150994
++#define SMSTPCR10 0xE6150998
++#define SMSTPCR11 0xE615099C
++
+ /*
+ * SH-I2C
+ * Ch2 and ch3 are different address. These are defined
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/rcar-mstp.h u-boot/arch/arm/include/asm/arch-rmobile/rcar-mstp.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/rcar-mstp.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-rmobile/rcar-mstp.h 2015-01-01 17:34:32.089505941 +0100
+@@ -0,0 +1,109 @@
++/*
++ * arch/arm/include/asm/arch-rmobile/rcar-mstp.h
++ *
++ * Copyright (C) 2013, 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
++ * Copyright (C) 2013, 2014 Renesas Electronics Corporation
++ *
++ * SPDX-License-Identifier: GPL-2.0
++ */
++
++#ifndef __ASM_ARCH_RCAR_MSTP_H
++#define __ASM_ARCH_RCAR_MSTP_H
++
++#define mstp_setbits(type, addr, saddr, set) \
++ out_##type((saddr), in_##type(addr) | (set))
++#define mstp_clrbits(type, addr, saddr, clear) \
++ out_##type((saddr), in_##type(addr) & ~(clear))
++#define mstp_setclrbits(type, addr, set, clear) \
++ out_##type((addr), (in_##type(addr) | (set)) & ~(clear))
++#define mstp_setbits_le32(addr, saddr, set) \
++ mstp_setbits(le32, addr, saddr, set)
++#define mstp_clrbits_le32(addr, saddr, clear) \
++ mstp_clrbits(le32, addr, saddr, clear)
++#define mstp_setclrbits_le32(addr, set, clear) \
++ mstp_setclrbits(le32, addr, set, clear)
++
++#ifndef CONFIG_SMSTP0_ENA
++#define CONFIG_SMSTP0_ENA 0x00
++#endif
++#ifndef CONFIG_SMSTP1_ENA
++#define CONFIG_SMSTP1_ENA 0x00
++#endif
++#ifndef CONFIG_SMSTP2_ENA
++#define CONFIG_SMSTP2_ENA 0x00
++#endif
++#ifndef CONFIG_SMSTP3_ENA
++#define CONFIG_SMSTP3_ENA 0x00
++#endif
++#ifndef CONFIG_SMSTP4_ENA
++#define CONFIG_SMSTP4_ENA 0x00
++#endif
++#ifndef CONFIG_SMSTP5_ENA
++#define CONFIG_SMSTP5_ENA 0x00
++#endif
++#ifndef CONFIG_SMSTP6_ENA
++#define CONFIG_SMSTP6_ENA 0x00
++#endif
++#ifndef CONFIG_SMSTP7_ENA
++#define CONFIG_SMSTP7_ENA 0x00
++#endif
++#ifndef CONFIG_SMSTP8_ENA
++#define CONFIG_SMSTP8_ENA 0x00
++#endif
++#ifndef CONFIG_SMSTP9_ENA
++#define CONFIG_SMSTP9_ENA 0x00
++#endif
++#ifndef CONFIG_SMSTP10_ENA
++#define CONFIG_SMSTP10_ENA 0x00
++#endif
++#ifndef CONFIG_SMSTP11_ENA
++#define CONFIG_SMSTP11_ENA 0x00
++#endif
++
++#ifndef CONFIG_RMSTP0_ENA
++#define CONFIG_RMSTP0_ENA 0x00
++#endif
++#ifndef CONFIG_RMSTP1_ENA
++#define CONFIG_RMSTP1_ENA 0x00
++#endif
++#ifndef CONFIG_RMSTP2_ENA
++#define CONFIG_RMSTP2_ENA 0x00
++#endif
++#ifndef CONFIG_RMSTP3_ENA
++#define CONFIG_RMSTP3_ENA 0x00
++#endif
++#ifndef CONFIG_RMSTP4_ENA
++#define CONFIG_RMSTP4_ENA 0x00
++#endif
++#ifndef CONFIG_RMSTP5_ENA
++#define CONFIG_RMSTP5_ENA 0x00
++#endif
++#ifndef CONFIG_RMSTP6_ENA
++#define CONFIG_RMSTP6_ENA 0x00
++#endif
++#ifndef CONFIG_RMSTP7_ENA
++#define CONFIG_RMSTP7_ENA 0x00
++#endif
++#ifndef CONFIG_RMSTP8_ENA
++#define CONFIG_RMSTP8_ENA 0x00
++#endif
++#ifndef CONFIG_RMSTP9_ENA
++#define CONFIG_RMSTP9_ENA 0x00
++#endif
++#ifndef CONFIG_RMSTP10_ENA
++#define CONFIG_RMSTP10_ENA 0x00
++#endif
++#ifndef CONFIG_RMSTP11_ENA
++#define CONFIG_RMSTP11_ENA 0x00
++#endif
++
++struct mstp_ctl {
++ u32 s_addr;
++ u32 s_dis;
++ u32 s_ena;
++ u32 r_addr;
++ u32 r_dis;
++ u32 r_ena;
++};
++
++#endif /* __ASM_ARCH_RCAR_MSTP_H */
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/clock_manager.h u-boot/arch/arm/include/asm/arch-socfpga/clock_manager.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/clock_manager.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-socfpga/clock_manager.h 2015-01-01 17:34:32.089505941 +0100
+@@ -14,6 +14,7 @@
+ unsigned int cm_get_l4_sp_clk_hz(void);
+ unsigned int cm_get_mmc_controller_clk_hz(void);
+ unsigned int cm_get_qspi_controller_clk_hz(void);
++unsigned int cm_get_spi_controller_clk_hz(void);
+ #endif
+
+ typedef struct {
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/freeze_controller.h u-boot/arch/arm/include/asm/arch-socfpga/freeze_controller.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/freeze_controller.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-socfpga/freeze_controller.h 2015-01-01 17:34:32.089505941 +0100
+@@ -42,7 +42,6 @@
+ #define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
+ #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
+ #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
+-#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2
+
+ void sys_mgr_frzctrl_freeze_req(void);
+ void sys_mgr_frzctrl_thaw_req(void);
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/scan_manager.h u-boot/arch/arm/include/asm/arch-socfpga/scan_manager.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/scan_manager.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-socfpga/scan_manager.h 2015-01-01 17:34:32.089505941 +0100
+@@ -13,6 +13,7 @@
+ u32 padding[2];
+ u32 fifo_single_byte;
+ u32 fifo_double_byte;
++ u32 fifo_triple_byte;
+ u32 fifo_quad_byte;
+ };
+
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/gpio.h u-boot/arch/arm/include/asm/arch-stv0991/gpio.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/gpio.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-stv0991/gpio.h 2015-01-01 17:34:32.093505875 +0100
+@@ -0,0 +1,22 @@
++/*
++ * (C) Copyright 2014
++ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __ASM_ARCH_STV0991_GPIO_H
++#define __ASM_ARCH_STV0991_GPIO_H
++
++enum gpio_direction {
++ GPIO_DIRECTION_IN,
++ GPIO_DIRECTION_OUT,
++};
++
++struct gpio_regs {
++ u32 data; /* offset 0x0 */
++ u32 reserved[0xff]; /* 0x4--0x3fc */
++ u32 dir; /* offset 0x400 */
++};
++
++#endif /* __ASM_ARCH_STV0991_GPIO_H */
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/hardware.h u-boot/arch/arm/include/asm/arch-stv0991/hardware.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/hardware.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-stv0991/hardware.h 2015-01-01 17:34:32.093505875 +0100
+@@ -0,0 +1,73 @@
++/*
++ * (C) Copyright 2014
++ * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef _ASM_ARCH_HARDWARE_H
++#define _ASM_ARCH_HARDWARE_H
++
++/* STV0991 */
++#define SRAM0_BASE_ADDR 0x00000000UL
++#define SRAM1_BASE_ADDR 0x00068000UL
++#define SRAM2_BASE_ADDR 0x000D0000UL
++#define SRAM3_BASE_ADDR 0x00138000UL
++#define CFS_SRAM0_BASE_ADDR 0x00198000UL
++#define CFS_SRAM1_BASE_ADDR 0x001B8000UL
++#define FAST_SRAM_BASE_ADDR 0x001D8000UL
++#define FLASH_BASE_ADDR 0x40000000UL
++#define PL310_BASE_ADDR 0x70000000UL
++#define HSAXIM_BASE_ADDR 0x70100000UL
++#define IMGSS_BASE_ADDR 0x70200000UL
++#define ADC_BASE_ADDR 0x80000000UL
++#define GPIOA_BASE_ADDR 0x80001000UL
++#define GPIOB_BASE_ADDR 0x80002000UL
++#define GPIOC_BASE_ADDR 0x80003000UL
++#define HDM_BASE_ADDR 0x80004000UL
++#define THSENS_BASE_ADDR 0x80200000UL
++#define GPTIMER2_BASE_ADDR 0x80201000UL
++#define GPTIMER1_BASE_ADDR 0x80202000UL
++#define QSPI_BASE_ADDR 0x80203000UL
++#define CGU_BASE_ADDR 0x80204000UL
++#define CREG_BASE_ADDR 0x80205000UL
++#define PEC_BASE_ADDR 0x80206000UL
++#define WDRU_BASE_ADDR 0x80207000UL
++#define BSEC_BASE_ADDR 0x80208000UL
++#define DAP_ROM_BASE_ADDR 0x80210000UL
++#define SOC_CTI_BASE_ADDR 0x80211000UL
++#define TPIU_BASE_ADDR 0x80212000UL
++#define TMC_ETF_BASE_ADDR 0x80213000UL
++#define R4_ETM_BASE_ADDR 0x80214000UL
++#define R4_CTI_BASE_ADDR 0x80215000UL
++#define R4_DBG_BASE_ADDR 0x80216000UL
++#define GMAC_BASE_ADDR 0x80300000UL
++#define RNSS_BASE_ADDR 0x80302000UL
++#define CRYP_BASE_ADDR 0x80303000UL
++#define HASH_BASE_ADDR 0x80304000UL
++#define GPDMA_BASE_ADDR 0x80305000UL
++#define ISA_BASE_ADDR 0x8032A000UL
++#define HCI_BASE_ADDR 0x80400000UL
++#define I2C1_BASE_ADDR 0x80401000UL
++#define I2C2_BASE_ADDR 0x80402000UL
++#define SAI_BASE_ADDR 0x80403000UL
++#define USI_BASE_ADDR 0x80404000UL
++#define SPI1_BASE_ADDR 0x80405000UL
++#define UART_BASE_ADDR 0x80406000UL
++#define SPI2_BASE_ADDR 0x80500000UL
++#define CAN_BASE_ADDR 0x80501000UL
++#define USART1_BASE_ADDR 0x80502000UL
++#define USART2_BASE_ADDR 0x80503000UL
++#define USART3_BASE_ADDR 0x80504000UL
++#define USART4_BASE_ADDR 0x80505000UL
++#define USART5_BASE_ADDR 0x80506000UL
++#define USART6_BASE_ADDR 0x80507000UL
++#define SDI2_BASE_ADDR 0x80600000UL
++#define SDI1_BASE_ADDR 0x80601000UL
++#define VICA_BASE_ADDR 0x81000000UL
++#define VICB_BASE_ADDR 0x81001000UL
++#define STM_CHANNELS_BASE_ADDR 0x81100000UL
++#define STM_BASE_ADDR 0x81110000UL
++#define SROM_BASE_ADDR 0xFFFF0000UL
++
++#endif /* _ASM_ARCH_HARDWARE_H */
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h 2015-01-01 17:34:32.093505875 +0100
+@@ -0,0 +1,116 @@
++/*
++ * (C) Copyright 2014
++ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef _STV0991_CGU_H
++#define _STV0991_CGU_H
++
++struct stv0991_cgu_regs {
++ u32 cpu_freq; /* offset 0x0 */
++ u32 icn2_freq; /* offset 0x4 */
++ u32 dma_freq; /* offset 0x8 */
++ u32 isp_freq; /* offset 0xc */
++ u32 h264_freq; /* offset 0x10 */
++ u32 osif_freq; /* offset 0x14 */
++ u32 ren_freq; /* offset 0x18 */
++ u32 tim_freq; /* offset 0x1c */
++ u32 sai_freq; /* offset 0x20 */
++ u32 eth_freq; /* offset 0x24 */
++ u32 i2c_freq; /* offset 0x28 */
++ u32 spi_freq; /* offset 0x2c */
++ u32 uart_freq; /* offset 0x30 */
++ u32 qspi_freq; /* offset 0x34 */
++ u32 sdio_freq; /* offset 0x38 */
++ u32 usi_freq; /* offset 0x3c */
++ u32 can_line_freq; /* offset 0x40 */
++ u32 debug_freq; /* offset 0x44 */
++ u32 trace_freq; /* offset 0x48 */
++ u32 stm_freq; /* offset 0x4c */
++ u32 eth_ctrl; /* offset 0x50 */
++ u32 reserved[3]; /* offset 0x54 */
++ u32 osc_ctrl; /* offset 0x60 */
++ u32 pll1_ctrl; /* offset 0x64 */
++ u32 pll1_freq; /* offset 0x68 */
++ u32 pll1_fract; /* offset 0x6c */
++ u32 pll1_spread; /* offset 0x70 */
++ u32 pll1_status; /* offset 0x74 */
++ u32 pll2_ctrl; /* offset 0x78 */
++ u32 pll2_freq; /* offset 0x7c */
++ u32 pll2_fract; /* offset 0x80 */
++ u32 pll2_spread; /* offset 0x84 */
++ u32 pll2_status; /* offset 0x88 */
++ u32 cgu_enable_1; /* offset 0x8c */
++ u32 cgu_enable_2; /* offset 0x90 */
++ u32 cgu_isp_pulse; /* offset 0x94 */
++ u32 cgu_h264_pulse; /* offset 0x98 */
++ u32 cgu_osif_pulse; /* offset 0x9c */
++ u32 cgu_ren_pulse; /* offset 0xa0 */
++
++};
++
++/* CGU Timer */
++#define CLK_TMR_OSC 0
++#define CLK_TMR_MCLK 1
++#define CLK_TMR_PLL1 2
++#define CLK_TMR_PLL2 3
++#define MDIV_SHIFT_TMR 3
++#define DIV_SHIFT_TMR 6
++
++#define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \
++ | 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK)
++
++/* Clock Enable/Disable */
++
++#define TIMER1_CLK_EN (1 << 15)
++
++/* CGU Uart config */
++#define CLK_UART_MCLK 0
++#define CLK_UART_PLL1 1
++#define CLK_UART_PLL2 2
++
++#define MDIV_SHIFT_UART 3
++#define DIV_SHIFT_UART 6
++
++#define UART_CLK_CFG (4 << DIV_SHIFT_UART \
++ | 1 << MDIV_SHIFT_UART | CLK_UART_MCLK)
++
++/* CGU Ethernet clock config */
++#define CLK_ETH_MCLK 0
++#define CLK_ETH_PLL1 1
++#define CLK_ETH_PLL2 2
++
++#define MDIV_SHIFT_ETH 3
++#define DIV_SHIFT_ETH 6
++#define DIV_ETH_125 9
++#define DIV_ETH_50 12
++#define DIV_ETH_P2P 15
++
++#define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \
++ | 1 << DIV_ETH_125 \
++ | 0 << DIV_SHIFT_ETH \
++ | 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1)
++ /* CGU Ethernet control */
++
++#define ETH_CLK_TX_EXT_PHY 0
++#define ETH_CLK_TX_125M 1
++#define ETH_CLK_TX_25M 2
++#define ETH_CLK_TX_2M5 3
++#define ETH_CLK_TX_DIS 7
++
++#define ETH_CLK_RX_EXT_PHY 0
++#define ETH_CLK_RX_25M 1
++#define ETH_CLK_RX_2M5 2
++#define ETH_CLK_RX_DIS 3
++#define RX_CLK_SHIFT 3
++#define ETH_CLK_MASK ~(0x1F)
++
++#define ETH_PHY_MODE_GMII 0
++#define ETH_PHY_MODE_RMII 1
++#define ETH_PHY_CLK_DIS 1
++
++#define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \
++ | ETH_CLK_TX_EXT_PHY)
++#endif
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_creg.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_creg.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_creg.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_creg.h 2015-01-01 17:34:32.093505875 +0100
+@@ -0,0 +1,95 @@
++/*
++ * (C) Copyright 2014
++ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef _STV0991_CREG_H
++#define _STV0991_CREG_H
++
++struct stv0991_creg {
++ u32 version; /* offset 0x0 */
++ u32 hdpctl; /* offset 0x4 */
++ u32 hdpval; /* offset 0x8 */
++ u32 hdpgposet; /* offset 0xc */
++ u32 hdpgpoclr; /* offset 0x10 */
++ u32 hdpgpoval; /* offset 0x14 */
++ u32 stm_mux; /* offset 0x18 */
++ u32 sysctrl_1; /* offset 0x1c */
++ u32 sysctrl_2; /* offset 0x20 */
++ u32 sysctrl_3; /* offset 0x24 */
++ u32 sysctrl_4; /* offset 0x28 */
++ u32 reserved_1[0x35]; /* offset 0x2C-0xFC */
++ u32 mux1; /* offset 0x100 */
++ u32 mux2; /* offset 0x104 */
++ u32 mux3; /* offset 0x108 */
++ u32 mux4; /* offset 0x10c */
++ u32 mux5; /* offset 0x110 */
++ u32 mux6; /* offset 0x114 */
++ u32 mux7; /* offset 0x118 */
++ u32 mux8; /* offset 0x11c */
++ u32 mux9; /* offset 0x120 */
++ u32 mux10; /* offset 0x124 */
++ u32 mux11; /* offset 0x128 */
++ u32 mux12; /* offset 0x12c */
++ u32 mux13; /* offset 0x130 */
++ u32 reserved_2[0x33]; /* offset 0x134-0x1FC */
++ u32 cfg_pad1; /* offset 0x200 */
++ u32 cfg_pad2; /* offset 0x204 */
++ u32 cfg_pad3; /* offset 0x208 */
++ u32 cfg_pad4; /* offset 0x20c */
++ u32 cfg_pad5; /* offset 0x210 */
++ u32 cfg_pad6; /* offset 0x214 */
++ u32 cfg_pad7; /* offset 0x218 */
++ u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */
++ u32 vdd_pad1; /* offset 0x300 */
++ u32 vdd_pad2; /* offset 0x304 */
++ u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */
++ u32 vdd_comp1; /* offset 0x400 */
++};
++
++/* CREG MUX 12 register */
++#define GPIOC_30_MUX_SHIFT 24
++#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT)
++#define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT)
++
++#define GPIOC_31_MUX_SHIFT 28
++#define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT)
++#define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT)
++
++/* CREG MUX 7 register */
++#define GPIOB_16_MUX_SHIFT 0
++#define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT)
++#define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT)
++
++#define GPIOB_17_MUX_SHIFT 4
++#define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT)
++#define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT)
++
++/* CREG CFG_PAD6 register */
++
++#define GPIOC_31_MODE_SHIFT 30
++#define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT)
++#define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT)
++#define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT)
++
++#define GPIOC_30_MODE_SHIFT 28
++#define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT)
++#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT)
++#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT)
++
++/* CREG Ethernet pad config */
++
++#define VDD_ETH_PS_1V8 0
++#define VDD_ETH_PS_2V5 2
++#define VDD_ETH_PS_3V3 3
++#define VDD_ETH_PS_MASK 0x3
++
++#define VDD_ETH_PS_SHIFT 12
++#define ETH_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT)
++
++#define VDD_ETH_M_PS_SHIFT 28
++#define ETH_M_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT)
++
++#endif
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_defs.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_defs.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_defs.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_defs.h 2015-01-01 17:34:32.093505875 +0100
+@@ -0,0 +1,16 @@
++/*
++ * (C) Copyright 2014
++ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __STV0991_DEFS_H__
++#define __STV0991_DEFS_H__
++#include <asm/arch/stv0991_periph.h>
++
++extern int stv0991_pinmux_config(enum periph_id);
++extern int clock_setup(enum periph_clock);
++
++#endif
++
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h 2015-01-01 17:34:32.093505875 +0100
+@@ -0,0 +1,43 @@
++/*
++ * (C) Copyright 2014
++ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef _STV0991_GPT_H
++#define _STV0991_GPT_H
++
++#include <asm/arch-stv0991/hardware.h>
++
++struct gpt_regs {
++ u32 cr1;
++ u32 cr2;
++ u32 reserved_1;
++ u32 dier; /* dma_int_en */
++ u32 sr; /* status reg */
++ u32 egr; /* event gen */
++ u32 reserved_2[3]; /* offset 0x18--0x20*/
++ u32 cnt;
++ u32 psc;
++ u32 arr;
++};
++
++struct gpt_regs *const gpt1_regs_ptr =
++ (struct gpt_regs *) GPTIMER1_BASE_ADDR;
++
++/* Timer control1 register */
++#define GPT_CR1_CEN 0x0001
++#define GPT_MODE_AUTO_RELOAD (1 << 7)
++
++/* Timer prescalar reg */
++#define GPT_PRESCALER_128 0x128
++
++/* Auto reload register for free running config */
++#define GPT_FREE_RUNNING 0xFFFF
++
++/* Timer, HZ specific defines */
++#define CONFIG_STV0991_HZ 1000
++#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128
++
++#endif
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_periph.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_periph.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_periph.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_periph.h 2015-01-01 17:34:32.093505875 +0100
+@@ -0,0 +1,44 @@
++/*
++ * (C) Copyright 2014
++ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __ASM_ARM_ARCH_PERIPH_H
++#define __ASM_ARM_ARCH_PERIPH_H
++
++/*
++ * Peripherals required for pinmux configuration. List will
++ * grow with support for more devices getting added.
++ * Numbering based on interrupt table.
++ *
++ */
++enum periph_id {
++ UART_GPIOC_30_31 = 0,
++ UART_GPIOB_16_17,
++ ETH_GPIOB_10_31_C_0_4,
++ PERIPH_ID_I2C0,
++ PERIPH_ID_I2C1,
++ PERIPH_ID_I2C2,
++ PERIPH_ID_I2C3,
++ PERIPH_ID_I2C4,
++ PERIPH_ID_I2C5,
++ PERIPH_ID_I2C6,
++ PERIPH_ID_I2C7,
++ PERIPH_ID_SPI0,
++ PERIPH_ID_SPI1,
++ PERIPH_ID_SPI2,
++ PERIPH_ID_SDMMC0,
++ PERIPH_ID_SDMMC1,
++ PERIPH_ID_SDMMC2,
++ PERIPH_ID_SDMMC3,
++ PERIPH_ID_I2S1,
++};
++
++enum periph_clock {
++ UART_CLOCK_CFG = 0,
++ ETH_CLOCK_CFG,
++};
++
++#endif /* __ASM_ARM_ARCH_PERIPH_H */
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h 2015-01-01 17:34:32.093505875 +0100
+@@ -0,0 +1,28 @@
++/*
++ * (C) Copyright 2014
++ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef _STV0991_WD_RST_H
++#define _STV0991_WD_RST_H
++#include <asm/arch-stv0991/hardware.h>
++
++struct stv0991_wd_ru {
++ u32 wdru_config;
++ u32 wdru_ctrl1;
++ u32 wdru_ctrl2;
++ u32 wdru_tim;
++ u32 wdru_count;
++ u32 wdru_stat;
++ u32 wdru_wrlock;
++};
++
++struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \
++ (struct stv0991_wd_ru *)WDRU_BASE_ADDR;
++
++/* Watchdog control register */
++#define WDRU_RST_SYS 0x1
++
++#endif
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-tegra/tegra_i2c.h u-boot/arch/arm/include/asm/arch-tegra/tegra_i2c.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-tegra/tegra_i2c.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-tegra/tegra_i2c.h 2015-01-01 17:34:32.097505809 +0100
+@@ -167,6 +167,6 @@
+ *
+ * @return number of bus, or -1 if there is no DVC active
+ */
+-int tegra_i2c_get_dvc_bus_num(void);
++int tegra_i2c_get_dvc_bus(struct udevice **busp);
+
+ #endif /* _TEGRA_I2C_H_ */
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-vf610/imx-regs.h u-boot/arch/arm/include/asm/arch-vf610/imx-regs.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/arch-vf610/imx-regs.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/arch-vf610/imx-regs.h 2015-01-01 17:34:32.109505612 +0100
+@@ -256,6 +256,14 @@
+ #define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8)
+ #define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf)
+
++/* System Reset Controller (SRC) */
++#define SRC_SRSR_SW_RST (0x1 << 18)
++#define SRC_SRSR_RESETB (0x1 << 7)
++#define SRC_SRSR_JTAG_RST (0x1 << 5)
++#define SRC_SRSR_WDOG_M4 (0x1 << 4)
++#define SRC_SRSR_WDOG_A5 (0x1 << 3)
++#define SRC_SRSR_POR_RST (0x1 << 0)
++
+ #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+ #include <asm/types.h>
+
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/kona-common/clk.h u-boot/arch/arm/include/asm/kona-common/clk.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/kona-common/clk.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/kona-common/clk.h 2015-01-01 17:34:32.113505547 +0100
+@@ -25,5 +25,6 @@
+ struct clk *clk_get_parent(struct clk *clk);
+ int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
+ int clk_bsc_enable(void *base);
++int clk_usb_otg_enable(void *base);
+
+ #endif
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/pcie_layerscape.h u-boot/arch/arm/include/asm/pcie_layerscape.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/pcie_layerscape.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/arm/include/asm/pcie_layerscape.h 2015-01-01 17:34:32.125505350 +0100
+@@ -0,0 +1,13 @@
++/*
++ * Copyright 2014 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __PCIE_LAYERSCAPE_H_
++#define __PCIE_LAYERSCAPE_H_
++
++void pci_init_board(void);
++void ft_pcie_setup(void *blob, bd_t *bd);
++
++#endif
+diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/semihosting.h u-boot/arch/arm/include/asm/semihosting.h
+--- u-boot-2015.01-rc3/arch/arm/include/asm/semihosting.h 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/include/asm/semihosting.h 2015-01-01 17:34:32.125505350 +0100
+@@ -12,10 +12,6 @@
+ * code for more information.
+ */
+ int smh_load(const char *fname, void *memp, int avail, int verbose);
+-int smh_read(int fd, void *memp, int len);
+-int smh_open(const char *fname, char *modestr);
+-int smh_close(int fd);
+-int smh_len_fd(int fd);
+-int smh_len(const char *fname);
++long smh_len(const char *fname);
+
+ #endif /* __SEMIHOSTING_H__ */
+diff -ruN u-boot-2015.01-rc3/arch/arm/Kconfig u-boot/arch/arm/Kconfig
+--- u-boot-2015.01-rc3/arch/arm/Kconfig 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/Kconfig 2015-01-01 17:34:31.989507580 +0100
+@@ -341,6 +341,10 @@
+ bool "Support spear600"
+ select CPU_ARM926EJS
+
++config TARGET_STV0991
++ bool "Support stv0991"
++ select CPU_V7
++
+ config TARGET_X600
+ bool "Support x600"
+ select CPU_ARM926EJS
+@@ -650,6 +654,7 @@
+
+ config TARGET_TBS2910
+ bool "Support tbs2910"
++ select CPU_V7
+
+ config TARGET_TQMA6
+ bool "TQ Systems TQMa6 board"
+@@ -728,12 +733,14 @@
+ select ARM64
+
+ config TARGET_LS1021AQDS
+- bool "Support ls1021aqds_nor"
++ bool "Support ls1021aqds"
+ select CPU_V7
++ select SUPPORT_SPL
+
+ config TARGET_LS1021ATWR
+- bool "Support ls1021atwr_nor"
++ bool "Support ls1021atwr"
+ select CPU_V7
++ select SUPPORT_SPL
+
+ config TARGET_BALLOON3
+ bool "Support balloon3"
+@@ -793,6 +800,7 @@
+ bool "Panasonic UniPhier platform"
+ select CPU_V7
+ select SUPPORT_SPL
++ select SPL
+ select OF_CONTROL if !SPL_BUILD
+
+ endchoice
+@@ -953,6 +961,7 @@
+ source "board/spear/x600/Kconfig"
+ source "board/st-ericsson/snowball/Kconfig"
+ source "board/st-ericsson/u8500/Kconfig"
++source "board/st/stv0991/Kconfig"
+ source "board/sunxi/Kconfig"
+ source "board/syteco/jadecpu/Kconfig"
+ source "board/syteco/zmx25/Kconfig"
+diff -ruN u-boot-2015.01-rc3/arch/arm/lib/semihosting.c u-boot/arch/arm/lib/semihosting.c
+--- u-boot-2015.01-rc3/arch/arm/lib/semihosting.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/arm/lib/semihosting.c 2015-01-01 17:34:32.133505219 +0100
+@@ -26,9 +26,9 @@
+ /*
+ * Call the handler
+ */
+-static int smh_trap(unsigned int sysnum, void *addr)
++static long smh_trap(unsigned int sysnum, void *addr)
+ {
+- register int result asm("r0");
++ register long result asm("r0");
+ #if defined(CONFIG_ARM64)
+ asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr));
+ #else
+@@ -39,167 +39,164 @@
+ }
+
+ /*
+- * Open, load a file into memory, and close it. Check that the available space
+- * is sufficient to store the entire file. Return the bytes actually read from
+- * the file as seen by the read function. The verbose flag enables some extra
+- * printing of successful read status.
++ * Open a file on the host. Mode is "r" or "rb" currently. Returns a file
++ * descriptor or -1 on error.
+ */
+-int smh_load(const char *fname, void *memp, int avail, int verbose)
++static long smh_open(const char *fname, char *modestr)
+ {
+- int ret, fd, len;
+-
+- ret = -1;
+-
+- debug("%s: fname \'%s\', avail %u, memp %p\n", __func__, fname,
+- avail, memp);
+-
+- /* Open the file */
+- fd = smh_open(fname, "rb");
+- if (fd == -1)
+- return ret;
++ long fd;
++ unsigned long mode;
++ struct smh_open_s {
++ const char *fname;
++ unsigned long mode;
++ size_t len;
++ } open;
+
+- /* Get the file length */
+- ret = smh_len_fd(fd);
+- if (ret == -1) {
+- smh_close(fd);
+- return ret;
+- }
++ debug("%s: file \'%s\', mode \'%s\'\n", __func__, fname, modestr);
+
+- /* Check that the file will fit in the supplied buffer */
+- if (ret > avail) {
+- printf("%s: ERROR ret %d, avail %u\n", __func__, ret,
+- avail);
+- smh_close(fd);
+- return ret;
++ /* Check the file mode */
++ if (!(strcmp(modestr, "r"))) {
++ mode = MODE_READ;
++ } else if (!(strcmp(modestr, "rb"))) {
++ mode = MODE_READBIN;
++ } else {
++ printf("%s: ERROR mode \'%s\' not supported\n", __func__,
++ modestr);
++ return -1;
+ }
+
+- len = ret;
+-
+- /* Read the file into the buffer */
+- ret = smh_read(fd, memp, len);
+- if (ret == 0) {
+- /* Print successful load information if requested */
+- if (verbose) {
+- printf("\n%s\n", fname);
+- printf(" 0x%8p dest\n", memp);
+- printf(" 0x%08x size\n", len);
+- printf(" 0x%08x avail\n", avail);
+- }
+- }
++ open.fname = fname;
++ open.len = strlen(fname);
++ open.mode = mode;
+
+- /* Close the file */
+- smh_close(fd);
++ /* Open the file on the host */
++ fd = smh_trap(SYSOPEN, &open);
++ if (fd == -1)
++ printf("%s: ERROR fd %ld for file \'%s\'\n", __func__, fd,
++ fname);
+
+- return ret;
++ return fd;
+ }
+
+ /*
+ * Read 'len' bytes of file into 'memp'. Returns 0 on success, else failure
+ */
+-int smh_read(int fd, void *memp, int len)
++static long smh_read(long fd, void *memp, size_t len)
+ {
+- int ret;
++ long ret;
+ struct smh_read_s {
+- int fd;
++ long fd;
+ void *memp;
+- int len;
++ size_t len;
+ } read;
+
+- debug("%s: fd %d, memp %p, len %d\n", __func__, fd, memp, len);
++ debug("%s: fd %ld, memp %p, len %lu\n", __func__, fd, memp, len);
+
+ read.fd = fd;
+ read.memp = memp;
+ read.len = len;
+
+ ret = smh_trap(SYSREAD, &read);
+- if (ret == 0) {
+- return 0;
+- } else {
++ if (ret < 0) {
+ /*
+ * The ARM handler allows for returning partial lengths,
+ * but in practice this never happens so rather than create
+ * hard to maintain partial read loops and such, just fail
+ * with an error message.
+ */
+- printf("%s: ERROR ret %d, fd %d, len %u memp %p\n",
++ printf("%s: ERROR ret %ld, fd %ld, len %lu memp %p\n",
+ __func__, ret, fd, len, memp);
++ return -1;
+ }
+- return ret;
++
++ return 0;
+ }
+
+ /*
+- * Open a file on the host. Mode is "r" or "rb" currently. Returns a file
+- * descriptor or -1 on error.
++ * Close the file using the file descriptor
+ */
+-int smh_open(const char *fname, char *modestr)
++static long smh_close(long fd)
+ {
+- int ret, fd, mode;
+- struct smh_open_s {
+- const char *fname;
+- unsigned int mode;
+- unsigned int len;
+- } open;
++ long ret;
+
+- debug("%s: file \'%s\', mode \'%s\'\n", __func__, fname, modestr);
+-
+- ret = -1;
++ debug("%s: fd %ld\n", __func__, fd);
+
+- /* Check the file mode */
+- if (!(strcmp(modestr, "r"))) {
+- mode = MODE_READ;
+- } else if (!(strcmp(modestr, "rb"))) {
+- mode = MODE_READBIN;
+- } else {
+- printf("%s: ERROR mode \'%s\' not supported\n", __func__,
+- modestr);
+- return ret;
+- }
+-
+- open.fname = fname;
+- open.len = strlen(fname);
+- open.mode = mode;
+-
+- /* Open the file on the host */
+- fd = smh_trap(SYSOPEN, &open);
+- if (fd == -1)
+- printf("%s: ERROR fd %d for file \'%s\'\n", __func__, fd,
+- fname);
++ ret = smh_trap(SYSCLOSE, &fd);
++ if (ret == -1)
++ printf("%s: ERROR fd %ld\n", __func__, fd);
+
+- return fd;
++ return ret;
+ }
+
+ /*
+- * Close the file using the file descriptor
++ * Get the file length from the file descriptor
+ */
+-int smh_close(int fd)
++static long smh_len_fd(long fd)
+ {
+- int ret;
+- long fdlong;
++ long ret;
+
+- debug("%s: fd %d\n", __func__, fd);
++ debug("%s: fd %ld\n", __func__, fd);
+
+- fdlong = (long)fd;
+- ret = smh_trap(SYSCLOSE, &fdlong);
++ ret = smh_trap(SYSFLEN, &fd);
+ if (ret == -1)
+- printf("%s: ERROR fd %d\n", __func__, fd);
++ printf("%s: ERROR ret %ld, fd %ld\n", __func__, ret, fd);
+
+ return ret;
+ }
+
+ /*
+- * Get the file length from the file descriptor
++ * Open, load a file into memory, and close it. Check that the available space
++ * is sufficient to store the entire file. Return the bytes actually read from
++ * the file as seen by the read function. The verbose flag enables some extra
++ * printing of successful read status.
+ */
+-int smh_len_fd(int fd)
++int smh_load(const char *fname, void *memp, int avail, int verbose)
+ {
+- int ret;
+- long fdlong;
++ long ret;
++ long fd;
++ size_t len;
+
+- debug("%s: fd %d\n", __func__, fd);
++ ret = -1;
+
+- fdlong = (long)fd;
+- ret = smh_trap(SYSFLEN, &fdlong);
+- if (ret == -1)
+- printf("%s: ERROR ret %d\n", __func__, ret);
++ debug("%s: fname \'%s\', avail %u, memp %p\n", __func__, fname,
++ avail, memp);
++
++ /* Open the file */
++ fd = smh_open(fname, "rb");
++ if (fd == -1)
++ return -1;
++
++ /* Get the file length */
++ ret = smh_len_fd(fd);
++ if (ret == -1) {
++ smh_close(fd);
++ return -1;
++ }
++
++ /* Check that the file will fit in the supplied buffer */
++ if (ret > avail) {
++ printf("%s: ERROR ret %ld, avail %u\n", __func__, ret,
++ avail);
++ smh_close(fd);
++ return -1;
++ }
++
++ len = ret;
++
++ /* Read the file into the buffer */
++ ret = smh_read(fd, memp, len);
++ if (ret == 0) {
++ /* Print successful load information if requested */
++ if (verbose) {
++ printf("\n%s\n", fname);
++ printf(" 0x%8p dest\n", memp);
++ printf(" 0x%08lx size\n", len);
++ printf(" 0x%08x avail\n", avail);
++ }
++ }
++
++ /* Close the file */
++ smh_close(fd);
+
+ return ret;
+ }
+@@ -207,26 +204,32 @@
+ /*
+ * Get the file length from the filename
+ */
+-int smh_len(const char *fname)
++long smh_len(const char *fname)
+ {
+- int ret, fd, len;
++ long ret;
++ long fd;
++ long len;
+
+ debug("%s: file \'%s\'\n", __func__, fname);
+
+ /* Open the file */
+ fd = smh_open(fname, "rb");
+- if (fd == -1)
++ if (fd < 0)
+ return fd;
+
+ /* Get the file length */
+ len = smh_len_fd(fd);
++ if (len < 0) {
++ smh_close(fd);
++ return len;
++ }
+
+ /* Close the file */
+ ret = smh_close(fd);
+- if (ret == -1)
++ if (ret < 0)
+ return ret;
+
+- debug("%s: returning len %d\n", __func__, len);
++ debug("%s: returning len %ld\n", __func__, len);
+
+ /* Return the file length (or -1 error indication) */
+ return len;
+diff -ruN u-boot-2015.01-rc3/arch/microblaze/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h u-boot/arch/microblaze/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h
+diff -ruN u-boot-2015.01-rc3/arch/microblaze/dts/include/dt-bindings/reset/altr,rst-mgr.h u-boot/arch/microblaze/dts/include/dt-bindings/reset/altr,rst-mgr.h
+diff -ruN u-boot-2015.01-rc3/arch/powerpc/cpu/mpc85xx/p5040_ids.c u-boot/arch/powerpc/cpu/mpc85xx/p5040_ids.c
+--- u-boot-2015.01-rc3/arch/powerpc/cpu/mpc85xx/p5040_ids.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/powerpc/cpu/mpc85xx/p5040_ids.c 2015-01-01 17:34:32.221503777 +0100
+@@ -49,23 +49,23 @@
+
+ #ifdef CONFIG_SYS_DPAA_FMAN
+ struct liodn_id_table fman1_liodn_tbl[] = {
+- SET_FMAN_RX_1G_LIODN(1, 0, 6),
+- SET_FMAN_RX_1G_LIODN(1, 1, 7),
+- SET_FMAN_RX_1G_LIODN(1, 2, 8),
+- SET_FMAN_RX_1G_LIODN(1, 3, 9),
+- SET_FMAN_RX_1G_LIODN(1, 4, 10),
+- SET_FMAN_RX_10G_LIODN(1, 0, 11),
++ SET_FMAN_RX_1G_LIODN(1, 0, 11),
++ SET_FMAN_RX_1G_LIODN(1, 1, 12),
++ SET_FMAN_RX_1G_LIODN(1, 2, 13),
++ SET_FMAN_RX_1G_LIODN(1, 3, 14),
++ SET_FMAN_RX_1G_LIODN(1, 4, 15),
++ SET_FMAN_RX_10G_LIODN(1, 0, 16),
+ };
+ int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+
+ #if (CONFIG_SYS_NUM_FMAN == 2)
+ struct liodn_id_table fman2_liodn_tbl[] = {
+- SET_FMAN_RX_1G_LIODN(2, 0, 12),
+- SET_FMAN_RX_1G_LIODN(2, 1, 13),
+- SET_FMAN_RX_1G_LIODN(2, 2, 14),
+- SET_FMAN_RX_1G_LIODN(2, 3, 15),
+- SET_FMAN_RX_1G_LIODN(2, 4, 16),
+- SET_FMAN_RX_10G_LIODN(2, 0, 17),
++ SET_FMAN_RX_1G_LIODN(2, 0, 17),
++ SET_FMAN_RX_1G_LIODN(2, 1, 18),
++ SET_FMAN_RX_1G_LIODN(2, 2, 19),
++ SET_FMAN_RX_1G_LIODN(2, 3, 20),
++ SET_FMAN_RX_1G_LIODN(2, 4, 21),
++ SET_FMAN_RX_10G_LIODN(2, 0, 22),
+ };
+ int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
+ #endif
+diff -ruN u-boot-2015.01-rc3/arch/powerpc/cpu/mpc85xx/portals.c u-boot/arch/powerpc/cpu/mpc85xx/portals.c
+--- u-boot-2015.01-rc3/arch/powerpc/cpu/mpc85xx/portals.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/powerpc/cpu/mpc85xx/portals.c 2015-01-01 17:34:32.221503777 +0100
+@@ -14,9 +14,46 @@
+ #include <asm/fsl_portals.h>
+ #include <asm/fsl_liodn.h>
+
++#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
++#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
++static void inhibit_portals(void __iomem *addr, int max_portals,
++ int arch_max_portals, int portal_cinh_size)
++{
++ uint32_t val;
++ int i;
++
++ /* arch_max_portals is the maximum based on memory size. This includes
++ * the reserved memory in the SoC. max_portals the number of physical
++ * portals in the SoC */
++ if (max_portals > arch_max_portals) {
++ printf("ERROR: portal config error\n");
++ max_portals = arch_max_portals;
++ }
++
++ for (i = 0; i < max_portals; i++) {
++ out_be32(addr, -1);
++ val = in_be32(addr);
++ if (!val) {
++ printf("ERROR: Stopped after %d portals\n", i);
++ goto done;
++ }
++ addr += portal_cinh_size;
++ }
++#ifdef DEBUG
++ printf("Cleared %d portals\n", i);
++#endif
++done:
++
++ return;
++}
++
+ void setup_portals(void)
+ {
+ ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
++ void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
++ CONFIG_SYS_BMAN_SWP_ISDR_REG;
++ void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
++ CONFIG_SYS_QMAN_SWP_ISDR_REG;
+ #ifdef CONFIG_FSL_CORENET
+ int i;
+
+@@ -38,6 +75,12 @@
+ out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
+ #endif
+ out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
++
++ /* Change default state of BMan ISDR portals to all 1s */
++ inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
++ CONFIG_SYS_BMAN_SP_CINH_SIZE);
++ inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
++ CONFIG_SYS_QMAN_SP_CINH_SIZE);
+ }
+
+ /* Update portal containter to match LAW setup of portal in phy map */
+diff -ruN u-boot-2015.01-rc3/arch/powerpc/cpu/mpc85xx/tlb.c u-boot/arch/powerpc/cpu/mpc85xx/tlb.c
+--- u-boot-2015.01-rc3/arch/powerpc/cpu/mpc85xx/tlb.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/powerpc/cpu/mpc85xx/tlb.c 2015-01-01 17:34:32.221503777 +0100
+@@ -299,12 +299,16 @@
+ {
+ unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
+ u64 memsize = (u64)memsize_in_meg << 20;
++ u64 size;
+
+- memsize = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED);
+- memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM);
++ size = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED);
++ size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM);
+
+- if (memsize)
+- print_size(memsize, " left unmapped\n");
++ if (size || memsize > CONFIG_MAX_MEM_MAPPED) {
++ print_size(memsize > CONFIG_MAX_MEM_MAPPED ?
++ memsize - CONFIG_MAX_MEM_MAPPED + size : size,
++ " left unmapped\n");
++ }
+
+ return memsize_in_meg;
+ }
+diff -ruN u-boot-2015.01-rc3/arch/powerpc/cpu/mpc8xxx/fdt.c u-boot/arch/powerpc/cpu/mpc8xxx/fdt.c
+--- u-boot-2015.01-rc3/arch/powerpc/cpu/mpc8xxx/fdt.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/powerpc/cpu/mpc8xxx/fdt.c 2015-01-01 17:34:32.225503711 +0100
+@@ -73,110 +73,6 @@
+ }
+ #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
+
+-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+-static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
+- const char *phy_type, int start_offset)
+-{
+- const char *compat_dr = "fsl-usb2-dr";
+- const char *compat_mph = "fsl-usb2-mph";
+- const char *prop_mode = "dr_mode";
+- const char *prop_type = "phy_type";
+- const char *node_type = NULL;
+- int node_offset;
+- int err;
+-
+- node_offset = fdt_node_offset_by_compatible(blob,
+- start_offset, compat_mph);
+- if (node_offset < 0) {
+- node_offset = fdt_node_offset_by_compatible(blob,
+- start_offset, compat_dr);
+- if (node_offset < 0) {
+- printf("WARNING: could not find compatible"
+- " node %s or %s: %s.\n", compat_mph,
+- compat_dr, fdt_strerror(node_offset));
+- return -1;
+- } else
+- node_type = compat_dr;
+- } else
+- node_type = compat_mph;
+-
+- if (mode) {
+- err = fdt_setprop(blob, node_offset, prop_mode, mode,
+- strlen(mode) + 1);
+- if (err < 0)
+- printf("WARNING: could not set %s for %s: %s.\n",
+- prop_mode, node_type, fdt_strerror(err));
+- }
+-
+- if (phy_type) {
+- err = fdt_setprop(blob, node_offset, prop_type, phy_type,
+- strlen(phy_type) + 1);
+- if (err < 0)
+- printf("WARNING: could not set %s for %s: %s.\n",
+- prop_type, node_type, fdt_strerror(err));
+- }
+-
+- return node_offset;
+-}
+-
+-void fdt_fixup_dr_usb(void *blob, bd_t *bd)
+-{
+- const char *modes[] = { "host", "peripheral", "otg" };
+- const char *phys[] = { "ulpi", "utmi" };
+- int usb_mode_off = -1;
+- int usb_phy_off = -1;
+- char str[5];
+- int i, j;
+-
+- for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
+- const char *dr_mode_type = NULL;
+- const char *dr_phy_type = NULL;
+- int mode_idx = -1, phy_idx = -1;
+- snprintf(str, 5, "%s%d", "usb", i);
+- if (hwconfig(str)) {
+- for (j = 0; j < ARRAY_SIZE(modes); j++) {
+- if (hwconfig_subarg_cmp(str, "dr_mode",
+- modes[j])) {
+- mode_idx = j;
+- break;
+- }
+- }
+-
+- for (j = 0; j < ARRAY_SIZE(phys); j++) {
+- if (hwconfig_subarg_cmp(str, "phy_type",
+- phys[j])) {
+- phy_idx = j;
+- break;
+- }
+- }
+-
+- if (mode_idx < 0 && phy_idx < 0) {
+- printf("WARNING: invalid phy or mode\n");
+- return;
+- }
+-
+- if (mode_idx > -1)
+- dr_mode_type = modes[mode_idx];
+-
+- if (phy_idx > -1)
+- dr_phy_type = phys[phy_idx];
+- }
+-
+- usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
+- dr_mode_type, NULL, usb_mode_off);
+-
+- if (usb_mode_off < 0)
+- return;
+-
+- usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
+- NULL, dr_phy_type, usb_phy_off);
+-
+- if (usb_phy_off < 0)
+- return;
+- }
+-}
+-#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
+-
+ /*
+ * update crypto node properties to a specified revision of the SEC
+ * called with sec_rev == 0 if not on an E processor
+diff -ruN u-boot-2015.01-rc3/arch/sandbox/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h u-boot/arch/sandbox/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h
+diff -ruN u-boot-2015.01-rc3/arch/sandbox/dts/include/dt-bindings/reset/altr,rst-mgr.h u-boot/arch/sandbox/dts/include/dt-bindings/reset/altr,rst-mgr.h
+diff -ruN u-boot-2015.01-rc3/arch/sandbox/dts/sandbox.dts u-boot/arch/sandbox/dts/sandbox.dts
+--- u-boot-2015.01-rc3/arch/sandbox/dts/sandbox.dts 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/sandbox/dts/sandbox.dts 2015-01-01 17:34:32.241503449 +0100
+@@ -134,6 +134,23 @@
+ num-gpios = <20>;
+ };
+
++ i2c@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++ compatible = "sandbox,i2c";
++ clock-frequency = <400000>;
++ eeprom@2c {
++ reg = <0x2c>;
++ compatible = "i2c-eeprom";
++ emul {
++ compatible = "sandbox,i2c-eeprom";
++ sandbox,filename = "i2c.bin";
++ sandbox,size = <128>;
++ };
++ };
++ };
++
+ spi@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+diff -ruN u-boot-2015.01-rc3/arch/sandbox/include/asm/test.h u-boot/arch/sandbox/include/asm/test.h
+--- u-boot-2015.01-rc3/arch/sandbox/include/asm/test.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/sandbox/include/asm/test.h 2015-01-01 17:34:32.241503449 +0100
+@@ -0,0 +1,26 @@
++/*
++ * Test-related constants for sandbox
++ *
++ * Copyright (c) 2014 Google, Inc
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __ASM_TEST_H
++#define __ASM_TEST_H
++
++/* The sandbox driver always permits an I2C device with this address */
++#define SANDBOX_I2C_TEST_ADDR 0x59
++
++enum sandbox_i2c_eeprom_test_mode {
++ SIE_TEST_MODE_NONE,
++ /* Permits read/write of only one byte per I2C transaction */
++ SIE_TEST_MODE_SINGLE_BYTE,
++};
++
++void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev,
++ enum sandbox_i2c_eeprom_test_mode mode);
++
++void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len);
++
++#endif
+diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/ivybridge/cpu.c u-boot/arch/x86/cpu/ivybridge/cpu.c
+--- u-boot-2015.01-rc3/arch/x86/cpu/ivybridge/cpu.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/x86/cpu/ivybridge/cpu.c 2015-01-01 17:34:32.249503317 +0100
+@@ -263,6 +263,7 @@
+ static int report_bist_failure(void)
+ {
+ if (gd->arch.bist != 0) {
++ post_code(POST_BIST_FAILURE);
+ printf("BIST failed: %08x\n", gd->arch.bist);
+ return -EFAULT;
+ }
+diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/ivybridge/microcode_intel.c u-boot/arch/x86/cpu/ivybridge/microcode_intel.c
+--- u-boot-2015.01-rc3/arch/x86/cpu/ivybridge/microcode_intel.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/x86/cpu/ivybridge/microcode_intel.c 2015-01-01 17:34:32.249503317 +0100
+@@ -40,6 +40,8 @@
+ update->data = fdt_getprop(blob, node, "data", &update->size);
+ if (!update->data)
+ return -EINVAL;
++ update->data += 48;
++ update->size -= 48;
+
+ update->header_version = fdtdec_get_int(blob, node,
+ "intel,header-version", 0);
+@@ -48,17 +50,17 @@
+ update->date_code = fdtdec_get_int(blob, node,
+ "intel,date-code", 0);
+ update->processor_signature = fdtdec_get_int(blob, node,
+- "intel.processor-signature", 0);
++ "intel,processor-signature", 0);
+ update->checksum = fdtdec_get_int(blob, node, "intel,checksum", 0);
+ update->loader_revision = fdtdec_get_int(blob, node,
+- "loader-revision", 0);
++ "intel,loader-revision", 0);
+ update->processor_flags = fdtdec_get_int(blob, node,
+- "processor-flags", 0);
++ "intel,processor-flags", 0);
+
+ return 0;
+ }
+
+-static uint32_t microcode_read_rev(void)
++static inline uint32_t microcode_read_rev(void)
+ {
+ /*
+ * Some Intel CPUs can be very finicky about the CPUID sequence used.
+@@ -114,6 +116,7 @@
+ {
+ struct microcode_update cpu, update;
+ const void *blob = gd->fdt_blob;
++ int skipped;
+ int count;
+ int node;
+ int ret;
+@@ -121,12 +124,13 @@
+ microcode_read_cpu(&cpu);
+ node = 0;
+ count = 0;
++ skipped = 0;
+ do {
+ node = fdtdec_next_compatible(blob, node,
+ COMPAT_INTEL_MICROCODE);
+ if (node < 0) {
+ debug("%s: Found %d updates\n", __func__, count);
+- return count ? 0 : -ENOENT;
++ return count ? 0 : skipped ? -EEXIST : -ENOENT;
+ }
+
+ ret = microcode_decode_node(blob, node, &update);
+@@ -135,12 +139,15 @@
+ ret);
+ return ret;
+ }
+- if (update.processor_signature == cpu.processor_signature &&
+- (update.processor_flags & cpu.processor_flags)) {
+- debug("%s: Update already exists\n", __func__);
+- return -EEXIST;
++ if (!(update.processor_signature == cpu.processor_signature &&
++ (update.processor_flags & cpu.processor_flags))) {
++ debug("%s: Skipping non-matching update, sig=%x, pf=%x\n",
++ __func__, update.processor_signature,
++ update.processor_flags);
++ skipped++;
++ continue;
+ }
+-
++ ret = microcode_read_rev();
+ wrmsr(0x79, (ulong)update.data, 0);
+ debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n",
+ microcode_read_rev(), update.date_code & 0xffff,
+diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/ivybridge/sdram.c u-boot/arch/x86/cpu/ivybridge/sdram.c
+--- u-boot-2015.01-rc3/arch/x86/cpu/ivybridge/sdram.c 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/x86/cpu/ivybridge/sdram.c 2015-01-01 17:34:32.253503252 +0100
+@@ -177,7 +177,7 @@
+
+ debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
+
+- data = (char *)CONFIG_X86_MRC_START;
++ data = (char *)CONFIG_X86_MRC_ADDR;
+ if (data) {
+ int rv;
+ int (*func)(struct pei_data *);
+diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/Makefile u-boot/arch/x86/cpu/Makefile
+--- u-boot-2015.01-rc3/arch/x86/cpu/Makefile 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/x86/cpu/Makefile 2015-01-01 17:34:32.249503317 +0100
+@@ -15,6 +15,7 @@
+ obj-$(CONFIG_SYS_COREBOOT) += coreboot/
+ obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
+ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
++obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
+ obj-y += lapic.o
+ obj-$(CONFIG_PCI) += pci.o
+ obj-y += turbo.o
+diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/fsp_configs.c u-boot/arch/x86/cpu/queensbay/fsp_configs.c
+--- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/fsp_configs.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/x86/cpu/queensbay/fsp_configs.c 2015-01-01 17:34:32.253503252 +0100
+@@ -0,0 +1,20 @@
++/*
++ * Copyright (C) 2013, Intel Corporation
++ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
++ *
++ * SPDX-License-Identifier: Intel
++ */
++
++#include <common.h>
++#include <asm/arch/fsp/fsp_support.h>
++
++void update_fsp_upd(struct upd_region *fsp_upd)
++{
++ /* Override any UPD setting if required */
++
++ /* Uncomment the line below to enable DEBUG message */
++ /* fsp_upd->serial_dbgport_type = 1; */
++
++ /* Examples on how to initialize the pointers in UPD region */
++ /* fsp_upd->pcd_example = (EXAMPLE_DATA *)&example; */
++}
+diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/fsp_support.c u-boot/arch/x86/cpu/queensbay/fsp_support.c
+--- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/fsp_support.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/x86/cpu/queensbay/fsp_support.c 2015-01-01 17:34:32.253503252 +0100
+@@ -0,0 +1,401 @@
++/*
++ * Copyright (C) 2013, Intel Corporation
++ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
++ *
++ * SPDX-License-Identifier: Intel
++ */
++
++#include <common.h>
++#include <asm/arch/fsp/fsp_support.h>
++#include <asm/post.h>
++
++/**
++ * Compares two GUIDs
++ *
++ * If the GUIDs are identical then true is returned.
++ * If there are any bit differences in the two GUIDs, then false is returned.
++ *
++ * @guid1: A pointer to a 128 bit GUID.
++ * @guid2: A pointer to a 128 bit GUID.
++ *
++ * @retval true: guid1 and guid2 are identical.
++ * @retval false: guid1 and guid2 are not identical.
++ */
++static bool compare_guid(const struct efi_guid *guid1,
++ const struct efi_guid *guid2)
++{
++ if (memcmp(guid1, guid2, sizeof(struct efi_guid)) == 0)
++ return true;
++ else
++ return false;
++}
++
++u32 __attribute__((optimize("O0"))) find_fsp_header(void)
++{
++ /*
++ * This function may be called before the a stack is established,
++ * so special care must be taken. First, it cannot declare any local
++ * variable using stack. Only register variable can be used here.
++ * Secondly, some compiler version will add prolog or epilog code
++ * for the C function. If so the function call may not work before
++ * stack is ready.
++ *
++ * GCC 4.8.1 has been verified to be working for the following codes.
++ */
++ volatile register u8 *fsp asm("eax");
++
++ /* Initalize the FSP base */
++ fsp = (u8 *)CONFIG_FSP_ADDR;
++
++ /* Check the FV signature, _FVH */
++ if (((struct fv_header *)fsp)->sign == EFI_FVH_SIGNATURE) {
++ /* Go to the end of the FV header and align the address */
++ fsp += ((struct fv_header *)fsp)->ext_hdr_off;
++ fsp += ((struct fv_ext_header *)fsp)->ext_hdr_size;
++ fsp = (u8 *)(((u32)fsp + 7) & 0xFFFFFFF8);
++ } else {
++ fsp = 0;
++ }
++
++ /* Check the FFS GUID */
++ if (fsp &&
++ ((struct ffs_file_header *)fsp)->name.data1 == FSP_GUID_DATA1 &&
++ ((struct ffs_file_header *)fsp)->name.data2 == FSP_GUID_DATA2 &&
++ ((struct ffs_file_header *)fsp)->name.data3 == FSP_GUID_DATA3 &&
++ ((struct ffs_file_header *)fsp)->name.data4[0] == FSP_GUID_DATA4_0 &&
++ ((struct ffs_file_header *)fsp)->name.data4[1] == FSP_GUID_DATA4_1 &&
++ ((struct ffs_file_header *)fsp)->name.data4[2] == FSP_GUID_DATA4_2 &&
++ ((struct ffs_file_header *)fsp)->name.data4[3] == FSP_GUID_DATA4_3 &&
++ ((struct ffs_file_header *)fsp)->name.data4[4] == FSP_GUID_DATA4_4 &&
++ ((struct ffs_file_header *)fsp)->name.data4[5] == FSP_GUID_DATA4_5 &&
++ ((struct ffs_file_header *)fsp)->name.data4[6] == FSP_GUID_DATA4_6 &&
++ ((struct ffs_file_header *)fsp)->name.data4[7] == FSP_GUID_DATA4_7) {
++ /* Add the FFS header size to find the raw section header */
++ fsp += sizeof(struct ffs_file_header);
++ } else {
++ fsp = 0;
++ }
++
++ if (fsp &&
++ ((struct raw_section *)fsp)->type == EFI_SECTION_RAW) {
++ /* Add the raw section header size to find the FSP header */
++ fsp += sizeof(struct raw_section);
++ } else {
++ fsp = 0;
++ }
++
++ return (u32)fsp;
++}
++
++void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list)
++{
++ u32 stack_len;
++ u32 stack_base;
++ u32 stack_top;
++
++ post_code(POST_MRC);
++
++ assert(status == 0);
++
++ /* Get the migrated stack in normal memory */
++ stack_base = (u32)fsp_get_bootloader_tmp_mem(hob_list, &stack_len);
++ assert(stack_base != 0);
++ stack_top = stack_base + stack_len - sizeof(u32);
++
++ /*
++ * Old stack base is stored at the very end of the stack top,
++ * use it to calculate the migrated shared data base
++ */
++ shared_data = (struct shared_data *)(stack_base +
++ ((u32)shared_data - *(u32 *)stack_top));
++
++ /* The boot loader main function entry */
++ fsp_init_done(hob_list);
++}
++
++void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
++{
++ struct shared_data shared_data;
++ fsp_init_f init;
++ struct fsp_init_params params;
++ struct fspinit_rtbuf rt_buf;
++ struct vpd_region *fsp_vpd;
++ struct fsp_header *fsp_hdr;
++ struct fsp_init_params *params_ptr;
++ struct upd_region *fsp_upd;
++
++ fsp_hdr = (struct fsp_header *)find_fsp_header();
++ if (fsp_hdr == NULL) {
++ /* No valid FSP info header was found */
++ panic("Invalid FSP header");
++ }
++
++ fsp_upd = (struct upd_region *)&shared_data.fsp_upd;
++ memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
++
++ /* Reserve a gap in stack top */
++ rt_buf.common.stack_top = (u32 *)stack_top - 32;
++ rt_buf.common.boot_mode = boot_mode;
++ rt_buf.common.upd_data = (struct upd_region *)fsp_upd;
++
++ /* Get VPD region start */
++ fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base +
++ fsp_hdr->cfg_region_off);
++
++ /* Verifify the VPD data region is valid */
++ assert((fsp_vpd->img_rev == VPD_IMAGE_REV) &&
++ (fsp_vpd->sign == VPD_IMAGE_ID));
++
++ /* Copy default data from Flash */
++ memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
++ sizeof(struct upd_region));
++
++ /* Verifify the UPD data region is valid */
++ assert(fsp_upd->terminator == UPD_TERMINATOR);
++
++ /* Override any UPD setting if required */
++ update_fsp_upd(fsp_upd);
++
++ memset(¶ms, 0, sizeof(struct fsp_init_params));
++ params.nvs_buf = nvs_buf;
++ params.rt_buf = (struct fspinit_rtbuf *)&rt_buf;
++ params.continuation = (fsp_continuation_f)asm_continuation;
++
++ init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init);
++ params_ptr = ¶ms;
++
++ shared_data.fsp_hdr = fsp_hdr;
++ shared_data.stack_top = (u32 *)stack_top;
++
++ post_code(POST_PRE_MRC);
++
++ /*
++ * Use ASM code to ensure the register value in EAX & ECX
++ * will be passed into BlContinuationFunc
++ */
++ asm volatile (
++ "pushl %0;"
++ "call *%%eax;"
++ ".global asm_continuation;"
++ "asm_continuation:;"
++ "movl %%ebx, %%eax;" /* shared_data */
++ "movl 4(%%esp), %%edx;" /* status */
++ "movl 8(%%esp), %%ecx;" /* hob_list */
++ "jmp fsp_continue;"
++ : : "m"(params_ptr), "a"(init), "b"(&shared_data)
++ );
++
++ /*
++ * Should never get here.
++ * Control will continue from fsp_continue.
++ * This line below is to prevent the compiler from optimizing
++ * structure intialization.
++ *
++ * DO NOT REMOVE!
++ */
++ init(¶ms);
++}
++
++u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase)
++{
++ fsp_notify_f notify;
++ struct fsp_notify_params params;
++ struct fsp_notify_params *params_ptr;
++ u32 status;
++
++ if (!fsp_hdr)
++ fsp_hdr = (struct fsp_header *)find_fsp_header();
++
++ if (fsp_hdr == NULL) {
++ /* No valid FSP info header */
++ panic("Invalid FSP header");
++ }
++
++ notify = (fsp_notify_f)(fsp_hdr->img_base + fsp_hdr->fsp_notify);
++ params.phase = phase;
++ params_ptr = ¶ms;
++
++ /*
++ * Use ASM code to ensure correct parameter is on the stack for
++ * FspNotify as U-Boot is using different ABI from FSP
++ */
++ asm volatile (
++ "pushl %1;" /* push notify phase */
++ "call *%%eax;" /* call FspNotify */
++ "addl $4, %%esp;" /* clean up the stack */
++ : "=a"(status) : "m"(params_ptr), "a"(notify), "m"(*params_ptr)
++ );
++
++ return status;
++}
++
++u32 fsp_get_usable_lowmem_top(const void *hob_list)
++{
++ union hob_pointers hob;
++ phys_addr_t phys_start;
++ u32 top;
++
++ /* Get the HOB list for processing */
++ hob.raw = (void *)hob_list;
++
++ /* * Collect memory ranges */
++ top = FSP_LOWMEM_BASE;
++ while (!end_of_hob(hob)) {
++ if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
++ if (hob.res_desc->type == RES_SYS_MEM) {
++ phys_start = hob.res_desc->phys_start;
++ /* Need memory above 1MB to be collected here */
++ if (phys_start >= FSP_LOWMEM_BASE &&
++ phys_start < (phys_addr_t)FSP_HIGHMEM_BASE)
++ top += (u32)(hob.res_desc->len);
++ }
++ }
++ hob.raw = get_next_hob(hob);
++ }
++
++ return top;
++}
++
++u64 fsp_get_usable_highmem_top(const void *hob_list)
++{
++ union hob_pointers hob;
++ phys_addr_t phys_start;
++ u64 top;
++
++ /* Get the HOB list for processing */
++ hob.raw = (void *)hob_list;
++
++ /* Collect memory ranges */
++ top = FSP_HIGHMEM_BASE;
++ while (!end_of_hob(hob)) {
++ if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
++ if (hob.res_desc->type == RES_SYS_MEM) {
++ phys_start = hob.res_desc->phys_start;
++ /* Need memory above 1MB to be collected here */
++ if (phys_start >= (phys_addr_t)FSP_HIGHMEM_BASE)
++ top += (u32)(hob.res_desc->len);
++ }
++ }
++ hob.raw = get_next_hob(hob);
++ }
++
++ return top;
++}
++
++u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len,
++ struct efi_guid *guid)
++{
++ union hob_pointers hob;
++
++ /* Get the HOB list for processing */
++ hob.raw = (void *)hob_list;
++
++ /* Collect memory ranges */
++ while (!end_of_hob(hob)) {
++ if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
++ if (hob.res_desc->type == RES_MEM_RESERVED) {
++ if (compare_guid(&hob.res_desc->owner, guid)) {
++ if (len)
++ *len = (u32)(hob.res_desc->len);
++
++ return (u64)(hob.res_desc->phys_start);
++ }
++ }
++ }
++ hob.raw = get_next_hob(hob);
++ }
++
++ return 0;
++}
++
++u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len)
++{
++ const struct efi_guid guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
++ u64 length;
++ u32 base;
++
++ base = (u32)fsp_get_reserved_mem_from_guid(hob_list,
++ &length, (struct efi_guid *)&guid);
++ if ((len != 0) && (base != 0))
++ *len = (u32)length;
++
++ return base;
++}
++
++u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len)
++{
++ const struct efi_guid guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID;
++ u64 length;
++ u32 base;
++
++ base = (u32)fsp_get_reserved_mem_from_guid(hob_list,
++ &length, (struct efi_guid *)&guid);
++ if ((len != 0) && (base != 0))
++ *len = (u32)length;
++
++ return base;
++}
++
++void *fsp_get_next_hob(u16 type, const void *hob_list)
++{
++ union hob_pointers hob;
++
++ assert(hob_list != NULL);
++
++ hob.raw = (u8 *)hob_list;
++
++ /* Parse the HOB list until end of list or matching type is found */
++ while (!end_of_hob(hob)) {
++ if (get_hob_type(hob) == type)
++ return hob.raw;
++
++ hob.raw = get_next_hob(hob);
++ }
++
++ return NULL;
++}
++
++void *fsp_get_next_guid_hob(const struct efi_guid *guid, const void *hob_list)
++{
++ union hob_pointers hob;
++
++ hob.raw = (u8 *)hob_list;
++ while ((hob.raw = fsp_get_next_hob(HOB_TYPE_GUID_EXT,
++ hob.raw)) != NULL) {
++ if (compare_guid(guid, &hob.guid->name))
++ break;
++ hob.raw = get_next_hob(hob);
++ }
++
++ return hob.raw;
++}
++
++void *fsp_get_guid_hob_data(const void *hob_list, u32 *len,
++ struct efi_guid *guid)
++{
++ u8 *guid_hob;
++
++ guid_hob = fsp_get_next_guid_hob(guid, hob_list);
++ if (guid_hob == NULL) {
++ return NULL;
++ } else {
++ if (len)
++ *len = get_guid_hob_data_size(guid_hob);
++
++ return get_guid_hob_data(guid_hob);
++ }
++}
++
++void *fsp_get_nvs_data(const void *hob_list, u32 *len)
++{
++ const struct efi_guid guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
++
++ return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
++}
++
++void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len)
++{
++ const struct efi_guid guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID;
++
++ return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
++}
+diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/Kconfig u-boot/arch/x86/cpu/queensbay/Kconfig
+--- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/x86/cpu/queensbay/Kconfig 2015-01-01 17:34:32.253503252 +0100
+@@ -0,0 +1,79 @@
++#
++# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++config INTEL_QUEENSBAY
++ bool
++ select HAVE_FSP
++ select HAVE_CMC
++
++if INTEL_QUEENSBAY
++
++config HAVE_FSP
++ bool "Add an Firmware Support Package binary"
++ help
++ Select this option to add an Firmware Support Package binary to
++ the resulting U-Boot image. It is a binary blob which U-Boot uses
++ to set up SDRAM and other chipset specific initialization.
++
++ Note: Without this binary U-Boot will not be able to set up its
++ SDRAM so will not boot.
++
++config FSP_FILE
++ string "Firmware Support Package binary filename"
++ depends on HAVE_FSP
++ default "fsp.bin"
++ help
++ The filename of the file to use as Firmware Support Package binary
++ in the board directory.
++
++config FSP_ADDR
++ hex "Firmware Support Package binary location"
++ depends on HAVE_FSP
++ default 0xfffc0000
++ help
++ FSP is not Position Independent Code (PIC) and the whole FSP has to
++ be rebased if it is placed at a location which is different from the
++ perferred base address specified during the FSP build. Use Intel's
++ Binary Configuration Tool (BCT) to do the rebase.
++
++ The default base address of 0xfffc0000 indicates that the binary must
++ be located at offset 0xc0000 from the beginning of a 1MB flash device.
++
++config FSP_TEMP_RAM_ADDR
++ hex
++ default 0x2000000
++ help
++ Stack top address which is used in FspInit after DRAM is ready and
++ CAR is disabled.
++
++config HAVE_CMC
++ bool "Add a Chipset Micro Code state machine binary"
++ help
++ Select this option to add a Chipset Micro Code state machine binary
++ to the resulting U-Boot image. It is a 64K data block of machine
++ specific code which must be put in the flash for the processor to
++ access when powered up before system BIOS is executed.
++
++config CMC_FILE
++ string "Chipset Micro Code state machine filename"
++ depends on HAVE_CMC
++ default "cmc.bin"
++ help
++ The filename of the file to use as Chipset Micro Code state machine
++ binary in the board directory.
++
++config CMC_ADDR
++ hex "Chipset Micro Code state machine binary location"
++ depends on HAVE_CMC
++ default 0xfffb0000
++ help
++ The location of the CMC binary is determined by a strap. It must be
++ put in flash at a location matching the strap-determined base address.
++
++ The default base address of 0xfffb0000 indicates that the binary must
++ be located at offset 0xb0000 from the beginning of a 1MB flash device.
++
++endif
+diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/Makefile u-boot/arch/x86/cpu/queensbay/Makefile
+--- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/x86/cpu/queensbay/Makefile 2015-01-01 17:34:32.253503252 +0100
+@@ -0,0 +1,9 @@
++#
++# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o
++obj-y += fsp_configs.o fsp_support.o
++obj-$(CONFIG_PCI) += tnc_pci.o
+diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/tnc.c u-boot/arch/x86/cpu/queensbay/tnc.c
+--- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/tnc.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/x86/cpu/queensbay/tnc.c 2015-01-01 17:34:32.253503252 +0100
+@@ -0,0 +1,72 @@
++/*
++ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <asm/pci.h>
++#include <asm/post.h>
++#include <asm/arch/tnc.h>
++#include <asm/arch/fsp/fsp_support.h>
++#include <asm/processor.h>
++
++static void unprotect_spi_flash(void)
++{
++ u32 bc;
++
++ bc = pci_read_config32(PCH_LPC_DEV, 0xd8);
++ bc |= 0x1; /* unprotect the flash */
++ pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
++}
++
++int arch_cpu_init(void)
++{
++ struct pci_controller *hose;
++ int ret;
++
++ post_code(POST_CPU_INIT);
++#ifdef CONFIG_SYS_X86_TSC_TIMER
++ timer_set_base(rdtsc());
++#endif
++
++ ret = x86_cpu_init_f();
++ if (ret)
++ return ret;
++
++ ret = pci_early_init_hose(&hose);
++ if (ret)
++ return ret;
++
++ unprotect_spi_flash();
++
++ return 0;
++}
++
++int print_cpuinfo(void)
++{
++ post_code(POST_CPU_INFO);
++ return default_print_cpuinfo();
++}
++
++void reset_cpu(ulong addr)
++{
++ /* cold reset */
++ outb(0x06, PORT_RESET);
++}
++
++void board_final_cleanup(void)
++{
++ u32 status;
++
++ /* call into FspNotify */
++ debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
++ status = fsp_notify(NULL, INIT_PHASE_BOOT);
++ if (status != FSP_SUCCESS)
++ debug("fail, error code %x\n", status);
++ else
++ debug("OK\n");
++
++ return;
++}
+diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/tnc_car.S u-boot/arch/x86/cpu/queensbay/tnc_car.S
+--- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/tnc_car.S 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/x86/cpu/queensbay/tnc_car.S 2015-01-01 17:34:32.253503252 +0100
+@@ -0,0 +1,124 @@
++/*
++ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <config.h>
++#include <asm/post.h>
++
++.globl car_init
++car_init:
++ /*
++ * Note: ebp holds the BIST value (built-in self test) so far, but ebp
++ * will be destroyed through the FSP call, thus we have to test the
++ * BIST value here before we call into FSP.
++ */
++ test %ebp, %ebp
++ jz car_init_start
++ post_code(POST_BIST_FAILURE)
++ jmp die
++
++car_init_start:
++ post_code(POST_CAR_START)
++ lea find_fsp_header_romstack, %esp
++ jmp find_fsp_header
++
++find_fsp_header_ret:
++ /* EAX points to FSP_INFO_HEADER */
++ mov %eax, %ebp
++
++ /* sanity test */
++ cmp $CONFIG_FSP_ADDR, %eax
++ jb die
++
++ /* calculate TempRamInitEntry address */
++ mov 0x30(%ebp), %eax
++ add 0x1c(%ebp), %eax
++
++ /* call FSP TempRamInitEntry to setup temporary stack */
++ lea temp_ram_init_romstack, %esp
++ jmp *%eax
++
++temp_ram_init_ret:
++ addl $4, %esp
++ cmp $0, %eax
++ jnz car_init_fail
++
++ post_code(POST_CAR_CPU_CACHE)
++
++ /*
++ * The FSP TempRamInit initializes the ecx and edx registers to
++ * point to a temporary but writable memory range (Cache-As-RAM).
++ * ecx: the start of this temporary memory range,
++ * edx: the end of this range.
++ */
++
++ /* stack grows down from top of CAR */
++ movl %edx, %esp
++
++ /*
++ * TODO:
++ *
++ * According to FSP architecture spec, the fsp_init() will not return
++ * to its caller, instead it requires the bootloader to provide a
++ * so-called continuation function to pass into the FSP as a parameter
++ * of fsp_init, and fsp_init() will call that continuation function
++ * directly.
++ *
++ * The call to fsp_init() may need to be moved out of the car_init()
++ * to cpu_init_f() with the help of some inline assembly codes.
++ * Note there is another issue that fsp_init() will setup another stack
++ * using the fsp_init parameter stack_top after DRAM is initialized,
++ * which means any data on the previous stack (on the CAR) gets lost
++ * (ie: U-Boot global_data). FSP is supposed to support such scenario,
++ * however it does not work. This should be revisited in the future.
++ */
++ movl $CONFIG_FSP_TEMP_RAM_ADDR, %eax
++ xorl %edx, %edx
++ xorl %ecx, %ecx
++ call fsp_init
++
++.global fsp_init_done
++fsp_init_done:
++ /*
++ * We come here from FspInit with eax pointing to the HOB list.
++ * Save eax to esi temporarily.
++ */
++ movl %eax, %esi
++ /*
++ * Re-initialize the ebp (BIST) to zero, as we already reach here
++ * which means we passed BIST testing before.
++ */
++ xorl %ebp, %ebp
++ jmp car_init_ret
++
++car_init_fail:
++ post_code(POST_CAR_FAILURE)
++
++die:
++ hlt
++ jmp die
++ hlt
++
++ /*
++ * The function call before CAR initialization is tricky. It cannot
++ * be called using the 'call' instruction but only the 'jmp' with
++ * the help of a handcrafted stack in the ROM. The stack needs to
++ * contain the function return address as well as the parameters.
++ */
++ .balign 4
++find_fsp_header_romstack:
++ .long find_fsp_header_ret
++
++ .balign 4
++temp_ram_init_romstack:
++ .long temp_ram_init_ret
++ .long temp_ram_init_params
++temp_ram_init_params:
++_dt_ucode_base_size:
++ /* These next two fields are filled in by ifdtool */
++ .long 0 /* microcode base */
++ .long 0 /* microcode size */
++ .long CONFIG_SYS_MONITOR_BASE /* code region base */
++ .long CONFIG_SYS_MONITOR_LEN /* code region size */
+diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/tnc_dram.c u-boot/arch/x86/cpu/queensbay/tnc_dram.c
+--- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/tnc_dram.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/x86/cpu/queensbay/tnc_dram.c 2015-01-01 17:34:32.253503252 +0100
+@@ -0,0 +1,78 @@
++/*
++ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/arch/fsp/fsp_support.h>
++#include <asm/e820.h>
++#include <asm/post.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int dram_init(void)
++{
++ phys_size_t ram_size = 0;
++ union hob_pointers hob;
++
++ hob.raw = gd->arch.hob_list;
++ while (!end_of_hob(hob)) {
++ if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
++ if (hob.res_desc->type == RES_SYS_MEM ||
++ hob.res_desc->type == RES_MEM_RESERVED) {
++ ram_size += hob.res_desc->len;
++ }
++ }
++ hob.raw = get_next_hob(hob);
++ }
++
++ gd->ram_size = ram_size;
++ post_code(POST_DRAM);
++
++ return 0;
++}
++
++void dram_init_banksize(void)
++{
++ gd->bd->bi_dram[0].start = 0;
++ gd->bd->bi_dram[0].size = gd->ram_size;
++}
++
++/*
++ * This function looks for the highest region of memory lower than 4GB which
++ * has enough space for U-Boot where U-Boot is aligned on a page boundary.
++ * It overrides the default implementation found elsewhere which simply
++ * picks the end of ram, wherever that may be. The location of the stack,
++ * the relocation address, and how far U-Boot is moved by relocation are
++ * set in the global data structure.
++ */
++ulong board_get_usable_ram_top(ulong total_size)
++{
++ return fsp_get_usable_lowmem_top(gd->arch.hob_list);
++}
++
++unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
++{
++ unsigned num_entries = 0;
++
++ union hob_pointers hob;
++
++ hob.raw = gd->arch.hob_list;
++
++ while (!end_of_hob(hob)) {
++ if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
++ entries[num_entries].addr = hob.res_desc->phys_start;
++ entries[num_entries].size = hob.res_desc->len;
++
++ if (hob.res_desc->type == RES_SYS_MEM)
++ entries[num_entries].type = E820_RAM;
++ else if (hob.res_desc->type == RES_MEM_RESERVED)
++ entries[num_entries].type = E820_RESERVED;
++ }
++ hob.raw = get_next_hob(hob);
++ num_entries++;
++ }
++
++ return num_entries;
++}
+diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/tnc_pci.c u-boot/arch/x86/cpu/queensbay/tnc_pci.c
+--- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/tnc_pci.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/x86/cpu/queensbay/tnc_pci.c 2015-01-01 17:34:32.253503252 +0100
+@@ -0,0 +1,61 @@
++/*
++ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <pci.h>
++#include <asm/pci.h>
++#include <asm/arch/fsp/fsp_support.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++void board_pci_setup_hose(struct pci_controller *hose)
++{
++ hose->first_busno = 0;
++ hose->last_busno = 0;
++
++ /* PCI memory space */
++ pci_set_region(hose->regions + 0,
++ CONFIG_PCI_MEM_BUS,
++ CONFIG_PCI_MEM_PHYS,
++ CONFIG_PCI_MEM_SIZE,
++ PCI_REGION_MEM);
++
++ /* PCI IO space */
++ pci_set_region(hose->regions + 1,
++ CONFIG_PCI_IO_BUS,
++ CONFIG_PCI_IO_PHYS,
++ CONFIG_PCI_IO_SIZE,
++ PCI_REGION_IO);
++
++ pci_set_region(hose->regions + 2,
++ CONFIG_PCI_PREF_BUS,
++ CONFIG_PCI_PREF_PHYS,
++ CONFIG_PCI_PREF_SIZE,
++ PCI_REGION_PREFETCH);
++
++ pci_set_region(hose->regions + 3,
++ 0,
++ 0,
++ gd->ram_size,
++ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
++
++ hose->region_count = 4;
++}
++
++int board_pci_post_scan(struct pci_controller *hose)
++{
++ u32 status;
++
++ /* call into FspNotify */
++ debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
++ status = fsp_notify(NULL, INIT_PHASE_PCI);
++ if (status != FSP_SUCCESS)
++ debug("fail, error code %x\n", status);
++ else
++ debug("OK\n");
++
++ return 0;
++}
+diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/topcliff.c u-boot/arch/x86/cpu/queensbay/topcliff.c
+--- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/topcliff.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/x86/cpu/queensbay/topcliff.c 2015-01-01 17:34:32.253503252 +0100
+@@ -0,0 +1,47 @@
++/*
++ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <errno.h>
++#include <malloc.h>
++#include <pci.h>
++#include <pci_ids.h>
++#include <sdhci.h>
++
++static struct pci_device_id mmc_supported[] = {
++ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
++ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
++ { }
++};
++
++int cpu_mmc_init(bd_t *bis)
++{
++ struct sdhci_host *mmc_host;
++ pci_dev_t devbusfn;
++ u32 iobase;
++ int ret;
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) {
++ devbusfn = pci_find_devices(mmc_supported, i);
++ if (devbusfn == -1)
++ return -ENODEV;
++
++ mmc_host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
++ if (!mmc_host)
++ return -ENOMEM;
++
++ mmc_host->name = "Topcliff SDHCI";
++ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
++ mmc_host->ioaddr = (void *)iobase;
++ mmc_host->quirks = 0;
++ ret = add_sdhci(mmc_host, 0, 0);
++ if (ret)
++ return ret;
++ }
++
++ return 0;
++}
+diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/start.S u-boot/arch/x86/cpu/start.S
+--- u-boot-2015.01-rc3/arch/x86/cpu/start.S 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/x86/cpu/start.S 2015-01-01 17:34:32.253503252 +0100
+@@ -1,5 +1,5 @@
+ /*
+- * U-boot - x86 Startup Code
++ * U-Boot - x86 Startup Code
+ *
+ * (C) Copyright 2008-2011
+ * Graeme Russ, <graeme.russ@gmail.com>
+@@ -17,6 +17,7 @@
+ #include <asm/processor.h>
+ #include <asm/processor-flags.h>
+ #include <generated/generic-asm-offsets.h>
++#include <generated/asm-offsets.h>
+
+ .section .text
+ .code32
+@@ -74,6 +75,7 @@
+ jmp car_init
+ .globl car_init_ret
+ car_init_ret:
++#ifndef CONFIG_HAVE_FSP
+ /*
+ * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM,
+ * or fully initialised SDRAM - we really don't care which)
+@@ -94,6 +96,12 @@
+ #ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
+ subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp
+ #endif
++#else
++ /*
++ * When we get here after car_init, esp points to a temporary stack
++ * and esi holds the HOB list address returned by the FSP.
++ */
++#endif
+
+ /* Reserve space on stack for global data */
+ subl $GENERATED_GBL_DATA_SIZE, %esp
+@@ -108,6 +116,13 @@
+ movl %esp, %edi
+ rep stosb
+
++#ifdef CONFIG_HAVE_FSP
++ /* Store HOB list */
++ movl %esp, %edx
++ addl $GD_HOB_LIST, %edx
++ movl %esi, (%edx)
++#endif
++
+ /* Setup first parameter to setup_gdt, pointer to global_data */
+ movl %esp, %eax
+
+diff -ruN u-boot-2015.01-rc3/arch/x86/dts/chromebook_link.dts u-boot/arch/x86/dts/chromebook_link.dts
+--- u-boot-2015.01-rc3/arch/x86/dts/chromebook_link.dts 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/x86/dts/chromebook_link.dts 2015-01-01 17:34:32.253503252 +0100
+@@ -214,10 +214,10 @@
+
+ microcode {
+ update@0 {
+-#include "m12206a7_00000028.dtsi"
++#include "microcode/m12206a7_00000029.dtsi"
+ };
+ update@1 {
+-#include "m12306a9_00000017.dtsi"
++#include "microcode/m12306a9_0000001b.dtsi"
+ };
+ };
+
+diff -ruN u-boot-2015.01-rc3/arch/x86/dts/coreboot.dtsi u-boot/arch/x86/dts/coreboot.dtsi
+--- u-boot-2015.01-rc3/arch/x86/dts/coreboot.dtsi 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/x86/dts/coreboot.dtsi 2015-01-01 17:34:32.253503252 +0100
+@@ -6,7 +6,7 @@
+ };
+
+ serial {
+- compatible = "coreboot-uart";
++ compatible = "x86-uart";
+ reg = <0x3f8 0x10>;
+ reg-shift = <0>;
+ io-mapped = <1>;
+diff -ruN u-boot-2015.01-rc3/arch/x86/dts/crownbay.dts u-boot/arch/x86/dts/crownbay.dts
+--- u-boot-2015.01-rc3/arch/x86/dts/crownbay.dts 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/x86/dts/crownbay.dts 2015-01-01 17:34:32.253503252 +0100
+@@ -0,0 +1,60 @@
++/*
++ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++/dts-v1/;
++
++/include/ "coreboot.dtsi"
++
++/ {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ model = "Intel Crown Bay";
++ compatible = "intel,crownbay", "intel,queensbay";
++
++ config {
++ silent_console = <0>;
++ };
++
++ gpioa {
++ compatible = "intel,ich6-gpio";
++ u-boot,dm-pre-reloc;
++ reg = <0 0x20>;
++ bank-name = "A";
++ };
++
++ gpiob {
++ compatible = "intel,ich6-gpio";
++ u-boot,dm-pre-reloc;
++ reg = <0x20 0x20>;
++ bank-name = "B";
++ };
++
++ serial {
++ reg = <0x3f8 8>;
++ clock-frequency = <115200>;
++ };
++
++ chosen { };
++ memory { device_type = "memory"; reg = <0 0>; };
++
++ spi {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "intel,ich7";
++ spi-flash@0 {
++ reg = <0>;
++ compatible = "sst,25vf016b", "spi-flash";
++ memory-map = <0xffe00000 0x00200000>;
++ };
++ };
++
++ microcode {
++ update@0 {
++#include "microcode/m0220661105_cv.dtsi"
++ };
++ };
++
++};
+diff -ruN u-boot-2015.01-rc3/arch/x86/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h u-boot/arch/x86/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h
+diff -ruN u-boot-2015.01-rc3/arch/x86/dts/include/dt-bindings/reset/altr,rst-mgr.h u-boot/arch/x86/dts/include/dt-bindings/reset/altr,rst-mgr.h
+diff -ruN u-boot-2015.01-rc3/arch/x86/dts/link.dts u-boot/arch/x86/dts/link.dts
+--- u-boot-2015.01-rc3/arch/x86/dts/link.dts 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/x86/dts/link.dts 2015-01-01 17:34:32.253503252 +0100
+@@ -214,10 +214,10 @@
+
+ microcode {
+ update@0 {
+-#include "m12206a7_00000028.dtsi"
++#include "microcode/m12206a7_00000029.dtsi"
+ };
+ update@1 {
+-#include "m12306a9_00000017.dtsi"
++#include "microcode/m12306a9_0000001b.dtsi"
+ };
+ };
+
+diff -ruN u-boot-2015.01-rc3/arch/x86/dts/m12206a7_00000028.dtsi u-boot/arch/x86/dts/m12206a7_00000028.dtsi
+--- u-boot-2015.01-rc3/arch/x86/dts/m12206a7_00000028.dtsi 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/x86/dts/m12206a7_00000028.dtsi 1970-01-01 01:00:00.000000000 +0100
+@@ -1,622 +0,0 @@
+-/*
+- * Copyright (c) <1995-2013>, Intel Corporation.
+- * All rights reserved.
+- *
+- * Redistribution. Redistribution and use in binary form, without modification, are
+- * permitted provided that the following conditions are met:
+- * .Redistributions must reproduce the above copyright notice and the following
+- * disclaimer in the documentation and/or other materials provided with the
+- * distribution.
+- * Neither the name of Intel Corporation nor the names of its suppliers may be used
+- * to endorse or promote products derived from this software without specific prior
+- * written permission.
+- * .No reverse engineering, decompilation, or disassembly of this software is
+- * permitted.
+- * ."Binary form" includes any format commonly used for electronic conveyance
+- * which is a reversible, bit-exact translation of binary representation to ASCII or
+- * ISO text, for example, "uuencode."
+- *
+- * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+- * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+- *
+- *---
+- * This is a device tree fragment. Use #include to add these properties to a
+- * node.
+- */
+-
+-compatible = "intel,microcode";
+-intel,header-version = <1>;
+-intel,update-revision = <0x28>;
+-intel,date-code = <0x04242012>;
+-intel,processor-signature = <0x000206a7>;
+-intel,checksum = <0xf3e9935d>;
+-intel,loader-revision = <1>;
+-intel,processor-flags = <0x12>;
+-
+-/* The 48-byte public header is omitted. */
+-data = <
+- 0x00000000 0x000000a1 0x00020001 0x00000028
+- 0x00000000 0x00000000 0x20120423 0x000008f1
+- 0x00000001 0x000206a7 0x00000000 0x00000000
+- 0x00000000 0x00000000 0x00000000 0x00000000
+- 0x00000000 0x000008f1 0x00000000 0x00000000
+- 0x00000000 0x00000000 0x00000000 0x00000000
+- 0x52b813ac 0xdb8994c7 0x70e9f6bb 0x9d6db2ff
+- 0xf4d70f5d 0x5b1eccf6 0xac59106f 0x0ae2e2c1
+- 0x1a7bbeb1 0x355a1d62 0x2e7eb594 0x09f8dea9
+- 0x432a49e4 0xbf520253 0xdafa4010 0x893a858a
+- 0x766e0efb 0xd91e196d 0x838bd2ef 0xe5146494
+- 0xd515f413 0x29704828 0xe85598b6 0xdcbe6c51
+- 0x88eabbfa 0xa1e8909f 0xd8931721 0x35386554
+- 0x089a78a7 0xd9914775 0xd4644748 0x1556a4dc
+- 0xf44448f6 0xd054d7db 0xf30f2b7d 0x5ae223d0
+- 0xcbbb48b0 0x5c8b0383 0x177de157 0x9c1e5f73
+- 0x2ec28289 0xd72a7b6c 0x823b6eb2 0x35e02171
+- 0xba8deae4 0x06f4d468 0x13dbafaa 0x72b419f1
+- 0x033385b5 0x05806920 0x4c6034cf 0x9bd117dc
+- 0x976e2d04 0x250330f0 0x7250b5e1 0x184980c2
+- 0x12a9d7d6 0x1bc808f9 0xae79994f 0xc6f87901
+- 0xc0e3132f 0x671491c5 0x236cad39 0x37889d9c
+- 0x67f7c3f3 0x964a6be5 0xbcced7da 0x57eeaa6e
+- 0x7bca1522 0x654fee4c 0x2a1ca5d9 0xa1803cf3
+- 0x00000011 0x8c316d2c 0x17603b7e 0x32e42981
+- 0xc26c1400 0xf0fbccb6 0xeab6b43a 0x11d456a5
+- 0x5b912d46 0x15195fe0 0x542f6db3 0x0b7f212e
+- 0x47718dd9 0x7c41b108 0x06c21111 0x4445d5ea
+- 0xb4fb8128 0xe07404a6 0x8d503da4 0x78fc7e44
+- 0xb9919656 0x9968c797 0x87f26ab0 0x23bb1af7
+- 0x1ec5d761 0x26f30d2c 0x7cdb747c 0xe4d42033
+- 0x8a5d4801 0x768aff57 0xbcfd5d11 0x7c853c2d
+- 0x231e6207 0x8b1988a6 0xd68fdb75 0x58dcb417
+- 0x44422ef9 0x2a186ebb 0x7d27e85f 0x36ac31f7
+- 0x1e487e77 0x2b0b8c37 0xd8ba682f 0x2cba791b
+- 0xe6d3dece 0x1b2c2a99 0x4e5decab 0xfbd313a3
+- 0xdbc78294 0x5a80cce7 0x2d8e0f0b 0xcf564f71
+- 0x073d1f37 0x25162870 0x96cdb85b 0x9c553048
+- 0x24eba740 0xfc0f352e 0x0c83be68 0x89b5076c
+- 0xc39c4355 0x6a4cf25c 0x2bbd2682 0xc524fdb9
+- 0x7ea19bae 0x191ad6f1 0xd3fbf3bf 0x21bf77fa
+- 0x8f77fec4 0x0f90f635 0xe55e165c 0x868d58c0
+- 0x966bc0ad 0x6c276364 0x9d8f7eff 0x4b7925d4
+- 0x8b2f9326 0x4ab7b47e 0x33a9087c 0xf31ab949
+- 0x69831dfb 0x4711a215 0x8128c1fa 0x8481c213
+- 0x7401b01b 0xfdcfdc50 0xd6b55266 0xae9b23ac
+- 0xfa2ad275 0xa225bb45 0x4dd720c4 0x760a20e6
+- 0x5f1223c9 0x2f334372 0x6e1dcdab 0xe8ee8638
+- 0x1c19ba8a 0xef9341c4 0x360aaa9d 0x90452ea9
+- 0x65852446 0xe9398fa3 0xbba6a631 0x1a3e90b9
+- 0xe2a73a56 0x6e8c0747 0x35c7c53d 0xcc1ac842
+- 0x183356af 0xb6e98608 0x987b43c2 0xa8a3cfd2
+- 0xc2c5fce0 0xcc3af64a 0xd6d3a291 0xe59ad1f5
+- 0x124ca513 0x9522b50a 0x25150477 0xa2eb5797
+- 0x7fc63626 0x648c48e3 0x9f5797ff 0x2307b84d
+- 0x980625a4 0xabc05983 0x24980807 0x773c4f99
+- 0x3407b872 0x07c3657a 0xa2cd9e48 0x49c1e6a8
+- 0xa881b84c 0xf804d72c 0xb5319d2a 0x3e39780f
+- 0x97518822 0x0acd54c2 0x0721a9ff 0x10e1d2fd
+- 0xa7b6db77 0x845b1a56 0xef00160e 0x6b41bfd5
+- 0xc994df0d 0xcf44a5ca 0x794b36a4 0xf9fdb127
+- 0x922a1366 0x822aa8a9 0x4b137bd5 0x5722a49f
+- 0x8933719a 0x17edc1a9 0x079d9538 0x21fae7d5
+- 0xe534fd73 0x9d3038d5 0x48c3a056 0x5b22d58a
+- 0x6f142866 0xf1d767cd 0xb51ad5a6 0x34a0ef85
+- 0x0111703e 0xca4b3a30 0xa0f3c34d 0x9d48775a
+- 0x3f2059f9 0xf2fe2c36 0x588861a9 0xed5bd9fe
+- 0x8231f7cb 0x8c115969 0x3f82ba00 0x21b3730c
+- 0xba757997 0x3ec0bb2c 0x16f11def 0x5d4356c6
+- 0xdc2e0bc2 0x58c1eb6e 0x313ede0c 0xb68fcc52
+- 0x84d3e1b5 0xcc6d9201 0x95046196 0x276b527b
+- 0x80a4a729 0xe782916d 0x5cf09e0b 0x98aaf9fa
+- 0x1de6dd43 0xab4f1962 0x49ece734 0x81455488
+- 0xc2597b61 0x5b22af85 0x646f7b94 0x09213a1f
+- 0x08edf7e4 0x963d343c 0x059ba888 0xb4e804ed
+- 0xe7cc826c 0xf87bafc7 0xeecaec10 0x8e60919c
+- 0xbf14c996 0xd3dcaee3 0xb8fa0b7e 0x81563c6e
+- 0x7f59a258 0x2f344446 0x374d8aa6 0x9b6de5c9
+- 0xbf992857 0xbc5b94fc 0x28adb080 0x17e41044
+- 0xb87b469e 0xda504d12 0xf21bef8b 0xce75c1e3
+- 0xdbd92c83 0x58bba0af 0x77b42977 0x506cfd75
+- 0x1139e875 0x6ce5fe43 0xc6a5d7b3 0x87f9e628
+- 0x7b5c500b 0x130066b3 0x789b611f 0xec8c1ba9
+- 0xb7e6872d 0xaf828cd6 0xc28d3316 0x2a91f6d0
+- 0xc725f063 0x065ac531 0x4f9ef4b8 0x2b9d927e
+- 0xaf54f3f9 0x7c924f72 0xda1d77ad 0xff00db67
+- 0xaf4f03c0 0xb4f4ee64 0x169e64e5 0x04653ac0
+- 0xed51cb70 0xfeaff0e5 0x51dbf346 0x072a2407
+- 0x23fb74f4 0x9a906eef 0x5d6fc3f0 0xbc3c374c
+- 0x1cf9f063 0x919015d9 0x5b3e9d07 0xd6209d8b
+- 0xa3710b3d 0x90ad23b8 0x420ceedc 0x58e8371f
+- 0x5d419d1f 0xb8acd13f 0x7d100d6d 0x210c10d1
+- 0xcd0a697e 0x5023db4b 0x33e6d8e7 0x44bbe6b4
+- 0x827e859f 0x6ca4cc81 0x661bb2c3 0x71209ee8
+- 0xb8c3ffaf 0xd1075f51 0xba1eae10 0x728b0a6a
+- 0xe4af7a2f 0xca9bcf2e 0xb249a631 0xdce6be47
+- 0x5c910321 0x425c3c27 0x33083e43 0xdea067ae
+- 0xea594a23 0x41b75c2c 0x3a401a95 0xd33cd88a
+- 0xc295cad0 0x67f48045 0x1dc9ad4c 0x4bc48864
+- 0x53991b6e 0x7aadde5f 0x2b0bf775 0x06ba5380
+- 0x9eb874be 0x2c4b967a 0x1bcc342f 0xe875001b
+- 0x15b5642d 0x5be99c9d 0xcb210ace 0x1b4924ad
+- 0x3793ed81 0x8b983114 0x3ec33981 0x75ec71e7
+- 0x8b5b7df3 0x834756f4 0x100fad01 0x70037fdf
+- 0x0cef9a36 0x3d9e3a2d 0x38b48efd 0xfc4034b6
+- 0xa32e29dd 0x388944bc 0xc1c15614 0x3877e9c7
+- 0xa5e733fa 0xa621bd53 0x4b651df6 0xce082970
+- 0x85f30d6f 0x729a5c87 0x31dd7ba9 0xdb495828
+- 0x7b12c698 0x953495c9 0x6b5f99e7 0x2cc42fa8
+- 0x697ac512 0x1be679de 0xc116d305 0x94a36606
+- 0x9e5e141e 0x874affed 0x58d40b0b 0x5e3cf5e5
+- 0x5d05e9a9 0x06840efc 0xd2f98b21 0xa1e83ab2
+- 0x4f726202 0xa6394535 0x62a02403 0x9f2167ec
+- 0x4f9fc77b 0x98073be4 0x2bc781fa 0xfc8e4c89
+- 0xc7179b97 0x692cf793 0x708ff7bb 0x12ecba93
+- 0xacd06e21 0x202bef76 0x03852241 0xe84e02a1
+- 0xf1f9ac8d 0xcee61aef 0x61a4f235 0xd22991eb
+- 0x67a81345 0x375a15c6 0xe8fae8a3 0xb4ff2b37
+- 0x339ee4ea 0x14ffadc3 0xf49340dd 0xf285e568
+- 0x00fc6970 0x369c52d1 0x4f55368f 0x3f4d75f1
+- 0x6a73b603 0x963c1f59 0x171e2bdc 0x72bac76b
+- 0x9e2e5c32 0x307f7c3f 0xd3b48637 0x3a917acf
+- 0xea52a65f 0xecd209fb 0xf0ad84bf 0xd4bdea70
+- 0xa2647b38 0xce040b49 0xc6d5f13d 0x5d942c52
+- 0xf8edc042 0x798fdefd 0x4b074246 0x1cb1873a
+- 0x6793c186 0x23b9c774 0x77bb0202 0xc519b3aa
+- 0xa30c09a2 0xe1f6669a 0xb7eddb8d 0x7aaa91d6
+- 0x076a3789 0x0ac47791 0x1e503404 0x44fe8c54
+- 0xf3cbbf49 0xd3234eef 0x0d898b3f 0xe854984b
+- 0xe3986de9 0x923a5c76 0x2ee9abca 0x1a9fedbe
+- 0xdf76dcd1 0xea07936b 0xcdaaf247 0xe62d98fa
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+- 0x0b074cfa 0xd26d4f99 0x3b43320b 0x230b680b
+- 0x9908f2d2 0xcbcb1952 0xf45a2f53 0x7b4564c6
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+- 0xe0a30a98 0x4c2bcf4f 0xd87acedd 0x19682d7a
+- 0xf97c025c 0x55d8feb3 0xbcd4d2ff 0x236c6f9f
+- 0x8ba0246d 0x42812f73 0x327636f5 0xc92cd30a
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+- 0x7077b1d1 0x17b05834 0xfa24bc02 0xf49f4473
+- 0x8f9ac6b4 0xa880c630 0xf7457b4d 0xd5f829e4
+- 0x25c49a99 0x1176a997 0xbb2d2009 0x61d35764
+- 0xa322c752 0x6ef3ae02 0x5faae6f8 0x9a52acf1
+- 0x19176f43 0x43843b07 0x14efc471 0xee474403
+- 0x319c4857 0xa19adcf0 0xc0a466e1 0x02db14ad
+- 0xb7f211f3 0x72aa6ca6 0x0eb9bffe 0x48a6d284
+- 0x9a93a2ee 0xac09fc5f 0x92a62c4f 0xd34f0271
+- 0xffb348c7 0xf229b6e2 0xc68ec1ca 0x19577dbc
+- 0x069a10bf 0xf64ac347 0xf7c3c848 0x81975294
+- 0x6376e550 0x93b53440 0x8bb17daa 0xc4c64c07
+- 0xcaeff293 0xd51497b0 0x33da3565 0xa73d5def
+- 0x4bf4dcde 0xfb470fcd 0xca7db864 0x7ef17022
+- 0x47567363 0xd8fb8d74 0xa68c3c72 0x8202e4f3
+- 0x75bf1798 0x16a70fd2 0xcc3b697f 0xab9a1075
+- 0x13f56ef3 0x269d0302 0xcb655a43 0xc9a4de88
+- 0xfb8363de 0xff40f36d 0xd2555489 0x647a7995
+- 0xfd8eda6e 0xa3958c9a 0x20e029b4 0xbed3e225
+- 0xa7df5f17 0x63bc3c1a 0x337ecc9d 0x6c329508
+- 0x786aa47e 0x1db5b093 0xc0acd73b 0xf9587237
+- 0x243e5d40 0xd3623c3a 0x338c4740 0xb672140e
+- 0x43640a9b 0xb7ef3f6a 0x44151074 0x749bcc46
+- 0xfa1f103b 0x0fefb19e 0x58855538 0x138ad276
+- 0x2641fd80 0x297d99d0 0xfaa63ba2 0x00b6f11a
+- 0x3793fb6b 0x124763a1 0x8b9419ac 0x56abf9eb
+- 0xdbf83419 0x43570571 0x37299cd8 0x8b201e62
+- 0xa4058fa5 0xb320e91b 0xbe7d40b7 0x4eca3b2d
+- 0x8519c155 0xf4b17021 0x9e4c572a 0xdc1f9e16
+- 0x39a589a3 0xa6cfc7a8 0x5b986910 0x64e150e7
+- 0x60b6f2c1 0x02bacd3f 0x2f3b5a5c 0xc6f453a8
+- 0x15a87a7e 0x76104a14 0xafa2ef63 0x2cd48dbe
+- 0x3c7abddc 0xd786ea5a 0x4f65867a 0x355cda38
+- 0x2ae03d9e 0x4f11f6be 0xfc0a0034 0xde4ea602
+- 0x21ff83ea 0x0f12d913 0xedf4da28 0xc96d8fd1
+- 0xd7e82c3c 0xfec63bdc 0x37a456d7 0x3007e18c
+- 0x091a47b6 0x82f1c641 0x82219cce 0x3e7e6993
+- 0x7b3a2115 0x0b8e1a02 0x40f88213 0xfa2f9c21
+- >;
+diff -ruN u-boot-2015.01-rc3/arch/x86/dts/m12306a9_00000017.dtsi u-boot/arch/x86/dts/m12306a9_00000017.dtsi
+--- u-boot-2015.01-rc3/arch/x86/dts/m12306a9_00000017.dtsi 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/x86/dts/m12306a9_00000017.dtsi 1970-01-01 01:00:00.000000000 +0100
+@@ -1,750 +0,0 @@
+-/*
+- * Copyright (c) <1995-2013>, Intel Corporation.
+- * All rights reserved.
+- *
+- * Redistribution. Redistribution and use in binary form, without modification, are
+- * permitted provided that the following conditions are met:
+- * .Redistributions must reproduce the above copyright notice and the following
+- * disclaimer in the documentation and/or other materials provided with the
+- * distribution.
+- * Neither the name of Intel Corporation nor the names of its suppliers may be used
+- * to endorse or promote products derived from this software without specific prior
+- * written permission.
+- * .No reverse engineering, decompilation, or disassembly of this software is
+- * permitted.
+- * ."Binary form" includes any format commonly used for electronic conveyance
+- * which is a reversible, bit-exact translation of binary representation to ASCII or
+- * ISO text, for example, "uuencode."
+- *
+- * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+- * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+- *
+- *---
+- * This is a device tree fragment. Use #include to add these properties to a
+- * node.
+- */
+-
+-compatible = "intel,microcode";
+-intel,header-version = <1>;
+-intel,update-revision = <0x17>;
+-intel,date-code = <0x01092013>;
+-intel,processor-signature = <0x000306a9>;
+-intel,checksum = <0x3546450b>;
+-intel,loader-revision = <1>;
+-intel,processor-flags = <0x12>;
+-
+-/* The 48-byte public header is omitted. */
+-data = <
+- 0x00000000 0x000000a1 0x00020001 0x00000017
+- 0x00000000 0x00000000 0x20130107 0x00000a61
+- 0x00000001 0x000306a9 0x00000000 0x00000000
+- 0x00000000 0x00000000 0x00000000 0x00000000
+- 0x00000000 0x00000000 0x00000000 0x00000000
+- 0x00000000 0x00000000 0x00000000 0x00000000
+- 0x86c5b0d4 0xf6978804 0x7f4f5870 0x6319dc3c
+- 0xbb3b7d61 0x33cf9075 0xe8424658 0xf611a357
+- 0x5a3401db 0x42caecce 0xb4d8e75e 0xe6dbaf24
+- 0x7861b35f 0x6bd717bc 0x23b9b731 0x82ec1ac8
+- 0x20337b64 0x5396dbf1 0x59973bff 0x724bc7e9
+- 0x5237193b 0x0b8647c1 0x6a0d0e16 0xbf9ddb5b
+- 0xace2cc1c 0xad707638 0x056f102f 0xa37e60f8
+- 0x76255642 0xfb86e030 0xb8069a40 0x367795f1
+- 0x653fb05e 0xab7f14ad 0xb6e8a8e1 0xd2598d20
+- 0x2eba3f68 0x78b372f1 0xba8d13f8 0x1f1de861
+- 0x97f951d5 0x8097c728 0x27dbf904 0xb97906a8
+- 0xffe7a4ac 0x4b947668 0xc1dbd726 0x2adcf777
+- 0x63b1bcf0 0x818e2a1b 0x49aa907b 0x2faf5e8d
+- 0xae842352 0x82707fae 0x0aa12b41 0xa0bae11c
+- 0xb4298c47 0xd2b4099c 0x4ff625f2 0xcd2630d4
+- 0x79850981 0x05dbf57d 0xb05b81a5 0x56e73ec7
+- 0x95cb3897 0xe262bda5 0xb2c6e288 0xcb7f8e77
+- 0x72b8bdd3 0x3f400494 0x63ade65b 0xbc4adc71
+- 0x00000011 0x06c0f8ff 0x0eb63d77 0xc54cdabf
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+- 0xd208ae00 0xfe8c2b5c 0x9a457293 0xd9365ac4
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+- 0x77c8ef6b 0x8369aeb1 0x71bc947f 0x0c6b49d8
+- 0x8ddd0513 0x028ad10d 0x99a1b28f 0xe6cfbdc8
+- 0x7978b4a6 0x3ebbade8 0x9985f5cf 0x431f42f1
+- 0x004372b2 0x18b67f68 0x20111c21 0xbb6f77ff
+- 0x1783b030 0xa045d7d1 0x0e9c7e09 0x3ccbd95f
+- 0x0b84a2ed 0xf0ee3325 0x63f2e126 0x5ec4c67b
+- 0x2ca782cc 0xcaf20d04 0x8b59d515 0x3212aa33
+- 0x335ca0c3 0x6f9e0cdd 0x4d4bf189 0x44d2fa0c
+- 0x5abe9396 0x492794ee 0x10dcfcb1 0x9acda9bd
+- 0xe8aa2803 0x3f1b9605 0x3e2ecb5a 0x971bfa8a
+- 0xcbf141d2 0x0afafe10 0x2fc906a6 0xefad20c0
+- 0x9e922581 0xe69142cc 0xc9c0ba82 0xc069e640
+- 0xb99c08b6 0x4b62ca1f 0xf3c5767a 0x6ab088c7
+- 0x8f0f0c0b 0x6726f64a 0x9711a3cd 0x46462571
+- 0x3a58350e 0xa2561911 0xe24dfdfe 0x97443fdc
+- 0xf80540be 0x069978bf 0xb38a359b 0x8e574f62
+- 0x69aea75c 0xdc753fcb 0x2a74002c 0xced027b4
+- 0xda993254 0x03409b83 0xf827331d 0x75fb3271
+- 0x01ad839d 0x68520842 0xca65c45c 0x1a3db5a0
+- 0x91d37dd3 0x6168c0fb 0x935f5a08 0x002007c3
+- 0x42eb4760 0xdab3a804 0x72a6297e 0x905c32d9
+- 0x81abcfa9 0x1b21d04a 0x5a1289ae 0x424e7183
+- 0xc207906c 0x31fe9134 0x5eb2e5af 0xc9253fc7
+- 0xc32be24f 0xe5474cbd 0xeff6e1b0 0x710e5e69
+- 0xe6c4c538 0x96b5f1de 0x2abc9c35 0xddbd1a92
+- 0x8aca40d7 0xe359c238 0x954718f4 0x18b157e5
+- 0xeeed790e 0x6948a963 0x24e70bfb 0x4d681547
+- 0xf68369a7 0x5b54409a 0x1f0b787a 0xc2610047
+- 0x0f8bd269 0xd7c8c154 0x9dee62d9 0xd4738ed8
+- 0x1a66c6b1 0x5bad5a5b 0xb110311a 0xfaec6802
+- 0x6b750f2d 0xcbf8d0e0 0x11edaf4b 0xf64a07bb
+- 0x422e7c15 0xb1732663 0x1ff404f0 0x2d5052b0
+- 0x6e45356c 0x7e2201e8 0x7c5ebcd1 0x1cb4425a
+- 0xb1539a64 0xa2e4459f 0xcf1ade8a 0xfc476473
+- 0xf4147deb 0x2afbdd77 0xff01fabc 0x6597408a
+- 0x0951220b 0x6750f3ec 0x0a242763 0xf3d71c05
+- 0x84cb1c26 0xdb7a81bd 0x7aea1a5d 0x7e719a48
+- 0xc5c12fe1 0x0ce2e988 0x29ecc6f0 0x5ede901a
+- 0xda8399b1 0x31c05d6b 0xe1956aff 0x59ed7c3d
+- 0x60832637 0x9bcb7cac 0x63c530d1 0x14c677de
+- 0x9225ed18 0x065327c9 0xd1ff6a0e 0x5516517e
+- 0x53c6f5c2 0xed5983cf 0xaa1d18b9 0xbe300d7f
+- 0xadc525a7 0x07ea81b6 0xfc517a09 0x4ead3f86
+- 0x45435f41 0x2efa58df 0x02348ebc 0x30ed6783
+- 0x190b4fb9 0x85c55d6e 0xc9ed8896 0x416ee113
+- 0x9b3536d9 0x30577cc0 0xbc4b88c8 0xcda59612
+- 0xdfe2bd89 0xd60cde71 0x98843881 0xcc1f32f2
+- 0x18b3f643 0x671a14ca 0xd6482a47 0xac6a7d38
+- 0x1897da16 0x91b6fcb3 0xf199bb35 0xd38c00ba
+- 0xa8c946b6 0x52a1ad37 0xd38ed2d4 0xa1d6f81d
+- 0x5af6865b 0xebdb858f 0xb844b110 0x53201ea2
+- 0x08870945 0x10c869de 0x19849613 0xdb35d3ed
+- 0xd68ebd6e 0x1056fd48 0xf1a0e305 0xe3982ebd
+- 0x6f7cc391 0x5956374a 0xf414a5a2 0x325119ab
+- 0x99ee1f96 0x6f044bd9 0x8374805b 0xb55c366c
+- 0xa2c77051 0x68f199e5 0xd36a9714 0x878f847b
+- 0xec0394ae 0x86d0584b 0xf4df66b9 0x451cd039
+- 0xf4de06ae 0x35dd0554 0x818a342f 0xeefdbfc9
+- 0x5b4e9edd 0x22d9313a 0x3b710d60 0x6deaeb4c
+- 0xa9e26512 0x98d31867 0x3c2c2d61 0x7eb5ce41
+- 0x40890db6 0x7a3aa660 0x3ef4f306 0x7322881f
+- 0x49dac4d5 0x96efe685 0x27bb7f49 0xbb955283
+- 0x79c5f2b7 0xff599c28 0x28ee7f5e 0x9f324b73
+- 0x45edb7cf 0x39a8b79c 0xd0919c6e 0xe149b29d
+- 0x62f5f82e 0xebcfa23e 0xd4d68937 0x54270090
+- 0x958af0d4 0xa1e4e799 0xaf68ac19 0x82a84f4e
+- 0x50f67b84 0xd5e59629 0xf5fdf24c 0xab1d63c5
+- 0x30835807 0x431fce5f 0xe5f96f4d 0x3f6b4802
+- 0x14010be8 0xdca45ae5 0xc82709af 0xff76ce2c
+- 0x8b222c22 0x73a2d948 0xa8d59cea 0x8c31849e
+- 0x469c2e5f 0x3777ee84 0x5fdfa5da 0x02ef9bb2
+- 0x792d3194 0xbed63f21 0x0b6dc5f1 0xc9d7fe08
+- 0x6df7883d 0x366566cf 0xef772769 0x37826465
+- 0x1cdc3086 0xa69ff7b6 0x235012ea 0x292f7e75
+- 0x30bdd0fd 0xffdc9df1 0x95c6d570 0xec206204
+- 0xc6cd42cb 0xc0d6dfd9 0xb7a16b71 0x17fa527e
+- 0x295f2c79 0x990f9820 0x8b8f447d 0x193f9ad1
+- 0xebddb2af 0x5dd532eb 0xf1bbd8e8 0x3444a3f4
+- 0x18ccce93 0x05edeb4f 0xc4a6b935 0xba37aab0
+- 0x96076ba4 0x250dc2f7 0xc4093548 0x030e777d
+- 0x7ea40933 0x8da7b1dd 0x59c0b79f 0x807d437c
+- 0xf5233ddf 0x54c1983f 0xfc18771b 0xe74b85f0
+- 0xdbd725b5 0x70cdd153 0x4ffe300c 0xfda4bdae
+- 0xf4ac75d2 0x91c4e15a 0x34d92b97 0x16356a79
+- >;
+diff -ruN u-boot-2015.01-rc3/arch/x86/dts/Makefile u-boot/arch/x86/dts/Makefile
+--- u-boot-2015.01-rc3/arch/x86/dts/Makefile 2014-12-08 22:35:08.000000000 +0100
++++ u-boot/arch/x86/dts/Makefile 2015-01-01 17:34:32.253503252 +0100
+@@ -1,6 +1,7 @@
+ dtb-y += link.dtb \
+ chromebook_link.dtb \
+- alex.dtb
++ alex.dtb \
++ crownbay.dtb
+
+ targets += $(dtb-y)
+
+diff -ruN u-boot-2015.01-rc3/arch/x86/dts/microcode/m0220661105_cv.dtsi u-boot/arch/x86/dts/microcode/m0220661105_cv.dtsi
+--- u-boot-2015.01-rc3/arch/x86/dts/microcode/m0220661105_cv.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/x86/dts/microcode/m0220661105_cv.dtsi 2015-01-01 17:34:32.253503252 +0100
+@@ -0,0 +1,368 @@
++/*
++ * Copyright (c) <1995-2014>, Intel Corporation.
++ * All rights reserved.
++ * Redistribution. Redistribution and use in binary form, without modification, are
++ * permitted provided that the following conditions are met:
++ * .Redistributions must reproduce the above copyright notice and the following
++ * disclaimer in the documentation and/or other materials provided with the
++ * distribution.
++ * .Neither the name of Intel Corporation nor the names of its suppliers may be used
++ * to endorse or promote products derived from this software without specific prior
++ * written permission.
++ * .No reverse engineering, decompilation, or disassembly of this software is
++ * permitted.
++ * ."Binary form" includes any format commonly used for electronic conveyance
++ * which is a reversible, bit-exact translation of binary representation to ASCII or
++ * ISO text, for example, "uuencode."
++ * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
++ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
++ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
++ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
++ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ * ---
++ * This is a device tree fragment. Use #include to add these properties to a
++ * node.
++ *
++ * Date: Sat Sep 13 22:51:38 CST 2014
++ */
++
++compatible = "intel,microcode";
++intel,header-version = <1>;
++intel,update-revision = <0x105>;
++intel,date-code = <0x7182011>;
++intel,processor-signature = <0x20661>;
++intel,checksum = <0x52558795>;
++intel,loader-revision = <1>;
++intel,processor-flags = <0x2>;
++
++/* The first 48-bytes are the public header which repeats the above data */
++data = <
++ 0x01000000 0x05010000 0x11201807 0x61060200
++ 0x95875552 0x01000000 0x02000000 0xd0130000
++ 0x00140000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0xa1000000 0x01000200 0x05010000
++ 0x19000000 0x00010500 0x15071120 0x01040000
++ 0x01000000 0x61060200 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x9557a557 0x7d7a0fe3 0x8e2fbe53 0x0db9e346
++ 0xd35c00d6 0x21bb34b7 0x662b6406 0xa0425035
++ 0x3d028208 0xcb843695 0xee06be0a 0x9817efa7
++ 0xb86c0d16 0x45f70c93 0x79fdc3af 0xd5f30da7
++ 0x460f62b0 0x238a0470 0xf0ec95bf 0x97b9c176
++ 0x6d612851 0x69b9b4b6 0x1df769cc 0xe11674df
++ 0x1b579adf 0xc8bcc050 0xcdb3e285 0x327592c1
++ 0xbeb6047a 0x977f6be5 0xc4854052 0x27f38b66
++ 0x4ca5eab3 0xf806decc 0x2be4b409 0x460a3b03
++ 0xde2f6e0f 0x53ce08b3 0x3ef0ef93 0x4e013088
++ 0x226f8a5c 0x57f7d291 0x8d640bf7 0x8a998907
++ 0x40464dd8 0x804ef3e5 0x647e35f3 0xeabee2d1
++ 0x3a5ce9c7 0x4d7ee530 0x564321ec 0x9e85107e
++ 0xd595581d 0xcbf6efde 0xed3010ed 0x3d607e82
++ 0xe32d4b6b 0xd06fec83 0xf39240a6 0xe487988d
++ 0xddbefcbe 0xefaf1121 0x96bf9acb 0xacce795c
++ 0x7fa5f89b 0xbe440e5d 0xb6d3a3dc 0xcad17290
++ 0x503ae748 0x04c80b8d 0xd394ea6a 0x3e4072c3
++ 0x11000000 0x0b0ae65d 0xc6c53cbd 0xd52a6c2d
++ 0x84cc192f 0x89498e7d 0x89270686 0xe68105e0
++ 0x4073a570 0xd3338d8e 0x51193152 0x7266182f
++ 0x980553fa 0x51b89c90 0xd13b6151 0xe6e40a91
++ 0x0ab997d8 0x2d0a443b 0x9d3d566d 0x820402d1
++ 0xdbe79fcc 0x7c5e0b45 0xaf94216d 0xbf717950
++ 0x520b3dd4 0x566a3396 0x0b6f794f 0xc5dfeda5
++ 0x71ba0f02 0x4839a5ed 0x39a4e4a6 0xe567c652
++ 0x0e044997 0x84a0effd 0x09c67178 0x89a815c8
++ 0xac821555 0xd6719303 0x582b964e 0xfe3a53f6
++ 0x241b9b8b 0xc6e65457 0x623a4e0a 0x590d7d03
++ 0xe50e7ce1 0x4bca4700 0xf24f5eff 0x1f1b20d9
++ 0x77e3227e 0x699b5e5d 0x9aa5f621 0xff08bba0
++ 0xf17ce716 0x0f5336f5 0xbce055a7 0x8cea9dac
++ 0x8e09d26c 0x66c3ddf0 0xbec71660 0x75248cd2
++ 0x29afcf8d 0xa5ade5ce 0xf68bace5 0x63b513cd
++ 0x4736a842 0x4dbf80df 0x4e85fbdf 0x4dce3d56
++ 0xf2150fdc 0xc4232709 0xffdc3e3a 0x92b72a3d
++ 0x9ffce715 0x682959d1 0x091ba33c 0x0f1dc729
++ 0x2f29a924 0x1df72429 0x19b0365d 0x2d5a3cd8
++ 0x20617351 0x109074f9 0xf232874a 0x40d79569
++ 0x97dbe4c6 0xa3b66845 0xa04d2faa 0x6dce9a96
++ 0xd4963c67 0xd4516f76 0x64a0b04d 0x0b87ddfe
++ 0xd8a5305d 0x717ecf67 0x77189035 0x40542ed4
++ 0x5a180ff1 0xb2042e2c 0x6639819b 0x0f0756c3
++ 0xf939bd70 0x25efe0d6 0x3eb65ae9 0x39a057d2
++ 0xb2595655 0xf808b4fd 0xe22d0593 0x76256500
++ 0x0eeee6ee 0x6895d1cf 0x9fc117a7 0xd19e5f15
++ 0xf677f085 0x1ecdb30d 0x704d0975 0x9099f42e
++ 0x421be0b2 0xd02548bd 0x3a16e675 0x7d8b051d
++ 0x9d24480f 0xbc006432 0x184da9ec 0xbad7abef
++ 0x299f58aa 0xc1a249fa 0x8d9d31f3 0xe73cda17
++ 0xf41ac993 0x7b88d3bb 0xf349c676 0xb8341361
++ 0x1b69bc01 0x98e0bfd2 0xf31db8d9 0xeb49b275
++ 0xabc40133 0xfb7d0701 0xcd5ff353 0x4eaceb8d
++ 0x67aac555 0x6d81693b 0xe81c555d 0x5d7f3688
++ 0xd4347083 0xcd861b1d 0xd332f2cb 0x43130028
++ 0x7f1a1c51 0xe2ce3af2 0xdff5076e 0x6ef21237
++ 0xf65fc8c4 0xbd28ff14 0xd70f49a3 0x4f559249
++ 0xd6fe7530 0x1fe89b4a 0xc1cc8975 0x2fd705c5
++ 0xf2993d77 0x60f2e3da 0xe3ca3c44 0xbd0f70b1
++ 0x0d333d10 0xa29a6aa1 0x43b5a6d4 0x30d15a08
++ 0x6df9564a 0xea09045d 0x54ca3f5a 0xfbcfa037
++ 0x6dd64d1b 0xa4a8995c 0x1f4298f0 0x3f4d9a86
++ 0x924ee146 0xc2e3f464 0xc247747f 0x8bf5c7d7
++ 0xf8f0b05d 0xf65a115f 0x4b1ae4e5 0xe131e187
++ 0xfaf713c1 0x5ff88660 0xcd4916b0 0x448028e0
++ 0x140711ca 0xffe77575 0x8b7740bd 0x82b6ed95
++ 0xd94d9647 0x2623c011 0xd54fba11 0x30a7050b
++ 0x28fe4069 0x70b8bf7d 0xf786eb6d 0xe39db734
++ 0xa3290669 0x8747e1d6 0x35804a42 0x1c26ed60
++ 0x30a8880f 0x8170a277 0xa1d97657 0x6ebcb3ed
++ 0x3bb6ce89 0xff808c1b 0xc919fd1e 0x911d8b14
++ 0xcbf41a24 0x82abc738 0xfb5e988e 0x328aa123
++ 0xf19146e3 0x587baa80 0xd105e811 0x83b09389
++ 0xa29fc554 0xe3831a28 0x183f8de7 0x4ef5656e
++ 0xcc940baf 0x938bf4b4 0x90627bae 0x14fc3cdb
++ 0x75e45681 0xf912c1b3 0x7a5b8a0f 0x3b970524
++ 0x6a74d34a 0xb3da9fe6 0x847a3bd8 0xfc4f7dd6
++ 0x88fd7f3b 0xbcd74a15 0x3afed836 0x17e31cd0
++ 0x5d866dcb 0x0ab69608 0xe334f0fb 0x7181d4a3
++ 0x8dc87560 0xd9c94d6f 0x491c2c91 0xca295ed6
++ 0xfb8dcd79 0xeb4d3f89 0xec581071 0x0457ebc6
++ 0x6b63590b 0x9dde4b79 0x3dc0a0aa 0x41ec8a1e
++ 0xfb2ab80e 0x07adc629 0xb8534a4f 0xd0d23901
++ 0xcfd024da 0x47c4163a 0xc89d26bb 0xe5cac48c
++ 0x17c7fbba 0xd992f42e 0x466f5e35 0xce48304e
++ 0x394683c8 0xef6e6b7a 0xb9d1242d 0xb961debd
++ 0x432a3dff 0xa4931ea7 0xd9f03907 0xc29e9ce6
++ 0x4fccf4c9 0xbf234555 0x0b6a6771 0xb29f29ef
++ 0x7edc4bfd 0x781dcf74 0x4ae31020 0x1ab72d9b
++ 0x0ac457e2 0xf9291e09 0xd4084918 0xa540d999
++ 0x223408d3 0x0bd039aa 0xaf0dd904 0x9cfd6a01
++ 0x826c6bca 0x8e41a96d 0xa56fc4ee 0x6a7509fb
++ 0x5cd2e6fc 0xb89aa158 0xb1e5d3f5 0x92ccd05e
++ 0x995d5acb 0x5ed1dc08 0x75038dac 0x4377c835
++ 0x265d66d8 0x3692096f 0xcd69ee59 0x310df351
++ 0x087e3133 0xe89e2d58 0x137fd054 0x00f3562b
++ 0x2ae304e5 0x9db0316d 0x6868cec6 0xb249ccec
++ 0x9f602c90 0xd3715e7c 0x3fcc8a62 0xa1c1e065
++ 0x5b4281d4 0x124dfd7e 0xe9d21462 0x77cbc940
++ 0xf915f2a5 0x66df82fc 0xa8c67c56 0xac4d461b
++ 0x836deb52 0x95fbb48d 0x3454b6bd 0xd87d7a64
++ 0xe64d32b8 0xc44c2aa0 0x3e213c1f 0x4d31b94d
++ 0x4640be5e 0xe127234b 0x9ca54856 0xac7d093f
++ 0x03d0508b 0x30f5121d 0x6e347d91 0x47772312
++ 0x318ea26e 0xad3f6902 0xb5598746 0x8be3b65b
++ 0xc8bbd31d 0x24691564 0xee77d2e8 0x3581944e
++ 0xeff8eed5 0xa29ea86c 0xc2597492 0x23c1c118
++ 0x7810c079 0xb966ee47 0x823e9954 0x9e558c0a
++ 0x74759c12 0x193c6b4e 0x7544597d 0x65c9bf8a
++ 0x68f5e263 0x718c679b 0xc8dc50ba 0x5f5ab841
++ 0xc3eaf579 0xc2072358 0x62481939 0xffe7e686
++ 0x201f3215 0x1d88dc8e 0x28fb4002 0x40c56ec5
++ 0xb7bcce00 0xd52f5042 0x84498e04 0xcc97fb7d
++ 0x64035e93 0xcd3478a4 0x15d63309 0xa9e47b85
++ 0xe835e45f 0x9de598b7 0x94f569f7 0x56689b0c
++ 0x381f9173 0x708b3e52 0xc81f0649 0x12113041
++ 0x4694aae2 0x69040fc0 0xe4ba7bf4 0xfadc5729
++ 0xc168381f 0x1985f118 0xab0ca720 0xf0150799
++ 0x42690e4a 0x71af3be9 0x9325f3b8 0x36575996
++ 0x4dc1dca7 0x7e534c37 0x01830a21 0x221eef4f
++ 0x18698322 0x57a80837 0x483ae2d8 0xef905b54
++ 0xe01827de 0xae9a8ff1 0x0058be7b 0x052632ad
++ 0x9df5c90b 0xb763fc7a 0x5535c95c 0x8eb5916a
++ 0x75fde5cc 0x57d8eeab 0x0dcc35c6 0xbf11c88f
++ 0x69142118 0x4f35c928 0x7966066c 0xb2d13b4b
++ 0xdad06d34 0xb5d8f5c7 0xe0bb11e6 0x8a36325d
++ 0xc1122d64 0xcf07a1a5 0xfe7ce9b1 0x176b624b
++ 0x4de883fd 0x00a9024b 0x3d3f7271 0x5072895d
++ 0x2634e158 0x2f3c9a35 0x95e374d1 0x65e66528
++ 0x47766433 0x4cb805ff 0xbc8f0319 0x6d5055a5
++ 0x4932e8c2 0xa93fbb4d 0x87f08bd9 0xf5e5706e
++ 0x409af40e 0x017edf5c 0xc5394c71 0x6fb97b6d
++ 0x7b5ddb6b 0x0256adfe 0x76d337e2 0xa3327113
++ 0xfbb4cb29 0xea68ca27 0xa76a865e 0x8cdb2dd3
++ 0x902642bd 0x16772269 0xb2341eaf 0x858fa943
++ 0xb087fac9 0xd17de85b 0x3d9c248a 0x0bdcf2d0
++ 0x874fc03c 0xf19f2591 0x190c06a9 0xc6b5c3ea
++ 0x472b6245 0xdb9f8201 0x46d27a0d 0x52218ffe
++ 0xece78c44 0x3ef6e38a 0xfcf19b65 0x536c840c
++ 0x86d363e8 0xaa852826 0xde17e3ec 0xa9c3b45b
++ 0xd322302a 0x48f03728 0x2f60d01a 0x3b356752
++ 0x8a869fd4 0x055d04f4 0x765074fb 0xb0b5c2d1
++ 0x865ad360 0x0cb6c6e8 0x5de9cf99 0x863938d3
++ 0xd4d9aeea 0x0babfa86 0x172cfb57 0x972d8f4f
++ 0xe9aeeb95 0x6acbe297 0xf2459e42 0x415fdd12
++ 0x84b2e67b 0x47d2d466 0x44bc85a4 0x1a55b957
++ 0xe4d01142 0xbf4ea387 0x5651e1a2 0x19124703
++ 0x8aaed1b2 0x841f3ecd 0xc6d6cc4f 0x1f2d8565
++ 0xba08e74a 0x68e5ecf4 0x07af5ef4 0xdd5a43a9
++ 0x6086c705 0x37ced045 0x0fb05ca6 0x35f39f3b
++ 0xda1ecbef 0x1daf6d76 0x5481d7ed 0xc51e8385
++ 0xa705e11e 0x127d2a7f 0x654d4710 0x1a34370e
++ 0xf8496ea4 0x4392b6ec 0x2f209933 0x9c5ab017
++ 0xa4f7b837 0x33e0a7d0 0x98fb0635 0xdefc042a
++ 0xc7a1f6b5 0x47107766 0xd06acfba 0xb8ac2a93
++ 0xe21cca44 0xf0150492 0xd4de2e01 0xe0d6e9a5
++ 0xa758b5df 0x2e1c31c0 0xc4794495 0x3d9cc157
++ 0xf94aa4f7 0xc2325855 0xcf9ddd12 0xaa70e611
++ 0x2b2404b8 0x75d87f38 0xa2a6f772 0x61abfa04
++ 0x23b61fb0 0x87f4067f 0x355abf99 0x2c4e6c48
++ 0x2dc8a3b2 0x119b08b5 0x3f1f6d09 0x374372f0
++ 0x24d79d32 0xef2b58be 0x461ab91c 0x1d31267e
++ 0x8b1b2c7e 0x27a4f103 0x1686c7c3 0x55af0d87
++ 0x61c2503b 0x9ffcca7f 0xc3cbdd07 0xd49a4f3c
++ 0x9ddc2ac9 0x335e1b2a 0xd8dcfc08 0x6e83f11c
++ 0x53de9e30 0x7b774670 0x15a97571 0x1ecacf66
++ 0x26581520 0xeee3496b 0x1fdf8174 0x4ddd3c61
++ 0xaa504fc2 0x0b09792e 0x9b81d1c7 0x10765c95
++ 0xd3e7b9d1 0xefdb38f9 0x4c44d38e 0xaaf8fd08
++ 0xceb22e7c 0x5ac74242 0x6baee02d 0x5c7eaa5b
++ 0x27265dca 0x614c3b5e 0x2994874d 0x486d48a3
++ 0x5945c4f9 0xe465f343 0x934e55de 0x633199a2
++ 0x147222cc 0x9bbb0c16 0x6a7e7ef1 0xb7bce9b5
++ 0x13413d18 0x628231af 0x0fd2d58c 0x4cbafba0
++ 0xa930fae6 0x91733823 0xe06f99c3 0xda3b57b7
++ 0x04b8a9dd 0x53451e33 0x11fde5fd 0x0e35bcb8
++ 0x3a5799d4 0x3893f9c0 0x6b9d0e1d 0xf8d948ce
++ 0xa33a6628 0x7d09792d 0xd74b3719 0x0afb4de0
++ 0xfaa5a685 0xecf7f8ac 0xcf34b855 0x89453b4d
++ 0x12f028c3 0x45edc3fd 0x792c43fc 0x2b054962
++ 0xb8799a92 0x0ab38d61 0xa6c6a76d 0x7670cdbd
++ 0xf878b511 0x9a3474ba 0x478673f0 0x7398bba8
++ 0x4fa10ff5 0xf0a1931c 0xd5938e03 0xe9a23c28
++ 0x7bea2a5b 0xf7a8db22 0xb94ae0e3 0x2abe6385
++ 0x0ef2cc36 0x6b997544 0x1e8cc4f1 0x69a5b182
++ 0x54f9b7c7 0x8fe56cba 0xc7c12fcc 0x8d689865
++ 0x2d6ef011 0xc6a1b740 0x66af0a76 0x76018cdd
++ 0x30661377 0xcf1fcf93 0x08046423 0xdf9371c8
++ 0x1795ec3e 0xf5ea09c6 0xe462de69 0xd7da78a1
++ 0xd8bda1eb 0x1179f53a 0x2b394767 0x3ba153a7
++ 0xf9c85bd7 0x5700c827 0x8478ac99 0x080a2f52
++ 0xdd1c18f1 0x579cea67 0x345c56ce 0x4563f16a
++ 0xfa1a5b74 0x0b6e233e 0xadc7bd9a 0xbee6d2f0
++ 0xa249f3ef 0xcdea9b77 0xeaaed82e 0xcc4448a7
++ 0x34f7cafb 0x7621bb44 0x4965b0eb 0xe6d6b8bf
++ 0x3c683b25 0x33bcb5fe 0x3f376249 0x5b40dc67
++ 0x658bf6aa 0x7f0c5d0d 0x61514591 0xeb3bb83f
++ 0xc2e208dd 0xe82f08f2 0x6ef75ae5 0x9c11bc0d
++ 0x289c0553 0x1578ce5d 0xb7f05c0e 0x818c5ebd
++ 0xe566ec9b 0xc6995b3f 0x0c02aac3 0x2b4264b3
++ 0xf9cad304 0x5b0479fb 0xf8ce8d6f 0xb7d80d8b
++ 0x41a0d223 0x71ec8a7a 0xc9d74d41 0x245c5988
++ 0xf607fc59 0xf1c7b6ab 0x142ef712 0xbf607800
++ 0x281e5911 0xad9a3e63 0x87b59384 0x7ebdc04c
++ 0x6f47867b 0xb6a304ac 0x289f65e7 0x335fc866
++ 0x77eb11b3 0xb70c25b2 0x70b43d52 0x684d46c0
++ 0x0940459b 0xde739ede 0x0b438a29 0xb713e77e
++ 0x71f539b7 0x8b2f0f7b 0x8d8ab95d 0x42cde8c9
++ 0x08c259d1 0x021eda69 0x2af81ddc 0xc7d13028
++ 0x05abfa20 0x6a61008b 0xfc62557f 0xd6d731b2
++ 0xb080aca3 0x6acae4a3 0xab33d2bc 0x7983c177
++ 0xdf0c357d 0xb8dcb956 0x9c214460 0xfeb75d75
++ 0x9b3d468b 0xd2c3106c 0xb1bd118e 0xf26df6a8
++ 0x11b9c4d2 0x031357f9 0xf7af8a12 0x70fef26c
++ 0xe5d8b8d5 0xf6746fd8 0xd6cc3266 0x4158e59f
++ 0xa38fbfcb 0x01c61ff6 0x44c7c4e6 0xf26db3aa
++ 0x46bb6d84 0x0a794535 0x1d5eab72 0x42345de7
++ 0x0c7e6d47 0x8bacc223 0xb7334b8d 0x3d9d951b
++ 0x18f4afc4 0x9c0cb708 0x53b71b82 0x603e8350
++ 0x6f2df978 0x0c6f3f0f 0x661ebca9 0x30788bd0
++ 0x982959c0 0x50aa1351 0x672297c1 0xa490a756
++ 0x21c9e911 0x977e172e 0x0446db50 0x49b711c1
++ 0xbc6d54c7 0x0fe0adb4 0xc4ec0fe4 0xae6d09b6
++ 0x316cfa53 0xba68cc8b 0x104bdbe9 0xc31639a3
++ 0x812a97fb 0xa1c6884b 0xc884d473 0xe3057c15
++ 0x5ee879a3 0x5abe8262 0xb906bbde 0xfd98fcbd
++ 0x6ae15c96 0x44a17e0e 0x28acfa15 0xb345122c
++ 0x6ddc4244 0x005eb369 0x22d038bc 0x0d226e4f
++ 0x64c7ed6c 0x7964b8d9 0xbc5d668d 0x99155e56
++ 0x9979151c 0x65312a00 0x0271d338 0x64867293
++ 0xed0d26fb 0xe69c5f02 0x93fd6871 0xf5702656
++ 0x4fad1c2b 0x20f8c272 0x438b964a 0x87ff3fa2
++ 0x6706537a 0x437b5709 0x6fb797dd 0x85679fab
++ 0x00da6b51 0xeecc5540 0x2998791c 0xc36d40ef
++ 0xb545e334 0x9ace5e06 0x8a9e6c54 0xc341d0cd
++ 0x1478a2d4 0xb81413bd 0x80601f72 0xa1b250b9
++ 0x1cb7f5ce 0xefad630c 0x32325fcc 0x29e3474d
++ 0x6a7ae043 0x879ee630 0xdc1e8a55 0x7ae794a8
++ 0x4ee38039 0x2ff4947a 0x53bb84b1 0x8f0b077d
++ 0xaa4c543b 0x9aa88443 0xeb31a017 0xf3485983
++ 0xe53b855c 0x6e17aec6 0x726458a6 0x5acf4345
++ 0xa1b95c5a 0x30668c67 0x47fb5dc7 0x8aafbff4
++ 0x4b94ef01 0x07bd6231 0x544afcf3 0xfdffca2f
++ 0xce847471 0xe90abc6e 0xf05e3cc1 0xf602a9c8
++ 0x8f104b51 0x1ae3da07 0xd07dfc04 0x561d9373
++ 0x6f6cc833 0xac982489 0x3c0f8afd 0xfab974d0
++ 0x397e135e 0x8edb3eb4 0x452b9509 0x3972829d
++ 0x639e3981 0x1c758ec1 0x11428fa5 0xe8308fa7
++ 0x571d71b9 0x94e40c2b 0x1aaaa397 0xce9283ae
++ 0x599bbb93 0x51c04bf7 0x556bc74f 0xf6e6e799
++ 0xc34191e0 0x5f06bce6 0x9f63ecd1 0x54437905
++ 0xf8f9bd50 0xde82cbf6 0xe11a9949 0x9d312bfa
++ 0xe712e3db 0xb57eabc9 0x57682068 0xc91c2e3c
++ 0x681e4fbd 0x0ecd3452 0xcc893248 0xf13f0600
++ 0x9a8a9194 0xb4c1cd29 0xd504d8f2 0xee6c5b8a
++ 0x211c9958 0x7a4f9c30 0x32775708 0xda97bf03
++ 0xf7035e57 0xbe77d547 0x37accd1e 0x6c537775
++ 0x8d63b752 0x7fec4a3c 0x94211d9e 0x60bfeb2a
++ 0xebd47130 0x747d52fc 0x8434f487 0xac9091cc
++ 0x8f8b228f 0xb77f96a1 0xc21fede9 0xa9e2678a
++ 0xbc815194 0x54d677ac 0x66c11faf 0xfb666595
++ 0x01e5e973 0x5c990d0c 0xf2cea425 0x5b516ff8
++ 0x8c932784 0xd18feb32 0xb5acd3d3 0x1703b89a
++ 0x34fb512c 0x0ac83386 0xd58c5728 0x5c018ed6
++ 0xbe0908a0 0xd490b0e9 0x0ec94527 0x2f281499
++ 0x471df723 0x03eddc08 0x9b99d975 0x11535b70
++ 0x5802288c 0xb3512d42 0x415a9c0d 0x52dbd146
++ 0x8b0c59bf 0xd8160cc7 0xe37dee6e 0xfd5211cc
++ 0x5635ff4d 0x8d783398 0xc11f5d62 0x54ca73b4
++ 0xc3ebdf96 0x835e7883 0x9cd03137 0xe4b4f709
++ 0xdbde6d86 0x2b562b2d 0xfecc0df5 0x172a5ec2
++ 0x568b52b9 0xf542957c 0xd738b325 0x49c49aaf
++ 0x6eb4c9ad 0x363f4978 0xac4b0cb3 0x4ec8dca8
++ 0x7a2ec2ba 0x10ff39bc 0x8b8748d5 0x6a86e67b
++ 0x0d81e2b6 0xf4bde138 0x02249333 0xab0c7acf
++ 0x4ce5e894 0x1656dad7 0x46c59329 0xa849fea0
++ 0x3d0400be 0x6898c4f7 0xd866ff9a 0x84a5b170
++ 0xc997009e 0x80524f6e 0xc80fb5dd 0x5bde0181
++ 0x0bb0c8a8 0xe5a6b9e4 0xd4753f0a 0xda9bf0c6
++ 0xd6dd041b 0x4c7338f0 0xa223bd71 0x23b58f4a
++ 0xf6e127dc 0x1777033d 0x5b057a0f 0xe08af0bf
++ 0x17c07032 0xbbc3f27f 0xac6dc98b 0x921e2f12
++ 0xcf32236d 0x6cb700a8 0xa3b4e5cc 0xe9b65d73
++ 0xca7d6f44 0x7b5917f6 0x7b80dd21 0x5ee87e45
++ 0x86799f71 0x0667e036 0x8f97dcca 0xc4bfd5d9
++ 0x90737eed 0x41b5a457 0xc6c96301 0xf8933e95
++ 0xe51c2456 0x00c661f4 0x8a0e1aaa 0x92aa4181
++ 0x1e3f8638 0xd481a14a 0xaf637189 0x91622fb3
++ 0x4450865d 0x4202b431 0x5248342b 0x01ff713b
++ 0xe33b5ec5 0x912d6856 0x10deb2ac 0x9072c180
++ 0x24d792af 0xa39c5dfd 0xb4c94140 0xfeb32004
++ 0xa174dae8 0x49da7dfc 0xa4db1090 0x7d2a998b
++ 0xb7eba69b 0x9b824871 0x3557bd1d 0xd3a73d9b
++ 0xf225310b 0xad1ffcf6 0x2d5f075b 0x592de6f4
++ 0x69e438f4 0x4ed8cac4 0xa79c947f 0xb95f9590
++ 0xb8ede5c9 0x0b1c9229 0x85a4b30e 0x65149920
++ 0x433461a8 0x186fda4f 0xbaee7097 0xd3cac1bd
++ 0x8bc32ca2 0x914f1512 0x9b619478 0x582a53c9
++ 0x4e624a00 0x77e445ec 0x6f823159 0xa9c4766b
++ 0x0dd6ad28 0xfabdadc5 0x704bfd95 0x08645056
++ 0xe1939821 0x76650b62 0x8876941a 0xf812239f
++ 0x2869ce13 0xa4d292c7 0xecba40fd 0x83d2fd8f
++ 0xdd45ccc0 0x7c12b7cb 0xdc0a20bb 0x0d9be34d
++ 0x4dd16a9d 0x25835446 0xb94d8c21 0x97ca8010
++ 0xddd09324 0x95ffe31f 0xa86136c9 0x828ac571
++ 0x9aa7fc00 0x382cc48c 0x015f7186 0xc3fd040d
++ 0x505408e0 0x21cdc34c 0xbd266059 0x6e2f673e
++ 0xe4523c1b 0x3ba56bb3 0x1c343938 0xabc0df54
++ 0x8ba4f1e8 0xfbd4c592 0xb678c884 0xff3be2f1
++ 0xca013570 0xfb0598df 0x3cb9cc1d 0xe3ba8ca3
++ 0xc3d7ecee 0x0ae84a0b 0x0d70f0c3 0x963110ff
++ >;
+diff -ruN u-boot-2015.01-rc3/arch/x86/dts/microcode/m12206a7_00000029.dtsi u-boot/arch/x86/dts/microcode/m12206a7_00000029.dtsi
+--- u-boot-2015.01-rc3/arch/x86/dts/microcode/m12206a7_00000029.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/arch/x86/dts/microcode/m12206a7_00000029.dtsi 2015-01-01 17:34:32.253503252 +0100
+@@ -0,0 +1,686 @@
++/*
++ * Copyright (c) <1995-2014>, Intel Corporation.
++ * All rights reserved.
++ * Redistribution. Redistribution and use in binary form, without modification, are
++ * permitted provided that the following conditions are met:
++ * .Redistributions must reproduce the above copyright notice and the following
++ * disclaimer in the documentation and/or other materials provided with the
++ * distribution.
++ * .Neither the name of Intel Corporation nor the names of its suppliers may be used
++ * to endorse or promote products derived from this software without specific prior
++ * written permission.
++ * .No reverse engineering, decompilation, or disassembly of this software is
++ * permitted.
++ * ."Binary form" includes any format commonly used for electronic conveyance
++ * which is a reversible, bit-exact translation of binary representation to ASCII or
++ * ISO text, for example, "uuencode."
++ * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
++ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
++ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
++ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
++ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ * ---
++ * This is a device tree fragment. Use #include to add these properties to a
++ * node.
++ */
++
++compatible = "intel,microcode";
++intel,header-version = <1>;
++intel,update-revision = <0x29>;
++intel,date-code = <0x6122013>;
++intel,processor-signature = <0x206a7>;
++intel,checksum = <0xc9c91df0>;
++intel,loader-revision = <1>;
++intel,processor-flags = <0x12>;
++
++/* The first 48-bytes are the public header which repeats the above data */
++data = <
++ 0x01000000 0x29000000 0x13201206 0xa7060200
++ 0xf01dc9c9 0x01000000 0x12000000 0xd0270000
++ 0x00280000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0xa1000000 0x01000200 0x29000000
++ 0x00000000 0x00000000 0x11061320 0xd1090000
++ 0x01000000 0xa7060200 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000
++ 0x00000000 0xd1090000 0x00000000 0x00000000
++ 0x00000000 0x00000000 0x00000000 0x00000000
++ 0xfd2a2f68 0x82ac7ebb 0xa4916328 0x7480b81b
++ 0xd329a777 0x25750339 0x9a8f7a9b 0xf1da9cb8
++ 0xb1be7b1a 0x621d5a35 0x94b57e2e 0xa9def809
++ 0xe4492a43 0x530252bf 0x1040fada 0x8a853a89
++ 0xfb0e6e76 0x6d191ed9 0xefd28b83 0x946414e5
++ 0x13f415d5 0x28487029 0xb69855e8 0x516cbedc
++ 0xfabbea88 0x9f90e8a1 0x211793d8 0x54653835
++ 0xa7789a08 0x754791d9 0x484764d4 0xdca45615
++ 0xf64844f4 0xdbd754d0 0x7d2b0ff3 0xd023e25a
++ 0xb048bbcb 0x83038b5c 0x57e17d17 0x735f1e9c
++ 0x8982c22e 0x6c7b2ad7 0xb26e3b82 0x7121e035
++ 0xe4ea8dba 0x68d4f406 0xaaafdb13 0xf119b472
++ 0xb5853303 0x20698005 0xcf34604c 0xdc17d19b
++ 0x042d6e97 0xf0300325 0xe1b55072 0xc2804918
++ 0xd6d7a912 0xf908c81b 0x4f9979ae 0x0179f8c6
++ 0x2f13e3c0 0xc5911467 0x39ad6c23 0x9c9d8837
++ 0xf3c3f767 0xe56b4a96 0xdad7cebc 0x6eaaee57
++ 0x2215ca7b 0x4cee4f65 0xd9a51c2a 0xf33c80a1
++ 0x11000000 0x0b468bda 0x0b57c7cb 0x885fad4b
++ 0x8a37307a 0x68cc7d5b 0xb6395b55 0x583626b8
++ 0x21efe98d 0xa516cc42 0xf5b978b1 0x585d8a11
++ 0xdd5f2ee4 0x17b1c7eb 0xb6f005ea 0x9ecc6ac6
++ 0x82c0f1b2 0x25a114fb 0xa6086296 0x93da75f4
++ 0x0695ff88 0xd413dd65 0xccf7609e 0xb7718aa8
++ 0x334406dd 0x28de253f 0xfb43ca83 0xa4674656
++ 0x7392e05f 0x9b062c62 0x17571892 0xb5811cbf
++ 0x9d64666b 0xa01c1500 0x5893e418 0x07ba6ed1
++ 0x0eebedd8 0x299a52bf 0xdfdb6191 0x4e846b26
++ 0x298b7431 0x576f4479 0xf5317e04 0xc9492745
++ 0x167c42e3 0x0c0cd705 0x82756ce5 0xe81ba860
++ 0x536c357c 0xc27433fa 0x41c8078f 0x1ff779d0
++ 0x73ddd76d 0xe606c66c 0xe0ad45bf 0xfebdc310
++ 0xcb2aa836 0x39903a79 0xe53d5dc1 0x0cb6a1ff
++ 0xe6091d08 0xcb2961d8 0xd38987ff 0x2bd624fd
++ 0xfb4e484a 0x8c60efbb 0x0ed088b5 0x5a142b04
++ 0xa737bab1 0x44da29a2 0xc046ecb1 0xe7ccefdc
++ 0x81895d2d 0x41266fa8 0x52a5e25e 0xcfeac133
++ 0x252b0737 0xec54b6c8 0xe1c9ebf6 0x25180c1a
++ 0xea65b9e2 0x5e9ada96 0x08559e07 0x414fcece
++ 0xdb4927f7 0xa229106d 0x6a7db273 0x8ac6a901
++ 0x00a87e4d 0x14fd1e2a 0x63a5fa87 0x5ca223c5
++ 0xc0c980c1 0x42c447ef 0x5b274187 0x75bd6279
++ 0xdb44dae2 0x60856af1 0x777caf5f 0x298e810a
++ 0x93f4f418 0x9e1ddf3f 0x6f589046 0x18ea149c
++ 0x4a5ce4b0 0x529db285 0x3c2dde59 0x1d680e51
++ 0x3a62d819 0xdf4c01d2 0x432a8f06 0x70a37043
++ 0x4a0d4baf 0x0d3395be 0xfce0391f 0x5228aac2
++ 0x9dd9b00e 0x6149f393 0x6fee1d85 0x1d3628cb
++ 0x107076de 0xd99fe940 0xa227eec2 0xc97d8119
++ 0xcf2fa8b2 0x821dac93 0x518875f2 0xd18d1d47
++ 0x3e27fdcb 0x47823f98 0x20d42c1e 0x9a58812b
++ 0xe0987435 0x1426f12f 0x61d6f627 0x5c58d415
++ 0xe5ca80de 0x9e11e526 0xbccc0f94 0xb49cec4d
++ 0x357f947c 0xbef0e2f2 0x5b9b2596 0xddc87ff7
++ 0x5f2705f8 0xa25f2be7 0xbb45a165 0xe49ef6d5
++ 0xe76e250a 0x75584c7d 0x7900da7b 0xee0e3360
++ 0x6988740c 0x4aa56944 0x2d485383 0xef45f5d5
++ 0x0df4b0f7 0x48199182 0x5b33c21c 0x8f2483c1
++ 0x8aae6c50 0xaf406ccb 0xb7522bda 0xeafb64de
++ 0x9a9b1fd7 0x3ab46c34 0x0ec5f025 0xe5bc9668
++ 0xdb108e78 0xd6152ac8 0xc382ec93 0x5abc2565
++ 0x4f256030 0x856f6eb5 0xb589dc96 0x3de80942
++ 0x49d20a05 0x8e3ac21b 0x0262ecc7 0x5f1bce89
++ 0xec50198c 0x0115b078 0xf67d94e3 0x1cc3682b
++ 0xfb2d4ab0 0x4d6ce252 0x1d7aace9 0xf7e99257
++ 0xc1235e85 0x8129ee72 0xb6cfbb13 0x6b851ab5
++ 0x430633d1 0xe9ed33e9 0xfe85a42a 0xb4583c0a
++ 0x35a65f5e 0x5fb0bc81 0xe16db440 0x7d022cf2
++ 0x8f832920 0x20ed9ad4 0x6a4ace8b 0xf4c85869
++ 0xf17dd57b 0x277ae0d5 0xb5f59c50 0x35d099a5
++ 0x9ce955ae 0xcb200000 0xcedc4073 0x2a2ba8b2
++ 0xa1b53439 0x46ced775 0x59069604 0x6488f5d8
++ 0x2bc0af55 0x643178a2 0x36f62be3 0x2606f0a1
++ 0x3057cf8a 0xc28f4a3d 0x708e8020 0xb3fccf9a
++ 0x29b79fa7 0x35622d93 0x85eb0e68 0x80fa3b59
++ 0x143f340f 0x20e17166 0x169fe55d 0x698f3655
++ 0x0bc8b45b 0xde3aaf6c 0xbd597266 0x75505401
++ 0x44d0095d 0x4c00f346 0xfb9ef2c6 0xee70ef96
++ 0xae807621 0xfbbe7490 0x9c0a283e 0x01a8058d
++ 0x1be53568 0x0b8dc8a8 0x45afb745 0x3ee1ff58
++ 0xe772e14e 0x3ca4e729 0x6973e751 0x764f244e
++ 0xca8d1621 0x6c4fb15c 0xae972e6d 0x3d26c6d3
++ 0x5ca8f450 0x6328d65c 0x2e7cd88c 0x87dddcc1
++ 0xcbbdefc6 0x1ab8c0cc 0xd21e503a 0x20c11d27
++ 0x2f0adc1d 0xc24240d2 0xc73aa069 0x99afc53e
++ 0xcab27e40 0xbe107ccb 0x8ad5f0ae 0x9024c188
++ 0xe02bb39d 0xdb784309 0xf91acb54 0x4d15b75d
++ 0xd339c237 0x3b556619 0xf69f91f6 0xca6fcfd4
++ 0xb5ddf471 0x0698490e 0xb0855c30 0xe2b34b13
++ 0x3c979248 0xc0484a59 0xb4cf9f4f 0x7975f2ac
++ 0x602259d3 0x89364c24 0x37f29913 0x0b4c88a0
++ 0x23f0b663 0x309c13d2 0x80a3d12c 0x4c866e87
++ 0xea7e29c0 0xbc33db6e 0x3c3af584 0x63da0de7
++ 0x9bc6bf5f 0x3b948269 0x4d41b09b 0x5724dd20
++ 0x4e16618b 0x5917781f 0x4bdec762 0x562cc3fd
++ 0x50e59d92 0xb3edea05 0xa6ceaa68 0x60af473d
++ 0x78a99aca 0xd60ba313 0xe502992c 0x0c25c2ba
++ 0x476eebd4 0xe7e23958 0xc4ac2757 0x0d6695ec
++ 0x7664b4f0 0xb87ed0a5 0xdcf23b2a 0x76d38802
++ 0x21699284 0x87b80e7c 0xf0e34f45 0x4bb84bc8
++ 0x0316744a 0x26de0ed4 0xb25ff5e3 0x31445bb1
++ 0xaccc5b87 0x271b976a 0xcdf5663b 0xe142d271
++ 0x1af28339 0x7d304ca4 0x11ee6243 0xdf70fbc3
++ 0xb8d88f25 0x4c2d9626 0x8eb72c77 0xceee1817
++ 0x4e1b35f7 0x6c261f67 0xa32a2801 0x67ace2af
++ 0x7c87f8c1 0xca6f2505 0x982269dc 0x137080a9
++ 0xe40fa78a 0x3897a66a 0xdc5d0ff7 0x58016e44
++ 0x21bcc988 0xf2a4df15 0x9fb021d4 0xca59e882
++ 0x3673d08e 0x7cf5d500 0xd41ab9df 0xc17b4a58
++ 0x2cb85aa3 0x01103427 0x5a8fac5b 0x7ac856b2
++ 0xb1532563 0x1b94b518 0xadea3bfa 0x597109a9
++ 0xf28df608 0xc2bf64bf 0xf517bb53 0x61b7d5ad
++ 0xa4a38e9d 0xa9fdc597 0xf990f2f1 0x00466640
++ 0xcecd06a7 0x5eef09d3 0xb67a08ae 0xd780d8a0
++ 0x07641a71 0x9dc9f7b9 0x5f0b5a44 0x94dfe40f
++ 0x6db0cf7c 0x3fe72d11 0xb2443ea3 0xe051f336
++ 0x4ec8a6a4 0x11201430 0xb44e2b28 0x5bd018b0
++ 0x444ba2bf 0xa63031eb 0x147f9826 0x3fc56ac1
++ 0xd3a75ad3 0xc3f71815 0x340bd72b 0x3e5a488d
++ 0x0cd8fb05 0x17791534 0x68e7321c 0x1489c701
++ 0xa39f2d71 0x7cbbd9f9 0x42cba365 0x024f7d9a
++ 0x29ef2da1 0x1eb9c4e6 0xc8b24985 0x9c33412c
++ 0x5fd3003d 0x7f0793b9 0x497b6ef4 0x3af648f2
++ 0x22f4a1db 0xac8500c7 0x3b1a859a 0x57921c78
++ 0xb0efd82e 0x8e60452d 0xd86ed85f 0xc1ae73d1
++ 0x633d83dd 0x7dbee7f6 0x46ef5590 0x027f2d50
++ 0x3c81bcf1 0x37a3940d 0xc92d0a8f 0x270cd02d
++ 0xaeed9d1c 0xb6d76bcd 0xda27f251 0x1625a683
++ 0xf2d1302d 0x3f95bc0e 0xdb4b36e0 0x96fe1e6e
++ 0x1dcbca54 0x57d44867 0x14aada62 0xf20f5444
++ 0x9ccf560e 0xb8d178af 0x9affe58e 0x8e3bd741
++ 0x7dff29e9 0x3c1998e5 0x9909e1df 0x1bbbd50f
++ 0xfda14fdb 0xb66fb65e 0xe646d5f3 0x71f41791
++ 0xbca50c12 0x57c6d2a2 0x8f5c750f 0x48f87301
++ 0x9103acac 0xef185c41 0x6dbe9524 0x3c040c16
++ 0x211dc2ac 0xa61925bb 0x20bfb41a 0x98253e77
++ 0x4d5ea3b8 0xc2b11b6d 0x7f072104 0x58340448
++ 0x596e3090 0x72484d15 0xf5e5d16b 0xc1b9faca
++ 0x5c786fdb 0xdcd97509 0x73d21aa9 0x2a90c7ae
++ 0x396ed0b1 0xa23e63da 0xea20cb1b 0xb2bb359b
++ 0xb5df6ff5 0xdbc470b4 0xa6fd8d97 0x9458f6d0
++ 0x97434866 0x2c9521c4 0xc51f6ad2 0xa33fb3b5
++ 0xb26915d7 0x3ef363da 0x9ff9f5c7 0xfa236e60
++ 0xa12b879d 0x2f98bd3b 0x95282ca8 0x64f90513
++ 0xc03d2962 0xb13b82f8 0xfdc2eb41 0xc39dcf3b
++ 0x95a409af 0xbaba6e7e 0x0d028543 0xc5b9426b
++ 0x35f5727b 0x8f3b9f8c 0x6e7b85d8 0x2cfa9b2e
++ 0x2a7117cb 0xa41f3fe5 0xbe17ff18 0x0f4a8be4
++ 0x20b9003a 0xebce04ff 0xd6f276d6 0x9fc66d07
++ 0x83f40250 0x560eaffe 0x92be2ddd 0xdb0ff83e
++ 0x424f0605 0xb3cf76a4 0x167725c5 0xe3b513e2
++ 0xc31a1a72 0x9f7161a4 0x25707dd1 0xdb5f2a91
++ 0x85db06af 0x78443bf6 0xebbd8e7d 0x7909e5fe
++ 0x618237a6 0xe6dea70c 0xcd3299c2 0x7736d40a
++ 0x044cda94 0x6cec190e 0xb9652583 0x51946c01
++ 0xcba67203 0x0dae0f1d 0x6d0dff0d 0x85756bf7
++ 0x1db9e08a 0x88977944 0xa6252c60 0x06ff1a07
++ 0x1b8d319f 0x884f10eb 0xbdeb7feb 0xe1681bb9
++ 0xb5f0cefc 0x5359534d 0x6de87cf9 0x94a78727
++ 0x15c17557 0x398876df 0x2f85f258 0xa0284d4b
++ 0x4879ca57 0xb5ab7844 0xb402fde8 0xd520cb53
++ 0x8a601365 0x8853b510 0x1e0538f6 0x0135f899
++ 0xa78c7bba 0xa33c8ccc 0x6cf0da00 0xa5f96757
++ 0x94714373 0x79413ed2 0x27c7b9cd 0xda172153
++ 0xeeeee91b 0x959d8437 0x660efcda 0x2a6ab94a
++ 0x8913d65f 0x24246350 0xf6c85ab5 0xf6b696f7
++ 0xd75840c8 0x046b7435 0xb55474fc 0xd8d8bab0
++ 0x265e79e0 0x0dd030b3 0x826a182c 0x38f1121b
++ 0xeb33b5cb 0xe3ca835b 0xe8850761 0x25955d7a
++ 0xbb6b7fb4 0xbc02ca0f 0x1b03bd1f 0xdd1a59d6
++ 0x5d48f10b 0x35e35688 0x1411d34a 0x6131c664
++ 0xc1b8b277 0x1bc8afd3 0x886f0c09 0xc1b6b517
++ 0x74ec9ecb 0xee2d43a5 0xbc0f122a 0xd1911c88
++ 0xc7e39b2e 0xa60c39b0 0x942fce7e 0xc8c2a2b6
++ 0x51978cc2 0xad8d9ed2 0xcc2b0c3d 0xf6aff0f7
++ 0xbfb3920a 0xd25aa79c 0x67d87d44 0xf612df60
++ 0xf06dbe9f 0xd4ab61da 0xd96c6b1b 0xb39ab4b7
++ 0x3368a90d 0x39c8bd81 0xf4ba5ead 0x6fe656ad
++ 0x93b946dc 0x2181219e 0x7b98805d 0x675af3fd
++ 0x59760289 0x934b4803 0x4189f27d 0x9503a5fd
++ 0x42aaa076 0x6b4bd024 0x86c826e9 0xe0370ff4
++ 0x1bfdf980 0xc487f797 0xd4754c3b 0x1098b2e8
++ 0x05753a1c 0x3833ede3 0x5f1065ec 0x40cb562e
++ 0x8d4fc418 0x392290d2 0x622d2e29 0x55df1f46
++ 0x4ae0893e 0x24ddf8a9 0x302a64dc 0xc93f7504
++ 0xde8e1674 0x033acbcd 0xc9732a64 0x6f7a7da3
++ 0x72b7c43a 0xb5110e6a 0x00865c19 0xaf5e00f7
++ 0x0a80b55d 0x6e638c0c 0x3771d602 0xb4a95ae7
++ 0x01ba3cff 0x42e350eb 0xedb1d897 0x82f0cfff
++ 0x98e79055 0x6b0cc62e 0x8ce1735b 0x62645395
++ 0xd99fc208 0x86ee3066 0xc8f13758 0x2378d582
++ 0xad41c218 0xc3954b87 0x47acab9a 0x69126227
++ 0xbf778357 0xc5a7b76c 0xb96894c4 0x89e2dd88
++ 0x27cc53b7 0x2187116c 0xd397c13b 0x578a6686
++ 0xe3e58b11 0xdc3e4d40 0x69f064f5 0xdfb64348
++ 0x42291e77 0xacc21c46 0x5444d976 0x616bcdc1
++ 0x01ffb3bd 0x5cb926e5 0xbd763a24 0xbf224c70
++ 0xdeca1d57 0xded1cc56 0x9b6cbcd2 0xee6efaf4
++ 0x44d634ff 0xf33334c6 0xd275d66b 0x6a1a4c9d
++ 0xbd675ae0 0x6289d1c1 0x053aeaf0 0x8a170aa1
++ 0xe12cfbb9 0x0ae15a94 0x1dab08f3 0x9a2657ab
++ 0x8348417f 0x9572e6dc 0x9c69e518 0x5397dfa1
++ 0xe46120cd 0xad4457fa 0x0106a79d 0x40b191be
++ 0xbb64bccb 0x9dda8fb0 0xc74fe994 0x64ac0ef1
++ 0x3a57986c 0x86e8dc78 0xbb055d88 0x7a1243da
++ 0x585cafe1 0x8968ad92 0x5b73bf26 0xccf77edc
++ 0x10ac1643 0x5738ba43 0x3d39ecee 0x57fd555b
++ 0x36ee9d5b 0xec9115fb 0x4250e03f 0x9e4fd6a6
++ 0xc547b01e 0x9c84f42a 0x37756616 0x217cb517
++ 0x33da3c5e 0xa0a7ae6f 0x8ddb7b99 0xbd84ac35
++ 0x644ec4e0 0xaa62a7ac 0x71795f77 0xd5f67163
++ 0x77dcc227 0x59f09342 0xf6666ce4 0x1e164a0c
++ 0x011e205b 0xc4a80a0c 0x7fd31f1d 0x05ccae4c
++ 0x39b6abfb 0xf4b7ac82 0x39d38e89 0x14c1e7f3
++ 0xdb3bb53b 0x02577ec5 0x7bc12087 0x65ccc2bd
++ 0x72492c6e 0xa6ae0062 0x965946ea 0x58e5f31a
++ 0xfdfd7770 0x052afb9c 0x889b8358 0x2dd65c3e
++ 0x55418587 0x445af0e9 0x43fe6671 0xae45e776
++ 0x2c25d02c 0x44805865 0xaa3a70c5 0x7dd55d11
++ 0x3499f5d7 0xc12e4a51 0x9ef98a38 0x5462e98c
++ 0x0f73c72f 0xd0481aa2 0x56bccd0e 0x64143a1a
++ 0xa7913ef6 0x0ca932ae 0x3739ec96 0xac5d38d5
++ 0xe9c8c754 0xd56e855b 0x950cadcc 0x91cb2e5e
++ 0x6e170c11 0x1eb66637 0xf641b0ae 0x8ba43c21
++ 0x3f43b8af 0x8f1596e7 0xb614d1ae 0xac99c14c
++ 0xe7beddce 0x5757f98b 0xfec1cf89 0x19608162
++ 0x96479a49 0x1f089d9e 0xc2e4ac47 0x1cdea563
++ 0x027f57a7 0xc0ba57c6 0x6eb2faa1 0x8e85c333
++ 0xc391dfd2 0xe2c0bcbf 0xc1f87d66 0xb597d958
++ 0x3655d5a3 0x2d9adaaf 0x8efd0aa0 0x05d65caf
++ 0xa28991d9 0x28b6d7cf 0xdcb48013 0x65e75783
++ 0x8b8b77ed 0xa4b36df8 0xa8ccfb9d 0xd0a1734c
++ 0x2dc97601 0x35d81082 0x2e6d26f8 0xf3baf2c5
++ 0x416084dc 0xd8b84ad5 0xa06b9edb 0x45c2b0b6
++ 0x553c973a 0xbbcda1bf 0xca154d25 0x7a781012
++ 0x4864ea32 0x0784f663 0x27656507 0xb359d4dd
++ 0x43d4c165 0x69b844c7 0x31b1b9e2 0x0f3420f8
++ 0x3cd2e455 0x201920cb 0x93018659 0x5c4a08f0
++ 0x3a0d094b 0x5448c1ed 0xc888d1a2 0x4826cb64
++ 0x625da2c7 0x12110d40 0x5cd8e76b 0x26e09eb5
++ 0x8c6aab45 0x6dd192c6 0x937f1252 0xc927efc5
++ 0x4c5bf11c 0xdd62c6fa 0xeef59620 0xbffc2d5b
++ 0xb90299f0 0xb24df71b 0x76656678 0x550b3228
++ 0x01536098 0x4fbfe03c 0xa82d0c31 0x2eec9bb6
++ 0x752e6720 0x26322556 0x5d94bd64 0xa2e1122a
++ 0x25899986 0xb63d5cc2 0x9222b055 0xbf4f0bcf
++ 0x3d182483 0xc7bb9999 0x97ffc8c1 0xa6500a8b
++ 0xb8b97382 0x3f6f39b0 0xcaca9f6c 0x7b67941d
++ 0x7875ea1e 0x3ff25c0d 0x4cff1a40 0xb5a351ef
++ 0x556a59e5 0x011e995f 0x25a7a5e9 0xedc8707a
++ 0x42b4ddfa 0xa51a3ddd 0x9c9f1d73 0xc8f24ef3
++ 0xfcd73118 0x1a61c16f 0x1e2fa7c7 0x1f49826a
++ 0xd8418fe9 0x726358a8 0x6a0857fa 0x6804ccc1
++ 0x78a55fa0 0xc3e41419 0x60416b10 0x2afe46d8
++ 0x0c0ba2f7 0xd3dfa8ca 0xfa474ea2 0x8e763446
++ 0x1f664c64 0x6a8d06cf 0x1b891114 0xa27c1a28
++ 0x98ddd324 0x26cc9fb8 0x544078da 0x03acbeee
++ 0xc3f3b761 0x56797b83 0xf04ac5a1 0x8603b17f
++ 0xb8989b96 0x28c7be17 0xb750b4a6 0x84b2f7f8
++ 0x32138f9b 0x7661c86b 0xb7517518 0xf2a961c6
++ 0x240a0100 0x100c5b96 0xa1931730 0x18513938
++ 0xdf2baa73 0xd6b55cce 0xf89cab59 0x238c90c3
++ 0x4799f50d 0x29cd7942 0x62677a47 0x7261f326
++ 0x4ff7da96 0x294ba5e9 0xb6474251 0x96de1b44
++ 0x9d84552f 0x1103468f 0xcfd063af 0x5d8a0b6c
++ 0x172670ac 0xc1a9b97f 0x0a278773 0x08b48bb5
++ 0x392b3563 0x8f65e926 0x4be71f10 0x7615e05e
++ 0x98b0c931 0x50bf9779 0x5baa97aa 0xb6e26fe4
++ 0x2c40971a 0xe5d739f0 0xa7e30500 0xc724895c
++ 0xc7a3f44a 0x5b381b1b 0xa7a478c7 0x219f567c
++ 0x42d7a960 0xaae6780f 0xa96c56d1 0xe3787bf4
++ 0x743f3a5e 0x6b99c9e1 0x36cf72b0 0x784ab5c2
++ 0x5113773d 0x625393af 0x62c4da61 0x05422921
++ 0x339711f3 0x3ee04f5e 0xf3a778b9 0x55e1bcf7
++ 0xe49e5a9f 0x5f0935f6 0xa13e17f5 0x3028d23b
++ 0xac9a6fd9 0x14006013 0xbf1b3fb2 0xce785f7b
++ 0x83942244 0xd299d59b 0xf8c0593b 0x71c74beb
++ 0x7561a1f5 0xb133ace7 0x15d5d4c1 0x21c3bb29
++ 0x6ab1c2c7 0xee20d3dd 0xcfd62c54 0xedf9a43e
++ 0x0e23222c 0x5eef5bc2 0xe7426bd0 0x42db58e9
++ 0x62ffe203 0xd63163c5 0x8dbbcb48 0x9e16d9c7
++ 0xb6d51e39 0xbee5a6c4 0x5d0bd775 0xeded86db
++ 0x9eb1454f 0x6217eb64 0xa4b76ae7 0xe3481698
++ 0x6d576cec 0xe751f610 0x1473bd83 0x4aaead8c
++ 0xff4a602b 0x01ed092b 0x310f16cb 0x2e199177
++ 0x693a8ad1 0xf5e520d1 0x1713d604 0xfff1225c
++ 0x644c81b8 0x1adf5032 0x79058d81 0x7aafda08
++ 0x80b6c9df 0x6f927c46 0x307bcaa6 0x0a1aac12
++ 0x7d20bdae 0xd0e9c9a7 0x4530bebc 0xf1dbac36
++ 0xdee3e8a9 0xa96d2aca 0x291c6944 0x436cfac8
++ 0x9dd501c3 0x696e0c6b 0xa85d7036 0xca1c1321
++ 0xcb802235 0xae614fec 0x4f0cf745 0x08604468
++ 0x93bd00f3 0xf39eb605 0x89a8f420 0x18a7f61a
++ 0xa0aebc3b 0x723e6ba9 0xed00f2a0 0x231b43d5
++ 0x37c81702 0x891ffeb9 0x122de4f5 0x90f16757
++ 0x1eb06046 0x21d5cdd1 0x75fd0e6f 0x7d595ae9
++ 0xeb8ed50e 0x7bfd8696 0x3b91f3e4 0xd629e74a
++ 0x1650dfcd 0xda48163d 0x2f8f5aba 0xbc40ee60
++ 0x5291b6b0 0xb059d788 0x1ed5f092 0x65b7a885
++ 0x44503d18 0x3a2893c8 0xaf3dab25 0x8ee0a8e5
++ 0xf82f0696 0xf4fe9322 0x863feff8 0x2cfee629
++ 0xacd8bcbc 0xb3791232 0xdd694c06 0x2a606479
++ 0xaed9bc38 0x49a126fd 0x2a9c7581 0xaf43095c
++ 0xb97acc90 0xca7a25b6 0x06adceb3 0xc8bf7269
++ 0x6eeb0c59 0xa953657b 0x8e175c3a 0x9facc87c
++ 0x4c143d0b 0xb4467fe4 0x372b6cbf 0x2099b361
++ 0xb8ac2cfe 0xb9a798d0 0x15b8b336 0xdab5d568
++ 0xb53a4dda 0x00ce1ef7 0xefef7644 0x41823aa2
++ 0xcb8d307d 0x3baf1baa 0x7124a219 0x8d2820df
++ 0xf3b8cfed 0x95e55a1b 0x8199fa40 0x631042fc
++ 0xf7886353 0x3592b875 0x3b516841 0xac7aa00a
++ 0x3dbfec52 0x9b91e8d6 0x0a8ffce6 0xd11429db
++ 0x92392bec 0xe194095b 0x253d7425 0x6b55919c
++ 0x4c11de8c 0x10b46ae6 0x5902c153 0x9509ace0
++ 0xbb65fc04 0x648a35e0 0xab728bec 0x738effb4
++ 0x416f95fd 0xee30a0da 0xcbaf3cb4 0x312fdeda
++ 0xcdb5aaf3 0xcc631b82 0xe3bf4d97 0x37e2a1b5
++ 0x2920c6b2 0x0d995ad3 0x11af607c 0xcacf31d6
++ 0x781496f2 0x9e478c0e 0xc4c14545 0x89ba2ab0
++ 0xdb1a8262 0xbb924c65 0xad836a24 0x4374fbd6
++ 0xd45a10df 0xd4158c0f 0xd4e88c1a 0xee8b8e23
++ 0x3472ee5c 0xc0a0de0c 0xb1ba04dd 0x7be6532b
++ 0x0101669b 0x2a56f032 0x12879eef 0xa600458f
++ 0x20a96992 0xa2e7910d 0x13235ef1 0xb1185320
++ 0x418ffba7 0xc0ba01af 0x27571c7a 0xde5b661f
++ 0xdd359089 0x6ae76b8d 0x095784d0 0x400a29fd
++ 0x5b3276cc 0x774c4e38 0x6a85e14f 0x37d8d1bd
++ 0x2007cea4 0x3e6942be 0x1a49828d 0xea4d84ff
++ 0x681b5a30 0xd8ff8440 0xac19844b 0x7553a6d0
++ 0x389fb0a2 0x1b0526fc 0xa193b9e0 0xb9987cb7
++ 0x6f14d980 0x0507f958 0xf6a1354f 0xcb9e49d8
++ 0x5a4e1d3f 0x10d8c348 0xb77cf166 0x5097503d
++ 0xf0e17ed5 0x72a2e029 0xddc756b8 0x0a0e30e8
++ 0xf12c6bc7 0x809db2c5 0x243fee9c 0xd2b57957
++ 0xc1b19244 0x8d59262c 0xff94c28e 0x2050edc2
++ 0xa4806d15 0x02026bf6 0x2d95c9d1 0xeb336e65
++ 0x84bcf6ac 0xe53b97b7 0x954eedc9 0xf22209fe
++ 0xf4771bc0 0x1e405f04 0x1d0ec592 0xcd479333
++ 0xdfeb3738 0x0ae23cb7 0x03d509c5 0x837a5e1a
++ 0x634a4467 0x7ee22185 0x102f5326 0x5d002daf
++ 0xea4e31ce 0x1d2be82e 0x5ebe1ad6 0x354259bd
++ 0xdaed312d 0x1e598ea0 0xd6a2b9af 0x76eb9bbb
++ 0x338645d3 0x4d3236f8 0x777011eb 0x0221d076
++ 0x22dee347 0x1e35037e 0x2f34d4c5 0xdda03e2e
++ 0xa541311d 0x3acf0087 0xb435b17c 0x08b8210e
++ 0x7c77f156 0xe20025f2 0xea0e32a9 0xbf766fd1
++ 0x8b6c4f43 0xf6ca80f1 0x07d1d342 0x272b865d
++ 0x8261aed7 0xf3bbe9cf 0x5835370f 0xfaaf4623
++ 0x8cb5a665 0xe6c92e5f 0x22ce69f6 0x61e16f89
++ 0xf15ec311 0xbacaf7b4 0x1317e388 0xa1869c49
++ 0x328da67f 0xd818a8fb 0x6f4c7613 0xcc13480c
++ 0x06789788 0xa7b4e1a8 0x0d8fed7b 0x48308fe3
++ 0xbe5ff9e2 0x7e7a74ee 0x4ffbb70c 0x551895c8
++ 0x734ffc0e 0x82b8b8d6 0xdf710f9c 0xc3df529d
++ 0xf175e377 0xcec6194f 0xc3443fb1 0x52655208
++ 0x94be229e 0x3279939e 0x771647a1 0x34c9a15a
++ 0xaae80baa 0x0b32ec13 0x6d59b440 0x50ddd10b
++ 0x98c166cd 0xfd465f40 0x74eabbc2 0x6dcb95c0
++ 0xddef6f85 0x54348377 0x905f31bd 0xbde86f48
++ 0x1322356f 0x90f3d5f2 0x5d2d4de3 0x2d5253a5
++ 0x729b8879 0x41839289 0x845f8061 0xf5ffcf8b
++ 0xf25ec4d7 0x30570dda 0xcc69f64b 0xeb024bde
++ 0xc847bf80 0xeb8c5624 0x4e4d28eb 0x43f6cc1e
++ 0x8c201bfb 0x1475f9cc 0xde13b005 0x11fd9342
++ 0x07617ac9 0x2fec6867 0x5b30a62e 0x5a8c91f7
++ 0x47208b6f 0x680a22af 0x60fd0ebd 0x229ebe44
++ 0x568c37d6 0xa3eb78b7 0x6f06f502 0x1b183db2
++ 0xd48e4d35 0x4fb23b3d 0x57d7dc0b 0x3d34b427
++ 0x0415552f 0x1bbe91d1 0x74e7ecf8 0xb1fdc30e
++ 0x466a69f5 0xfddf86b3 0xfb61fd48 0xae250961
++ 0x6a99bcec 0x2142c5c8 0x1c08d4ea 0xe8f849c2
++ 0xa3cb1614 0x43ac8702 0x22b50659 0x92dc3644
++ 0x7a40a305 0x4a1e0780 0xfb638be0 0xb0912795
++ 0x522a688e 0x1133c55d 0x0544a27b 0x3c56a574
++ 0x748502e1 0xaee58228 0x30ae0736 0x41a029ad
++ 0xa1e3d0e1 0xa9b66582 0x6ec07231 0xda4dba0d
++ 0x41db8fa0 0x731529eb 0x87f679d3 0x593d1579
++ 0x10935a3c 0x793d7b44 0xac680a86 0x1d01ec27
++ 0x6d669681 0xef056753 0x96aab271 0xae070e5f
++ 0x3321dc26 0xa5ea33a2 0xf8f14406 0xdc755c9d
++ 0x7f8e3210 0xc2fd90cd 0x34c102d7 0xe1c744a7
++ 0xa79f623f 0x07507959 0x34d28c67 0x26cbff85
++ 0xfa24075b 0x618dcdfc 0x64d52c6e 0xce650b7d
++ 0xcc414394 0xadc52ceb 0x43667ed0 0xa04f518d
++ 0xe52196a2 0xbcb7e578 0x2ed0486e 0x4d669b00
++ 0xf765e153 0xd2f097df 0x4ef97542 0xfa31d688
++ 0x1698d42e 0x3d828d65 0x222355aa 0xf2c37eb2
++ 0x3da4052b 0x198577ae 0x819590ff 0x5ab919a5
++ 0x673d5552 0xd2fa9d52 0xb711b72c 0xabd9c188
++ 0xb73a4ce5 0x2d20447b 0x3d19d4c4 0x4bbe86d0
++ 0xd205021c 0xe9875ec2 0x8dcb01f3 0x6e109fec
++ 0x60a3a693 0x2fb6b975 0x0ed26de1 0x7487f920
++ 0x83092880 0x4d5fcb5d 0x72b047d0 0xa256dcdd
++ 0xfef28251 0x41e36ee6 0xd91e2c20 0x7698357b
++ 0xb3684b1a 0x272311be 0x32860f75 0x44a6cc61
++ 0x63e3f66f 0x5a1497b7 0xeddf5a57 0xcdd4577c
++ 0x3cc63cd3 0xf7e72773 0x3fc9bb40 0x97ce4118
++ 0x1438da68 0x7a32210b 0x2aa07598 0x04e858ca
++ 0x850e0082 0x0b0f78d1 0xb178c391 0x9a2e231e
++ 0xa8f3b67b 0x2a08ea99 0x340d101b 0x42973ffa
++ 0x755ae5cf 0x201213c4 0x445e44f7 0x15a872c8
++ 0x857b94f3 0x24c023ab 0xb203df2a 0xc4711de8
++ 0xd1faaeea 0x1eb857b6 0x8c1b712b 0x11ad0f2a
++ 0xc64cf474 0xff6c128c 0xff13eac3 0xc4952e8f
++ 0xacdac9d1 0xb8c2f092 0x38d50a33 0xaeec4534
++ 0xa661a7ee 0x4d19a2bd 0x0f2d95e4 0x9a221827
++ 0xc9fe071f 0xe53486d7 0x1dc5426c 0x848eea4c
++ 0x607f616b 0x41a301f6 0xeadc389c 0x1f109048
++ 0x249f14da 0x2a20d362 0x7c93cd00 0x7ca633e8
++ 0xe50fb5a4 0xace8f92f 0x49638c89 0x478b4371
++ 0x60d70e8b 0x0bfb8bfb 0x6cac803d 0x702996e4
++ 0x15a35d2c 0xd68a2d93 0xe025d5ee 0xd8ca8c86
++ 0x295393d3 0xce1be3f8 0x0ee6bd15 0xd6735f38
++ 0x311495e6 0x7eb8bc83 0xea53551f 0x4fa9a90d
++ 0xe16a9ea0 0x651eb233 0x95f0afec 0xc687ed29
++ 0x0cd3abc8 0x132bb8b4 0xd70dadd3 0x538e630a
++ 0x98481e4c 0x0d7e6f1b 0x3986b2de 0xbe0924dd
++ 0x1d14608e 0x189f553e 0x7a6b7786 0x48bae520
++ 0xed56a3cf 0x795b4c6f 0x8670597a 0x40eb02ab
++ 0xf9b0b287 0xec9f86c3 0xe9a8c3a1 0xe6860542
++ 0x387ad930 0x8676e402 0x633f0709 0xd661d134
++ 0x011c1396 0xabf1f3f5 0x3fd76128 0x7be75289
++ 0xa6046e69 0xf3713680 0xa2ed30c5 0x893df28d
++ 0x197b8543 0x9860bef6 0xf6930c5c 0x6c0c379b
++ 0x0b0026e1 0x3ca86896 0xa7ea0bdc 0xca94413f
++ 0x6cbe8d16 0xd3e4edf9 0xb06efcef 0x3a8934c6
++ 0x00195592 0xa978bf0c 0x7435b0d1 0x3b17d97c
++ 0x0438684e 0x576ced8e 0x648683fc 0x362a8a87
++ 0x493fd86f 0x6bbe0476 0x16f74de4 0xbfeaaba8
++ 0xe6b90728 0xdc252878 0xe0b72eac 0x0872f52c
++ 0x2bab1521 0xa6c0d894 0x9f2b3726 0xd392e334
++ 0x785f82ce 0x15bba4af 0xb55cd743 0x6e8e9cf8
++ 0x047fd2e7 0x1fdfe424 0x8d4820e5 0xce7dd8c3
++ 0x88c82282 0x31ef9a76 0x1881fc38 0x3932a9da
++ 0x65bbfefb 0xe00f33b6 0xdd0754aa 0x1f596051
++ 0x704dfd7b 0x2604be1b 0x08b6c4f5 0x3f244085
++ 0xd89c65e3 0xcc4cdb71 0x143a2681 0x1bd3d004
++ 0x009460ff 0x86e314a5 0xb1aff86f 0xaa2599df
++ 0xbf68de69 0x355c8267 0x9588dbed 0xe47edd9b
++ 0x266b2ddd 0x129b0b01 0x6e6622a6 0xb3ea4a00
++ 0x802abd6b 0x7a268c1d 0x9f5a7b41 0x6f4aba0e
++ 0xe279b988 0x660ef08f 0xf4207beb 0xfa0168f6
++ 0x93266ea0 0xedfef092 0x302b5e5f 0x7278d2be
++ 0x58a494ab 0x8f53a302 0xf5e766de 0x1ef717bf
++ 0x45e2d6fd 0xf593b066 0xaea0f1e1 0x1bd1e027
++ 0xf853ba21 0x1127c5c4 0x8aa43b18 0xf1fba0b8
++ 0xe1cfb0b8 0xa9f9fef6 0x1320f1ab 0x5f7dfc74
++ 0x30f11ab4 0xaf47a3cc 0x9c190830 0xac085edb
++ 0x8b4db7c8 0x771ec065 0x6d5f3c3f 0xb8815437
++ 0x20d3c99c 0x00823c74 0x24d63cae 0x7587e453
++ 0x1a3fd67b 0xa5b361cd 0x789d168b 0x98a93943
++ 0xd7505c0a 0xa923b38d 0x46097a4f 0x814e41dc
++ 0x0f50f2de 0xbb548368 0xc48273d4 0xf27b6798
++ 0x9a6b5231 0x68491e7b 0x3f482179 0x89ea3b35
++ 0xa7525ffd 0xf8f1f616 0x07859572 0x738cb4b3
++ 0x8937c6dd 0xf5988c71 0x4874905e 0x677a8c17
++ 0xd58df987 0xc4210078 0xe6b1c480 0x7a91e14d
++ 0xa1228a7a 0x09057467 0x6cd59ec7 0x6ba93248
++ 0xb8e263cb 0xd3305730 0xaec36ee6 0xc773d0b5
++ 0x2895f8ec 0x6c9f5fb5 0xd32a21a5 0xcea9d058
++ 0xfa97282f 0x5559ceb4 0x5a0bf57c 0xf3cd99b5
++ 0x2771f6c4 0xfcc9a35d 0x5143417e 0x7c6f9db7
++ 0xb47cb7df 0xe7dde37b 0x70a07531 0xe25e06a2
++ 0x3bbb7d30 0xaf41b085 0xe664f973 0xee2c7ab7
++ 0xef8eb1b5 0xfba67f7d 0xd71568dc 0xbbff3339
++ 0xdf49725d 0xbc0e7edc 0x5361e6d3 0xb0978c73
++ 0x1320540a 0xa9843a06 0x34099c74 0x4bdddd23
++ 0x18680496 0x44f9cc19 0x6de71a34 0xe4eae858
++ 0x3349a819 0x28400571 0x10a55fe9 0x05672399
++ 0xb376eadd 0xed4b1a35 0xe79d0a4f 0xca8d0601
++ 0x78a7b066 0x8ea59a40 0x7be112a2 0xe99ea438
++ 0x44bd9efa 0x6e5227a1 0x70325aef 0x777282e9
++ 0xb579c189 0x4ee92bc9 0x0d0236dd 0xb57cf232
++ 0xb815e184 0xd05823e4 0x0c9490b8 0x70a5fa56
++ 0xdf0f178a 0x99d27374 0x1aba9e05 0x18378c3d
++ 0x86991118 0x3a199a70 0x90b2a2cf 0x67a6923b
++ 0x0975e5f2 0xf50fb0a3 0xbffbd67a 0xce6371e7
++ 0x203564ef 0xb1d7a395 0x201cb1c4 0x30085e3c
++ 0xfb2c66b4 0xf80ae969 0x1d407625 0x0bca1a0f
++ 0xb62c078f 0x83efbf38 0xbd7b0a69 0x7d9bb66a
++ 0x46b5c885 0xb256d753 0x0b5d008e 0x1756d5bf
++ 0xa9ffdaf6 0x01231fcb 0x8c69e461 0xbb2ad661
++ 0x29dee8f7 0xf1f23d56 0xd5e90ffa 0x48d9d93e
++ 0x77b26e95 0x49c47953 0x7565da8e 0x41a6124a
++ 0xfce69643 0x55f99554 0xa5501d6e 0x5738b726
++ 0x4c989c96 0x93cbe27e 0x20ff3d38 0xf4787a09
++ 0xfa3520e4 0x26b2dc11 0xb701c94b 0xcd8857ee
++ 0xb4b07229 0x0bbcf1a7 0x3d31cd32 0x08ced413
++ 0x3da04c1d 0x7bdf1787 0x344f510d 0x53a02e8e
++ 0x7e295418 0xa5ed24b3 0x3a5a2c98 0x34947e44
++ 0xb398bfcb 0x7c0ea498 0x18db3289 0xec646beb
++ 0x2e8ed766 0x5aff9ee3 0x497dc7fa 0xa70c3be4
++ 0xfc9306c4 &nb
projects / openwrt / openwrt.git / commitdiff