layerscape: add 64b/32b target for ls1012ardb device

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.

The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.

Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>

diff --git a/package/boot/uboot-layerscape-32b/Makefile b/package/boot/uboot-layerscape-32b/Makefile
index d6a6d2654a858d372d7ee29253308590f020567c..c4e6213ac7cfa4f7924068a5f88afc0e2ca6f49a 100644 (file)
--- a/package/boot/uboot-layerscape-32b/Makefile
+++ b/package/boot/uboot-layerscape-32b/Makefile
@@ -16,7 +16,7 @@ PKG_SOURCE_PROTO:=git
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
 PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
 PKG_SOURCE_URL:=https://github.com/fsl-jyt/uboot-ls-32b.git
-PKG_SOURCE_VERSION:=4fbf7e76eb7671d9822d0310319f6ad70d324547
+PKG_SOURCE_VERSION:=719f8b606334bc73367f78c204dce69786963b65
 
 PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
 
@@ -35,8 +35,14 @@ define uboot/ls1043ardb
        CONFIG=ls1043ardb-uboot.bin
 endef
 
+define uboot/ls1012ardb
+       TITLE:=U-Boot binary $(PKG_NAME)-$(PKG_VERSION) for NXP ls1012ardb 32b Dev Board
+       CONFIG=ls1012ardb-uboot.bin.swap
+endef
+
 UBOOTS := \
-       ls1043ardb
+       ls1043ardb \
+       ls1012ardb
 
 define Package/uboot/template
 define Package/uboot-layerscape-32b-$(1)

diff --git a/package/boot/uboot-layerscape/Makefile b/package/boot/uboot-layerscape/Makefile
index fa07b32c8f4508093ee1391e1739a253e02d9801..dd9ade61c1eb650ee3feb752886559641d3e0d7f 100644 (file)
--- a/package/boot/uboot-layerscape/Makefile
+++ b/package/boot/uboot-layerscape/Makefile
@@ -33,8 +33,15 @@ define uboot/ls1043ardb
        CONFIG=ls1043ardb
 endef
 
+define uboot/ls1012ardb
+       TITLE:=U-Boot $(PKG_NAME)-$(PKG_VERSION) for NXP ls1012ardb 64b Dev Board
+       CONFIG=ls1012ardb_qspi
+       IMAGE=u-boot-swap.bin
+endef
+
 UBOOTS := \
-       ls1043ardb
+       ls1043ardb \
+       ls1012ardb
 
 define Package/uboot/template
 define Package/uboot-layerscape-64b-$(1)

diff --git a/package/boot/uboot-layerscape/patches/0006-armv8-fsl-layerscape-Put-SMMU-config-code-in-SMMU_BA.patch b/package/boot/uboot-layerscape/patches/0006-armv8-fsl-layerscape-Put-SMMU-config-code-in-SMMU_BA.patch
new file mode 100644 (file)
index 0000000..a8a9aa3
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0006-armv8-fsl-layerscape-Put-SMMU-config-code-in-SMMU_BA.patch
@@ -0,0 +1,37 @@
+From be06181f45695ce71536ecb461615ebf6f18011e Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Tue, 15 Mar 2016 13:40:07 +0530
+Subject: [PATCH 06/93] armv8: fsl-layerscape: Put SMMU config code in
+ SMMU_BASE
+
+It is not mandatory for Layerscape SoCs to have SMMU. SoCs like
+LS1012A are layerscape SoC without SMMU IP.
+
+So put SMMU configuration code under SMMU_BASE.
+
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S |    2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+index 93f4a65..5f5bfb9 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
++++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+@@ -95,11 +95,13 @@ ENTRY(lowlevel_init)
+       bl      ccn504_set_qos
+ #endif
+ 
++#ifdef SMMU_BASE
+       /* Set the SMMU page size in the sACR register */
+       ldr     x1, =SMMU_BASE
+       ldr     w0, [x1, #0x10]
+       orr     w0, w0, #1 << 16  /* set sACR.pagesize to indicate 64K page */
+       str     w0, [x1, #0x10]
++#endif
+ 
+       /* Initialize GIC Secure Bank Status */
+ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0007-armv8-fsl-layerscape-Avoid-LS1043A-specifc-defines.patch b/package/boot/uboot-layerscape/patches/0007-armv8-fsl-layerscape-Avoid-LS1043A-specifc-defines.patch
new file mode 100644 (file)
index 0000000..6cb1847
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0007-armv8-fsl-layerscape-Avoid-LS1043A-specifc-defines.patch
@@ -0,0 +1,44 @@
+From 825d623c913c63b1f00c42f27ef0916b11d9f09f Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Tue, 15 Mar 2016 13:40:22 +0530
+Subject: [PATCH 07/93] armv8: fsl-layerscape: Avoid LS1043A specifc defines
+
+Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant.
+
+So Avoid LS1043A specific defines in arch/arm
+
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/soc.c            |    2 +-
+ .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |    2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+index 92dcb72..23f0c88 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+@@ -314,7 +314,7 @@ int sata_init(void)
+ }
+ #endif
+ 
+-#elif defined(CONFIG_LS1043A)
++#elif defined(CONFIG_FSL_LSCH2)
+ #ifdef CONFIG_SCSI_AHCI_PLAT
+ int sata_init(void)
+ {
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+index d1fbde7..7096dac 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+@@ -55,7 +55,7 @@ enum srds {
+       FSL_SRDS_1  = 0,
+       FSL_SRDS_2  = 1,
+ };
+-#elif defined(CONFIG_LS1043A)
++#elif defined(CONFIG_FSL_LSCH2)
+ enum srds_prtcl {
+       NONE = 0,
+       PCIE1,
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0008-armv8-ls1043a-Add-the-OCRAM-initialization.patch b/package/boot/uboot-layerscape/patches/0008-armv8-ls1043a-Add-the-OCRAM-initialization.patch
new file mode 100644 (file)
index 0000000..5715a22
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0008-armv8-ls1043a-Add-the-OCRAM-initialization.patch
@@ -0,0 +1,82 @@
+From b3bbf1aeb0245a0f5565f669dd4b2f5f5be40d8a Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Wed, 16 Mar 2016 08:43:55 +0530
+Subject: [PATCH 08/93] armv8/ls1043a: Add the OCRAM initialization
+
+Clear the content to zero and the ECC error bit of OCRAM1/2.
+
+The OCRAM must be initialized to ZERO by the unit of 8-Byte before
+accessing it, or else it will generate ECC error. And the IBR has
+accessed the OCRAM before this initialization, so the ECC error
+status bit should to be cleared.
+
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/cpu/armv8/start.S |   39 +++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 39 insertions(+)
+
+diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
+index dd583c9..235213f 100644
+--- a/arch/arm/cpu/armv8/start.S
++++ b/arch/arm/cpu/armv8/start.S
+@@ -11,6 +11,9 @@
+ #include <asm/macro.h>
+ #include <asm/armv8/mmu.h>
+ 
++#define DCSR_SYS_DCFG_SBEESR2 0x20140534
++#define DCSR_SYS_DCFG_MBEESR2 0x20140544
++
+ /*************************************************************************
+  *
+  * Startup Code (reset vector)
+@@ -215,10 +218,46 @@ WEAK(lowlevel_init)
+ #endif /* CONFIG_ARMV8_MULTIENTRY */
+ 
+ 2:
++#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
++      bl      fsl_ocram_init
++#endif
+       mov     lr, x29                 /* Restore LR */
+       ret
+ ENDPROC(lowlevel_init)
+ 
++#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
++ENTRY(fsl_ocram_init)
++      mov     x28, lr                 /* Save LR */
++      bl      fsl_clear_ocram
++      bl      fsl_ocram_clear_ecc_err
++      mov     lr, x28                 /* Restore LR */
++      ret
++ENDPROC(fsl_ocram_init)
++
++ENTRY(fsl_clear_ocram)
++/* Clear OCRAM */
++      ldr     x0, =CONFIG_SYS_FSL_OCRAM_BASE
++      ldr     x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
++      mov     x2, #0
++clear_loop:
++      str     x2, [x0]
++      add     x0, x0, #8
++      cmp     x0, x1
++      b.lo    clear_loop
++      ret
++ENDPROC(fsl_clear_ocram)
++
++ENTRY(fsl_ocram_clear_ecc_err)
++      /* OCRAM1/2 ECC status bit */
++      mov     w1, #0x60
++      ldr     x0, =DCSR_SYS_DCFG_SBEESR2
++      str     w1, [x0]
++      ldr     x0, =DCSR_SYS_DCFG_MBEESR2
++      str     w1, [x0]
++      ret
++ENDPROC(fsl_ocram_init)
++#endif
++
+ WEAK(smp_kick_all_cpus)
+       /* Kick secondary cpus up by SGI 0 interrupt */
+       mov     x29, lr                 /* Save LR */
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0009-driver-mtd-spi-Adding-support-for-QSPI-Emulator.patch b/package/boot/uboot-layerscape/patches/0009-driver-mtd-spi-Adding-support-for-QSPI-Emulator.patch
new file mode 100644 (file)
index 0000000..f0b65a1
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0009-driver-mtd-spi-Adding-support-for-QSPI-Emulator.patch
@@ -0,0 +1,29 @@
+From f022d8d9dc505ee917fef6c7109d67cc015a98fa Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Mon, 25 Apr 2016 16:05:36 +0530
+Subject: [PATCH 09/93] driver: mtd: spi: Adding support for QSPI Emulator
+
+Serial number and vendor id are added for The QSPI Emulator
+
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ drivers/mtd/spi/sf_params.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
+index 4f37e33..1424f2a 100644
+--- a/drivers/mtd/spi/sf_params.c
++++ b/drivers/mtd/spi/sf_params.c
+@@ -67,6 +67,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
+       {"S25FL128S_64K",  0x012018, 0x4d01,    64 * 1024,   256, RD_FULL,                   WR_QPP},
+       {"S25FL256S_256K", 0x010219, 0x4d00,   256 * 1024,   128, RD_FULL,                   WR_QPP},
+       {"S25FL256S_64K",  0x010219, 0x4d01,    64 * 1024,   512, RD_FULL,                   WR_QPP},
++      {"S25FS512S",      0x010220, 0x0102,    256 * 1024,  256, RD_FULL,              WR_QPP},
+       {"S25FL512S_256K", 0x010220, 0x4d00,   256 * 1024,   256, RD_FULL,                   WR_QPP},
+       {"S25FL512S_64K",  0x010220, 0x4d01,    64 * 1024,  1024, RD_FULL,                   WR_QPP},
+       {"S25FL512S_512K", 0x010220, 0x4f00,   256 * 1024,   256, RD_FULL,                   WR_QPP},
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0010-driver-mtd-spi-Adding-support-for-QSPI-flash.patch b/package/boot/uboot-layerscape/patches/0010-driver-mtd-spi-Adding-support-for-QSPI-flash.patch
new file mode 100644 (file)
index 0000000..01ace8f
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0010-driver-mtd-spi-Adding-support-for-QSPI-flash.patch
@@ -0,0 +1,45 @@
+From 27d1d5620ae352d230189fbea364198398065ae2 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Mon, 25 Apr 2016 16:06:48 +0530
+Subject: [PATCH 10/93] driver: mtd: spi: Adding support for QSPI flash
+
+Serial number and vendor id are added for QSPI flash
+common on both LS1012AQDS and LS1012ARDB.
+
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ drivers/mtd/spi/sf_params.c |    1 +
+ drivers/mtd/spi/spi_flash.c |    3 ++-
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
+index 1424f2a..1afb8b3 100644
+--- a/drivers/mtd/spi/sf_params.c
++++ b/drivers/mtd/spi/sf_params.c
+@@ -68,6 +68,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
+       {"S25FL256S_256K", 0x010219, 0x4d00,   256 * 1024,   128, RD_FULL,                   WR_QPP},
+       {"S25FL256S_64K",  0x010219, 0x4d01,    64 * 1024,   512, RD_FULL,                   WR_QPP},
+       {"S25FS512S",      0x010220, 0x0102,    256 * 1024,  256, RD_FULL,              WR_QPP},
++      {"S25FS512S_256K", 0x010220, 0x4D00,    128 * 1024,  512, RD_FULL,              WR_QPP},
+       {"S25FL512S_256K", 0x010220, 0x4d00,   256 * 1024,   256, RD_FULL,                   WR_QPP},
+       {"S25FL512S_64K",  0x010220, 0x4d01,    64 * 1024,  1024, RD_FULL,                   WR_QPP},
+       {"S25FL512S_512K", 0x010220, 0x4f00,   256 * 1024,   256, RD_FULL,                   WR_QPP},
+diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
+index 2d23aee..865e929 100644
+--- a/drivers/mtd/spi/spi_flash.c
++++ b/drivers/mtd/spi/spi_flash.c
+@@ -1033,7 +1033,8 @@ int spi_flash_scan(struct spi_flash *flash)
+        * sector that is not overlaid by the parameter sectors.
+        * The uniform sector erase command has no effect on parameter sectors.
+        */
+-      if (jedec == 0x0219 && (ext_jedec & 0xff00) == 0x4d00) {
++      if ((jedec == 0x0219 || (jedec == 0x0220)) &&
++          (ext_jedec & 0xff00) == 0x4d00) {
+               int ret;
+               u8 id[6];
+ 
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0011-armv8-fsl-layerscape-fix-compile-warning-rcw_tmp.patch b/package/boot/uboot-layerscape/patches/0011-armv8-fsl-layerscape-fix-compile-warning-rcw_tmp.patch
new file mode 100644 (file)
index 0000000..6448acb
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0011-armv8-fsl-layerscape-fix-compile-warning-rcw_tmp.patch
@@ -0,0 +1,38 @@
+From 5a5108627b16ab33fb82c16e49ac926ef3a901b8 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Wed, 6 Apr 2016 17:44:22 +0530
+Subject: [PATCH 11/93] armv8: fsl-layerscape: fix compile warning "rcw_tmp"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: In function
+‘get_sys_info’:
+arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:29:6: warning:
+unused variable ‘rcw_tmp’ [-Wunused-variable]
+  u32 rcw_tmp;
+
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c |    5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+index d301fff..078b087 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+@@ -25,7 +25,10 @@ void get_sys_info(struct sys_info *sys_info)
+       struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+       u32 ccr;
+ #endif
+-#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
++#if (defined(CONFIG_FSL_ESDHC) &&\
++      defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
++      defined(CONFIG_SYS_DPAA_FMAN)
++
+       u32 rcw_tmp;
+ #endif
+       struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0012-armv8-LSCH2-early-and-final-mmu-needs-matching-NS-at.patch b/package/boot/uboot-layerscape/patches/0012-armv8-LSCH2-early-and-final-mmu-needs-matching-NS-at.patch
new file mode 100644 (file)
index 0000000..33c3a57
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0012-armv8-LSCH2-early-and-final-mmu-needs-matching-NS-at.patch
@@ -0,0 +1,58 @@
+From edc5b23b8dd04980e0fa48fe79ba811b775cd2c2 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Sat, 23 Apr 2016 12:34:59 +0530
+Subject: [PATCH 12/93] armv8: LSCH2 early and final mmu needs matching NS
+ attribute
+
+When switching between the early and final mmu tables, the stack will
+get corrupted if the Non-Secure attribute is different.  For ls1043a,
+this issue is currently masked because flush_dcache_all is called
+before the switch when CONFIG_SYS_DPAA_FMAN is defined.
+
+Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/include/asm/arch-fsl-layerscape/cpu.h |   12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+index a9dadfa..a7522da 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+@@ -159,9 +159,11 @@ static const struct sys_mmu_table early_mmu_table[] = {
+       { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+         CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+       { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+-        CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
++        CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
++        PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+       { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+-        CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
++        CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
++        PMD_SECT_OUTER_SHARE | PMD_SECT_NS},
+ #endif
+ };
+ 
+@@ -249,7 +251,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
+         CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+       { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+-        CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
++        CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
++        PMD_SECT_OUTER_SHARE | PMD_SECT_NS},
+       { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+         CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+@@ -260,7 +263,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
+         CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+       { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
+-        CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
++        CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL,
++        PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+ #endif
+ };
+ #endif
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0013-armv8-fsl-layerscape-Add-support-of-QorIQ-LS1012A-So.patch b/package/boot/uboot-layerscape/patches/0013-armv8-fsl-layerscape-Add-support-of-QorIQ-LS1012A-So.patch
new file mode 100644 (file)
index 0000000..ea7ab96
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0013-armv8-fsl-layerscape-Add-support-of-QorIQ-LS1012A-So.patch
@@ -0,0 +1,418 @@
+From 53ffd67d944fa23037e7f97e583fae300d4367f7 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Sat, 23 Apr 2016 15:23:52 +0530
+Subject: [PATCH 13/93] armv8: fsl-layerscape: Add support of QorIQ LS1012A
+ SoC
+
+[context adjustment]
+
+The QorIQ LS1012A processor, optimized for battery-backed or
+USB-powered, integrates a single ARM Cortex-A53 core with a hardware
+packet forwarding engine and high-speed interfaces to deliver
+line-rate networking performance.
+
+This patch add support of LS1012A SoC along with
+ - Update platform & DDR clock read logic as per SVR
+ - Define MMDC controller register set.
+ - Update LUT base address for PCIe
+ - Avoid L3 platform cache compilation
+ - Update USB address, errata
+ - SerDes table
+
+Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/Makefile         |    4 ++
+ .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c |   24 +++++--
+ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S       |    2 +
+ arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c |   74 ++++++++++++++++++++
+ arch/arm/cpu/armv8/fsl-layerscape/soc.c            |    6 +-
+ arch/arm/include/asm/arch-fsl-layerscape/config.h  |   32 +++++++++
+ arch/arm/include/asm/arch-fsl-layerscape/cpu.h     |    1 +
+ .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |    1 +
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |    4 ++
+ arch/arm/include/asm/arch-fsl-layerscape/soc.h     |    1 +
+ include/fsl_mmdc.h                                 |   53 ++++++++++++++
+ include/linux/usb/xhci-fsl.h                       |    4 ++
+ 12 files changed, 199 insertions(+), 7 deletions(-)
+ create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
+ create mode 100644 include/fsl_mmdc.h
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+index 27bfeb1..03f73d1 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
++++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+@@ -33,3 +33,7 @@ endif
+ ifneq ($(CONFIG_LS1043A),)
+ obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
+ endif
++
++ifneq ($(CONFIG_LS1012A),)
++obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
++endif
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+index 078b087..63e5bed 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+@@ -33,6 +33,7 @@ void get_sys_info(struct sys_info *sys_info)
+ #endif
+       struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
+       unsigned int cpu;
++      unsigned int svr, ver;
+       const u8 core_cplx_pll[8] = {
+               [0] = 0,        /* CC1 PPL / 1 */
+               [1] = 0,        /* CC1 PPL / 2 */
+@@ -59,12 +60,20 @@ void get_sys_info(struct sys_info *sys_info)
+       sys_info->freq_ddrbus = sysclk;
+ #endif
+ 
+-      sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
+-                      FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+-                      FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+-      sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
+-                      FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
+-                      FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
++      svr = gur_in32(&gur->svr);
++      ver = SVR_SOC_VER(svr);
++      if (ver == SVR_LS1012) {
++              sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
++                              FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
++                              FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
++      } else {
++              sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
++                              FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
++                              FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
++              sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
++                              FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
++                              FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
++      }
+ 
+       for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
+               ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
+@@ -83,6 +92,9 @@ void get_sys_info(struct sys_info *sys_info)
+                       freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+       }
+ 
++      if (ver == SVR_LS1012)
++              sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
++
+ #define HWA_CGA_M1_CLK_SEL    0xe0000000
+ #define HWA_CGA_M1_CLK_SHIFT  29
+ #ifdef CONFIG_SYS_DPAA_FMAN
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+index 5f5bfb9..b40834a 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
++++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+@@ -184,6 +184,7 @@ ENTRY(lowlevel_init)
+       ret
+ ENDPROC(lowlevel_init)
+ 
++#ifdef CONFIG_FSL_LSCH3
+ hnf_pstate_poll:
+       /* x0 has the desired status, return 0 for success, 1 for timeout
+        * clobber x1, x2, x3, x4, x6, x7
+@@ -261,6 +262,7 @@ ENTRY(__asm_flush_l3_cache)
+       mov     lr, x29
+       ret
+ ENDPROC(__asm_flush_l3_cache)
++#endif
+ 
+ #ifdef CONFIG_MP
+       /* Keep literals not used by the secondary boot code outside it */
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
+new file mode 100644
+index 0000000..ff0903c
+--- /dev/null
++++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
+@@ -0,0 +1,74 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/arch/fsl_serdes.h>
++#include <asm/arch/immap_lsch2.h>
++
++struct serdes_config {
++      u32 protocol;
++      u8 lanes[SRDS_MAX_LANES];
++};
++
++static struct serdes_config serdes1_cfg_tbl[] = {
++      {0x2208, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, SATA1} },
++      {0x0008, {NONE, NONE, NONE, SATA1} },
++      {0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} },
++      {0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
++      {0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} },
++      {0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
++      {0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
++      {0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
++      {0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
++      {}
++};
++
++static struct serdes_config *serdes_cfg_tbl[] = {
++      serdes1_cfg_tbl,
++};
++
++enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
++{
++      struct serdes_config *ptr;
++
++      if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
++              return 0;
++
++      ptr = serdes_cfg_tbl[serdes];
++      while (ptr->protocol) {
++              if (ptr->protocol == cfg)
++                      return ptr->lanes[lane];
++              ptr++;
++      }
++
++      return 0;
++}
++
++int is_serdes_prtcl_valid(int serdes, u32 prtcl)
++{
++      int i;
++      struct serdes_config *ptr;
++
++      if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
++              return 0;
++
++      ptr = serdes_cfg_tbl[serdes];
++      while (ptr->protocol) {
++              if (ptr->protocol == prtcl)
++                      break;
++              ptr++;
++      }
++
++      if (!ptr->protocol)
++              return 0;
++
++      for (i = 0; i < SRDS_MAX_LANES; i++) {
++              if (ptr->lanes[i] != NONE)
++                      return 1;
++      }
++
++      return 0;
++}
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+index 23f0c88..ec561a7 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+@@ -12,8 +12,10 @@
+ #include <asm/io.h>
+ #include <asm/global_data.h>
+ #include <asm/arch-fsl-layerscape/config.h>
++#ifdef CONFIG_SYS_FSL_DDR
+ #include <fsl_ddr_sdram.h>
+ #include <fsl_ddr.h>
++#endif
+ #ifdef CONFIG_CHAIN_OF_TRUST
+ #include <fsl_validate.h>
+ #endif
+@@ -46,14 +48,16 @@ static void erratum_a009008(void)
+ static void erratum_a009798(void)
+ {
+ #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+-#if defined(CONFIG_LS1043A)
++#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
+       u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+       u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+       scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
++#if defined(CONFIG_LS1043A)
+       val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+       scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+       val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+       scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
++#endif
+ #elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+       u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+       u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
+index f876c56..6ea4e8e 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
+@@ -14,8 +14,11 @@
+ #else
+ #define CONFIG_SYS_FSL_DDRC_ARM_GEN3  /* Enable Freescale ARM DDR3 driver */
+ #endif
++
++#ifndef CONFIG_LS1012A
+ #define CONFIG_SYS_FSL_DDR            /* Freescale DDR driver */
+ #define CONFIG_SYS_FSL_DDR_VER                FSL_DDR_VER_5_0
++#endif
+ 
+ /*
+  * Reserve secure memory
+@@ -205,6 +208,35 @@
+ #define CONFIG_SYS_FSL_ERRATUM_A008997
+ #define CONFIG_SYS_FSL_ERRATUM_A009007
+ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC         1
++#elif defined(CONFIG_LS1012A)
++#define CONFIG_MAX_CPUS                         1
++#define CONFIG_SYS_CACHELINE_SIZE             64
++#define CONFIG_NUM_DDR_CONTROLLERS            1
++#define CONFIG_SYS_CCSRBAR_DEFAULT            0x01000000
++#define CONFIG_SYS_FSL_SEC_COMPAT             5
++#undef        CONFIG_SYS_FSL_DDRC_ARM_GEN3
++
++#define CONFIG_SYS_FSL_OCRAM_BASE             0x10000000 /* initial RAM */
++#define CONFIG_SYS_FSL_OCRAM_SIZE             0x200000 /* 2 MiB */
++
++#define GICD_BASE             0x01401000
++#define GICC_BASE             0x01402000
++
++#define CONFIG_SYS_FSL_CCSR_GUR_BE
++#define CONFIG_SYS_FSL_CCSR_SCFG_BE
++#define CONFIG_SYS_FSL_ESDHC_BE
++#define CONFIG_SYS_FSL_WDOG_BE
++#define CONFIG_SYS_FSL_DSPI_BE
++#define CONFIG_SYS_FSL_QSPI_BE
++#define CONFIG_SYS_FSL_PEX_LUT_BE
++
++#define SRDS_MAX_LANES                4
++#define CONFIG_SYS_FSL_SRDS_1
++#define CONFIG_SYS_FSL_PCIE_COMPAT            "fsl,qoriq-pcie-v2.4"
++#define CONFIG_SYS_FSL_SEC_BE
++
++#define CONFIG_SYS_FSL_ERRATUM_A009798
++
+ #else
+ #error SoC not defined
+ #endif
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+index a7522da..e4ff990 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+@@ -14,6 +14,7 @@ static struct cpu_type cpu_type_list[] = {
+       CPU_TYPE_ENTRY(LS1043, LS1043, 4),
+       CPU_TYPE_ENTRY(LS1023, LS1023, 2),
+       CPU_TYPE_ENTRY(LS2040, LS2040, 4),
++      CPU_TYPE_ENTRY(LS1012, LS1012, 1),
+ };
+ 
+ #ifndef CONFIG_SYS_DCACHE_OFF
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+index 7096dac..4a3f4f3 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+@@ -134,6 +134,7 @@ enum srds_prtcl {
+       SGMII_2500_FM2_DTSEC6,
+       SGMII_2500_FM2_DTSEC9,
+       SGMII_2500_FM2_DTSEC10,
++      TX_CLK,
+       SERDES_PRCTL_COUNT
+ };
+ 
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index 2852f9c..5b026f8 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -62,7 +62,11 @@
+ #define CONFIG_SYS_PCIE2_PHYS_ADDR            0x4800000000ULL
+ #define CONFIG_SYS_PCIE3_PHYS_ADDR            0x5000000000ULL
+ /* LUT registers */
++#ifdef CONFIG_LS1012A
++#define PCIE_LUT_BASE                         0xC0000
++#else
+ #define PCIE_LUT_BASE                         0x10000
++#endif
+ #define PCIE_LUT_LCTRL0                               0x7F8
+ #define PCIE_LUT_DBG                          0x7FC
+ 
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+index 56989e1..0822b49 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+@@ -41,6 +41,7 @@ struct cpu_type {
+       { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
+ 
+ #define SVR_WO_E              0xFFFFFE
++#define SVR_LS1012            0x870400
+ #define SVR_LS1043            0x879200
+ #define SVR_LS1023            0x879208
+ #define SVR_LS2045            0x870120
+diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
+new file mode 100644
+index 0000000..3df822e
+--- /dev/null
++++ b/include/fsl_mmdc.h
+@@ -0,0 +1,53 @@
++/*
++ * Copyright 2015 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++#ifndef FSL_MMDC_H
++#define FSL_MMDC_H
++
++/* MMDC Registers */
++struct mmdc_p_regs {
++      u32 mdctl;
++      u32 mdpdc;
++      u32 mdotc;
++      u32 mdcfg0;
++      u32 mdcfg1;
++      u32 mdcfg2;
++      u32 mdmisc;
++      u32 mdscr;
++      u32 mdref;
++      u32 res1[2];
++      u32 mdrwd;
++      u32 mdor;
++      u32 mdmrr;
++      u32 mdcfg3lp;
++      u32 mdmr4;
++      u32 mdasp;
++      u32 res3[239];
++      u32 maarcr;
++      u32 mapsr;
++      u32 res4[254];
++      u32 mpzqhwctrl;
++      u32 res5[2];
++      u32 mpwldectrl0;
++      u32 mpwldectrl1;
++      u32 res6;
++      u32 mpodtctrl;
++      u32 mprddqby0dl;
++      u32 mprddqby1dl;
++      u32 mprddqby2dl;
++      u32 mprddqby3dl;
++      u32 res7[4];
++      u32 mpdgctrl0;
++      u32 mpdgctrl1;
++      u32 res8;
++      u32 mprddlctl;
++      u32 res9;
++      u32 mpwrdlctl;
++      u32 res10[25];
++      u32 mpmur0;
++};
++
++#endif /* FSL_MMDC_H */
+diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
+index 4966608..72a5d5b 100644
+--- a/include/linux/usb/xhci-fsl.h
++++ b/include/linux/usb/xhci-fsl.h
+@@ -66,6 +66,10 @@ struct fsl_xhci {
+ #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
++#elif defined(CONFIG_LS1012A)
++#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
++#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
++#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+ #endif
+ 
+ #define FSL_USB_XHCI_ADDR     {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0014-armv8-ls1012a-Add-support-of-ls1012aqds-board.patch b/package/boot/uboot-layerscape/patches/0014-armv8-ls1012a-Add-support-of-ls1012aqds-board.patch
new file mode 100644 (file)
index 0000000..4a9ebfa
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0014-armv8-ls1012a-Add-support-of-ls1012aqds-board.patch
@@ -0,0 +1,1237 @@
+From faf0aac702a2253471f98687ed40138e514e38ab Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Mon, 25 Apr 2016 14:36:16 +0530
+Subject: [PATCH 14/93] armv8: ls1012a: Add support of ls1012aqds board
+
+QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012AQDS board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/Kconfig                              |   10 ++
+ arch/arm/dts/Makefile                         |    3 +-
+ arch/arm/dts/fsl-ls1012a-qds.dts              |   14 ++
+ arch/arm/dts/fsl-ls1012a-qds.dtsi             |  123 +++++++++++++
+ arch/arm/dts/fsl-ls1012a.dtsi                 |  119 ++++++++++++
+ board/freescale/ls1012aqds/Kconfig            |   15 ++
+ board/freescale/ls1012aqds/MAINTAINERS        |    6 +
+ board/freescale/ls1012aqds/Makefile           |    7 +
+ board/freescale/ls1012aqds/README             |   94 ++++++++++
+ board/freescale/ls1012aqds/ls1012aqds.c       |  199 ++++++++++++++++++++
+ board/freescale/ls1012aqds/ls1012aqds_qixis.h |   35 ++++
+ configs/ls1012aqds_qspi_defconfig             |   10 ++
+ include/configs/ls1012a_common.h              |  239 +++++++++++++++++++++++++
+ include/configs/ls1012aqds.h                  |  133 ++++++++++++++
+ include/fsl_mmdc.h                            |   57 +++++-
+ 15 files changed, 1055 insertions(+), 9 deletions(-)
+ create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dts
+ create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dtsi
+ create mode 100644 arch/arm/dts/fsl-ls1012a.dtsi
+ create mode 100644 board/freescale/ls1012aqds/Kconfig
+ create mode 100644 board/freescale/ls1012aqds/MAINTAINERS
+ create mode 100644 board/freescale/ls1012aqds/Makefile
+ create mode 100644 board/freescale/ls1012aqds/README
+ create mode 100644 board/freescale/ls1012aqds/ls1012aqds.c
+ create mode 100644 board/freescale/ls1012aqds/ls1012aqds_qixis.h
+ create mode 100644 configs/ls1012aqds_qspi_defconfig
+ create mode 100644 include/configs/ls1012a_common.h
+ create mode 100644 include/configs/ls1012aqds.h
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 9bd6cf1..f5033db 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -647,6 +647,15 @@ config TARGET_HIKEY
+         Support for HiKey 96boards platform. It features a HI6220
+         SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
+ 
++config TARGET_LS1012AQDS
++      bool "Support ls1012aqds"
++      select ARM64
++      help
++        Support for Freescale LS1012AQDS platform.
++        The LS1012A Development System (QDS) is a high-performance
++        development platform that supports the QorIQ LS1012A
++        Layerscape Architecture processor.
++
+ config TARGET_LS1021AQDS
+       bool "Support ls1021aqds"
+       select CPU_V7
+@@ -792,6 +801,7 @@ source "board/freescale/ls1021aqds/Kconfig"
+ source "board/freescale/ls1043aqds/Kconfig"
+ source "board/freescale/ls1021atwr/Kconfig"
+ source "board/freescale/ls1043ardb/Kconfig"
++source "board/freescale/ls1012aqds/Kconfig"
+ source "board/freescale/mx23evk/Kconfig"
+ source "board/freescale/mx25pdk/Kconfig"
+ source "board/freescale/mx28evk/Kconfig"
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index c1c81e4..ed5eb38 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -94,7 +94,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
+       fsl-ls2080a-rdb.dtb
+ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
+       fsl-ls1043a-qds-lpuart.dtb \
+-      fsl-ls1043a-rdb.dtb
++      fsl-ls1043a-rdb.dtb \
++      fsl-ls1012a-qds.dtb
+ 
+ dtb-$(CONFIG_MACH_SUN4I) += \
+       sun4i-a10-a1000.dtb \
+diff --git a/arch/arm/dts/fsl-ls1012a-qds.dts b/arch/arm/dts/fsl-ls1012a-qds.dts
+new file mode 100644
+index 0000000..ef6de34
+--- /dev/null
++++ b/arch/arm/dts/fsl-ls1012a-qds.dts
+@@ -0,0 +1,14 @@
++/*
++ * Copyright (C) 2016 Freescale Semiconductor
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++/dts-v1/;
++#include "fsl-ls1012a-qds.dtsi"
++
++/ {
++       chosen {
++               stdout-path = &duart0;
++       };
++};
+diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi
+new file mode 100644
+index 0000000..a32a84a
+--- /dev/null
++++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
+@@ -0,0 +1,123 @@
++/*
++ * Copyright (C) 2016 Freescale Semiconductor
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++/include/ "fsl-ls1012a.dtsi"
++
++/ {
++      model = "LS1012A QDS Board";
++      aliases {
++              spi0 = &qspi;
++              spi1 = &dspi0;
++      };
++};
++
++&dspi0 {
++      bus-num = <0>;
++      status = "okay";
++
++      dflash0: n25q128a {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "spi-flash";
++              reg = <0>;
++              spi-max-frequency = <1000000>; /* input clock */
++      };
++
++      dflash1: sst25wf040b {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "spi-flash";
++              spi-max-frequency = <3500000>;
++              reg = <1>;
++      };
++
++      dflash2: en25s64 {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "spi-flash";
++              spi-max-frequency = <3500000>;
++              reg = <2>;
++      };
++};
++
++&qspi {
++      bus-num = <0>;
++      status = "okay";
++
++      qflash0: s25fl128s@0 {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "spi-flash";
++              spi-max-frequency = <20000000>;
++              reg = <0>;
++      };
++};
++
++&i2c0 {
++      status = "okay";
++      pca9547@77 {
++              compatible = "philips,pca9547";
++              reg = <0x77>;
++              #address-cells = <1>;
++              #size-cells = <0>;
++
++              i2c@0 {
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x0>;
++
++                      rtc@68 {
++                              compatible = "dallas,ds3232";
++                              reg = <0x68>;
++                              /* IRQ10_B */
++                              interrupts = <0 150 0x4>;
++                      };
++              };
++
++              i2c@2 {
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x2>;
++
++                      ina220@40 {
++                              compatible = "ti,ina220";
++                              reg = <0x40>;
++                              shunt-resistor = <1000>;
++                      };
++
++                      ina220@41 {
++                              compatible = "ti,ina220";
++                              reg = <0x41>;
++                              shunt-resistor = <1000>;
++                      };
++              };
++
++              i2c@3 {
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x3>;
++
++                      eeprom@56 {
++                              compatible = "at24,24c512";
++                              reg = <0x56>;
++                      };
++
++                      eeprom@57 {
++                              compatible = "at24,24c512";
++                              reg = <0x57>;
++                      };
++
++                      adt7461a@4c {
++                              compatible = "adt7461a";
++                              reg = <0x4c>;
++                      };
++              };
++      };
++};
++
++&duart0 {
++      status = "okay";
++};
+diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
+new file mode 100644
+index 0000000..87a287a
+--- /dev/null
++++ b/arch/arm/dts/fsl-ls1012a.dtsi
+@@ -0,0 +1,119 @@
++/*
++ * Copyright (C) 2016 Freescale Semiconductor
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++/include/ "skeleton64.dtsi"
++
++/ {
++      compatible = "fsl,ls1012a";
++      interrupt-parent = <&gic>;
++      cpus {
++              #address-cells = <2>;
++              #size-cells = <0>;
++
++              cpu0: cpu@0 {
++                      device_type = "cpu";
++                      compatible = "arm,cortex-a53";
++                      reg = <0x0 0x0>;
++                      clocks = <&clockgen 1 0>;
++              };
++
++      };
++
++      sysclk: sysclk {
++              compatible = "fixed-clock";
++              #clock-cells = <0>;
++              clock-frequency = <100000000>;
++              clock-output-names = "sysclk";
++      };
++
++      gic: interrupt-controller@1400000 {
++              compatible = "arm,gic-400";
++              #interrupt-cells = <3>;
++              interrupt-controller;
++              reg = <0x0 0x1401000 0 0x1000>, /* GICD */
++                    <0x0 0x1402000 0 0x2000>, /* GICC */
++                    <0x0 0x1404000 0 0x2000>, /* GICH */
++                    <0x0 0x1406000 0 0x2000>; /* GICV */
++              interrupts = <1 9 0xf08>;
++      };
++
++      soc {
++              compatible = "simple-bus";
++              #address-cells = <2>;
++              #size-cells = <2>;
++              ranges;
++
++              clockgen: clocking@1ee1000 {
++                      compatible = "fsl,ls1012a-clockgen";
++                      reg = <0x0 0x1ee1000 0x0 0x1000>;
++                      #clock-cells = <2>;
++                      clocks = <&sysclk>;
++              };
++
++              dspi0: dspi@2100000 {
++                      compatible = "fsl,vf610-dspi";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x0 0x2100000 0x0 0x10000>;
++                      interrupts = <0 64 0x4>;
++                      clock-names = "dspi";
++                      clocks = <&clockgen 4 0>;
++                      num-cs = <6>;
++                      big-endian;
++                      status = "disabled";
++              };
++
++
++              i2c0: i2c@2180000 {
++                      compatible = "fsl,vf610-i2c";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x0 0x2180000 0x0 0x10000>;
++                      interrupts = <0 56 0x4>;
++                      clock-names = "i2c";
++                      clocks = <&clockgen 4 0>;
++                      status = "disabled";
++              };
++
++              i2c1: i2c@2190000 {
++                      compatible = "fsl,vf610-i2c";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x0 0x2190000 0x0 0x10000>;
++                      interrupts = <0 57 0x4>;
++                      clock-names = "i2c";
++                      clocks = <&clockgen 4 0>;
++                      status = "disabled";
++              };
++
++              duart0: serial@21c0500 {
++                      compatible = "fsl,ns16550", "ns16550a";
++                      reg = <0x00 0x21c0500 0x0 0x100>;
++                      interrupts = <0 54 0x4>;
++                      clocks = <&clockgen 4 0>;
++              };
++
++              duart1: serial@21c0600 {
++                      compatible = "fsl,ns16550", "ns16550a";
++                      reg = <0x00 0x21c0600 0x0 0x100>;
++                      interrupts = <0 54 0x4>;
++                      clocks = <&clockgen 4 0>;
++              };
++
++              qspi: quadspi@1550000 {
++                      compatible = "fsl,vf610-qspi";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x0 0x1550000 0x0 0x10000>,
++                              <0x0 0x40000000 0x0 0x4000000>;
++                      reg-names = "QuadSPI", "QuadSPI-memory";
++                      num-cs = <2>;
++                      big-endian;
++                      status = "disabled";
++              };
++
++      };
++};
+diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
+new file mode 100644
+index 0000000..1257ec8
+--- /dev/null
++++ b/board/freescale/ls1012aqds/Kconfig
+@@ -0,0 +1,15 @@
++if TARGET_LS1012AQDS
++
++config SYS_BOARD
++      default "ls1012aqds"
++
++config SYS_VENDOR
++      default "freescale"
++
++config SYS_SOC
++      default "fsl-layerscape"
++
++config SYS_CONFIG_NAME
++      default "ls1012aqds"
++
++endif
+diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS
+new file mode 100644
+index 0000000..3c01df6
+--- /dev/null
++++ b/board/freescale/ls1012aqds/MAINTAINERS
+@@ -0,0 +1,6 @@
++LS1012AQDS BOARD
++M:
++S:    Maintained
++F:    board/freescale/ls1012aqds/
++F:    include/configs/ls1012aqds.h
++F:    configs/ls1012aqds_defconfig
+diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
+new file mode 100644
+index 0000000..0b813f9
+--- /dev/null
++++ b/board/freescale/ls1012aqds/Makefile
+@@ -0,0 +1,7 @@
++#
++# Copyright 2016 Freescale Semiconductor, Inc.
++#
++# SPDX-License-Identifier:      GPL-2.0+
++#
++
++obj-y += ls1012aqds.o
+diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README
+new file mode 100644
+index 0000000..e94a267
+--- /dev/null
++++ b/board/freescale/ls1012aqds/README
+@@ -0,0 +1,94 @@
++Overview
++--------
++The LS1012AQDS power supplies (PS) provide all the voltages necessary
++for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
++and other onboard peripherals.
++
++LS1012A SoC Overview
++--------------------
++The LS1012A features an advanced 64-bit ARM v8 Cortex-
++A53 processor, with 32 KB of parity protected L1-I cache,
++32 KB of ECC protected L1-D cache, as well as 256 KB of
++ECC protected L2 cache.
++
++The LS1012A SoC includes the following function and features:
++ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
++ - ARM v8 cryptography extensions
++ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
++    16-/8-bit operation (no ECC support)
++ - ARM core-link CCI-400 cache coherent interconnect
++ - Packet Forwarding Engine (PFE)
++ - Cryptography acceleration (SEC)
++ - Ethernet interfaces supported by PFE:
++ - One Configurable x3 SerDes:
++    Two Serdes PLLs supported for usage by any SerDes data lane
++    Support for up to 6 GBaud operation
++ - High-speed peripheral interfaces:
++     - One PCI Express Gen2 controller, supporting x1 operation
++     - One serial ATA (SATA Gen 3.0) controller
++     - One USB 3.0/2.0 controller with integrated PHY
++     - One USB 2.0 controller with ULPI interface. .
++ - Additional peripheral interfaces:
++    - One quad serial peripheral interface (QuadSPI) controller
++    - One serial peripheral interface (SPI) controller
++    - Two enhanced secure digital host controllers
++    - Two I2C controllers
++    - One 16550 compliant DUART (two UART interfaces)
++    - Two general purpose IOs (GPIO)
++    - Two FlexTimers
++    - Five synchronous audio interfaces (SAI)
++    - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
++    - Single-source clocking solution enabling generation of core, platform,
++    DDR, SerDes, and USB clocks from a single external crystal and internal
++    crystaloscillator
++    - Thermal monitor unit (TMU) with +/- 3C accuracy
++    - Two WatchDog timers
++    - ARM generic timer
++ - QorIQ platform's trust architecture 2.1
++
++ LS1012AQDS board Overview
++ -----------------------
++ - SERDES Connections, 4 lanes supporting:
++      - PCI Express - 3.0
++      - SGMII, SGMII 2.5
++      - SATA 3.0
++ - DDR Controller
++     - 6-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
++ - QSPI Controller
++     - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
++       signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
++       emulator
++ - USB 3.0
++    - One USB 3.0 controller with integrated PHY
++    - One high-speed USB 3.0 port
++ - USB 2.0
++    - One USB 2.0 controller with ULPI interface
++ - Two enhanced secure digital host controllers:
++    - SDHC1 controller can be connected to onboard SDHC connector
++    - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
++ - 2 I2C controllers
++ - One SATA onboard connectors
++ - UART
++ - 5 SAI
++    - One SAI port with audio codec SGTL5000:
++      • Provides MIC bias
++      • Provides headphone and line output
++    - One SAI port terminated at 2x6 header
++    - Three SAI Tx/Rx ports terminated at 2x3 headers
++ - ARM JTAG support
++
++Booting Options
++---------------
++a) QSPI Flash Emu Boot
++b) QSPI Flash 1
++c) QSPI Flash 2
++
++QSPI flash map
++--------------
++Images                | Size  |QSPI Flash Address
++------------------------------------------
++RCW + PBI     | 1MB   | 0x4000_0000
++U-boot                | 1MB   | 0x4010_0000
++U-boot Env    | 1MB   | 0x4020_0000
++PPA FIT image | 2MB   | 0x4050_0000
++Linux ITB     | ~53MB | 0x40A0_0000
+diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
+new file mode 100644
+index 0000000..ffcd0d8
+--- /dev/null
++++ b/board/freescale/ls1012aqds/ls1012aqds.c
+@@ -0,0 +1,199 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++#include <common.h>
++#include <i2c.h>
++#include <fdt_support.h>
++#include <asm/io.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/fsl_serdes.h>
++#include <asm/arch/fdt.h>
++#include <asm/arch/soc.h>
++#include <ahci.h>
++#include <hwconfig.h>
++#include <mmc.h>
++#include <scsi.h>
++#include <fm_eth.h>
++#include <fsl_csu.h>
++#include <fsl_esdhc.h>
++#include <fsl_mmdc.h>
++#include <spl.h>
++#include <netdev.h>
++
++#include "../common/qixis.h"
++#include "ls1012aqds_qixis.h"
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int checkboard(void)
++{
++      puts("Board: LS1012AQDS\n");
++
++      return 0;
++}
++
++void mmdc_init(void)
++{
++      struct mmdc_p_regs *mmdc =
++              (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
++
++      /* Set MMDC_MDSCR[CON_REQ] */
++      out_be32(&mmdc->mdscr, 0x00008000);
++
++      /* configure timing parms */
++      out_be32(&mmdc->mdotc, 0x12554000);
++      out_be32(&mmdc->mdcfg0, 0xbabf7954);
++      out_be32(&mmdc->mdcfg1, 0xff328f64);
++      out_be32(&mmdc->mdcfg2, 0x01ff00db);
++
++      /* other parms  */
++      out_be32(&mmdc->mdmisc,    0x00000680);
++      out_be32(&mmdc->mpmur0,    0x00000800);
++      out_be32(&mmdc->mdrwd,     0x00002000);
++      out_be32(&mmdc->mpodtctrl, 0x0000022a);
++
++      /* out of reset delays */
++      out_be32(&mmdc->mdor, 0x00bf1023);
++
++      /* physical parms */
++      out_be32(&mmdc->mdctl, 0x05180000);
++      out_be32(&mmdc->mdasp, 0x0000007f);
++
++      /* Enable MMDC */
++      out_be32(&mmdc->mdctl, 0x85180000);
++
++      /* dram init sequence: update MRs */
++      out_be32(&mmdc->mdscr, 0x00088032);
++      out_be32(&mmdc->mdscr, 0x00008033);
++      out_be32(&mmdc->mdscr, 0x00048031);
++      out_be32(&mmdc->mdscr, 0x19308030);
++
++      /* dram init sequence: ZQCL */
++      out_be32(&mmdc->mdscr,      0x04008040);
++      out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
++
++      mdelay(100);
++
++      /* Calibrations now: wr lvl */
++      out_be32(&mmdc->mdscr,   0x00848031);
++      out_be32(&mmdc->mdscr,   0x00008200);
++      out_be32(&mmdc->mpwlgcr, 0x00000001);
++
++      mdelay(100);
++
++      out_be32(&mmdc->mdscr, 0x00048031);
++      out_be32(&mmdc->mdscr, 0x00008000);
++
++      /*    manual_refresh */
++      out_be32(&mmdc->mdscr, 0x00008020);
++
++      mdelay(100);
++
++      /* Calibrations now: Read DQS gating calibration */
++      out_be32(&mmdc->mdscr,     0x04008050);
++      out_be32(&mmdc->mdscr,     0x00048033);
++      out_be32(&mmdc->mppdcmpr2, 0x00000001);
++      out_be32(&mmdc->mprddlctl, 0x40404040);
++      out_be32(&mmdc->mpdgctrl0, 0x10000000);
++
++      mdelay(100);
++
++      out_be32(&mmdc->mdscr, 0x00008033);
++
++      /*   manual_refresh */
++      out_be32(&mmdc->mdscr, 0x00008020);
++
++      mdelay(100);
++
++      /* Calibrations now: Read calibration */
++      out_be32(&mmdc->mdscr,       0x04008050);
++      out_be32(&mmdc->mdscr,       0x00048033);
++      out_be32(&mmdc->mppdcmpr2,   0x00000001);
++      out_be32(&mmdc->mprddlhwctl, 0x00000010);
++
++      mdelay(400);
++
++      out_be32(&mmdc->mdscr, 0x00008033);
++
++      /* manual_refresh */
++      out_be32(&mmdc->mdscr, 0x00008020);
++
++      mdelay(100);
++
++      /* PD, SR */
++      out_be32(&mmdc->mdpdc, 0x00030035);
++      out_be32(&mmdc->mapsr, 0x00001067);
++
++      /* refresh scheme */
++      out_be32(&mmdc->mdref, 0x103e8000);
++
++      mdelay(400);
++
++      /* disable CON_REQ */
++      out_be32(&mmdc->mdscr, 0x0);
++
++      mdelay(50);
++}
++
++int dram_init(void)
++{
++      mmdc_init();
++
++      gd->ram_size = 0x40000000;
++
++      return 0;
++}
++
++int board_early_init_f(void)
++{
++      fsl_lsch2_early_init_f();
++
++      return 0;
++}
++
++int board_init(void)
++{
++      struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
++                                 CONFIG_SYS_CCI400_ADDR;
++
++      /* Set CCI-400 control override register to enable barrier
++       * transaction */
++      out_le32(&cci->ctrl_ord,
++               CCI400_CTRLORD_EN_BARRIER);
++
++#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
++      enable_layerscape_ns_access();
++#endif
++
++#ifdef CONFIG_ENV_IS_NOWHERE
++      gd->env_addr = (ulong)&default_environment[0];
++#endif
++      return 0;
++}
++
++int board_eth_init(bd_t *bis)
++{
++      return pci_eth_init(bis);
++}
++
++#ifdef CONFIG_OF_BOARD_SETUP
++int ft_board_setup(void *blob, bd_t *bd)
++{
++      u64 base[CONFIG_NR_DRAM_BANKS];
++      u64 size[CONFIG_NR_DRAM_BANKS];
++
++      /* fixup DT for the two DDR banks */
++      base[0] = gd->bd->bi_dram[0].start;
++      size[0] = gd->bd->bi_dram[0].size;
++      base[1] = gd->bd->bi_dram[1].start;
++      size[1] = gd->bd->bi_dram[1].size;
++
++      fdt_fixup_memory_banks(blob, base, size, 2);
++      ft_cpu_setup(blob, bd);
++
++      return 0;
++}
++#endif
+diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
+new file mode 100644
+index 0000000..584f604
+--- /dev/null
++++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
+@@ -0,0 +1,35 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++#ifndef __LS1043AQDS_QIXIS_H__
++#define __LS1043AQDS_QIXIS_H__
++
++/* Definitions of QIXIS Registers for LS1043AQDS */
++
++/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
++#define BRDCFG4_EMISEL_MASK           0xe0
++#define BRDCFG4_EMISEL_SHIFT          5
++
++/* SYSCLK */
++#define QIXIS_SYSCLK_66                       0x0
++#define QIXIS_SYSCLK_83                       0x1
++#define QIXIS_SYSCLK_100              0x2
++#define QIXIS_SYSCLK_125              0x3
++#define QIXIS_SYSCLK_133              0x4
++
++/* DDRCLK */
++#define QIXIS_DDRCLK_66                       0x0
++#define QIXIS_DDRCLK_100              0x1
++#define QIXIS_DDRCLK_125              0x2
++#define QIXIS_DDRCLK_133              0x3
++
++/* BRDCFG2 - SD clock*/
++#define QIXIS_SDCLK1_100              0x0
++#define QIXIS_SDCLK1_125              0x1
++#define QIXIS_SDCLK1_165              0x2
++#define QIXIS_SDCLK1_100_SP           0x3
++
++#endif
+diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
+new file mode 100644
+index 0000000..ef2c0ad
+--- /dev/null
++++ b/configs/ls1012aqds_qspi_defconfig
+@@ -0,0 +1,10 @@
++CONFIG_ARM=y
++CONFIG_TARGET_LS1012AQDS=y
++CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
++# CONFIG_CMD_IMLS is not set
++CONFIG_SYS_NS16550=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
++CONFIG_OF_CONTROL=y
++CONFIG_DM=y
++CONFIG_SPI_FLASH=y
++CONFIG_DM_SPI=y
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+new file mode 100644
+index 0000000..9ed04f9
+--- /dev/null
++++ b/include/configs/ls1012a_common.h
+@@ -0,0 +1,239 @@
++/*
++ * Copyright (C) 2015 Freescale Semiconductor
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++#ifndef __LS1012A_COMMON_H
++#define __LS1012A_COMMON_H
++
++#define CONFIG_FSL_LAYERSCAPE
++#define CONFIG_FSL_LSCH2
++#define CONFIG_LS1012A
++#define CONFIG_GICV2
++
++#define       CONFIG_SYS_HAS_SERDES
++
++#include <asm/arch/config.h>
++#define CONFIG_SYS_NO_FLASH
++
++#define CONFIG_SUPPORT_RAW_INITRD
++
++#define CONFIG_DISPLAY_BOARDINFO_LATE
++
++#define CONFIG_SYS_TEXT_BASE          0x40100000
++
++#define CONFIG_SYS_FSL_CLK
++#define CONFIG_SYS_CLK_FREQ           100000000
++#define CONFIG_DDR_CLK_FREQ           125000000
++
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_BOARD_EARLY_INIT_F     1
++
++#define CONFIG_SYS_INIT_SP_ADDR               (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
++#define CONFIG_SYS_LOAD_ADDR  (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
++
++#define CONFIG_SYS_DDR_SDRAM_BASE     0x80000000
++#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY     0
++#define CONFIG_SYS_SDRAM_BASE         CONFIG_SYS_DDR_SDRAM_BASE
++
++/* Generic Timer Definitions */
++#define COUNTER_FREQUENCY             25000000        /* 12MHz */
++
++/* CSU */
++#define CONFIG_LAYERSCAPE_NS_ACCESS
++
++/* Size of malloc() pool */
++#define CONFIG_SYS_MALLOC_LEN         (CONFIG_ENV_SIZE + 128 * 1024)
++
++/*SPI device */
++#ifdef CONFIG_QSPI_BOOT
++#define CONFIG_SYS_QE_FW_IN_SPIFLASH
++#define CONFIG_SYS_FMAN_FW_ADDR               0x400d0000
++#define CONFIG_ENV_SPI_BUS            0
++#define CONFIG_ENV_SPI_CS             0
++#define CONFIG_ENV_SPI_MAX_HZ         1000000
++#define CONFIG_ENV_SPI_MODE           0x03
++#define CONFIG_CMD_SF
++#define CONFIG_SPI_FLASH_SPANSION
++#define CONFIG_SPI_FLASH_ATMEL
++#define CONFIG_FSL_SPI_INTERFACE
++#define CONFIG_SF_DATAFLASH
++
++#define CONFIG_FSL_QSPI
++#define QSPI0_AMBA_BASE               0x40000000
++#define CONFIG_SPI_FLASH_SPANSION
++#define CONFIG_DM_SPI_FLASH
++#define CONFIG_SPI_FLASH_BAR
++
++#define FSL_QSPI_FLASH_SIZE           (1 << 24)
++#define FSL_QSPI_FLASH_NUM            2
++
++/*
++ * Environment
++ */
++#define CONFIG_ENV_OVERWRITE
++
++#define CONFIG_ENV_IS_IN_SPI_FLASH
++#define CONFIG_ENV_SIZE                       0x40000          /* 256KB */
++#define CONFIG_ENV_OFFSET             0x200000        /* 2MB */
++#define CONFIG_ENV_SECT_SIZE          0x40000
++#endif
++
++/* I2C */
++#if !defined(CONFIG_EMU)
++#define CONFIG_CMD_I2C
++#define CONFIG_SYS_I2C
++#define CONFIG_SYS_I2C_MXC
++#define CONFIG_SYS_I2C_MXC_I2C1               /* enable I2C bus 1 */
++#define CONFIG_SYS_I2C_MXC_I2C2               /* enable I2C bus 2 */
++#endif /* CONFIG_EMU */
++
++/*  MMC  */
++#if  !defined(CONFIG_EMU)
++#define CONFIG_MMC
++#ifdef CONFIG_MMC
++#define CONFIG_CMD_MMC
++#define CONFIG_FSL_ESDHC
++#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
++#define CONFIG_GENERIC_MMC
++#define CONFIG_CMD_FAT
++#define CONFIG_DOS_PARTITION
++#endif
++#endif /* CONFIG_EMU */
++
++/* SATA */
++#if  !defined(CONFIG_EMU)
++#define CONFIG_LIBATA
++#define CONFIG_SCSI_AHCI
++#define CONFIG_SCSI_AHCI_PLAT
++#define CONFIG_CMD_SCSI
++#define CONFIG_CMD_FAT
++#define CONFIG_CMD_EXT2
++#define CONFIG_DOS_PARTITION
++#define CONFIG_BOARD_LATE_INIT
++
++#define CONFIG_SYS_SATA                               AHCI_BASE_ADDR
++
++#define CONFIG_SYS_SCSI_MAX_SCSI_ID           1
++#define CONFIG_SYS_SCSI_MAX_LUN                       1
++#define CONFIG_SYS_SCSI_MAX_DEVICE            (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
++                                              CONFIG_SYS_SCSI_MAX_LUN)
++
++#define CONFIG_PCI            /* Enable PCI/PCIE */
++#define CONFIG_PCIE1          /* PCIE controller 1 */
++#define CONFIG_PCIE_LAYERSCAPE        /* Use common FSL Layerscape PCIe code */
++#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
++
++#define CONFIG_SYS_PCI_64BIT
++
++#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
++#define CONFIG_SYS_PCIE_CFG0_SIZE     0x00001000      /* 4k */
++#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
++#define CONFIG_SYS_PCIE_CFG1_SIZE     0x00001000      /* 4k */
++
++#define CONFIG_SYS_PCIE_IO_BUS                0x00000000
++#define CONFIG_SYS_PCIE_IO_PHYS_OFF   0x00010000
++#define CONFIG_SYS_PCIE_IO_SIZE               0x00010000      /* 64k */
++
++#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
++#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
++#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
++
++#define CONFIG_NET_MULTI
++#define CONFIG_PCI_PNP
++#define CONFIG_E1000
++#define CONFIG_PCI_SCAN_SHOW
++#define CONFIG_CMD_PCI
++#endif
++
++#define CONFIG_CONS_INDEX       1
++#define CONFIG_SYS_NS16550_SERIAL
++#define CONFIG_SYS_NS16550_REG_SIZE     1
++#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
++
++#ifdef CONFIG_EMU
++#define CONFIG_BAUDRATE                       3000
++#else
++#define CONFIG_BAUDRATE                       115200
++#endif
++#define CONFIG_SYS_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200 }
++
++/* Command line configuration */
++#define CONFIG_CMD_CACHE
++#define CONFIG_CMD_DHCP
++#define CONFIG_CMD_ENV
++#define CONFIG_CMD_GREPENV
++#define CONFIG_CMD_MII
++#define CONFIG_CMD_PING
++#undef CONFIG_CMD_IMLS
++
++
++#define CONFIG_ARCH_EARLY_INIT_R
++
++#define CONFIG_SYS_HZ                 1000
++
++#define CONFIG_HWCONFIG
++#define HWCONFIG_BUFFER_SIZE          128
++
++#define CONFIG_DISPLAY_CPUINFO
++
++/* Initial environment variables */
++#define CONFIG_EXTRA_ENV_SETTINGS             \
++      "initrd_high=0xffffffff\0"              \
++      "verify=no\0"                           \
++      "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
++      "loadaddr=0x80100000\0"                 \
++      "kernel_addr=0x100000\0"                \
++      "ramdisk_addr=0x800000\0"               \
++      "ramdisk_size=0x2000000\0"              \
++      "fdt_high=0xffffffffffffffff\0"         \
++      "initrd_high=0xffffffffffffffff\0"      \
++      "kernel_start=0xa00000\0"               \
++      "kernel_load=0xa0000000\0"              \
++      "kernel_size=0x2800000\0"               \
++      "console=ttyAMA0,38400n8\0"
++
++#ifdef        CONFIG_EMU
++#define CONFIG_BOOTARGS               "console=ttyS2,115200 root=/dev/ram0 " \
++                              "earlycon=uart8250,mmio,0x21d0500,115200n8"
++/* Kernel image should be pre-loaded to address kernel_load */
++#define CONFIG_BOOTCOMMAND    "bootm $kernel_load"
++#else
++#define CONFIG_BOOTARGS               "console=ttyS0,115200 root=/dev/ram0 " \
++                              "earlycon=uart8250,mmio,0x21c0500"
++#define CONFIG_BOOTCOMMAND            "sf probe 0:0; sf read $kernel_load "\
++                                      "$kernel_start $kernel_size && "\
++                                      "bootm $kernel_load"
++#endif
++#define CONFIG_BOOTDELAY              10
++
++/* Monitor Command Prompt */
++#define CONFIG_SYS_CBSIZE             512     /* Console I/O Buffer Size */
++#define CONFIG_SYS_PROMPT             "=> "
++#define CONFIG_SYS_PBSIZE             (CONFIG_SYS_CBSIZE + \
++                                      sizeof(CONFIG_SYS_PROMPT) + 16)
++#define CONFIG_SYS_HUSH_PARSER
++#define CONFIG_SYS_PROMPT_HUSH_PS2    "> "
++#define CONFIG_SYS_BARGSIZE           CONFIG_SYS_CBSIZE /* Boot args buffer */
++#define CONFIG_SYS_LONGHELP
++#define CONFIG_CMDLINE_EDITING                1
++#define CONFIG_AUTO_COMPLETE
++#define CONFIG_SYS_MAXARGS            64      /* max command args */
++
++#define CONFIG_PANIC_HANG
++#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
++
++/* Flat Device Tree Definitions */
++#define CONFIG_OF_LIBFDT
++#define CONFIG_OF_BOARD_SETUP
++
++/* new uImage format support */
++#define CONFIG_FIT
++#define CONFIG_FIT_VERBOSE    /* enable fit_format_{error,warning}() */
++#define CONFIG_CMD_BOOTZ
++#define CONFIG_CMDLINE_TAG
++
++#include <asm/fsl_secure_boot.h>
++
++#endif /* __LS1012A_COMMON_H */
+diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
+new file mode 100644
+index 0000000..6346d3e
+--- /dev/null
++++ b/include/configs/ls1012aqds.h
+@@ -0,0 +1,133 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++#ifndef __LS1012AQDS_H__
++#define __LS1012AQDS_H__
++
++#include "ls1012a_common.h"
++
++
++#define CONFIG_DIMM_SLOTS_PER_CTLR    1
++#define CONFIG_CHIP_SELECTS_PER_CTRL  1
++#define CONFIG_NR_DRAM_BANKS          2
++
++#ifdef CONFIG_SYS_DPAA_FMAN
++#define CONFIG_FMAN_ENET
++#define CONFIG_PHYLIB
++#define CONFIG_PHY_VITESSE
++#define CONFIG_PHY_REALTEK
++#define RGMII_PHY1_ADDR               0x1
++#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
++#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
++#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
++#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
++#endif
++
++#define CONFIG_QIXIS_I2C_ACCESS
++
++/*
++ * I2C bus multiplexer
++ */
++#define I2C_MUX_PCA_ADDR_PRI          0x77
++#define I2C_MUX_PCA_ADDR_SEC          0x76 /* Secondary multiplexer */
++#define I2C_RETIMER_ADDR              0x18
++#define I2C_MUX_CH_DEFAULT            0x8
++#define I2C_MUX_CH_CH7301             0xC
++#define I2C_MUX_CH5                   0xD
++#define I2C_MUX_CH7                   0xF
++
++#define I2C_MUX_CH_VOL_MONITOR 0xa
++
++/*
++* RTC configuration
++*/
++#define RTC
++#define CONFIG_RTC_PCF8563 1
++#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
++#define CONFIG_CMD_DATE
++
++/* EEPROM */
++#define CONFIG_ID_EEPROM
++#define CONFIG_CMD_EEPROM
++#define CONFIG_SYS_I2C_EEPROM_NXID
++#define CONFIG_SYS_EEPROM_BUS_NUM    0
++#define CONFIG_SYS_I2C_EEPROM_ADDR   0x57
++#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN     1
++#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
++#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
++
++
++/* Voltage monitor on channel 2*/
++#define I2C_VOL_MONITOR_ADDR           0x40
++#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
++#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
++#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
++
++/* DSPI */
++#define CONFIG_FSL_DSPI
++#define CONFIG_FSL_DSPI1
++#define CONFIG_DEFAULT_SPI_BUS 1
++
++#define CONFIG_CMD_SPI
++#define MMAP_DSPI          DSPI1_BASE_ADDR
++
++#define CONFIG_SYS_DSPI_CTAR0   1
++
++#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
++                              DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
++                              DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
++                              DSPI_CTAR_DT(0))
++#define CONFIG_SPI_FLASH_SST /* cs1 */
++
++#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
++                              DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
++                              DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
++                              DSPI_CTAR_DT(0))
++#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
++
++#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
++                              DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
++                              DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
++                              DSPI_CTAR_DT(0))
++#define CONFIG_SPI_FLASH_EON /* cs3 */
++
++#define CONFIG_SF_DEFAULT_SPEED      10000000
++#define CONFIG_SF_DEFAULT_MODE       SPI_MODE_0
++#define CONFIG_SF_DEFAULT_BUS        1
++#define CONFIG_SF_DEFAULT_CS         0
++
++/*
++* USB
++*/
++/* EHCI Support - disbaled by default */
++/*#define CONFIG_HAS_FSL_DR_USB*/
++
++#ifdef CONFIG_HAS_FSL_DR_USB
++#define CONFIG_USB_EHCI
++#define CONFIG_USB_EHCI_FSL
++#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
++#endif
++
++/*XHCI Support - enabled by default*/
++#define CONFIG_HAS_FSL_XHCI_USB
++
++#ifdef CONFIG_HAS_FSL_XHCI_USB
++#define CONFIG_USB_XHCI
++#define CONFIG_USB_XHCI_FSL
++#define CONFIG_USB_XHCI_DWC3
++#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
++#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
++#define CONFIG_CMD_USB
++#define CONFIG_USB_STORAGE
++#define CONFIG_CMD_EXT2
++#endif
++
++#define CONFIG_CMD_MEMINFO
++#define CONFIG_CMD_MEMTEST
++#define CONFIG_SYS_MEMTEST_START      0x80000000
++#define CONFIG_SYS_MEMTEST_END                0x9fffffff
++
++#endif /* __LS1012AQDS_H__ */
+diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
+index 3df822e..d47e625 100644
+--- a/include/fsl_mmdc.h
++++ b/include/fsl_mmdc.h
+@@ -25,29 +25,70 @@ struct mmdc_p_regs {
+       u32 mdcfg3lp;
+       u32 mdmr4;
+       u32 mdasp;
+-      u32 res3[239];
++      u32 res2[239];
+       u32 maarcr;
+       u32 mapsr;
+-      u32 res4[254];
++      u32 maexidr0;
++      u32 maexidr1;
++      u32 madpcr0;
++      u32 madpcr1;
++      u32 madpsr0;
++      u32 madpsr1;
++      u32 madpsr2;
++      u32 madpsr3;
++      u32 madpsr4;
++      u32 madpsr5;
++      u32 masbs0;
++      u32 masbs1;
++      u32 res3[2];
++      u32 magenp;
++      u32 res4[239];
+       u32 mpzqhwctrl;
+-      u32 res5[2];
++      u32 mpzqswctrl;
++      u32 mpwlgcr;
+       u32 mpwldectrl0;
+       u32 mpwldectrl1;
+-      u32 res6;
++      u32 mpwldlst;
+       u32 mpodtctrl;
+       u32 mprddqby0dl;
+       u32 mprddqby1dl;
+       u32 mprddqby2dl;
+       u32 mprddqby3dl;
+-      u32 res7[4];
++      u32 res5[4];
+       u32 mpdgctrl0;
+       u32 mpdgctrl1;
+-      u32 res8;
++      u32 mpdgdlst0;
+       u32 mprddlctl;
+-      u32 res9;
++      u32 mprddlst;
+       u32 mpwrdlctl;
+-      u32 res10[25];
++      u32 mpwrdlst;
++      u32 mpsdctrl;
++      u32 mpzqlp2ctl;
++      u32 mprddlhwctl;
++      u32 mpwrdlhwctl;
++      u32 mprddlhwst0;
++      u32 mprddlhwst1;
++      u32 mpwrdlhwst0;
++      u32 mpwrdlhwst1;
++      u32 mpwlhwerr;
++      u32 mpdghwst0;
++      u32 mpdghwst1;
++      u32 mpdghwst2;
++      u32 mpdghwst3;
++      u32 mppdcmpr1;
++      u32 mppdcmpr2;
++      u32 mpswdar0;
++      u32 mpswdrdr0;
++      u32 mpswdrdr1;
++      u32 mpswdrdr2;
++      u32 mpswdrdr3;
++      u32 mpswdrdr4;
++      u32 mpswdrdr5;
++      u32 mpswdrdr6;
++      u32 mpswdrdr7;
+       u32 mpmur0;
++      u32 mpwrcadl;
++      u32 mpdccr;
+ };
+ 
+ #endif /* FSL_MMDC_H */
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0015-armv8-ls1012a-Add-support-of-ls1012ardb-board.patch b/package/boot/uboot-layerscape/patches/0015-armv8-ls1012a-Add-support-of-ls1012ardb-board.patch
new file mode 100644 (file)
index 0000000..1c23602
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0015-armv8-ls1012a-Add-support-of-ls1012ardb-board.patch
@@ -0,0 +1,634 @@
+From 4bb641f4d28053bd1ff4af73dc0a63be2151f851 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Mon, 25 Apr 2016 14:37:33 +0530
+Subject: [PATCH 15/93] armv8: ls1012a: Add support of ls1012ardb board
+
+QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012ARDB board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/Kconfig                        |   10 ++
+ arch/arm/dts/Makefile                   |    3 +-
+ arch/arm/dts/fsl-ls1012a-rdb.dts        |   16 +++
+ arch/arm/dts/fsl-ls1012a-rdb.dtsi       |   39 ++++++
+ board/freescale/ls1012ardb/Kconfig      |   15 +++
+ board/freescale/ls1012ardb/MAINTAINERS  |    6 +
+ board/freescale/ls1012ardb/Makefile     |    7 +
+ board/freescale/ls1012ardb/README       |   89 +++++++++++++
+ board/freescale/ls1012ardb/ls1012ardb.c |  220 +++++++++++++++++++++++++++++++
+ configs/ls1012ardb_qspi_defconfig       |   10 ++
+ include/configs/ls1012a_common.h        |    3 +-
+ include/configs/ls1012ardb.h            |   61 +++++++++
+ include/linux/usb/xhci-fsl.h            |    2 +-
+ 13 files changed, 477 insertions(+), 4 deletions(-)
+ create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dts
+ create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dtsi
+ create mode 100644 board/freescale/ls1012ardb/Kconfig
+ create mode 100644 board/freescale/ls1012ardb/MAINTAINERS
+ create mode 100644 board/freescale/ls1012ardb/Makefile
+ create mode 100644 board/freescale/ls1012ardb/README
+ create mode 100644 board/freescale/ls1012ardb/ls1012ardb.c
+ create mode 100644 configs/ls1012ardb_qspi_defconfig
+ create mode 100644 include/configs/ls1012ardb.h
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index f5033db..5c20801 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -656,6 +656,15 @@ config TARGET_LS1012AQDS
+         development platform that supports the QorIQ LS1012A
+         Layerscape Architecture processor.
+ 
++config TARGET_LS1012ARDB
++      bool "Support ls1012ardb"
++      select ARM64
++      help
++        Support for Freescale LS1012ARDB platform.
++        The LS1012A Reference design board (RDB) is a high-performance
++        development platform that supports the QorIQ LS1012A
++        Layerscape Architecture processor.
++
+ config TARGET_LS1021AQDS
+       bool "Support ls1021aqds"
+       select CPU_V7
+@@ -802,6 +811,7 @@ source "board/freescale/ls1043aqds/Kconfig"
+ source "board/freescale/ls1021atwr/Kconfig"
+ source "board/freescale/ls1043ardb/Kconfig"
+ source "board/freescale/ls1012aqds/Kconfig"
++source "board/freescale/ls1012ardb/Kconfig"
+ source "board/freescale/mx23evk/Kconfig"
+ source "board/freescale/mx25pdk/Kconfig"
+ source "board/freescale/mx28evk/Kconfig"
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index ed5eb38..9e8137b 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -95,7 +95,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
+ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
+       fsl-ls1043a-qds-lpuart.dtb \
+       fsl-ls1043a-rdb.dtb \
+-      fsl-ls1012a-qds.dtb
++      fsl-ls1012a-qds.dtb \
++      fsl-ls1012a-rdb.dtb
+ 
+ dtb-$(CONFIG_MACH_SUN4I) += \
+       sun4i-a10-a1000.dtb \
+diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dts b/arch/arm/dts/fsl-ls1012a-rdb.dts
+new file mode 100644
+index 0000000..4ec9786
+--- /dev/null
++++ b/arch/arm/dts/fsl-ls1012a-rdb.dts
+@@ -0,0 +1,16 @@
++/*
++ * Device Tree file for Freescale Layerscape-1012A family SoC.
++ *
++ * Copyright (C) 2016, Freescale Semiconductor
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++/dts-v1/;
++#include "fsl-ls1012a-rdb.dtsi"
++
++/ {
++       chosen {
++               stdout-path = &duart0;
++       };
++};
+diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
+new file mode 100644
+index 0000000..71aba78
+--- /dev/null
++++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
+@@ -0,0 +1,39 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
++ *
++ * Copyright (C) 2016, Freescale Semiconductor
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++/include/ "fsl-ls1012a.dtsi"
++
++/ {
++      model = "LS1012A RDB Board";
++      aliases {
++              spi0 = &qspi;
++      };
++};
++
++&qspi {
++      bus-num = <0>;
++      status = "okay";
++
++      qflash0: s25fl128s@0 {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "spi-flash";
++              spi-max-frequency = <20000000>;
++              reg = <0>;
++      };
++};
++
++&i2c0 {
++      status = "okay";
++};
++
++&duart0 {
++      status = "okay";
++};
+diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
+new file mode 100644
+index 0000000..3f67c28
+--- /dev/null
++++ b/board/freescale/ls1012ardb/Kconfig
+@@ -0,0 +1,15 @@
++if TARGET_LS1012ARDB
++
++config SYS_BOARD
++      default "ls1012ardb"
++
++config SYS_VENDOR
++      default "freescale"
++
++config SYS_SOC
++      default "fsl-layerscape"
++
++config SYS_CONFIG_NAME
++      default "ls1012ardb"
++
++endif
+diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
+new file mode 100644
+index 0000000..757e810
+--- /dev/null
++++ b/board/freescale/ls1012ardb/MAINTAINERS
+@@ -0,0 +1,6 @@
++LS1012ARDB BOARD
++M:
++S:    Maintained
++F:    board/freescale/ls1012ardb/
++F:    include/configs/ls1012ardb.h
++F:    configs/ls1012ardb_defconfig
+diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
+new file mode 100644
+index 0000000..05fa9d9
+--- /dev/null
++++ b/board/freescale/ls1012ardb/Makefile
+@@ -0,0 +1,7 @@
++#
++# Copyright 2016 Freescale Semiconductor, Inc.
++#
++# SPDX-License-Identifier:      GPL-2.0+
++#
++
++obj-y += ls1012ardb.o
+diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README
+new file mode 100644
+index 0000000..cda03f6
+--- /dev/null
++++ b/board/freescale/ls1012ardb/README
+@@ -0,0 +1,89 @@
++Overview
++--------
++The LS1012ARDB power supplies (PS) provide all the voltages necessary
++for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
++and other onboard peripherals.
++
++LS1012A SoC Overview
++--------------------
++The LS1012A features an advanced 64-bit ARM v8 Cortex-
++A53 processor, with 32 KB of parity protected L1-I cache,
++32 KB of ECC protected L1-D cache, as well as 256 KB of
++ECC protected L2 cache.
++
++The LS1012A SoC includes the following function and features:
++ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
++ - ARM v8 cryptography extensions
++ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
++    16-/8-bit operation (no ECC support)
++ - ARM core-link CCI-400 cache coherent interconnect
++ - Packet Forwarding Engine (PFE)
++ - Cryptography acceleration (SEC)
++ - Ethernet interfaces supported by PFE:
++ - One Configurable x3 SerDes:
++    Two Serdes PLLs supported for usage by any SerDes data lane
++    Support for up to 6 GBaud operation
++ - High-speed peripheral interfaces:
++     - One PCI Express Gen2 controller, supporting x1 operation
++     - One serial ATA (SATA Gen 3.0) controller
++     - One USB 3.0/2.0 controller with integrated PHY
++     - One USB 2.0 controller with ULPI interface. .
++ - Additional peripheral interfaces:
++    - One quad serial peripheral interface (QuadSPI) controller
++    - One serial peripheral interface (SPI) controller
++    - Two enhanced secure digital host controllers
++    - Two I2C controllers
++    - One 16550 compliant DUART (two UART interfaces)
++    - Two general purpose IOs (GPIO)
++    - Two FlexTimers
++    - Five synchronous audio interfaces (SAI)
++    - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
++    - Single-source clocking solution enabling generation of core, platform,
++    DDR, SerDes, and USB clocks from a single external crystal and internal
++    crystaloscillator
++    - Thermal monitor unit (TMU) with +/- 3C accuracy
++    - Two WatchDog timers
++    - ARM generic timer
++ - QorIQ platform's trust architecture 2.1
++
++ LS1012ARDB board Overview
++ -----------------------
++ - SERDES Connections, 4 lanes supporting:
++      - PCI Express - 3.0
++      - SGMII, SGMII 2.5
++      - SATA 3.0
++ - DDR Controller
++     - 6-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
++ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
++ signals to
++    - QSPI NOR flash memory (2 virtual banks)
++    - the QSPI emulator.s
++ - USB 3.0
++    - one high-speed USB 2.0/3.0 port.
++ - Two enhanced secure digital host controllers:
++    - SDHC1 controller can be connected to onboard SDHC connector
++    - SDHC2 controller: Three dual 1:4 mux/demux devices,
++    74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
++    SDIO WiFi, SPI, and Ardiuno shield
++ - 2 I2C controllers
++ - One SATA onboard connectors
++ - UART
++   - The LS1012A processor consists of two UART controllers,
++   out of which only UART1 is used on RDB.
++ - ARM JTAG support
++
++Booting Options
++---------------
++a) QSPI Flash Emu Boot
++b) QSPI Flash 1
++c) QSPI Flash 2
++
++QSPI flash map
++--------------
++Images                | Size  |QSPI Flash Address
++------------------------------------------
++RCW + PBI     | 1MB   | 0x4000_0000
++U-boot                | 1MB   | 0x4010_0000
++U-boot Env    | 1MB   | 0x4020_0000
++PPA FIT image | 2MB   | 0x4050_0000
++Linux ITB     | ~53MB | 0x40A0_0000
+diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
+new file mode 100644
+index 0000000..4a7aaaa
+--- /dev/null
++++ b/board/freescale/ls1012ardb/ls1012ardb.c
+@@ -0,0 +1,220 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++#include <common.h>
++#include <i2c.h>
++#include <asm/io.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/fsl_serdes.h>
++#include <asm/arch/ppa.h>
++#include <asm/arch/soc.h>
++#include <hwconfig.h>
++#include <ahci.h>
++#include <mmc.h>
++#include <scsi.h>
++#include <fsl_csu.h>
++#include <fsl_esdhc.h>
++#include <environment.h>
++#include <fsl_mmdc.h>
++#include <netdev.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int checkboard(void)
++{
++      u8 in1;
++
++      puts("Board: LS1012ARDB ");
++
++      /* Initialize i2c early for Serial flash bank information */
++      i2c_set_bus_num(0);
++
++      if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
++              printf("Error reading i2c boot information!\n");
++              return 0; /* Don't want to hang() on this error */
++      }
++
++      puts("Version");
++      if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
++              puts(": RevA");
++      else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
++              puts(": RevB");
++      else
++              puts(": unknown");
++
++      printf(", boot from QSPI");
++      if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
++              puts(": emu\n");
++      else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
++              puts(": bank1\n");
++      else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
++              puts(": bank2\n");
++      else
++              puts("unknown\n");
++
++      return 0;
++}
++
++void mmdc_init(void)
++{
++      struct mmdc_p_regs *mmdc =
++              (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
++
++      /* Set MMDC_MDSCR[CON_REQ] */
++      out_be32(&mmdc->mdscr, 0x00008000);
++
++      /* configure timing parms */
++      out_be32(&mmdc->mdotc, 0x12554000);
++      out_be32(&mmdc->mdcfg0, 0xbabf7954);
++      out_be32(&mmdc->mdcfg1, 0xff328f64);
++      out_be32(&mmdc->mdcfg2, 0x01ff00db);
++
++      /* other parms  */
++      out_be32(&mmdc->mdmisc,    0x00000680);
++      out_be32(&mmdc->mpmur0,    0x00000800);
++      out_be32(&mmdc->mdrwd,     0x00002000);
++      out_be32(&mmdc->mpodtctrl, 0x0000022a);
++
++      /* out of reset delays */
++      out_be32(&mmdc->mdor, 0x00bf1023);
++
++      /* physical parms */
++      out_be32(&mmdc->mdctl, 0x05180000);
++      out_be32(&mmdc->mdasp, 0x0000007f);
++
++      /* Enable MMDC */
++      out_be32(&mmdc->mdctl, 0x85180000);
++
++      /* dram init sequence: update MRs */
++      out_be32(&mmdc->mdscr, 0x00088032);
++      out_be32(&mmdc->mdscr, 0x00008033);
++      out_be32(&mmdc->mdscr, 0x00048031);
++      out_be32(&mmdc->mdscr, 0x19308030);
++
++      /* dram init sequence: ZQCL */
++      out_be32(&mmdc->mdscr,      0x04008040);
++      out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
++
++      mdelay(100);
++
++      /* Calibrations now: wr lvl */
++      out_be32(&mmdc->mdscr,   0x00848031);
++      out_be32(&mmdc->mdscr,   0x00008200);
++      out_be32(&mmdc->mpwlgcr, 0x00000001);
++
++      mdelay(100);
++
++      out_be32(&mmdc->mdscr, 0x00048031);
++      out_be32(&mmdc->mdscr, 0x00008000);
++
++      /*    manual_refresh */
++      out_be32(&mmdc->mdscr, 0x00008020);
++
++      mdelay(100);
++
++      /* Calibrations now: Read DQS gating calibration */
++      out_be32(&mmdc->mdscr,     0x04008050);
++      out_be32(&mmdc->mdscr,     0x00048033);
++      out_be32(&mmdc->mppdcmpr2, 0x00000001);
++      out_be32(&mmdc->mprddlctl, 0x40404040);
++      out_be32(&mmdc->mpdgctrl0, 0x10000000);
++
++      mdelay(100);
++
++      out_be32(&mmdc->mdscr, 0x00008033);
++
++      /*   manual_refresh */
++      out_be32(&mmdc->mdscr, 0x00008020);
++
++      mdelay(100);
++
++      /* Calibrations now: Read calibration */
++      out_be32(&mmdc->mdscr,       0x04008050);
++      out_be32(&mmdc->mdscr,       0x00048033);
++      out_be32(&mmdc->mppdcmpr2,   0x00000001);
++      out_be32(&mmdc->mprddlhwctl, 0x00000010);
++
++      mdelay(400);
++
++      out_be32(&mmdc->mdscr, 0x00008033);
++
++      /* manual_refresh */
++      out_be32(&mmdc->mdscr, 0x00008020);
++
++      mdelay(100);
++
++      /* PD, SR */
++      out_be32(&mmdc->mdpdc, 0x00030035);
++      out_be32(&mmdc->mapsr, 0x00001067);
++
++      /* refresh scheme */
++      out_be32(&mmdc->mdref, 0x103e8000);
++
++      mdelay(400);
++
++      /* disable CON_REQ */
++      out_be32(&mmdc->mdscr, 0x0);
++
++      mdelay(50);
++}
++
++int dram_init(void)
++{
++      mmdc_init();
++
++      gd->ram_size = 0x40000000;
++
++      return 0;
++}
++
++int board_eth_init(bd_t *bis)
++{
++      return pci_eth_init(bis);
++}
++
++int board_early_init_f(void)
++{
++      fsl_lsch2_early_init_f();
++
++      return 0;
++}
++
++int board_init(void)
++{
++      struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
++      /*
++       * Set CCI-400 control override register to enable barrier
++       * transaction
++       */
++      out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
++
++#ifdef CONFIG_ENV_IS_NOWHERE
++      gd->env_addr = (ulong)&default_environment[0];
++#endif
++
++#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
++      enable_layerscape_ns_access();
++#endif
++
++      return 0;
++}
++
++int ft_board_setup(void *blob, bd_t *bd)
++{
++      u64 base[CONFIG_NR_DRAM_BANKS];
++      u64 size[CONFIG_NR_DRAM_BANKS];
++
++      /* fixup DT for the two DDR banks */
++      base[0] = gd->bd->bi_dram[0].start;
++      size[0] = gd->bd->bi_dram[0].size;
++      base[1] = gd->bd->bi_dram[1].start;
++      size[1] = gd->bd->bi_dram[1].size;
++
++      fdt_fixup_memory_banks(blob, base, size, 2);
++      ft_cpu_setup(blob, bd);
++
++      return 0;
++}
+diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
+new file mode 100644
+index 0000000..f819038
+--- /dev/null
++++ b/configs/ls1012ardb_qspi_defconfig
+@@ -0,0 +1,10 @@
++CONFIG_ARM=y
++CONFIG_TARGET_LS1012ARDB=y
++CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
++# CONFIG_CMD_IMLS is not set
++CONFIG_SYS_NS16550=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
++CONFIG_OF_CONTROL=y
++CONFIG_DM=y
++CONFIG_SPI_FLASH=y
++CONFIG_DM_SPI=y
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 9ed04f9..3fd360a 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -12,7 +12,7 @@
+ #define CONFIG_LS1012A
+ #define CONFIG_GICV2
+ 
+-#define       CONFIG_SYS_HAS_SERDES
++#define CONFIG_SYS_HAS_SERDES
+ 
+ #include <asm/arch/config.h>
+ #define CONFIG_SYS_NO_FLASH
+@@ -56,7 +56,6 @@
+ #define CONFIG_ENV_SPI_MODE           0x03
+ #define CONFIG_CMD_SF
+ #define CONFIG_SPI_FLASH_SPANSION
+-#define CONFIG_SPI_FLASH_ATMEL
+ #define CONFIG_FSL_SPI_INTERFACE
+ #define CONFIG_SF_DATAFLASH
+ 
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+new file mode 100644
+index 0000000..9ff5935
+--- /dev/null
++++ b/include/configs/ls1012ardb.h
+@@ -0,0 +1,61 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++#ifndef __LS1012ARDB_H__
++#define __LS1012ARDB_H__
++
++#include "ls1012a_common.h"
++
++
++#define CONFIG_DIMM_SLOTS_PER_CTLR    1
++#define CONFIG_CHIP_SELECTS_PER_CTRL  1
++#define CONFIG_NR_DRAM_BANKS          2
++
++#define CONFIG_CMD_MEMINFO
++#define CONFIG_CMD_MEMTEST
++#define CONFIG_SYS_MEMTEST_START      0x80000000
++#define CONFIG_SYS_MEMTEST_END                0x9fffffff
++
++#define CONFIG_PHYLIB
++#define CONFIG_PHY_REALTEK
++#define SGMII_PHY1_ADDR               0x0
++#define RGMII_PHY2_ADDR               0x1
++
++/*
++* USB
++*/
++#define CONFIG_HAS_FSL_XHCI_USB
++
++#ifdef CONFIG_HAS_FSL_XHCI_USB
++#define CONFIG_USB_XHCI
++#define CONFIG_USB_XHCI_FSL
++#define CONFIG_USB_XHCI_DWC3
++#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
++#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
++#define CONFIG_CMD_USB
++#define CONFIG_USB_STORAGE
++#define CONFIG_CMD_EXT2
++#endif
++
++/*
++ * I2C IO expander
++ */
++
++#define I2C_MUX_IO1_ADDR      0x24
++#define __SW_BOOT_MASK                0xFC
++#define __SW_BOOT_EMU         0x10
++#define __SW_BOOT_BANK1               0x00
++#define __SW_BOOT_BANK2               0x01
++#define __SW_REV_MASK         0x07
++#define __SW_REV_A            0xF8
++#define __SW_REV_B            0xF0
++
++#define CONFIG_CMD_MEMINFO
++#define CONFIG_CMD_MEMTEST
++#define CONFIG_SYS_MEMTEST_START      0x80000000
++#define CONFIG_SYS_MEMTEST_END                0x9fffffff
++
++#endif /* __LS1012ARDB_H__ */
+diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
+index 72a5d5b..7ab88c3 100644
+--- a/include/linux/usb/xhci-fsl.h
++++ b/include/linux/usb/xhci-fsl.h
+@@ -62,7 +62,7 @@ struct fsl_xhci {
+ #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+-#elif defined(CONFIG_LS1043A)
++#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
+ #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0016-ARM-asm-types-Introduce-DMA_ADDR_T_64BIT.patch b/package/boot/uboot-layerscape/patches/0016-ARM-asm-types-Introduce-DMA_ADDR_T_64BIT.patch
new file mode 100644 (file)
index 0000000..7f39efc
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0016-ARM-asm-types-Introduce-DMA_ADDR_T_64BIT.patch
@@ -0,0 +1,80 @@
+From 4aa3d79020aeca3780ea113a495d18662d593761 Mon Sep 17 00:00:00 2001
+From: Lokesh Vutla <lokeshvutla@ti.com>
+Date: Thu, 24 Mar 2016 16:02:00 +0530
+Subject: [PATCH 16/93] ARM: asm: types: Introduce DMA_ADDR_T_64BIT
+
+dma_addr_t holds any valid DMA address. If the DMA API only uses 32-bit
+addresses, dma_addr_t need only be 32 bits wide.  Bus addresses, e.g., PCI BARs,
+may be wider than 32 bits, but drivers do memory-mapped I/O to ioremapped
+kernel virtual addresses, so they don't care about the size of the actual
+bus addresses.
+Also 32 bit ARM systems with LPAE enabled can use 64bit address space, but
+DMA still use 32bit address like in case of DRA7 and Keystone platforms.
+
+This is inspired from the Linux kernel types implementation[1]
+
+[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/include/linux/types.h#n142
+
+Acked-by: Lukasz Majewski <l.majewski@samsung.com>
+Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
+Reviewed-by: Tom Rini <trini@konsulko.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/Kconfig             |    4 ++++
+ arch/arm/include/asm/types.h |   17 +++++++++++++++--
+ 2 files changed, 19 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 5c20801..b536684 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -7,6 +7,10 @@ config SYS_ARCH
+ config ARM64
+       bool
+ 
++config DMA_ADDR_T_64BIT
++      bool
++      default y if ARM64
++
+ config HAS_VBAR
+         bool
+ 
+diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
+index 388058e..d108915 100644
+--- a/arch/arm/include/asm/types.h
++++ b/arch/arm/include/asm/types.h
+@@ -46,16 +46,29 @@ typedef unsigned long long u64;
+ #endif        /* CONFIG_ARM64 */
+ 
+ #ifdef CONFIG_PHYS_64BIT
+-typedef unsigned long long dma_addr_t;
+ typedef unsigned long long phys_addr_t;
+ typedef unsigned long long phys_size_t;
+ #else
+ /* DMA addresses are 32-bits wide */
+-typedef u32 dma_addr_t;
+ typedef unsigned long phys_addr_t;
+ typedef unsigned long phys_size_t;
+ #endif
+ 
++/*
++ * A dma_addr_t can hold any valid DMA address, i.e., any address returned
++ * by the DMA API.
++ *
++ * If the DMA API only uses 32-bit addresses, dma_addr_t need only be 32
++ * bits wide.  Bus addresses, e.g., PCI BARs, may be wider than 32 bits,
++ * but drivers do memory-mapped I/O to ioremapped kernel virtual addresses,
++ * so they don't care about the size of the actual bus addresses.
++ */
++#ifdef CONFIG_DMA_ADDR_T_64BIT
++typedef unsigned long long dma_addr_t;
++#else
++typedef u32 dma_addr_t;
++#endif
++
+ #endif /* __KERNEL__ */
+ 
+ typedef unsigned long resource_size_t;
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0017-armv8-fsl-layerscape-add-dwc3-gadget-driver-support.patch b/package/boot/uboot-layerscape/patches/0017-armv8-fsl-layerscape-add-dwc3-gadget-driver-support.patch
new file mode 100644 (file)
index 0000000..6095082
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0017-armv8-fsl-layerscape-add-dwc3-gadget-driver-support.patch
@@ -0,0 +1,465 @@
+From f160c56c71c59d2d865142fdeb3040e9cc4b6a77 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Mon, 25 Apr 2016 17:14:25 +0530
+Subject: [PATCH 17/93] armv8/fsl-layerscape: add dwc3 gadget driver support
+
+Implements the dwc3 gadget driver support for LS1043
+and LS1012 platform.
+
+NOTE: Do not upstream this patch.It needs rework for open source
+submission.
+
+Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/soc.c            |   98 +++++++++++++++++++-
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |    6 ++
+ .../include/asm/arch-fsl-layerscape/sys_proto.h    |   10 ++
+ common/cmd_usb_mass_storage.c                      |    2 +-
+ drivers/usb/dwc3/core.c                            |   12 +++
+ drivers/usb/dwc3/ep0.c                             |   10 +-
+ drivers/usb/dwc3/gadget.c                          |   11 ++-
+ drivers/usb/dwc3/io.h                              |    8 +-
+ drivers/usb/gadget/f_mass_storage.c                |   10 +-
+ include/configs/ls1012aqds.h                       |   15 +++
+ include/configs/ls1012ardb.h                       |   15 +++
+ include/configs/ls1043aqds.h                       |   15 +++
+ 12 files changed, 197 insertions(+), 15 deletions(-)
+ create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+index ec561a7..0a170eb 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+@@ -19,6 +19,10 @@
+ #ifdef CONFIG_CHAIN_OF_TRUST
+ #include <fsl_validate.h>
+ #endif
++#include <usb.h>
++#include <dwc3-uboot.h>
++#include <linux/usb/xhci-fsl.h>
++
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
+@@ -406,9 +410,19 @@ void fsl_lsch2_early_init_f(void)
+ #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
+       out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+ #endif
+-      /* Make SEC reads and writes snoopable */
++
++#if defined(CONFIG_LS1043A)
++      /* Make SEC and USB reads and writes snoopable */
+       setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
+-                   SCFG_SNPCNFGCR_SECWRSNP);
++                   SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
++                   SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
++                   SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
++                   SCFG_SNPCNFGCR_USB3WRSNP);
++#elif defined(CONFIG_LS1012A)
++      /* Make SEC and reads and writes snoopable */
++      setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP |
++                   SCFG_SNPCNFGCR_USB1RDSNP | SCFG_SNPCNFGCR_USB1WRSNP);
++#endif
+ 
+       /*
+        * Enable snoop requests and DVM message requests for
+@@ -428,6 +442,86 @@ void fsl_lsch2_early_init_f(void)
+ }
+ #endif
+ 
++#ifdef CONFIG_USB_DWC3
++
++#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
++static struct dwc3_device dwc3_device_data0 = {
++      .maximum_speed = USB_SPEED_HIGH,
++      .base = CONFIG_SYS_FSL_XHCI_USB1_ADDR,
++      .dr_mode = USB_DR_MODE_PERIPHERAL,
++      .index = 0,
++};
++
++#if defined(CONFIG_LS1043A)
++static struct dwc3_device dwc3_device_data1 = {
++      .maximum_speed = USB_SPEED_HIGH,
++      .base = CONFIG_SYS_FSL_XHCI_USB2_ADDR,
++      .dr_mode = USB_DR_MODE_PERIPHERAL,
++      .index = 1,
++};
++
++static struct dwc3_device dwc3_device_data2 = {
++      .maximum_speed = USB_SPEED_HIGH,
++      .base = CONFIG_SYS_FSL_XHCI_USB3_ADDR,
++      .dr_mode = USB_DR_MODE_PERIPHERAL,
++      .index = 2,
++};
++#endif
++
++int usb_gadget_handle_interrupts(int index)
++{
++      dwc3_uboot_handle_interrupt(index);
++      return 0;
++}
++#endif
++
++int board_usb_init(int index, enum usb_init_type init)
++{
++      switch (init) {
++      case USB_INIT_DEVICE:
++              switch (index) {
++#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
++              case 0:
++                      dwc3_uboot_init(&dwc3_device_data0);
++                      break;
++
++#if defined(CONFIG_LS1043A)
++              case 1:
++                      dwc3_uboot_init(&dwc3_device_data1);
++                      break;
++              case 2:
++                      dwc3_uboot_init(&dwc3_device_data2);
++                      break;
++#endif
++#endif
++              default:
++                      printf("Invalid Controller Index\n");
++                      return -1;
++              }
++              break;
++      default:
++              break;
++      }
++      return 0;
++}
++
++int board_usb_cleanup(int index, enum usb_init_type init)
++{
++      switch (init) {
++      case USB_INIT_DEVICE:
++#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
++              dwc3_uboot_exit(index);
++#endif
++              break;
++      default:
++              break;
++      }
++      return 0;
++}
++#endif
++
++
++
+ #ifdef CONFIG_BOARD_LATE_INIT
+ int board_late_init(void)
+ {
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index 5b026f8..414a222 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -355,6 +355,12 @@ struct ccsr_gur {
+ 
+ #define SCFG_SNPCNFGCR_SECRDSNP               0x80000000
+ #define SCFG_SNPCNFGCR_SECWRSNP               0x40000000
++#define SCFG_SNPCNFGCR_USB1RDSNP      0x00200000
++#define SCFG_SNPCNFGCR_USB1WRSNP      0x00100000
++#define SCFG_SNPCNFGCR_USB2RDSNP      0x00008000
++#define SCFG_SNPCNFGCR_USB2WRSNP      0x00010000
++#define SCFG_SNPCNFGCR_USB3RDSNP      0x00002000
++#define SCFG_SNPCNFGCR_USB3WRSNP      0x00004000
+ 
+ /* Supplemental Configuration Unit */
+ struct ccsr_scfg {
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
+new file mode 100644
+index 0000000..1e31d3d
+--- /dev/null
++++ b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
+@@ -0,0 +1,10 @@
++/*
++ * Copyright 2015 Freescale Semiconductor
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SYS_PROTO_H_
++#define _ASM_ARMV8_FSL_LAYERSCAPE_SYS_PROTO_H_
++
++#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SYS_PROTO_H_ */
+diff --git a/common/cmd_usb_mass_storage.c b/common/cmd_usb_mass_storage.c
+index 0407389..7d507b5 100644
+--- a/common/cmd_usb_mass_storage.c
++++ b/common/cmd_usb_mass_storage.c
+@@ -140,7 +140,7 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
+       while (1) {
+               usb_gadget_handle_interrupts(controller_index);
+ 
+-              rc = fsg_main_thread(NULL);
++              rc = fsg_main_thread(&controller_index);
+               if (rc) {
+                       /* Check I/O error */
+                       if (rc == -EIO)
+diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
+index 85cc96a..b8e4066 100644
+--- a/drivers/usb/dwc3/core.c
++++ b/drivers/usb/dwc3/core.c
+@@ -690,6 +690,18 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
+               return -ENOMEM;
+       }
+ 
++#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
++       /* Change burst beat and outstanding pipelined transfers requests */
++      dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
++                  (dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) & ~0xff) | 0xf);
++      dwc3_writel(dwc->regs, DWC3_GSBUSCFG1,
++                  dwc3_readl(dwc->regs, DWC3_GSBUSCFG1) | 0xf00);
++
++      /* Enable snooping */
++      dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
++                  dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) | 0x22220000);
++#endif
++
+       if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
+               dwc->dr_mode = USB_DR_MODE_HOST;
+       else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
+diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
+index 12b133f..e61d980 100644
+--- a/drivers/usb/dwc3/ep0.c
++++ b/drivers/usb/dwc3/ep0.c
+@@ -81,8 +81,8 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
+               trb->ctrl |= (DWC3_TRB_CTRL_IOC
+                               | DWC3_TRB_CTRL_LST);
+ 
+-      dwc3_flush_cache((long)buf_dma, len);
+-      dwc3_flush_cache((long)trb, sizeof(*trb));
++      dwc3_flush_cache((uintptr_t)buf_dma, len);
++      dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
+ 
+       if (chain)
+               return 0;
+@@ -790,7 +790,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
+       if (!r)
+               return;
+ 
+-      dwc3_flush_cache((long)trb, sizeof(*trb));
++      dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
+ 
+       status = DWC3_TRB_SIZE_TRBSTS(trb->size);
+       if (status == DWC3_TRBSTS_SETUP_PENDING) {
+@@ -821,7 +821,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
+                       ur->actual += transferred;
+ 
+                       trb++;
+-                      dwc3_flush_cache((long)trb, sizeof(*trb));
++                      dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
+                       length = trb->size & DWC3_TRB_SIZE_MASK;
+ 
+                       ep0->free_slot = 0;
+@@ -831,7 +831,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
+                                       maxp);
+               transferred = min_t(u32, ur->length - transferred,
+                                   transfer_size - length);
+-              dwc3_flush_cache((long)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
++              dwc3_flush_cache((uintptr_t)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
+               memcpy(buf, dwc->ep0_bounce, transferred);
+       } else {
+               transferred = ur->length - length;
+diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
+index 8ff949d..649f1a4 100644
+--- a/drivers/usb/dwc3/gadget.c
++++ b/drivers/usb/dwc3/gadget.c
+@@ -244,7 +244,7 @@ void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
+ 
+       list_del(&req->list);
+       req->trb = NULL;
+-      dwc3_flush_cache((long)req->request.dma, req->request.length);
++      dwc3_flush_cache((uintptr_t)req->request.dma, req->request.length);
+ 
+       if (req->request.status == -EINPROGRESS)
+               req->request.status = status;
+@@ -771,8 +771,8 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
+ 
+       trb->ctrl |= DWC3_TRB_CTRL_HWO;
+ 
+-      dwc3_flush_cache((long)dma, length);
+-      dwc3_flush_cache((long)trb, sizeof(*trb));
++      dwc3_flush_cache((uintptr_t)dma, length);
++      dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
+ }
+ 
+ /*
+@@ -1769,7 +1769,7 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
+       slot %= DWC3_TRB_NUM;
+       trb = &dep->trb_pool[slot];
+ 
+-      dwc3_flush_cache((long)trb, sizeof(*trb));
++      dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
+       __dwc3_cleanup_done_trbs(dwc, dep, req, trb, event, status);
+       dwc3_gadget_giveback(dep, req, status);
+ 
+@@ -2447,6 +2447,7 @@ static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
+       int left;
+       u32 reg;
+ 
++
+       evt = dwc->ev_buffs[buf];
+       left = evt->count;
+ 
+@@ -2670,7 +2671,7 @@ void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
+ 
+               for (i = 0; i < dwc->num_event_buffers; i++) {
+                       evt = dwc->ev_buffs[i];
+-                      dwc3_flush_cache((long)evt->buf, evt->length);
++                      dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
+               }
+ 
+               dwc3_thread_interrupt(0, dwc);
+diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h
+index 0d9fa22..cab5122 100644
+--- a/drivers/usb/dwc3/io.h
++++ b/drivers/usb/dwc3/io.h
+@@ -48,8 +48,14 @@ static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value)
+       writel(value, base + offs);
+ }
+ 
+-static inline void dwc3_flush_cache(int addr, int length)
++static inline void dwc3_flush_cache(uintptr_t addr, int length)
+ {
+       flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
+ }
++
++static inline void dwc3_inval_cache(uintptr_t addr, int length)
++{
++      invalidate_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
++}
++
+ #endif /* __DRIVERS_USB_DWC3_IO_H */
+diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
+index ec1f23a..ec0229f 100644
+--- a/drivers/usb/gadget/f_mass_storage.c
++++ b/drivers/usb/gadget/f_mass_storage.c
+@@ -362,6 +362,7 @@ struct fsg_common {
+       char inquiry_string[8 + 16 + 4 + 1];
+ 
+       struct kref             ref;
++      unsigned int controller_index;
+ };
+ 
+ struct fsg_config {
+@@ -690,7 +691,7 @@ static int sleep_thread(struct fsg_common *common)
+                       k = 0;
+               }
+ 
+-              usb_gadget_handle_interrupts(0);
++              usb_gadget_handle_interrupts(common->controller_index);
+       }
+       common->thread_wakeup_needed = 0;
+       return rc;
+@@ -2405,6 +2406,11 @@ int fsg_main_thread(void *common_)
+ {
+       int ret;
+       struct fsg_common       *common = the_fsg_common;
++
++      /* update the controller_index */
++      if (common_)
++              common->controller_index = *(unsigned int *)common_;
++
+       /* The main loop */
+       do {
+               if (exception_in_progress(common)) {
+@@ -2475,6 +2481,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common,
+ 
+       common->ops = NULL;
+       common->private_data = NULL;
++      common->controller_index = 0;
+ 
+       common->gadget = gadget;
+       common->ep0 = gadget->ep0;
+@@ -2769,6 +2776,7 @@ int fsg_add(struct usb_configuration *c)
+ 
+       fsg_common->ops = NULL;
+       fsg_common->private_data = NULL;
++      fsg_common->controller_index = 0;
+ 
+       the_fsg_common = fsg_common;
+ 
+diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
+index 6346d3e..fdada18 100644
+--- a/include/configs/ls1012aqds.h
++++ b/include/configs/ls1012aqds.h
+@@ -123,6 +123,21 @@
+ #define CONFIG_CMD_USB
+ #define CONFIG_USB_STORAGE
+ #define CONFIG_CMD_EXT2
++
++#define CONFIG_USB_DWC3
++#define CONFIG_USB_DWC3_GADGET
++
++#define CONFIG_USB_GADGET
++#define CONFIG_USB_FUNCTION_MASS_STORAGE
++#define CONFIG_USB_GADGET_DOWNLOAD
++#define CONFIG_USB_GADGET_VBUS_DRAW 2
++#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
++#define CONFIG_G_DNL_VENDOR_NUM 0x1234
++#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
++#define CONFIG_USB_GADGET_DUALSPEED
++
++/* USB Gadget ums command */
++#define CONFIG_CMD_USB_MASS_STORAGE
+ #endif
+ 
+ #define CONFIG_CMD_MEMINFO
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index 9ff5935..af3d33f 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -38,6 +38,21 @@
+ #define CONFIG_CMD_USB
+ #define CONFIG_USB_STORAGE
+ #define CONFIG_CMD_EXT2
++
++#define CONFIG_USB_DWC3
++#define CONFIG_USB_DWC3_GADGET
++
++#define CONFIG_USB_GADGET
++#define CONFIG_USB_FUNCTION_MASS_STORAGE
++#define CONFIG_USB_GADGET_DOWNLOAD
++#define CONFIG_USB_GADGET_VBUS_DRAW 2
++#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
++#define CONFIG_G_DNL_VENDOR_NUM 0x1234
++#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
++#define CONFIG_USB_GADGET_DUALSPEED
++
++/* USB Gadget ums command */
++#define CONFIG_CMD_USB_MASS_STORAGE
+ #endif
+ 
+ /*
+diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
+index 9828360..9e23615 100644
+--- a/include/configs/ls1043aqds.h
++++ b/include/configs/ls1043aqds.h
+@@ -400,6 +400,21 @@ unsigned long get_board_ddr_clk(void);
+ #define CONFIG_CMD_USB
+ #define CONFIG_USB_STORAGE
+ #define CONFIG_CMD_EXT2
++
++#define CONFIG_USB_DWC3
++#define CONFIG_USB_DWC3_GADGET
++
++#define CONFIG_USB_GADGET
++#define CONFIG_USB_FUNCTION_MASS_STORAGE
++#define CONFIG_USB_GADGET_DOWNLOAD
++#define CONFIG_USB_GADGET_VBUS_DRAW 2
++#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
++#define CONFIG_G_DNL_VENDOR_NUM 0x1234
++#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
++#define CONFIG_USB_GADGET_DUALSPEED
++
++/* USB Gadget ums command */
++#define CONFIG_CMD_USB_MASS_STORAGE
+ #endif
+ 
+ /*
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0018-boards-ls1012aqds-Enable-SDHC_CD-in-brdcfg10-of-FPGA.patch b/package/boot/uboot-layerscape/patches/0018-boards-ls1012aqds-Enable-SDHC_CD-in-brdcfg10-of-FPGA.patch
new file mode 100644 (file)
index 0000000..f46b1b2
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0018-boards-ls1012aqds-Enable-SDHC_CD-in-brdcfg10-of-FPGA.patch
@@ -0,0 +1,62 @@
+From 035a4db85bbf28ba1452c49c9f8d05a085f2544b Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Tue, 26 Apr 2016 17:40:05 +0530
+Subject: [PATCH 18/93] boards: ls1012aqds: Enable SDHC_CD in brdcfg10 of FPGA
+
+Default configuration of brdcfg10 in FPGA does not enable SDHC_CD
+signal.
+
+Enable SDHC_CD by default during boot sequence.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ board/freescale/ls1012aqds/ls1012aqds.c |   12 ++++++++++++
+ include/configs/ls1012aqds.h            |    3 +++
+ 2 files changed, 15 insertions(+)
+
+diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
+index ffcd0d8..6d5fef8 100644
+--- a/board/freescale/ls1012aqds/ls1012aqds.c
++++ b/board/freescale/ls1012aqds/ls1012aqds.c
+@@ -154,6 +154,18 @@ int board_early_init_f(void)
+       return 0;
+ }
+ 
++#ifdef CONFIG_MISC_INIT_R
++int misc_init_r(void)
++{
++      u8 mux_sdhc_cd = 0x80;
++
++      i2c_set_bus_num(0);
++
++      i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
++      return 0;
++}
++#endif
++
+ int board_init(void)
+ {
+       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
+diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
+index fdada18..bb433de 100644
+--- a/include/configs/ls1012aqds.h
++++ b/include/configs/ls1012aqds.h
+@@ -27,6 +27,7 @@
+ #endif
+ 
+ #define CONFIG_QIXIS_I2C_ACCESS
++#define CONFIG_SYS_I2C_FPGA_ADDR      0x66
+ 
+ /*
+  * I2C bus multiplexer
+@@ -145,4 +146,6 @@
+ #define CONFIG_SYS_MEMTEST_START      0x80000000
+ #define CONFIG_SYS_MEMTEST_END                0x9fffffff
+ 
++#define CONFIG_MISC_INIT_R
++
+ #endif /* __LS1012AQDS_H__ */
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0019-armv8-ls1012a-Add-CSU-assignment-for-eSDHC2-SAI1-SAI.patch b/package/boot/uboot-layerscape/patches/0019-armv8-ls1012a-Add-CSU-assignment-for-eSDHC2-SAI1-SAI.patch
new file mode 100644 (file)
index 0000000..9b3219f
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0019-armv8-ls1012a-Add-CSU-assignment-for-eSDHC2-SAI1-SAI.patch
@@ -0,0 +1,50 @@
+From 8aad7c4c5d8becaf6c60e1585c8e70010b3c0ce2 Mon Sep 17 00:00:00 2001
+From: Makarand Pawagi <makarand.pawagi@mindspeed.com>
+Date: Mon, 2 May 2016 09:33:45 +0530
+Subject: [PATCH 19/93] armv8: ls1012a: Add CSU assignment for eSDHC2, SAI1,
+ SAI2, SAI3, SAI4
+
+    Access settings for different IPs has to be enabled through CSU registers. Following
+    IP's are added for LS1012A:
+    Added CSU ID for eSDHC-2, reg: CSL40_REG[23:16]
+    Added CSU ID for SAI-1, reg: CSL41_REG[7:0]
+    Added CSU ID for SAI-2, reg: CSL41_REG[23:16]
+    Added CSU ID for SAI-3, reg: CSL42_REG[7:0]
+    Added CSU ID for SAI-4, reg: CSL42_REG[23:16
+---
+ .../include/asm/arch-fsl-layerscape/ns_access.h    |   10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+index a3ccdb0..d6642a7 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+@@ -69,7 +69,12 @@ enum csu_cslx_ind {
+       CSU_CSLX_IIC4 = 77,
+       CSU_CSLX_WDT4,
+       CSU_CSLX_WDT3,
++    CSU_CSLX_ESDHC2 = 80,
+       CSU_CSLX_WDT5 = 81,
++      CSU_CSLX_SAI2,
++      CSU_CSLX_SAI1,
++      CSU_CSLX_SAI4,
++      CSU_CSLX_SAI3,
+       CSU_CSLX_FTM2 = 86,
+       CSU_CSLX_FTM1,
+       CSU_CSLX_FTM4,
+@@ -143,7 +148,12 @@ static struct csu_ns_dev ns_dev[] = {
+        {CSU_CSLX_IIC4, CSU_ALL_RW},
+        {CSU_CSLX_WDT4, CSU_ALL_RW},
+        {CSU_CSLX_WDT3, CSU_ALL_RW},
++     {CSU_CSLX_ESDHC2, CSU_ALL_RW},
+        {CSU_CSLX_WDT5, CSU_ALL_RW},
++       {CSU_CSLX_SAI2, CSU_ALL_RW},
++       {CSU_CSLX_SAI1, CSU_ALL_RW},
++       {CSU_CSLX_SAI4, CSU_ALL_RW},
++       {CSU_CSLX_SAI3, CSU_ALL_RW},
+        {CSU_CSLX_FTM2, CSU_ALL_RW},
+        {CSU_CSLX_FTM1, CSU_ALL_RW},
+        {CSU_CSLX_FTM4, CSU_ALL_RW},
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0020-armv8-ls1012a-Update-DDR-init-sequence.patch b/package/boot/uboot-layerscape/patches/0020-armv8-ls1012a-Update-DDR-init-sequence.patch
new file mode 100644 (file)
index 0000000..78a3ba4
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0020-armv8-ls1012a-Update-DDR-init-sequence.patch
@@ -0,0 +1,280 @@
+From e8703a5bba4bc0e9fa6aefe0eae7caf9141b8bdc Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Mon, 2 May 2016 18:28:16 +0530
+Subject: [PATCH 20/93] armv8: ls1012a: Update DDR init sequence
+
+Current DDR init code uses lots of delay.
+
+Use wait for bit clear instead of delays.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ board/freescale/ls1012aqds/ls1012aqds.c |   67 +++++++++++++++++--------------
+ board/freescale/ls1012ardb/ls1012ardb.c |   54 +++++++++++--------------
+ 2 files changed, 60 insertions(+), 61 deletions(-)
+
+diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
+index 6d5fef8..5cb225f 100644
+--- a/board/freescale/ls1012aqds/ls1012aqds.c
++++ b/board/freescale/ls1012aqds/ls1012aqds.c
+@@ -28,6 +28,20 @@
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
++static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
++{
++      int timeout = 1000;
++
++      out_be32(ptr, value);
++
++      while (in_be32(ptr) & bits) {
++              udelay(100);
++              timeout--;
++      }
++      if (timeout <= 0)
++              puts("Error: wait for clear timeout.\n");
++}
++
+ int checkboard(void)
+ {
+       puts("Board: LS1012AQDS\n");
+@@ -44,7 +58,7 @@ void mmdc_init(void)
+       out_be32(&mmdc->mdscr, 0x00008000);
+ 
+       /* configure timing parms */
+-      out_be32(&mmdc->mdotc, 0x12554000);
++      out_be32(&mmdc->mdotc,  0x12554000);
+       out_be32(&mmdc->mdcfg0, 0xbabf7954);
+       out_be32(&mmdc->mdcfg1, 0xff328f64);
+       out_be32(&mmdc->mdcfg2, 0x01ff00db);
+@@ -56,7 +70,7 @@ void mmdc_init(void)
+       out_be32(&mmdc->mpodtctrl, 0x0000022a);
+ 
+       /* out of reset delays */
+-      out_be32(&mmdc->mdor, 0x00bf1023);
++      out_be32(&mmdc->mdor,  0x00bf1023);
+ 
+       /* physical parms */
+       out_be32(&mmdc->mdctl, 0x05180000);
+@@ -73,69 +87,60 @@ void mmdc_init(void)
+ 
+       /* dram init sequence: ZQCL */
+       out_be32(&mmdc->mdscr,      0x04008040);
+-      out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
+-
+-      mdelay(100);
++      set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
+ 
+       /* Calibrations now: wr lvl */
+       out_be32(&mmdc->mdscr,   0x00848031);
+       out_be32(&mmdc->mdscr,   0x00008200);
+-      out_be32(&mmdc->mpwlgcr, 0x00000001);
++      set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
+ 
+-      mdelay(100);
++      mdelay(1);
+ 
+       out_be32(&mmdc->mdscr, 0x00048031);
+       out_be32(&mmdc->mdscr, 0x00008000);
+ 
+-      /*    manual_refresh */
+-      out_be32(&mmdc->mdscr, 0x00008020);
+-
+-      mdelay(100);
++      mdelay(1);
+ 
+       /* Calibrations now: Read DQS gating calibration */
+       out_be32(&mmdc->mdscr,     0x04008050);
+       out_be32(&mmdc->mdscr,     0x00048033);
+       out_be32(&mmdc->mppdcmpr2, 0x00000001);
+       out_be32(&mmdc->mprddlctl, 0x40404040);
+-      out_be32(&mmdc->mpdgctrl0, 0x10000000);
+-
+-      mdelay(100);
++      set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
+ 
+       out_be32(&mmdc->mdscr, 0x00008033);
+ 
+-      /*   manual_refresh */
+-      out_be32(&mmdc->mdscr, 0x00008020);
+-
+-      mdelay(100);
+ 
+       /* Calibrations now: Read calibration */
+       out_be32(&mmdc->mdscr,       0x04008050);
+       out_be32(&mmdc->mdscr,       0x00048033);
+       out_be32(&mmdc->mppdcmpr2,   0x00000001);
+-      out_be32(&mmdc->mprddlhwctl, 0x00000010);
+-
+-      mdelay(400);
++      set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
+ 
+       out_be32(&mmdc->mdscr, 0x00008033);
+ 
+-      /* manual_refresh */
+-      out_be32(&mmdc->mdscr, 0x00008020);
+-
+-      mdelay(100);
+-
+       /* PD, SR */
+       out_be32(&mmdc->mdpdc, 0x00030035);
+       out_be32(&mmdc->mapsr, 0x00001067);
+ 
+       /* refresh scheme */
+-      out_be32(&mmdc->mdref, 0x103e8000);
+-
+-      mdelay(400);
++      set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
+ 
+       /* disable CON_REQ */
+       out_be32(&mmdc->mdscr, 0x0);
++}
+ 
+-      mdelay(50);
++int select_i2c_ch_pca9547(u8 ch)
++{
++      int ret;
++
++      ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
++      if (ret) {
++              puts("PCA: failed to select proper channel\n");
++              return ret;
++      }
++
++      return 0;
+ }
+ 
+ int dram_init(void)
+@@ -183,6 +188,8 @@ int board_init(void)
+ #ifdef CONFIG_ENV_IS_NOWHERE
+       gd->env_addr = (ulong)&default_environment[0];
+ #endif
++      select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
++
+       return 0;
+ }
+ 
+diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
+index 4a7aaaa..f7b9bce 100644
+--- a/board/freescale/ls1012ardb/ls1012ardb.c
++++ b/board/freescale/ls1012ardb/ls1012ardb.c
+@@ -23,6 +23,20 @@
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
++static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
++{
++      int timeout = 1000;
++
++      out_be32(ptr, value);
++
++      while (in_be32(ptr) & bits) {
++              udelay(100);
++              timeout--;
++      }
++      if (timeout <= 0)
++              puts("Error: wait for clear timeout.\n");
++}
++
+ int checkboard(void)
+ {
+       u8 in1;
+@@ -67,7 +81,7 @@ void mmdc_init(void)
+       out_be32(&mmdc->mdscr, 0x00008000);
+ 
+       /* configure timing parms */
+-      out_be32(&mmdc->mdotc, 0x12554000);
++      out_be32(&mmdc->mdotc,  0x12554000);
+       out_be32(&mmdc->mdcfg0, 0xbabf7954);
+       out_be32(&mmdc->mdcfg1, 0xff328f64);
+       out_be32(&mmdc->mdcfg2, 0x01ff00db);
+@@ -79,7 +93,7 @@ void mmdc_init(void)
+       out_be32(&mmdc->mpodtctrl, 0x0000022a);
+ 
+       /* out of reset delays */
+-      out_be32(&mmdc->mdor, 0x00bf1023);
++      out_be32(&mmdc->mdor,  0x00bf1023);
+ 
+       /* physical parms */
+       out_be32(&mmdc->mdctl, 0x05180000);
+@@ -96,69 +110,47 @@ void mmdc_init(void)
+ 
+       /* dram init sequence: ZQCL */
+       out_be32(&mmdc->mdscr,      0x04008040);
+-      out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
+-
+-      mdelay(100);
++      set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
+ 
+       /* Calibrations now: wr lvl */
+       out_be32(&mmdc->mdscr,   0x00848031);
+       out_be32(&mmdc->mdscr,   0x00008200);
+-      out_be32(&mmdc->mpwlgcr, 0x00000001);
++      set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
+ 
+-      mdelay(100);
++      mdelay(1);
+ 
+       out_be32(&mmdc->mdscr, 0x00048031);
+       out_be32(&mmdc->mdscr, 0x00008000);
+ 
+-      /*    manual_refresh */
+-      out_be32(&mmdc->mdscr, 0x00008020);
+-
+-      mdelay(100);
++      mdelay(1);
+ 
+       /* Calibrations now: Read DQS gating calibration */
+       out_be32(&mmdc->mdscr,     0x04008050);
+       out_be32(&mmdc->mdscr,     0x00048033);
+       out_be32(&mmdc->mppdcmpr2, 0x00000001);
+       out_be32(&mmdc->mprddlctl, 0x40404040);
+-      out_be32(&mmdc->mpdgctrl0, 0x10000000);
+-
+-      mdelay(100);
++      set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
+ 
+       out_be32(&mmdc->mdscr, 0x00008033);
+ 
+-      /*   manual_refresh */
+-      out_be32(&mmdc->mdscr, 0x00008020);
+-
+-      mdelay(100);
+ 
+       /* Calibrations now: Read calibration */
+       out_be32(&mmdc->mdscr,       0x04008050);
+       out_be32(&mmdc->mdscr,       0x00048033);
+       out_be32(&mmdc->mppdcmpr2,   0x00000001);
+-      out_be32(&mmdc->mprddlhwctl, 0x00000010);
+-
+-      mdelay(400);
++      set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
+ 
+       out_be32(&mmdc->mdscr, 0x00008033);
+ 
+-      /* manual_refresh */
+-      out_be32(&mmdc->mdscr, 0x00008020);
+-
+-      mdelay(100);
+-
+       /* PD, SR */
+       out_be32(&mmdc->mdpdc, 0x00030035);
+       out_be32(&mmdc->mapsr, 0x00001067);
+ 
+       /* refresh scheme */
+-      out_be32(&mmdc->mdref, 0x103e8000);
+-
+-      mdelay(400);
++      set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
+ 
+       /* disable CON_REQ */
+       out_be32(&mmdc->mdscr, 0x0);
+-
+-      mdelay(50);
+ }
+ 
+ int dram_init(void)
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0021-sf-set-the-Uniform-Sector-to-CR3NV-instead-of-CR3V.patch b/package/boot/uboot-layerscape/patches/0021-sf-set-the-Uniform-Sector-to-CR3NV-instead-of-CR3V.patch
new file mode 100644 (file)
index 0000000..079995d
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0021-sf-set-the-Uniform-Sector-to-CR3NV-instead-of-CR3V.patch
@@ -0,0 +1,26 @@
+From 90ded6778736d5a0843d24eb8e5a47db72c05af9 Mon Sep 17 00:00:00 2001
+From: Mingkai Hu <mingkai.hu@nxp.com>
+Date: Mon, 18 Apr 2016 22:44:21 +0800
+Subject: [PATCH 21/93] sf: set the Uniform Sector to CR3NV instead of CR3V
+
+Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
+---
+ drivers/mtd/spi/spi_flash.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
+index 865e929..97e53c7 100644
+--- a/drivers/mtd/spi/spi_flash.c
++++ b/drivers/mtd/spi/spi_flash.c
+@@ -942,7 +942,7 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
+ static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
+ {
+       u8 cmd[4];
+-      u32 offset = 0x800004; /* CR3V register offset */
++      u32 offset = 0x000004; /* CR3NV register offset */
+       u8 cr3v;
+       int ret;
+ 
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0022-include-usb-Rename-USB-controller-base-address-mappi.patch b/package/boot/uboot-layerscape/patches/0022-include-usb-Rename-USB-controller-base-address-mappi.patch
new file mode 100644 (file)
index 0000000..b4d1634
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0022-include-usb-Rename-USB-controller-base-address-mappi.patch
@@ -0,0 +1,124 @@
+From 46c9963880e5cba6390864477f19b25369c6c944 Mon Sep 17 00:00:00 2001
+From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Date: Thu, 5 May 2016 15:01:02 +0530
+Subject: [PATCH 22/93] include: usb: Rename USB controller base address
+ mapping
+
+[context adjustment]
+
+Remove Soc specific defines and use generic chasis specific defines
+for USB controller base address mapping.
+
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |    6 +++---
+ .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |    4 ++--
+ arch/arm/include/asm/arch-ls102xa/config.h         |    6 ++----
+ include/linux/usb/xhci-fsl.h                       |   20 ++++++++------------
+ include/usb/ehci-fsl.h                             |    2 +-
+ 5 files changed, 16 insertions(+), 22 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index 414a222..3e37f00 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -33,9 +33,9 @@
+ #define CONFIG_SYS_NS16550_COM2                       (CONFIG_SYS_IMMR + 0x011c0600)
+ #define CONFIG_SYS_NS16550_COM3                       (CONFIG_SYS_IMMR + 0x011d0500)
+ #define CONFIG_SYS_NS16550_COM4                       (CONFIG_SYS_IMMR + 0x011d0600)
+-#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR     (CONFIG_SYS_IMMR + 0x01f00000)
+-#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR     (CONFIG_SYS_IMMR + 0x02000000)
+-#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR     (CONFIG_SYS_IMMR + 0x02100000)
++#define CONFIG_SYS_XHCI_USB1_ADDR             (CONFIG_SYS_IMMR + 0x01f00000)
++#define CONFIG_SYS_XHCI_USB2_ADDR             (CONFIG_SYS_IMMR + 0x02000000)
++#define CONFIG_SYS_XHCI_USB3_ADDR             (CONFIG_SYS_IMMR + 0x02100000)
+ #define CONFIG_SYS_PCIE1_ADDR                 (CONFIG_SYS_IMMR + 0x2400000)
+ #define CONFIG_SYS_PCIE2_ADDR                 (CONFIG_SYS_IMMR + 0x2500000)
+ #define CONFIG_SYS_PCIE3_ADDR                 (CONFIG_SYS_IMMR + 0x2600000)
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+index 0ab709c..cf1f37a 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+@@ -51,8 +51,8 @@
+ #define I2C3_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x01020000)
+ #define I2C4_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x01030000)
+ 
+-#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR     (CONFIG_SYS_IMMR + 0x02100000)
+-#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR     (CONFIG_SYS_IMMR + 0x02110000)
++#define CONFIG_SYS_XHCI_USB1_ADDR             (CONFIG_SYS_IMMR + 0x02100000)
++#define CONFIG_SYS_XHCI_USB2_ADDR             (CONFIG_SYS_IMMR + 0x02110000)
+ 
+ /* TZ Address Space Controller Definitions */
+ #define TZASC1_BASE                   0x01100000      /* as per CCSR map. */
+diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
+index 926ac58..05fff80 100644
+--- a/arch/arm/include/asm/arch-ls102xa/config.h
++++ b/arch/arm/include/asm/arch-ls102xa/config.h
+@@ -36,13 +36,11 @@
+ #define CONFIG_SYS_NS16550_COM1                       (CONFIG_SYS_IMMR + 0x011c0500)
+ #define CONFIG_SYS_NS16550_COM2                       (CONFIG_SYS_IMMR + 0x011d0500)
+ #define CONFIG_SYS_DCU_ADDR                   (CONFIG_SYS_IMMR + 0x01ce0000)
+-#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR     (CONFIG_SYS_IMMR + 0x02100000)
+-#define CONFIG_SYS_LS102XA_USB1_ADDR \
+-      (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
++#define CONFIG_SYS_XHCI_USB1_ADDR             (CONFIG_SYS_IMMR + 0x02100000)
++#define CONFIG_SYS_EHCI_USB1_ADDR             (CONFIG_SYS_IMMR + 0x07600000)
+ 
+ #define CONFIG_SYS_FSL_SEC_OFFSET             0x00700000
+ #define CONFIG_SYS_FSL_JR0_OFFSET             0x00710000
+-#define CONFIG_SYS_LS102XA_USB1_OFFSET                0x07600000
+ #define CONFIG_SYS_TSEC1_OFFSET                       0x01d10000
+ #define CONFIG_SYS_TSEC2_OFFSET                       0x01d50000
+ #define CONFIG_SYS_TSEC3_OFFSET                       0x01d90000
+diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
+index 7ab88c3..b2b3264 100644
+--- a/include/linux/usb/xhci-fsl.h
++++ b/include/linux/usb/xhci-fsl.h
+@@ -54,22 +54,18 @@ struct fsl_xhci {
+       struct dwc3 *dwc3_reg;
+ };
+ 
+-#if defined(CONFIG_LS102XA)
+-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
++#if defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A)
++#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+ #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+ #elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
+-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
+-#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+-#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
+-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
+-#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
+-#elif defined(CONFIG_LS1012A)
+-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
++#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
++#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
++#elif defined(CONFIG_LS1043A)
++#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
++#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
++#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR
+ #endif
+ 
+ #define FSL_USB_XHCI_ADDR     {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
+diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
+index e9349b5..b8d78d0 100644
+--- a/include/usb/ehci-fsl.h
++++ b/include/usb/ehci-fsl.h
+@@ -164,7 +164,7 @@
+ #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
+ #define CONFIG_SYS_FSL_USB2_ADDR      0
+ #elif defined(CONFIG_LS102XA)
+-#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
++#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
+ #define CONFIG_SYS_FSL_USB2_ADDR        0
+ #endif
+ 
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0023-drivers-usb-fsl-add-USB-ULPI-init-code.patch b/package/boot/uboot-layerscape/patches/0023-drivers-usb-fsl-add-USB-ULPI-init-code.patch
new file mode 100644 (file)
index 0000000..61b445d
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0023-drivers-usb-fsl-add-USB-ULPI-init-code.patch
@@ -0,0 +1,65 @@
+From 271adb5c0546b080fb350a41520c600a16739f1a Mon Sep 17 00:00:00 2001
+From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Date: Fri, 6 May 2016 09:05:29 +0530
+Subject: [PATCH 23/93] drivers: usb: fsl: add USB ULPI init code
+
+This adds the required code to set up a ULPI USB port, for
+new NXP USB PHY used in QorIQ platforms.
+
+To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT
+have to be set in the board configuration file.
+
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+---
+ drivers/usb/host/ehci-fsl.c |   21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
+index 97b7f14..3f06345 100644
+--- a/drivers/usb/host/ehci-fsl.c
++++ b/drivers/usb/host/ehci-fsl.c
+@@ -16,6 +16,9 @@
+ #include <hwconfig.h>
+ #include <fsl_usb.h>
+ #include <fdt_support.h>
++#ifdef CONFIG_USB_ULPI
++#include <usb/ulpi.h>
++#endif
+ 
+ #include "ehci.h"
+ 
+@@ -50,6 +53,10 @@ int ehci_hcd_init(int index, enum usb_init_type init,
+       const char *phy_type = NULL;
+       size_t len;
+       char current_usb_controller[5];
++#ifdef CONFIG_USB_ULPI
++      int ret;
++      struct ulpi_viewport ulpi_vp;
++#endif
+ #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+       char usb_phy[5];
+ 
+@@ -126,6 +133,20 @@ int ehci_hcd_init(int index, enum usb_init_type init,
+               udelay(1000); /* delay required for PHY Clk to appear */
+               if (!usb_phy_clk_valid(ehci))
+                       return -EINVAL;
++
++#ifdef CONFIG_USB_ULPI
++              ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
++              ulpi_vp.port_num = 0;
++
++              ret = ulpi_init(&ulpi_vp);
++              if (ret) {
++                      puts("NXP ULPI viewport init failed\n");
++                      return -1;
++              }
++
++              ulpi_set_vbus(&ulpi_vp, 1, 1);
++              ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 1);
++#endif
+               out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
+       }
+ 
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0024-config-ls1012aqds-Add-USB-EHCI-support-for-ls1012aqd.patch b/package/boot/uboot-layerscape/patches/0024-config-ls1012aqds-Add-USB-EHCI-support-for-ls1012aqd.patch
new file mode 100644 (file)
index 0000000..4277f15
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0024-config-ls1012aqds-Add-USB-EHCI-support-for-ls1012aqd.patch
@@ -0,0 +1,67 @@
+From dec7ec15a9c2f2c3e0a09bb9cda8a24e4d469242 Mon Sep 17 00:00:00 2001
+From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Date: Fri, 6 May 2016 09:09:32 +0530
+Subject: [PATCH 24/93] config: ls1012aqds: Add USB EHCI support for
+ ls1012aqds
+
+Add USB EHCI support for ls1012aqds platform
+
+Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+---
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |    1 +
+ include/configs/ls1012aqds.h                       |    5 +++++
+ include/usb/ehci-fsl.h                             |    2 +-
+ 3 files changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index 3e37f00..24add1a 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -36,6 +36,7 @@
+ #define CONFIG_SYS_XHCI_USB1_ADDR             (CONFIG_SYS_IMMR + 0x01f00000)
+ #define CONFIG_SYS_XHCI_USB2_ADDR             (CONFIG_SYS_IMMR + 0x02000000)
+ #define CONFIG_SYS_XHCI_USB3_ADDR             (CONFIG_SYS_IMMR + 0x02100000)
++#define CONFIG_SYS_EHCI_USB1_ADDR             (CONFIG_SYS_IMMR + 0x07600000)
+ #define CONFIG_SYS_PCIE1_ADDR                 (CONFIG_SYS_IMMR + 0x2400000)
+ #define CONFIG_SYS_PCIE2_ADDR                 (CONFIG_SYS_IMMR + 0x2500000)
+ #define CONFIG_SYS_PCIE3_ADDR                 (CONFIG_SYS_IMMR + 0x2600000)
+diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
+index bb433de..51ca902 100644
+--- a/include/configs/ls1012aqds.h
++++ b/include/configs/ls1012aqds.h
+@@ -109,6 +109,8 @@
+ #ifdef CONFIG_HAS_FSL_DR_USB
+ #define CONFIG_USB_EHCI
+ #define CONFIG_USB_EHCI_FSL
++#define CONFIG_USB_ULPI
++#define CONFIG_USB_ULPI_VIEWPORT
+ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+ #endif
+ 
+@@ -121,6 +123,9 @@
+ #define CONFIG_USB_XHCI_DWC3
+ #define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+ #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
++#endif
++
++#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
+ #define CONFIG_CMD_USB
+ #define CONFIG_USB_STORAGE
+ #define CONFIG_CMD_EXT2
+diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
+index b8d78d0..94b1efa 100644
+--- a/include/usb/ehci-fsl.h
++++ b/include/usb/ehci-fsl.h
+@@ -163,7 +163,7 @@
+ #elif defined(CONFIG_MPC512X)
+ #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
+ #define CONFIG_SYS_FSL_USB2_ADDR      0
+-#elif defined(CONFIG_LS102XA)
++#elif defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A)
+ #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
+ #define CONFIG_SYS_FSL_USB2_ADDR        0
+ #endif
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0025-armv8-ls1012ardb-Add-qspi-SECURE-BOOT-target.patch b/package/boot/uboot-layerscape/patches/0025-armv8-ls1012ardb-Add-qspi-SECURE-BOOT-target.patch
new file mode 100644 (file)
index 0000000..e42e51e
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0025-armv8-ls1012ardb-Add-qspi-SECURE-BOOT-target.patch
@@ -0,0 +1,115 @@
+From 93a1095c7da7291ffb12116de9122d431b9f6113 Mon Sep 17 00:00:00 2001
+From: Sumit Garg <sumit.garg@nxp.com>
+Date: Fri, 6 May 2016 11:11:58 -0400
+Subject: [PATCH 25/93] armv8: ls1012ardb: Add qspi SECURE BOOT target
+
+Add qspi SECURE BOOT target to enable chain of trust. Also enable
+sec_init in boot sequence.
+
+Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
+Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
+---
+ arch/arm/include/asm/arch-fsl-layerscape/config.h |    7 +++++++
+ arch/arm/include/asm/fsl_secure_boot.h            |    7 ++++++-
+ board/freescale/ls1012ardb/ls1012ardb.c           |    5 +++++
+ configs/ls1012ardb_qspi_SECURE_BOOT_defconfig     |   10 ++++++++++
+ include/configs/ls1012ardb.h                      |    2 ++
+ 5 files changed, 30 insertions(+), 1 deletion(-)
+ create mode 100644 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
+index 6ea4e8e..679be6c 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
+@@ -237,6 +237,13 @@
+ 
+ #define CONFIG_SYS_FSL_ERRATUM_A009798
+ 
++#define CONFIG_SYS_FSL_SFP_VER_3_2
++#define CONFIG_SYS_FSL_SEC_MON_BE
++#define CONFIG_SYS_FSL_SEC_BE
++#define CONFIG_SYS_FSL_SFP_BE
++#define CONFIG_SYS_FSL_SRK_LE
++#define CONFIG_KEY_REVOCATION
++
+ #else
+ #error SoC not defined
+ #endif
+diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
+index c7f8b3e..c973255 100644
+--- a/arch/arm/include/asm/fsl_secure_boot.h
++++ b/arch/arm/include/asm/fsl_secure_boot.h
+@@ -50,7 +50,7 @@
+ #endif
+ 
+ #if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\
+-      defined(CONFIG_LS2085A)
++      defined(CONFIG_LS2085A) || defined(CONFIG_LS1012A)
+ /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
+  * Similiarly for LS2080 and LS2085
+  */
+@@ -81,6 +81,11 @@
+ #define CONFIG_BS_ADDR_FLASH          0x583900000
+ #define CONFIG_BS_HDR_ADDR_RAM                0xa3920000
+ #define CONFIG_BS_ADDR_RAM            0xa3900000
++#elif defined(CONFIG_LS1012A)
++#define CONFIG_BS_HDR_ADDR_FLASH      0x400c0000
++#define CONFIG_BS_ADDR_FLASH          0x40060000
++#define CONFIG_BS_HDR_ADDR_RAM                0xa0060000
++#define CONFIG_BS_ADDR_RAM            0xa0060000
+ #else
+ #define CONFIG_BS_HDR_ADDR_FLASH      0x600a0000
+ #define CONFIG_BS_ADDR_FLASH          0x60060000
+diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
+index f7b9bce..347b8c8 100644
+--- a/board/freescale/ls1012ardb/ls1012ardb.c
++++ b/board/freescale/ls1012ardb/ls1012ardb.c
+@@ -20,6 +20,7 @@
+ #include <environment.h>
+ #include <fsl_mmdc.h>
+ #include <netdev.h>
++#include <fsl_sec.h>
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
+@@ -191,6 +192,10 @@ int board_init(void)
+       enable_layerscape_ns_access();
+ #endif
+ 
++#ifdef CONFIG_FSL_CAAM
++      sec_init();
++#endif
++
+       return 0;
+ }
+ 
+diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+new file mode 100644
+index 0000000..92a95a8
+--- /dev/null
++++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+@@ -0,0 +1,10 @@
++CONFIG_ARM=y
++CONFIG_TARGET_LS1012ARDB=y
++CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,SECURE_BOOT"
++# CONFIG_CMD_IMLS is not set
++CONFIG_SYS_NS16550=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
++CONFIG_OF_CONTROL=y
++CONFIG_DM=y
++CONFIG_SPI_FLASH=y
++CONFIG_DM_SPI=y
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index af3d33f..b40e02b 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -73,4 +73,6 @@
+ #define CONFIG_SYS_MEMTEST_START      0x80000000
+ #define CONFIG_SYS_MEMTEST_END                0x9fffffff
+ 
++#define CONFIG_FSL_CAAM                       /* Enable CAAM */
++
+ #endif /* __LS1012ARDB_H__ */
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0026-fsl-qixis-conditionally-compile-IFC-based-qixis-func.patch b/package/boot/uboot-layerscape/patches/0026-fsl-qixis-conditionally-compile-IFC-based-qixis-func.patch
new file mode 100644 (file)
index 0000000..3d49a2f
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0026-fsl-qixis-conditionally-compile-IFC-based-qixis-func.patch
@@ -0,0 +1,38 @@
+From d99349711fa42b3e401bf9a71e315440b8ed2c17 Mon Sep 17 00:00:00 2001
+From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Date: Tue, 10 May 2016 09:21:35 +0530
+Subject: [PATCH 26/93] fsl, qixis: conditionally compile IFC based qixis
+ functions
+
+Check if qixis supports memory-mapped read/write
+before compiling IFC based qixis read/write functions.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+---
+ board/freescale/common/qixis.c |    2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
+index 113295f..2e35d41 100644
+--- a/board/freescale/common/qixis.c
++++ b/board/freescale/common/qixis.c
+@@ -27,6 +27,7 @@ void qixis_write_i2c(unsigned int reg, u8 value)
+ }
+ #endif
+ 
++#ifdef QIXIS_BASE
+ u8 qixis_read(unsigned int reg)
+ {
+       void *p = (void *)QIXIS_BASE;
+@@ -40,6 +41,7 @@ void qixis_write(unsigned int reg, u8 value)
+ 
+       out_8(p + reg, value);
+ }
++#endif
+ 
+ u16 qixis_read_minor(void)
+ {
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0027-fsl-qixis-Add-flag-for-LBMAP-brdcfg-reg-offset.patch b/package/boot/uboot-layerscape/patches/0027-fsl-qixis-Add-flag-for-LBMAP-brdcfg-reg-offset.patch
new file mode 100644 (file)
index 0000000..a002e1c
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0027-fsl-qixis-Add-flag-for-LBMAP-brdcfg-reg-offset.patch
@@ -0,0 +1,48 @@
+From 34a472a20695cbd6ab1bc2d0686c6f324d8e0d6c Mon Sep 17 00:00:00 2001
+From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Date: Tue, 10 May 2016 09:38:46 +0530
+Subject: [PATCH 27/93] fsl, qixis: Add flag for LBMAP brdcfg reg offset
+
+Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP
+configuration register instead of hardcoding it in
+set_lbmap() function.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+---
+ board/freescale/common/qixis.c |   11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
+index 2e35d41..0db0ed6 100644
+--- a/board/freescale/common/qixis.c
++++ b/board/freescale/common/qixis.c
+@@ -14,6 +14,13 @@
+ #include <i2c.h>
+ #include "qixis.h"
+ 
++#ifndef QIXIS_LBMAP_BRDCFG_REG
++/*
++ * For consistency with existing platforms
++ */
++#define QIXIS_LBMAP_BRDCFG_REG 0x00
++#endif
++
+ #ifdef CONFIG_SYS_I2C_FPGA_ADDR
+ u8 qixis_read_i2c(unsigned int reg)
+ {
+@@ -144,9 +151,9 @@ static void __maybe_unused set_lbmap(int lbmap)
+ {
+       u8 reg;
+ 
+-      reg = QIXIS_READ(brdcfg[0]);
++      reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
+       reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
+-      QIXIS_WRITE(brdcfg[0], reg);
++      QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
+ }
+ 
+ static void __maybe_unused set_rcw_src(int rcw_src)
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0028-fsl-ls1012a-qixis-Add-support-for-qixis-subsystem.patch b/package/boot/uboot-layerscape/patches/0028-fsl-ls1012a-qixis-Add-support-for-qixis-subsystem.patch
new file mode 100644 (file)
index 0000000..0604685
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0028-fsl-ls1012a-qixis-Add-support-for-qixis-subsystem.patch
@@ -0,0 +1,80 @@
+From 4fcb1d5141ff6d9527ceac9f391e1da4128f5a60 Mon Sep 17 00:00:00 2001
+From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Date: Tue, 10 May 2016 09:54:36 +0530
+Subject: [PATCH 28/93] fsl, ls1012a, qixis: Add support for qixis subsystem
+
+Add support for the printing FPGA build information,
+altbank switching and board reset using qixis subsystem.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+---
+ board/freescale/ls1012aqds/ls1012aqds.c |   20 +++++++++++++++++++-
+ include/configs/ls1012aqds.h            |   17 +++++++++++++++++
+ 2 files changed, 36 insertions(+), 1 deletion(-)
+
+diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
+index 5cb225f..446989b 100644
+--- a/board/freescale/ls1012aqds/ls1012aqds.c
++++ b/board/freescale/ls1012aqds/ls1012aqds.c
+@@ -44,8 +44,26 @@ static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+ 
+ int checkboard(void)
+ {
+-      puts("Board: LS1012AQDS\n");
++      char buf[64];
++      u8 sw;
+ 
++      sw = QIXIS_READ(arch);
++      printf("Board Arch: V%d, ", sw >> 4);
++      printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
++
++      sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
++
++      if (sw & QIXIS_LBMAP_ALTBANK)
++              printf("flash: 2\n");
++      else
++              printf("flash: 1\n");
++
++      printf("FPGA: v%d (%s), build %d",
++                      (int)QIXIS_READ(scver), qixis_read_tag(buf),
++                      (int)qixis_read_minor());
++
++      /* the timestamp string contains "\n" at the end */
++      printf(" on %s", qixis_read_time(buf));
+       return 0;
+ }
+ 
+diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
+index 51ca902..de998b8 100644
+--- a/include/configs/ls1012aqds.h
++++ b/include/configs/ls1012aqds.h
+@@ -26,8 +26,25 @@
+ #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+ #endif
+ 
++/*
++ * QIXIS Definitions
++ */
++#define CONFIG_FSL_QIXIS
++
++#ifdef CONFIG_FSL_QIXIS
+ #define CONFIG_QIXIS_I2C_ACCESS
+ #define CONFIG_SYS_I2C_FPGA_ADDR      0x66
++#define QIXIS_LBMAP_BRDCFG_REG                0x04
++#define QIXIS_LBMAP_SWITCH            6
++#define QIXIS_LBMAP_MASK              0xf7
++#define QIXIS_LBMAP_SHIFT             0
++#define QIXIS_LBMAP_DFLTBANK          0x00
++#define QIXIS_LBMAP_ALTBANK           0x08
++#define QIXIS_RST_CTL_RESET           0x41
++#define QIXIS_RCFG_CTL_RECONFIG_IDLE  0x20
++#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
++#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
++#endif
+ 
+ /*
+  * I2C bus multiplexer
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0029-armv8-ls1012a-Added-CSU-assignment-for-USB2.patch b/package/boot/uboot-layerscape/patches/0029-armv8-ls1012a-Added-CSU-assignment-for-USB2.patch
new file mode 100644 (file)
index 0000000..228e762
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0029-armv8-ls1012a-Added-CSU-assignment-for-USB2.patch
@@ -0,0 +1,37 @@
+From 57700b94f9111578d0fc05bb8f273c0b29951572 Mon Sep 17 00:00:00 2001
+From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Date: Wed, 11 May 2016 14:59:39 +0530
+Subject: [PATCH 29/93] armv8: ls1012a: Added CSU assignment for USB2
+
+Access settings for USB2 IP is added through CSU register.
+
+Added CSU ID for USB2, reg: CSL23_REG[8:0]
+
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+---
+ .../include/asm/arch-fsl-layerscape/ns_access.h    |    2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+index d6642a7..2fd33e1 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+@@ -38,6 +38,7 @@ enum csu_cslx_ind {
+       CSU_CSLX_ESDHC,
+       CSU_CSLX_IFC = 45,
+       CSU_CSLX_I2C1,
++      CSU_CSLX_USB_2,
+       CSU_CSLX_I2C3 = 48,
+       CSU_CSLX_I2C2,
+       CSU_CSLX_DUART2 = 50,
+@@ -117,6 +118,7 @@ static struct csu_ns_dev ns_dev[] = {
+        {CSU_CSLX_ESDHC, CSU_ALL_RW},
+        {CSU_CSLX_IFC, CSU_ALL_RW},
+        {CSU_CSLX_I2C1, CSU_ALL_RW},
++       {CSU_CSLX_USB_2, CSU_ALL_RW},
+        {CSU_CSLX_I2C3, CSU_ALL_RW},
+        {CSU_CSLX_I2C2, CSU_ALL_RW},
+        {CSU_CSLX_DUART2, CSU_ALL_RW},
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch b/package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch
new file mode 100644 (file)
index 0000000..33ea668
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch
@@ -0,0 +1,32 @@
+From 367c16da9255dacf6440f3c72c01c197cfb1bbe8 Mon Sep 17 00:00:00 2001
+From: Sumit Garg <sumit.garg@nxp.com>
+Date: Wed, 11 May 2016 12:44:35 -0400
+Subject: [PATCH 30/93] ARMv8: Enable CPUECTLR.SMPEN for data coherency
+
+Data coherency is enabled only when the CPUECTLR.SMPEN bit is set.
+The SMPEN bit should be set before enabling the data cache. If not
+enabled, the cache is not coherent with other cores and data
+corruption could occur. It also enables core level cache snooping.
+
+Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
+---
+ arch/arm/cpu/armv8/start.S |    3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
+index 235213f..9703f6b 100644
+--- a/arch/arm/cpu/armv8/start.S
++++ b/arch/arm/cpu/armv8/start.S
+@@ -70,6 +70,9 @@ reset:
+       mov     x0, #3 << 20
+       msr     cpacr_el1, x0                   /* Enable FP/SIMD */
+ 0:
++      /* Enalbe SMPEN bit */
++      mov     x0, #0x40
++      msr     s3_1_c15_c2_1, x0
+ 
+       /* Apply ARM core specific erratas */
+       bl      apply_core_errata
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0031-mtd-sf-add-exceed-flash-16MB-support-for-qspi.patch b/package/boot/uboot-layerscape/patches/0031-mtd-sf-add-exceed-flash-16MB-support-for-qspi.patch
new file mode 100644 (file)
index 0000000..aa39699
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0031-mtd-sf-add-exceed-flash-16MB-support-for-qspi.patch
@@ -0,0 +1,308 @@
+From 6cfe5c5e7f6a4b3d46f65967fe10820ee2e3d2fa Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Fri, 13 May 2016 16:30:33 +0800
+Subject: [PATCH 31/93] mtd: sf: add exceed flash 16MB support for qspi
+
+spi/spi_flash.c: The flash S25FS512S cannot legacy commands
+such as Bank Address Related Command, So we need add the exceed
+16MB suuport. So we extend the cmd[] size to support 32-bit address,
+what's more, as to spi/fsl_qspi.c need to a flag to pionts the address
+mask, So add the magic num '0xaa' into cmd[].
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ arch/arm/dts/fsl-ls1012a.dtsi    |    2 +-
+ drivers/mtd/spi/sf_internal.h    |    7 ++++
+ drivers/mtd/spi/spi_flash.c      |   73 ++++++++++++++++++++++++++++++--------
+ drivers/spi/fsl_qspi.c           |   30 ++++++++++++++--
+ include/configs/ls1012a_common.h |    3 +-
+ 5 files changed, 95 insertions(+), 20 deletions(-)
+
+diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
+index 87a287a..2549c91 100644
+--- a/arch/arm/dts/fsl-ls1012a.dtsi
++++ b/arch/arm/dts/fsl-ls1012a.dtsi
+@@ -108,7 +108,7 @@
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x1550000 0x0 0x10000>,
+-                              <0x0 0x40000000 0x0 0x4000000>;
++                              <0x0 0x40000000 0x0 0x8000000>;
+                       reg-names = "QuadSPI", "QuadSPI-memory";
+                       num-cs = <2>;
+                       big-endian;
+diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
+index c778b60..3c38425 100644
+--- a/drivers/mtd/spi/sf_internal.h
++++ b/drivers/mtd/spi/sf_internal.h
+@@ -57,6 +57,13 @@ enum spi_nor_option_flags {
+ #define SPI_FLASH_CMD_LEN             (1 + SPI_FLASH_3B_ADDR_LEN)
+ #define SPI_FLASH_16MB_BOUN           0x1000000
+ 
++#define SPI_FLASH_ADDR_MAGIC          0xaa
++#define SPI_FLASH_ADDR_MAGIC_LEN      1
++#define SPI_FLASH_4B_ADDR_LEN         4
++#define SPI_FLASH_CMD_LEN_EXT         (1 + SPI_FLASH_4B_ADDR_LEN + \
++              SPI_FLASH_ADDR_MAGIC_LEN)
++#define SPI_FLASH_64MB_BOUN           0x4000000
++
+ /* CFI Manufacture ID's */
+ #define SPI_FLASH_CFI_MFR_SPANSION    0x01
+ #define SPI_FLASH_CFI_MFR_STMICRO     0x20
+diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
+index 97e53c7..9d61ac0 100644
+--- a/drivers/mtd/spi/spi_flash.c
++++ b/drivers/mtd/spi/spi_flash.c
+@@ -21,12 +21,20 @@
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
+-static void spi_flash_addr(u32 addr, u8 *cmd)
++static void spi_flash_addr(u32 addr, u8 *cmd, u32 offset_ext)
+ {
+-      /* cmd[0] is actual command */
+-      cmd[1] = addr >> 16;
+-      cmd[2] = addr >> 8;
+-      cmd[3] = addr >> 0;
++      if (offset_ext >= SPI_FLASH_16MB_BOUN) {
++              /* cmd[0] is actual command */
++              cmd[1] = addr >> 24;
++              cmd[2] = addr >> 16;
++              cmd[3] = addr >> 8;
++              cmd[4] = addr >> 0;
++              cmd[5] = SPI_FLASH_ADDR_MAGIC;
++      } else {
++              cmd[1] = addr >> 16;
++              cmd[2] = addr >> 8;
++              cmd[3] = addr >> 0;
++      }
+ }
+ 
+ /* Read commands array */
+@@ -302,9 +310,11 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
+ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+ {
+       u32 erase_size, erase_addr;
+-      u8 cmd[SPI_FLASH_CMD_LEN];
++      u8 *cmd, cmdsz;
+       int ret = -1;
++      u32 offset_ext;
+ 
++      offset_ext = offset;
+       erase_size = flash->erase_size;
+       if (offset % erase_size || len % erase_size) {
+               debug("SF: Erase offset/length not multiple of erase size\n");
+@@ -319,7 +329,18 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+               }
+       }
+ 
++      if (offset > SPI_FLASH_16MB_BOUN)
++              cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
++      else
++              cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
++      cmd = calloc(1, cmdsz);
++      if (!cmd) {
++              debug("SF: Failed to allocate cmd\n");
++              return -ENOMEM;
++      }
++      memset(cmd, 0x0, cmdsz);
+       cmd[0] = flash->erase_cmd;
++
+       while (len) {
+               erase_addr = offset;
+ 
+@@ -332,7 +353,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+               if (ret < 0)
+                       return ret;
+ #endif
+-              spi_flash_addr(erase_addr, cmd);
++              spi_flash_addr(erase_addr, cmd, offset_ext);
+ 
+               debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
+                     cmd[2], cmd[3], erase_addr);
+@@ -347,6 +368,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+               len -= erase_size;
+       }
+ 
++      free(cmd);
+       return ret;
+ }
+ 
+@@ -356,9 +378,11 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+       unsigned long byte_addr, page_size;
+       u32 write_addr;
+       size_t chunk_len, actual;
+-      u8 cmd[SPI_FLASH_CMD_LEN];
++      u8 *cmd, cmdsz;
+       int ret = -1;
++      u32 offset_ext;
+ 
++      offset_ext = offset;
+       page_size = flash->page_size;
+ 
+       if (flash->flash_is_locked) {
+@@ -369,6 +393,16 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+               }
+       }
+ 
++      if (offset > SPI_FLASH_16MB_BOUN)
++              cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
++      else
++              cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
++      cmd = calloc(1, cmdsz);
++      if (!cmd) {
++              debug("SF: Failed to allocate cmd\n");
++              return -ENOMEM;
++      }
++      memset(cmd, 0x0, cmdsz);
+       cmd[0] = flash->write_cmd;
+       for (actual = 0; actual < len; actual += chunk_len) {
+               write_addr = offset;
+@@ -389,7 +423,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+                       chunk_len = min(chunk_len,
+                                       (size_t)flash->spi->max_write_size);
+ 
+-              spi_flash_addr(write_addr, cmd);
++              spi_flash_addr(write_addr, cmd, offset_ext);
+ 
+               debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
+                     buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+@@ -404,6 +438,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+               offset += chunk_len;
+       }
+ 
++      free(cmd);
+       return ret;
+ }
+ 
+@@ -442,6 +477,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+       u32 remain_len, read_len, read_addr;
+       int bank_sel = 0;
+       int ret = -1;
++      u32 offset_ext;
++
++      offset_ext = offset;
+ 
+       /* Handle memory-mapped SPI */
+       if (flash->memory_map) {
+@@ -456,15 +494,18 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+               spi_release_bus(flash->spi);
+               return 0;
+       }
+-
+-      cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
++      if (offset > SPI_FLASH_16MB_BOUN)
++              cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
++      else
++              cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
+       cmd = calloc(1, cmdsz);
+       if (!cmd) {
+               debug("SF: Failed to allocate cmd\n");
+               return -ENOMEM;
+       }
+-
++      memset(cmd, 0x0, cmdsz);
+       cmd[0] = flash->read_cmd;
++
+       while (len) {
+               read_addr = offset;
+ 
+@@ -478,14 +519,18 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+                       return ret;
+               bank_sel = flash->bank_curr;
+ #endif
+-              remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
++              if (offset_ext >= SPI_FLASH_16MB_BOUN) {
++                      remain_len = flash->size - offset;
++              } else {
++                      remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
+                               (bank_sel + 1)) - offset;
++              }
+               if (len < remain_len)
+                       read_len = len;
+               else
+                       read_len = remain_len;
+ 
+-              spi_flash_addr(read_addr, cmd);
++              spi_flash_addr(read_addr, cmd, offset_ext);
+ 
+               ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
+               if (ret < 0) {
+diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
+index 2b20038..09759fa 100644
+--- a/drivers/spi/fsl_qspi.c
++++ b/drivers/spi/fsl_qspi.c
+@@ -26,6 +26,9 @@ DECLARE_GLOBAL_DATA_PTR;
+ #endif
+ 
+ #define OFFSET_BITS_MASK      GENMASK(23, 0)
++/* the qspi contrller memmap space ,instead of flash space */
++#define OFFSET_BITS_MASK_QSPI_SPACE   GENMASK(27, 0)
++#define SPI_FLASH_ADDR_EXT_MAGIC      0xaa
+ 
+ #define FLASH_STATUS_WEL      0x02
+ 
+@@ -757,6 +760,13 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
+       u32 bytes = DIV_ROUND_UP(bitlen, 8);
+       static u32 wr_sfaddr;
+       u32 txbuf;
++      u8 offset_ext = 0;
++      u32 flash_offset;
++
++      if (((u8 *)dout)[5] == SPI_FLASH_ADDR_EXT_MAGIC) {
++              offset_ext = 1;
++              memcpy(&flash_offset, dout + 1, 4);
++      }
+ 
+       if (dout) {
+               if (flags & SPI_XFER_BEGIN) {
+@@ -772,14 +782,28 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
+ 
+               if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
+                   priv->cur_seqid == QSPI_CMD_RDAR) {
+-                      priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
++                      if (offset_ext)
++                              priv->sf_addr = swab32(flash_offset) &
++                                      OFFSET_BITS_MASK_QSPI_SPACE;
++                      else
++                              priv->sf_addr = swab32(txbuf) &
++                                      OFFSET_BITS_MASK;
+               } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
+                          (priv->cur_seqid == QSPI_CMD_BE_4K)) {
+-                      priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
++                      if (offset_ext)
++                              priv->sf_addr = swab32(flash_offset) &
++                                      OFFSET_BITS_MASK_QSPI_SPACE;
++                      else
++                              priv->sf_addr = swab32(txbuf) &
++                                      OFFSET_BITS_MASK;
+                       qspi_op_erase(priv);
+               } else if (priv->cur_seqid == QSPI_CMD_PP ||
+                          priv->cur_seqid == QSPI_CMD_WRAR) {
+-                      wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
++                      if (offset_ext)
++                              wr_sfaddr = swab32(flash_offset) &
++                                      OFFSET_BITS_MASK_QSPI_SPACE;
++                      else
++                              wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
+               } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
+                        (priv->cur_seqid == QSPI_CMD_WREAR)) {
+ #ifdef CONFIG_SPI_FLASH_BAR
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 3fd360a..150444d 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -63,9 +63,8 @@
+ #define QSPI0_AMBA_BASE               0x40000000
+ #define CONFIG_SPI_FLASH_SPANSION
+ #define CONFIG_DM_SPI_FLASH
+-#define CONFIG_SPI_FLASH_BAR
+ 
+-#define FSL_QSPI_FLASH_SIZE           (1 << 24)
++#define FSL_QSPI_FLASH_SIZE           (1 << 26)
+ #define FSL_QSPI_FLASH_NUM            2
+ 
+ /*
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0032-driver-spi-fsl_qspi-enable-AHB-read-for-qspi.patch b/package/boot/uboot-layerscape/patches/0032-driver-spi-fsl_qspi-enable-AHB-read-for-qspi.patch
new file mode 100644 (file)
index 0000000..31e0a83
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0032-driver-spi-fsl_qspi-enable-AHB-read-for-qspi.patch
@@ -0,0 +1,30 @@
+From c67f214546a9d8ac00b9b947c145f4c032def8e2 Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Mon, 16 May 2016 14:39:52 +0800
+Subject: [PATCH 32/93] driver: spi: fsl_qspi: enable AHB read for qspi
+
+If we don't enable the AHB read for ls1012a, input 'md 0x40000000',
+'md 0x41000000','md 0x42000000' address will be overlapped.
+After QSPI controller initialization for AHB, 'md 0x...' will access
+the whole QSPI flash address space.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ include/configs/ls1012a_common.h |    1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 150444d..121824c 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -66,6 +66,7 @@
+ 
+ #define FSL_QSPI_FLASH_SIZE           (1 << 26)
+ #define FSL_QSPI_FLASH_NUM            2
++#define CONFIG_SYS_FSL_QSPI_AHB
+ 
+ /*
+  * Environment
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0033-mmc-fsl_esdhc-support-two-esdhc-host-controllers.patch b/package/boot/uboot-layerscape/patches/0033-mmc-fsl_esdhc-support-two-esdhc-host-controllers.patch
new file mode 100644 (file)
index 0000000..9cc171c
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0033-mmc-fsl_esdhc-support-two-esdhc-host-controllers.patch
@@ -0,0 +1,47 @@
+From 2daf451df50209e7626c2bf424d50ff23055784a Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Wed, 18 May 2016 10:52:38 +0800
+Subject: [PATCH 33/93] mmc: fsl_esdhc: support two esdhc host controllers
+
+This patch is to support two esdhc host controllers with
+the macro CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT.
+
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/mmc/fsl_esdhc.c |   15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
+index 7cc61a0..cacf879 100644
+--- a/drivers/mmc/fsl_esdhc.c
++++ b/drivers/mmc/fsl_esdhc.c
+@@ -748,11 +748,26 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
+ int fsl_esdhc_mmc_init(bd_t *bis)
+ {
+       struct fsl_esdhc_cfg *cfg;
++#ifdef CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
++      struct fsl_esdhc_cfg *cfg_1;
++#endif
+ 
+       cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
+       cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+       cfg->sdhc_clk = gd->arch.sdhc_clk;
++#ifdef CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
++      cfg_1 = calloc(sizeof(struct fsl_esdhc_cfg), 1);
++      cfg_1->esdhc_base = CONFIG_SYS_FSL_ESDHC_1_ADDR;
++      cfg_1->sdhc_clk = gd->arch.sdhc_clk;
++
++      if (fsl_esdhc_initialize(bis, cfg))
++              return -1;
++      if (fsl_esdhc_initialize(bis, cfg_1))
++              return -1;
++      return 0;
++#else
+       return fsl_esdhc_initialize(bis, cfg);
++#endif
+ }
+ 
+ #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0034-mmc-fsl_esdhc-add-workaround-for-non-removable-card-.patch b/package/boot/uboot-layerscape/patches/0034-mmc-fsl_esdhc-add-workaround-for-non-removable-card-.patch
new file mode 100644 (file)
index 0000000..00c4449
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0034-mmc-fsl_esdhc-add-workaround-for-non-removable-card-.patch
@@ -0,0 +1,57 @@
+From e3e641993a1a5148e71bdd3f7b3cb5da695b1632 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Fri, 20 May 2016 11:17:30 +0800
+Subject: [PATCH 34/93] mmc: fsl_esdhc: add workaround for non-removable card
+ of esdhc-2
+
+The esdhc-2 usually uses some on-board memory devices such as eMMC
+card or SDIO wifi module, and it doesn't support SDHC_CD_B. So we
+could only assume it always has a card instead of detecting SDHC_CD_B
+status. This patch is to add workaround for these non-removable
+cards which are used by esdhc-2.
+
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/mmc/fsl_esdhc.c |    6 +++++-
+ include/fsl_esdhc.h     |    1 +
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
+index cacf879..2c6e175 100644
+--- a/drivers/mmc/fsl_esdhc.c
++++ b/drivers/mmc/fsl_esdhc.c
+@@ -628,6 +628,8 @@ static int esdhc_getcd(struct mmc *mmc)
+       struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+       int timeout = 1000;
+ 
++      if (cfg->non_removable_card)
++              return 1;
+ #ifdef CONFIG_ESDHC_DETECT_QUIRK
+       if (CONFIG_ESDHC_DETECT_QUIRK)
+               return 1;
+@@ -759,7 +761,9 @@ int fsl_esdhc_mmc_init(bd_t *bis)
+       cfg_1 = calloc(sizeof(struct fsl_esdhc_cfg), 1);
+       cfg_1->esdhc_base = CONFIG_SYS_FSL_ESDHC_1_ADDR;
+       cfg_1->sdhc_clk = gd->arch.sdhc_clk;
+-
++#ifdef CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
++      cfg_1->non_removable_card = true;
++#endif
+       if (fsl_esdhc_initialize(bis, cfg))
+               return -1;
+       if (fsl_esdhc_initialize(bis, cfg_1))
+diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
+index 073048f..8335106 100644
+--- a/include/fsl_esdhc.h
++++ b/include/fsl_esdhc.h
+@@ -175,6 +175,7 @@ struct fsl_esdhc_cfg {
+ #endif
+       u32     sdhc_clk;
+       u8      max_bus_width;
++      bool    non_removable_card;
+       struct mmc_config cfg;
+ };
+ 
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0035-armv8-ls1012a-enable-two-esdhc-host-controllers-supp.patch b/package/boot/uboot-layerscape/patches/0035-armv8-ls1012a-enable-two-esdhc-host-controllers-supp.patch
new file mode 100644 (file)
index 0000000..2099d40
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0035-armv8-ls1012a-enable-two-esdhc-host-controllers-supp.patch
@@ -0,0 +1,43 @@
+From 7d3d85483a6c4085de5c016b86838681e97e6577 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Fri, 20 May 2016 11:31:17 +0800
+Subject: [PATCH 35/93] armv8: ls1012a: enable two esdhc host controllers
+ support
+
+LS1012A chip has two esdhc host controllers, and this patch
+is to enable two controllers support for it.
+
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |    1 +
+ include/configs/ls1012a_common.h                   |    2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index 24add1a..6918757 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -19,6 +19,7 @@
+ #define CONFIG_SYS_GIC400_ADDR                        (CONFIG_SYS_IMMR + 0x00400000)
+ #define CONFIG_SYS_IFC_ADDR                   (CONFIG_SYS_IMMR + 0x00530000)
+ #define CONFIG_SYS_FSL_ESDHC_ADDR             (CONFIG_SYS_IMMR + 0x00560000)
++#define CONFIG_SYS_FSL_ESDHC_1_ADDR           (CONFIG_SYS_IMMR + 0x00580000)
+ #define CONFIG_SYS_FSL_CSU_ADDR                       (CONFIG_SYS_IMMR + 0x00510000)
+ #define CONFIG_SYS_FSL_GUTS_ADDR              (CONFIG_SYS_IMMR + 0x00ee0000)
+ #define CONFIG_SYS_FSL_RST_ADDR                       (CONFIG_SYS_IMMR + 0x00ee00b0)
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 121824c..89d1370 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -94,6 +94,8 @@
+ #ifdef CONFIG_MMC
+ #define CONFIG_CMD_MMC
+ #define CONFIG_FSL_ESDHC
++#define CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
++#define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
+ #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_CMD_FAT
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0036-driver-spi-add-exceed-16MB-flash-support.patch b/package/boot/uboot-layerscape/patches/0036-driver-spi-add-exceed-16MB-flash-support.patch
new file mode 100644 (file)
index 0000000..c43ae97
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0036-driver-spi-add-exceed-16MB-flash-support.patch
@@ -0,0 +1,144 @@
+From e70ae7f7ed00ecdbfa45fac3f342f1130df5029b Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Fri, 20 May 2016 16:37:34 +0800
+Subject: [PATCH 36/93] driver: spi: add exceed 16MB flash support
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi/spi_flash.c |   41 +++++++++++------------------------------
+ 1 file changed, 11 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
+index 9d61ac0..e9d1c64 100644
+--- a/drivers/mtd/spi/spi_flash.c
++++ b/drivers/mtd/spi/spi_flash.c
+@@ -21,9 +21,9 @@
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
+-static void spi_flash_addr(u32 addr, u8 *cmd, u32 offset_ext)
++static void spi_flash_addr(u32 addr, u8 *cmd)
+ {
+-      if (offset_ext >= SPI_FLASH_16MB_BOUN) {
++      if (addr >= SPI_FLASH_16MB_BOUN) {
+               /* cmd[0] is actual command */
+               cmd[1] = addr >> 24;
+               cmd[2] = addr >> 16;
+@@ -312,9 +312,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+       u32 erase_size, erase_addr;
+       u8 *cmd, cmdsz;
+       int ret = -1;
+-      u32 offset_ext;
+ 
+-      offset_ext = offset;
+       erase_size = flash->erase_size;
+       if (offset % erase_size || len % erase_size) {
+               debug("SF: Erase offset/length not multiple of erase size\n");
+@@ -329,10 +327,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+               }
+       }
+ 
+-      if (offset > SPI_FLASH_16MB_BOUN)
+-              cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
+-      else
+-              cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
++      cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
+       cmd = calloc(1, cmdsz);
+       if (!cmd) {
+               debug("SF: Failed to allocate cmd\n");
+@@ -353,7 +348,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+               if (ret < 0)
+                       return ret;
+ #endif
+-              spi_flash_addr(erase_addr, cmd, offset_ext);
++              spi_flash_addr(erase_addr, cmd);
+ 
+               debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
+                     cmd[2], cmd[3], erase_addr);
+@@ -380,9 +375,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+       size_t chunk_len, actual;
+       u8 *cmd, cmdsz;
+       int ret = -1;
+-      u32 offset_ext;
+ 
+-      offset_ext = offset;
+       page_size = flash->page_size;
+ 
+       if (flash->flash_is_locked) {
+@@ -393,10 +386,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+               }
+       }
+ 
+-      if (offset > SPI_FLASH_16MB_BOUN)
+-              cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
+-      else
+-              cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
++      cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
+       cmd = calloc(1, cmdsz);
+       if (!cmd) {
+               debug("SF: Failed to allocate cmd\n");
+@@ -423,7 +413,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+                       chunk_len = min(chunk_len,
+                                       (size_t)flash->spi->max_write_size);
+ 
+-              spi_flash_addr(write_addr, cmd, offset_ext);
++              spi_flash_addr(write_addr, cmd);
+ 
+               debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
+                     buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+@@ -477,9 +467,6 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+       u32 remain_len, read_len, read_addr;
+       int bank_sel = 0;
+       int ret = -1;
+-      u32 offset_ext;
+-
+-      offset_ext = offset;
+ 
+       /* Handle memory-mapped SPI */
+       if (flash->memory_map) {
+@@ -494,10 +481,8 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+               spi_release_bus(flash->spi);
+               return 0;
+       }
+-      if (offset > SPI_FLASH_16MB_BOUN)
+-              cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
+-      else
+-              cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
++
++      cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
+       cmd = calloc(1, cmdsz);
+       if (!cmd) {
+               debug("SF: Failed to allocate cmd\n");
+@@ -508,7 +493,6 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ 
+       while (len) {
+               read_addr = offset;
+-
+ #ifdef CONFIG_SF_DUAL_FLASH
+               if (flash->dual_flash > SF_SINGLE_FLASH)
+                       spi_flash_dual(flash, &read_addr);
+@@ -519,18 +503,15 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+                       return ret;
+               bank_sel = flash->bank_curr;
+ #endif
+-              if (offset_ext >= SPI_FLASH_16MB_BOUN) {
+-                      remain_len = flash->size - offset;
+-              } else {
+-                      remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
++              remain_len = ((flash->size << flash->shift) *
+                               (bank_sel + 1)) - offset;
+-              }
++
+               if (len < remain_len)
+                       read_len = len;
+               else
+                       read_len = remain_len;
+ 
+-              spi_flash_addr(read_addr, cmd, offset_ext);
++              spi_flash_addr(read_addr, cmd);
+ 
+               ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
+               if (ret < 0) {
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0037-driver-spi-remove-Warning-prints-for-Spansion-FS-S-f.patch b/package/boot/uboot-layerscape/patches/0037-driver-spi-remove-Warning-prints-for-Spansion-FS-S-f.patch
new file mode 100644 (file)
index 0000000..981182b
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0037-driver-spi-remove-Warning-prints-for-Spansion-FS-S-f.patch
@@ -0,0 +1,60 @@
+From 65a6669afc667dacacf24a3a3f340205e38b0c5d Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Fri, 27 May 2016 10:25:09 +0800
+Subject: [PATCH 37/93] driver: spi: remove Warning prints for Spansion FS-S
+ fmaily
+
+The Spansion flash FS-S family don't support the bank related
+commands, Even if flash size exceed 16MB, we cannot enable the
+macro CONFIG_SPI_FLASH_BAR. Also, we need remove the irrelevant
+warnings:
+"puts("SF: Warning - Only lower 16MiB accessible,"
+"Full access #define CONFIG_SPI_FLASH_BAR"
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi/spi_flash.c |   13 +++++++++----
+ 1 file changed, 9 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
+index e9d1c64..b0f09ab 100644
+--- a/drivers/mtd/spi/spi_flash.c
++++ b/drivers/mtd/spi/spi_flash.c
+@@ -1009,6 +1009,9 @@ int spi_flash_scan(struct spi_flash *flash)
+       u8 idcode[5];
+       u8 cmd;
+       int ret;
++#ifdef CONFIG_SPI_FLASH_SPANSION
++      u8 id[6];
++#endif
+ 
+       /* Read the ID codes */
+       ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
+@@ -1062,7 +1065,6 @@ int spi_flash_scan(struct spi_flash *flash)
+       if ((jedec == 0x0219 || (jedec == 0x0220)) &&
+           (ext_jedec & 0xff00) == 0x4d00) {
+               int ret;
+-              u8 id[6];
+ 
+               /* Read the ID codes again, 6 bytes */
+               ret = spi_flash_cmd(flash->spi, CMD_READ_ID, id, sizeof(id));
+@@ -1253,10 +1255,13 @@ int spi_flash_scan(struct spi_flash *flash)
+ #endif
+ 
+ #ifndef CONFIG_SPI_FLASH_BAR
+-      if (((flash->dual_flash == SF_SINGLE_FLASH) &&
+-           (flash->size > SPI_FLASH_16MB_BOUN)) ||
++      if ((id[5] != 0x81) &&
++      /*Spansion FS-S family not support BAR ,
++      Even if CONFIG_SPI_FLASH_BAR is unable,  Need not the Warning prints */
++           ((((flash->dual_flash == SF_SINGLE_FLASH) &&
++           (flash->size > SPI_FLASH_16MB_BOUN))) ||
+            ((flash->dual_flash > SF_SINGLE_FLASH) &&
+-           (flash->size > SPI_FLASH_16MB_BOUN << 1))) {
++           (flash->size > SPI_FLASH_16MB_BOUN << 1)))) {
+               puts("SF: Warning - Only lower 16MiB accessible,");
+               puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
+       }
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0038-Shift-board-specific-configurations.patch b/package/boot/uboot-layerscape/patches/0038-Shift-board-specific-configurations.patch
new file mode 100644 (file)
index 0000000..1c1cc81
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0038-Shift-board-specific-configurations.patch
@@ -0,0 +1,228 @@
+From 8f096adfd96941e596b5fbf30a21193e32f2c1b0 Mon Sep 17 00:00:00 2001
+From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Date: Fri, 27 May 2016 15:10:40 +0530
+Subject: [PATCH 38/93] Shift board specific configurations
+
+Board specific configurations are moved from
+ls1012a_common.h to ls1012aqds.h and ls1012ardb.h
+
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+---
+ include/configs/ls1012a_common.h |   60 --------------------------------------
+ include/configs/ls1012aqds.h     |   58 ++++++++++++++++++++++++++++++++++++
+ include/configs/ls1012ardb.h     |   58 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 116 insertions(+), 60 deletions(-)
+
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 89d1370..07ef7c6 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -88,66 +88,6 @@
+ #define CONFIG_SYS_I2C_MXC_I2C2               /* enable I2C bus 2 */
+ #endif /* CONFIG_EMU */
+ 
+-/*  MMC  */
+-#if  !defined(CONFIG_EMU)
+-#define CONFIG_MMC
+-#ifdef CONFIG_MMC
+-#define CONFIG_CMD_MMC
+-#define CONFIG_FSL_ESDHC
+-#define CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
+-#define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
+-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+-#define CONFIG_GENERIC_MMC
+-#define CONFIG_CMD_FAT
+-#define CONFIG_DOS_PARTITION
+-#endif
+-#endif /* CONFIG_EMU */
+-
+-/* SATA */
+-#if  !defined(CONFIG_EMU)
+-#define CONFIG_LIBATA
+-#define CONFIG_SCSI_AHCI
+-#define CONFIG_SCSI_AHCI_PLAT
+-#define CONFIG_CMD_SCSI
+-#define CONFIG_CMD_FAT
+-#define CONFIG_CMD_EXT2
+-#define CONFIG_DOS_PARTITION
+-#define CONFIG_BOARD_LATE_INIT
+-
+-#define CONFIG_SYS_SATA                               AHCI_BASE_ADDR
+-
+-#define CONFIG_SYS_SCSI_MAX_SCSI_ID           1
+-#define CONFIG_SYS_SCSI_MAX_LUN                       1
+-#define CONFIG_SYS_SCSI_MAX_DEVICE            (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+-                                              CONFIG_SYS_SCSI_MAX_LUN)
+-
+-#define CONFIG_PCI            /* Enable PCI/PCIE */
+-#define CONFIG_PCIE1          /* PCIE controller 1 */
+-#define CONFIG_PCIE_LAYERSCAPE        /* Use common FSL Layerscape PCIe code */
+-#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+-
+-#define CONFIG_SYS_PCI_64BIT
+-
+-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
+-#define CONFIG_SYS_PCIE_CFG0_SIZE     0x00001000      /* 4k */
+-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
+-#define CONFIG_SYS_PCIE_CFG1_SIZE     0x00001000      /* 4k */
+-
+-#define CONFIG_SYS_PCIE_IO_BUS                0x00000000
+-#define CONFIG_SYS_PCIE_IO_PHYS_OFF   0x00010000
+-#define CONFIG_SYS_PCIE_IO_SIZE               0x00010000      /* 64k */
+-
+-#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
+-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
+-#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
+-
+-#define CONFIG_NET_MULTI
+-#define CONFIG_PCI_PNP
+-#define CONFIG_E1000
+-#define CONFIG_PCI_SCAN_SHOW
+-#define CONFIG_CMD_PCI
+-#endif
+-
+ #define CONFIG_CONS_INDEX       1
+ #define CONFIG_SYS_NS16550_SERIAL
+ #define CONFIG_SYS_NS16550_REG_SIZE     1
+diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
+index de998b8..488811b 100644
+--- a/include/configs/ls1012aqds.h
++++ b/include/configs/ls1012aqds.h
+@@ -26,6 +26,64 @@
+ #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+ #endif
+ 
++/*  MMC  */
++#if  !defined(CONFIG_EMU)
++#define CONFIG_MMC
++#ifdef CONFIG_MMC
++#define CONFIG_CMD_MMC
++#define CONFIG_FSL_ESDHC
++#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
++#define CONFIG_GENERIC_MMC
++#define CONFIG_CMD_FAT
++#define CONFIG_DOS_PARTITION
++#endif
++#endif /* CONFIG_EMU */
++
++/* SATA */
++#if  !defined(CONFIG_EMU)
++#define CONFIG_LIBATA
++#define CONFIG_SCSI_AHCI
++#define CONFIG_SCSI_AHCI_PLAT
++#define CONFIG_CMD_SCSI
++#define CONFIG_CMD_FAT
++#define CONFIG_CMD_EXT2
++#define CONFIG_DOS_PARTITION
++#define CONFIG_BOARD_LATE_INIT
++
++#define CONFIG_SYS_SATA                               AHCI_BASE_ADDR
++
++#define CONFIG_SYS_SCSI_MAX_SCSI_ID           1
++#define CONFIG_SYS_SCSI_MAX_LUN                       1
++#define CONFIG_SYS_SCSI_MAX_DEVICE            (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
++                                              CONFIG_SYS_SCSI_MAX_LUN)
++
++#define CONFIG_PCI            /* Enable PCI/PCIE */
++#define CONFIG_PCIE1          /* PCIE controller 1 */
++#define CONFIG_PCIE_LAYERSCAPE        /* Use common FSL Layerscape PCIe code */
++#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
++
++#define CONFIG_SYS_PCI_64BIT
++
++#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
++#define CONFIG_SYS_PCIE_CFG0_SIZE     0x00001000      /* 4k */
++#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
++#define CONFIG_SYS_PCIE_CFG1_SIZE     0x00001000      /* 4k */
++
++#define CONFIG_SYS_PCIE_IO_BUS                0x00000000
++#define CONFIG_SYS_PCIE_IO_PHYS_OFF   0x00010000
++#define CONFIG_SYS_PCIE_IO_SIZE               0x00010000      /* 64k */
++
++#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
++#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
++#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
++
++#define CONFIG_NET_MULTI
++#define CONFIG_PCI_PNP
++#define CONFIG_E1000
++#define CONFIG_PCI_SCAN_SHOW
++#define CONFIG_CMD_PCI
++#endif
++
+ /*
+  * QIXIS Definitions
+  */
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index b40e02b..1629e19 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -55,6 +55,64 @@
+ #define CONFIG_CMD_USB_MASS_STORAGE
+ #endif
+ 
++/*  MMC  */
++#if  !defined(CONFIG_EMU)
++#define CONFIG_MMC
++#ifdef CONFIG_MMC
++#define CONFIG_CMD_MMC
++#define CONFIG_FSL_ESDHC
++#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
++#define CONFIG_GENERIC_MMC
++#define CONFIG_CMD_FAT
++#define CONFIG_DOS_PARTITION
++#endif
++#endif /* CONFIG_EMU */
++
++/* SATA */
++#if  !defined(CONFIG_EMU)
++#define CONFIG_LIBATA
++#define CONFIG_SCSI_AHCI
++#define CONFIG_SCSI_AHCI_PLAT
++#define CONFIG_CMD_SCSI
++#define CONFIG_CMD_FAT
++#define CONFIG_CMD_EXT2
++#define CONFIG_DOS_PARTITION
++#define CONFIG_BOARD_LATE_INIT
++
++#define CONFIG_SYS_SATA                               AHCI_BASE_ADDR
++
++#define CONFIG_SYS_SCSI_MAX_SCSI_ID           1
++#define CONFIG_SYS_SCSI_MAX_LUN                       1
++#define CONFIG_SYS_SCSI_MAX_DEVICE            (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
++                                              CONFIG_SYS_SCSI_MAX_LUN)
++
++#define CONFIG_PCI            /* Enable PCI/PCIE */
++#define CONFIG_PCIE1          /* PCIE controller 1 */
++#define CONFIG_PCIE_LAYERSCAPE        /* Use common FSL Layerscape PCIe code */
++#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
++
++#define CONFIG_SYS_PCI_64BIT
++
++#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
++#define CONFIG_SYS_PCIE_CFG0_SIZE     0x00001000      /* 4k */
++#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
++#define CONFIG_SYS_PCIE_CFG1_SIZE     0x00001000      /* 4k */
++
++#define CONFIG_SYS_PCIE_IO_BUS                0x00000000
++#define CONFIG_SYS_PCIE_IO_PHYS_OFF   0x00010000
++#define CONFIG_SYS_PCIE_IO_SIZE               0x00010000      /* 64k */
++
++#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
++#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
++#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
++
++#define CONFIG_NET_MULTI
++#define CONFIG_PCI_PNP
++#define CONFIG_E1000
++#define CONFIG_PCI_SCAN_SHOW
++#define CONFIG_CMD_PCI
++#endif
++
+ /*
+  * I2C IO expander
+  */
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0039-armv8-ls1012a-Add-support-of-ls1012afrdm-board.patch b/package/boot/uboot-layerscape/patches/0039-armv8-ls1012a-Add-support-of-ls1012afrdm-board.patch
new file mode 100644 (file)
index 0000000..8df1d91
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0039-armv8-ls1012a-Add-support-of-ls1012afrdm-board.patch
@@ -0,0 +1,566 @@
+From 6aaa5973b9ae8452a546e0666b2389bb163fb949 Mon Sep 17 00:00:00 2001
+From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Date: Thu, 19 May 2016 16:45:27 +0530
+Subject: [PATCH 39/93] armv8: ls1012a: Add support of ls1012afrdm board
+
+QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012AFRDM board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+---
+ arch/arm/Kconfig                          |   10 ++
+ arch/arm/dts/Makefile                     |    3 +-
+ arch/arm/dts/fsl-ls1012a-frdm.dts         |   16 +++
+ arch/arm/dts/fsl-ls1012a-frdm.dtsi        |   39 ++++++
+ board/freescale/ls1012afrdm/Kconfig       |   15 +++
+ board/freescale/ls1012afrdm/MAINTAINERS   |    6 +
+ board/freescale/ls1012afrdm/Makefile      |    7 ++
+ board/freescale/ls1012afrdm/README        |   94 +++++++++++++++
+ board/freescale/ls1012afrdm/ls1012afrdm.c |  183 +++++++++++++++++++++++++++++
+ configs/ls1012afrdm_qspi_defconfig        |   10 ++
+ include/configs/ls1012afrdm.h             |   59 ++++++++++
+ 11 files changed, 441 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dts
+ create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dtsi
+ create mode 100644 board/freescale/ls1012afrdm/Kconfig
+ create mode 100644 board/freescale/ls1012afrdm/MAINTAINERS
+ create mode 100644 board/freescale/ls1012afrdm/Makefile
+ create mode 100644 board/freescale/ls1012afrdm/README
+ create mode 100644 board/freescale/ls1012afrdm/ls1012afrdm.c
+ create mode 100644 configs/ls1012afrdm_qspi_defconfig
+ create mode 100644 include/configs/ls1012afrdm.h
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index b536684..23fce38 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -669,6 +669,15 @@ config TARGET_LS1012ARDB
+         development platform that supports the QorIQ LS1012A
+         Layerscape Architecture processor.
+ 
++config TARGET_LS1012AFRDM
++      bool "Support ls1012afrdm"
++      select ARM64
++      help
++        Support for Freescale LS1012AFRDM platform.
++        The LS1012A Freedom  board (FRDM) is a high-performance
++        development platform that supports the QorIQ LS1012A
++        Layerscape Architecture processor.
++
+ config TARGET_LS1021AQDS
+       bool "Support ls1021aqds"
+       select CPU_V7
+@@ -816,6 +825,7 @@ source "board/freescale/ls1021atwr/Kconfig"
+ source "board/freescale/ls1043ardb/Kconfig"
+ source "board/freescale/ls1012aqds/Kconfig"
+ source "board/freescale/ls1012ardb/Kconfig"
++source "board/freescale/ls1012afrdm/Kconfig"
+ source "board/freescale/mx23evk/Kconfig"
+ source "board/freescale/mx25pdk/Kconfig"
+ source "board/freescale/mx28evk/Kconfig"
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 9e8137b..de023b4 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -96,7 +96,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
+       fsl-ls1043a-qds-lpuart.dtb \
+       fsl-ls1043a-rdb.dtb \
+       fsl-ls1012a-qds.dtb \
+-      fsl-ls1012a-rdb.dtb
++      fsl-ls1012a-rdb.dtb \
++      fsl-ls1012a-frdm.dtb
+ 
+ dtb-$(CONFIG_MACH_SUN4I) += \
+       sun4i-a10-a1000.dtb \
+diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dts b/arch/arm/dts/fsl-ls1012a-frdm.dts
+new file mode 100644
+index 0000000..3a06c0a
+--- /dev/null
++++ b/arch/arm/dts/fsl-ls1012a-frdm.dts
+@@ -0,0 +1,16 @@
++/*
++ * Device Tree file for Freescale Layerscape-1012A family SoC.
++ *
++ * Copyright (C) 2016, Freescale Semiconductor
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++/dts-v1/;
++#include "fsl-ls1012a-frdm.dtsi"
++
++/ {
++      chosen {
++              stdout-path = &duart0;
++      };
++};
+diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
+new file mode 100644
+index 0000000..9f0db91
+--- /dev/null
++++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
+@@ -0,0 +1,39 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
++ *
++ * Copyright (C) 2016, Freescale Semiconductor
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++/include/ "fsl-ls1012a.dtsi"
++
++/ {
++      model = "LS1012A FREEDOM Board";
++      aliases {
++              spi0 = &qspi;
++      };
++};
++
++&qspi {
++      bus-num = <0>;
++      status = "okay";
++
++      qflash0: s25fl128s@0 {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "spi-flash";
++              spi-max-frequency = <20000000>;
++              reg = <0>;
++      };
++};
++
++&i2c0 {
++      status = "okay";
++};
++
++&duart0 {
++      status = "okay";
++};
+diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
+new file mode 100644
+index 0000000..a34521c
+--- /dev/null
++++ b/board/freescale/ls1012afrdm/Kconfig
+@@ -0,0 +1,15 @@
++if TARGET_LS1012AFRDM
++
++config SYS_BOARD
++      default "ls1012afrdm"
++
++config SYS_VENDOR
++      default "freescale"
++
++config SYS_SOC
++      default "fsl-layerscape"
++
++config SYS_CONFIG_NAME
++      default "ls1012afrdm"
++
++endif
+diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
+new file mode 100644
+index 0000000..2f31d0f
+--- /dev/null
++++ b/board/freescale/ls1012afrdm/MAINTAINERS
+@@ -0,0 +1,6 @@
++LS1012AFRDM BOARD
++M:    Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
++S:    Maintained
++F:    board/freescale/ls1012afrdm/
++F:    include/configs/ls1012afrdm.h
++F:    configs/ls1012afrdm_defconfig
+diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
+new file mode 100644
+index 0000000..dbfa2ce
+--- /dev/null
++++ b/board/freescale/ls1012afrdm/Makefile
+@@ -0,0 +1,7 @@
++#
++# Copyright 2016 Freescale Semiconductor, Inc.
++#
++# SPDX-License-Identifier:      GPL-2.0+
++#
++
++obj-y += ls1012afrdm.o
+diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README
+new file mode 100644
+index 0000000..0aadbb1
+--- /dev/null
++++ b/board/freescale/ls1012afrdm/README
+@@ -0,0 +1,94 @@
++Overview
++--------
++The LS1012AFRDM power supplies (PS) provide all the voltages necessary
++for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
++and other onboard peripherals.
++
++LS1012A SoC Overview
++--------------------
++The LS1012A features an advanced 64-bit ARM v8 Cortex-
++A53 processor, with 32 KB of parity protected L1-I cache,
++32 KB of ECC protected L1-D cache, as well as 256 KB of
++ECC protected L2 cache.
++
++The LS1012A SoC includes the following function and features:
++ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
++ - ARM v8 cryptography extensions
++ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
++    16-/8-bit operation (no ECC support)
++ - ARM core-link CCI-400 cache coherent interconnect
++ - Packet Forwarding Engine (PFE)
++ - Cryptography acceleration (SEC)
++ - Ethernet interfaces supported by PFE:
++ - One Configurable x3 SerDes:
++    Two Serdes PLLs supported for usage by any SerDes data lane
++    Support for up to 6 GBaud operation
++ - High-speed peripheral interfaces:
++     - One PCI Express Gen2 controller, supporting x1 operation
++     - One serial ATA (SATA Gen 3.0) controller
++     - One USB 3.0/2.0 controller with integrated PHY
++     - One USB 2.0 controller with ULPI interface. .
++ - Additional peripheral interfaces:
++    - One quad serial peripheral interface (QuadSPI) controller
++    - One serial peripheral interface (SPI) controller
++    - Two enhanced secure digital host controllers
++    - Two I2C controllers
++    - One 16550 compliant DUART (two UART interfaces)
++    - Two general purpose IOs (GPIO)
++    - Two FlexTimers
++    - Five synchronous audio interfaces (SAI)
++    - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
++    - Single-source clocking solution enabling generation of core, platform,
++    DDR, SerDes, and USB clocks from a single external crystal and internal
++    crystaloscillator
++    - Thermal monitor unit (TMU) with +/- 3C accuracy
++    - Two WatchDog timers
++    - ARM generic timer
++ - QorIQ platform's trust architecture 2.1
++
++ LS1012AFRDM board Overview
++ -----------------------
++ - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
++     - 2 SGMII 1G PHYs
++ - DDR Controller
++     - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
++      operating at 1.35 V
++ - QSPI
++     - Onboard 512 Mbit QSPI flash memory running at speed up
++      to 108/54 MHz
++ - One high-speed USB 2.0/3.0 port, one USB 2.0 port
++     - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
++       Micro-AB connector.
++     - USB 2.0 port is a debug port (CMSIS DAP) and is configured
++       as a Micro-AB device.
++ - I2C controller
++     - One I2C bus with connectivity to Arduino headers
++ - UART
++     - UART (Console): UART1 (Without flow control) for console
++ - ARM JTAG support
++     - ARM Cortex® 10-pin JTAG connector for LS1012A
++     - CMSIS DAP through K20 microcontroller
++ - SAI Audio interface
++     - One SAI port, SAI 2 with full duplex support
++ - Clocks
++     - 25 MHz crystal for LS1012A
++     - 8 MHz Crystal for K20
++     - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
++ - Power Supplies
++     - 5 V input supply from USB
++     - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
++       other board interfaces
++
++Booting Options
++---------------
++a) QSPI Flash 1
++
++QSPI flash map
++--------------
++Images                | Size  |QSPI Flash Address
++------------------------------------------
++RCW + PBI     | 1MB   | 0x4000_0000
++U-boot                | 1MB   | 0x4010_0000
++U-boot Env    | 1MB   | 0x4020_0000
++PPA FIT image | 2MB   | 0x4050_0000
++Linux ITB     | ~53MB | 0x40A0_0000
+diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
+new file mode 100644
+index 0000000..6be8951
+--- /dev/null
++++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
+@@ -0,0 +1,183 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++#include <common.h>
++#include <i2c.h>
++#include <asm/io.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/fsl_serdes.h>
++#include <asm/arch/ppa.h>
++#include <asm/arch/soc.h>
++#include <hwconfig.h>
++#include <ahci.h>
++#include <mmc.h>
++#include <scsi.h>
++#include <fsl_csu.h>
++#include <fsl_esdhc.h>
++#include <environment.h>
++#include <fsl_mmdc.h>
++#include <netdev.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
++{
++      int timeout = 1000;
++
++      out_be32(ptr, value);
++
++      while (in_be32(ptr) & bits) {
++              udelay(100);
++              timeout--;
++      }
++      if (timeout <= 0)
++              puts("Error: wait for clear timeout.\n");
++}
++
++int checkboard(void)
++{
++      puts("Board: LS1012AFRDM ");
++
++      return 0;
++}
++
++void mmdc_init(void)
++{
++      struct mmdc_p_regs *mmdc =
++              (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
++
++      /* Set MMDC_MDSCR[CON_REQ] */
++      out_be32(&mmdc->mdscr, 0x00008000);
++
++      /* configure timing parms */
++      out_be32(&mmdc->mdotc,  0x12554000);
++      out_be32(&mmdc->mdcfg0, 0xbabf7954);
++      out_be32(&mmdc->mdcfg1, 0xff328f64);
++      out_be32(&mmdc->mdcfg2, 0x01ff00db);
++
++      /* other parms  */
++      out_be32(&mmdc->mdmisc,    0x00000680);
++      out_be32(&mmdc->mpmur0,    0x00000800);
++      out_be32(&mmdc->mdrwd,     0x00002000);
++      out_be32(&mmdc->mpodtctrl, 0x0000022a);
++
++      /* out of reset delays */
++      out_be32(&mmdc->mdor,  0x00bf1023);
++
++      /* physical parms */
++      out_be32(&mmdc->mdctl, 0x04180000);
++      out_be32(&mmdc->mdasp, 0x0000007f);
++
++      /* Enable MMDC */
++      out_be32(&mmdc->mdctl, 0x84180000);
++
++      /* dram init sequence: update MRs */
++      out_be32(&mmdc->mdscr, 0x00088032);
++      out_be32(&mmdc->mdscr, 0x00008033);
++      out_be32(&mmdc->mdscr, 0x00048031);
++      out_be32(&mmdc->mdscr, 0x19308030);
++
++      /* dram init sequence: ZQCL */
++      out_be32(&mmdc->mdscr,      0x04008040);
++      set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
++
++      /* Calibrations now: wr lvl */
++      out_be32(&mmdc->mdscr,   0x00848031);
++      out_be32(&mmdc->mdscr,   0x00008200);
++      set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
++
++      mdelay(1);
++
++      out_be32(&mmdc->mdscr, 0x00048031);
++      out_be32(&mmdc->mdscr, 0x00008000);
++
++      mdelay(1);
++
++      /* Calibrations now: Read DQS gating calibration */
++      out_be32(&mmdc->mdscr,     0x04008050);
++      out_be32(&mmdc->mdscr,     0x00048033);
++      out_be32(&mmdc->mppdcmpr2, 0x00000001);
++      out_be32(&mmdc->mprddlctl, 0x40404040);
++      set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
++
++      out_be32(&mmdc->mdscr, 0x00008033);
++
++      /* Calibrations now: Read calibration */
++      out_be32(&mmdc->mdscr,       0x04008050);
++      out_be32(&mmdc->mdscr,       0x00048033);
++      out_be32(&mmdc->mppdcmpr2,   0x00000001);
++      set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
++
++      out_be32(&mmdc->mdscr, 0x00008033);
++
++      /* PD, SR */
++      out_be32(&mmdc->mdpdc, 0x00030035);
++      out_be32(&mmdc->mapsr, 0x00001067);
++
++      /* refresh scheme */
++      set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
++
++      /* disable CON_REQ */
++      out_be32(&mmdc->mdscr, 0x0);
++}
++
++int dram_init(void)
++{
++      mmdc_init();
++
++      gd->ram_size = 0x20000000;
++
++      return 0;
++}
++
++int board_eth_init(bd_t *bis)
++{
++      return pci_eth_init(bis);
++}
++
++int board_early_init_f(void)
++{
++      fsl_lsch2_early_init_f();
++
++      return 0;
++}
++
++int board_init(void)
++{
++      struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
++      /*
++       * Set CCI-400 control override register to enable barrier
++       * transaction
++       */
++      out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
++
++#ifdef CONFIG_ENV_IS_NOWHERE
++      gd->env_addr = (ulong)&default_environment[0];
++#endif
++
++#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
++      enable_layerscape_ns_access();
++#endif
++
++      return 0;
++}
++
++int ft_board_setup(void *blob, bd_t *bd)
++{
++      u64 base[CONFIG_NR_DRAM_BANKS];
++      u64 size[CONFIG_NR_DRAM_BANKS];
++
++      /* fixup DT for the two DDR banks */
++      base[0] = gd->bd->bi_dram[0].start;
++      size[0] = gd->bd->bi_dram[0].size;
++      base[1] = gd->bd->bi_dram[1].start;
++      size[1] = gd->bd->bi_dram[1].size;
++
++      fdt_fixup_memory_banks(blob, base, size, 2);
++      ft_cpu_setup(blob, bd);
++
++      return 0;
++}
+diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
+new file mode 100644
+index 0000000..e27181c
+--- /dev/null
++++ b/configs/ls1012afrdm_qspi_defconfig
+@@ -0,0 +1,10 @@
++CONFIG_ARM=y
++CONFIG_TARGET_LS1012AFRDM=y
++CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
++# CONFIG_CMD_IMLS is not set
++CONFIG_SYS_NS16550=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
++CONFIG_OF_CONTROL=y
++CONFIG_DM=y
++CONFIG_SPI_FLASH=y
++CONFIG_DM_SPI=y
+diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
+new file mode 100644
+index 0000000..3231ab7
+--- /dev/null
++++ b/include/configs/ls1012afrdm.h
+@@ -0,0 +1,59 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++#ifndef __LS1012ARDB_H__
++#define __LS1012ARDB_H__
++
++#include "ls1012a_common.h"
++
++#define CONFIG_DIMM_SLOTS_PER_CTLR    1
++#define CONFIG_CHIP_SELECTS_PER_CTRL  1
++#define CONFIG_NR_DRAM_BANKS          2
++
++#define CONFIG_CMD_MEMINFO
++#define CONFIG_CMD_MEMTEST
++#define CONFIG_SYS_MEMTEST_START      0x80000000
++#define CONFIG_SYS_MEMTEST_END                0x9fffffff
++
++#define CONFIG_PHYLIB
++#define CONFIG_PHY_REALTEK
++/*
++* USB
++*/
++#define CONFIG_HAS_FSL_XHCI_USB
++
++#ifdef CONFIG_HAS_FSL_XHCI_USB
++#define CONFIG_USB_XHCI
++#define CONFIG_USB_XHCI_FSL
++#define CONFIG_USB_XHCI_DWC3
++#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
++#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
++#define CONFIG_CMD_USB
++#define CONFIG_USB_STORAGE
++#define CONFIG_CMD_EXT2
++
++#define CONFIG_USB_DWC3
++#define CONFIG_USB_DWC3_GADGET
++
++#define CONFIG_USB_GADGET
++#define CONFIG_USB_FUNCTION_MASS_STORAGE
++#define CONFIG_USB_GADGET_DOWNLOAD
++#define CONFIG_USB_GADGET_VBUS_DRAW 2
++#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
++#define CONFIG_G_DNL_VENDOR_NUM 0x1234
++#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
++#define CONFIG_USB_GADGET_DUALSPEED
++
++/* USB Gadget ums command */
++#define CONFIG_CMD_USB_MASS_STORAGE
++#endif
++
++#define CONFIG_CMD_MEMINFO
++#define CONFIG_CMD_MEMTEST
++#define CONFIG_SYS_MEMTEST_START      0x80000000
++#define CONFIG_SYS_MEMTEST_END                0x9fffffff
++
++#endif /* __LS1012ARDB_H__ */
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0040-DNCPE-138-CSU-config-for-PFE.patch b/package/boot/uboot-layerscape/patches/0040-DNCPE-138-CSU-config-for-PFE.patch
new file mode 100644 (file)
index 0000000..f77f8fa
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0040-DNCPE-138-CSU-config-for-PFE.patch
@@ -0,0 +1,36 @@
+From 0bfcfaafa23af0e8c9ae9df3236831fcaaa597b8 Mon Sep 17 00:00:00 2001
+From: Anji J <anji.jagarlmudi@freescale.com>
+Date: Mon, 4 Apr 2016 15:07:47 +0530
+Subject: [PATCH 40/93] DNCPE-138 CSU config for PFE
+
+Configure PFE for NS access.
+
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ .../include/asm/arch-fsl-layerscape/ns_access.h    |    2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+index 2fd33e1..5250ac7 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+@@ -25,6 +25,7 @@ enum csu_cslx_ind {
+       CSU_CSLX_PCIE3_IO,
+       CSU_CSLX_USB3 = 20,
+       CSU_CSLX_USB2,
++      CSU_CSLX_PFE = 23,
+       CSU_CSLX_SERDES = 32,
+       CSU_CSLX_QDMA,
+       CSU_CSLX_LPUART2,
+@@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = {
+        {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
+        {CSU_CSLX_USB3, CSU_ALL_RW},
+        {CSU_CSLX_USB2, CSU_ALL_RW},
++       {CSU_CSLX_PFE, CSU_ALL_RW},
+        {CSU_CSLX_SERDES, CSU_ALL_RW},
+        {CSU_CSLX_QDMA, CSU_ALL_RW},
+        {CSU_CSLX_LPUART2, CSU_ALL_RW},
+-- 
+1.7.9.5
+

diff --git a/package/boot/uboot-layerscape/patches/0041-DNCPE-4-LS1012A-PPFE-driver.patch b/package/boot/uboot-layerscape/patches/0041-DNCPE-4-LS1012A-PPFE-driver.patch
new file mode 100644 (file)
index 0000000..f2b157c
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0041-DNCPE-4-LS1012A-PPFE-driver.patch
@@ -0,0 +1,7589 @@
+From 487b9b2e5c767ee2110cce57539f0ebeb5a74872 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Tue, 24 May 2016 14:05:18 +0530
+Subject: [PATCH 41/93] DNCPE-4: LS1012A PPFE driver
+
+[context adjustment]
+
+- Ported PFE driver from LS1024
+- Did changes for GEMAC/MDIO/PHY
+- LS1012A address translation changes
+- Added pfe command  to the U-boot.
+- Added gemac_stat command
+- Added config PFE_START to conditionally start pfe on bootup time.
+- Change Rx packet ack model
+- Class firmware changes to ignore Rx error status
+
+- SCFG changes for pfe
+- Configure CCI-400 QoS settings
+- Configure transaction attributes
+- Configure RGMII port config
+
+Testing status on board
+
+RGMII - Works fine, can download file through tftp.
+SGMII - CRC errors are seen, but basic rx/tx works.
+
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/cpu.c            |    5 +
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |   42 +-
+ board/freescale/ls1012aqds/Makefile                |    1 +
+ board/freescale/ls1012aqds/eth.c                   |  199 +++
+ board/freescale/ls1012aqds/ls1012aqds.c            |    5 -
+ board/freescale/ls1012aqds/ls1012aqds.h            |  149 ++
+ board/freescale/ls1012aqds/ls1012aqds_qixis.h      |    2 +-
+ board/freescale/ls1012ardb/Makefile                |    1 +
+ board/freescale/ls1012ardb/eth.c                   |   68 +
+ board/freescale/ls1012ardb/ls1012ardb.c            |    4 -
+ common/Makefile                                    |    2 +
+ common/cmd_gemac_stat.c                            |  147 ++
+ common/cmd_pfe_commands.c                          |  983 ++++++++++++
+ drivers/net/Makefile                               |    1 +
+ drivers/net/pfe_eth/Makefile                       |    1 +
+ drivers/net/pfe_eth/class_sbl_elf.fw               |    1 +
+ drivers/net/pfe_eth/hal.h                          |   64 +
+ drivers/net/pfe_eth/pfe.c                          | 1677 ++++++++++++++++++++
+ drivers/net/pfe_eth/pfe/cbus.h                     |   74 +
+ drivers/net/pfe_eth/pfe/cbus/bmu.h                 |   37 +
+ drivers/net/pfe_eth/pfe/cbus/class_csr.h           |  206 +++
+ drivers/net/pfe_eth/pfe/cbus/emac.h                |  232 +++
+ drivers/net/pfe_eth/pfe/cbus/gpi.h                 |   60 +
+ drivers/net/pfe_eth/pfe/cbus/gpt.h                 |   11 +
+ drivers/net/pfe_eth/pfe/cbus/hif.h                 |   62 +
+ drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h           |   33 +
+ drivers/net/pfe_eth/pfe/cbus/tmu_csr.h             |  102 ++
+ drivers/net/pfe_eth/pfe/cbus/util_csr.h            |   43 +
+ drivers/net/pfe_eth/pfe/class.h                    |  142 ++
+ drivers/net/pfe_eth/pfe/class/ccu.h                |   10 +
+ drivers/net/pfe_eth/pfe/class/efet.h               |   21 +
+ drivers/net/pfe_eth/pfe/class/mac_hash.h           |   28 +
+ drivers/net/pfe_eth/pfe/class/perg.h               |   21 +
+ drivers/net/pfe_eth/pfe/class/vlan_hash.h          |   28 +
+ drivers/net/pfe_eth/pfe/gpt.h                      |   11 +
+ drivers/net/pfe_eth/pfe/pe.h                       |  147 ++
+ drivers/net/pfe_eth/pfe/pfe.h                      |  250 +++
+ drivers/net/pfe_eth/pfe/tmu.h                      |   48 +
+ drivers/net/pfe_eth/pfe/tmu/phy_queue.h            |   31 +
+ drivers/net/pfe_eth/pfe/tmu/sched.h                |   47 +
+ drivers/net/pfe_eth/pfe/tmu/shaper.h               |   19 +
+ drivers/net/pfe_eth/pfe/uart.h                     |   13 +
+ drivers/net/pfe_eth/pfe/util.h                     |   30 +
+ drivers/net/pfe_eth/pfe/util/eape.h                |   10 +
+ drivers/net/pfe_eth/pfe/util/efet.h                |   20 +
+ drivers/net/pfe_eth/pfe/util/inq.h                 |   10 +
+ drivers/net/pfe_eth/pfe_driver.c                   |  710 +++++++++
+ drivers/net/pfe_eth/pfe_driver.h                   |  141 ++
+ drivers/net/pfe_eth/pfe_eth.c                      |  521 ++++++
+ drivers/net/pfe_eth/pfe_eth.h                      |  161 ++
+ drivers/net/pfe_eth/pfe_firmware.c                 |  193 +++
+ drivers/net/pfe_eth/pfe_firmware.h                 |   20 +
+ drivers/net/pfe_eth/pfe_mod.h                      |  140 ++
+ drivers/net/pfe_eth/tmu_sbl_elf.fw                 |    1 +
+ drivers/net/pfe_eth/util_sbl_elf.fw                |    1 +
+ include/configs/ls1012a_common.h                   |   10 +
+ include/configs/ls1012aqds.h                       |   13 +-
+ include/configs/ls1012ardb.h                       |    6 +-
+ 58 files changed, 6994 insertions(+), 21 deletions(-)
+ create mode 100644 board/freescale/ls1012aqds/eth.c
+ create mode 100644 board/freescale/ls1012aqds/ls1012aqds.h
+ create mode 100644 board/freescale/ls1012ardb/eth.c
+ create mode 100644 common/cmd_gemac_stat.c
+ create mode 100644 common/cmd_pfe_commands.c
+ create mode 100644 drivers/net/pfe_eth/Makefile
+ create mode 100644 drivers/net/pfe_eth/class_sbl_elf.fw
+ create mode 100644 drivers/net/pfe_eth/hal.h
+ create mode 100644 drivers/net/pfe_eth/pfe.c
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/bmu.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/class_csr.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/emac.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/gpi.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/gpt.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/hif.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/util_csr.h
+ create mode 100644 drivers/net/pfe_eth/pfe/class.h
+ create mode 100644 drivers/net/pfe_eth/pfe/class/ccu.h
+ create mode 100644 drivers/net/pfe_eth/pfe/class/efet.h
+ create mode 100644 drivers/net/pfe_eth/pfe/class/mac_hash.h
+ create mode 100644 drivers/net/pfe_eth/pfe/class/perg.h
+ create mode 100644 drivers/net/pfe_eth/pfe/class/vlan_hash.h
+ create mode 100644 drivers/net/pfe_eth/pfe/gpt.h
+ create mode 100644 drivers/net/pfe_eth/pfe/pe.h
+ create mode 100644 drivers/net/pfe_eth/pfe/pfe.h
+ create mode 100644 drivers/net/pfe_eth/pfe/tmu.h
+ create mode 100644 drivers/net/pfe_eth/pfe/tmu/phy_queue.h
+ create mode 100644 drivers/net/pfe_eth/pfe/tmu/sched.h
+ create mode 100644 drivers/net/pfe_eth/pfe/tmu/shaper.h
+ create mode 100644 drivers/net/pfe_eth/pfe/uart.h
+ create mode 100644 drivers/net/pfe_eth/pfe/util.h
+ create mode 100644 drivers/net/pfe_eth/pfe/util/eape.h
+ create mode 100644 drivers/net/pfe_eth/pfe/util/efet.h
+ create mode 100644 drivers/net/pfe_eth/pfe/util/inq.h
+ create mode 100644 drivers/net/pfe_eth/pfe_driver.c
+ create mode 100644 drivers/net/pfe_eth/pfe_driver.h
+ create mode 100644 drivers/net/pfe_eth/pfe_eth.c
+ create mode 100644 drivers/net/pfe_eth/pfe_eth.h
+ create mode 100644 drivers/net/pfe_eth/pfe_firmware.c
+ create mode 100644 drivers/net/pfe_eth/pfe_firmware.h
+ create mode 100644 drivers/net/pfe_eth/pfe_mod.h
+ create mode 100644 drivers/net/pfe_eth/tmu_sbl_elf.fw
+ create mode 100644 drivers/net/pfe_eth/util_sbl_elf.fw
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+index 340d9f9..8f59577 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+@@ -573,6 +573,11 @@ int cpu_eth_init(bd_t *bis)
+ {
+       int error = 0;
+ 
++#if defined(CONFIG_FSL_PPFE) && !defined(CONFIG_CMD_PFE_START)
++      ls1012a_gemac_initialize(bis, 0 , "pfe_eth0");
++      ls1012a_gemac_initialize(bis, 1 , "pfe_eth1");
++#endif
++
+ #ifdef CONFIG_FSL_MC_ENET
+       error = fsl_mc_ldpaa_init(bis);
+ #endif
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index 6918757..a264f9a 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -41,6 +41,7 @@
+ #define CONFIG_SYS_PCIE1_ADDR                 (CONFIG_SYS_IMMR + 0x2400000)
+ #define CONFIG_SYS_PCIE2_ADDR                 (CONFIG_SYS_IMMR + 0x2500000)
+ #define CONFIG_SYS_PCIE3_ADDR                 (CONFIG_SYS_IMMR + 0x2600000)
++#define CONFIG_SYS_PPFE_ADDR                  (CONFIG_SYS_IMMR + 0x3000000)
+ #define CONFIG_SYS_SEC_MON_ADDR                       (CONFIG_SYS_IMMR + 0xe90000)
+ #define CONFIG_SYS_SFP_ADDR                   (CONFIG_SYS_IMMR + 0xe80200)
+ 
+@@ -364,6 +365,24 @@ struct ccsr_gur {
+ #define SCFG_SNPCNFGCR_USB3RDSNP      0x00002000
+ #define SCFG_SNPCNFGCR_USB3WRSNP      0x00004000
+ 
++/* RGMIIPCR bit definitions*/
++#define SCFG_RGMIIPCR_EN_AUTO         (0x00000008)
++#define SCFG_RGMIIPCR_SETSP_1000M     (0x00000004)
++#define SCFG_RGMIIPCR_SETSP_100M      (0x00000000)
++#define SCFG_RGMIIPCR_SETSP_10M               (0x00000002)
++#define SCFG_RGMIIPCR_SETFD           (0x00000001)
++
++/*PFEASBCR bit definitions */
++#define SCFG_PPFEASBCR_ARCACHE0               (0x80000000)
++#define SCFG_PPFEASBCR_AWCACHE0               (0x40000000)
++#define SCFG_PPFEASBCR_ARCACHE1               (0x20000000)
++#define SCFG_PPFEASBCR_AWCACHE1               (0x10000000)
++#define SCFG_PPFEASBCR_ARSNP          (0x08000000)
++#define SCFG_PPFEASBCR_AWSNP          (0x04000000)
++
++
++
++
+ /* Supplemental Configuration Unit */
+ struct ccsr_scfg {
+       u8 res_000[0x100-0x000];
+@@ -381,7 +400,12 @@ struct ccsr_scfg {
+       u8 res_140[0x158-0x140];
+       u32 altcbar;
+       u32 qspi_cfg;
+-      u8 res_160[0x180-0x160];
++      u8 res_160[0x164-0x160];
++      u32 wr_qos1;
++      u32 wr_qos2;
++      u32 rd_qos1;
++      u32 rd_qos2;
++      u8 res_174[0x180-0x174];
+       u32 dmamcr;
+       u8 res_184[0x18c-0x184];
+       u32 debug_icid;
+@@ -411,7 +435,21 @@ struct ccsr_scfg {
+       u32 usb_refclk_selcr1;
+       u32 usb_refclk_selcr2;
+       u32 usb_refclk_selcr3;
+-      u8 res_424[0x600-0x424];
++      u8 res_424[0x434-0x424];
++      u32 rgmiipcr;
++      u32 res_438;
++      u32 rgmiipsr;
++      u32 pfepfcssr1;
++      u32 pfeintencr1;
++      u32 pfepfcssr2;
++      u32 pfeintencr2;
++      u32 pfeerrcr;
++      u32 pfeeerrintencr;
++      u32 pfeasbcr;
++      u32 pfebsbcr;
++      u8 res_460[0x484-0x460];
++      u32 mdioselcr;
++      u8 res_468[0x600-0x468];
+       u32 scratchrw[4];
+       u8 res_610[0x680-0x610];
+       u32 corebcr;
+diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
+index 0b813f9..b18494a 100644
+--- a/board/freescale/ls1012aqds/Makefile
++++ b/board/freescale/ls1012aqds/Makefile
+@@ -5,3 +5,4 @@
+ #
+ 
+ obj-y += ls1012aqds.o
++obj-y += eth.o
+diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
+new file mode 100644
+index 0000000..1bd7c9d
+--- /dev/null
++++ b/board/freescale/ls1012aqds/eth.c
+@@ -0,0 +1,199 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <netdev.h>
++#include <fm_eth.h>
++#include <fsl_mdio.h>
++#include <malloc.h>
++#include <fsl_dtsec.h>
++#include <asm/arch/soc.h>
++#include <asm/arch-fsl-layerscape/config.h>
++#include <asm/arch/fsl_serdes.h>
++
++#include "../common/qixis.h"
++#include "../../../drivers/net/pfe_eth/pfe_eth.h"
++#include "ls1012aqds_qixis.h"
++#include <asm/arch-fsl-layerscape/immap_lsch2.h>
++
++#define EMI_NONE      0xFF
++#define EMI1_RGMII    1
++#define EMI1_SLOT1    2
++#define EMI1_SLOT2    3
++
++#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
++
++static int mdio_mux[NUM_FM_PORTS];
++
++static const char * const mdio_names[] = {
++      "NULL",
++      "LS1012AQDS_MDIO_RGMII",
++      "LS1012AQDS_MDIO_SLOT1",
++      "LS1012AQDS_MDIO_SLOT2",
++      "NULL",
++};
++
++static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval)
++{
++      return mdio_names[muxval];
++}
++
++struct ls1012aqds_mdio {
++      u8 muxval;
++      struct mii_dev *realbus;
++};
++
++static void ls1012aqds_mux_mdio(u8 muxval)
++{
++      u8 brdcfg4;
++
++      if (muxval < 7) {
++              brdcfg4 = QIXIS_READ(brdcfg[4]);
++              brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
++              brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
++              QIXIS_WRITE(brdcfg[4], brdcfg4);
++      }
++}
++
++static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
++                            int regnum)
++{
++      struct ls1012aqds_mdio *priv = bus->priv;
++
++      ls1012aqds_mux_mdio(priv->muxval);
++
++      return priv->realbus->read(priv->realbus, addr, devad, regnum);
++}
++
++static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
++                             int regnum, u16 value)
++{
++      struct ls1012aqds_mdio *priv = bus->priv;
++
++      ls1012aqds_mux_mdio(priv->muxval);
++
++      return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
++}
++
++static int ls1012aqds_mdio_reset(struct mii_dev *bus)
++{
++      struct ls1012aqds_mdio *priv = bus->priv;
++
++      if(priv->realbus->reset)
++              return priv->realbus->reset(priv->realbus);
++}
++
++static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
++{
++      struct ls1012aqds_mdio *pmdio;
++      struct mii_dev *bus = mdio_alloc();
++
++      if (!bus) {
++              printf("Failed to allocate ls1012aqds MDIO bus\n");
++              return -1;
++      }
++
++      pmdio = malloc(sizeof(*pmdio));
++      if (!pmdio) {
++              printf("Failed to allocate ls1012aqds private data\n");
++              free(bus);
++              return -1;
++      }
++
++      bus->read = ls1012aqds_mdio_read;
++      bus->write = ls1012aqds_mdio_write;
++      bus->reset = ls1012aqds_mdio_reset;
++      sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval));
++
++      pmdio->realbus = miiphy_get_dev_by_name(realbusname);
++
++      if (!pmdio->realbus) {
++              printf("No bus with name %s\n", realbusname);
++              free(bus);
++              free(pmdio);
++              return -1;
++      }
++
++      pmdio->muxval = muxval;
++      bus->priv = pmdio;
++      return mdio_register(bus);
++}
++
++int board_eth_init(bd_t *bis)
++{
++#ifdef CONFIG_FSL_PPFE
++        struct mii_dev *bus;
++      struct mdio_info mac1_mdio_info;
++      struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
++      u8 data8;
++
++
++      /*TODO Following config should be done for all boards, where is the right place to put this */
++      out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
++      out_be32(&scfg->pfebsbcr, in_be32(&scfg->pfebsbcr) | SCFG_PPFEASBCR_AWCACHE0);
++
++      /*CCI-400 QoS settings for PFE */
++      out_be32(&scfg->wr_qos1, 0x0ff00000);
++      out_be32(&scfg->rd_qos1, 0x0ff00000);
++
++      /* Set RGMII into 1G + Full duplex mode */
++      out_be32(&scfg->rgmiipcr, in_be32(&scfg->rgmiipcr) | (SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETFD));
++
++      out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x520), 0xFFFFFFFF);
++      out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x524), 0xFFFFFFFF);
++
++      ls1012aqds_mux_mdio(2);
++
++#ifdef RGMII_RESET_WA
++      /* Work around for FPGA registers initialization
++       * This is needed for RGMII to work */
++      printf("Reset RGMII WA....\n");
++      data8 = QIXIS_READ(rst_frc[0]);
++      data8 |= 0x2;
++      QIXIS_WRITE(rst_frc[0], data8);
++      data8 = QIXIS_READ(rst_frc[0]);
++
++      data8 = QIXIS_READ(res8[6]);
++      data8 |= 0xff;
++      QIXIS_WRITE(res8[6], data8);
++      data8 = QIXIS_READ(res8[6]);
++
++#endif
++
++      mac1_mdio_info.reg_base = (void *)0x04200000; /*EMAC1_BASE_ADDR*/
++      mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
++
++      bus = ls1012a_mdio_init(&mac1_mdio_info);
++      if(!bus)
++      {
++              printf("Failed to register mdio \n");
++              return -1;
++      }
++
++      /*Based on RCW config initialize correctly */
++      /*MAC2 */
++      if(ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII) < 0)
++      {
++              printf("Failed to register mdio for %s\n", ls1012aqds_mdio_name_for_muxval(EMI1_RGMII));
++              return -1;
++      }
++      ls1012a_set_mdio(1, miiphy_get_dev_by_name(ls1012aqds_mdio_name_for_muxval(EMI1_RGMII)));
++      ls1012a_set_phy_address_mode(1,  EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_RGMII);
++
++      /*MAC1 */
++      if(ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1) < 0)
++      {
++              printf("Failed to register mdio for %s\n", ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1));
++              return -1;
++      }
++      ls1012a_set_mdio(0, miiphy_get_dev_by_name(ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1)));
++      ls1012a_set_phy_address_mode(0,  EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
++
++      cpu_eth_init(bis);
++#endif
++      return pci_eth_init(bis);
++}
+diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
+index 446989b..b7365e8 100644
+--- a/board/freescale/ls1012aqds/ls1012aqds.c
++++ b/board/freescale/ls1012aqds/ls1012aqds.c
+@@ -211,11 +211,6 @@ int board_init(void)
+       return 0;
+ }
+ 
+-int board_eth_init(bd_t *bis)
+-{
+-      return pci_eth_init(bis);
+-}
+-
+ #ifdef CONFIG_OF_BOARD_SETUP
+ int ft_board_setup(void *blob, bd_t *bd)
+ {
+diff --git a/board/freescale/ls1012aqds/ls1012aqds.h b/board/freescale/ls1012aqds/ls1012aqds.h
+new file mode 100644
+index 0000000..42e10f5
+--- /dev/null
++++ b/board/freescale/ls1012aqds/ls1012aqds.h
+@@ -0,0 +1,149 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++#ifndef __LS1012AQDS_H__
++#define __LS1012AQDS_H__
++
++#include "ls1012a_common.h"
++
++
++#define CONFIG_DIMM_SLOTS_PER_CTLR    1
++#define CONFIG_CHIP_SELECTS_PER_CTRL  1
++#define CONFIG_NR_DRAM_BANKS          2
++
++#ifdef CONFIG_FSL_PPFE
++/*#define CONFIG_CMD_PFE_START */
++#define EMAC1_PHY_ADDR          0x1e
++#define EMAC2_PHY_ADDR          0x1
++#define CONFIG_PHYLIB
++#define CONFIG_PHY_VITESSE
++#define CONFIG_PHY_REALTEK
++#endif
++
++#define CONFIG_QIXIS_I2C_ACCESS
++#define CONFIG_SYS_I2C_FPGA_ADDR      0x66
++
++/*
++ * I2C bus multiplexer
++ */
++#define I2C_MUX_PCA_ADDR_PRI          0x77
++#define I2C_MUX_PCA_ADDR_SEC          0x76 /* Secondary multiplexer */
++#define I2C_RETIMER_ADDR              0x18
++#define I2C_MUX_CH_DEFAULT            0x8
++#define I2C_MUX_CH_CH7301             0xC
++#define I2C_MUX_CH5                   0xD
++#define I2C_MUX_CH7                   0xF
++
++#define I2C_MUX_CH_VOL_MONITOR 0xa
++
++/*
++* RTC configuration
++*/
++#define RTC
++#define CONFIG_RTC_PCF8563 1
++#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
++#define CONFIG_CMD_DATE
++
++/* EEPROM */
++#define CONFIG_ID_EEPROM
++#define CONFIG_CMD_EEPROM
++#define CONFIG_SYS_I2C_EEPROM_NXID
++#define CONFIG_SYS_EEPROM_BUS_NUM    0
++#define CONFIG_SYS_I2C_EEPROM_ADDR   0x57
++#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN     1
++#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
++#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
++
++
++/* Voltage monitor on channel 2*/
++#define I2C_VOL_MONITOR_ADDR           0x40
++#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
++#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
++#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
++
++
++/* DSPI */
++#define CONFIG_FSL_DSPI
++#define CONFIG_FSL_DSPI1
++#define CONFIG_DEFAULT_SPI_BUS 1
++
++#define CONFIG_CMD_SPI
++#define MMAP_DSPI          DSPI1_BASE_ADDR
++
++#define CONFIG_SYS_DSPI_CTAR0   1
++
++#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
++                              DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
++                              DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
++                              DSPI_CTAR_DT(0))
++#define CONFIG_SPI_FLASH_SST /* cs1 */
++
++#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
++                              DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
++                              DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
++                              DSPI_CTAR_DT(0))
++#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
++
++#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
++                              DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
++                              DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
++                              DSPI_CTAR_DT(0))
++#define CONFIG_SPI_FLASH_EON /* cs3 */
++
++#define CONFIG_SF_DEFAULT_SPEED      10000000
++#define CONFIG_SF_DEFAULT_MODE       SPI_MODE_0
++#define CONFIG_SF_DEFAULT_BUS        1
++#define CONFIG_SF_DEFAULT_CS         0
++
++/*
++* USB
++*/
++/* EHCI Support - disbaled by default */
++/*#define CONFIG_HAS_FSL_DR_USB*/
++
++#ifdef CONFIG_HAS_FSL_DR_USB
++#define CONFIG_USB_EHCI
++#define CONFIG_USB_EHCI_FSL
++#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
++#endif
++
++/*XHCI Support - enabled by default*/
++#define CONFIG_HAS_FSL_XHCI_USB
++
++#ifdef CONFIG_HAS_FSL_XHCI_USB
++#define CONFIG_USB_XHCI
++#define CONFIG_USB_XHCI_FSL
++#define CONFIG_USB_XHCI_DWC3
++#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
++#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
++#define CONFIG_CMD_USB
++#define CONFIG_USB_STORAGE
++#define CONFIG_CMD_EXT2
++
++#define CONFIG_USB_DWC3
++#define CONFIG_USB_DWC3_GADGET
++
++#define CONFIG_USB_GADGET
++#define CONFIG_USB_FUNCTION_MASS_STORAGE
++#define CONFIG_USB_GADGET_DOWNLOAD
++#define CONFIG_USB_GADGET_VBUS_DRAW 2
++#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
++#define CONFIG_G_DNL_VENDOR_NUM 0x1234
++#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
++#define CONFIG_USB_GADGET_DUALSPEED
++
++/* USB Gadget ums command */
++#define CONFIG_CMD_USB_MASS_STORAGE
++#endif
++
++#define CONFIG_CMD_MEMINFO
++#define CONFIG_CMD_MEMTEST
++#define CONFIG_SYS_MEMTEST_START      0x80000000
++#define CONFIG_SYS_MEMTEST_END                0x9fffffff
++
++#define CONFIG_MISC_INIT_R
++
++#endif /* __LS1012AQDS_H__ */
+diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
+index 584f604..7a1ba3d 100644
+--- a/board/freescale/ls1012aqds/ls1012aqds_qixis.h
++++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
+@@ -11,7 +11,7 @@
+ 
+ /* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+ #define BRDCFG4_EMISEL_MASK           0xe0
+-#define BRDCFG4_EMISEL_SHIFT          5
++#define BRDCFG4_EMISEL_SHIFT          6
+ 
+ /* SYSCLK */
+ #define QIXIS_SYSCLK_66                       0x0
+diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
+index 05fa9d9..bd80ce5 100644
+--- a/board/freescale/ls1012ardb/Makefile
++++ b/board/freescale/ls1012ardb/Makefile
+@@ -5,3 +5,4 @@
+ #
+ 
+ obj-y += ls1012ardb.o
++obj-y += eth.o
+diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
+new file mode 100644
+index 0000000..29830e8
+--- /dev/null
++++ b/board/freescale/ls1012ardb/eth.c
+@@ -0,0 +1,68 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier:   GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <netdev.h>
++#include <fm_eth.h>
++#include <fsl_mdio.h>
++#include <malloc.h>
++#include <fsl_dtsec.h>
++#include <asm/arch/soc.h>
++#include <asm/arch-fsl-layerscape/config.h>
++#include <asm/arch/fsl_serdes.h>
++
++#include "../../../drivers/net/pfe_eth/pfe_eth.h"
++#include <asm/arch-fsl-layerscape/immap_lsch2.h>
++
++#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
++
++int board_eth_init(bd_t *bis)
++{
++#ifdef CONFIG_FSL_PPFE
++        struct mii_dev *bus;
++      struct mdio_info mac1_mdio_info;
++      struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
++
++
++      /*TODO Following config should be done for all boards, where is the right place to put this */
++      out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
++      out_be32(&scfg->pfebsbcr, in_be32(&scfg->pfebsbcr) | SCFG_PPFEASBCR_AWCACHE0);
++
++      /*CCI-400 QoS settings for PFE */
++      out_be32(&scfg->wr_qos1, 0x0ff00000);
++      out_be32(&scfg->rd_qos1, 0x0ff00000);
++
++      /* Set RGMII into 1G + Full duplex mode */
++      out_be32(&scfg->rgmiipcr, in_be32(&scfg->rgmiipcr) | (SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETFD));
++
++
++      out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x520), 0xFFFFFFFF);
++      out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x524), 0xFFFFFFFF);
++
++      mac1_mdio_info.reg_base = (void *)0x04200000; /*EMAC1_BASE_ADDR*/
++      mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
++
++      bus = ls1012a_mdio_init(&mac1_mdio_info);
++      if(!bus)
++      {
++              printf("Failed to register mdio \n");
++              return -1;
++      }
++
++      /*MAC1 */
++      ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
++      ls1012a_set_phy_address_mode(0,  EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
++
++      /*MAC2 */
++      ls1012a_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
++      ls1012a_set_phy_address_mode(1,  EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_RGMII);
++
++
++      cpu_eth_init(bis);
++#endif
++      return pci_eth_init(bis);
++}
+diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
+index 347b8c8..90cbd5e 100644
+--- a/board/freescale/ls1012ardb/ls1012ardb.c
++++ b/board/freescale/ls1012ardb/ls1012ardb.c
+@@ -163,10 +163,6 @@ int dram_init(void)
+       return 0;
+ }
+ 
+-int board_eth_init(bd_t *bis)
+-{
+-      return pci_eth_init(bis);
+-}
+ 
+ int board_early_init_f(void)
+ {
+diff --git a/common/Makefile b/common/Makefile
+index 2a1d9f8..f5db77e 100644
+--- a/common/Makefile
++++ b/common/Makefile
+@@ -136,6 +136,8 @@ obj-$(CONFIG_CMD_MII) += cmd_mii.o
+ ifdef CONFIG_PHYLIB
+ obj-$(CONFIG_CMD_MII) += cmd_mdio.o
+ endif
++obj-$(CONFIG_CMD_PFE_COMMANDS) += cmd_pfe_commands.o
++obj-$(CONFIG_CMD_PFE_COMMANDS) += cmd_gemac_stat.o
+ obj-$(CONFIG_CMD_MISC) += cmd_misc.o
+ obj-$(CONFIG_CMD_MMC) += cmd_mmc.o
+ obj-$(CONFIG_CMD_MMC_SPI) += cmd_mmc_spi.o
+diff --git a/common/cmd_gemac_stat.c b/common/cmd_gemac_stat.c
+new file mode 100644
+index 0000000..49bb1aa
+--- /dev/null
++++ b/common/cmd_gemac_stat.c
+@@ -0,0 +1,147 @@
++/*
++ * (C) Copyright 2003
++ *  Author : Laurent Brando (Mindspeed Technologies)
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++/**
++ * @file
++ * @brief Retrieve GEMAC Statistics
++ */
++
++#include <common.h>
++#include <command.h>
++#include "../drivers/net/pfe_eth/pfe_eth.h"
++#include "../drivers/net/pfe_eth/pfe/pfe.h"
++#include "../drivers/net/pfe_eth/pfe_firmware.h"
++#include "../drivers/net/pfe_eth/pfe/cbus.h"
++#include "../drivers/net/pfe_eth/pfe/cbus/class_csr.h"
++#include "../drivers/net/pfe_eth/pfe/cbus/emac.h"
++
++#define ETH_GSTRING_LEN         32 /* from linux/include/ethtool.h */
++
++static const struct fec_stat {
++      char name[ETH_GSTRING_LEN];
++      u16 offset;
++} fec_stats[] = {
++      /* RMON TX */
++      { "tx_dropped", RMON_T_DROP },
++      { "tx_packets", RMON_T_PACKETS },
++      { "tx_broadcast", RMON_T_BC_PKT },
++      { "tx_multicast", RMON_T_MC_PKT },
++      { "tx_crc_errors", RMON_T_CRC_ALIGN },
++      { "tx_undersize", RMON_T_UNDERSIZE },
++      { "tx_oversize", RMON_T_OVERSIZE },
++      { "tx_fragment", RMON_T_FRAG },
++      { "tx_jabber", RMON_T_JAB },
++      { "tx_collision", RMON_T_COL },
++      { "tx_64byte", RMON_T_P64 },
++      { "tx_65to127byte", RMON_T_P65TO127 },
++      { "tx_128to255byte", RMON_T_P128TO255 },
++      { "tx_256to511byte", RMON_T_P256TO511 },
++      { "tx_512to1023byte", RMON_T_P512TO1023 },
++      { "tx_1024to2047byte", RMON_T_P1024TO2047 },
++      { "tx_GTE2048byte", RMON_T_P_GTE2048 },
++      { "tx_octets", RMON_T_OCTETS },
++
++      /* IEEE TX */
++      { "IEEE_tx_drop", IEEE_T_DROP },
++      { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
++      { "IEEE_tx_1col", IEEE_T_1COL },
++      { "IEEE_tx_mcol", IEEE_T_MCOL },
++      { "IEEE_tx_def", IEEE_T_DEF },
++      { "IEEE_tx_lcol", IEEE_T_LCOL },
++      { "IEEE_tx_excol", IEEE_T_EXCOL },
++      { "IEEE_tx_macerr", IEEE_T_MACERR },
++      { "IEEE_tx_cserr", IEEE_T_CSERR },
++      { "IEEE_tx_sqe", IEEE_T_SQE },
++      { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
++      { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
++
++      /* RMON RX */
++      { "rx_packets", RMON_R_PACKETS },
++      { "rx_broadcast", RMON_R_BC_PKT },
++      { "rx_multicast", RMON_R_MC_PKT },
++      { "rx_crc_errors", RMON_R_CRC_ALIGN },
++      { "rx_undersize", RMON_R_UNDERSIZE },
++      { "rx_oversize", RMON_R_OVERSIZE },
++      { "rx_fragment", RMON_R_FRAG },
++      { "rx_jabber", RMON_R_JAB },
++      { "rx_64byte", RMON_R_P64 },
++      { "rx_65to127byte", RMON_R_P65TO127 },
++      { "rx_128to255byte", RMON_R_P128TO255 },
++      { "rx_256to511byte", RMON_R_P256TO511 },
++      { "rx_512to1023byte", RMON_R_P512TO1023 },
++      { "rx_1024to2047byte", RMON_R_P1024TO2047 },
++      { "rx_GTE2048byte", RMON_R_P_GTE2048 },
++      { "rx_octets", RMON_R_OCTETS },
++
++      /* IEEE RX */
++      { "IEEE_rx_drop", IEEE_R_DROP },
++      { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
++      { "IEEE_rx_crc", IEEE_R_CRC },
++      { "IEEE_rx_align", IEEE_R_ALIGN },
++      { "IEEE_rx_macerr", IEEE_R_MACERR },
++      { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
++      { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
++};
++
++static void ls1012a_emac_print_stats(void *base)
++{
++      int i;
++
++      for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
++              printf("%s: %d\n", fec_stats[i].name, readl(base + fec_stats[i].offset));
++}
++
++static int gemac_stats(cmd_tbl_t *cmdtp, int flag, int argc,
++                     char * const argv[])
++{
++      void *gemac_base = NULL;
++
++      if (argc != 2) {
++              printf("Usage: \n" "gemac_stat [ethx]\n");
++              return CMD_RET_SUCCESS;
++      }
++
++      if ( strcmp(argv[1], "eth0") == 0)
++              gemac_base = (void *)EMAC1_BASE_ADDR;
++      else if ( strcmp(argv[1], "eth1") == 0)
++              gemac_base = (void *)EMAC2_BASE_ADDR;
++
++      if (gemac_base)
++      {
++              ls1012a_emac_print_stats(gemac_base);
++      }
++      else
++      {
++              printf("no such net device: %s\n", argv[1]);
++              return 1;
++      }
++
++      return 0;
++}
++
++U_BOOT_CMD(
++      gemac_stat,     2,      1,      gemac_stats,
++      "retrieve GEMAC statistics",
++      "Usage: \n"
++      "gemac_stat [ethx]\n"
++);
+diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
+new file mode 100644
+index 0000000..f9f92c7
+--- /dev/null
++++ b/common/cmd_pfe_commands.c
+@@ -0,0 +1,983 @@
++/*
++ * (C) Copyright 2012
++ *  Author : Bill Westland (Mindspeed Technologies)
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++/**
++ * @file
++ * @brief PFE utility commands
++ */
++
++#include <common.h>
++#include <command.h>
++#include "../drivers/net/pfe_eth/pfe_eth.h"
++#include "../drivers/net/pfe_eth/pfe/pfe.h"
++#include "../drivers/net/pfe_eth/pfe_firmware.h"
++#include "../drivers/net/pfe_eth/pfe/cbus/class_csr.h"
++#include "../drivers/net/pfe_eth/pfe/cbus/gpi.h"
++DECLARE_GLOBAL_DATA_PTR;
++
++int pfe_load_elf(int pe_mask, const struct firmware *fw);
++int ls1012a_gemac_initialize(bd_t * bis, int dev_id, char *devname);
++
++static void pfe_command_help(void)
++{
++      printf("Usage: pfe [start | firmware | load | lib | pe | gemac | gem | gpi | class | tmu | util | hif | status | expt | fftest] <options>\n");
++}
++
++static void pfe_command_firmware(int argc, char * const argv[])
++{
++      if (argc == 3 && strcmp(argv[2], "init") == 0)
++      {
++              pfe_firmware_init((u8 *)0x80100000, (u8 *)0x80180000, (u8 *)0x80200000);
++      }
++      else if (argc == 3 && strcmp(argv[2], "exit") == 0)
++      {
++              pfe_firmware_exit();
++      }
++      else
++      {
++              if (argc >= 3 && strcmp(argv[2], "help") != 0)
++              {
++                      printf("Unknown option: %s\n", argv[2]);
++              }
++              printf("Usage: pfe firmware [init | exit]\n");
++      }
++}
++
++static void pfe_command_load(int argc, char * const argv[])
++{
++      if (argc >= 3 && strcmp(argv[2], "elf") == 0)
++      {
++              if (argc == 5)
++              {
++                      u32 mask;
++                      unsigned long image_start;
++                      struct firmware fw;
++                      mask = simple_strtoul(argv[3], NULL, 0);
++                      image_start = simple_strtoul(argv[4], NULL, 16);
++                      fw.data = (u8 *)image_start;
++                      pfe_load_elf(mask, &fw);
++              }
++              else
++              {
++                      printf("Usage: pfe load elf <pe_mask> <image_start>\n");
++              }
++      }
++      else
++      {
++              if (argc >= 3 && strcmp(argv[2], "help") != 0)
++              {
++                      printf("Unknown option: %s\n", argv[2]);
++              }
++              printf("Usage: pfe load elf <parameters>\n");
++      }
++}
++#if 0
++static void pfe_command_lib(int argc, char *argv[])
++{
++      if (argc >= 3 && strcmp(argv[2], "init") == 0)
++      {
++              if (argc == 3)
++                      pfe_lib_init((void *)COMCERTO_AXI_HFE_CFG_BASE, (void *)CONFIG_DDR_BASEADDR, CONFIG_DDR_PHYS_BASEADDR);
++              else if (argc == 6)
++              {
++                      u32 cbus_base;
++                      u32 ddr_base;
++                      u32 ddr_phys_base;
++                      cbus_base = simple_strtoul(argv[3], NULL, 16);
++                      ddr_base = simple_strtoul(argv[4], NULL, 16);
++                      ddr_phys_base = simple_strtoul(argv[5], NULL, 16);
++                      pfe_lib_init((void *)cbus_base, (void *)ddr_base, ddr_phys_base);
++              }
++              else
++              {
++                      printf("Usage: pfe lib init [<cbus_base> <ddr_base> <ddr_phys_base>]\n");
++              }
++      }
++      else
++      {
++              if (argc >= 3 && strcmp(argv[2], "help") != 0)
++              {
++                      printf("Unknown option: %s\n", argv[2]);
++              }
++              printf("Usage: pfe lib init <parameters>\n");
++      }
++}
++#endif
++static void pfe_command_pe(int argc, char * const argv[])
++{
++      if (argc >= 3 && strcmp(argv[2], "pmem") == 0)
++      {
++              if (argc >= 4 && strcmp(argv[3], "read") == 0)
++              {
++                      int i;
++                      int num;
++                      int id;
++                      u32 addr;
++                      u32 size;
++                      u32 val;
++                      if (argc == 7)
++                              num = simple_strtoul(argv[6], NULL, 0);
++                      else if (argc == 6)
++                              num = 1;
++                      else
++                      {
++                              printf("Usage: pfe pe pmem read <id> <addr> [<num>]\n");
++                              return;
++                      }
++                      id = simple_strtoul(argv[4], NULL, 0);
++                      addr = simple_strtoul(argv[5], NULL, 16);
++                      size = 4;
++                      for (i = 0; i < num; i++, addr += 4)
++                      {
++                              val = pe_pmem_read(id, addr, size);
++                              val = be32_to_cpu(val);
++                              if(!(i&3)) printf("%08x: ", addr);
++                              printf("%08x%s", val, i == num - 1 || (i & 3) == 3 ? "\n" : " ");
++                      }
++              }
++              else
++              {
++                      printf("Usage: pfe pe pmem read <parameters>\n");
++              }
++      }
++      else if (argc >= 3 && strcmp(argv[2], "dmem") == 0)
++      {
++              if (argc >= 4 && strcmp(argv[3], "read") == 0)
++              {
++                      int i;
++                      int num;
++                      int id;
++                      u32 addr;
++                      u32 size;
++                      u32 val;
++                      if (argc == 7)
++                              num = simple_strtoul(argv[6], NULL, 0);
++                      else if (argc == 6)
++                              num = 1;
++                      else
++                      {
++                              printf("Usage: pfe pe dmem read <id> <addr> [<num>]\n");
++                              return;
++                      }
++                      id = simple_strtoul(argv[4], NULL, 0);
++                      addr = simple_strtoul(argv[5], NULL, 16);
++                      size = 4;
++                      for (i = 0; i < num; i++, addr += 4)
++                      {
++                              val = pe_dmem_read(id, addr, size);
++                              val = be32_to_cpu(val);
++                              if(!(i&3)) printf("%08x: ", addr);
++                              printf("%08x%s", val, i == num - 1 || (i & 3) == 3 ? "\n" : " ");
++                      }
++              }
++              else if (argc >= 4 && strcmp(argv[3], "write") == 0)
++              {
++                      int id;
++                      u32 val;
++                      u32 addr;
++                      u32 size;
++                      if (argc != 7)
++                      {
++                              printf("Usage: pfe pe dmem write <id> <val> <addr>\n");
++                              return;
++                      }
++                      id = simple_strtoul(argv[4], NULL, 0);
++                      val = simple_strtoul(argv[5], NULL, 16);
++                      val = cpu_to_be32(val);
++                      addr = simple_strtoul(argv[6], NULL, 16);
++                      size = 4;
++                      pe_dmem_write(id, val, addr, size);
++              }
++              else
++              {
++                      printf("Usage: pfe pe dmem [read | write] <parameters>\n");
++              }
++      }
++      else if (argc >= 3 && strcmp(argv[2], "lmem") == 0)
++      {
++              if (argc >= 4 && strcmp(argv[3], "read") == 0)
++              {
++                      int i;
++                      int num;
++                      u32 val;
++                      u32 offset;
++                      if (argc == 6)
++                              num = simple_strtoul(argv[5], NULL, 0);
++                      else if (argc == 5)
++                              num = 1;
++                      else
++                      {
++                              printf("Usage: pfe pe lmem read <offset> [<num>]\n");
++                              return;
++                      }
++                      offset = simple_strtoul(argv[4], NULL, 16);
++                      for (i = 0; i < num; i++, offset += 4)
++                      {
++                              pe_lmem_read(&val, 4, offset);
++                              val = be32_to_cpu(val);
++                              printf("%08x%s", val, i == num - 1 || (i & 7) == 7 ? "\n" : " ");
++                      }
++              }
++              else if (argc >= 4 && strcmp(argv[3], "write") == 0)
++              {
++                      u32 val;
++                      u32 offset;
++                      if (argc != 6)
++                      {
++                              printf("Usage: pfe pe lmem write <val> <offset>\n");
++                              return;
++                      }
++                      val = simple_strtoul(argv[4], NULL, 16);
++                      val = cpu_to_be32(val);
++                      offset = simple_strtoul(argv[5], NULL, 16);
++                      pe_lmem_write(&val, 4, offset);
++              }
++              else
++              {
++                      printf("Usage: pfe pe lmem [read | write] <parameters>\n");
++              }
++      }
++      else
++      {
++              if (strcmp(argv[2], "help") != 0)
++              {
++                      printf("Unknown option: %s\n", argv[2]);
++              }
++              printf("Usage: pfe pe <parameters>\n");
++      }
++      //void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned int len)
++      //void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
++      //void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
++      //int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr)
++}
++
++#if 0
++static void pfe_command_gemac(int argc, char *argv[])
++{
++void gemac_init(void *base, void *cfg)
++void gemac_set_speed(void *base, MAC_SPEED gem_speed)
++void gemac_set_duplex(void *base, int duplex)
++void gemac_set_mode(void *base, int mode)
++void gemac_reset(void *base)
++void gemac_enable(void *base)
++void gemac_disable(void *base)
++void gemac_set_address(void *base, SPEC_ADDR *addr)
++SPEC_ADDR gemac_get_address(void *base)
++void gemac_set_laddr1(void *base, MAC_ADDR *address)
++void gemac_set_laddr2(void *base, MAC_ADDR *address)
++void gemac_set_laddr3(void *base, MAC_ADDR *address)
++void gemac_set_laddr4(void *base, MAC_ADDR *address)
++void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index)
++void gemac_allow_broadcast(void *base)
++void gemac_no_broadcast(void *base)
++void gemac_enable_unicast(void *base)
++void gemac_disable_unicast(void *base)
++void gemac_enable_multicast(void *base)
++void gemac_disable_multicast(void *base)
++void gemac_enable_fcs_rx(void *base)
++void gemac_disable_fcs_rx(void *base)
++void gemac_enable_1536_rx(void *base)
++void gemac_disable_1536_rx(void *base)
++void gemac_enable_pause_rx(void *base)
++void gemac_disable_pause_rx(void *base)
++void gemac_set_config(void *base, GEMAC_CFG *cfg)
++unsigned int * gemac_get_stats(void *base)
++}
++#endif
++
++#if 0
++static void pfe_command_gem(int argc, char *argv[])
++{
++MAC_ADDR gem_get_laddr1(void *base)
++MAC_ADDR gem_get_laddr2(void *base)
++MAC_ADDR gem_get_laddr3(void *base)
++MAC_ADDR gem_get_laddr4(void *base)
++MAC_ADDR gem_get_laddrN(void *base, unsigned int entry_index)
++}
++#endif
++
++#if 0
++static void pfe_command_gpi(int argc, char *argv[])
++{
++void gpi_init(void *base, GPI_CFG *cfg)
++void gpi_reset(void *base)
++void gpi_enable(void *base)
++void gpi_disable(void *base)
++void gpi_set_config(void *base, GPI_CFG *cfg)
++}
++#endif
++
++#if 1
++static void pfe_command_class(int argc, char * const argv[])
++{
++      if (argc >= 3 && strcmp(argv[2], "init") == 0)
++      {
++              CLASS_CFG cfg;
++              if (argc == 3)
++              {
++#define CONFIG_DDR_PHYS_BASEADDR      0x03800000
++                      cfg.route_table_hash_bits = ROUTE_TABLE_HASH_BITS;
++                      cfg.route_table_baseaddr = CONFIG_DDR_PHYS_BASEADDR + ROUTE_TABLE_BASEADDR;
++              }
++              else if (argc == 5)
++              {
++                      cfg.route_table_hash_bits = simple_strtoul(argv[3], NULL, 16);
++                      cfg.route_table_baseaddr = simple_strtoul(argv[4], NULL, 16);
++              }
++              else
++              {
++                      printf("Usage: pfe class init <route_table_hash_bits> <route_table_baseaddr>\n");
++              }
++              class_init(&cfg);
++      }
++      else if (argc == 3 && strcmp(argv[2], "reset") == 0)
++      {
++              class_reset();
++      }
++      else if (argc == 3 && strcmp(argv[2], "enable") == 0)
++      {
++              class_enable();
++      }
++      else if (argc == 3 && strcmp(argv[2], "disable") == 0)
++      {
++              class_disable();
++      }
++      else if (argc >= 3 && strcmp(argv[2], "config") == 0)
++      {
++              CLASS_CFG cfg;
++              if (argc == 3)
++              {
++                      cfg.route_table_hash_bits = ROUTE_TABLE_HASH_BITS;
++                      cfg.route_table_baseaddr = CONFIG_DDR_PHYS_BASEADDR + ROUTE_TABLE_BASEADDR;
++              }
++              else if (argc == 5)
++              {
++                      cfg.route_table_hash_bits = simple_strtoul(argv[3], NULL, 16);
++                      cfg.route_table_baseaddr = simple_strtoul(argv[4], NULL, 16);
++              }
++              else
++              {
++                      printf("Usage: pfe class config <route_table_hash_bits> <route_table_baseaddr>\n");
++              }
++              class_set_config(&cfg);
++      }
++      else if (argc >= 3 && strcmp(argv[2], "bus") == 0)
++      {
++              if (argc >= 4 && strcmp(argv[3], "read") == 0)
++              {
++                      u32 addr;
++                      u32 size;
++                      u32 val;
++                      if (argc != 6)
++                      {
++                              printf("Usage: pfe class bus read <addr> <size>\n");
++                              return;
++                      }
++                      addr = simple_strtoul(argv[4], NULL, 16);
++                      size = simple_strtoul(argv[5], NULL, 16);
++                      val = class_bus_read(addr, size);
++                      printf("%08x\n", val);
++              }
++              else if (argc >= 4 && strcmp(argv[3], "write") == 0)
++              {
++                      u32 val;
++                      u32 addr;
++                      u32 size;
++                      if (argc != 7)
++                      {
++                              printf("Usage: pfe class bus write <val> <addr> <size>\n");
++                              return;
++                      }
++                      val = simple_strtoul(argv[4], NULL, 16);
++                      addr = simple_strtoul(argv[5], NULL, 16);
++                      size = simple_strtoul(argv[6], NULL, 16);
++                      class_bus_write(val, addr, size);
++              }
++              else
++              {
++                      printf("Usage: pfe class bus [read | write] <parameters>\n");
++              }
++      }
++      else
++      {
++              if (argc >= 3 && strcmp(argv[2], "help") != 0)
++              {
++                      printf("Unknown option: %s\n", argv[2]);
++              }
++              printf("Usage: pfe class [init | reset | enable | disable | config | bus] <parameters>\n");
++      }
++}
++
++static void pfe_command_tmu(int argc, char * const argv[])
++{
++      if (argc >= 3 && strcmp(argv[2], "init") == 0)
++      {
++              if (argc == 5)
++              {
++                      TMU_CFG cfg;
++                      cfg.llm_base_addr = simple_strtoul(argv[3], NULL, 16);
++                      cfg.llm_queue_len = simple_strtoul(argv[4], NULL, 16);
++                      tmu_init(&cfg);
++              }
++              else
++              {
++                      printf("Usage: pfe tmu init <llm_base_addr> <llm_queue_len>\n");
++              }
++      }
++      else if (argc >= 3 && strcmp(argv[2], "enable") == 0)
++      {
++              if (argc == 4)
++              {
++                      u32 mask;
++                      mask = simple_strtoul(argv[3], NULL, 16);
++                      tmu_enable(mask);
++              }
++              else
++              {
++                      printf("Usage: pfe tmu enable <pe_mask>\n");
++              }
++      }
++      else if (argc >= 3 && strcmp(argv[2], "disable") == 0)
++      {
++              if (argc == 4)
++              {
++                      u32 mask;
++                      mask = simple_strtoul(argv[3], NULL, 16);
++                      tmu_disable(mask);
++              }
++              else
++              {
++                      printf("Usage: pfe tmu disable <pe_mask>\n");
++              }
++      }
++      else
++      {
++              if (argc >= 3 && strcmp(argv[2], "help") != 0)
++              {
++                      printf("Unknown option: %s\n", argv[2]);
++              }
++              printf("Usage: pfe tmu [init | enable | disable] <parameters>\n");
++      }
++}
++#endif
++
++/** qm_read_drop_stat
++ * This function is used to read the drop statistics from the TMU
++ * hw drop counter.  Since the hw counter is always cleared afer
++ * reading, this function maintains the previous drop count, and
++ * adds the new value to it.  That value can be retrieved by
++ * passing a pointer to it with the total_drops arg.
++ *
++ * @param tmu           TMU number (0 - 3)
++ * @param queue         queue number (0 - 15)
++ * @param total_drops   pointer to location to store total drops (or NULL)
++ * @param do_reset      if TRUE, clear total drops after updating
++ *
++ */
++
++u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset)
++{
++#define NUM_QUEUES            16
++      static u32 qtotal[TMU_MAX_ID + 1][NUM_QUEUES];
++      u32 val;
++      writel((tmu << 8) | queue, TMU_TEQ_CTRL);
++      writel((tmu << 8) | queue, TMU_LLM_CTRL);
++      val = readl(TMU_TEQ_DROP_STAT);
++      qtotal[tmu][queue] += val;
++      if (total_drops)
++              *total_drops = qtotal[tmu][queue];
++      if (do_reset)
++              qtotal[tmu][queue] = 0;
++      return val;
++}
++
++static ssize_t tmu_queue_stats(char *buf, int tmu, int queue)
++{
++      ssize_t len = 0;
++      u32 drops;
++
++      printf("%d-%02d, ", tmu, queue);
++
++      drops = qm_read_drop_stat(tmu, queue, NULL, 0);
++
++      /* Select queue */
++      writel((tmu << 8) | queue, TMU_TEQ_CTRL);
++      writel((tmu << 8) | queue, TMU_LLM_CTRL);
++
++      printf("(teq) drop: %10u, tx: %10u (llm) head: %08x, tail: %08x, drop: %10u\n",
++                      drops, readl(TMU_TEQ_TRANS_STAT),
++                      readl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR),
++                      readl(TMU_LLM_QUE_DROPCNT));
++
++      return len;
++}
++
++
++static ssize_t tmu_queues(char *buf, int tmu)
++{
++      ssize_t len = 0;
++      int queue;
++
++      for (queue = 0; queue < 16; queue++)
++              len += tmu_queue_stats(buf + len, tmu, queue);
++
++      return len;
++}
++
++void hif_status(void)
++{
++      printf("hif:\n");
++
++      printf("  tx curr bd:    %x\n", readl(HIF_TX_CURR_BD_ADDR));
++      printf("  tx status:     %x\n", readl(HIF_TX_STATUS));
++      printf("  tx dma status: %x\n", readl(HIF_TX_DMA_STATUS));
++
++      printf("  rx curr bd:    %x\n", readl(HIF_RX_CURR_BD_ADDR));
++      printf("  rx status:     %x\n", readl(HIF_RX_STATUS));
++      printf("  rx dma status: %x\n", readl(HIF_RX_DMA_STATUS));
++
++      printf("hif nocopy:\n");
++
++      printf("  tx curr bd:    %x\n", readl(HIF_NOCPY_TX_CURR_BD_ADDR));
++      printf("  tx status:     %x\n", readl(HIF_NOCPY_TX_STATUS));
++      printf("  tx dma status: %x\n", readl(HIF_NOCPY_TX_DMA_STATUS));
++
++      printf("  rx curr bd:    %x\n", readl(HIF_NOCPY_RX_CURR_BD_ADDR));
++      printf("  rx status:     %x\n", readl(HIF_NOCPY_RX_STATUS));
++      printf("  rx dma status: %x\n", readl(HIF_NOCPY_RX_DMA_STATUS));
++}
++
++static void  gpi(int id, void *base)
++{
++        u32 val;
++
++        printf("gpi%d:\n  ", id);
++
++        printf("  tx under stick: %x\n", readl(base + GPI_FIFO_STATUS));
++        val = readl(base + GPI_FIFO_DEBUG);
++        printf("  tx pkts:        %x\n", (val >> 23) & 0x3f);
++        printf("  rx pkts:        %x\n", (val >> 18) & 0x3f);
++        printf("  tx bytes:       %x\n", (val >> 9) & 0x1ff);
++        printf("  rx bytes:       %x\n", (val >> 0) & 0x1ff);
++        printf("  overrun:        %x\n", readl(base + GPI_OVERRUN_DROPCNT));
++}
++
++void  bmu(int id, void *base)
++{
++      printf("bmu: %d\n", id);
++      printf("  buf size:  %x\n", (1 << readl(base + BMU_BUF_SIZE)));
++      printf("  buf count: %x\n", readl(base + BMU_BUF_CNT));
++      printf("  buf rem:   %x\n", readl(base + BMU_REM_BUF_CNT));
++      printf("  buf curr:  %x\n", readl(base + BMU_CURR_BUF_CNT));
++      printf("  free err:  %x\n", readl(base + BMU_FREE_ERR_ADDR));
++}
++
++#define       PESTATUS_ADDR_CLASS     0x800
++#define       PESTATUS_ADDR_TMU       0x80
++#define       PESTATUS_ADDR_UTIL      0x0
++
++static void pfe_pe_status(int argc, char * const argv[])
++{
++      int do_clear = 0;
++      int j;
++      u32 id;
++      u32 dmem_addr;
++      u32 cpu_state;
++      u32 activity_counter;
++      u32 rx;
++      u32 tx;
++      u32 drop;
++      char statebuf[5];
++      u32 class_debug_reg = 0;
++      u32 debug_indicator;
++      u32 debug[16];
++
++      if (argc == 4 && strcmp(argv[3], "clear") == 0)
++              do_clear = 1;
++
++      for (id = CLASS0_ID; id < MAX_PE; id++)
++      {
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++              if (id == UTIL_ID)
++              {
++                      printf("util:\n");
++                      dmem_addr = PESTATUS_ADDR_UTIL;
++              }
++              else if (id >= TMU0_ID)
++#else
++              if (id >= TMU0_ID)
++#endif
++              {
++                      if (id == TMU2_ID)
++                              continue;
++                      if (id == TMU0_ID)
++                              printf("tmu:\n");
++                      dmem_addr = PESTATUS_ADDR_TMU;
++              }
++              else
++              {
++                      if (id == CLASS0_ID)
++                              printf("class:\n");
++                      dmem_addr = PESTATUS_ADDR_CLASS;
++                      class_debug_reg = readl(CLASS_PE0_DEBUG + id * 4);
++              }
++              cpu_state = pe_dmem_read(id, dmem_addr, 4);
++              dmem_addr += 4;
++              memcpy(statebuf, (char *)&cpu_state, 4);
++              statebuf[4] = '\0';
++              activity_counter = pe_dmem_read(id, dmem_addr, 4);
++              dmem_addr += 4;
++              rx = pe_dmem_read(id, dmem_addr, 4);
++              if (do_clear)
++                      pe_dmem_write(id, 0, dmem_addr, 4);
++              dmem_addr += 4;
++              tx = pe_dmem_read(id, dmem_addr, 4);
++              if (do_clear)
++                      pe_dmem_write(id, 0, dmem_addr, 4);
++              dmem_addr += 4;
++              drop = pe_dmem_read(id, dmem_addr, 4);
++              if (do_clear)
++                      pe_dmem_write(id, 0, dmem_addr, 4);
++              dmem_addr += 4;
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++              if (id == UTIL_ID)
++              {
++                      printf("state=%4s ctr=%08x rx=%x tx=%x\n",
++                                      statebuf, cpu_to_be32(activity_counter),
++                                      cpu_to_be32(rx), cpu_to_be32(tx));
++              }
++              else
++#endif
++              if (id >= TMU0_ID)
++              {
++                      printf("%d: state=%4s ctr=%08x rx=%x qstatus=%x\n",
++                                      id - TMU0_ID, statebuf, cpu_to_be32(activity_counter),
++                                      cpu_to_be32(rx), cpu_to_be32(tx));
++              }
++              else
++              {
++                      printf("%d: pc=1%04x ldst=%04x state=%4s ctr=%08x rx=%x tx=%x drop=%x\n",
++                                      id - CLASS0_ID, class_debug_reg & 0xFFFF, class_debug_reg >> 16,
++                                      statebuf, cpu_to_be32(activity_counter),
++                                      cpu_to_be32(rx), cpu_to_be32(tx), cpu_to_be32(drop));
++              }
++              debug_indicator = pe_dmem_read(id, dmem_addr, 4);
++              dmem_addr += 4;
++              if (debug_indicator == cpu_to_be32('DBUG'))
++              {
++                      int last = 0;
++                      for (j = 0; j < 16; j++)
++                      {
++                              debug[j] = pe_dmem_read(id, dmem_addr, 4);
++                              if (debug[j])
++                              {
++                                      last = j + 1;
++                                      if (do_clear)
++                                              pe_dmem_write(id, 0, dmem_addr, 4);
++                              }
++                              dmem_addr += 4;
++                      }
++                      for (j = 0; j < last; j++)
++                      {
++                              printf("%08x%s", cpu_to_be32(debug[j]), (j & 0x7) == 0x7 || j == last - 1 ? "\n" : " ");
++                      }
++              }
++      }
++
++}
++
++static void pfe_command_status(int argc, char * const argv[])
++{
++
++      if (argc >= 3 && strcmp(argv[2], "pe") == 0)
++      {
++              pfe_pe_status(argc, argv);
++      }
++      else if (argc == 3 && strcmp(argv[2], "bmu") == 0)
++      {
++              bmu(1, BMU1_BASE_ADDR);
++              bmu(2, BMU2_BASE_ADDR);
++      }
++      else if (argc == 3 && strcmp(argv[2], "hif") == 0)
++      {
++              hif_status();
++      }
++      else if (argc == 3 && strcmp(argv[2], "gpi") == 0)
++      {
++              gpi(0, EGPI1_BASE_ADDR);
++              gpi(1, EGPI2_BASE_ADDR);
++              gpi(3, HGPI_BASE_ADDR);
++      }
++      else if (argc == 3 && strcmp(argv[2], "tmu0_queues") == 0)
++      {
++              tmu_queues(NULL, 0);
++      }
++      else if (argc == 3 && strcmp(argv[2], "tmu1_queues") == 0)
++      {
++              tmu_queues(NULL, 1);
++      }
++      else if (argc == 3 && strcmp(argv[2], "tmu3_queues") == 0)
++      {
++              tmu_queues(NULL, 3);
++      }
++      else
++              printf("Usage: pfe status [pe <clear> | bmu | gpi | hif | tmuX_queues ]\n");
++
++      return;
++}
++
++
++#define EXPT_DUMP_ADDR 0x1fa8
++#define EXPT_REG_COUNT 20
++static const char *register_names[EXPT_REG_COUNT] = {
++              "  pc", "ECAS", " EID", "  ED",
++              "  sp", "  r1", "  r2", "  r3",
++              "  r4", "  r5", "  r6", "  r7",
++              "  r8", "  r9", " r10", " r11",
++              " r12", " r13", " r14", " r15"
++};
++
++static void pfe_command_expt(int argc, char * const argv[])
++{
++      unsigned int id, i, val, addr;
++
++      if (argc == 3)
++      {
++              id = simple_strtoul(argv[2], NULL, 0);
++              addr = EXPT_DUMP_ADDR;
++              printf("Exception information for PE %d:\n", id);
++              for (i = 0; i < EXPT_REG_COUNT; i++)
++              {
++                      val = pe_dmem_read(id, addr, 4);
++                      val = be32_to_cpu(val);
++                      printf("%s:%08x%s", register_names[i], val, (i & 3) == 3 ? "\n" : " ");
++                      addr += 4;
++              }
++      }
++      else
++      {
++              printf("Usage: pfe expt <id>\n");
++      }
++}
++
++static void pfe_command_util(int argc, char * const argv[])
++{
++      if (argc == 3 && strcmp(argv[2], "init") == 0)
++      {
++              UTIL_CFG cfg;
++              util_init(&cfg);
++      }
++      else if (argc == 3 && strcmp(argv[2], "reset") == 0)
++      {
++              util_reset();
++      }
++      else if (argc == 3 && strcmp(argv[2], "enable") == 0)
++      {
++              util_enable();
++      }
++      else if (argc == 3 && strcmp(argv[2], "disable") == 0)
++      {
++              util_disable();
++      }
++      else if (argc >= 3 && strcmp(argv[2], "bus") == 0)
++              {
++                      if (argc >= 4 && strcmp(argv[3], "read") == 0)
++                      {
++                              u32 addr;
++                              u32 size;
++                              u32 val;
++                              if (argc != 6)
++                              {
++                                      printf("Usage: pfe util bus read <addr> <size>\n");
++                                      return;
++                              }
++                              addr = simple_strtoul(argv[4], NULL, 16);
++                              size = simple_strtoul(argv[5], NULL, 16);
++                              val = util_bus_read(addr, size);
++                              printf("%08x\n", val);
++                      }
++                      else if (argc >= 4 && strcmp(argv[3], "write") == 0)
++                      {
++                              u32 val;
++                              u32 addr;
++                              u32 size;
++                              if (argc != 7)
++                              {
++                                      printf("Usage: pfe util bus write <val> <addr> <size>\n");
++                                      return;
++                              }
++                              val = simple_strtoul(argv[4], NULL, 16);
++                              addr = simple_strtoul(argv[5], NULL, 16);
++                              size = simple_strtoul(argv[6], NULL, 16);
++                              util_bus_write(val, addr, size);
++                      }
++                      else
++                      {
++                              printf("Usage: pfe util bus [read | write] <parameters>\n");
++                      }
++              }
++      else
++      {
++              if (argc >= 3 && strcmp(argv[2], "help") != 0)
++              {
++                      printf("Unknown option: %s\n", argv[2]);
++              }
++              printf("Usage: pfe util [init | reset | enable | disable | bus] <parameters>\n");
++      }
++}
++
++#if 0
++static void pfe_command_hif(int argc, char *argv[])
++{
++void hif_nocpy_init(void)
++void hif_init(void)
++void hif_tx_enable(void)
++void hif_tx_disable(void)
++void hif_rx_enable(void)
++void hif_rx_disable(void)
++}
++#endif
++
++#define ROUTE_TABLE_START     (CONFIG_DDR_PHYS_BASEADDR+ROUTE_TABLE_BASEADDR)
++static void pfe_command_fftest(int argc, char * const argv[])
++{
++      bd_t *bd = gd->bd;
++      struct eth_device *edev_eth0;
++      struct eth_device *edev_eth1;
++
++
++      // open eth0 and eth1 
++      edev_eth0 = eth_get_dev_by_name("pfe_eth0");
++      if (!edev_eth0)
++      {
++              printf("Cannot access eth0\n");
++              return;
++      }
++
++      if (eth_write_hwaddr(edev_eth0, "eth", edev_eth0->index))
++              puts("\nWarning: failed to set MAC address for c2000_gemac0\n");
++
++      if (edev_eth0->state != ETH_STATE_ACTIVE)
++      {
++              if (edev_eth0->init(edev_eth0, bd) < 0) {
++                      printf("eth0 init failed\n");
++                      return;
++              }
++              edev_eth0->state = ETH_STATE_ACTIVE;
++      }
++
++      edev_eth1 = eth_get_dev_by_name("pfe_eth1");
++      if (!edev_eth1)
++      {
++              printf("Cannot access eth1\n");
++              return;
++      }
++
++      if (eth_write_hwaddr(edev_eth1, "eth", edev_eth1->index))
++              puts("\nWarning: failed to set MAC address for c2000_gemac1\n");
++
++      if (edev_eth1->state != ETH_STATE_ACTIVE)
++      {
++              if (edev_eth1->init(edev_eth1, bd) < 0) {
++                      printf("eth1 init failed\n");
++                      return;
++              }
++              edev_eth1->state = ETH_STATE_ACTIVE;
++      }
++
++}
++
++#ifdef CONFIG_CMD_PFE_START
++static void pfe_command_start(int argc, char * const argv[])
++{
++      printf("Starting PFE \n");
++      ls1012a_gemac_initialize(gd->bd, 0 , "pfe_eth0");
++      ls1012a_gemac_initialize(gd->bd, 1 , "pfe_eth1");
++}
++#endif
++
++
++static int pfe_command(cmd_tbl_t *cmdtp, int flag, int argc,
++                     char * const argv[])
++{
++      if (argc == 1 || strcmp(argv[1], "help") == 0)
++      {
++              pfe_command_help();
++              return CMD_RET_SUCCESS;
++      }
++      if (strcmp(argv[1], "firmware") == 0)
++              pfe_command_firmware(argc, argv);
++      else if (strcmp(argv[1], "load") == 0)
++              pfe_command_load(argc, argv);
++#if 0
++      else if (strcmp(argv[1], "lib") == 0)
++              pfe_command_lib(argc, argv);
++#endif
++      else if (strcmp(argv[1], "pe") == 0)
++              pfe_command_pe(argc, argv);
++#if 0
++      else if (strcmp(argv[1], "gemac") == 0)
++              pfe_command_gemac(argc, argv);
++      else if (strcmp(argv[1], "gem") == 0)
++              pfe_command_gem(argc, argv);
++      else if (strcmp(argv[1], "gpi") == 0)
++              pfe_command_gpi(argc, argv);
++#endif
++#if 1
++      else if (strcmp(argv[1], "class") == 0)
++              pfe_command_class(argc, argv);
++      else if (strcmp(argv[1], "tmu") == 0)
++              pfe_command_tmu(argc, argv);
++#endif
++      else if (strcmp(argv[1], "status") == 0)
++              pfe_command_status(argc, argv);
++      else if (strcmp(argv[1], "expt") == 0)
++              pfe_command_expt(argc, argv);
++      else if (strcmp(argv[1], "util") == 0)
++              pfe_command_util(argc, argv);
++#if 0
++      else if (strcmp(argv[1], "hif") == 0)
++              pfe_command_hif(argc, argv);
++#endif
++      else if (strcmp(argv[1], "fftest") == 0)
++              pfe_command_fftest(argc, argv);
++#ifdef CONFIG_CMD_PFE_START
++      else if (strcmp(argv[1], "start") == 0)
++              pfe_command_start(argc, argv);
++#endif
++      else
++      {
++              printf("Unknown option: %s\n", argv[1]);
++              pfe_command_help();
++              return CMD_RET_FAILURE;
++      }
++      return CMD_RET_SUCCESS;
++}
++
++
++U_BOOT_CMD(
++      pfe,    7,      1,      pfe_command,
++      "Performs PFE lib utility functions",
++      "Usage: \n"
++      "pfe <options>"
++);
+diff --git a/drivers/net/Makefile b/drivers/net/Makefile
+index 150470c..c683b8f 100644
+--- a/drivers/net/Makefile
++++ b/drivers/net/Makefile
+@@ -72,3 +72,4 @@ obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
+ obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
+ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
+ obj-$(CONFIG_VSC9953) += vsc9953.o
++obj-$(CONFIG_FSL_PPFE) += pfe_eth/
+diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
+new file mode 100644
+index 0000000..1af837d
+--- /dev/null
++++ b/drivers/net/pfe_eth/Makefile
+@@ -0,0 +1 @@
++obj-y += pfe_eth.o pfe_firmware.o pfe.o pfe_driver.o
+diff --git a/drivers/net/pfe_eth/class_sbl_elf.fw b/drivers/net/pfe_eth/class_sbl_elf.fw
+new file mode 100644
+index 0000000..3745d9a
+--- /dev/null
++++ b/drivers/net/pfe_eth/class_sbl_elf.fw
+@@ -0,0 +1 @@
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+\ No newline at end of file
+diff --git a/drivers/net/pfe_eth/hal.h b/drivers/net/pfe_eth/hal.h
+new file mode 100644
+index 0000000..e795fe6
+--- /dev/null
++++ b/drivers/net/pfe_eth/hal.h
+@@ -0,0 +1,64 @@
++/*
++ *  (C) Copyright 2011
++ *  Author : Mindspeed Technologes
++ *  
++ *  See file CREDITS for list of people who contributed to this
++ *  project.
++ *
++ *  This program is free software; you can redistribute it and/or
++ *  modify it under the terms of the GNU General Public License as
++ *  published by the Free Software Foundation; either version 2 of
++ *  the License, or (at your option) any later version.
++ *  
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *  
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ *  MA 02111-1307 USA
++ * */
++
++#ifndef _HAL_H_
++#define _HAL_H_
++
++#if defined(CONFIG_PLATFORM_PCI)  
++/* For ChipIT */
++
++#include <linux/types.h>
++#include <linux/elf.h>
++#include <linux/errno.h>
++#include <linux/pci.h>
++#include <asm/io.h>
++#include <linux/slab.h>
++#include <linux/firmware.h>
++
++
++#define free(x)  kfree(x)
++#define xzalloc(x)  kmalloc(x, GFP_DMA)
++#define printf  printk
++
++//#define dprint(fmt, arg...) printk(fmt, ##arg)
++#define dprint(fmt, arg...)   
++
++#else
++
++#include <linux/types.h>
++#include <elf.h>
++#include <common.h>
++//#include <errno.h>
++#include <asm/byteorder.h>
++#include <miiphy.h>
++#include <malloc.h>
++#include <asm/io.h>
++
++
++#include "pfe_eth.h"
++
++#endif
++
++
++#endif /* _HAL_H_ */
++
+diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
+new file mode 100644
+index 0000000..3b5570a
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe.c
+@@ -0,0 +1,1677 @@
++#include "hal.h"
++#include "pfe/pfe.h"
++
++void *cbus_base_addr;
++void *ddr_base_addr;
++unsigned long ddr_phys_base_addr;
++#if 0
++#define dprintf(fmt, arg...) printf(fmt, ##arg)
++#else
++#define dprintf(fmt, arg...)
++#endif
++static struct pe_info pe[MAX_PE];
++
++/** Initializes the PFE library.
++* Must be called before using any of the library functions.
++*
++* @param[in] cbus_base                CBUS virtual base address (as mapped in the host CPU address space)
++* @param[in] ddr_base         DDR virtual base address (as mapped in the host CPU address space)
++* @param[in] ddr_phys_base    DDR physical base address (as mapped in platform)
++*/
++void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base)
++{
++      cbus_base_addr = cbus_base;
++      ddr_base_addr = ddr_base;
++      ddr_phys_base_addr = ddr_phys_base;
++
++      pe[CLASS0_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(0);
++      pe[CLASS0_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(0);
++      pe[CLASS0_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
++      pe[CLASS0_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
++      pe[CLASS0_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
++      pe[CLASS0_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
++
++      pe[CLASS1_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(1);
++      pe[CLASS1_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(1);
++      pe[CLASS1_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
++      pe[CLASS1_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
++      pe[CLASS1_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
++      pe[CLASS1_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
++
++      pe[CLASS2_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(2);
++      pe[CLASS2_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(2);
++      pe[CLASS2_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
++      pe[CLASS2_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
++      pe[CLASS2_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
++      pe[CLASS2_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
++
++      pe[CLASS3_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(3);
++      pe[CLASS3_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(3);
++      pe[CLASS3_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
++      pe[CLASS3_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
++      pe[CLASS3_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
++      pe[CLASS3_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
++
++#if !defined(CONFIG_PLATFORM_PCI)
++      pe[CLASS4_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(4);
++      pe[CLASS4_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(4);
++      pe[CLASS4_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
++      pe[CLASS4_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
++      pe[CLASS4_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
++      pe[CLASS4_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
++
++      pe[CLASS5_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(5);
++      pe[CLASS5_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(5);
++      pe[CLASS5_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
++      pe[CLASS5_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
++      pe[CLASS5_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
++      pe[CLASS5_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
++#endif
++      pe[TMU0_ID].dmem_base_addr = (u32)TMU_DMEM_BASE_ADDR(0);
++      pe[TMU0_ID].pmem_base_addr = (u32)TMU_IMEM_BASE_ADDR(0);
++      pe[TMU0_ID].pmem_size = (u32)TMU_IMEM_SIZE;
++      pe[TMU0_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
++      pe[TMU0_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
++      pe[TMU0_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
++
++#if !defined(CONFIG_TMU_DUMMY)
++      pe[TMU1_ID].dmem_base_addr = (u32)TMU_DMEM_BASE_ADDR(1);
++      pe[TMU1_ID].pmem_base_addr = (u32)TMU_IMEM_BASE_ADDR(1);
++      pe[TMU1_ID].pmem_size = (u32)TMU_IMEM_SIZE;
++      pe[TMU1_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
++      pe[TMU1_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
++      pe[TMU1_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
++
++#if !defined(CONFIG_LS1012A)
++      pe[TMU2_ID].dmem_base_addr = (u32)TMU_DMEM_BASE_ADDR(2);
++      pe[TMU2_ID].pmem_base_addr = (u32)TMU_IMEM_BASE_ADDR(2);
++      pe[TMU2_ID].pmem_size = (u32)TMU_IMEM_SIZE;
++      pe[TMU2_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
++      pe[TMU2_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
++      pe[TMU2_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
++#endif
++
++      pe[TMU3_ID].dmem_base_addr = (u32)TMU_DMEM_BASE_ADDR(3);
++      pe[TMU3_ID].pmem_base_addr = (u32)TMU_IMEM_BASE_ADDR(3);
++      pe[TMU3_ID].pmem_size = (u32)TMU_IMEM_SIZE;
++      pe[TMU3_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
++      pe[TMU3_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
++      pe[TMU3_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
++#endif
++
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++      pe[UTIL_ID].dmem_base_addr = (u32)UTIL_DMEM_BASE_ADDR;
++      pe[UTIL_ID].mem_access_wdata = (void *)UTIL_MEM_ACCESS_WDATA;
++      pe[UTIL_ID].mem_access_addr = (void *)UTIL_MEM_ACCESS_ADDR;
++      pe[UTIL_ID].mem_access_rdata = (void *)UTIL_MEM_ACCESS_RDATA;
++#endif
++}
++
++
++/** Writes a buffer to PE internal memory from the host
++ * through indirect access registers.
++ *
++ * @param[in] id              PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] src             Buffer source address
++ * @param[in] mem_access_addr DMEM destination address (must be 32bit aligned)
++ * @param[in] len             Number of bytes to copy
++ */
++void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned int len)
++{
++      u32 offset = 0, val, addr;
++      unsigned int len32 = len >> 2;
++      int i;
++
++      addr = mem_access_addr | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(0, 4);
++
++      for (i = 0; i < len32; i++, offset += 4, src += 4) {
++              val = *(u32 *)src;
++              writel(cpu_to_be32(val), pe[id].mem_access_wdata);
++              writel(addr + offset, pe[id].mem_access_addr);
++      }
++
++      if ((len = (len & 0x3))) {
++              val = 0;
++
++              addr = (mem_access_addr | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset;
++
++              for (i = 0; i < len; i++, src++)
++                      val |= (*(u8 *)src) << (8 * i);
++
++              writel(cpu_to_be32(val), pe[id].mem_access_wdata);
++              writel(addr, pe[id].mem_access_addr);
++      }
++}
++
++/** Writes a buffer to PE internal data memory (DMEM) from the host
++ * through indirect access registers.
++ * @param[in] id              PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] src             Buffer source address
++ * @param[in] dst             DMEM destination address (must be 32bit aligned)
++ * @param[in] len             Number of bytes to copy
++ */
++void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
++{
++      pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst | PE_MEM_ACCESS_DMEM, src, len);
++}
++
++
++/** Writes a buffer to PE internal program memory (PMEM) from the host
++ * through indirect access registers.
++ * @param[in] id              PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
++ * @param[in] src             Buffer source address
++ * @param[in] dst             PMEM destination address (must be 32bit aligned)
++ * @param[in] len             Number of bytes to copy
++ */
++void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
++{
++      pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size - 1)) | PE_MEM_ACCESS_IMEM, src, len);
++}
++
++
++/** Reads PE internal program memory (IMEM) from the host
++ * through indirect access registers.
++ * @param[in] id              PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
++ * @param[in] addr            PMEM read address (must be aligned on size)
++ * @param[in] size            Number of bytes to read (maximum 4, must not cross 32bit boundaries)
++ * @return                    the data read (in PE endianess, i.e BE).
++ */
++u32 pe_pmem_read(int id, u32 addr, u8 size)
++{
++      u32 offset = addr & 0x3;
++      u32 mask = 0xffffffff >> ((4 - size) << 3);
++      u32 val;
++
++      addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1)) | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_IMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++      writel(addr, pe[id].mem_access_addr);
++      val = be32_to_cpu(readl(pe[id].mem_access_rdata));
++
++      return (val >> (offset << 3)) & mask;
++}
++
++
++/** Writes PE internal data memory (DMEM) from the host
++ * through indirect access registers.
++ * @param[in] id              PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] addr            DMEM write address (must be aligned on size)
++ * @param[in] val             Value to write (in PE endianess, i.e BE)
++ * @param[in] size            Number of bytes to write (maximum 4, must not cross 32bit boundaries)
++ */
++void pe_dmem_write(int id, u32 val, u32 addr, u8 size)
++{
++      u32 offset = addr & 0x3;
++
++      addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++      /* Indirect access interface is byte swapping data being written */
++      writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata);
++      writel(addr, pe[id].mem_access_addr);
++}
++
++
++/** Reads PE internal data memory (DMEM) from the host
++ * through indirect access registers.
++ * @param[in] id              PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] addr            DMEM read address (must be aligned on size)
++ * @param[in] size            Number of bytes to read (maximum 4, must not cross 32bit boundaries)
++ * @return                    the data read (in PE endianess, i.e BE).
++ */
++u32 pe_dmem_read(int id, u32 addr, u8 size)
++{
++      u32 offset = addr & 0x3;
++      u32 mask = 0xffffffff >> ((4 - size) << 3);
++      u32 val;
++
++      addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++      writel(addr, pe[id].mem_access_addr);
++
++      /* Indirect access interface is byte swapping data being read */
++      val = be32_to_cpu(readl(pe[id].mem_access_rdata));
++
++      return (val >> (offset << 3)) & mask;
++}
++
++/** This function is used to write to CLASS internal bus peripherals (ccu, pe-lem) from the host
++* through indirect access registers.
++* @param[in]  val     value to write
++* @param[in]  addr    Address to write to (must be aligned on size)
++* @param[in]  size    Number of bytes to write (1, 2 or 4)
++*
++*/
++void class_bus_write(u32 val, u32 addr, u8 size)
++{
++      u32 offset = addr & 0x3;
++
++      writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
++
++      addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE | (size << 24);
++
++      writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA);
++      writel(addr, CLASS_BUS_ACCESS_ADDR);
++}
++
++
++/** Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host
++* through indirect access registers.
++* @param[in] addr     Address to read from (must be aligned on size)
++* @param[in] size     Number of bytes to read (1, 2 or 4)
++* @return             the read data
++*
++*/
++u32 class_bus_read(u32 addr, u8 size)
++{
++      u32 offset = addr & 0x3;
++      u32 mask = 0xffffffff >> ((4 - size) << 3);
++      u32 val;
++
++      writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
++
++      addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24);
++
++      writel(addr, CLASS_BUS_ACCESS_ADDR);
++      val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA));
++
++      return (val >> (offset << 3)) & mask;
++}
++
++/** Writes data to the cluster memory (PE_LMEM)
++* @param[in] dst      PE LMEM destination address (must be 32bit aligned)
++* @param[in] src      Buffer source address
++* @param[in] len      Number of bytes to copy
++*/
++void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len)
++{
++      u32 len32 = len >> 2;
++      int i;
++
++      for (i = 0; i < len32; i++, src += 4, dst += 4)
++              class_bus_write(*(u32 *)src, dst, 4);
++
++      if (len & 0x2)
++      {
++              class_bus_write(*(u16 *)src, dst, 2);
++              src += 2;
++              dst += 2;
++      }
++
++      if (len & 0x1)
++      {
++              class_bus_write(*(u8 *)src, dst, 1);
++              src++;
++              dst++;
++      }
++}
++
++/** Writes value to the cluster memory (PE_LMEM)
++* @param[in] dst      PE LMEM destination address (must be 32bit aligned)
++* @param[in] val      Value to write
++* @param[in] len      Number of bytes to write
++*/
++void class_pe_lmem_memset(u32 dst, int val, unsigned int len)
++{
++      u32 len32 = len >> 2;
++      int i;
++
++      val = val | (val << 8) | (val << 16) | (val << 24);
++      
++      for (i = 0; i < len32; i++, dst += 4)
++              class_bus_write(val, dst, 4);
++
++      if (len & 0x2)
++      {
++              class_bus_write(val, dst, 2);
++              dst += 2;
++      }
++
++      if (len & 0x1)
++      {
++              class_bus_write(val, dst, 1);
++              dst++;
++      }
++}
++
++/** Reads data from the cluster memory (PE_LMEM)
++* @param[out] dst             pointer to the source buffer data are copied to
++* @param[in] len              length in bytes of the amount of data to read from cluster memory
++* @param[in] offset   offset in bytes in the cluster memory where data are read from
++*/
++void pe_lmem_read(u32 *dst, u32 len, u32 offset)
++{
++      u32 len32 = len >> 2;
++      int i = 0;
++
++      for (i = 0; i < len32; dst++, i++, offset += 4)
++              *dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, 4);
++
++      /* FIXME we may have an out of bounds access on dst */
++      if (len & 0x03)
++              *dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, (len & 0x03));
++}
++
++/** Writes data to the cluster memory (PE_LMEM)
++* @param[in] src      pointer to the source buffer data are copied from
++* @param[in] len      length in bytes of the amount of data to write to the cluster memory
++* @param[in] offset   offset in bytes in the cluster memory where data are written to
++*/
++void pe_lmem_write(u32 *src, u32 len, u32 offset)
++{
++      u32 len32 = len >> 2;
++      int i = 0;
++
++      for (i = 0; i < len32; src++, i++, offset += 4)
++              class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, 4);
++
++      /* FIXME we may have an out of bounds access on src */
++      if (len & 0x03)
++              class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, (len & 0x03));
++}
++
++/** Writes UTIL program memory (DDR) from the host.
++ *
++ * @param[in] addr    Address to write (virtual, must be aligned on size)
++ * @param[in] val             Value to write (in PE endianess, i.e BE)
++ * @param[in] size            Number of bytes to write (2 or 4)
++ */
++static void util_pmem_write(u32 val, void *addr, u8 size)
++{
++      void *addr64 = (void *)((unsigned long)addr & ~0x7);
++      unsigned long off = 8 - ((unsigned long)addr & 0x7) - size;
++      
++      //IMEM should  be loaded as a 64bit swapped value in a 64bit aligned location
++      if (size == 4)
++              writel(be32_to_cpu(val), addr64 + off);
++      else
++              writew(be16_to_cpu((u16)val), addr64 + off);
++}
++
++
++/** Writes a buffer to UTIL program memory (DDR) from the host.
++ *
++ * @param[in] dst     Address to write (virtual, must be at least 16bit aligned)
++ * @param[in] src     Buffer to write (in PE endianess, i.e BE, must have same alignment as dst)
++ * @param[in] len     Number of bytes to write (must be at least 16bit aligned)
++ */
++static void util_pmem_memcpy(void *dst, const void *src, unsigned int len)
++{
++      unsigned int len32;
++      int i;
++
++      if ((unsigned long)src & 0x2) {
++              util_pmem_write(*(u16 *)src, dst, 2);
++              src += 2;
++              dst += 2;
++              len -= 2;
++      }
++
++      len32 = len >> 2;
++
++      for (i = 0; i < len32; i++, dst += 4, src += 4)
++              util_pmem_write(*(u32 *)src, dst, 4);
++
++      if (len & 0x2)
++              util_pmem_write(*(u16 *)src, dst, len & 0x2);
++}
++
++
++/** Loads an elf section into pmem
++ * Code needs to be at least 16bit aligned and only PROGBITS sections are supported
++ *
++ * @param[in] id      PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
++ * @param[in] data    pointer to the elf firmware
++ * @param[in] shdr    pointer to the elf section header
++ *
++ */
++static int pe_load_pmem_section(int id, const void *data, Elf32_Shdr *shdr)
++{
++      u32 offset = be32_to_cpu(shdr->sh_offset);
++      u32 addr = be32_to_cpu(shdr->sh_addr);
++      u32 size = be32_to_cpu(shdr->sh_size);
++      u32 type = be32_to_cpu(shdr->sh_type);
++
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++      if (id == UTIL_ID)
++      {
++              printf("%s: unsuported pmem section for UTIL\n", __func__);
++              return -1;
++      }
++#endif
++
++      if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
++      {
++              printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
++                      __func__, addr, (unsigned long) data + offset);
++
++              return -1;
++      }
++
++      if (addr & 0x1)
++      {
++              printf("%s: load address(%x) is not 16bit aligned\n", __func__, addr);
++              return -1;
++      }
++
++      if (size & 0x1)
++      {
++              printf("%s: load size(%x) is not 16bit aligned\n", __func__, size);
++              return -1;
++      }
++
++              dprintf("pmem pe%d @%x len %d\n",id, addr, size);
++      switch (type)
++        {
++        case SHT_PROGBITS:
++              pe_pmem_memcpy_to32(id, addr, data + offset, size);
++              break;
++
++      default:
++              printf("%s: unsuported section type(%x)\n", __func__, type);
++              return -1;
++              break;
++      }
++
++      return 0;
++}
++
++
++/** Loads an elf section into dmem
++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0
++ *
++ * @param[in] id              PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] data            pointer to the elf firmware
++ * @param[in] shdr            pointer to the elf section header
++ *
++ */
++static int pe_load_dmem_section(int id, const void *data, Elf32_Shdr *shdr)
++{
++      u32 offset = be32_to_cpu(shdr->sh_offset);
++      u32 addr = be32_to_cpu(shdr->sh_addr);
++      u32 size = be32_to_cpu(shdr->sh_size);
++      u32 type = be32_to_cpu(shdr->sh_type);
++      u32 size32 = size >> 2;
++      int i;
++
++      if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
++      {
++              printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
++                      __func__, addr, (unsigned long)data + offset);
++
++              return -1;
++      }
++
++      if (addr & 0x3)
++      {
++              printf("%s: load address(%x) is not 32bit aligned\n", __func__, addr);
++              return -1;
++      }
++
++      switch (type)
++        {
++        case SHT_PROGBITS:
++              dprintf("dmem pe%d @%x len %d\n",id, addr, size);
++              pe_dmem_memcpy_to32(id, addr, data + offset, size);
++              break;
++