PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
PKG_SOURCE_URL:=https://github.com/fsl-jyt/uboot-ls-32b.git
-PKG_SOURCE_VERSION:=4fbf7e76eb7671d9822d0310319f6ad70d324547
+PKG_SOURCE_VERSION:=719f8b606334bc73367f78c204dce69786963b65
PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
CONFIG=ls1043ardb-uboot.bin
endef
+define uboot/ls1012ardb
+ TITLE:=U-Boot binary $(PKG_NAME)-$(PKG_VERSION) for NXP ls1012ardb 32b Dev Board
+ CONFIG=ls1012ardb-uboot.bin.swap
+endef
+
UBOOTS := \
- ls1043ardb
+ ls1043ardb \
+ ls1012ardb
define Package/uboot/template
define Package/uboot-layerscape-32b-$(1)
CONFIG=ls1043ardb
endef
+define uboot/ls1012ardb
+ TITLE:=U-Boot $(PKG_NAME)-$(PKG_VERSION) for NXP ls1012ardb 64b Dev Board
+ CONFIG=ls1012ardb_qspi
+ IMAGE=u-boot-swap.bin
+endef
+
UBOOTS := \
- ls1043ardb
+ ls1043ardb \
+ ls1012ardb
define Package/uboot/template
define Package/uboot-layerscape-64b-$(1)
--- /dev/null
+From be06181f45695ce71536ecb461615ebf6f18011e Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Tue, 15 Mar 2016 13:40:07 +0530
+Subject: [PATCH 06/93] armv8: fsl-layerscape: Put SMMU config code in
+ SMMU_BASE
+
+It is not mandatory for Layerscape SoCs to have SMMU. SoCs like
+LS1012A are layerscape SoC without SMMU IP.
+
+So put SMMU configuration code under SMMU_BASE.
+
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+index 93f4a65..5f5bfb9 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
++++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+@@ -95,11 +95,13 @@ ENTRY(lowlevel_init)
+ bl ccn504_set_qos
+ #endif
+
++#ifdef SMMU_BASE
+ /* Set the SMMU page size in the sACR register */
+ ldr x1, =SMMU_BASE
+ ldr w0, [x1, #0x10]
+ orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
+ str w0, [x1, #0x10]
++#endif
+
+ /* Initialize GIC Secure Bank Status */
+ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+--
+1.7.9.5
+
--- /dev/null
+From 825d623c913c63b1f00c42f27ef0916b11d9f09f Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Tue, 15 Mar 2016 13:40:22 +0530
+Subject: [PATCH 07/93] armv8: fsl-layerscape: Avoid LS1043A specifc defines
+
+Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant.
+
+So Avoid LS1043A specific defines in arch/arm
+
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
+ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+index 92dcb72..23f0c88 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+@@ -314,7 +314,7 @@ int sata_init(void)
+ }
+ #endif
+
+-#elif defined(CONFIG_LS1043A)
++#elif defined(CONFIG_FSL_LSCH2)
+ #ifdef CONFIG_SCSI_AHCI_PLAT
+ int sata_init(void)
+ {
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+index d1fbde7..7096dac 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+@@ -55,7 +55,7 @@ enum srds {
+ FSL_SRDS_1 = 0,
+ FSL_SRDS_2 = 1,
+ };
+-#elif defined(CONFIG_LS1043A)
++#elif defined(CONFIG_FSL_LSCH2)
+ enum srds_prtcl {
+ NONE = 0,
+ PCIE1,
+--
+1.7.9.5
+
--- /dev/null
+From b3bbf1aeb0245a0f5565f669dd4b2f5f5be40d8a Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Wed, 16 Mar 2016 08:43:55 +0530
+Subject: [PATCH 08/93] armv8/ls1043a: Add the OCRAM initialization
+
+Clear the content to zero and the ECC error bit of OCRAM1/2.
+
+The OCRAM must be initialized to ZERO by the unit of 8-Byte before
+accessing it, or else it will generate ECC error. And the IBR has
+accessed the OCRAM before this initialization, so the ECC error
+status bit should to be cleared.
+
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/cpu/armv8/start.S | 39 +++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 39 insertions(+)
+
+diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
+index dd583c9..235213f 100644
+--- a/arch/arm/cpu/armv8/start.S
++++ b/arch/arm/cpu/armv8/start.S
+@@ -11,6 +11,9 @@
+ #include <asm/macro.h>
+ #include <asm/armv8/mmu.h>
+
++#define DCSR_SYS_DCFG_SBEESR2 0x20140534
++#define DCSR_SYS_DCFG_MBEESR2 0x20140544
++
+ /*************************************************************************
+ *
+ * Startup Code (reset vector)
+@@ -215,10 +218,46 @@ WEAK(lowlevel_init)
+ #endif /* CONFIG_ARMV8_MULTIENTRY */
+
+ 2:
++#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
++ bl fsl_ocram_init
++#endif
+ mov lr, x29 /* Restore LR */
+ ret
+ ENDPROC(lowlevel_init)
+
++#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
++ENTRY(fsl_ocram_init)
++ mov x28, lr /* Save LR */
++ bl fsl_clear_ocram
++ bl fsl_ocram_clear_ecc_err
++ mov lr, x28 /* Restore LR */
++ ret
++ENDPROC(fsl_ocram_init)
++
++ENTRY(fsl_clear_ocram)
++/* Clear OCRAM */
++ ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
++ ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
++ mov x2, #0
++clear_loop:
++ str x2, [x0]
++ add x0, x0, #8
++ cmp x0, x1
++ b.lo clear_loop
++ ret
++ENDPROC(fsl_clear_ocram)
++
++ENTRY(fsl_ocram_clear_ecc_err)
++ /* OCRAM1/2 ECC status bit */
++ mov w1, #0x60
++ ldr x0, =DCSR_SYS_DCFG_SBEESR2
++ str w1, [x0]
++ ldr x0, =DCSR_SYS_DCFG_MBEESR2
++ str w1, [x0]
++ ret
++ENDPROC(fsl_ocram_init)
++#endif
++
+ WEAK(smp_kick_all_cpus)
+ /* Kick secondary cpus up by SGI 0 interrupt */
+ mov x29, lr /* Save LR */
+--
+1.7.9.5
+
--- /dev/null
+From f022d8d9dc505ee917fef6c7109d67cc015a98fa Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Mon, 25 Apr 2016 16:05:36 +0530
+Subject: [PATCH 09/93] driver: mtd: spi: Adding support for QSPI Emulator
+
+Serial number and vendor id are added for The QSPI Emulator
+
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ drivers/mtd/spi/sf_params.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
+index 4f37e33..1424f2a 100644
+--- a/drivers/mtd/spi/sf_params.c
++++ b/drivers/mtd/spi/sf_params.c
+@@ -67,6 +67,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
+ {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP},
+ {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP},
+ {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
++ {"S25FS512S", 0x010220, 0x0102, 256 * 1024, 256, RD_FULL, WR_QPP},
+ {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP},
+ {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
+ {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP},
+--
+1.7.9.5
+
--- /dev/null
+From 27d1d5620ae352d230189fbea364198398065ae2 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Mon, 25 Apr 2016 16:06:48 +0530
+Subject: [PATCH 10/93] driver: mtd: spi: Adding support for QSPI flash
+
+Serial number and vendor id are added for QSPI flash
+common on both LS1012AQDS and LS1012ARDB.
+
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ drivers/mtd/spi/sf_params.c | 1 +
+ drivers/mtd/spi/spi_flash.c | 3 ++-
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
+index 1424f2a..1afb8b3 100644
+--- a/drivers/mtd/spi/sf_params.c
++++ b/drivers/mtd/spi/sf_params.c
+@@ -68,6 +68,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
+ {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP},
+ {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
+ {"S25FS512S", 0x010220, 0x0102, 256 * 1024, 256, RD_FULL, WR_QPP},
++ {"S25FS512S_256K", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL, WR_QPP},
+ {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP},
+ {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
+ {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP},
+diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
+index 2d23aee..865e929 100644
+--- a/drivers/mtd/spi/spi_flash.c
++++ b/drivers/mtd/spi/spi_flash.c
+@@ -1033,7 +1033,8 @@ int spi_flash_scan(struct spi_flash *flash)
+ * sector that is not overlaid by the parameter sectors.
+ * The uniform sector erase command has no effect on parameter sectors.
+ */
+- if (jedec == 0x0219 && (ext_jedec & 0xff00) == 0x4d00) {
++ if ((jedec == 0x0219 || (jedec == 0x0220)) &&
++ (ext_jedec & 0xff00) == 0x4d00) {
+ int ret;
+ u8 id[6];
+
+--
+1.7.9.5
+
--- /dev/null
+From 5a5108627b16ab33fb82c16e49ac926ef3a901b8 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Wed, 6 Apr 2016 17:44:22 +0530
+Subject: [PATCH 11/93] armv8: fsl-layerscape: fix compile warning "rcw_tmp"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: In function
+‘get_sys_info’:
+arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:29:6: warning:
+unused variable ‘rcw_tmp’ [-Wunused-variable]
+ u32 rcw_tmp;
+
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+index d301fff..078b087 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+@@ -25,7 +25,10 @@ void get_sys_info(struct sys_info *sys_info)
+ struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+ u32 ccr;
+ #endif
+-#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
++#if (defined(CONFIG_FSL_ESDHC) &&\
++ defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
++ defined(CONFIG_SYS_DPAA_FMAN)
++
+ u32 rcw_tmp;
+ #endif
+ struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
+--
+1.7.9.5
+
--- /dev/null
+From edc5b23b8dd04980e0fa48fe79ba811b775cd2c2 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Sat, 23 Apr 2016 12:34:59 +0530
+Subject: [PATCH 12/93] armv8: LSCH2 early and final mmu needs matching NS
+ attribute
+
+When switching between the early and final mmu tables, the stack will
+get corrupted if the Non-Secure attribute is different. For ls1043a,
+this issue is currently masked because flush_dcache_all is called
+before the switch when CONFIG_SYS_DPAA_FMAN is defined.
+
+Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+index a9dadfa..a7522da 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+@@ -159,9 +159,11 @@ static const struct sys_mmu_table early_mmu_table[] = {
+ { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+ CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+- CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
++ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
++ PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
++ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
++ PMD_SECT_OUTER_SHARE | PMD_SECT_NS},
+ #endif
+ };
+
+@@ -249,7 +251,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
+ CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
++ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
++ PMD_SECT_OUTER_SHARE | PMD_SECT_NS},
+ { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+ CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+@@ -260,7 +263,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
+ CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+ { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
+- CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
++ CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL,
++ PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+ #endif
+ };
+ #endif
+--
+1.7.9.5
+
--- /dev/null
+From 53ffd67d944fa23037e7f97e583fae300d4367f7 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Sat, 23 Apr 2016 15:23:52 +0530
+Subject: [PATCH 13/93] armv8: fsl-layerscape: Add support of QorIQ LS1012A
+ SoC
+
+[context adjustment]
+
+The QorIQ LS1012A processor, optimized for battery-backed or
+USB-powered, integrates a single ARM Cortex-A53 core with a hardware
+packet forwarding engine and high-speed interfaces to deliver
+line-rate networking performance.
+
+This patch add support of LS1012A SoC along with
+ - Update platform & DDR clock read logic as per SVR
+ - Define MMDC controller register set.
+ - Update LUT base address for PCIe
+ - Avoid L3 platform cache compilation
+ - Update USB address, errata
+ - SerDes table
+
+Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 ++
+ .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 24 +++++--
+ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +
+ arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c | 74 ++++++++++++++++++++
+ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 +-
+ arch/arm/include/asm/arch-fsl-layerscape/config.h | 32 +++++++++
+ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 1 +
+ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 1 +
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 ++
+ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 +
+ include/fsl_mmdc.h | 53 ++++++++++++++
+ include/linux/usb/xhci-fsl.h | 4 ++
+ 12 files changed, 199 insertions(+), 7 deletions(-)
+ create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
+ create mode 100644 include/fsl_mmdc.h
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+index 27bfeb1..03f73d1 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
++++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+@@ -33,3 +33,7 @@ endif
+ ifneq ($(CONFIG_LS1043A),)
+ obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
+ endif
++
++ifneq ($(CONFIG_LS1012A),)
++obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
++endif
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+index 078b087..63e5bed 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+@@ -33,6 +33,7 @@ void get_sys_info(struct sys_info *sys_info)
+ #endif
+ struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
+ unsigned int cpu;
++ unsigned int svr, ver;
+ const u8 core_cplx_pll[8] = {
+ [0] = 0, /* CC1 PPL / 1 */
+ [1] = 0, /* CC1 PPL / 2 */
+@@ -59,12 +60,20 @@ void get_sys_info(struct sys_info *sys_info)
+ sys_info->freq_ddrbus = sysclk;
+ #endif
+
+- sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
+- FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+- FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+- sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
+- FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
+- FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
++ svr = gur_in32(&gur->svr);
++ ver = SVR_SOC_VER(svr);
++ if (ver == SVR_LS1012) {
++ sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
++ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
++ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
++ } else {
++ sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
++ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
++ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
++ sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
++ FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
++ FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
++ }
+
+ for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
+ ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
+@@ -83,6 +92,9 @@ void get_sys_info(struct sys_info *sys_info)
+ freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+ }
+
++ if (ver == SVR_LS1012)
++ sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
++
+ #define HWA_CGA_M1_CLK_SEL 0xe0000000
+ #define HWA_CGA_M1_CLK_SHIFT 29
+ #ifdef CONFIG_SYS_DPAA_FMAN
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+index 5f5bfb9..b40834a 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
++++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+@@ -184,6 +184,7 @@ ENTRY(lowlevel_init)
+ ret
+ ENDPROC(lowlevel_init)
+
++#ifdef CONFIG_FSL_LSCH3
+ hnf_pstate_poll:
+ /* x0 has the desired status, return 0 for success, 1 for timeout
+ * clobber x1, x2, x3, x4, x6, x7
+@@ -261,6 +262,7 @@ ENTRY(__asm_flush_l3_cache)
+ mov lr, x29
+ ret
+ ENDPROC(__asm_flush_l3_cache)
++#endif
+
+ #ifdef CONFIG_MP
+ /* Keep literals not used by the secondary boot code outside it */
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
+new file mode 100644
+index 0000000..ff0903c
+--- /dev/null
++++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
+@@ -0,0 +1,74 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/arch/fsl_serdes.h>
++#include <asm/arch/immap_lsch2.h>
++
++struct serdes_config {
++ u32 protocol;
++ u8 lanes[SRDS_MAX_LANES];
++};
++
++static struct serdes_config serdes1_cfg_tbl[] = {
++ {0x2208, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, SATA1} },
++ {0x0008, {NONE, NONE, NONE, SATA1} },
++ {0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} },
++ {0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
++ {0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} },
++ {0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
++ {0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
++ {0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
++ {0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
++ {}
++};
++
++static struct serdes_config *serdes_cfg_tbl[] = {
++ serdes1_cfg_tbl,
++};
++
++enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
++{
++ struct serdes_config *ptr;
++
++ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
++ return 0;
++
++ ptr = serdes_cfg_tbl[serdes];
++ while (ptr->protocol) {
++ if (ptr->protocol == cfg)
++ return ptr->lanes[lane];
++ ptr++;
++ }
++
++ return 0;
++}
++
++int is_serdes_prtcl_valid(int serdes, u32 prtcl)
++{
++ int i;
++ struct serdes_config *ptr;
++
++ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
++ return 0;
++
++ ptr = serdes_cfg_tbl[serdes];
++ while (ptr->protocol) {
++ if (ptr->protocol == prtcl)
++ break;
++ ptr++;
++ }
++
++ if (!ptr->protocol)
++ return 0;
++
++ for (i = 0; i < SRDS_MAX_LANES; i++) {
++ if (ptr->lanes[i] != NONE)
++ return 1;
++ }
++
++ return 0;
++}
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+index 23f0c88..ec561a7 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+@@ -12,8 +12,10 @@
+ #include <asm/io.h>
+ #include <asm/global_data.h>
+ #include <asm/arch-fsl-layerscape/config.h>
++#ifdef CONFIG_SYS_FSL_DDR
+ #include <fsl_ddr_sdram.h>
+ #include <fsl_ddr.h>
++#endif
+ #ifdef CONFIG_CHAIN_OF_TRUST
+ #include <fsl_validate.h>
+ #endif
+@@ -46,14 +48,16 @@ static void erratum_a009008(void)
+ static void erratum_a009798(void)
+ {
+ #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+-#if defined(CONFIG_LS1043A)
++#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
++#if defined(CONFIG_LS1043A)
+ val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+ val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
++#endif
+ #elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
+index f876c56..6ea4e8e 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
+@@ -14,8 +14,11 @@
+ #else
+ #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
+ #endif
++
++#ifndef CONFIG_LS1012A
+ #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
+ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
++#endif
+
+ /*
+ * Reserve secure memory
+@@ -205,6 +208,35 @@
+ #define CONFIG_SYS_FSL_ERRATUM_A008997
+ #define CONFIG_SYS_FSL_ERRATUM_A009007
+ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
++#elif defined(CONFIG_LS1012A)
++#define CONFIG_MAX_CPUS 1
++#define CONFIG_SYS_CACHELINE_SIZE 64
++#define CONFIG_NUM_DDR_CONTROLLERS 1
++#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
++#define CONFIG_SYS_FSL_SEC_COMPAT 5
++#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
++
++#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
++#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
++
++#define GICD_BASE 0x01401000
++#define GICC_BASE 0x01402000
++
++#define CONFIG_SYS_FSL_CCSR_GUR_BE
++#define CONFIG_SYS_FSL_CCSR_SCFG_BE
++#define CONFIG_SYS_FSL_ESDHC_BE
++#define CONFIG_SYS_FSL_WDOG_BE
++#define CONFIG_SYS_FSL_DSPI_BE
++#define CONFIG_SYS_FSL_QSPI_BE
++#define CONFIG_SYS_FSL_PEX_LUT_BE
++
++#define SRDS_MAX_LANES 4
++#define CONFIG_SYS_FSL_SRDS_1
++#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
++#define CONFIG_SYS_FSL_SEC_BE
++
++#define CONFIG_SYS_FSL_ERRATUM_A009798
++
+ #else
+ #error SoC not defined
+ #endif
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+index a7522da..e4ff990 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+@@ -14,6 +14,7 @@ static struct cpu_type cpu_type_list[] = {
+ CPU_TYPE_ENTRY(LS1043, LS1043, 4),
+ CPU_TYPE_ENTRY(LS1023, LS1023, 2),
+ CPU_TYPE_ENTRY(LS2040, LS2040, 4),
++ CPU_TYPE_ENTRY(LS1012, LS1012, 1),
+ };
+
+ #ifndef CONFIG_SYS_DCACHE_OFF
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+index 7096dac..4a3f4f3 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+@@ -134,6 +134,7 @@ enum srds_prtcl {
+ SGMII_2500_FM2_DTSEC6,
+ SGMII_2500_FM2_DTSEC9,
+ SGMII_2500_FM2_DTSEC10,
++ TX_CLK,
+ SERDES_PRCTL_COUNT
+ };
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index 2852f9c..5b026f8 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -62,7 +62,11 @@
+ #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
+ #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
+ /* LUT registers */
++#ifdef CONFIG_LS1012A
++#define PCIE_LUT_BASE 0xC0000
++#else
+ #define PCIE_LUT_BASE 0x10000
++#endif
+ #define PCIE_LUT_LCTRL0 0x7F8
+ #define PCIE_LUT_DBG 0x7FC
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+index 56989e1..0822b49 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+@@ -41,6 +41,7 @@ struct cpu_type {
+ { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
+
+ #define SVR_WO_E 0xFFFFFE
++#define SVR_LS1012 0x870400
+ #define SVR_LS1043 0x879200
+ #define SVR_LS1023 0x879208
+ #define SVR_LS2045 0x870120
+diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
+new file mode 100644
+index 0000000..3df822e
+--- /dev/null
++++ b/include/fsl_mmdc.h
+@@ -0,0 +1,53 @@
++/*
++ * Copyright 2015 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef FSL_MMDC_H
++#define FSL_MMDC_H
++
++/* MMDC Registers */
++struct mmdc_p_regs {
++ u32 mdctl;
++ u32 mdpdc;
++ u32 mdotc;
++ u32 mdcfg0;
++ u32 mdcfg1;
++ u32 mdcfg2;
++ u32 mdmisc;
++ u32 mdscr;
++ u32 mdref;
++ u32 res1[2];
++ u32 mdrwd;
++ u32 mdor;
++ u32 mdmrr;
++ u32 mdcfg3lp;
++ u32 mdmr4;
++ u32 mdasp;
++ u32 res3[239];
++ u32 maarcr;
++ u32 mapsr;
++ u32 res4[254];
++ u32 mpzqhwctrl;
++ u32 res5[2];
++ u32 mpwldectrl0;
++ u32 mpwldectrl1;
++ u32 res6;
++ u32 mpodtctrl;
++ u32 mprddqby0dl;
++ u32 mprddqby1dl;
++ u32 mprddqby2dl;
++ u32 mprddqby3dl;
++ u32 res7[4];
++ u32 mpdgctrl0;
++ u32 mpdgctrl1;
++ u32 res8;
++ u32 mprddlctl;
++ u32 res9;
++ u32 mpwrdlctl;
++ u32 res10[25];
++ u32 mpmur0;
++};
++
++#endif /* FSL_MMDC_H */
+diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
+index 4966608..72a5d5b 100644
+--- a/include/linux/usb/xhci-fsl.h
++++ b/include/linux/usb/xhci-fsl.h
+@@ -66,6 +66,10 @@ struct fsl_xhci {
+ #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
++#elif defined(CONFIG_LS1012A)
++#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
++#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
++#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+ #endif
+
+ #define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
+--
+1.7.9.5
+
--- /dev/null
+From faf0aac702a2253471f98687ed40138e514e38ab Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Mon, 25 Apr 2016 14:36:16 +0530
+Subject: [PATCH 14/93] armv8: ls1012a: Add support of ls1012aqds board
+
+QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012AQDS board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/Kconfig | 10 ++
+ arch/arm/dts/Makefile | 3 +-
+ arch/arm/dts/fsl-ls1012a-qds.dts | 14 ++
+ arch/arm/dts/fsl-ls1012a-qds.dtsi | 123 +++++++++++++
+ arch/arm/dts/fsl-ls1012a.dtsi | 119 ++++++++++++
+ board/freescale/ls1012aqds/Kconfig | 15 ++
+ board/freescale/ls1012aqds/MAINTAINERS | 6 +
+ board/freescale/ls1012aqds/Makefile | 7 +
+ board/freescale/ls1012aqds/README | 94 ++++++++++
+ board/freescale/ls1012aqds/ls1012aqds.c | 199 ++++++++++++++++++++
+ board/freescale/ls1012aqds/ls1012aqds_qixis.h | 35 ++++
+ configs/ls1012aqds_qspi_defconfig | 10 ++
+ include/configs/ls1012a_common.h | 239 +++++++++++++++++++++++++
+ include/configs/ls1012aqds.h | 133 ++++++++++++++
+ include/fsl_mmdc.h | 57 +++++-
+ 15 files changed, 1055 insertions(+), 9 deletions(-)
+ create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dts
+ create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dtsi
+ create mode 100644 arch/arm/dts/fsl-ls1012a.dtsi
+ create mode 100644 board/freescale/ls1012aqds/Kconfig
+ create mode 100644 board/freescale/ls1012aqds/MAINTAINERS
+ create mode 100644 board/freescale/ls1012aqds/Makefile
+ create mode 100644 board/freescale/ls1012aqds/README
+ create mode 100644 board/freescale/ls1012aqds/ls1012aqds.c
+ create mode 100644 board/freescale/ls1012aqds/ls1012aqds_qixis.h
+ create mode 100644 configs/ls1012aqds_qspi_defconfig
+ create mode 100644 include/configs/ls1012a_common.h
+ create mode 100644 include/configs/ls1012aqds.h
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 9bd6cf1..f5033db 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -647,6 +647,15 @@ config TARGET_HIKEY
+ Support for HiKey 96boards platform. It features a HI6220
+ SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
+
++config TARGET_LS1012AQDS
++ bool "Support ls1012aqds"
++ select ARM64
++ help
++ Support for Freescale LS1012AQDS platform.
++ The LS1012A Development System (QDS) is a high-performance
++ development platform that supports the QorIQ LS1012A
++ Layerscape Architecture processor.
++
+ config TARGET_LS1021AQDS
+ bool "Support ls1021aqds"
+ select CPU_V7
+@@ -792,6 +801,7 @@ source "board/freescale/ls1021aqds/Kconfig"
+ source "board/freescale/ls1043aqds/Kconfig"
+ source "board/freescale/ls1021atwr/Kconfig"
+ source "board/freescale/ls1043ardb/Kconfig"
++source "board/freescale/ls1012aqds/Kconfig"
+ source "board/freescale/mx23evk/Kconfig"
+ source "board/freescale/mx25pdk/Kconfig"
+ source "board/freescale/mx28evk/Kconfig"
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index c1c81e4..ed5eb38 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -94,7 +94,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
+ fsl-ls2080a-rdb.dtb
+ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
+ fsl-ls1043a-qds-lpuart.dtb \
+- fsl-ls1043a-rdb.dtb
++ fsl-ls1043a-rdb.dtb \
++ fsl-ls1012a-qds.dtb
+
+ dtb-$(CONFIG_MACH_SUN4I) += \
+ sun4i-a10-a1000.dtb \
+diff --git a/arch/arm/dts/fsl-ls1012a-qds.dts b/arch/arm/dts/fsl-ls1012a-qds.dts
+new file mode 100644
+index 0000000..ef6de34
+--- /dev/null
++++ b/arch/arm/dts/fsl-ls1012a-qds.dts
+@@ -0,0 +1,14 @@
++/*
++ * Copyright (C) 2016 Freescale Semiconductor
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++/dts-v1/;
++#include "fsl-ls1012a-qds.dtsi"
++
++/ {
++ chosen {
++ stdout-path = &duart0;
++ };
++};
+diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi
+new file mode 100644
+index 0000000..a32a84a
+--- /dev/null
++++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
+@@ -0,0 +1,123 @@
++/*
++ * Copyright (C) 2016 Freescale Semiconductor
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++/include/ "fsl-ls1012a.dtsi"
++
++/ {
++ model = "LS1012A QDS Board";
++ aliases {
++ spi0 = &qspi;
++ spi1 = &dspi0;
++ };
++};
++
++&dspi0 {
++ bus-num = <0>;
++ status = "okay";
++
++ dflash0: n25q128a {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "spi-flash";
++ reg = <0>;
++ spi-max-frequency = <1000000>; /* input clock */
++ };
++
++ dflash1: sst25wf040b {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "spi-flash";
++ spi-max-frequency = <3500000>;
++ reg = <1>;
++ };
++
++ dflash2: en25s64 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "spi-flash";
++ spi-max-frequency = <3500000>;
++ reg = <2>;
++ };
++};
++
++&qspi {
++ bus-num = <0>;
++ status = "okay";
++
++ qflash0: s25fl128s@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "spi-flash";
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++ };
++};
++
++&i2c0 {
++ status = "okay";
++ pca9547@77 {
++ compatible = "philips,pca9547";
++ reg = <0x77>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ i2c@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0>;
++
++ rtc@68 {
++ compatible = "dallas,ds3232";
++ reg = <0x68>;
++ /* IRQ10_B */
++ interrupts = <0 150 0x4>;
++ };
++ };
++
++ i2c@2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x2>;
++
++ ina220@40 {
++ compatible = "ti,ina220";
++ reg = <0x40>;
++ shunt-resistor = <1000>;
++ };
++
++ ina220@41 {
++ compatible = "ti,ina220";
++ reg = <0x41>;
++ shunt-resistor = <1000>;
++ };
++ };
++
++ i2c@3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x3>;
++
++ eeprom@56 {
++ compatible = "at24,24c512";
++ reg = <0x56>;
++ };
++
++ eeprom@57 {
++ compatible = "at24,24c512";
++ reg = <0x57>;
++ };
++
++ adt7461a@4c {
++ compatible = "adt7461a";
++ reg = <0x4c>;
++ };
++ };
++ };
++};
++
++&duart0 {
++ status = "okay";
++};
+diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
+new file mode 100644
+index 0000000..87a287a
+--- /dev/null
++++ b/arch/arm/dts/fsl-ls1012a.dtsi
+@@ -0,0 +1,119 @@
++/*
++ * Copyright (C) 2016 Freescale Semiconductor
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++/include/ "skeleton64.dtsi"
++
++/ {
++ compatible = "fsl,ls1012a";
++ interrupt-parent = <&gic>;
++ cpus {
++ #address-cells = <2>;
++ #size-cells = <0>;
++
++ cpu0: cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a53";
++ reg = <0x0 0x0>;
++ clocks = <&clockgen 1 0>;
++ };
++
++ };
++
++ sysclk: sysclk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <100000000>;
++ clock-output-names = "sysclk";
++ };
++
++ gic: interrupt-controller@1400000 {
++ compatible = "arm,gic-400";
++ #interrupt-cells = <3>;
++ interrupt-controller;
++ reg = <0x0 0x1401000 0 0x1000>, /* GICD */
++ <0x0 0x1402000 0 0x2000>, /* GICC */
++ <0x0 0x1404000 0 0x2000>, /* GICH */
++ <0x0 0x1406000 0 0x2000>; /* GICV */
++ interrupts = <1 9 0xf08>;
++ };
++
++ soc {
++ compatible = "simple-bus";
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ clockgen: clocking@1ee1000 {
++ compatible = "fsl,ls1012a-clockgen";
++ reg = <0x0 0x1ee1000 0x0 0x1000>;
++ #clock-cells = <2>;
++ clocks = <&sysclk>;
++ };
++
++ dspi0: dspi@2100000 {
++ compatible = "fsl,vf610-dspi";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x2100000 0x0 0x10000>;
++ interrupts = <0 64 0x4>;
++ clock-names = "dspi";
++ clocks = <&clockgen 4 0>;
++ num-cs = <6>;
++ big-endian;
++ status = "disabled";
++ };
++
++
++ i2c0: i2c@2180000 {
++ compatible = "fsl,vf610-i2c";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x2180000 0x0 0x10000>;
++ interrupts = <0 56 0x4>;
++ clock-names = "i2c";
++ clocks = <&clockgen 4 0>;
++ status = "disabled";
++ };
++
++ i2c1: i2c@2190000 {
++ compatible = "fsl,vf610-i2c";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x2190000 0x0 0x10000>;
++ interrupts = <0 57 0x4>;
++ clock-names = "i2c";
++ clocks = <&clockgen 4 0>;
++ status = "disabled";
++ };
++
++ duart0: serial@21c0500 {
++ compatible = "fsl,ns16550", "ns16550a";
++ reg = <0x00 0x21c0500 0x0 0x100>;
++ interrupts = <0 54 0x4>;
++ clocks = <&clockgen 4 0>;
++ };
++
++ duart1: serial@21c0600 {
++ compatible = "fsl,ns16550", "ns16550a";
++ reg = <0x00 0x21c0600 0x0 0x100>;
++ interrupts = <0 54 0x4>;
++ clocks = <&clockgen 4 0>;
++ };
++
++ qspi: quadspi@1550000 {
++ compatible = "fsl,vf610-qspi";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x1550000 0x0 0x10000>,
++ <0x0 0x40000000 0x0 0x4000000>;
++ reg-names = "QuadSPI", "QuadSPI-memory";
++ num-cs = <2>;
++ big-endian;
++ status = "disabled";
++ };
++
++ };
++};
+diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
+new file mode 100644
+index 0000000..1257ec8
+--- /dev/null
++++ b/board/freescale/ls1012aqds/Kconfig
+@@ -0,0 +1,15 @@
++if TARGET_LS1012AQDS
++
++config SYS_BOARD
++ default "ls1012aqds"
++
++config SYS_VENDOR
++ default "freescale"
++
++config SYS_SOC
++ default "fsl-layerscape"
++
++config SYS_CONFIG_NAME
++ default "ls1012aqds"
++
++endif
+diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS
+new file mode 100644
+index 0000000..3c01df6
+--- /dev/null
++++ b/board/freescale/ls1012aqds/MAINTAINERS
+@@ -0,0 +1,6 @@
++LS1012AQDS BOARD
++M:
++S: Maintained
++F: board/freescale/ls1012aqds/
++F: include/configs/ls1012aqds.h
++F: configs/ls1012aqds_defconfig
+diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
+new file mode 100644
+index 0000000..0b813f9
+--- /dev/null
++++ b/board/freescale/ls1012aqds/Makefile
+@@ -0,0 +1,7 @@
++#
++# Copyright 2016 Freescale Semiconductor, Inc.
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y += ls1012aqds.o
+diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README
+new file mode 100644
+index 0000000..e94a267
+--- /dev/null
++++ b/board/freescale/ls1012aqds/README
+@@ -0,0 +1,94 @@
++Overview
++--------
++The LS1012AQDS power supplies (PS) provide all the voltages necessary
++for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
++and other onboard peripherals.
++
++LS1012A SoC Overview
++--------------------
++The LS1012A features an advanced 64-bit ARM v8 Cortex-
++A53 processor, with 32 KB of parity protected L1-I cache,
++32 KB of ECC protected L1-D cache, as well as 256 KB of
++ECC protected L2 cache.
++
++The LS1012A SoC includes the following function and features:
++ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
++ - ARM v8 cryptography extensions
++ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
++ 16-/8-bit operation (no ECC support)
++ - ARM core-link CCI-400 cache coherent interconnect
++ - Packet Forwarding Engine (PFE)
++ - Cryptography acceleration (SEC)
++ - Ethernet interfaces supported by PFE:
++ - One Configurable x3 SerDes:
++ Two Serdes PLLs supported for usage by any SerDes data lane
++ Support for up to 6 GBaud operation
++ - High-speed peripheral interfaces:
++ - One PCI Express Gen2 controller, supporting x1 operation
++ - One serial ATA (SATA Gen 3.0) controller
++ - One USB 3.0/2.0 controller with integrated PHY
++ - One USB 2.0 controller with ULPI interface. .
++ - Additional peripheral interfaces:
++ - One quad serial peripheral interface (QuadSPI) controller
++ - One serial peripheral interface (SPI) controller
++ - Two enhanced secure digital host controllers
++ - Two I2C controllers
++ - One 16550 compliant DUART (two UART interfaces)
++ - Two general purpose IOs (GPIO)
++ - Two FlexTimers
++ - Five synchronous audio interfaces (SAI)
++ - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
++ - Single-source clocking solution enabling generation of core, platform,
++ DDR, SerDes, and USB clocks from a single external crystal and internal
++ crystaloscillator
++ - Thermal monitor unit (TMU) with +/- 3C accuracy
++ - Two WatchDog timers
++ - ARM generic timer
++ - QorIQ platform's trust architecture 2.1
++
++ LS1012AQDS board Overview
++ -----------------------
++ - SERDES Connections, 4 lanes supporting:
++ - PCI Express - 3.0
++ - SGMII, SGMII 2.5
++ - SATA 3.0
++ - DDR Controller
++ - 6-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
++ - QSPI Controller
++ - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
++ signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
++ emulator
++ - USB 3.0
++ - One USB 3.0 controller with integrated PHY
++ - One high-speed USB 3.0 port
++ - USB 2.0
++ - One USB 2.0 controller with ULPI interface
++ - Two enhanced secure digital host controllers:
++ - SDHC1 controller can be connected to onboard SDHC connector
++ - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
++ - 2 I2C controllers
++ - One SATA onboard connectors
++ - UART
++ - 5 SAI
++ - One SAI port with audio codec SGTL5000:
++ • Provides MIC bias
++ • Provides headphone and line output
++ - One SAI port terminated at 2x6 header
++ - Three SAI Tx/Rx ports terminated at 2x3 headers
++ - ARM JTAG support
++
++Booting Options
++---------------
++a) QSPI Flash Emu Boot
++b) QSPI Flash 1
++c) QSPI Flash 2
++
++QSPI flash map
++--------------
++Images | Size |QSPI Flash Address
++------------------------------------------
++RCW + PBI | 1MB | 0x4000_0000
++U-boot | 1MB | 0x4010_0000
++U-boot Env | 1MB | 0x4020_0000
++PPA FIT image | 2MB | 0x4050_0000
++Linux ITB | ~53MB | 0x40A0_0000
+diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
+new file mode 100644
+index 0000000..ffcd0d8
+--- /dev/null
++++ b/board/freescale/ls1012aqds/ls1012aqds.c
+@@ -0,0 +1,199 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <i2c.h>
++#include <fdt_support.h>
++#include <asm/io.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/fsl_serdes.h>
++#include <asm/arch/fdt.h>
++#include <asm/arch/soc.h>
++#include <ahci.h>
++#include <hwconfig.h>
++#include <mmc.h>
++#include <scsi.h>
++#include <fm_eth.h>
++#include <fsl_csu.h>
++#include <fsl_esdhc.h>
++#include <fsl_mmdc.h>
++#include <spl.h>
++#include <netdev.h>
++
++#include "../common/qixis.h"
++#include "ls1012aqds_qixis.h"
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int checkboard(void)
++{
++ puts("Board: LS1012AQDS\n");
++
++ return 0;
++}
++
++void mmdc_init(void)
++{
++ struct mmdc_p_regs *mmdc =
++ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
++
++ /* Set MMDC_MDSCR[CON_REQ] */
++ out_be32(&mmdc->mdscr, 0x00008000);
++
++ /* configure timing parms */
++ out_be32(&mmdc->mdotc, 0x12554000);
++ out_be32(&mmdc->mdcfg0, 0xbabf7954);
++ out_be32(&mmdc->mdcfg1, 0xff328f64);
++ out_be32(&mmdc->mdcfg2, 0x01ff00db);
++
++ /* other parms */
++ out_be32(&mmdc->mdmisc, 0x00000680);
++ out_be32(&mmdc->mpmur0, 0x00000800);
++ out_be32(&mmdc->mdrwd, 0x00002000);
++ out_be32(&mmdc->mpodtctrl, 0x0000022a);
++
++ /* out of reset delays */
++ out_be32(&mmdc->mdor, 0x00bf1023);
++
++ /* physical parms */
++ out_be32(&mmdc->mdctl, 0x05180000);
++ out_be32(&mmdc->mdasp, 0x0000007f);
++
++ /* Enable MMDC */
++ out_be32(&mmdc->mdctl, 0x85180000);
++
++ /* dram init sequence: update MRs */
++ out_be32(&mmdc->mdscr, 0x00088032);
++ out_be32(&mmdc->mdscr, 0x00008033);
++ out_be32(&mmdc->mdscr, 0x00048031);
++ out_be32(&mmdc->mdscr, 0x19308030);
++
++ /* dram init sequence: ZQCL */
++ out_be32(&mmdc->mdscr, 0x04008040);
++ out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
++
++ mdelay(100);
++
++ /* Calibrations now: wr lvl */
++ out_be32(&mmdc->mdscr, 0x00848031);
++ out_be32(&mmdc->mdscr, 0x00008200);
++ out_be32(&mmdc->mpwlgcr, 0x00000001);
++
++ mdelay(100);
++
++ out_be32(&mmdc->mdscr, 0x00048031);
++ out_be32(&mmdc->mdscr, 0x00008000);
++
++ /* manual_refresh */
++ out_be32(&mmdc->mdscr, 0x00008020);
++
++ mdelay(100);
++
++ /* Calibrations now: Read DQS gating calibration */
++ out_be32(&mmdc->mdscr, 0x04008050);
++ out_be32(&mmdc->mdscr, 0x00048033);
++ out_be32(&mmdc->mppdcmpr2, 0x00000001);
++ out_be32(&mmdc->mprddlctl, 0x40404040);
++ out_be32(&mmdc->mpdgctrl0, 0x10000000);
++
++ mdelay(100);
++
++ out_be32(&mmdc->mdscr, 0x00008033);
++
++ /* manual_refresh */
++ out_be32(&mmdc->mdscr, 0x00008020);
++
++ mdelay(100);
++
++ /* Calibrations now: Read calibration */
++ out_be32(&mmdc->mdscr, 0x04008050);
++ out_be32(&mmdc->mdscr, 0x00048033);
++ out_be32(&mmdc->mppdcmpr2, 0x00000001);
++ out_be32(&mmdc->mprddlhwctl, 0x00000010);
++
++ mdelay(400);
++
++ out_be32(&mmdc->mdscr, 0x00008033);
++
++ /* manual_refresh */
++ out_be32(&mmdc->mdscr, 0x00008020);
++
++ mdelay(100);
++
++ /* PD, SR */
++ out_be32(&mmdc->mdpdc, 0x00030035);
++ out_be32(&mmdc->mapsr, 0x00001067);
++
++ /* refresh scheme */
++ out_be32(&mmdc->mdref, 0x103e8000);
++
++ mdelay(400);
++
++ /* disable CON_REQ */
++ out_be32(&mmdc->mdscr, 0x0);
++
++ mdelay(50);
++}
++
++int dram_init(void)
++{
++ mmdc_init();
++
++ gd->ram_size = 0x40000000;
++
++ return 0;
++}
++
++int board_early_init_f(void)
++{
++ fsl_lsch2_early_init_f();
++
++ return 0;
++}
++
++int board_init(void)
++{
++ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
++ CONFIG_SYS_CCI400_ADDR;
++
++ /* Set CCI-400 control override register to enable barrier
++ * transaction */
++ out_le32(&cci->ctrl_ord,
++ CCI400_CTRLORD_EN_BARRIER);
++
++#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
++ enable_layerscape_ns_access();
++#endif
++
++#ifdef CONFIG_ENV_IS_NOWHERE
++ gd->env_addr = (ulong)&default_environment[0];
++#endif
++ return 0;
++}
++
++int board_eth_init(bd_t *bis)
++{
++ return pci_eth_init(bis);
++}
++
++#ifdef CONFIG_OF_BOARD_SETUP
++int ft_board_setup(void *blob, bd_t *bd)
++{
++ u64 base[CONFIG_NR_DRAM_BANKS];
++ u64 size[CONFIG_NR_DRAM_BANKS];
++
++ /* fixup DT for the two DDR banks */
++ base[0] = gd->bd->bi_dram[0].start;
++ size[0] = gd->bd->bi_dram[0].size;
++ base[1] = gd->bd->bi_dram[1].start;
++ size[1] = gd->bd->bi_dram[1].size;
++
++ fdt_fixup_memory_banks(blob, base, size, 2);
++ ft_cpu_setup(blob, bd);
++
++ return 0;
++}
++#endif
+diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
+new file mode 100644
+index 0000000..584f604
+--- /dev/null
++++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
+@@ -0,0 +1,35 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __LS1043AQDS_QIXIS_H__
++#define __LS1043AQDS_QIXIS_H__
++
++/* Definitions of QIXIS Registers for LS1043AQDS */
++
++/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
++#define BRDCFG4_EMISEL_MASK 0xe0
++#define BRDCFG4_EMISEL_SHIFT 5
++
++/* SYSCLK */
++#define QIXIS_SYSCLK_66 0x0
++#define QIXIS_SYSCLK_83 0x1
++#define QIXIS_SYSCLK_100 0x2
++#define QIXIS_SYSCLK_125 0x3
++#define QIXIS_SYSCLK_133 0x4
++
++/* DDRCLK */
++#define QIXIS_DDRCLK_66 0x0
++#define QIXIS_DDRCLK_100 0x1
++#define QIXIS_DDRCLK_125 0x2
++#define QIXIS_DDRCLK_133 0x3
++
++/* BRDCFG2 - SD clock*/
++#define QIXIS_SDCLK1_100 0x0
++#define QIXIS_SDCLK1_125 0x1
++#define QIXIS_SDCLK1_165 0x2
++#define QIXIS_SDCLK1_100_SP 0x3
++
++#endif
+diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
+new file mode 100644
+index 0000000..ef2c0ad
+--- /dev/null
++++ b/configs/ls1012aqds_qspi_defconfig
+@@ -0,0 +1,10 @@
++CONFIG_ARM=y
++CONFIG_TARGET_LS1012AQDS=y
++CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
++# CONFIG_CMD_IMLS is not set
++CONFIG_SYS_NS16550=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
++CONFIG_OF_CONTROL=y
++CONFIG_DM=y
++CONFIG_SPI_FLASH=y
++CONFIG_DM_SPI=y
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+new file mode 100644
+index 0000000..9ed04f9
+--- /dev/null
++++ b/include/configs/ls1012a_common.h
+@@ -0,0 +1,239 @@
++/*
++ * Copyright (C) 2015 Freescale Semiconductor
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __LS1012A_COMMON_H
++#define __LS1012A_COMMON_H
++
++#define CONFIG_FSL_LAYERSCAPE
++#define CONFIG_FSL_LSCH2
++#define CONFIG_LS1012A
++#define CONFIG_GICV2
++
++#define CONFIG_SYS_HAS_SERDES
++
++#include <asm/arch/config.h>
++#define CONFIG_SYS_NO_FLASH
++
++#define CONFIG_SUPPORT_RAW_INITRD
++
++#define CONFIG_DISPLAY_BOARDINFO_LATE
++
++#define CONFIG_SYS_TEXT_BASE 0x40100000
++
++#define CONFIG_SYS_FSL_CLK
++#define CONFIG_SYS_CLK_FREQ 100000000
++#define CONFIG_DDR_CLK_FREQ 125000000
++
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_BOARD_EARLY_INIT_F 1
++
++#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
++#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
++
++#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
++#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
++#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
++
++/* Generic Timer Definitions */
++#define COUNTER_FREQUENCY 25000000 /* 12MHz */
++
++/* CSU */
++#define CONFIG_LAYERSCAPE_NS_ACCESS
++
++/* Size of malloc() pool */
++#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
++
++/*SPI device */
++#ifdef CONFIG_QSPI_BOOT
++#define CONFIG_SYS_QE_FW_IN_SPIFLASH
++#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
++#define CONFIG_ENV_SPI_BUS 0
++#define CONFIG_ENV_SPI_CS 0
++#define CONFIG_ENV_SPI_MAX_HZ 1000000
++#define CONFIG_ENV_SPI_MODE 0x03
++#define CONFIG_CMD_SF
++#define CONFIG_SPI_FLASH_SPANSION
++#define CONFIG_SPI_FLASH_ATMEL
++#define CONFIG_FSL_SPI_INTERFACE
++#define CONFIG_SF_DATAFLASH
++
++#define CONFIG_FSL_QSPI
++#define QSPI0_AMBA_BASE 0x40000000
++#define CONFIG_SPI_FLASH_SPANSION
++#define CONFIG_DM_SPI_FLASH
++#define CONFIG_SPI_FLASH_BAR
++
++#define FSL_QSPI_FLASH_SIZE (1 << 24)
++#define FSL_QSPI_FLASH_NUM 2
++
++/*
++ * Environment
++ */
++#define CONFIG_ENV_OVERWRITE
++
++#define CONFIG_ENV_IS_IN_SPI_FLASH
++#define CONFIG_ENV_SIZE 0x40000 /* 256KB */
++#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
++#define CONFIG_ENV_SECT_SIZE 0x40000
++#endif
++
++/* I2C */
++#if !defined(CONFIG_EMU)
++#define CONFIG_CMD_I2C
++#define CONFIG_SYS_I2C
++#define CONFIG_SYS_I2C_MXC
++#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
++#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
++#endif /* CONFIG_EMU */
++
++/* MMC */
++#if !defined(CONFIG_EMU)
++#define CONFIG_MMC
++#ifdef CONFIG_MMC
++#define CONFIG_CMD_MMC
++#define CONFIG_FSL_ESDHC
++#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
++#define CONFIG_GENERIC_MMC
++#define CONFIG_CMD_FAT
++#define CONFIG_DOS_PARTITION
++#endif
++#endif /* CONFIG_EMU */
++
++/* SATA */
++#if !defined(CONFIG_EMU)
++#define CONFIG_LIBATA
++#define CONFIG_SCSI_AHCI
++#define CONFIG_SCSI_AHCI_PLAT
++#define CONFIG_CMD_SCSI
++#define CONFIG_CMD_FAT
++#define CONFIG_CMD_EXT2
++#define CONFIG_DOS_PARTITION
++#define CONFIG_BOARD_LATE_INIT
++
++#define CONFIG_SYS_SATA AHCI_BASE_ADDR
++
++#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
++#define CONFIG_SYS_SCSI_MAX_LUN 1
++#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
++ CONFIG_SYS_SCSI_MAX_LUN)
++
++#define CONFIG_PCI /* Enable PCI/PCIE */
++#define CONFIG_PCIE1 /* PCIE controller 1 */
++#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
++#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
++
++#define CONFIG_SYS_PCI_64BIT
++
++#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
++#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
++#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
++#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
++
++#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
++#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
++#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
++
++#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
++#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
++#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
++
++#define CONFIG_NET_MULTI
++#define CONFIG_PCI_PNP
++#define CONFIG_E1000
++#define CONFIG_PCI_SCAN_SHOW
++#define CONFIG_CMD_PCI
++#endif
++
++#define CONFIG_CONS_INDEX 1
++#define CONFIG_SYS_NS16550_SERIAL
++#define CONFIG_SYS_NS16550_REG_SIZE 1
++#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
++
++#ifdef CONFIG_EMU
++#define CONFIG_BAUDRATE 3000
++#else
++#define CONFIG_BAUDRATE 115200
++#endif
++#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
++
++/* Command line configuration */
++#define CONFIG_CMD_CACHE
++#define CONFIG_CMD_DHCP
++#define CONFIG_CMD_ENV
++#define CONFIG_CMD_GREPENV
++#define CONFIG_CMD_MII
++#define CONFIG_CMD_PING
++#undef CONFIG_CMD_IMLS
++
++
++#define CONFIG_ARCH_EARLY_INIT_R
++
++#define CONFIG_SYS_HZ 1000
++
++#define CONFIG_HWCONFIG
++#define HWCONFIG_BUFFER_SIZE 128
++
++#define CONFIG_DISPLAY_CPUINFO
++
++/* Initial environment variables */
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ "initrd_high=0xffffffff\0" \
++ "verify=no\0" \
++ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
++ "loadaddr=0x80100000\0" \
++ "kernel_addr=0x100000\0" \
++ "ramdisk_addr=0x800000\0" \
++ "ramdisk_size=0x2000000\0" \
++ "fdt_high=0xffffffffffffffff\0" \
++ "initrd_high=0xffffffffffffffff\0" \
++ "kernel_start=0xa00000\0" \
++ "kernel_load=0xa0000000\0" \
++ "kernel_size=0x2800000\0" \
++ "console=ttyAMA0,38400n8\0"
++
++#ifdef CONFIG_EMU
++#define CONFIG_BOOTARGS "console=ttyS2,115200 root=/dev/ram0 " \
++ "earlycon=uart8250,mmio,0x21d0500,115200n8"
++/* Kernel image should be pre-loaded to address kernel_load */
++#define CONFIG_BOOTCOMMAND "bootm $kernel_load"
++#else
++#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
++ "earlycon=uart8250,mmio,0x21c0500"
++#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
++ "$kernel_start $kernel_size && "\
++ "bootm $kernel_load"
++#endif
++#define CONFIG_BOOTDELAY 10
++
++/* Monitor Command Prompt */
++#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
++#define CONFIG_SYS_PROMPT "=> "
++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
++ sizeof(CONFIG_SYS_PROMPT) + 16)
++#define CONFIG_SYS_HUSH_PARSER
++#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
++#define CONFIG_SYS_LONGHELP
++#define CONFIG_CMDLINE_EDITING 1
++#define CONFIG_AUTO_COMPLETE
++#define CONFIG_SYS_MAXARGS 64 /* max command args */
++
++#define CONFIG_PANIC_HANG
++#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
++
++/* Flat Device Tree Definitions */
++#define CONFIG_OF_LIBFDT
++#define CONFIG_OF_BOARD_SETUP
++
++/* new uImage format support */
++#define CONFIG_FIT
++#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
++#define CONFIG_CMD_BOOTZ
++#define CONFIG_CMDLINE_TAG
++
++#include <asm/fsl_secure_boot.h>
++
++#endif /* __LS1012A_COMMON_H */
+diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
+new file mode 100644
+index 0000000..6346d3e
+--- /dev/null
++++ b/include/configs/ls1012aqds.h
+@@ -0,0 +1,133 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __LS1012AQDS_H__
++#define __LS1012AQDS_H__
++
++#include "ls1012a_common.h"
++
++
++#define CONFIG_DIMM_SLOTS_PER_CTLR 1
++#define CONFIG_CHIP_SELECTS_PER_CTRL 1
++#define CONFIG_NR_DRAM_BANKS 2
++
++#ifdef CONFIG_SYS_DPAA_FMAN
++#define CONFIG_FMAN_ENET
++#define CONFIG_PHYLIB
++#define CONFIG_PHY_VITESSE
++#define CONFIG_PHY_REALTEK
++#define RGMII_PHY1_ADDR 0x1
++#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
++#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
++#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
++#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
++#endif
++
++#define CONFIG_QIXIS_I2C_ACCESS
++
++/*
++ * I2C bus multiplexer
++ */
++#define I2C_MUX_PCA_ADDR_PRI 0x77
++#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
++#define I2C_RETIMER_ADDR 0x18
++#define I2C_MUX_CH_DEFAULT 0x8
++#define I2C_MUX_CH_CH7301 0xC
++#define I2C_MUX_CH5 0xD
++#define I2C_MUX_CH7 0xF
++
++#define I2C_MUX_CH_VOL_MONITOR 0xa
++
++/*
++* RTC configuration
++*/
++#define RTC
++#define CONFIG_RTC_PCF8563 1
++#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
++#define CONFIG_CMD_DATE
++
++/* EEPROM */
++#define CONFIG_ID_EEPROM
++#define CONFIG_CMD_EEPROM
++#define CONFIG_SYS_I2C_EEPROM_NXID
++#define CONFIG_SYS_EEPROM_BUS_NUM 0
++#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
++#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
++#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
++#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
++
++
++/* Voltage monitor on channel 2*/
++#define I2C_VOL_MONITOR_ADDR 0x40
++#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
++#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
++#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
++
++/* DSPI */
++#define CONFIG_FSL_DSPI
++#define CONFIG_FSL_DSPI1
++#define CONFIG_DEFAULT_SPI_BUS 1
++
++#define CONFIG_CMD_SPI
++#define MMAP_DSPI DSPI1_BASE_ADDR
++
++#define CONFIG_SYS_DSPI_CTAR0 1
++
++#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
++ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
++ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
++ DSPI_CTAR_DT(0))
++#define CONFIG_SPI_FLASH_SST /* cs1 */
++
++#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
++ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
++ DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
++ DSPI_CTAR_DT(0))
++#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
++
++#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
++ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
++ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
++ DSPI_CTAR_DT(0))
++#define CONFIG_SPI_FLASH_EON /* cs3 */
++
++#define CONFIG_SF_DEFAULT_SPEED 10000000
++#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
++#define CONFIG_SF_DEFAULT_BUS 1
++#define CONFIG_SF_DEFAULT_CS 0
++
++/*
++* USB
++*/
++/* EHCI Support - disbaled by default */
++/*#define CONFIG_HAS_FSL_DR_USB*/
++
++#ifdef CONFIG_HAS_FSL_DR_USB
++#define CONFIG_USB_EHCI
++#define CONFIG_USB_EHCI_FSL
++#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
++#endif
++
++/*XHCI Support - enabled by default*/
++#define CONFIG_HAS_FSL_XHCI_USB
++
++#ifdef CONFIG_HAS_FSL_XHCI_USB
++#define CONFIG_USB_XHCI
++#define CONFIG_USB_XHCI_FSL
++#define CONFIG_USB_XHCI_DWC3
++#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
++#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
++#define CONFIG_CMD_USB
++#define CONFIG_USB_STORAGE
++#define CONFIG_CMD_EXT2
++#endif
++
++#define CONFIG_CMD_MEMINFO
++#define CONFIG_CMD_MEMTEST
++#define CONFIG_SYS_MEMTEST_START 0x80000000
++#define CONFIG_SYS_MEMTEST_END 0x9fffffff
++
++#endif /* __LS1012AQDS_H__ */
+diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
+index 3df822e..d47e625 100644
+--- a/include/fsl_mmdc.h
++++ b/include/fsl_mmdc.h
+@@ -25,29 +25,70 @@ struct mmdc_p_regs {
+ u32 mdcfg3lp;
+ u32 mdmr4;
+ u32 mdasp;
+- u32 res3[239];
++ u32 res2[239];
+ u32 maarcr;
+ u32 mapsr;
+- u32 res4[254];
++ u32 maexidr0;
++ u32 maexidr1;
++ u32 madpcr0;
++ u32 madpcr1;
++ u32 madpsr0;
++ u32 madpsr1;
++ u32 madpsr2;
++ u32 madpsr3;
++ u32 madpsr4;
++ u32 madpsr5;
++ u32 masbs0;
++ u32 masbs1;
++ u32 res3[2];
++ u32 magenp;
++ u32 res4[239];
+ u32 mpzqhwctrl;
+- u32 res5[2];
++ u32 mpzqswctrl;
++ u32 mpwlgcr;
+ u32 mpwldectrl0;
+ u32 mpwldectrl1;
+- u32 res6;
++ u32 mpwldlst;
+ u32 mpodtctrl;
+ u32 mprddqby0dl;
+ u32 mprddqby1dl;
+ u32 mprddqby2dl;
+ u32 mprddqby3dl;
+- u32 res7[4];
++ u32 res5[4];
+ u32 mpdgctrl0;
+ u32 mpdgctrl1;
+- u32 res8;
++ u32 mpdgdlst0;
+ u32 mprddlctl;
+- u32 res9;
++ u32 mprddlst;
+ u32 mpwrdlctl;
+- u32 res10[25];
++ u32 mpwrdlst;
++ u32 mpsdctrl;
++ u32 mpzqlp2ctl;
++ u32 mprddlhwctl;
++ u32 mpwrdlhwctl;
++ u32 mprddlhwst0;
++ u32 mprddlhwst1;
++ u32 mpwrdlhwst0;
++ u32 mpwrdlhwst1;
++ u32 mpwlhwerr;
++ u32 mpdghwst0;
++ u32 mpdghwst1;
++ u32 mpdghwst2;
++ u32 mpdghwst3;
++ u32 mppdcmpr1;
++ u32 mppdcmpr2;
++ u32 mpswdar0;
++ u32 mpswdrdr0;
++ u32 mpswdrdr1;
++ u32 mpswdrdr2;
++ u32 mpswdrdr3;
++ u32 mpswdrdr4;
++ u32 mpswdrdr5;
++ u32 mpswdrdr6;
++ u32 mpswdrdr7;
+ u32 mpmur0;
++ u32 mpwrcadl;
++ u32 mpdccr;
+ };
+
+ #endif /* FSL_MMDC_H */
+--
+1.7.9.5
+
--- /dev/null
+From 4bb641f4d28053bd1ff4af73dc0a63be2151f851 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Mon, 25 Apr 2016 14:37:33 +0530
+Subject: [PATCH 15/93] armv8: ls1012a: Add support of ls1012ardb board
+
+QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012ARDB board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/Kconfig | 10 ++
+ arch/arm/dts/Makefile | 3 +-
+ arch/arm/dts/fsl-ls1012a-rdb.dts | 16 +++
+ arch/arm/dts/fsl-ls1012a-rdb.dtsi | 39 ++++++
+ board/freescale/ls1012ardb/Kconfig | 15 +++
+ board/freescale/ls1012ardb/MAINTAINERS | 6 +
+ board/freescale/ls1012ardb/Makefile | 7 +
+ board/freescale/ls1012ardb/README | 89 +++++++++++++
+ board/freescale/ls1012ardb/ls1012ardb.c | 220 +++++++++++++++++++++++++++++++
+ configs/ls1012ardb_qspi_defconfig | 10 ++
+ include/configs/ls1012a_common.h | 3 +-
+ include/configs/ls1012ardb.h | 61 +++++++++
+ include/linux/usb/xhci-fsl.h | 2 +-
+ 13 files changed, 477 insertions(+), 4 deletions(-)
+ create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dts
+ create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dtsi
+ create mode 100644 board/freescale/ls1012ardb/Kconfig
+ create mode 100644 board/freescale/ls1012ardb/MAINTAINERS
+ create mode 100644 board/freescale/ls1012ardb/Makefile
+ create mode 100644 board/freescale/ls1012ardb/README
+ create mode 100644 board/freescale/ls1012ardb/ls1012ardb.c
+ create mode 100644 configs/ls1012ardb_qspi_defconfig
+ create mode 100644 include/configs/ls1012ardb.h
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index f5033db..5c20801 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -656,6 +656,15 @@ config TARGET_LS1012AQDS
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
++config TARGET_LS1012ARDB
++ bool "Support ls1012ardb"
++ select ARM64
++ help
++ Support for Freescale LS1012ARDB platform.
++ The LS1012A Reference design board (RDB) is a high-performance
++ development platform that supports the QorIQ LS1012A
++ Layerscape Architecture processor.
++
+ config TARGET_LS1021AQDS
+ bool "Support ls1021aqds"
+ select CPU_V7
+@@ -802,6 +811,7 @@ source "board/freescale/ls1043aqds/Kconfig"
+ source "board/freescale/ls1021atwr/Kconfig"
+ source "board/freescale/ls1043ardb/Kconfig"
+ source "board/freescale/ls1012aqds/Kconfig"
++source "board/freescale/ls1012ardb/Kconfig"
+ source "board/freescale/mx23evk/Kconfig"
+ source "board/freescale/mx25pdk/Kconfig"
+ source "board/freescale/mx28evk/Kconfig"
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index ed5eb38..9e8137b 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -95,7 +95,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
+ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
+ fsl-ls1043a-qds-lpuart.dtb \
+ fsl-ls1043a-rdb.dtb \
+- fsl-ls1012a-qds.dtb
++ fsl-ls1012a-qds.dtb \
++ fsl-ls1012a-rdb.dtb
+
+ dtb-$(CONFIG_MACH_SUN4I) += \
+ sun4i-a10-a1000.dtb \
+diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dts b/arch/arm/dts/fsl-ls1012a-rdb.dts
+new file mode 100644
+index 0000000..4ec9786
+--- /dev/null
++++ b/arch/arm/dts/fsl-ls1012a-rdb.dts
+@@ -0,0 +1,16 @@
++/*
++ * Device Tree file for Freescale Layerscape-1012A family SoC.
++ *
++ * Copyright (C) 2016, Freescale Semiconductor
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++/dts-v1/;
++#include "fsl-ls1012a-rdb.dtsi"
++
++/ {
++ chosen {
++ stdout-path = &duart0;
++ };
++};
+diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
+new file mode 100644
+index 0000000..71aba78
+--- /dev/null
++++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
+@@ -0,0 +1,39 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
++ *
++ * Copyright (C) 2016, Freescale Semiconductor
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++/include/ "fsl-ls1012a.dtsi"
++
++/ {
++ model = "LS1012A RDB Board";
++ aliases {
++ spi0 = &qspi;
++ };
++};
++
++&qspi {
++ bus-num = <0>;
++ status = "okay";
++
++ qflash0: s25fl128s@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "spi-flash";
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++ };
++};
++
++&i2c0 {
++ status = "okay";
++};
++
++&duart0 {
++ status = "okay";
++};
+diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
+new file mode 100644
+index 0000000..3f67c28
+--- /dev/null
++++ b/board/freescale/ls1012ardb/Kconfig
+@@ -0,0 +1,15 @@
++if TARGET_LS1012ARDB
++
++config SYS_BOARD
++ default "ls1012ardb"
++
++config SYS_VENDOR
++ default "freescale"
++
++config SYS_SOC
++ default "fsl-layerscape"
++
++config SYS_CONFIG_NAME
++ default "ls1012ardb"
++
++endif
+diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
+new file mode 100644
+index 0000000..757e810
+--- /dev/null
++++ b/board/freescale/ls1012ardb/MAINTAINERS
+@@ -0,0 +1,6 @@
++LS1012ARDB BOARD
++M:
++S: Maintained
++F: board/freescale/ls1012ardb/
++F: include/configs/ls1012ardb.h
++F: configs/ls1012ardb_defconfig
+diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
+new file mode 100644
+index 0000000..05fa9d9
+--- /dev/null
++++ b/board/freescale/ls1012ardb/Makefile
+@@ -0,0 +1,7 @@
++#
++# Copyright 2016 Freescale Semiconductor, Inc.
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y += ls1012ardb.o
+diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README
+new file mode 100644
+index 0000000..cda03f6
+--- /dev/null
++++ b/board/freescale/ls1012ardb/README
+@@ -0,0 +1,89 @@
++Overview
++--------
++The LS1012ARDB power supplies (PS) provide all the voltages necessary
++for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
++and other onboard peripherals.
++
++LS1012A SoC Overview
++--------------------
++The LS1012A features an advanced 64-bit ARM v8 Cortex-
++A53 processor, with 32 KB of parity protected L1-I cache,
++32 KB of ECC protected L1-D cache, as well as 256 KB of
++ECC protected L2 cache.
++
++The LS1012A SoC includes the following function and features:
++ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
++ - ARM v8 cryptography extensions
++ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
++ 16-/8-bit operation (no ECC support)
++ - ARM core-link CCI-400 cache coherent interconnect
++ - Packet Forwarding Engine (PFE)
++ - Cryptography acceleration (SEC)
++ - Ethernet interfaces supported by PFE:
++ - One Configurable x3 SerDes:
++ Two Serdes PLLs supported for usage by any SerDes data lane
++ Support for up to 6 GBaud operation
++ - High-speed peripheral interfaces:
++ - One PCI Express Gen2 controller, supporting x1 operation
++ - One serial ATA (SATA Gen 3.0) controller
++ - One USB 3.0/2.0 controller with integrated PHY
++ - One USB 2.0 controller with ULPI interface. .
++ - Additional peripheral interfaces:
++ - One quad serial peripheral interface (QuadSPI) controller
++ - One serial peripheral interface (SPI) controller
++ - Two enhanced secure digital host controllers
++ - Two I2C controllers
++ - One 16550 compliant DUART (two UART interfaces)
++ - Two general purpose IOs (GPIO)
++ - Two FlexTimers
++ - Five synchronous audio interfaces (SAI)
++ - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
++ - Single-source clocking solution enabling generation of core, platform,
++ DDR, SerDes, and USB clocks from a single external crystal and internal
++ crystaloscillator
++ - Thermal monitor unit (TMU) with +/- 3C accuracy
++ - Two WatchDog timers
++ - ARM generic timer
++ - QorIQ platform's trust architecture 2.1
++
++ LS1012ARDB board Overview
++ -----------------------
++ - SERDES Connections, 4 lanes supporting:
++ - PCI Express - 3.0
++ - SGMII, SGMII 2.5
++ - SATA 3.0
++ - DDR Controller
++ - 6-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
++ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
++ signals to
++ - QSPI NOR flash memory (2 virtual banks)
++ - the QSPI emulator.s
++ - USB 3.0
++ - one high-speed USB 2.0/3.0 port.
++ - Two enhanced secure digital host controllers:
++ - SDHC1 controller can be connected to onboard SDHC connector
++ - SDHC2 controller: Three dual 1:4 mux/demux devices,
++ 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
++ SDIO WiFi, SPI, and Ardiuno shield
++ - 2 I2C controllers
++ - One SATA onboard connectors
++ - UART
++ - The LS1012A processor consists of two UART controllers,
++ out of which only UART1 is used on RDB.
++ - ARM JTAG support
++
++Booting Options
++---------------
++a) QSPI Flash Emu Boot
++b) QSPI Flash 1
++c) QSPI Flash 2
++
++QSPI flash map
++--------------
++Images | Size |QSPI Flash Address
++------------------------------------------
++RCW + PBI | 1MB | 0x4000_0000
++U-boot | 1MB | 0x4010_0000
++U-boot Env | 1MB | 0x4020_0000
++PPA FIT image | 2MB | 0x4050_0000
++Linux ITB | ~53MB | 0x40A0_0000
+diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
+new file mode 100644
+index 0000000..4a7aaaa
+--- /dev/null
++++ b/board/freescale/ls1012ardb/ls1012ardb.c
+@@ -0,0 +1,220 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <i2c.h>
++#include <asm/io.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/fsl_serdes.h>
++#include <asm/arch/ppa.h>
++#include <asm/arch/soc.h>
++#include <hwconfig.h>
++#include <ahci.h>
++#include <mmc.h>
++#include <scsi.h>
++#include <fsl_csu.h>
++#include <fsl_esdhc.h>
++#include <environment.h>
++#include <fsl_mmdc.h>
++#include <netdev.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int checkboard(void)
++{
++ u8 in1;
++
++ puts("Board: LS1012ARDB ");
++
++ /* Initialize i2c early for Serial flash bank information */
++ i2c_set_bus_num(0);
++
++ if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
++ printf("Error reading i2c boot information!\n");
++ return 0; /* Don't want to hang() on this error */
++ }
++
++ puts("Version");
++ if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
++ puts(": RevA");
++ else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
++ puts(": RevB");
++ else
++ puts(": unknown");
++
++ printf(", boot from QSPI");
++ if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
++ puts(": emu\n");
++ else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
++ puts(": bank1\n");
++ else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
++ puts(": bank2\n");
++ else
++ puts("unknown\n");
++
++ return 0;
++}
++
++void mmdc_init(void)
++{
++ struct mmdc_p_regs *mmdc =
++ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
++
++ /* Set MMDC_MDSCR[CON_REQ] */
++ out_be32(&mmdc->mdscr, 0x00008000);
++
++ /* configure timing parms */
++ out_be32(&mmdc->mdotc, 0x12554000);
++ out_be32(&mmdc->mdcfg0, 0xbabf7954);
++ out_be32(&mmdc->mdcfg1, 0xff328f64);
++ out_be32(&mmdc->mdcfg2, 0x01ff00db);
++
++ /* other parms */
++ out_be32(&mmdc->mdmisc, 0x00000680);
++ out_be32(&mmdc->mpmur0, 0x00000800);
++ out_be32(&mmdc->mdrwd, 0x00002000);
++ out_be32(&mmdc->mpodtctrl, 0x0000022a);
++
++ /* out of reset delays */
++ out_be32(&mmdc->mdor, 0x00bf1023);
++
++ /* physical parms */
++ out_be32(&mmdc->mdctl, 0x05180000);
++ out_be32(&mmdc->mdasp, 0x0000007f);
++
++ /* Enable MMDC */
++ out_be32(&mmdc->mdctl, 0x85180000);
++
++ /* dram init sequence: update MRs */
++ out_be32(&mmdc->mdscr, 0x00088032);
++ out_be32(&mmdc->mdscr, 0x00008033);
++ out_be32(&mmdc->mdscr, 0x00048031);
++ out_be32(&mmdc->mdscr, 0x19308030);
++
++ /* dram init sequence: ZQCL */
++ out_be32(&mmdc->mdscr, 0x04008040);
++ out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
++
++ mdelay(100);
++
++ /* Calibrations now: wr lvl */
++ out_be32(&mmdc->mdscr, 0x00848031);
++ out_be32(&mmdc->mdscr, 0x00008200);
++ out_be32(&mmdc->mpwlgcr, 0x00000001);
++
++ mdelay(100);
++
++ out_be32(&mmdc->mdscr, 0x00048031);
++ out_be32(&mmdc->mdscr, 0x00008000);
++
++ /* manual_refresh */
++ out_be32(&mmdc->mdscr, 0x00008020);
++
++ mdelay(100);
++
++ /* Calibrations now: Read DQS gating calibration */
++ out_be32(&mmdc->mdscr, 0x04008050);
++ out_be32(&mmdc->mdscr, 0x00048033);
++ out_be32(&mmdc->mppdcmpr2, 0x00000001);
++ out_be32(&mmdc->mprddlctl, 0x40404040);
++ out_be32(&mmdc->mpdgctrl0, 0x10000000);
++
++ mdelay(100);
++
++ out_be32(&mmdc->mdscr, 0x00008033);
++
++ /* manual_refresh */
++ out_be32(&mmdc->mdscr, 0x00008020);
++
++ mdelay(100);
++
++ /* Calibrations now: Read calibration */
++ out_be32(&mmdc->mdscr, 0x04008050);
++ out_be32(&mmdc->mdscr, 0x00048033);
++ out_be32(&mmdc->mppdcmpr2, 0x00000001);
++ out_be32(&mmdc->mprddlhwctl, 0x00000010);
++
++ mdelay(400);
++
++ out_be32(&mmdc->mdscr, 0x00008033);
++
++ /* manual_refresh */
++ out_be32(&mmdc->mdscr, 0x00008020);
++
++ mdelay(100);
++
++ /* PD, SR */
++ out_be32(&mmdc->mdpdc, 0x00030035);
++ out_be32(&mmdc->mapsr, 0x00001067);
++
++ /* refresh scheme */
++ out_be32(&mmdc->mdref, 0x103e8000);
++
++ mdelay(400);
++
++ /* disable CON_REQ */
++ out_be32(&mmdc->mdscr, 0x0);
++
++ mdelay(50);
++}
++
++int dram_init(void)
++{
++ mmdc_init();
++
++ gd->ram_size = 0x40000000;
++
++ return 0;
++}
++
++int board_eth_init(bd_t *bis)
++{
++ return pci_eth_init(bis);
++}
++
++int board_early_init_f(void)
++{
++ fsl_lsch2_early_init_f();
++
++ return 0;
++}
++
++int board_init(void)
++{
++ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
++ /*
++ * Set CCI-400 control override register to enable barrier
++ * transaction
++ */
++ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
++
++#ifdef CONFIG_ENV_IS_NOWHERE
++ gd->env_addr = (ulong)&default_environment[0];
++#endif
++
++#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
++ enable_layerscape_ns_access();
++#endif
++
++ return 0;
++}
++
++int ft_board_setup(void *blob, bd_t *bd)
++{
++ u64 base[CONFIG_NR_DRAM_BANKS];
++ u64 size[CONFIG_NR_DRAM_BANKS];
++
++ /* fixup DT for the two DDR banks */
++ base[0] = gd->bd->bi_dram[0].start;
++ size[0] = gd->bd->bi_dram[0].size;
++ base[1] = gd->bd->bi_dram[1].start;
++ size[1] = gd->bd->bi_dram[1].size;
++
++ fdt_fixup_memory_banks(blob, base, size, 2);
++ ft_cpu_setup(blob, bd);
++
++ return 0;
++}
+diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
+new file mode 100644
+index 0000000..f819038
+--- /dev/null
++++ b/configs/ls1012ardb_qspi_defconfig
+@@ -0,0 +1,10 @@
++CONFIG_ARM=y
++CONFIG_TARGET_LS1012ARDB=y
++CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
++# CONFIG_CMD_IMLS is not set
++CONFIG_SYS_NS16550=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
++CONFIG_OF_CONTROL=y
++CONFIG_DM=y
++CONFIG_SPI_FLASH=y
++CONFIG_DM_SPI=y
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 9ed04f9..3fd360a 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -12,7 +12,7 @@
+ #define CONFIG_LS1012A
+ #define CONFIG_GICV2
+
+-#define CONFIG_SYS_HAS_SERDES
++#define CONFIG_SYS_HAS_SERDES
+
+ #include <asm/arch/config.h>
+ #define CONFIG_SYS_NO_FLASH
+@@ -56,7 +56,6 @@
+ #define CONFIG_ENV_SPI_MODE 0x03
+ #define CONFIG_CMD_SF
+ #define CONFIG_SPI_FLASH_SPANSION
+-#define CONFIG_SPI_FLASH_ATMEL
+ #define CONFIG_FSL_SPI_INTERFACE
+ #define CONFIG_SF_DATAFLASH
+
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+new file mode 100644
+index 0000000..9ff5935
+--- /dev/null
++++ b/include/configs/ls1012ardb.h
+@@ -0,0 +1,61 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __LS1012ARDB_H__
++#define __LS1012ARDB_H__
++
++#include "ls1012a_common.h"
++
++
++#define CONFIG_DIMM_SLOTS_PER_CTLR 1
++#define CONFIG_CHIP_SELECTS_PER_CTRL 1
++#define CONFIG_NR_DRAM_BANKS 2
++
++#define CONFIG_CMD_MEMINFO
++#define CONFIG_CMD_MEMTEST
++#define CONFIG_SYS_MEMTEST_START 0x80000000
++#define CONFIG_SYS_MEMTEST_END 0x9fffffff
++
++#define CONFIG_PHYLIB
++#define CONFIG_PHY_REALTEK
++#define SGMII_PHY1_ADDR 0x0
++#define RGMII_PHY2_ADDR 0x1
++
++/*
++* USB
++*/
++#define CONFIG_HAS_FSL_XHCI_USB
++
++#ifdef CONFIG_HAS_FSL_XHCI_USB
++#define CONFIG_USB_XHCI
++#define CONFIG_USB_XHCI_FSL
++#define CONFIG_USB_XHCI_DWC3
++#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
++#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
++#define CONFIG_CMD_USB
++#define CONFIG_USB_STORAGE
++#define CONFIG_CMD_EXT2
++#endif
++
++/*
++ * I2C IO expander
++ */
++
++#define I2C_MUX_IO1_ADDR 0x24
++#define __SW_BOOT_MASK 0xFC
++#define __SW_BOOT_EMU 0x10
++#define __SW_BOOT_BANK1 0x00
++#define __SW_BOOT_BANK2 0x01
++#define __SW_REV_MASK 0x07
++#define __SW_REV_A 0xF8
++#define __SW_REV_B 0xF0
++
++#define CONFIG_CMD_MEMINFO
++#define CONFIG_CMD_MEMTEST
++#define CONFIG_SYS_MEMTEST_START 0x80000000
++#define CONFIG_SYS_MEMTEST_END 0x9fffffff
++
++#endif /* __LS1012ARDB_H__ */
+diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
+index 72a5d5b..7ab88c3 100644
+--- a/include/linux/usb/xhci-fsl.h
++++ b/include/linux/usb/xhci-fsl.h
+@@ -62,7 +62,7 @@ struct fsl_xhci {
+ #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+-#elif defined(CONFIG_LS1043A)
++#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
+ #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
+--
+1.7.9.5
+
--- /dev/null
+From 4aa3d79020aeca3780ea113a495d18662d593761 Mon Sep 17 00:00:00 2001
+From: Lokesh Vutla <lokeshvutla@ti.com>
+Date: Thu, 24 Mar 2016 16:02:00 +0530
+Subject: [PATCH 16/93] ARM: asm: types: Introduce DMA_ADDR_T_64BIT
+
+dma_addr_t holds any valid DMA address. If the DMA API only uses 32-bit
+addresses, dma_addr_t need only be 32 bits wide. Bus addresses, e.g., PCI BARs,
+may be wider than 32 bits, but drivers do memory-mapped I/O to ioremapped
+kernel virtual addresses, so they don't care about the size of the actual
+bus addresses.
+Also 32 bit ARM systems with LPAE enabled can use 64bit address space, but
+DMA still use 32bit address like in case of DRA7 and Keystone platforms.
+
+This is inspired from the Linux kernel types implementation[1]
+
+[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/include/linux/types.h#n142
+
+Acked-by: Lukasz Majewski <l.majewski@samsung.com>
+Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
+Reviewed-by: Tom Rini <trini@konsulko.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/Kconfig | 4 ++++
+ arch/arm/include/asm/types.h | 17 +++++++++++++++--
+ 2 files changed, 19 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 5c20801..b536684 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -7,6 +7,10 @@ config SYS_ARCH
+ config ARM64
+ bool
+
++config DMA_ADDR_T_64BIT
++ bool
++ default y if ARM64
++
+ config HAS_VBAR
+ bool
+
+diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
+index 388058e..d108915 100644
+--- a/arch/arm/include/asm/types.h
++++ b/arch/arm/include/asm/types.h
+@@ -46,16 +46,29 @@ typedef unsigned long long u64;
+ #endif /* CONFIG_ARM64 */
+
+ #ifdef CONFIG_PHYS_64BIT
+-typedef unsigned long long dma_addr_t;
+ typedef unsigned long long phys_addr_t;
+ typedef unsigned long long phys_size_t;
+ #else
+ /* DMA addresses are 32-bits wide */
+-typedef u32 dma_addr_t;
+ typedef unsigned long phys_addr_t;
+ typedef unsigned long phys_size_t;
+ #endif
+
++/*
++ * A dma_addr_t can hold any valid DMA address, i.e., any address returned
++ * by the DMA API.
++ *
++ * If the DMA API only uses 32-bit addresses, dma_addr_t need only be 32
++ * bits wide. Bus addresses, e.g., PCI BARs, may be wider than 32 bits,
++ * but drivers do memory-mapped I/O to ioremapped kernel virtual addresses,
++ * so they don't care about the size of the actual bus addresses.
++ */
++#ifdef CONFIG_DMA_ADDR_T_64BIT
++typedef unsigned long long dma_addr_t;
++#else
++typedef u32 dma_addr_t;
++#endif
++
+ #endif /* __KERNEL__ */
+
+ typedef unsigned long resource_size_t;
+--
+1.7.9.5
+
--- /dev/null
+From f160c56c71c59d2d865142fdeb3040e9cc4b6a77 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Mon, 25 Apr 2016 17:14:25 +0530
+Subject: [PATCH 17/93] armv8/fsl-layerscape: add dwc3 gadget driver support
+
+Implements the dwc3 gadget driver support for LS1043
+and LS1012 platform.
+
+NOTE: Do not upstream this patch.It needs rework for open source
+submission.
+
+Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 98 +++++++++++++++++++-
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++
+ .../include/asm/arch-fsl-layerscape/sys_proto.h | 10 ++
+ common/cmd_usb_mass_storage.c | 2 +-
+ drivers/usb/dwc3/core.c | 12 +++
+ drivers/usb/dwc3/ep0.c | 10 +-
+ drivers/usb/dwc3/gadget.c | 11 ++-
+ drivers/usb/dwc3/io.h | 8 +-
+ drivers/usb/gadget/f_mass_storage.c | 10 +-
+ include/configs/ls1012aqds.h | 15 +++
+ include/configs/ls1012ardb.h | 15 +++
+ include/configs/ls1043aqds.h | 15 +++
+ 12 files changed, 197 insertions(+), 15 deletions(-)
+ create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+index ec561a7..0a170eb 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+@@ -19,6 +19,10 @@
+ #ifdef CONFIG_CHAIN_OF_TRUST
+ #include <fsl_validate.h>
+ #endif
++#include <usb.h>
++#include <dwc3-uboot.h>
++#include <linux/usb/xhci-fsl.h>
++
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+@@ -406,9 +410,19 @@ void fsl_lsch2_early_init_f(void)
+ #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
+ out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+ #endif
+- /* Make SEC reads and writes snoopable */
++
++#if defined(CONFIG_LS1043A)
++ /* Make SEC and USB reads and writes snoopable */
+ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
+- SCFG_SNPCNFGCR_SECWRSNP);
++ SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
++ SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
++ SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
++ SCFG_SNPCNFGCR_USB3WRSNP);
++#elif defined(CONFIG_LS1012A)
++ /* Make SEC and reads and writes snoopable */
++ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP |
++ SCFG_SNPCNFGCR_USB1RDSNP | SCFG_SNPCNFGCR_USB1WRSNP);
++#endif
+
+ /*
+ * Enable snoop requests and DVM message requests for
+@@ -428,6 +442,86 @@ void fsl_lsch2_early_init_f(void)
+ }
+ #endif
+
++#ifdef CONFIG_USB_DWC3
++
++#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
++static struct dwc3_device dwc3_device_data0 = {
++ .maximum_speed = USB_SPEED_HIGH,
++ .base = CONFIG_SYS_FSL_XHCI_USB1_ADDR,
++ .dr_mode = USB_DR_MODE_PERIPHERAL,
++ .index = 0,
++};
++
++#if defined(CONFIG_LS1043A)
++static struct dwc3_device dwc3_device_data1 = {
++ .maximum_speed = USB_SPEED_HIGH,
++ .base = CONFIG_SYS_FSL_XHCI_USB2_ADDR,
++ .dr_mode = USB_DR_MODE_PERIPHERAL,
++ .index = 1,
++};
++
++static struct dwc3_device dwc3_device_data2 = {
++ .maximum_speed = USB_SPEED_HIGH,
++ .base = CONFIG_SYS_FSL_XHCI_USB3_ADDR,
++ .dr_mode = USB_DR_MODE_PERIPHERAL,
++ .index = 2,
++};
++#endif
++
++int usb_gadget_handle_interrupts(int index)
++{
++ dwc3_uboot_handle_interrupt(index);
++ return 0;
++}
++#endif
++
++int board_usb_init(int index, enum usb_init_type init)
++{
++ switch (init) {
++ case USB_INIT_DEVICE:
++ switch (index) {
++#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
++ case 0:
++ dwc3_uboot_init(&dwc3_device_data0);
++ break;
++
++#if defined(CONFIG_LS1043A)
++ case 1:
++ dwc3_uboot_init(&dwc3_device_data1);
++ break;
++ case 2:
++ dwc3_uboot_init(&dwc3_device_data2);
++ break;
++#endif
++#endif
++ default:
++ printf("Invalid Controller Index\n");
++ return -1;
++ }
++ break;
++ default:
++ break;
++ }
++ return 0;
++}
++
++int board_usb_cleanup(int index, enum usb_init_type init)
++{
++ switch (init) {
++ case USB_INIT_DEVICE:
++#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
++ dwc3_uboot_exit(index);
++#endif
++ break;
++ default:
++ break;
++ }
++ return 0;
++}
++#endif
++
++
++
+ #ifdef CONFIG_BOARD_LATE_INIT
+ int board_late_init(void)
+ {
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index 5b026f8..414a222 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -355,6 +355,12 @@ struct ccsr_gur {
+
+ #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
+ #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
++#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000
++#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000
++#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000
++#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000
++#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000
++#define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000
+
+ /* Supplemental Configuration Unit */
+ struct ccsr_scfg {
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
+new file mode 100644
+index 0000000..1e31d3d
+--- /dev/null
++++ b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
+@@ -0,0 +1,10 @@
++/*
++ * Copyright 2015 Freescale Semiconductor
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SYS_PROTO_H_
++#define _ASM_ARMV8_FSL_LAYERSCAPE_SYS_PROTO_H_
++
++#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SYS_PROTO_H_ */
+diff --git a/common/cmd_usb_mass_storage.c b/common/cmd_usb_mass_storage.c
+index 0407389..7d507b5 100644
+--- a/common/cmd_usb_mass_storage.c
++++ b/common/cmd_usb_mass_storage.c
+@@ -140,7 +140,7 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
+ while (1) {
+ usb_gadget_handle_interrupts(controller_index);
+
+- rc = fsg_main_thread(NULL);
++ rc = fsg_main_thread(&controller_index);
+ if (rc) {
+ /* Check I/O error */
+ if (rc == -EIO)
+diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
+index 85cc96a..b8e4066 100644
+--- a/drivers/usb/dwc3/core.c
++++ b/drivers/usb/dwc3/core.c
+@@ -690,6 +690,18 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
+ return -ENOMEM;
+ }
+
++#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
++ /* Change burst beat and outstanding pipelined transfers requests */
++ dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
++ (dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) & ~0xff) | 0xf);
++ dwc3_writel(dwc->regs, DWC3_GSBUSCFG1,
++ dwc3_readl(dwc->regs, DWC3_GSBUSCFG1) | 0xf00);
++
++ /* Enable snooping */
++ dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
++ dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) | 0x22220000);
++#endif
++
+ if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
+ dwc->dr_mode = USB_DR_MODE_HOST;
+ else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
+diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
+index 12b133f..e61d980 100644
+--- a/drivers/usb/dwc3/ep0.c
++++ b/drivers/usb/dwc3/ep0.c
+@@ -81,8 +81,8 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
+ trb->ctrl |= (DWC3_TRB_CTRL_IOC
+ | DWC3_TRB_CTRL_LST);
+
+- dwc3_flush_cache((long)buf_dma, len);
+- dwc3_flush_cache((long)trb, sizeof(*trb));
++ dwc3_flush_cache((uintptr_t)buf_dma, len);
++ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
+
+ if (chain)
+ return 0;
+@@ -790,7 +790,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
+ if (!r)
+ return;
+
+- dwc3_flush_cache((long)trb, sizeof(*trb));
++ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
+
+ status = DWC3_TRB_SIZE_TRBSTS(trb->size);
+ if (status == DWC3_TRBSTS_SETUP_PENDING) {
+@@ -821,7 +821,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
+ ur->actual += transferred;
+
+ trb++;
+- dwc3_flush_cache((long)trb, sizeof(*trb));
++ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
+ length = trb->size & DWC3_TRB_SIZE_MASK;
+
+ ep0->free_slot = 0;
+@@ -831,7 +831,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
+ maxp);
+ transferred = min_t(u32, ur->length - transferred,
+ transfer_size - length);
+- dwc3_flush_cache((long)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
++ dwc3_flush_cache((uintptr_t)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
+ memcpy(buf, dwc->ep0_bounce, transferred);
+ } else {
+ transferred = ur->length - length;
+diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
+index 8ff949d..649f1a4 100644
+--- a/drivers/usb/dwc3/gadget.c
++++ b/drivers/usb/dwc3/gadget.c
+@@ -244,7 +244,7 @@ void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
+
+ list_del(&req->list);
+ req->trb = NULL;
+- dwc3_flush_cache((long)req->request.dma, req->request.length);
++ dwc3_flush_cache((uintptr_t)req->request.dma, req->request.length);
+
+ if (req->request.status == -EINPROGRESS)
+ req->request.status = status;
+@@ -771,8 +771,8 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
+
+ trb->ctrl |= DWC3_TRB_CTRL_HWO;
+
+- dwc3_flush_cache((long)dma, length);
+- dwc3_flush_cache((long)trb, sizeof(*trb));
++ dwc3_flush_cache((uintptr_t)dma, length);
++ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
+ }
+
+ /*
+@@ -1769,7 +1769,7 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
+ slot %= DWC3_TRB_NUM;
+ trb = &dep->trb_pool[slot];
+
+- dwc3_flush_cache((long)trb, sizeof(*trb));
++ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
+ __dwc3_cleanup_done_trbs(dwc, dep, req, trb, event, status);
+ dwc3_gadget_giveback(dep, req, status);
+
+@@ -2447,6 +2447,7 @@ static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
+ int left;
+ u32 reg;
+
++
+ evt = dwc->ev_buffs[buf];
+ left = evt->count;
+
+@@ -2670,7 +2671,7 @@ void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
+
+ for (i = 0; i < dwc->num_event_buffers; i++) {
+ evt = dwc->ev_buffs[i];
+- dwc3_flush_cache((long)evt->buf, evt->length);
++ dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
+ }
+
+ dwc3_thread_interrupt(0, dwc);
+diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h
+index 0d9fa22..cab5122 100644
+--- a/drivers/usb/dwc3/io.h
++++ b/drivers/usb/dwc3/io.h
+@@ -48,8 +48,14 @@ static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value)
+ writel(value, base + offs);
+ }
+
+-static inline void dwc3_flush_cache(int addr, int length)
++static inline void dwc3_flush_cache(uintptr_t addr, int length)
+ {
+ flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
+ }
++
++static inline void dwc3_inval_cache(uintptr_t addr, int length)
++{
++ invalidate_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
++}
++
+ #endif /* __DRIVERS_USB_DWC3_IO_H */
+diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
+index ec1f23a..ec0229f 100644
+--- a/drivers/usb/gadget/f_mass_storage.c
++++ b/drivers/usb/gadget/f_mass_storage.c
+@@ -362,6 +362,7 @@ struct fsg_common {
+ char inquiry_string[8 + 16 + 4 + 1];
+
+ struct kref ref;
++ unsigned int controller_index;
+ };
+
+ struct fsg_config {
+@@ -690,7 +691,7 @@ static int sleep_thread(struct fsg_common *common)
+ k = 0;
+ }
+
+- usb_gadget_handle_interrupts(0);
++ usb_gadget_handle_interrupts(common->controller_index);
+ }
+ common->thread_wakeup_needed = 0;
+ return rc;
+@@ -2405,6 +2406,11 @@ int fsg_main_thread(void *common_)
+ {
+ int ret;
+ struct fsg_common *common = the_fsg_common;
++
++ /* update the controller_index */
++ if (common_)
++ common->controller_index = *(unsigned int *)common_;
++
+ /* The main loop */
+ do {
+ if (exception_in_progress(common)) {
+@@ -2475,6 +2481,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common,
+
+ common->ops = NULL;
+ common->private_data = NULL;
++ common->controller_index = 0;
+
+ common->gadget = gadget;
+ common->ep0 = gadget->ep0;
+@@ -2769,6 +2776,7 @@ int fsg_add(struct usb_configuration *c)
+
+ fsg_common->ops = NULL;
+ fsg_common->private_data = NULL;
++ fsg_common->controller_index = 0;
+
+ the_fsg_common = fsg_common;
+
+diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
+index 6346d3e..fdada18 100644
+--- a/include/configs/ls1012aqds.h
++++ b/include/configs/ls1012aqds.h
+@@ -123,6 +123,21 @@
+ #define CONFIG_CMD_USB
+ #define CONFIG_USB_STORAGE
+ #define CONFIG_CMD_EXT2
++
++#define CONFIG_USB_DWC3
++#define CONFIG_USB_DWC3_GADGET
++
++#define CONFIG_USB_GADGET
++#define CONFIG_USB_FUNCTION_MASS_STORAGE
++#define CONFIG_USB_GADGET_DOWNLOAD
++#define CONFIG_USB_GADGET_VBUS_DRAW 2
++#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
++#define CONFIG_G_DNL_VENDOR_NUM 0x1234
++#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
++#define CONFIG_USB_GADGET_DUALSPEED
++
++/* USB Gadget ums command */
++#define CONFIG_CMD_USB_MASS_STORAGE
+ #endif
+
+ #define CONFIG_CMD_MEMINFO
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index 9ff5935..af3d33f 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -38,6 +38,21 @@
+ #define CONFIG_CMD_USB
+ #define CONFIG_USB_STORAGE
+ #define CONFIG_CMD_EXT2
++
++#define CONFIG_USB_DWC3
++#define CONFIG_USB_DWC3_GADGET
++
++#define CONFIG_USB_GADGET
++#define CONFIG_USB_FUNCTION_MASS_STORAGE
++#define CONFIG_USB_GADGET_DOWNLOAD
++#define CONFIG_USB_GADGET_VBUS_DRAW 2
++#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
++#define CONFIG_G_DNL_VENDOR_NUM 0x1234
++#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
++#define CONFIG_USB_GADGET_DUALSPEED
++
++/* USB Gadget ums command */
++#define CONFIG_CMD_USB_MASS_STORAGE
+ #endif
+
+ /*
+diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
+index 9828360..9e23615 100644
+--- a/include/configs/ls1043aqds.h
++++ b/include/configs/ls1043aqds.h
+@@ -400,6 +400,21 @@ unsigned long get_board_ddr_clk(void);
+ #define CONFIG_CMD_USB
+ #define CONFIG_USB_STORAGE
+ #define CONFIG_CMD_EXT2
++
++#define CONFIG_USB_DWC3
++#define CONFIG_USB_DWC3_GADGET
++
++#define CONFIG_USB_GADGET
++#define CONFIG_USB_FUNCTION_MASS_STORAGE
++#define CONFIG_USB_GADGET_DOWNLOAD
++#define CONFIG_USB_GADGET_VBUS_DRAW 2
++#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
++#define CONFIG_G_DNL_VENDOR_NUM 0x1234
++#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
++#define CONFIG_USB_GADGET_DUALSPEED
++
++/* USB Gadget ums command */
++#define CONFIG_CMD_USB_MASS_STORAGE
+ #endif
+
+ /*
+--
+1.7.9.5
+
--- /dev/null
+From 035a4db85bbf28ba1452c49c9f8d05a085f2544b Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Tue, 26 Apr 2016 17:40:05 +0530
+Subject: [PATCH 18/93] boards: ls1012aqds: Enable SDHC_CD in brdcfg10 of FPGA
+
+Default configuration of brdcfg10 in FPGA does not enable SDHC_CD
+signal.
+
+Enable SDHC_CD by default during boot sequence.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ board/freescale/ls1012aqds/ls1012aqds.c | 12 ++++++++++++
+ include/configs/ls1012aqds.h | 3 +++
+ 2 files changed, 15 insertions(+)
+
+diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
+index ffcd0d8..6d5fef8 100644
+--- a/board/freescale/ls1012aqds/ls1012aqds.c
++++ b/board/freescale/ls1012aqds/ls1012aqds.c
+@@ -154,6 +154,18 @@ int board_early_init_f(void)
+ return 0;
+ }
+
++#ifdef CONFIG_MISC_INIT_R
++int misc_init_r(void)
++{
++ u8 mux_sdhc_cd = 0x80;
++
++ i2c_set_bus_num(0);
++
++ i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
++ return 0;
++}
++#endif
++
+ int board_init(void)
+ {
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
+diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
+index fdada18..bb433de 100644
+--- a/include/configs/ls1012aqds.h
++++ b/include/configs/ls1012aqds.h
+@@ -27,6 +27,7 @@
+ #endif
+
+ #define CONFIG_QIXIS_I2C_ACCESS
++#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+
+ /*
+ * I2C bus multiplexer
+@@ -145,4 +146,6 @@
+ #define CONFIG_SYS_MEMTEST_START 0x80000000
+ #define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
++#define CONFIG_MISC_INIT_R
++
+ #endif /* __LS1012AQDS_H__ */
+--
+1.7.9.5
+
--- /dev/null
+From 8aad7c4c5d8becaf6c60e1585c8e70010b3c0ce2 Mon Sep 17 00:00:00 2001
+From: Makarand Pawagi <makarand.pawagi@mindspeed.com>
+Date: Mon, 2 May 2016 09:33:45 +0530
+Subject: [PATCH 19/93] armv8: ls1012a: Add CSU assignment for eSDHC2, SAI1,
+ SAI2, SAI3, SAI4
+
+ Access settings for different IPs has to be enabled through CSU registers. Following
+ IP's are added for LS1012A:
+ Added CSU ID for eSDHC-2, reg: CSL40_REG[23:16]
+ Added CSU ID for SAI-1, reg: CSL41_REG[7:0]
+ Added CSU ID for SAI-2, reg: CSL41_REG[23:16]
+ Added CSU ID for SAI-3, reg: CSL42_REG[7:0]
+ Added CSU ID for SAI-4, reg: CSL42_REG[23:16
+---
+ .../include/asm/arch-fsl-layerscape/ns_access.h | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+index a3ccdb0..d6642a7 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+@@ -69,7 +69,12 @@ enum csu_cslx_ind {
+ CSU_CSLX_IIC4 = 77,
+ CSU_CSLX_WDT4,
+ CSU_CSLX_WDT3,
++ CSU_CSLX_ESDHC2 = 80,
+ CSU_CSLX_WDT5 = 81,
++ CSU_CSLX_SAI2,
++ CSU_CSLX_SAI1,
++ CSU_CSLX_SAI4,
++ CSU_CSLX_SAI3,
+ CSU_CSLX_FTM2 = 86,
+ CSU_CSLX_FTM1,
+ CSU_CSLX_FTM4,
+@@ -143,7 +148,12 @@ static struct csu_ns_dev ns_dev[] = {
+ {CSU_CSLX_IIC4, CSU_ALL_RW},
+ {CSU_CSLX_WDT4, CSU_ALL_RW},
+ {CSU_CSLX_WDT3, CSU_ALL_RW},
++ {CSU_CSLX_ESDHC2, CSU_ALL_RW},
+ {CSU_CSLX_WDT5, CSU_ALL_RW},
++ {CSU_CSLX_SAI2, CSU_ALL_RW},
++ {CSU_CSLX_SAI1, CSU_ALL_RW},
++ {CSU_CSLX_SAI4, CSU_ALL_RW},
++ {CSU_CSLX_SAI3, CSU_ALL_RW},
+ {CSU_CSLX_FTM2, CSU_ALL_RW},
+ {CSU_CSLX_FTM1, CSU_ALL_RW},
+ {CSU_CSLX_FTM4, CSU_ALL_RW},
+--
+1.7.9.5
+
--- /dev/null
+From e8703a5bba4bc0e9fa6aefe0eae7caf9141b8bdc Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Mon, 2 May 2016 18:28:16 +0530
+Subject: [PATCH 20/93] armv8: ls1012a: Update DDR init sequence
+
+Current DDR init code uses lots of delay.
+
+Use wait for bit clear instead of delays.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ board/freescale/ls1012aqds/ls1012aqds.c | 67 +++++++++++++++++--------------
+ board/freescale/ls1012ardb/ls1012ardb.c | 54 +++++++++++--------------
+ 2 files changed, 60 insertions(+), 61 deletions(-)
+
+diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
+index 6d5fef8..5cb225f 100644
+--- a/board/freescale/ls1012aqds/ls1012aqds.c
++++ b/board/freescale/ls1012aqds/ls1012aqds.c
+@@ -28,6 +28,20 @@
+
+ DECLARE_GLOBAL_DATA_PTR;
+
++static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
++{
++ int timeout = 1000;
++
++ out_be32(ptr, value);
++
++ while (in_be32(ptr) & bits) {
++ udelay(100);
++ timeout--;
++ }
++ if (timeout <= 0)
++ puts("Error: wait for clear timeout.\n");
++}
++
+ int checkboard(void)
+ {
+ puts("Board: LS1012AQDS\n");
+@@ -44,7 +58,7 @@ void mmdc_init(void)
+ out_be32(&mmdc->mdscr, 0x00008000);
+
+ /* configure timing parms */
+- out_be32(&mmdc->mdotc, 0x12554000);
++ out_be32(&mmdc->mdotc, 0x12554000);
+ out_be32(&mmdc->mdcfg0, 0xbabf7954);
+ out_be32(&mmdc->mdcfg1, 0xff328f64);
+ out_be32(&mmdc->mdcfg2, 0x01ff00db);
+@@ -56,7 +70,7 @@ void mmdc_init(void)
+ out_be32(&mmdc->mpodtctrl, 0x0000022a);
+
+ /* out of reset delays */
+- out_be32(&mmdc->mdor, 0x00bf1023);
++ out_be32(&mmdc->mdor, 0x00bf1023);
+
+ /* physical parms */
+ out_be32(&mmdc->mdctl, 0x05180000);
+@@ -73,69 +87,60 @@ void mmdc_init(void)
+
+ /* dram init sequence: ZQCL */
+ out_be32(&mmdc->mdscr, 0x04008040);
+- out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
+-
+- mdelay(100);
++ set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
+
+ /* Calibrations now: wr lvl */
+ out_be32(&mmdc->mdscr, 0x00848031);
+ out_be32(&mmdc->mdscr, 0x00008200);
+- out_be32(&mmdc->mpwlgcr, 0x00000001);
++ set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
+
+- mdelay(100);
++ mdelay(1);
+
+ out_be32(&mmdc->mdscr, 0x00048031);
+ out_be32(&mmdc->mdscr, 0x00008000);
+
+- /* manual_refresh */
+- out_be32(&mmdc->mdscr, 0x00008020);
+-
+- mdelay(100);
++ mdelay(1);
+
+ /* Calibrations now: Read DQS gating calibration */
+ out_be32(&mmdc->mdscr, 0x04008050);
+ out_be32(&mmdc->mdscr, 0x00048033);
+ out_be32(&mmdc->mppdcmpr2, 0x00000001);
+ out_be32(&mmdc->mprddlctl, 0x40404040);
+- out_be32(&mmdc->mpdgctrl0, 0x10000000);
+-
+- mdelay(100);
++ set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
+
+ out_be32(&mmdc->mdscr, 0x00008033);
+
+- /* manual_refresh */
+- out_be32(&mmdc->mdscr, 0x00008020);
+-
+- mdelay(100);
+
+ /* Calibrations now: Read calibration */
+ out_be32(&mmdc->mdscr, 0x04008050);
+ out_be32(&mmdc->mdscr, 0x00048033);
+ out_be32(&mmdc->mppdcmpr2, 0x00000001);
+- out_be32(&mmdc->mprddlhwctl, 0x00000010);
+-
+- mdelay(400);
++ set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
+
+ out_be32(&mmdc->mdscr, 0x00008033);
+
+- /* manual_refresh */
+- out_be32(&mmdc->mdscr, 0x00008020);
+-
+- mdelay(100);
+-
+ /* PD, SR */
+ out_be32(&mmdc->mdpdc, 0x00030035);
+ out_be32(&mmdc->mapsr, 0x00001067);
+
+ /* refresh scheme */
+- out_be32(&mmdc->mdref, 0x103e8000);
+-
+- mdelay(400);
++ set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
+
+ /* disable CON_REQ */
+ out_be32(&mmdc->mdscr, 0x0);
++}
+
+- mdelay(50);
++int select_i2c_ch_pca9547(u8 ch)
++{
++ int ret;
++
++ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
++ if (ret) {
++ puts("PCA: failed to select proper channel\n");
++ return ret;
++ }
++
++ return 0;
+ }
+
+ int dram_init(void)
+@@ -183,6 +188,8 @@ int board_init(void)
+ #ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+ #endif
++ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
++
+ return 0;
+ }
+
+diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
+index 4a7aaaa..f7b9bce 100644
+--- a/board/freescale/ls1012ardb/ls1012ardb.c
++++ b/board/freescale/ls1012ardb/ls1012ardb.c
+@@ -23,6 +23,20 @@
+
+ DECLARE_GLOBAL_DATA_PTR;
+
++static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
++{
++ int timeout = 1000;
++
++ out_be32(ptr, value);
++
++ while (in_be32(ptr) & bits) {
++ udelay(100);
++ timeout--;
++ }
++ if (timeout <= 0)
++ puts("Error: wait for clear timeout.\n");
++}
++
+ int checkboard(void)
+ {
+ u8 in1;
+@@ -67,7 +81,7 @@ void mmdc_init(void)
+ out_be32(&mmdc->mdscr, 0x00008000);
+
+ /* configure timing parms */
+- out_be32(&mmdc->mdotc, 0x12554000);
++ out_be32(&mmdc->mdotc, 0x12554000);
+ out_be32(&mmdc->mdcfg0, 0xbabf7954);
+ out_be32(&mmdc->mdcfg1, 0xff328f64);
+ out_be32(&mmdc->mdcfg2, 0x01ff00db);
+@@ -79,7 +93,7 @@ void mmdc_init(void)
+ out_be32(&mmdc->mpodtctrl, 0x0000022a);
+
+ /* out of reset delays */
+- out_be32(&mmdc->mdor, 0x00bf1023);
++ out_be32(&mmdc->mdor, 0x00bf1023);
+
+ /* physical parms */
+ out_be32(&mmdc->mdctl, 0x05180000);
+@@ -96,69 +110,47 @@ void mmdc_init(void)
+
+ /* dram init sequence: ZQCL */
+ out_be32(&mmdc->mdscr, 0x04008040);
+- out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
+-
+- mdelay(100);
++ set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
+
+ /* Calibrations now: wr lvl */
+ out_be32(&mmdc->mdscr, 0x00848031);
+ out_be32(&mmdc->mdscr, 0x00008200);
+- out_be32(&mmdc->mpwlgcr, 0x00000001);
++ set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
+
+- mdelay(100);
++ mdelay(1);
+
+ out_be32(&mmdc->mdscr, 0x00048031);
+ out_be32(&mmdc->mdscr, 0x00008000);
+
+- /* manual_refresh */
+- out_be32(&mmdc->mdscr, 0x00008020);
+-
+- mdelay(100);
++ mdelay(1);
+
+ /* Calibrations now: Read DQS gating calibration */
+ out_be32(&mmdc->mdscr, 0x04008050);
+ out_be32(&mmdc->mdscr, 0x00048033);
+ out_be32(&mmdc->mppdcmpr2, 0x00000001);
+ out_be32(&mmdc->mprddlctl, 0x40404040);
+- out_be32(&mmdc->mpdgctrl0, 0x10000000);
+-
+- mdelay(100);
++ set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
+
+ out_be32(&mmdc->mdscr, 0x00008033);
+
+- /* manual_refresh */
+- out_be32(&mmdc->mdscr, 0x00008020);
+-
+- mdelay(100);
+
+ /* Calibrations now: Read calibration */
+ out_be32(&mmdc->mdscr, 0x04008050);
+ out_be32(&mmdc->mdscr, 0x00048033);
+ out_be32(&mmdc->mppdcmpr2, 0x00000001);
+- out_be32(&mmdc->mprddlhwctl, 0x00000010);
+-
+- mdelay(400);
++ set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
+
+ out_be32(&mmdc->mdscr, 0x00008033);
+
+- /* manual_refresh */
+- out_be32(&mmdc->mdscr, 0x00008020);
+-
+- mdelay(100);
+-
+ /* PD, SR */
+ out_be32(&mmdc->mdpdc, 0x00030035);
+ out_be32(&mmdc->mapsr, 0x00001067);
+
+ /* refresh scheme */
+- out_be32(&mmdc->mdref, 0x103e8000);
+-
+- mdelay(400);
++ set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
+
+ /* disable CON_REQ */
+ out_be32(&mmdc->mdscr, 0x0);
+-
+- mdelay(50);
+ }
+
+ int dram_init(void)
+--
+1.7.9.5
+
--- /dev/null
+From 90ded6778736d5a0843d24eb8e5a47db72c05af9 Mon Sep 17 00:00:00 2001
+From: Mingkai Hu <mingkai.hu@nxp.com>
+Date: Mon, 18 Apr 2016 22:44:21 +0800
+Subject: [PATCH 21/93] sf: set the Uniform Sector to CR3NV instead of CR3V
+
+Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
+---
+ drivers/mtd/spi/spi_flash.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
+index 865e929..97e53c7 100644
+--- a/drivers/mtd/spi/spi_flash.c
++++ b/drivers/mtd/spi/spi_flash.c
+@@ -942,7 +942,7 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
+ static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
+ {
+ u8 cmd[4];
+- u32 offset = 0x800004; /* CR3V register offset */
++ u32 offset = 0x000004; /* CR3NV register offset */
+ u8 cr3v;
+ int ret;
+
+--
+1.7.9.5
+
--- /dev/null
+From 46c9963880e5cba6390864477f19b25369c6c944 Mon Sep 17 00:00:00 2001
+From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Date: Thu, 5 May 2016 15:01:02 +0530
+Subject: [PATCH 22/93] include: usb: Rename USB controller base address
+ mapping
+
+[context adjustment]
+
+Remove Soc specific defines and use generic chasis specific defines
+for USB controller base address mapping.
+
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 +++---
+ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++--
+ arch/arm/include/asm/arch-ls102xa/config.h | 6 ++----
+ include/linux/usb/xhci-fsl.h | 20 ++++++++------------
+ include/usb/ehci-fsl.h | 2 +-
+ 5 files changed, 16 insertions(+), 22 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index 414a222..3e37f00 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -33,9 +33,9 @@
+ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
+ #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
+ #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
+-#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
+-#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
+-#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
++#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
++#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
++#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
+ #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
+ #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+index 0ab709c..cf1f37a 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+@@ -51,8 +51,8 @@
+ #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
+ #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
+
+-#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+-#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
++#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
++#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
+
+ /* TZ Address Space Controller Definitions */
+ #define TZASC1_BASE 0x01100000 /* as per CCSR map. */
+diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
+index 926ac58..05fff80 100644
+--- a/arch/arm/include/asm/arch-ls102xa/config.h
++++ b/arch/arm/include/asm/arch-ls102xa/config.h
+@@ -36,13 +36,11 @@
+ #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
+ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
+ #define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
+-#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+-#define CONFIG_SYS_LS102XA_USB1_ADDR \
+- (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
++#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
++#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
+
+ #define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
+ #define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
+-#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
+ #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
+ #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
+ #define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
+diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
+index 7ab88c3..b2b3264 100644
+--- a/include/linux/usb/xhci-fsl.h
++++ b/include/linux/usb/xhci-fsl.h
+@@ -54,22 +54,18 @@ struct fsl_xhci {
+ struct dwc3 *dwc3_reg;
+ };
+
+-#if defined(CONFIG_LS102XA)
+-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
++#if defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A)
++#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+ #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+ #elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
+-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
+-#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+-#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
+-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
+-#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
+-#elif defined(CONFIG_LS1012A)
+-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
++#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
++#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
++#elif defined(CONFIG_LS1043A)
++#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
++#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
++#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR
+ #endif
+
+ #define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
+diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
+index e9349b5..b8d78d0 100644
+--- a/include/usb/ehci-fsl.h
++++ b/include/usb/ehci-fsl.h
+@@ -164,7 +164,7 @@
+ #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
+ #define CONFIG_SYS_FSL_USB2_ADDR 0
+ #elif defined(CONFIG_LS102XA)
+-#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
++#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
+ #define CONFIG_SYS_FSL_USB2_ADDR 0
+ #endif
+
+--
+1.7.9.5
+
--- /dev/null
+From 271adb5c0546b080fb350a41520c600a16739f1a Mon Sep 17 00:00:00 2001
+From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Date: Fri, 6 May 2016 09:05:29 +0530
+Subject: [PATCH 23/93] drivers: usb: fsl: add USB ULPI init code
+
+This adds the required code to set up a ULPI USB port, for
+new NXP USB PHY used in QorIQ platforms.
+
+To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT
+have to be set in the board configuration file.
+
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+---
+ drivers/usb/host/ehci-fsl.c | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
+index 97b7f14..3f06345 100644
+--- a/drivers/usb/host/ehci-fsl.c
++++ b/drivers/usb/host/ehci-fsl.c
+@@ -16,6 +16,9 @@
+ #include <hwconfig.h>
+ #include <fsl_usb.h>
+ #include <fdt_support.h>
++#ifdef CONFIG_USB_ULPI
++#include <usb/ulpi.h>
++#endif
+
+ #include "ehci.h"
+
+@@ -50,6 +53,10 @@ int ehci_hcd_init(int index, enum usb_init_type init,
+ const char *phy_type = NULL;
+ size_t len;
+ char current_usb_controller[5];
++#ifdef CONFIG_USB_ULPI
++ int ret;
++ struct ulpi_viewport ulpi_vp;
++#endif
+ #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+ char usb_phy[5];
+
+@@ -126,6 +133,20 @@ int ehci_hcd_init(int index, enum usb_init_type init,
+ udelay(1000); /* delay required for PHY Clk to appear */
+ if (!usb_phy_clk_valid(ehci))
+ return -EINVAL;
++
++#ifdef CONFIG_USB_ULPI
++ ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
++ ulpi_vp.port_num = 0;
++
++ ret = ulpi_init(&ulpi_vp);
++ if (ret) {
++ puts("NXP ULPI viewport init failed\n");
++ return -1;
++ }
++
++ ulpi_set_vbus(&ulpi_vp, 1, 1);
++ ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 1);
++#endif
+ out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
+ }
+
+--
+1.7.9.5
+
--- /dev/null
+From dec7ec15a9c2f2c3e0a09bb9cda8a24e4d469242 Mon Sep 17 00:00:00 2001
+From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Date: Fri, 6 May 2016 09:09:32 +0530
+Subject: [PATCH 24/93] config: ls1012aqds: Add USB EHCI support for
+ ls1012aqds
+
+Add USB EHCI support for ls1012aqds platform
+
+Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+---
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
+ include/configs/ls1012aqds.h | 5 +++++
+ include/usb/ehci-fsl.h | 2 +-
+ 3 files changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index 3e37f00..24add1a 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -36,6 +36,7 @@
+ #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
+ #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
+ #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
++#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
+ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
+ #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
+ #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
+diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
+index bb433de..51ca902 100644
+--- a/include/configs/ls1012aqds.h
++++ b/include/configs/ls1012aqds.h
+@@ -109,6 +109,8 @@
+ #ifdef CONFIG_HAS_FSL_DR_USB
+ #define CONFIG_USB_EHCI
+ #define CONFIG_USB_EHCI_FSL
++#define CONFIG_USB_ULPI
++#define CONFIG_USB_ULPI_VIEWPORT
+ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+ #endif
+
+@@ -121,6 +123,9 @@
+ #define CONFIG_USB_XHCI_DWC3
+ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+ #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
++#endif
++
++#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
+ #define CONFIG_CMD_USB
+ #define CONFIG_USB_STORAGE
+ #define CONFIG_CMD_EXT2
+diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
+index b8d78d0..94b1efa 100644
+--- a/include/usb/ehci-fsl.h
++++ b/include/usb/ehci-fsl.h
+@@ -163,7 +163,7 @@
+ #elif defined(CONFIG_MPC512X)
+ #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
+ #define CONFIG_SYS_FSL_USB2_ADDR 0
+-#elif defined(CONFIG_LS102XA)
++#elif defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A)
+ #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
+ #define CONFIG_SYS_FSL_USB2_ADDR 0
+ #endif
+--
+1.7.9.5
+
--- /dev/null
+From 93a1095c7da7291ffb12116de9122d431b9f6113 Mon Sep 17 00:00:00 2001
+From: Sumit Garg <sumit.garg@nxp.com>
+Date: Fri, 6 May 2016 11:11:58 -0400
+Subject: [PATCH 25/93] armv8: ls1012ardb: Add qspi SECURE BOOT target
+
+Add qspi SECURE BOOT target to enable chain of trust. Also enable
+sec_init in boot sequence.
+
+Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
+Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
+---
+ arch/arm/include/asm/arch-fsl-layerscape/config.h | 7 +++++++
+ arch/arm/include/asm/fsl_secure_boot.h | 7 ++++++-
+ board/freescale/ls1012ardb/ls1012ardb.c | 5 +++++
+ configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 10 ++++++++++
+ include/configs/ls1012ardb.h | 2 ++
+ 5 files changed, 30 insertions(+), 1 deletion(-)
+ create mode 100644 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
+index 6ea4e8e..679be6c 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
+@@ -237,6 +237,13 @@
+
+ #define CONFIG_SYS_FSL_ERRATUM_A009798
+
++#define CONFIG_SYS_FSL_SFP_VER_3_2
++#define CONFIG_SYS_FSL_SEC_MON_BE
++#define CONFIG_SYS_FSL_SEC_BE
++#define CONFIG_SYS_FSL_SFP_BE
++#define CONFIG_SYS_FSL_SRK_LE
++#define CONFIG_KEY_REVOCATION
++
+ #else
+ #error SoC not defined
+ #endif
+diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
+index c7f8b3e..c973255 100644
+--- a/arch/arm/include/asm/fsl_secure_boot.h
++++ b/arch/arm/include/asm/fsl_secure_boot.h
+@@ -50,7 +50,7 @@
+ #endif
+
+ #if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\
+- defined(CONFIG_LS2085A)
++ defined(CONFIG_LS2085A) || defined(CONFIG_LS1012A)
+ /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
+ * Similiarly for LS2080 and LS2085
+ */
+@@ -81,6 +81,11 @@
+ #define CONFIG_BS_ADDR_FLASH 0x583900000
+ #define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
+ #define CONFIG_BS_ADDR_RAM 0xa3900000
++#elif defined(CONFIG_LS1012A)
++#define CONFIG_BS_HDR_ADDR_FLASH 0x400c0000
++#define CONFIG_BS_ADDR_FLASH 0x40060000
++#define CONFIG_BS_HDR_ADDR_RAM 0xa0060000
++#define CONFIG_BS_ADDR_RAM 0xa0060000
+ #else
+ #define CONFIG_BS_HDR_ADDR_FLASH 0x600a0000
+ #define CONFIG_BS_ADDR_FLASH 0x60060000
+diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
+index f7b9bce..347b8c8 100644
+--- a/board/freescale/ls1012ardb/ls1012ardb.c
++++ b/board/freescale/ls1012ardb/ls1012ardb.c
+@@ -20,6 +20,7 @@
+ #include <environment.h>
+ #include <fsl_mmdc.h>
+ #include <netdev.h>
++#include <fsl_sec.h>
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+@@ -191,6 +192,10 @@ int board_init(void)
+ enable_layerscape_ns_access();
+ #endif
+
++#ifdef CONFIG_FSL_CAAM
++ sec_init();
++#endif
++
+ return 0;
+ }
+
+diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+new file mode 100644
+index 0000000..92a95a8
+--- /dev/null
++++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+@@ -0,0 +1,10 @@
++CONFIG_ARM=y
++CONFIG_TARGET_LS1012ARDB=y
++CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,SECURE_BOOT"
++# CONFIG_CMD_IMLS is not set
++CONFIG_SYS_NS16550=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
++CONFIG_OF_CONTROL=y
++CONFIG_DM=y
++CONFIG_SPI_FLASH=y
++CONFIG_DM_SPI=y
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index af3d33f..b40e02b 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -73,4 +73,6 @@
+ #define CONFIG_SYS_MEMTEST_START 0x80000000
+ #define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
++#define CONFIG_FSL_CAAM /* Enable CAAM */
++
+ #endif /* __LS1012ARDB_H__ */
+--
+1.7.9.5
+
--- /dev/null
+From d99349711fa42b3e401bf9a71e315440b8ed2c17 Mon Sep 17 00:00:00 2001
+From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Date: Tue, 10 May 2016 09:21:35 +0530
+Subject: [PATCH 26/93] fsl, qixis: conditionally compile IFC based qixis
+ functions
+
+Check if qixis supports memory-mapped read/write
+before compiling IFC based qixis read/write functions.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+---
+ board/freescale/common/qixis.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
+index 113295f..2e35d41 100644
+--- a/board/freescale/common/qixis.c
++++ b/board/freescale/common/qixis.c
+@@ -27,6 +27,7 @@ void qixis_write_i2c(unsigned int reg, u8 value)
+ }
+ #endif
+
++#ifdef QIXIS_BASE
+ u8 qixis_read(unsigned int reg)
+ {
+ void *p = (void *)QIXIS_BASE;
+@@ -40,6 +41,7 @@ void qixis_write(unsigned int reg, u8 value)
+
+ out_8(p + reg, value);
+ }
++#endif
+
+ u16 qixis_read_minor(void)
+ {
+--
+1.7.9.5
+
--- /dev/null
+From 34a472a20695cbd6ab1bc2d0686c6f324d8e0d6c Mon Sep 17 00:00:00 2001
+From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Date: Tue, 10 May 2016 09:38:46 +0530
+Subject: [PATCH 27/93] fsl, qixis: Add flag for LBMAP brdcfg reg offset
+
+Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP
+configuration register instead of hardcoding it in
+set_lbmap() function.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+---
+ board/freescale/common/qixis.c | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
+index 2e35d41..0db0ed6 100644
+--- a/board/freescale/common/qixis.c
++++ b/board/freescale/common/qixis.c
+@@ -14,6 +14,13 @@
+ #include <i2c.h>
+ #include "qixis.h"
+
++#ifndef QIXIS_LBMAP_BRDCFG_REG
++/*
++ * For consistency with existing platforms
++ */
++#define QIXIS_LBMAP_BRDCFG_REG 0x00
++#endif
++
+ #ifdef CONFIG_SYS_I2C_FPGA_ADDR
+ u8 qixis_read_i2c(unsigned int reg)
+ {
+@@ -144,9 +151,9 @@ static void __maybe_unused set_lbmap(int lbmap)
+ {
+ u8 reg;
+
+- reg = QIXIS_READ(brdcfg[0]);
++ reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
+ reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
+- QIXIS_WRITE(brdcfg[0], reg);
++ QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
+ }
+
+ static void __maybe_unused set_rcw_src(int rcw_src)
+--
+1.7.9.5
+
--- /dev/null
+From 4fcb1d5141ff6d9527ceac9f391e1da4128f5a60 Mon Sep 17 00:00:00 2001
+From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Date: Tue, 10 May 2016 09:54:36 +0530
+Subject: [PATCH 28/93] fsl, ls1012a, qixis: Add support for qixis subsystem
+
+Add support for the printing FPGA build information,
+altbank switching and board reset using qixis subsystem.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+---
+ board/freescale/ls1012aqds/ls1012aqds.c | 20 +++++++++++++++++++-
+ include/configs/ls1012aqds.h | 17 +++++++++++++++++
+ 2 files changed, 36 insertions(+), 1 deletion(-)
+
+diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
+index 5cb225f..446989b 100644
+--- a/board/freescale/ls1012aqds/ls1012aqds.c
++++ b/board/freescale/ls1012aqds/ls1012aqds.c
+@@ -44,8 +44,26 @@ static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+
+ int checkboard(void)
+ {
+- puts("Board: LS1012AQDS\n");
++ char buf[64];
++ u8 sw;
+
++ sw = QIXIS_READ(arch);
++ printf("Board Arch: V%d, ", sw >> 4);
++ printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
++
++ sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
++
++ if (sw & QIXIS_LBMAP_ALTBANK)
++ printf("flash: 2\n");
++ else
++ printf("flash: 1\n");
++
++ printf("FPGA: v%d (%s), build %d",
++ (int)QIXIS_READ(scver), qixis_read_tag(buf),
++ (int)qixis_read_minor());
++
++ /* the timestamp string contains "\n" at the end */
++ printf(" on %s", qixis_read_time(buf));
+ return 0;
+ }
+
+diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
+index 51ca902..de998b8 100644
+--- a/include/configs/ls1012aqds.h
++++ b/include/configs/ls1012aqds.h
+@@ -26,8 +26,25 @@
+ #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+ #endif
+
++/*
++ * QIXIS Definitions
++ */
++#define CONFIG_FSL_QIXIS
++
++#ifdef CONFIG_FSL_QIXIS
+ #define CONFIG_QIXIS_I2C_ACCESS
+ #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
++#define QIXIS_LBMAP_BRDCFG_REG 0x04
++#define QIXIS_LBMAP_SWITCH 6
++#define QIXIS_LBMAP_MASK 0xf7
++#define QIXIS_LBMAP_SHIFT 0
++#define QIXIS_LBMAP_DFLTBANK 0x00
++#define QIXIS_LBMAP_ALTBANK 0x08
++#define QIXIS_RST_CTL_RESET 0x41
++#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
++#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
++#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
++#endif
+
+ /*
+ * I2C bus multiplexer
+--
+1.7.9.5
+
--- /dev/null
+From 57700b94f9111578d0fc05bb8f273c0b29951572 Mon Sep 17 00:00:00 2001
+From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Date: Wed, 11 May 2016 14:59:39 +0530
+Subject: [PATCH 29/93] armv8: ls1012a: Added CSU assignment for USB2
+
+Access settings for USB2 IP is added through CSU register.
+
+Added CSU ID for USB2, reg: CSL23_REG[8:0]
+
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+---
+ .../include/asm/arch-fsl-layerscape/ns_access.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+index d6642a7..2fd33e1 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+@@ -38,6 +38,7 @@ enum csu_cslx_ind {
+ CSU_CSLX_ESDHC,
+ CSU_CSLX_IFC = 45,
+ CSU_CSLX_I2C1,
++ CSU_CSLX_USB_2,
+ CSU_CSLX_I2C3 = 48,
+ CSU_CSLX_I2C2,
+ CSU_CSLX_DUART2 = 50,
+@@ -117,6 +118,7 @@ static struct csu_ns_dev ns_dev[] = {
+ {CSU_CSLX_ESDHC, CSU_ALL_RW},
+ {CSU_CSLX_IFC, CSU_ALL_RW},
+ {CSU_CSLX_I2C1, CSU_ALL_RW},
++ {CSU_CSLX_USB_2, CSU_ALL_RW},
+ {CSU_CSLX_I2C3, CSU_ALL_RW},
+ {CSU_CSLX_I2C2, CSU_ALL_RW},
+ {CSU_CSLX_DUART2, CSU_ALL_RW},
+--
+1.7.9.5
+
--- /dev/null
+From 367c16da9255dacf6440f3c72c01c197cfb1bbe8 Mon Sep 17 00:00:00 2001
+From: Sumit Garg <sumit.garg@nxp.com>
+Date: Wed, 11 May 2016 12:44:35 -0400
+Subject: [PATCH 30/93] ARMv8: Enable CPUECTLR.SMPEN for data coherency
+
+Data coherency is enabled only when the CPUECTLR.SMPEN bit is set.
+The SMPEN bit should be set before enabling the data cache. If not
+enabled, the cache is not coherent with other cores and data
+corruption could occur. It also enables core level cache snooping.
+
+Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
+---
+ arch/arm/cpu/armv8/start.S | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
+index 235213f..9703f6b 100644
+--- a/arch/arm/cpu/armv8/start.S
++++ b/arch/arm/cpu/armv8/start.S
+@@ -70,6 +70,9 @@ reset:
+ mov x0, #3 << 20
+ msr cpacr_el1, x0 /* Enable FP/SIMD */
+ 0:
++ /* Enalbe SMPEN bit */
++ mov x0, #0x40
++ msr s3_1_c15_c2_1, x0
+
+ /* Apply ARM core specific erratas */
+ bl apply_core_errata
+--
+1.7.9.5
+
--- /dev/null
+From 6cfe5c5e7f6a4b3d46f65967fe10820ee2e3d2fa Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Fri, 13 May 2016 16:30:33 +0800
+Subject: [PATCH 31/93] mtd: sf: add exceed flash 16MB support for qspi
+
+spi/spi_flash.c: The flash S25FS512S cannot legacy commands
+such as Bank Address Related Command, So we need add the exceed
+16MB suuport. So we extend the cmd[] size to support 32-bit address,
+what's more, as to spi/fsl_qspi.c need to a flag to pionts the address
+mask, So add the magic num '0xaa' into cmd[].
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ arch/arm/dts/fsl-ls1012a.dtsi | 2 +-
+ drivers/mtd/spi/sf_internal.h | 7 ++++
+ drivers/mtd/spi/spi_flash.c | 73 ++++++++++++++++++++++++++++++--------
+ drivers/spi/fsl_qspi.c | 30 ++++++++++++++--
+ include/configs/ls1012a_common.h | 3 +-
+ 5 files changed, 95 insertions(+), 20 deletions(-)
+
+diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
+index 87a287a..2549c91 100644
+--- a/arch/arm/dts/fsl-ls1012a.dtsi
++++ b/arch/arm/dts/fsl-ls1012a.dtsi
+@@ -108,7 +108,7 @@
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x1550000 0x0 0x10000>,
+- <0x0 0x40000000 0x0 0x4000000>;
++ <0x0 0x40000000 0x0 0x8000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ num-cs = <2>;
+ big-endian;
+diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
+index c778b60..3c38425 100644
+--- a/drivers/mtd/spi/sf_internal.h
++++ b/drivers/mtd/spi/sf_internal.h
+@@ -57,6 +57,13 @@ enum spi_nor_option_flags {
+ #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
+ #define SPI_FLASH_16MB_BOUN 0x1000000
+
++#define SPI_FLASH_ADDR_MAGIC 0xaa
++#define SPI_FLASH_ADDR_MAGIC_LEN 1
++#define SPI_FLASH_4B_ADDR_LEN 4
++#define SPI_FLASH_CMD_LEN_EXT (1 + SPI_FLASH_4B_ADDR_LEN + \
++ SPI_FLASH_ADDR_MAGIC_LEN)
++#define SPI_FLASH_64MB_BOUN 0x4000000
++
+ /* CFI Manufacture ID's */
+ #define SPI_FLASH_CFI_MFR_SPANSION 0x01
+ #define SPI_FLASH_CFI_MFR_STMICRO 0x20
+diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
+index 97e53c7..9d61ac0 100644
+--- a/drivers/mtd/spi/spi_flash.c
++++ b/drivers/mtd/spi/spi_flash.c
+@@ -21,12 +21,20 @@
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+-static void spi_flash_addr(u32 addr, u8 *cmd)
++static void spi_flash_addr(u32 addr, u8 *cmd, u32 offset_ext)
+ {
+- /* cmd[0] is actual command */
+- cmd[1] = addr >> 16;
+- cmd[2] = addr >> 8;
+- cmd[3] = addr >> 0;
++ if (offset_ext >= SPI_FLASH_16MB_BOUN) {
++ /* cmd[0] is actual command */
++ cmd[1] = addr >> 24;
++ cmd[2] = addr >> 16;
++ cmd[3] = addr >> 8;
++ cmd[4] = addr >> 0;
++ cmd[5] = SPI_FLASH_ADDR_MAGIC;
++ } else {
++ cmd[1] = addr >> 16;
++ cmd[2] = addr >> 8;
++ cmd[3] = addr >> 0;
++ }
+ }
+
+ /* Read commands array */
+@@ -302,9 +310,11 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
+ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+ {
+ u32 erase_size, erase_addr;
+- u8 cmd[SPI_FLASH_CMD_LEN];
++ u8 *cmd, cmdsz;
+ int ret = -1;
++ u32 offset_ext;
+
++ offset_ext = offset;
+ erase_size = flash->erase_size;
+ if (offset % erase_size || len % erase_size) {
+ debug("SF: Erase offset/length not multiple of erase size\n");
+@@ -319,7 +329,18 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+ }
+ }
+
++ if (offset > SPI_FLASH_16MB_BOUN)
++ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
++ else
++ cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
++ cmd = calloc(1, cmdsz);
++ if (!cmd) {
++ debug("SF: Failed to allocate cmd\n");
++ return -ENOMEM;
++ }
++ memset(cmd, 0x0, cmdsz);
+ cmd[0] = flash->erase_cmd;
++
+ while (len) {
+ erase_addr = offset;
+
+@@ -332,7 +353,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+ if (ret < 0)
+ return ret;
+ #endif
+- spi_flash_addr(erase_addr, cmd);
++ spi_flash_addr(erase_addr, cmd, offset_ext);
+
+ debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
+ cmd[2], cmd[3], erase_addr);
+@@ -347,6 +368,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+ len -= erase_size;
+ }
+
++ free(cmd);
+ return ret;
+ }
+
+@@ -356,9 +378,11 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ unsigned long byte_addr, page_size;
+ u32 write_addr;
+ size_t chunk_len, actual;
+- u8 cmd[SPI_FLASH_CMD_LEN];
++ u8 *cmd, cmdsz;
+ int ret = -1;
++ u32 offset_ext;
+
++ offset_ext = offset;
+ page_size = flash->page_size;
+
+ if (flash->flash_is_locked) {
+@@ -369,6 +393,16 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ }
+ }
+
++ if (offset > SPI_FLASH_16MB_BOUN)
++ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
++ else
++ cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
++ cmd = calloc(1, cmdsz);
++ if (!cmd) {
++ debug("SF: Failed to allocate cmd\n");
++ return -ENOMEM;
++ }
++ memset(cmd, 0x0, cmdsz);
+ cmd[0] = flash->write_cmd;
+ for (actual = 0; actual < len; actual += chunk_len) {
+ write_addr = offset;
+@@ -389,7 +423,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ chunk_len = min(chunk_len,
+ (size_t)flash->spi->max_write_size);
+
+- spi_flash_addr(write_addr, cmd);
++ spi_flash_addr(write_addr, cmd, offset_ext);
+
+ debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
+ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+@@ -404,6 +438,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ offset += chunk_len;
+ }
+
++ free(cmd);
+ return ret;
+ }
+
+@@ -442,6 +477,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ u32 remain_len, read_len, read_addr;
+ int bank_sel = 0;
+ int ret = -1;
++ u32 offset_ext;
++
++ offset_ext = offset;
+
+ /* Handle memory-mapped SPI */
+ if (flash->memory_map) {
+@@ -456,15 +494,18 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ spi_release_bus(flash->spi);
+ return 0;
+ }
+-
+- cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
++ if (offset > SPI_FLASH_16MB_BOUN)
++ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
++ else
++ cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
+ cmd = calloc(1, cmdsz);
+ if (!cmd) {
+ debug("SF: Failed to allocate cmd\n");
+ return -ENOMEM;
+ }
+-
++ memset(cmd, 0x0, cmdsz);
+ cmd[0] = flash->read_cmd;
++
+ while (len) {
+ read_addr = offset;
+
+@@ -478,14 +519,18 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ return ret;
+ bank_sel = flash->bank_curr;
+ #endif
+- remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
++ if (offset_ext >= SPI_FLASH_16MB_BOUN) {
++ remain_len = flash->size - offset;
++ } else {
++ remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
+ (bank_sel + 1)) - offset;
++ }
+ if (len < remain_len)
+ read_len = len;
+ else
+ read_len = remain_len;
+
+- spi_flash_addr(read_addr, cmd);
++ spi_flash_addr(read_addr, cmd, offset_ext);
+
+ ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
+ if (ret < 0) {
+diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
+index 2b20038..09759fa 100644
+--- a/drivers/spi/fsl_qspi.c
++++ b/drivers/spi/fsl_qspi.c
+@@ -26,6 +26,9 @@ DECLARE_GLOBAL_DATA_PTR;
+ #endif
+
+ #define OFFSET_BITS_MASK GENMASK(23, 0)
++/* the qspi contrller memmap space ,instead of flash space */
++#define OFFSET_BITS_MASK_QSPI_SPACE GENMASK(27, 0)
++#define SPI_FLASH_ADDR_EXT_MAGIC 0xaa
+
+ #define FLASH_STATUS_WEL 0x02
+
+@@ -757,6 +760,13 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
+ u32 bytes = DIV_ROUND_UP(bitlen, 8);
+ static u32 wr_sfaddr;
+ u32 txbuf;
++ u8 offset_ext = 0;
++ u32 flash_offset;
++
++ if (((u8 *)dout)[5] == SPI_FLASH_ADDR_EXT_MAGIC) {
++ offset_ext = 1;
++ memcpy(&flash_offset, dout + 1, 4);
++ }
+
+ if (dout) {
+ if (flags & SPI_XFER_BEGIN) {
+@@ -772,14 +782,28 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
+
+ if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
+ priv->cur_seqid == QSPI_CMD_RDAR) {
+- priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
++ if (offset_ext)
++ priv->sf_addr = swab32(flash_offset) &
++ OFFSET_BITS_MASK_QSPI_SPACE;
++ else
++ priv->sf_addr = swab32(txbuf) &
++ OFFSET_BITS_MASK;
+ } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
+ (priv->cur_seqid == QSPI_CMD_BE_4K)) {
+- priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
++ if (offset_ext)
++ priv->sf_addr = swab32(flash_offset) &
++ OFFSET_BITS_MASK_QSPI_SPACE;
++ else
++ priv->sf_addr = swab32(txbuf) &
++ OFFSET_BITS_MASK;
+ qspi_op_erase(priv);
+ } else if (priv->cur_seqid == QSPI_CMD_PP ||
+ priv->cur_seqid == QSPI_CMD_WRAR) {
+- wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
++ if (offset_ext)
++ wr_sfaddr = swab32(flash_offset) &
++ OFFSET_BITS_MASK_QSPI_SPACE;
++ else
++ wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
+ } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
+ (priv->cur_seqid == QSPI_CMD_WREAR)) {
+ #ifdef CONFIG_SPI_FLASH_BAR
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 3fd360a..150444d 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -63,9 +63,8 @@
+ #define QSPI0_AMBA_BASE 0x40000000
+ #define CONFIG_SPI_FLASH_SPANSION
+ #define CONFIG_DM_SPI_FLASH
+-#define CONFIG_SPI_FLASH_BAR
+
+-#define FSL_QSPI_FLASH_SIZE (1 << 24)
++#define FSL_QSPI_FLASH_SIZE (1 << 26)
+ #define FSL_QSPI_FLASH_NUM 2
+
+ /*
+--
+1.7.9.5
+
--- /dev/null
+From c67f214546a9d8ac00b9b947c145f4c032def8e2 Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Mon, 16 May 2016 14:39:52 +0800
+Subject: [PATCH 32/93] driver: spi: fsl_qspi: enable AHB read for qspi
+
+If we don't enable the AHB read for ls1012a, input 'md 0x40000000',
+'md 0x41000000','md 0x42000000' address will be overlapped.
+After QSPI controller initialization for AHB, 'md 0x...' will access
+the whole QSPI flash address space.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ include/configs/ls1012a_common.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 150444d..121824c 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -66,6 +66,7 @@
+
+ #define FSL_QSPI_FLASH_SIZE (1 << 26)
+ #define FSL_QSPI_FLASH_NUM 2
++#define CONFIG_SYS_FSL_QSPI_AHB
+
+ /*
+ * Environment
+--
+1.7.9.5
+
--- /dev/null
+From 2daf451df50209e7626c2bf424d50ff23055784a Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Wed, 18 May 2016 10:52:38 +0800
+Subject: [PATCH 33/93] mmc: fsl_esdhc: support two esdhc host controllers
+
+This patch is to support two esdhc host controllers with
+the macro CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT.
+
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/mmc/fsl_esdhc.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
+index 7cc61a0..cacf879 100644
+--- a/drivers/mmc/fsl_esdhc.c
++++ b/drivers/mmc/fsl_esdhc.c
+@@ -748,11 +748,26 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
+ int fsl_esdhc_mmc_init(bd_t *bis)
+ {
+ struct fsl_esdhc_cfg *cfg;
++#ifdef CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
++ struct fsl_esdhc_cfg *cfg_1;
++#endif
+
+ cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
+ cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+ cfg->sdhc_clk = gd->arch.sdhc_clk;
++#ifdef CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
++ cfg_1 = calloc(sizeof(struct fsl_esdhc_cfg), 1);
++ cfg_1->esdhc_base = CONFIG_SYS_FSL_ESDHC_1_ADDR;
++ cfg_1->sdhc_clk = gd->arch.sdhc_clk;
++
++ if (fsl_esdhc_initialize(bis, cfg))
++ return -1;
++ if (fsl_esdhc_initialize(bis, cfg_1))
++ return -1;
++ return 0;
++#else
+ return fsl_esdhc_initialize(bis, cfg);
++#endif
+ }
+
+ #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+--
+1.7.9.5
+
--- /dev/null
+From e3e641993a1a5148e71bdd3f7b3cb5da695b1632 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Fri, 20 May 2016 11:17:30 +0800
+Subject: [PATCH 34/93] mmc: fsl_esdhc: add workaround for non-removable card
+ of esdhc-2
+
+The esdhc-2 usually uses some on-board memory devices such as eMMC
+card or SDIO wifi module, and it doesn't support SDHC_CD_B. So we
+could only assume it always has a card instead of detecting SDHC_CD_B
+status. This patch is to add workaround for these non-removable
+cards which are used by esdhc-2.
+
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/mmc/fsl_esdhc.c | 6 +++++-
+ include/fsl_esdhc.h | 1 +
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
+index cacf879..2c6e175 100644
+--- a/drivers/mmc/fsl_esdhc.c
++++ b/drivers/mmc/fsl_esdhc.c
+@@ -628,6 +628,8 @@ static int esdhc_getcd(struct mmc *mmc)
+ struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ int timeout = 1000;
+
++ if (cfg->non_removable_card)
++ return 1;
+ #ifdef CONFIG_ESDHC_DETECT_QUIRK
+ if (CONFIG_ESDHC_DETECT_QUIRK)
+ return 1;
+@@ -759,7 +761,9 @@ int fsl_esdhc_mmc_init(bd_t *bis)
+ cfg_1 = calloc(sizeof(struct fsl_esdhc_cfg), 1);
+ cfg_1->esdhc_base = CONFIG_SYS_FSL_ESDHC_1_ADDR;
+ cfg_1->sdhc_clk = gd->arch.sdhc_clk;
+-
++#ifdef CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
++ cfg_1->non_removable_card = true;
++#endif
+ if (fsl_esdhc_initialize(bis, cfg))
+ return -1;
+ if (fsl_esdhc_initialize(bis, cfg_1))
+diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
+index 073048f..8335106 100644
+--- a/include/fsl_esdhc.h
++++ b/include/fsl_esdhc.h
+@@ -175,6 +175,7 @@ struct fsl_esdhc_cfg {
+ #endif
+ u32 sdhc_clk;
+ u8 max_bus_width;
++ bool non_removable_card;
+ struct mmc_config cfg;
+ };
+
+--
+1.7.9.5
+
--- /dev/null
+From 7d3d85483a6c4085de5c016b86838681e97e6577 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Fri, 20 May 2016 11:31:17 +0800
+Subject: [PATCH 35/93] armv8: ls1012a: enable two esdhc host controllers
+ support
+
+LS1012A chip has two esdhc host controllers, and this patch
+is to enable two controllers support for it.
+
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
+ include/configs/ls1012a_common.h | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index 24add1a..6918757 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -19,6 +19,7 @@
+ #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
+ #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
+ #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
++#define CONFIG_SYS_FSL_ESDHC_1_ADDR (CONFIG_SYS_IMMR + 0x00580000)
+ #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
+ #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
+ #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 121824c..89d1370 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -94,6 +94,8 @@
+ #ifdef CONFIG_MMC
+ #define CONFIG_CMD_MMC
+ #define CONFIG_FSL_ESDHC
++#define CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
++#define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
+ #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_CMD_FAT
+--
+1.7.9.5
+
--- /dev/null
+From e70ae7f7ed00ecdbfa45fac3f342f1130df5029b Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Fri, 20 May 2016 16:37:34 +0800
+Subject: [PATCH 36/93] driver: spi: add exceed 16MB flash support
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi/spi_flash.c | 41 +++++++++++------------------------------
+ 1 file changed, 11 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
+index 9d61ac0..e9d1c64 100644
+--- a/drivers/mtd/spi/spi_flash.c
++++ b/drivers/mtd/spi/spi_flash.c
+@@ -21,9 +21,9 @@
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+-static void spi_flash_addr(u32 addr, u8 *cmd, u32 offset_ext)
++static void spi_flash_addr(u32 addr, u8 *cmd)
+ {
+- if (offset_ext >= SPI_FLASH_16MB_BOUN) {
++ if (addr >= SPI_FLASH_16MB_BOUN) {
+ /* cmd[0] is actual command */
+ cmd[1] = addr >> 24;
+ cmd[2] = addr >> 16;
+@@ -312,9 +312,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+ u32 erase_size, erase_addr;
+ u8 *cmd, cmdsz;
+ int ret = -1;
+- u32 offset_ext;
+
+- offset_ext = offset;
+ erase_size = flash->erase_size;
+ if (offset % erase_size || len % erase_size) {
+ debug("SF: Erase offset/length not multiple of erase size\n");
+@@ -329,10 +327,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+ }
+ }
+
+- if (offset > SPI_FLASH_16MB_BOUN)
+- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
+- else
+- cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
++ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
+ cmd = calloc(1, cmdsz);
+ if (!cmd) {
+ debug("SF: Failed to allocate cmd\n");
+@@ -353,7 +348,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+ if (ret < 0)
+ return ret;
+ #endif
+- spi_flash_addr(erase_addr, cmd, offset_ext);
++ spi_flash_addr(erase_addr, cmd);
+
+ debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
+ cmd[2], cmd[3], erase_addr);
+@@ -380,9 +375,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ size_t chunk_len, actual;
+ u8 *cmd, cmdsz;
+ int ret = -1;
+- u32 offset_ext;
+
+- offset_ext = offset;
+ page_size = flash->page_size;
+
+ if (flash->flash_is_locked) {
+@@ -393,10 +386,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ }
+ }
+
+- if (offset > SPI_FLASH_16MB_BOUN)
+- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
+- else
+- cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
++ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
+ cmd = calloc(1, cmdsz);
+ if (!cmd) {
+ debug("SF: Failed to allocate cmd\n");
+@@ -423,7 +413,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ chunk_len = min(chunk_len,
+ (size_t)flash->spi->max_write_size);
+
+- spi_flash_addr(write_addr, cmd, offset_ext);
++ spi_flash_addr(write_addr, cmd);
+
+ debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
+ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+@@ -477,9 +467,6 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ u32 remain_len, read_len, read_addr;
+ int bank_sel = 0;
+ int ret = -1;
+- u32 offset_ext;
+-
+- offset_ext = offset;
+
+ /* Handle memory-mapped SPI */
+ if (flash->memory_map) {
+@@ -494,10 +481,8 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ spi_release_bus(flash->spi);
+ return 0;
+ }
+- if (offset > SPI_FLASH_16MB_BOUN)
+- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
+- else
+- cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
++
++ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
+ cmd = calloc(1, cmdsz);
+ if (!cmd) {
+ debug("SF: Failed to allocate cmd\n");
+@@ -508,7 +493,6 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+
+ while (len) {
+ read_addr = offset;
+-
+ #ifdef CONFIG_SF_DUAL_FLASH
+ if (flash->dual_flash > SF_SINGLE_FLASH)
+ spi_flash_dual(flash, &read_addr);
+@@ -519,18 +503,15 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ return ret;
+ bank_sel = flash->bank_curr;
+ #endif
+- if (offset_ext >= SPI_FLASH_16MB_BOUN) {
+- remain_len = flash->size - offset;
+- } else {
+- remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
++ remain_len = ((flash->size << flash->shift) *
+ (bank_sel + 1)) - offset;
+- }
++
+ if (len < remain_len)
+ read_len = len;
+ else
+ read_len = remain_len;
+
+- spi_flash_addr(read_addr, cmd, offset_ext);
++ spi_flash_addr(read_addr, cmd);
+
+ ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
+ if (ret < 0) {
+--
+1.7.9.5
+
--- /dev/null
+From 65a6669afc667dacacf24a3a3f340205e38b0c5d Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Fri, 27 May 2016 10:25:09 +0800
+Subject: [PATCH 37/93] driver: spi: remove Warning prints for Spansion FS-S
+ fmaily
+
+The Spansion flash FS-S family don't support the bank related
+commands, Even if flash size exceed 16MB, we cannot enable the
+macro CONFIG_SPI_FLASH_BAR. Also, we need remove the irrelevant
+warnings:
+"puts("SF: Warning - Only lower 16MiB accessible,"
+"Full access #define CONFIG_SPI_FLASH_BAR"
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi/spi_flash.c | 13 +++++++++----
+ 1 file changed, 9 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
+index e9d1c64..b0f09ab 100644
+--- a/drivers/mtd/spi/spi_flash.c
++++ b/drivers/mtd/spi/spi_flash.c
+@@ -1009,6 +1009,9 @@ int spi_flash_scan(struct spi_flash *flash)
+ u8 idcode[5];
+ u8 cmd;
+ int ret;
++#ifdef CONFIG_SPI_FLASH_SPANSION
++ u8 id[6];
++#endif
+
+ /* Read the ID codes */
+ ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
+@@ -1062,7 +1065,6 @@ int spi_flash_scan(struct spi_flash *flash)
+ if ((jedec == 0x0219 || (jedec == 0x0220)) &&
+ (ext_jedec & 0xff00) == 0x4d00) {
+ int ret;
+- u8 id[6];
+
+ /* Read the ID codes again, 6 bytes */
+ ret = spi_flash_cmd(flash->spi, CMD_READ_ID, id, sizeof(id));
+@@ -1253,10 +1255,13 @@ int spi_flash_scan(struct spi_flash *flash)
+ #endif
+
+ #ifndef CONFIG_SPI_FLASH_BAR
+- if (((flash->dual_flash == SF_SINGLE_FLASH) &&
+- (flash->size > SPI_FLASH_16MB_BOUN)) ||
++ if ((id[5] != 0x81) &&
++ /*Spansion FS-S family not support BAR ,
++ Even if CONFIG_SPI_FLASH_BAR is unable, Need not the Warning prints */
++ ((((flash->dual_flash == SF_SINGLE_FLASH) &&
++ (flash->size > SPI_FLASH_16MB_BOUN))) ||
+ ((flash->dual_flash > SF_SINGLE_FLASH) &&
+- (flash->size > SPI_FLASH_16MB_BOUN << 1))) {
++ (flash->size > SPI_FLASH_16MB_BOUN << 1)))) {
+ puts("SF: Warning - Only lower 16MiB accessible,");
+ puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
+ }
+--
+1.7.9.5
+
--- /dev/null
+From 8f096adfd96941e596b5fbf30a21193e32f2c1b0 Mon Sep 17 00:00:00 2001
+From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Date: Fri, 27 May 2016 15:10:40 +0530
+Subject: [PATCH 38/93] Shift board specific configurations
+
+Board specific configurations are moved from
+ls1012a_common.h to ls1012aqds.h and ls1012ardb.h
+
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+---
+ include/configs/ls1012a_common.h | 60 --------------------------------------
+ include/configs/ls1012aqds.h | 58 ++++++++++++++++++++++++++++++++++++
+ include/configs/ls1012ardb.h | 58 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 116 insertions(+), 60 deletions(-)
+
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 89d1370..07ef7c6 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -88,66 +88,6 @@
+ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+ #endif /* CONFIG_EMU */
+
+-/* MMC */
+-#if !defined(CONFIG_EMU)
+-#define CONFIG_MMC
+-#ifdef CONFIG_MMC
+-#define CONFIG_CMD_MMC
+-#define CONFIG_FSL_ESDHC
+-#define CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
+-#define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
+-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+-#define CONFIG_GENERIC_MMC
+-#define CONFIG_CMD_FAT
+-#define CONFIG_DOS_PARTITION
+-#endif
+-#endif /* CONFIG_EMU */
+-
+-/* SATA */
+-#if !defined(CONFIG_EMU)
+-#define CONFIG_LIBATA
+-#define CONFIG_SCSI_AHCI
+-#define CONFIG_SCSI_AHCI_PLAT
+-#define CONFIG_CMD_SCSI
+-#define CONFIG_CMD_FAT
+-#define CONFIG_CMD_EXT2
+-#define CONFIG_DOS_PARTITION
+-#define CONFIG_BOARD_LATE_INIT
+-
+-#define CONFIG_SYS_SATA AHCI_BASE_ADDR
+-
+-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+-#define CONFIG_SYS_SCSI_MAX_LUN 1
+-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+- CONFIG_SYS_SCSI_MAX_LUN)
+-
+-#define CONFIG_PCI /* Enable PCI/PCIE */
+-#define CONFIG_PCIE1 /* PCIE controller 1 */
+-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+-#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+-
+-#define CONFIG_SYS_PCI_64BIT
+-
+-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
+-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
+-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
+-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
+-
+-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
+-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
+-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
+-
+-#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
+-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
+-#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
+-
+-#define CONFIG_NET_MULTI
+-#define CONFIG_PCI_PNP
+-#define CONFIG_E1000
+-#define CONFIG_PCI_SCAN_SHOW
+-#define CONFIG_CMD_PCI
+-#endif
+-
+ #define CONFIG_CONS_INDEX 1
+ #define CONFIG_SYS_NS16550_SERIAL
+ #define CONFIG_SYS_NS16550_REG_SIZE 1
+diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
+index de998b8..488811b 100644
+--- a/include/configs/ls1012aqds.h
++++ b/include/configs/ls1012aqds.h
+@@ -26,6 +26,64 @@
+ #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+ #endif
+
++/* MMC */
++#if !defined(CONFIG_EMU)
++#define CONFIG_MMC
++#ifdef CONFIG_MMC
++#define CONFIG_CMD_MMC
++#define CONFIG_FSL_ESDHC
++#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
++#define CONFIG_GENERIC_MMC
++#define CONFIG_CMD_FAT
++#define CONFIG_DOS_PARTITION
++#endif
++#endif /* CONFIG_EMU */
++
++/* SATA */
++#if !defined(CONFIG_EMU)
++#define CONFIG_LIBATA
++#define CONFIG_SCSI_AHCI
++#define CONFIG_SCSI_AHCI_PLAT
++#define CONFIG_CMD_SCSI
++#define CONFIG_CMD_FAT
++#define CONFIG_CMD_EXT2
++#define CONFIG_DOS_PARTITION
++#define CONFIG_BOARD_LATE_INIT
++
++#define CONFIG_SYS_SATA AHCI_BASE_ADDR
++
++#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
++#define CONFIG_SYS_SCSI_MAX_LUN 1
++#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
++ CONFIG_SYS_SCSI_MAX_LUN)
++
++#define CONFIG_PCI /* Enable PCI/PCIE */
++#define CONFIG_PCIE1 /* PCIE controller 1 */
++#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
++#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
++
++#define CONFIG_SYS_PCI_64BIT
++
++#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
++#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
++#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
++#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
++
++#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
++#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
++#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
++
++#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
++#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
++#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
++
++#define CONFIG_NET_MULTI
++#define CONFIG_PCI_PNP
++#define CONFIG_E1000
++#define CONFIG_PCI_SCAN_SHOW
++#define CONFIG_CMD_PCI
++#endif
++
+ /*
+ * QIXIS Definitions
+ */
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index b40e02b..1629e19 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -55,6 +55,64 @@
+ #define CONFIG_CMD_USB_MASS_STORAGE
+ #endif
+
++/* MMC */
++#if !defined(CONFIG_EMU)
++#define CONFIG_MMC
++#ifdef CONFIG_MMC
++#define CONFIG_CMD_MMC
++#define CONFIG_FSL_ESDHC
++#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
++#define CONFIG_GENERIC_MMC
++#define CONFIG_CMD_FAT
++#define CONFIG_DOS_PARTITION
++#endif
++#endif /* CONFIG_EMU */
++
++/* SATA */
++#if !defined(CONFIG_EMU)
++#define CONFIG_LIBATA
++#define CONFIG_SCSI_AHCI
++#define CONFIG_SCSI_AHCI_PLAT
++#define CONFIG_CMD_SCSI
++#define CONFIG_CMD_FAT
++#define CONFIG_CMD_EXT2
++#define CONFIG_DOS_PARTITION
++#define CONFIG_BOARD_LATE_INIT
++
++#define CONFIG_SYS_SATA AHCI_BASE_ADDR
++
++#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
++#define CONFIG_SYS_SCSI_MAX_LUN 1
++#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
++ CONFIG_SYS_SCSI_MAX_LUN)
++
++#define CONFIG_PCI /* Enable PCI/PCIE */
++#define CONFIG_PCIE1 /* PCIE controller 1 */
++#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
++#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
++
++#define CONFIG_SYS_PCI_64BIT
++
++#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
++#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
++#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
++#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
++
++#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
++#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
++#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
++
++#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
++#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
++#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
++
++#define CONFIG_NET_MULTI
++#define CONFIG_PCI_PNP
++#define CONFIG_E1000
++#define CONFIG_PCI_SCAN_SHOW
++#define CONFIG_CMD_PCI
++#endif
++
+ /*
+ * I2C IO expander
+ */
+--
+1.7.9.5
+
--- /dev/null
+From 6aaa5973b9ae8452a546e0666b2389bb163fb949 Mon Sep 17 00:00:00 2001
+From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Date: Thu, 19 May 2016 16:45:27 +0530
+Subject: [PATCH 39/93] armv8: ls1012a: Add support of ls1012afrdm board
+
+QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012AFRDM board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+---
+ arch/arm/Kconfig | 10 ++
+ arch/arm/dts/Makefile | 3 +-
+ arch/arm/dts/fsl-ls1012a-frdm.dts | 16 +++
+ arch/arm/dts/fsl-ls1012a-frdm.dtsi | 39 ++++++
+ board/freescale/ls1012afrdm/Kconfig | 15 +++
+ board/freescale/ls1012afrdm/MAINTAINERS | 6 +
+ board/freescale/ls1012afrdm/Makefile | 7 ++
+ board/freescale/ls1012afrdm/README | 94 +++++++++++++++
+ board/freescale/ls1012afrdm/ls1012afrdm.c | 183 +++++++++++++++++++++++++++++
+ configs/ls1012afrdm_qspi_defconfig | 10 ++
+ include/configs/ls1012afrdm.h | 59 ++++++++++
+ 11 files changed, 441 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dts
+ create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dtsi
+ create mode 100644 board/freescale/ls1012afrdm/Kconfig
+ create mode 100644 board/freescale/ls1012afrdm/MAINTAINERS
+ create mode 100644 board/freescale/ls1012afrdm/Makefile
+ create mode 100644 board/freescale/ls1012afrdm/README
+ create mode 100644 board/freescale/ls1012afrdm/ls1012afrdm.c
+ create mode 100644 configs/ls1012afrdm_qspi_defconfig
+ create mode 100644 include/configs/ls1012afrdm.h
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index b536684..23fce38 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -669,6 +669,15 @@ config TARGET_LS1012ARDB
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
++config TARGET_LS1012AFRDM
++ bool "Support ls1012afrdm"
++ select ARM64
++ help
++ Support for Freescale LS1012AFRDM platform.
++ The LS1012A Freedom board (FRDM) is a high-performance
++ development platform that supports the QorIQ LS1012A
++ Layerscape Architecture processor.
++
+ config TARGET_LS1021AQDS
+ bool "Support ls1021aqds"
+ select CPU_V7
+@@ -816,6 +825,7 @@ source "board/freescale/ls1021atwr/Kconfig"
+ source "board/freescale/ls1043ardb/Kconfig"
+ source "board/freescale/ls1012aqds/Kconfig"
+ source "board/freescale/ls1012ardb/Kconfig"
++source "board/freescale/ls1012afrdm/Kconfig"
+ source "board/freescale/mx23evk/Kconfig"
+ source "board/freescale/mx25pdk/Kconfig"
+ source "board/freescale/mx28evk/Kconfig"
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 9e8137b..de023b4 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -96,7 +96,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
+ fsl-ls1043a-qds-lpuart.dtb \
+ fsl-ls1043a-rdb.dtb \
+ fsl-ls1012a-qds.dtb \
+- fsl-ls1012a-rdb.dtb
++ fsl-ls1012a-rdb.dtb \
++ fsl-ls1012a-frdm.dtb
+
+ dtb-$(CONFIG_MACH_SUN4I) += \
+ sun4i-a10-a1000.dtb \
+diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dts b/arch/arm/dts/fsl-ls1012a-frdm.dts
+new file mode 100644
+index 0000000..3a06c0a
+--- /dev/null
++++ b/arch/arm/dts/fsl-ls1012a-frdm.dts
+@@ -0,0 +1,16 @@
++/*
++ * Device Tree file for Freescale Layerscape-1012A family SoC.
++ *
++ * Copyright (C) 2016, Freescale Semiconductor
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++/dts-v1/;
++#include "fsl-ls1012a-frdm.dtsi"
++
++/ {
++ chosen {
++ stdout-path = &duart0;
++ };
++};
+diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
+new file mode 100644
+index 0000000..9f0db91
+--- /dev/null
++++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
+@@ -0,0 +1,39 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
++ *
++ * Copyright (C) 2016, Freescale Semiconductor
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++/include/ "fsl-ls1012a.dtsi"
++
++/ {
++ model = "LS1012A FREEDOM Board";
++ aliases {
++ spi0 = &qspi;
++ };
++};
++
++&qspi {
++ bus-num = <0>;
++ status = "okay";
++
++ qflash0: s25fl128s@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "spi-flash";
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++ };
++};
++
++&i2c0 {
++ status = "okay";
++};
++
++&duart0 {
++ status = "okay";
++};
+diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
+new file mode 100644
+index 0000000..a34521c
+--- /dev/null
++++ b/board/freescale/ls1012afrdm/Kconfig
+@@ -0,0 +1,15 @@
++if TARGET_LS1012AFRDM
++
++config SYS_BOARD
++ default "ls1012afrdm"
++
++config SYS_VENDOR
++ default "freescale"
++
++config SYS_SOC
++ default "fsl-layerscape"
++
++config SYS_CONFIG_NAME
++ default "ls1012afrdm"
++
++endif
+diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
+new file mode 100644
+index 0000000..2f31d0f
+--- /dev/null
++++ b/board/freescale/ls1012afrdm/MAINTAINERS
+@@ -0,0 +1,6 @@
++LS1012AFRDM BOARD
++M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
++S: Maintained
++F: board/freescale/ls1012afrdm/
++F: include/configs/ls1012afrdm.h
++F: configs/ls1012afrdm_defconfig
+diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
+new file mode 100644
+index 0000000..dbfa2ce
+--- /dev/null
++++ b/board/freescale/ls1012afrdm/Makefile
+@@ -0,0 +1,7 @@
++#
++# Copyright 2016 Freescale Semiconductor, Inc.
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y += ls1012afrdm.o
+diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README
+new file mode 100644
+index 0000000..0aadbb1
+--- /dev/null
++++ b/board/freescale/ls1012afrdm/README
+@@ -0,0 +1,94 @@
++Overview
++--------
++The LS1012AFRDM power supplies (PS) provide all the voltages necessary
++for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
++and other onboard peripherals.
++
++LS1012A SoC Overview
++--------------------
++The LS1012A features an advanced 64-bit ARM v8 Cortex-
++A53 processor, with 32 KB of parity protected L1-I cache,
++32 KB of ECC protected L1-D cache, as well as 256 KB of
++ECC protected L2 cache.
++
++The LS1012A SoC includes the following function and features:
++ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
++ - ARM v8 cryptography extensions
++ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
++ 16-/8-bit operation (no ECC support)
++ - ARM core-link CCI-400 cache coherent interconnect
++ - Packet Forwarding Engine (PFE)
++ - Cryptography acceleration (SEC)
++ - Ethernet interfaces supported by PFE:
++ - One Configurable x3 SerDes:
++ Two Serdes PLLs supported for usage by any SerDes data lane
++ Support for up to 6 GBaud operation
++ - High-speed peripheral interfaces:
++ - One PCI Express Gen2 controller, supporting x1 operation
++ - One serial ATA (SATA Gen 3.0) controller
++ - One USB 3.0/2.0 controller with integrated PHY
++ - One USB 2.0 controller with ULPI interface. .
++ - Additional peripheral interfaces:
++ - One quad serial peripheral interface (QuadSPI) controller
++ - One serial peripheral interface (SPI) controller
++ - Two enhanced secure digital host controllers
++ - Two I2C controllers
++ - One 16550 compliant DUART (two UART interfaces)
++ - Two general purpose IOs (GPIO)
++ - Two FlexTimers
++ - Five synchronous audio interfaces (SAI)
++ - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
++ - Single-source clocking solution enabling generation of core, platform,
++ DDR, SerDes, and USB clocks from a single external crystal and internal
++ crystaloscillator
++ - Thermal monitor unit (TMU) with +/- 3C accuracy
++ - Two WatchDog timers
++ - ARM generic timer
++ - QorIQ platform's trust architecture 2.1
++
++ LS1012AFRDM board Overview
++ -----------------------
++ - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
++ - 2 SGMII 1G PHYs
++ - DDR Controller
++ - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
++ operating at 1.35 V
++ - QSPI
++ - Onboard 512 Mbit QSPI flash memory running at speed up
++ to 108/54 MHz
++ - One high-speed USB 2.0/3.0 port, one USB 2.0 port
++ - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
++ Micro-AB connector.
++ - USB 2.0 port is a debug port (CMSIS DAP) and is configured
++ as a Micro-AB device.
++ - I2C controller
++ - One I2C bus with connectivity to Arduino headers
++ - UART
++ - UART (Console): UART1 (Without flow control) for console
++ - ARM JTAG support
++ - ARM Cortex® 10-pin JTAG connector for LS1012A
++ - CMSIS DAP through K20 microcontroller
++ - SAI Audio interface
++ - One SAI port, SAI 2 with full duplex support
++ - Clocks
++ - 25 MHz crystal for LS1012A
++ - 8 MHz Crystal for K20
++ - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
++ - Power Supplies
++ - 5 V input supply from USB
++ - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
++ other board interfaces
++
++Booting Options
++---------------
++a) QSPI Flash 1
++
++QSPI flash map
++--------------
++Images | Size |QSPI Flash Address
++------------------------------------------
++RCW + PBI | 1MB | 0x4000_0000
++U-boot | 1MB | 0x4010_0000
++U-boot Env | 1MB | 0x4020_0000
++PPA FIT image | 2MB | 0x4050_0000
++Linux ITB | ~53MB | 0x40A0_0000
+diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
+new file mode 100644
+index 0000000..6be8951
+--- /dev/null
++++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
+@@ -0,0 +1,183 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <i2c.h>
++#include <asm/io.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/fsl_serdes.h>
++#include <asm/arch/ppa.h>
++#include <asm/arch/soc.h>
++#include <hwconfig.h>
++#include <ahci.h>
++#include <mmc.h>
++#include <scsi.h>
++#include <fsl_csu.h>
++#include <fsl_esdhc.h>
++#include <environment.h>
++#include <fsl_mmdc.h>
++#include <netdev.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
++{
++ int timeout = 1000;
++
++ out_be32(ptr, value);
++
++ while (in_be32(ptr) & bits) {
++ udelay(100);
++ timeout--;
++ }
++ if (timeout <= 0)
++ puts("Error: wait for clear timeout.\n");
++}
++
++int checkboard(void)
++{
++ puts("Board: LS1012AFRDM ");
++
++ return 0;
++}
++
++void mmdc_init(void)
++{
++ struct mmdc_p_regs *mmdc =
++ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
++
++ /* Set MMDC_MDSCR[CON_REQ] */
++ out_be32(&mmdc->mdscr, 0x00008000);
++
++ /* configure timing parms */
++ out_be32(&mmdc->mdotc, 0x12554000);
++ out_be32(&mmdc->mdcfg0, 0xbabf7954);
++ out_be32(&mmdc->mdcfg1, 0xff328f64);
++ out_be32(&mmdc->mdcfg2, 0x01ff00db);
++
++ /* other parms */
++ out_be32(&mmdc->mdmisc, 0x00000680);
++ out_be32(&mmdc->mpmur0, 0x00000800);
++ out_be32(&mmdc->mdrwd, 0x00002000);
++ out_be32(&mmdc->mpodtctrl, 0x0000022a);
++
++ /* out of reset delays */
++ out_be32(&mmdc->mdor, 0x00bf1023);
++
++ /* physical parms */
++ out_be32(&mmdc->mdctl, 0x04180000);
++ out_be32(&mmdc->mdasp, 0x0000007f);
++
++ /* Enable MMDC */
++ out_be32(&mmdc->mdctl, 0x84180000);
++
++ /* dram init sequence: update MRs */
++ out_be32(&mmdc->mdscr, 0x00088032);
++ out_be32(&mmdc->mdscr, 0x00008033);
++ out_be32(&mmdc->mdscr, 0x00048031);
++ out_be32(&mmdc->mdscr, 0x19308030);
++
++ /* dram init sequence: ZQCL */
++ out_be32(&mmdc->mdscr, 0x04008040);
++ set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
++
++ /* Calibrations now: wr lvl */
++ out_be32(&mmdc->mdscr, 0x00848031);
++ out_be32(&mmdc->mdscr, 0x00008200);
++ set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
++
++ mdelay(1);
++
++ out_be32(&mmdc->mdscr, 0x00048031);
++ out_be32(&mmdc->mdscr, 0x00008000);
++
++ mdelay(1);
++
++ /* Calibrations now: Read DQS gating calibration */
++ out_be32(&mmdc->mdscr, 0x04008050);
++ out_be32(&mmdc->mdscr, 0x00048033);
++ out_be32(&mmdc->mppdcmpr2, 0x00000001);
++ out_be32(&mmdc->mprddlctl, 0x40404040);
++ set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
++
++ out_be32(&mmdc->mdscr, 0x00008033);
++
++ /* Calibrations now: Read calibration */
++ out_be32(&mmdc->mdscr, 0x04008050);
++ out_be32(&mmdc->mdscr, 0x00048033);
++ out_be32(&mmdc->mppdcmpr2, 0x00000001);
++ set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
++
++ out_be32(&mmdc->mdscr, 0x00008033);
++
++ /* PD, SR */
++ out_be32(&mmdc->mdpdc, 0x00030035);
++ out_be32(&mmdc->mapsr, 0x00001067);
++
++ /* refresh scheme */
++ set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
++
++ /* disable CON_REQ */
++ out_be32(&mmdc->mdscr, 0x0);
++}
++
++int dram_init(void)
++{
++ mmdc_init();
++
++ gd->ram_size = 0x20000000;
++
++ return 0;
++}
++
++int board_eth_init(bd_t *bis)
++{
++ return pci_eth_init(bis);
++}
++
++int board_early_init_f(void)
++{
++ fsl_lsch2_early_init_f();
++
++ return 0;
++}
++
++int board_init(void)
++{
++ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
++ /*
++ * Set CCI-400 control override register to enable barrier
++ * transaction
++ */
++ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
++
++#ifdef CONFIG_ENV_IS_NOWHERE
++ gd->env_addr = (ulong)&default_environment[0];
++#endif
++
++#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
++ enable_layerscape_ns_access();
++#endif
++
++ return 0;
++}
++
++int ft_board_setup(void *blob, bd_t *bd)
++{
++ u64 base[CONFIG_NR_DRAM_BANKS];
++ u64 size[CONFIG_NR_DRAM_BANKS];
++
++ /* fixup DT for the two DDR banks */
++ base[0] = gd->bd->bi_dram[0].start;
++ size[0] = gd->bd->bi_dram[0].size;
++ base[1] = gd->bd->bi_dram[1].start;
++ size[1] = gd->bd->bi_dram[1].size;
++
++ fdt_fixup_memory_banks(blob, base, size, 2);
++ ft_cpu_setup(blob, bd);
++
++ return 0;
++}
+diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
+new file mode 100644
+index 0000000..e27181c
+--- /dev/null
++++ b/configs/ls1012afrdm_qspi_defconfig
+@@ -0,0 +1,10 @@
++CONFIG_ARM=y
++CONFIG_TARGET_LS1012AFRDM=y
++CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
++# CONFIG_CMD_IMLS is not set
++CONFIG_SYS_NS16550=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
++CONFIG_OF_CONTROL=y
++CONFIG_DM=y
++CONFIG_SPI_FLASH=y
++CONFIG_DM_SPI=y
+diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
+new file mode 100644
+index 0000000..3231ab7
+--- /dev/null
++++ b/include/configs/ls1012afrdm.h
+@@ -0,0 +1,59 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __LS1012ARDB_H__
++#define __LS1012ARDB_H__
++
++#include "ls1012a_common.h"
++
++#define CONFIG_DIMM_SLOTS_PER_CTLR 1
++#define CONFIG_CHIP_SELECTS_PER_CTRL 1
++#define CONFIG_NR_DRAM_BANKS 2
++
++#define CONFIG_CMD_MEMINFO
++#define CONFIG_CMD_MEMTEST
++#define CONFIG_SYS_MEMTEST_START 0x80000000
++#define CONFIG_SYS_MEMTEST_END 0x9fffffff
++
++#define CONFIG_PHYLIB
++#define CONFIG_PHY_REALTEK
++/*
++* USB
++*/
++#define CONFIG_HAS_FSL_XHCI_USB
++
++#ifdef CONFIG_HAS_FSL_XHCI_USB
++#define CONFIG_USB_XHCI
++#define CONFIG_USB_XHCI_FSL
++#define CONFIG_USB_XHCI_DWC3
++#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
++#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
++#define CONFIG_CMD_USB
++#define CONFIG_USB_STORAGE
++#define CONFIG_CMD_EXT2
++
++#define CONFIG_USB_DWC3
++#define CONFIG_USB_DWC3_GADGET
++
++#define CONFIG_USB_GADGET
++#define CONFIG_USB_FUNCTION_MASS_STORAGE
++#define CONFIG_USB_GADGET_DOWNLOAD
++#define CONFIG_USB_GADGET_VBUS_DRAW 2
++#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
++#define CONFIG_G_DNL_VENDOR_NUM 0x1234
++#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
++#define CONFIG_USB_GADGET_DUALSPEED
++
++/* USB Gadget ums command */
++#define CONFIG_CMD_USB_MASS_STORAGE
++#endif
++
++#define CONFIG_CMD_MEMINFO
++#define CONFIG_CMD_MEMTEST
++#define CONFIG_SYS_MEMTEST_START 0x80000000
++#define CONFIG_SYS_MEMTEST_END 0x9fffffff
++
++#endif /* __LS1012ARDB_H__ */
+--
+1.7.9.5
+
--- /dev/null
+From 0bfcfaafa23af0e8c9ae9df3236831fcaaa597b8 Mon Sep 17 00:00:00 2001
+From: Anji J <anji.jagarlmudi@freescale.com>
+Date: Mon, 4 Apr 2016 15:07:47 +0530
+Subject: [PATCH 40/93] DNCPE-138 CSU config for PFE
+
+Configure PFE for NS access.
+
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ .../include/asm/arch-fsl-layerscape/ns_access.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+index 2fd33e1..5250ac7 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+@@ -25,6 +25,7 @@ enum csu_cslx_ind {
+ CSU_CSLX_PCIE3_IO,
+ CSU_CSLX_USB3 = 20,
+ CSU_CSLX_USB2,
++ CSU_CSLX_PFE = 23,
+ CSU_CSLX_SERDES = 32,
+ CSU_CSLX_QDMA,
+ CSU_CSLX_LPUART2,
+@@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = {
+ {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
+ {CSU_CSLX_USB3, CSU_ALL_RW},
+ {CSU_CSLX_USB2, CSU_ALL_RW},
++ {CSU_CSLX_PFE, CSU_ALL_RW},
+ {CSU_CSLX_SERDES, CSU_ALL_RW},
+ {CSU_CSLX_QDMA, CSU_ALL_RW},
+ {CSU_CSLX_LPUART2, CSU_ALL_RW},
+--
+1.7.9.5
+
--- /dev/null
+From 487b9b2e5c767ee2110cce57539f0ebeb5a74872 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Tue, 24 May 2016 14:05:18 +0530
+Subject: [PATCH 41/93] DNCPE-4: LS1012A PPFE driver
+
+[context adjustment]
+
+- Ported PFE driver from LS1024
+- Did changes for GEMAC/MDIO/PHY
+- LS1012A address translation changes
+- Added pfe command to the U-boot.
+- Added gemac_stat command
+- Added config PFE_START to conditionally start pfe on bootup time.
+- Change Rx packet ack model
+- Class firmware changes to ignore Rx error status
+
+- SCFG changes for pfe
+- Configure CCI-400 QoS settings
+- Configure transaction attributes
+- Configure RGMII port config
+
+Testing status on board
+
+RGMII - Works fine, can download file through tftp.
+SGMII - CRC errors are seen, but basic rx/tx works.
+
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 +
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 42 +-
+ board/freescale/ls1012aqds/Makefile | 1 +
+ board/freescale/ls1012aqds/eth.c | 199 +++
+ board/freescale/ls1012aqds/ls1012aqds.c | 5 -
+ board/freescale/ls1012aqds/ls1012aqds.h | 149 ++
+ board/freescale/ls1012aqds/ls1012aqds_qixis.h | 2 +-
+ board/freescale/ls1012ardb/Makefile | 1 +
+ board/freescale/ls1012ardb/eth.c | 68 +
+ board/freescale/ls1012ardb/ls1012ardb.c | 4 -
+ common/Makefile | 2 +
+ common/cmd_gemac_stat.c | 147 ++
+ common/cmd_pfe_commands.c | 983 ++++++++++++
+ drivers/net/Makefile | 1 +
+ drivers/net/pfe_eth/Makefile | 1 +
+ drivers/net/pfe_eth/class_sbl_elf.fw | 1 +
+ drivers/net/pfe_eth/hal.h | 64 +
+ drivers/net/pfe_eth/pfe.c | 1677 ++++++++++++++++++++
+ drivers/net/pfe_eth/pfe/cbus.h | 74 +
+ drivers/net/pfe_eth/pfe/cbus/bmu.h | 37 +
+ drivers/net/pfe_eth/pfe/cbus/class_csr.h | 206 +++
+ drivers/net/pfe_eth/pfe/cbus/emac.h | 232 +++
+ drivers/net/pfe_eth/pfe/cbus/gpi.h | 60 +
+ drivers/net/pfe_eth/pfe/cbus/gpt.h | 11 +
+ drivers/net/pfe_eth/pfe/cbus/hif.h | 62 +
+ drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h | 33 +
+ drivers/net/pfe_eth/pfe/cbus/tmu_csr.h | 102 ++
+ drivers/net/pfe_eth/pfe/cbus/util_csr.h | 43 +
+ drivers/net/pfe_eth/pfe/class.h | 142 ++
+ drivers/net/pfe_eth/pfe/class/ccu.h | 10 +
+ drivers/net/pfe_eth/pfe/class/efet.h | 21 +
+ drivers/net/pfe_eth/pfe/class/mac_hash.h | 28 +
+ drivers/net/pfe_eth/pfe/class/perg.h | 21 +
+ drivers/net/pfe_eth/pfe/class/vlan_hash.h | 28 +
+ drivers/net/pfe_eth/pfe/gpt.h | 11 +
+ drivers/net/pfe_eth/pfe/pe.h | 147 ++
+ drivers/net/pfe_eth/pfe/pfe.h | 250 +++
+ drivers/net/pfe_eth/pfe/tmu.h | 48 +
+ drivers/net/pfe_eth/pfe/tmu/phy_queue.h | 31 +
+ drivers/net/pfe_eth/pfe/tmu/sched.h | 47 +
+ drivers/net/pfe_eth/pfe/tmu/shaper.h | 19 +
+ drivers/net/pfe_eth/pfe/uart.h | 13 +
+ drivers/net/pfe_eth/pfe/util.h | 30 +
+ drivers/net/pfe_eth/pfe/util/eape.h | 10 +
+ drivers/net/pfe_eth/pfe/util/efet.h | 20 +
+ drivers/net/pfe_eth/pfe/util/inq.h | 10 +
+ drivers/net/pfe_eth/pfe_driver.c | 710 +++++++++
+ drivers/net/pfe_eth/pfe_driver.h | 141 ++
+ drivers/net/pfe_eth/pfe_eth.c | 521 ++++++
+ drivers/net/pfe_eth/pfe_eth.h | 161 ++
+ drivers/net/pfe_eth/pfe_firmware.c | 193 +++
+ drivers/net/pfe_eth/pfe_firmware.h | 20 +
+ drivers/net/pfe_eth/pfe_mod.h | 140 ++
+ drivers/net/pfe_eth/tmu_sbl_elf.fw | 1 +
+ drivers/net/pfe_eth/util_sbl_elf.fw | 1 +
+ include/configs/ls1012a_common.h | 10 +
+ include/configs/ls1012aqds.h | 13 +-
+ include/configs/ls1012ardb.h | 6 +-
+ 58 files changed, 6994 insertions(+), 21 deletions(-)
+ create mode 100644 board/freescale/ls1012aqds/eth.c
+ create mode 100644 board/freescale/ls1012aqds/ls1012aqds.h
+ create mode 100644 board/freescale/ls1012ardb/eth.c
+ create mode 100644 common/cmd_gemac_stat.c
+ create mode 100644 common/cmd_pfe_commands.c
+ create mode 100644 drivers/net/pfe_eth/Makefile
+ create mode 100644 drivers/net/pfe_eth/class_sbl_elf.fw
+ create mode 100644 drivers/net/pfe_eth/hal.h
+ create mode 100644 drivers/net/pfe_eth/pfe.c
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/bmu.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/class_csr.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/emac.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/gpi.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/gpt.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/hif.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
+ create mode 100644 drivers/net/pfe_eth/pfe/cbus/util_csr.h
+ create mode 100644 drivers/net/pfe_eth/pfe/class.h
+ create mode 100644 drivers/net/pfe_eth/pfe/class/ccu.h
+ create mode 100644 drivers/net/pfe_eth/pfe/class/efet.h
+ create mode 100644 drivers/net/pfe_eth/pfe/class/mac_hash.h
+ create mode 100644 drivers/net/pfe_eth/pfe/class/perg.h
+ create mode 100644 drivers/net/pfe_eth/pfe/class/vlan_hash.h
+ create mode 100644 drivers/net/pfe_eth/pfe/gpt.h
+ create mode 100644 drivers/net/pfe_eth/pfe/pe.h
+ create mode 100644 drivers/net/pfe_eth/pfe/pfe.h
+ create mode 100644 drivers/net/pfe_eth/pfe/tmu.h
+ create mode 100644 drivers/net/pfe_eth/pfe/tmu/phy_queue.h
+ create mode 100644 drivers/net/pfe_eth/pfe/tmu/sched.h
+ create mode 100644 drivers/net/pfe_eth/pfe/tmu/shaper.h
+ create mode 100644 drivers/net/pfe_eth/pfe/uart.h
+ create mode 100644 drivers/net/pfe_eth/pfe/util.h
+ create mode 100644 drivers/net/pfe_eth/pfe/util/eape.h
+ create mode 100644 drivers/net/pfe_eth/pfe/util/efet.h
+ create mode 100644 drivers/net/pfe_eth/pfe/util/inq.h
+ create mode 100644 drivers/net/pfe_eth/pfe_driver.c
+ create mode 100644 drivers/net/pfe_eth/pfe_driver.h
+ create mode 100644 drivers/net/pfe_eth/pfe_eth.c
+ create mode 100644 drivers/net/pfe_eth/pfe_eth.h
+ create mode 100644 drivers/net/pfe_eth/pfe_firmware.c
+ create mode 100644 drivers/net/pfe_eth/pfe_firmware.h
+ create mode 100644 drivers/net/pfe_eth/pfe_mod.h
+ create mode 100644 drivers/net/pfe_eth/tmu_sbl_elf.fw
+ create mode 100644 drivers/net/pfe_eth/util_sbl_elf.fw
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+index 340d9f9..8f59577 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+@@ -573,6 +573,11 @@ int cpu_eth_init(bd_t *bis)
+ {
+ int error = 0;
+
++#if defined(CONFIG_FSL_PPFE) && !defined(CONFIG_CMD_PFE_START)
++ ls1012a_gemac_initialize(bis, 0 , "pfe_eth0");
++ ls1012a_gemac_initialize(bis, 1 , "pfe_eth1");
++#endif
++
+ #ifdef CONFIG_FSL_MC_ENET
+ error = fsl_mc_ldpaa_init(bis);
+ #endif
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index 6918757..a264f9a 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -41,6 +41,7 @@
+ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
+ #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
+ #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
++#define CONFIG_SYS_PPFE_ADDR (CONFIG_SYS_IMMR + 0x3000000)
+ #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
+ #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
+
+@@ -364,6 +365,24 @@ struct ccsr_gur {
+ #define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000
+ #define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000
+
++/* RGMIIPCR bit definitions*/
++#define SCFG_RGMIIPCR_EN_AUTO (0x00000008)
++#define SCFG_RGMIIPCR_SETSP_1000M (0x00000004)
++#define SCFG_RGMIIPCR_SETSP_100M (0x00000000)
++#define SCFG_RGMIIPCR_SETSP_10M (0x00000002)
++#define SCFG_RGMIIPCR_SETFD (0x00000001)
++
++/*PFEASBCR bit definitions */
++#define SCFG_PPFEASBCR_ARCACHE0 (0x80000000)
++#define SCFG_PPFEASBCR_AWCACHE0 (0x40000000)
++#define SCFG_PPFEASBCR_ARCACHE1 (0x20000000)
++#define SCFG_PPFEASBCR_AWCACHE1 (0x10000000)
++#define SCFG_PPFEASBCR_ARSNP (0x08000000)
++#define SCFG_PPFEASBCR_AWSNP (0x04000000)
++
++
++
++
+ /* Supplemental Configuration Unit */
+ struct ccsr_scfg {
+ u8 res_000[0x100-0x000];
+@@ -381,7 +400,12 @@ struct ccsr_scfg {
+ u8 res_140[0x158-0x140];
+ u32 altcbar;
+ u32 qspi_cfg;
+- u8 res_160[0x180-0x160];
++ u8 res_160[0x164-0x160];
++ u32 wr_qos1;
++ u32 wr_qos2;
++ u32 rd_qos1;
++ u32 rd_qos2;
++ u8 res_174[0x180-0x174];
+ u32 dmamcr;
+ u8 res_184[0x18c-0x184];
+ u32 debug_icid;
+@@ -411,7 +435,21 @@ struct ccsr_scfg {
+ u32 usb_refclk_selcr1;
+ u32 usb_refclk_selcr2;
+ u32 usb_refclk_selcr3;
+- u8 res_424[0x600-0x424];
++ u8 res_424[0x434-0x424];
++ u32 rgmiipcr;
++ u32 res_438;
++ u32 rgmiipsr;
++ u32 pfepfcssr1;
++ u32 pfeintencr1;
++ u32 pfepfcssr2;
++ u32 pfeintencr2;
++ u32 pfeerrcr;
++ u32 pfeeerrintencr;
++ u32 pfeasbcr;
++ u32 pfebsbcr;
++ u8 res_460[0x484-0x460];
++ u32 mdioselcr;
++ u8 res_468[0x600-0x468];
+ u32 scratchrw[4];
+ u8 res_610[0x680-0x610];
+ u32 corebcr;
+diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
+index 0b813f9..b18494a 100644
+--- a/board/freescale/ls1012aqds/Makefile
++++ b/board/freescale/ls1012aqds/Makefile
+@@ -5,3 +5,4 @@
+ #
+
+ obj-y += ls1012aqds.o
++obj-y += eth.o
+diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
+new file mode 100644
+index 0000000..1bd7c9d
+--- /dev/null
++++ b/board/freescale/ls1012aqds/eth.c
+@@ -0,0 +1,199 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <netdev.h>
++#include <fm_eth.h>
++#include <fsl_mdio.h>
++#include <malloc.h>
++#include <fsl_dtsec.h>
++#include <asm/arch/soc.h>
++#include <asm/arch-fsl-layerscape/config.h>
++#include <asm/arch/fsl_serdes.h>
++
++#include "../common/qixis.h"
++#include "../../../drivers/net/pfe_eth/pfe_eth.h"
++#include "ls1012aqds_qixis.h"
++#include <asm/arch-fsl-layerscape/immap_lsch2.h>
++
++#define EMI_NONE 0xFF
++#define EMI1_RGMII 1
++#define EMI1_SLOT1 2
++#define EMI1_SLOT2 3
++
++#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
++
++static int mdio_mux[NUM_FM_PORTS];
++
++static const char * const mdio_names[] = {
++ "NULL",
++ "LS1012AQDS_MDIO_RGMII",
++ "LS1012AQDS_MDIO_SLOT1",
++ "LS1012AQDS_MDIO_SLOT2",
++ "NULL",
++};
++
++static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval)
++{
++ return mdio_names[muxval];
++}
++
++struct ls1012aqds_mdio {
++ u8 muxval;
++ struct mii_dev *realbus;
++};
++
++static void ls1012aqds_mux_mdio(u8 muxval)
++{
++ u8 brdcfg4;
++
++ if (muxval < 7) {
++ brdcfg4 = QIXIS_READ(brdcfg[4]);
++ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
++ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
++ QIXIS_WRITE(brdcfg[4], brdcfg4);
++ }
++}
++
++static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
++ int regnum)
++{
++ struct ls1012aqds_mdio *priv = bus->priv;
++
++ ls1012aqds_mux_mdio(priv->muxval);
++
++ return priv->realbus->read(priv->realbus, addr, devad, regnum);
++}
++
++static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
++ int regnum, u16 value)
++{
++ struct ls1012aqds_mdio *priv = bus->priv;
++
++ ls1012aqds_mux_mdio(priv->muxval);
++
++ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
++}
++
++static int ls1012aqds_mdio_reset(struct mii_dev *bus)
++{
++ struct ls1012aqds_mdio *priv = bus->priv;
++
++ if(priv->realbus->reset)
++ return priv->realbus->reset(priv->realbus);
++}
++
++static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
++{
++ struct ls1012aqds_mdio *pmdio;
++ struct mii_dev *bus = mdio_alloc();
++
++ if (!bus) {
++ printf("Failed to allocate ls1012aqds MDIO bus\n");
++ return -1;
++ }
++
++ pmdio = malloc(sizeof(*pmdio));
++ if (!pmdio) {
++ printf("Failed to allocate ls1012aqds private data\n");
++ free(bus);
++ return -1;
++ }
++
++ bus->read = ls1012aqds_mdio_read;
++ bus->write = ls1012aqds_mdio_write;
++ bus->reset = ls1012aqds_mdio_reset;
++ sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval));
++
++ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
++
++ if (!pmdio->realbus) {
++ printf("No bus with name %s\n", realbusname);
++ free(bus);
++ free(pmdio);
++ return -1;
++ }
++
++ pmdio->muxval = muxval;
++ bus->priv = pmdio;
++ return mdio_register(bus);
++}
++
++int board_eth_init(bd_t *bis)
++{
++#ifdef CONFIG_FSL_PPFE
++ struct mii_dev *bus;
++ struct mdio_info mac1_mdio_info;
++ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
++ u8 data8;
++
++
++ /*TODO Following config should be done for all boards, where is the right place to put this */
++ out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
++ out_be32(&scfg->pfebsbcr, in_be32(&scfg->pfebsbcr) | SCFG_PPFEASBCR_AWCACHE0);
++
++ /*CCI-400 QoS settings for PFE */
++ out_be32(&scfg->wr_qos1, 0x0ff00000);
++ out_be32(&scfg->rd_qos1, 0x0ff00000);
++
++ /* Set RGMII into 1G + Full duplex mode */
++ out_be32(&scfg->rgmiipcr, in_be32(&scfg->rgmiipcr) | (SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETFD));
++
++ out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x520), 0xFFFFFFFF);
++ out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x524), 0xFFFFFFFF);
++
++ ls1012aqds_mux_mdio(2);
++
++#ifdef RGMII_RESET_WA
++ /* Work around for FPGA registers initialization
++ * This is needed for RGMII to work */
++ printf("Reset RGMII WA....\n");
++ data8 = QIXIS_READ(rst_frc[0]);
++ data8 |= 0x2;
++ QIXIS_WRITE(rst_frc[0], data8);
++ data8 = QIXIS_READ(rst_frc[0]);
++
++ data8 = QIXIS_READ(res8[6]);
++ data8 |= 0xff;
++ QIXIS_WRITE(res8[6], data8);
++ data8 = QIXIS_READ(res8[6]);
++
++#endif
++
++ mac1_mdio_info.reg_base = (void *)0x04200000; /*EMAC1_BASE_ADDR*/
++ mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
++
++ bus = ls1012a_mdio_init(&mac1_mdio_info);
++ if(!bus)
++ {
++ printf("Failed to register mdio \n");
++ return -1;
++ }
++
++ /*Based on RCW config initialize correctly */
++ /*MAC2 */
++ if(ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII) < 0)
++ {
++ printf("Failed to register mdio for %s\n", ls1012aqds_mdio_name_for_muxval(EMI1_RGMII));
++ return -1;
++ }
++ ls1012a_set_mdio(1, miiphy_get_dev_by_name(ls1012aqds_mdio_name_for_muxval(EMI1_RGMII)));
++ ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_RGMII);
++
++ /*MAC1 */
++ if(ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1) < 0)
++ {
++ printf("Failed to register mdio for %s\n", ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1));
++ return -1;
++ }
++ ls1012a_set_mdio(0, miiphy_get_dev_by_name(ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1)));
++ ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
++
++ cpu_eth_init(bis);
++#endif
++ return pci_eth_init(bis);
++}
+diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
+index 446989b..b7365e8 100644
+--- a/board/freescale/ls1012aqds/ls1012aqds.c
++++ b/board/freescale/ls1012aqds/ls1012aqds.c
+@@ -211,11 +211,6 @@ int board_init(void)
+ return 0;
+ }
+
+-int board_eth_init(bd_t *bis)
+-{
+- return pci_eth_init(bis);
+-}
+-
+ #ifdef CONFIG_OF_BOARD_SETUP
+ int ft_board_setup(void *blob, bd_t *bd)
+ {
+diff --git a/board/freescale/ls1012aqds/ls1012aqds.h b/board/freescale/ls1012aqds/ls1012aqds.h
+new file mode 100644
+index 0000000..42e10f5
+--- /dev/null
++++ b/board/freescale/ls1012aqds/ls1012aqds.h
+@@ -0,0 +1,149 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __LS1012AQDS_H__
++#define __LS1012AQDS_H__
++
++#include "ls1012a_common.h"
++
++
++#define CONFIG_DIMM_SLOTS_PER_CTLR 1
++#define CONFIG_CHIP_SELECTS_PER_CTRL 1
++#define CONFIG_NR_DRAM_BANKS 2
++
++#ifdef CONFIG_FSL_PPFE
++/*#define CONFIG_CMD_PFE_START */
++#define EMAC1_PHY_ADDR 0x1e
++#define EMAC2_PHY_ADDR 0x1
++#define CONFIG_PHYLIB
++#define CONFIG_PHY_VITESSE
++#define CONFIG_PHY_REALTEK
++#endif
++
++#define CONFIG_QIXIS_I2C_ACCESS
++#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
++
++/*
++ * I2C bus multiplexer
++ */
++#define I2C_MUX_PCA_ADDR_PRI 0x77
++#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
++#define I2C_RETIMER_ADDR 0x18
++#define I2C_MUX_CH_DEFAULT 0x8
++#define I2C_MUX_CH_CH7301 0xC
++#define I2C_MUX_CH5 0xD
++#define I2C_MUX_CH7 0xF
++
++#define I2C_MUX_CH_VOL_MONITOR 0xa
++
++/*
++* RTC configuration
++*/
++#define RTC
++#define CONFIG_RTC_PCF8563 1
++#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
++#define CONFIG_CMD_DATE
++
++/* EEPROM */
++#define CONFIG_ID_EEPROM
++#define CONFIG_CMD_EEPROM
++#define CONFIG_SYS_I2C_EEPROM_NXID
++#define CONFIG_SYS_EEPROM_BUS_NUM 0
++#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
++#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
++#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
++#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
++
++
++/* Voltage monitor on channel 2*/
++#define I2C_VOL_MONITOR_ADDR 0x40
++#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
++#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
++#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
++
++
++/* DSPI */
++#define CONFIG_FSL_DSPI
++#define CONFIG_FSL_DSPI1
++#define CONFIG_DEFAULT_SPI_BUS 1
++
++#define CONFIG_CMD_SPI
++#define MMAP_DSPI DSPI1_BASE_ADDR
++
++#define CONFIG_SYS_DSPI_CTAR0 1
++
++#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
++ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
++ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
++ DSPI_CTAR_DT(0))
++#define CONFIG_SPI_FLASH_SST /* cs1 */
++
++#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
++ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
++ DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
++ DSPI_CTAR_DT(0))
++#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
++
++#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
++ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
++ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
++ DSPI_CTAR_DT(0))
++#define CONFIG_SPI_FLASH_EON /* cs3 */
++
++#define CONFIG_SF_DEFAULT_SPEED 10000000
++#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
++#define CONFIG_SF_DEFAULT_BUS 1
++#define CONFIG_SF_DEFAULT_CS 0
++
++/*
++* USB
++*/
++/* EHCI Support - disbaled by default */
++/*#define CONFIG_HAS_FSL_DR_USB*/
++
++#ifdef CONFIG_HAS_FSL_DR_USB
++#define CONFIG_USB_EHCI
++#define CONFIG_USB_EHCI_FSL
++#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
++#endif
++
++/*XHCI Support - enabled by default*/
++#define CONFIG_HAS_FSL_XHCI_USB
++
++#ifdef CONFIG_HAS_FSL_XHCI_USB
++#define CONFIG_USB_XHCI
++#define CONFIG_USB_XHCI_FSL
++#define CONFIG_USB_XHCI_DWC3
++#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
++#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
++#define CONFIG_CMD_USB
++#define CONFIG_USB_STORAGE
++#define CONFIG_CMD_EXT2
++
++#define CONFIG_USB_DWC3
++#define CONFIG_USB_DWC3_GADGET
++
++#define CONFIG_USB_GADGET
++#define CONFIG_USB_FUNCTION_MASS_STORAGE
++#define CONFIG_USB_GADGET_DOWNLOAD
++#define CONFIG_USB_GADGET_VBUS_DRAW 2
++#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
++#define CONFIG_G_DNL_VENDOR_NUM 0x1234
++#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
++#define CONFIG_USB_GADGET_DUALSPEED
++
++/* USB Gadget ums command */
++#define CONFIG_CMD_USB_MASS_STORAGE
++#endif
++
++#define CONFIG_CMD_MEMINFO
++#define CONFIG_CMD_MEMTEST
++#define CONFIG_SYS_MEMTEST_START 0x80000000
++#define CONFIG_SYS_MEMTEST_END 0x9fffffff
++
++#define CONFIG_MISC_INIT_R
++
++#endif /* __LS1012AQDS_H__ */
+diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
+index 584f604..7a1ba3d 100644
+--- a/board/freescale/ls1012aqds/ls1012aqds_qixis.h
++++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
+@@ -11,7 +11,7 @@
+
+ /* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+ #define BRDCFG4_EMISEL_MASK 0xe0
+-#define BRDCFG4_EMISEL_SHIFT 5
++#define BRDCFG4_EMISEL_SHIFT 6
+
+ /* SYSCLK */
+ #define QIXIS_SYSCLK_66 0x0
+diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
+index 05fa9d9..bd80ce5 100644
+--- a/board/freescale/ls1012ardb/Makefile
++++ b/board/freescale/ls1012ardb/Makefile
+@@ -5,3 +5,4 @@
+ #
+
+ obj-y += ls1012ardb.o
++obj-y += eth.o
+diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
+new file mode 100644
+index 0000000..29830e8
+--- /dev/null
++++ b/board/freescale/ls1012ardb/eth.c
+@@ -0,0 +1,68 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <netdev.h>
++#include <fm_eth.h>
++#include <fsl_mdio.h>
++#include <malloc.h>
++#include <fsl_dtsec.h>
++#include <asm/arch/soc.h>
++#include <asm/arch-fsl-layerscape/config.h>
++#include <asm/arch/fsl_serdes.h>
++
++#include "../../../drivers/net/pfe_eth/pfe_eth.h"
++#include <asm/arch-fsl-layerscape/immap_lsch2.h>
++
++#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
++
++int board_eth_init(bd_t *bis)
++{
++#ifdef CONFIG_FSL_PPFE
++ struct mii_dev *bus;
++ struct mdio_info mac1_mdio_info;
++ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
++
++
++ /*TODO Following config should be done for all boards, where is the right place to put this */
++ out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
++ out_be32(&scfg->pfebsbcr, in_be32(&scfg->pfebsbcr) | SCFG_PPFEASBCR_AWCACHE0);
++
++ /*CCI-400 QoS settings for PFE */
++ out_be32(&scfg->wr_qos1, 0x0ff00000);
++ out_be32(&scfg->rd_qos1, 0x0ff00000);
++
++ /* Set RGMII into 1G + Full duplex mode */
++ out_be32(&scfg->rgmiipcr, in_be32(&scfg->rgmiipcr) | (SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETFD));
++
++
++ out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x520), 0xFFFFFFFF);
++ out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x524), 0xFFFFFFFF);
++
++ mac1_mdio_info.reg_base = (void *)0x04200000; /*EMAC1_BASE_ADDR*/
++ mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
++
++ bus = ls1012a_mdio_init(&mac1_mdio_info);
++ if(!bus)
++ {
++ printf("Failed to register mdio \n");
++ return -1;
++ }
++
++ /*MAC1 */
++ ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
++ ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
++
++ /*MAC2 */
++ ls1012a_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
++ ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_RGMII);
++
++
++ cpu_eth_init(bis);
++#endif
++ return pci_eth_init(bis);
++}
+diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
+index 347b8c8..90cbd5e 100644
+--- a/board/freescale/ls1012ardb/ls1012ardb.c
++++ b/board/freescale/ls1012ardb/ls1012ardb.c
+@@ -163,10 +163,6 @@ int dram_init(void)
+ return 0;
+ }
+
+-int board_eth_init(bd_t *bis)
+-{
+- return pci_eth_init(bis);
+-}
+
+ int board_early_init_f(void)
+ {
+diff --git a/common/Makefile b/common/Makefile
+index 2a1d9f8..f5db77e 100644
+--- a/common/Makefile
++++ b/common/Makefile
+@@ -136,6 +136,8 @@ obj-$(CONFIG_CMD_MII) += cmd_mii.o
+ ifdef CONFIG_PHYLIB
+ obj-$(CONFIG_CMD_MII) += cmd_mdio.o
+ endif
++obj-$(CONFIG_CMD_PFE_COMMANDS) += cmd_pfe_commands.o
++obj-$(CONFIG_CMD_PFE_COMMANDS) += cmd_gemac_stat.o
+ obj-$(CONFIG_CMD_MISC) += cmd_misc.o
+ obj-$(CONFIG_CMD_MMC) += cmd_mmc.o
+ obj-$(CONFIG_CMD_MMC_SPI) += cmd_mmc_spi.o
+diff --git a/common/cmd_gemac_stat.c b/common/cmd_gemac_stat.c
+new file mode 100644
+index 0000000..49bb1aa
+--- /dev/null
++++ b/common/cmd_gemac_stat.c
+@@ -0,0 +1,147 @@
++/*
++ * (C) Copyright 2003
++ * Author : Laurent Brando (Mindspeed Technologies)
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++/**
++ * @file
++ * @brief Retrieve GEMAC Statistics
++ */
++
++#include <common.h>
++#include <command.h>
++#include "../drivers/net/pfe_eth/pfe_eth.h"
++#include "../drivers/net/pfe_eth/pfe/pfe.h"
++#include "../drivers/net/pfe_eth/pfe_firmware.h"
++#include "../drivers/net/pfe_eth/pfe/cbus.h"
++#include "../drivers/net/pfe_eth/pfe/cbus/class_csr.h"
++#include "../drivers/net/pfe_eth/pfe/cbus/emac.h"
++
++#define ETH_GSTRING_LEN 32 /* from linux/include/ethtool.h */
++
++static const struct fec_stat {
++ char name[ETH_GSTRING_LEN];
++ u16 offset;
++} fec_stats[] = {
++ /* RMON TX */
++ { "tx_dropped", RMON_T_DROP },
++ { "tx_packets", RMON_T_PACKETS },
++ { "tx_broadcast", RMON_T_BC_PKT },
++ { "tx_multicast", RMON_T_MC_PKT },
++ { "tx_crc_errors", RMON_T_CRC_ALIGN },
++ { "tx_undersize", RMON_T_UNDERSIZE },
++ { "tx_oversize", RMON_T_OVERSIZE },
++ { "tx_fragment", RMON_T_FRAG },
++ { "tx_jabber", RMON_T_JAB },
++ { "tx_collision", RMON_T_COL },
++ { "tx_64byte", RMON_T_P64 },
++ { "tx_65to127byte", RMON_T_P65TO127 },
++ { "tx_128to255byte", RMON_T_P128TO255 },
++ { "tx_256to511byte", RMON_T_P256TO511 },
++ { "tx_512to1023byte", RMON_T_P512TO1023 },
++ { "tx_1024to2047byte", RMON_T_P1024TO2047 },
++ { "tx_GTE2048byte", RMON_T_P_GTE2048 },
++ { "tx_octets", RMON_T_OCTETS },
++
++ /* IEEE TX */
++ { "IEEE_tx_drop", IEEE_T_DROP },
++ { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
++ { "IEEE_tx_1col", IEEE_T_1COL },
++ { "IEEE_tx_mcol", IEEE_T_MCOL },
++ { "IEEE_tx_def", IEEE_T_DEF },
++ { "IEEE_tx_lcol", IEEE_T_LCOL },
++ { "IEEE_tx_excol", IEEE_T_EXCOL },
++ { "IEEE_tx_macerr", IEEE_T_MACERR },
++ { "IEEE_tx_cserr", IEEE_T_CSERR },
++ { "IEEE_tx_sqe", IEEE_T_SQE },
++ { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
++ { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
++
++ /* RMON RX */
++ { "rx_packets", RMON_R_PACKETS },
++ { "rx_broadcast", RMON_R_BC_PKT },
++ { "rx_multicast", RMON_R_MC_PKT },
++ { "rx_crc_errors", RMON_R_CRC_ALIGN },
++ { "rx_undersize", RMON_R_UNDERSIZE },
++ { "rx_oversize", RMON_R_OVERSIZE },
++ { "rx_fragment", RMON_R_FRAG },
++ { "rx_jabber", RMON_R_JAB },
++ { "rx_64byte", RMON_R_P64 },
++ { "rx_65to127byte", RMON_R_P65TO127 },
++ { "rx_128to255byte", RMON_R_P128TO255 },
++ { "rx_256to511byte", RMON_R_P256TO511 },
++ { "rx_512to1023byte", RMON_R_P512TO1023 },
++ { "rx_1024to2047byte", RMON_R_P1024TO2047 },
++ { "rx_GTE2048byte", RMON_R_P_GTE2048 },
++ { "rx_octets", RMON_R_OCTETS },
++
++ /* IEEE RX */
++ { "IEEE_rx_drop", IEEE_R_DROP },
++ { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
++ { "IEEE_rx_crc", IEEE_R_CRC },
++ { "IEEE_rx_align", IEEE_R_ALIGN },
++ { "IEEE_rx_macerr", IEEE_R_MACERR },
++ { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
++ { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
++};
++
++static void ls1012a_emac_print_stats(void *base)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
++ printf("%s: %d\n", fec_stats[i].name, readl(base + fec_stats[i].offset));
++}
++
++static int gemac_stats(cmd_tbl_t *cmdtp, int flag, int argc,
++ char * const argv[])
++{
++ void *gemac_base = NULL;
++
++ if (argc != 2) {
++ printf("Usage: \n" "gemac_stat [ethx]\n");
++ return CMD_RET_SUCCESS;
++ }
++
++ if ( strcmp(argv[1], "eth0") == 0)
++ gemac_base = (void *)EMAC1_BASE_ADDR;
++ else if ( strcmp(argv[1], "eth1") == 0)
++ gemac_base = (void *)EMAC2_BASE_ADDR;
++
++ if (gemac_base)
++ {
++ ls1012a_emac_print_stats(gemac_base);
++ }
++ else
++ {
++ printf("no such net device: %s\n", argv[1]);
++ return 1;
++ }
++
++ return 0;
++}
++
++U_BOOT_CMD(
++ gemac_stat, 2, 1, gemac_stats,
++ "retrieve GEMAC statistics",
++ "Usage: \n"
++ "gemac_stat [ethx]\n"
++);
+diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
+new file mode 100644
+index 0000000..f9f92c7
+--- /dev/null
++++ b/common/cmd_pfe_commands.c
+@@ -0,0 +1,983 @@
++/*
++ * (C) Copyright 2012
++ * Author : Bill Westland (Mindspeed Technologies)
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++/**
++ * @file
++ * @brief PFE utility commands
++ */
++
++#include <common.h>
++#include <command.h>
++#include "../drivers/net/pfe_eth/pfe_eth.h"
++#include "../drivers/net/pfe_eth/pfe/pfe.h"
++#include "../drivers/net/pfe_eth/pfe_firmware.h"
++#include "../drivers/net/pfe_eth/pfe/cbus/class_csr.h"
++#include "../drivers/net/pfe_eth/pfe/cbus/gpi.h"
++DECLARE_GLOBAL_DATA_PTR;
++
++int pfe_load_elf(int pe_mask, const struct firmware *fw);
++int ls1012a_gemac_initialize(bd_t * bis, int dev_id, char *devname);
++
++static void pfe_command_help(void)
++{
++ printf("Usage: pfe [start | firmware | load | lib | pe | gemac | gem | gpi | class | tmu | util | hif | status | expt | fftest] <options>\n");
++}
++
++static void pfe_command_firmware(int argc, char * const argv[])
++{
++ if (argc == 3 && strcmp(argv[2], "init") == 0)
++ {
++ pfe_firmware_init((u8 *)0x80100000, (u8 *)0x80180000, (u8 *)0x80200000);
++ }
++ else if (argc == 3 && strcmp(argv[2], "exit") == 0)
++ {
++ pfe_firmware_exit();
++ }
++ else
++ {
++ if (argc >= 3 && strcmp(argv[2], "help") != 0)
++ {
++ printf("Unknown option: %s\n", argv[2]);
++ }
++ printf("Usage: pfe firmware [init | exit]\n");
++ }
++}
++
++static void pfe_command_load(int argc, char * const argv[])
++{
++ if (argc >= 3 && strcmp(argv[2], "elf") == 0)
++ {
++ if (argc == 5)
++ {
++ u32 mask;
++ unsigned long image_start;
++ struct firmware fw;
++ mask = simple_strtoul(argv[3], NULL, 0);
++ image_start = simple_strtoul(argv[4], NULL, 16);
++ fw.data = (u8 *)image_start;
++ pfe_load_elf(mask, &fw);
++ }
++ else
++ {
++ printf("Usage: pfe load elf <pe_mask> <image_start>\n");
++ }
++ }
++ else
++ {
++ if (argc >= 3 && strcmp(argv[2], "help") != 0)
++ {
++ printf("Unknown option: %s\n", argv[2]);
++ }
++ printf("Usage: pfe load elf <parameters>\n");
++ }
++}
++#if 0
++static void pfe_command_lib(int argc, char *argv[])
++{
++ if (argc >= 3 && strcmp(argv[2], "init") == 0)
++ {
++ if (argc == 3)
++ pfe_lib_init((void *)COMCERTO_AXI_HFE_CFG_BASE, (void *)CONFIG_DDR_BASEADDR, CONFIG_DDR_PHYS_BASEADDR);
++ else if (argc == 6)
++ {
++ u32 cbus_base;
++ u32 ddr_base;
++ u32 ddr_phys_base;
++ cbus_base = simple_strtoul(argv[3], NULL, 16);
++ ddr_base = simple_strtoul(argv[4], NULL, 16);
++ ddr_phys_base = simple_strtoul(argv[5], NULL, 16);
++ pfe_lib_init((void *)cbus_base, (void *)ddr_base, ddr_phys_base);
++ }
++ else
++ {
++ printf("Usage: pfe lib init [<cbus_base> <ddr_base> <ddr_phys_base>]\n");
++ }
++ }
++ else
++ {
++ if (argc >= 3 && strcmp(argv[2], "help") != 0)
++ {
++ printf("Unknown option: %s\n", argv[2]);
++ }
++ printf("Usage: pfe lib init <parameters>\n");
++ }
++}
++#endif
++static void pfe_command_pe(int argc, char * const argv[])
++{
++ if (argc >= 3 && strcmp(argv[2], "pmem") == 0)
++ {
++ if (argc >= 4 && strcmp(argv[3], "read") == 0)
++ {
++ int i;
++ int num;
++ int id;
++ u32 addr;
++ u32 size;
++ u32 val;
++ if (argc == 7)
++ num = simple_strtoul(argv[6], NULL, 0);
++ else if (argc == 6)
++ num = 1;
++ else
++ {
++ printf("Usage: pfe pe pmem read <id> <addr> [<num>]\n");
++ return;
++ }
++ id = simple_strtoul(argv[4], NULL, 0);
++ addr = simple_strtoul(argv[5], NULL, 16);
++ size = 4;
++ for (i = 0; i < num; i++, addr += 4)
++ {
++ val = pe_pmem_read(id, addr, size);
++ val = be32_to_cpu(val);
++ if(!(i&3)) printf("%08x: ", addr);
++ printf("%08x%s", val, i == num - 1 || (i & 3) == 3 ? "\n" : " ");
++ }
++ }
++ else
++ {
++ printf("Usage: pfe pe pmem read <parameters>\n");
++ }
++ }
++ else if (argc >= 3 && strcmp(argv[2], "dmem") == 0)
++ {
++ if (argc >= 4 && strcmp(argv[3], "read") == 0)
++ {
++ int i;
++ int num;
++ int id;
++ u32 addr;
++ u32 size;
++ u32 val;
++ if (argc == 7)
++ num = simple_strtoul(argv[6], NULL, 0);
++ else if (argc == 6)
++ num = 1;
++ else
++ {
++ printf("Usage: pfe pe dmem read <id> <addr> [<num>]\n");
++ return;
++ }
++ id = simple_strtoul(argv[4], NULL, 0);
++ addr = simple_strtoul(argv[5], NULL, 16);
++ size = 4;
++ for (i = 0; i < num; i++, addr += 4)
++ {
++ val = pe_dmem_read(id, addr, size);
++ val = be32_to_cpu(val);
++ if(!(i&3)) printf("%08x: ", addr);
++ printf("%08x%s", val, i == num - 1 || (i & 3) == 3 ? "\n" : " ");
++ }
++ }
++ else if (argc >= 4 && strcmp(argv[3], "write") == 0)
++ {
++ int id;
++ u32 val;
++ u32 addr;
++ u32 size;
++ if (argc != 7)
++ {
++ printf("Usage: pfe pe dmem write <id> <val> <addr>\n");
++ return;
++ }
++ id = simple_strtoul(argv[4], NULL, 0);
++ val = simple_strtoul(argv[5], NULL, 16);
++ val = cpu_to_be32(val);
++ addr = simple_strtoul(argv[6], NULL, 16);
++ size = 4;
++ pe_dmem_write(id, val, addr, size);
++ }
++ else
++ {
++ printf("Usage: pfe pe dmem [read | write] <parameters>\n");
++ }
++ }
++ else if (argc >= 3 && strcmp(argv[2], "lmem") == 0)
++ {
++ if (argc >= 4 && strcmp(argv[3], "read") == 0)
++ {
++ int i;
++ int num;
++ u32 val;
++ u32 offset;
++ if (argc == 6)
++ num = simple_strtoul(argv[5], NULL, 0);
++ else if (argc == 5)
++ num = 1;
++ else
++ {
++ printf("Usage: pfe pe lmem read <offset> [<num>]\n");
++ return;
++ }
++ offset = simple_strtoul(argv[4], NULL, 16);
++ for (i = 0; i < num; i++, offset += 4)
++ {
++ pe_lmem_read(&val, 4, offset);
++ val = be32_to_cpu(val);
++ printf("%08x%s", val, i == num - 1 || (i & 7) == 7 ? "\n" : " ");
++ }
++ }
++ else if (argc >= 4 && strcmp(argv[3], "write") == 0)
++ {
++ u32 val;
++ u32 offset;
++ if (argc != 6)
++ {
++ printf("Usage: pfe pe lmem write <val> <offset>\n");
++ return;
++ }
++ val = simple_strtoul(argv[4], NULL, 16);
++ val = cpu_to_be32(val);
++ offset = simple_strtoul(argv[5], NULL, 16);
++ pe_lmem_write(&val, 4, offset);
++ }
++ else
++ {
++ printf("Usage: pfe pe lmem [read | write] <parameters>\n");
++ }
++ }
++ else
++ {
++ if (strcmp(argv[2], "help") != 0)
++ {
++ printf("Unknown option: %s\n", argv[2]);
++ }
++ printf("Usage: pfe pe <parameters>\n");
++ }
++ //void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned int len)
++ //void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
++ //void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
++ //int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr)
++}
++
++#if 0
++static void pfe_command_gemac(int argc, char *argv[])
++{
++void gemac_init(void *base, void *cfg)
++void gemac_set_speed(void *base, MAC_SPEED gem_speed)
++void gemac_set_duplex(void *base, int duplex)
++void gemac_set_mode(void *base, int mode)
++void gemac_reset(void *base)
++void gemac_enable(void *base)
++void gemac_disable(void *base)
++void gemac_set_address(void *base, SPEC_ADDR *addr)
++SPEC_ADDR gemac_get_address(void *base)
++void gemac_set_laddr1(void *base, MAC_ADDR *address)
++void gemac_set_laddr2(void *base, MAC_ADDR *address)
++void gemac_set_laddr3(void *base, MAC_ADDR *address)
++void gemac_set_laddr4(void *base, MAC_ADDR *address)
++void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index)
++void gemac_allow_broadcast(void *base)
++void gemac_no_broadcast(void *base)
++void gemac_enable_unicast(void *base)
++void gemac_disable_unicast(void *base)
++void gemac_enable_multicast(void *base)
++void gemac_disable_multicast(void *base)
++void gemac_enable_fcs_rx(void *base)
++void gemac_disable_fcs_rx(void *base)
++void gemac_enable_1536_rx(void *base)
++void gemac_disable_1536_rx(void *base)
++void gemac_enable_pause_rx(void *base)
++void gemac_disable_pause_rx(void *base)
++void gemac_set_config(void *base, GEMAC_CFG *cfg)
++unsigned int * gemac_get_stats(void *base)
++}
++#endif
++
++#if 0
++static void pfe_command_gem(int argc, char *argv[])
++{
++MAC_ADDR gem_get_laddr1(void *base)
++MAC_ADDR gem_get_laddr2(void *base)
++MAC_ADDR gem_get_laddr3(void *base)
++MAC_ADDR gem_get_laddr4(void *base)
++MAC_ADDR gem_get_laddrN(void *base, unsigned int entry_index)
++}
++#endif
++
++#if 0
++static void pfe_command_gpi(int argc, char *argv[])
++{
++void gpi_init(void *base, GPI_CFG *cfg)
++void gpi_reset(void *base)
++void gpi_enable(void *base)
++void gpi_disable(void *base)
++void gpi_set_config(void *base, GPI_CFG *cfg)
++}
++#endif
++
++#if 1
++static void pfe_command_class(int argc, char * const argv[])
++{
++ if (argc >= 3 && strcmp(argv[2], "init") == 0)
++ {
++ CLASS_CFG cfg;
++ if (argc == 3)
++ {
++#define CONFIG_DDR_PHYS_BASEADDR 0x03800000
++ cfg.route_table_hash_bits = ROUTE_TABLE_HASH_BITS;
++ cfg.route_table_baseaddr = CONFIG_DDR_PHYS_BASEADDR + ROUTE_TABLE_BASEADDR;
++ }
++ else if (argc == 5)
++ {
++ cfg.route_table_hash_bits = simple_strtoul(argv[3], NULL, 16);
++ cfg.route_table_baseaddr = simple_strtoul(argv[4], NULL, 16);
++ }
++ else
++ {
++ printf("Usage: pfe class init <route_table_hash_bits> <route_table_baseaddr>\n");
++ }
++ class_init(&cfg);
++ }
++ else if (argc == 3 && strcmp(argv[2], "reset") == 0)
++ {
++ class_reset();
++ }
++ else if (argc == 3 && strcmp(argv[2], "enable") == 0)
++ {
++ class_enable();
++ }
++ else if (argc == 3 && strcmp(argv[2], "disable") == 0)
++ {
++ class_disable();
++ }
++ else if (argc >= 3 && strcmp(argv[2], "config") == 0)
++ {
++ CLASS_CFG cfg;
++ if (argc == 3)
++ {
++ cfg.route_table_hash_bits = ROUTE_TABLE_HASH_BITS;
++ cfg.route_table_baseaddr = CONFIG_DDR_PHYS_BASEADDR + ROUTE_TABLE_BASEADDR;
++ }
++ else if (argc == 5)
++ {
++ cfg.route_table_hash_bits = simple_strtoul(argv[3], NULL, 16);
++ cfg.route_table_baseaddr = simple_strtoul(argv[4], NULL, 16);
++ }
++ else
++ {
++ printf("Usage: pfe class config <route_table_hash_bits> <route_table_baseaddr>\n");
++ }
++ class_set_config(&cfg);
++ }
++ else if (argc >= 3 && strcmp(argv[2], "bus") == 0)
++ {
++ if (argc >= 4 && strcmp(argv[3], "read") == 0)
++ {
++ u32 addr;
++ u32 size;
++ u32 val;
++ if (argc != 6)
++ {
++ printf("Usage: pfe class bus read <addr> <size>\n");
++ return;
++ }
++ addr = simple_strtoul(argv[4], NULL, 16);
++ size = simple_strtoul(argv[5], NULL, 16);
++ val = class_bus_read(addr, size);
++ printf("%08x\n", val);
++ }
++ else if (argc >= 4 && strcmp(argv[3], "write") == 0)
++ {
++ u32 val;
++ u32 addr;
++ u32 size;
++ if (argc != 7)
++ {
++ printf("Usage: pfe class bus write <val> <addr> <size>\n");
++ return;
++ }
++ val = simple_strtoul(argv[4], NULL, 16);
++ addr = simple_strtoul(argv[5], NULL, 16);
++ size = simple_strtoul(argv[6], NULL, 16);
++ class_bus_write(val, addr, size);
++ }
++ else
++ {
++ printf("Usage: pfe class bus [read | write] <parameters>\n");
++ }
++ }
++ else
++ {
++ if (argc >= 3 && strcmp(argv[2], "help") != 0)
++ {
++ printf("Unknown option: %s\n", argv[2]);
++ }
++ printf("Usage: pfe class [init | reset | enable | disable | config | bus] <parameters>\n");
++ }
++}
++
++static void pfe_command_tmu(int argc, char * const argv[])
++{
++ if (argc >= 3 && strcmp(argv[2], "init") == 0)
++ {
++ if (argc == 5)
++ {
++ TMU_CFG cfg;
++ cfg.llm_base_addr = simple_strtoul(argv[3], NULL, 16);
++ cfg.llm_queue_len = simple_strtoul(argv[4], NULL, 16);
++ tmu_init(&cfg);
++ }
++ else
++ {
++ printf("Usage: pfe tmu init <llm_base_addr> <llm_queue_len>\n");
++ }
++ }
++ else if (argc >= 3 && strcmp(argv[2], "enable") == 0)
++ {
++ if (argc == 4)
++ {
++ u32 mask;
++ mask = simple_strtoul(argv[3], NULL, 16);
++ tmu_enable(mask);
++ }
++ else
++ {
++ printf("Usage: pfe tmu enable <pe_mask>\n");
++ }
++ }
++ else if (argc >= 3 && strcmp(argv[2], "disable") == 0)
++ {
++ if (argc == 4)
++ {
++ u32 mask;
++ mask = simple_strtoul(argv[3], NULL, 16);
++ tmu_disable(mask);
++ }
++ else
++ {
++ printf("Usage: pfe tmu disable <pe_mask>\n");
++ }
++ }
++ else
++ {
++ if (argc >= 3 && strcmp(argv[2], "help") != 0)
++ {
++ printf("Unknown option: %s\n", argv[2]);
++ }
++ printf("Usage: pfe tmu [init | enable | disable] <parameters>\n");
++ }
++}
++#endif
++
++/** qm_read_drop_stat
++ * This function is used to read the drop statistics from the TMU
++ * hw drop counter. Since the hw counter is always cleared afer
++ * reading, this function maintains the previous drop count, and
++ * adds the new value to it. That value can be retrieved by
++ * passing a pointer to it with the total_drops arg.
++ *
++ * @param tmu TMU number (0 - 3)
++ * @param queue queue number (0 - 15)
++ * @param total_drops pointer to location to store total drops (or NULL)
++ * @param do_reset if TRUE, clear total drops after updating
++ *
++ */
++
++u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset)
++{
++#define NUM_QUEUES 16
++ static u32 qtotal[TMU_MAX_ID + 1][NUM_QUEUES];
++ u32 val;
++ writel((tmu << 8) | queue, TMU_TEQ_CTRL);
++ writel((tmu << 8) | queue, TMU_LLM_CTRL);
++ val = readl(TMU_TEQ_DROP_STAT);
++ qtotal[tmu][queue] += val;
++ if (total_drops)
++ *total_drops = qtotal[tmu][queue];
++ if (do_reset)
++ qtotal[tmu][queue] = 0;
++ return val;
++}
++
++static ssize_t tmu_queue_stats(char *buf, int tmu, int queue)
++{
++ ssize_t len = 0;
++ u32 drops;
++
++ printf("%d-%02d, ", tmu, queue);
++
++ drops = qm_read_drop_stat(tmu, queue, NULL, 0);
++
++ /* Select queue */
++ writel((tmu << 8) | queue, TMU_TEQ_CTRL);
++ writel((tmu << 8) | queue, TMU_LLM_CTRL);
++
++ printf("(teq) drop: %10u, tx: %10u (llm) head: %08x, tail: %08x, drop: %10u\n",
++ drops, readl(TMU_TEQ_TRANS_STAT),
++ readl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR),
++ readl(TMU_LLM_QUE_DROPCNT));
++
++ return len;
++}
++
++
++static ssize_t tmu_queues(char *buf, int tmu)
++{
++ ssize_t len = 0;
++ int queue;
++
++ for (queue = 0; queue < 16; queue++)
++ len += tmu_queue_stats(buf + len, tmu, queue);
++
++ return len;
++}
++
++void hif_status(void)
++{
++ printf("hif:\n");
++
++ printf(" tx curr bd: %x\n", readl(HIF_TX_CURR_BD_ADDR));
++ printf(" tx status: %x\n", readl(HIF_TX_STATUS));
++ printf(" tx dma status: %x\n", readl(HIF_TX_DMA_STATUS));
++
++ printf(" rx curr bd: %x\n", readl(HIF_RX_CURR_BD_ADDR));
++ printf(" rx status: %x\n", readl(HIF_RX_STATUS));
++ printf(" rx dma status: %x\n", readl(HIF_RX_DMA_STATUS));
++
++ printf("hif nocopy:\n");
++
++ printf(" tx curr bd: %x\n", readl(HIF_NOCPY_TX_CURR_BD_ADDR));
++ printf(" tx status: %x\n", readl(HIF_NOCPY_TX_STATUS));
++ printf(" tx dma status: %x\n", readl(HIF_NOCPY_TX_DMA_STATUS));
++
++ printf(" rx curr bd: %x\n", readl(HIF_NOCPY_RX_CURR_BD_ADDR));
++ printf(" rx status: %x\n", readl(HIF_NOCPY_RX_STATUS));
++ printf(" rx dma status: %x\n", readl(HIF_NOCPY_RX_DMA_STATUS));
++}
++
++static void gpi(int id, void *base)
++{
++ u32 val;
++
++ printf("gpi%d:\n ", id);
++
++ printf(" tx under stick: %x\n", readl(base + GPI_FIFO_STATUS));
++ val = readl(base + GPI_FIFO_DEBUG);
++ printf(" tx pkts: %x\n", (val >> 23) & 0x3f);
++ printf(" rx pkts: %x\n", (val >> 18) & 0x3f);
++ printf(" tx bytes: %x\n", (val >> 9) & 0x1ff);
++ printf(" rx bytes: %x\n", (val >> 0) & 0x1ff);
++ printf(" overrun: %x\n", readl(base + GPI_OVERRUN_DROPCNT));
++}
++
++void bmu(int id, void *base)
++{
++ printf("bmu: %d\n", id);
++ printf(" buf size: %x\n", (1 << readl(base + BMU_BUF_SIZE)));
++ printf(" buf count: %x\n", readl(base + BMU_BUF_CNT));
++ printf(" buf rem: %x\n", readl(base + BMU_REM_BUF_CNT));
++ printf(" buf curr: %x\n", readl(base + BMU_CURR_BUF_CNT));
++ printf(" free err: %x\n", readl(base + BMU_FREE_ERR_ADDR));
++}
++
++#define PESTATUS_ADDR_CLASS 0x800
++#define PESTATUS_ADDR_TMU 0x80
++#define PESTATUS_ADDR_UTIL 0x0
++
++static void pfe_pe_status(int argc, char * const argv[])
++{
++ int do_clear = 0;
++ int j;
++ u32 id;
++ u32 dmem_addr;
++ u32 cpu_state;
++ u32 activity_counter;
++ u32 rx;
++ u32 tx;
++ u32 drop;
++ char statebuf[5];
++ u32 class_debug_reg = 0;
++ u32 debug_indicator;
++ u32 debug[16];
++
++ if (argc == 4 && strcmp(argv[3], "clear") == 0)
++ do_clear = 1;
++
++ for (id = CLASS0_ID; id < MAX_PE; id++)
++ {
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++ if (id == UTIL_ID)
++ {
++ printf("util:\n");
++ dmem_addr = PESTATUS_ADDR_UTIL;
++ }
++ else if (id >= TMU0_ID)
++#else
++ if (id >= TMU0_ID)
++#endif
++ {
++ if (id == TMU2_ID)
++ continue;
++ if (id == TMU0_ID)
++ printf("tmu:\n");
++ dmem_addr = PESTATUS_ADDR_TMU;
++ }
++ else
++ {
++ if (id == CLASS0_ID)
++ printf("class:\n");
++ dmem_addr = PESTATUS_ADDR_CLASS;
++ class_debug_reg = readl(CLASS_PE0_DEBUG + id * 4);
++ }
++ cpu_state = pe_dmem_read(id, dmem_addr, 4);
++ dmem_addr += 4;
++ memcpy(statebuf, (char *)&cpu_state, 4);
++ statebuf[4] = '\0';
++ activity_counter = pe_dmem_read(id, dmem_addr, 4);
++ dmem_addr += 4;
++ rx = pe_dmem_read(id, dmem_addr, 4);
++ if (do_clear)
++ pe_dmem_write(id, 0, dmem_addr, 4);
++ dmem_addr += 4;
++ tx = pe_dmem_read(id, dmem_addr, 4);
++ if (do_clear)
++ pe_dmem_write(id, 0, dmem_addr, 4);
++ dmem_addr += 4;
++ drop = pe_dmem_read(id, dmem_addr, 4);
++ if (do_clear)
++ pe_dmem_write(id, 0, dmem_addr, 4);
++ dmem_addr += 4;
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++ if (id == UTIL_ID)
++ {
++ printf("state=%4s ctr=%08x rx=%x tx=%x\n",
++ statebuf, cpu_to_be32(activity_counter),
++ cpu_to_be32(rx), cpu_to_be32(tx));
++ }
++ else
++#endif
++ if (id >= TMU0_ID)
++ {
++ printf("%d: state=%4s ctr=%08x rx=%x qstatus=%x\n",
++ id - TMU0_ID, statebuf, cpu_to_be32(activity_counter),
++ cpu_to_be32(rx), cpu_to_be32(tx));
++ }
++ else
++ {
++ printf("%d: pc=1%04x ldst=%04x state=%4s ctr=%08x rx=%x tx=%x drop=%x\n",
++ id - CLASS0_ID, class_debug_reg & 0xFFFF, class_debug_reg >> 16,
++ statebuf, cpu_to_be32(activity_counter),
++ cpu_to_be32(rx), cpu_to_be32(tx), cpu_to_be32(drop));
++ }
++ debug_indicator = pe_dmem_read(id, dmem_addr, 4);
++ dmem_addr += 4;
++ if (debug_indicator == cpu_to_be32('DBUG'))
++ {
++ int last = 0;
++ for (j = 0; j < 16; j++)
++ {
++ debug[j] = pe_dmem_read(id, dmem_addr, 4);
++ if (debug[j])
++ {
++ last = j + 1;
++ if (do_clear)
++ pe_dmem_write(id, 0, dmem_addr, 4);
++ }
++ dmem_addr += 4;
++ }
++ for (j = 0; j < last; j++)
++ {
++ printf("%08x%s", cpu_to_be32(debug[j]), (j & 0x7) == 0x7 || j == last - 1 ? "\n" : " ");
++ }
++ }
++ }
++
++}
++
++static void pfe_command_status(int argc, char * const argv[])
++{
++
++ if (argc >= 3 && strcmp(argv[2], "pe") == 0)
++ {
++ pfe_pe_status(argc, argv);
++ }
++ else if (argc == 3 && strcmp(argv[2], "bmu") == 0)
++ {
++ bmu(1, BMU1_BASE_ADDR);
++ bmu(2, BMU2_BASE_ADDR);
++ }
++ else if (argc == 3 && strcmp(argv[2], "hif") == 0)
++ {
++ hif_status();
++ }
++ else if (argc == 3 && strcmp(argv[2], "gpi") == 0)
++ {
++ gpi(0, EGPI1_BASE_ADDR);
++ gpi(1, EGPI2_BASE_ADDR);
++ gpi(3, HGPI_BASE_ADDR);
++ }
++ else if (argc == 3 && strcmp(argv[2], "tmu0_queues") == 0)
++ {
++ tmu_queues(NULL, 0);
++ }
++ else if (argc == 3 && strcmp(argv[2], "tmu1_queues") == 0)
++ {
++ tmu_queues(NULL, 1);
++ }
++ else if (argc == 3 && strcmp(argv[2], "tmu3_queues") == 0)
++ {
++ tmu_queues(NULL, 3);
++ }
++ else
++ printf("Usage: pfe status [pe <clear> | bmu | gpi | hif | tmuX_queues ]\n");
++
++ return;
++}
++
++
++#define EXPT_DUMP_ADDR 0x1fa8
++#define EXPT_REG_COUNT 20
++static const char *register_names[EXPT_REG_COUNT] = {
++ " pc", "ECAS", " EID", " ED",
++ " sp", " r1", " r2", " r3",
++ " r4", " r5", " r6", " r7",
++ " r8", " r9", " r10", " r11",
++ " r12", " r13", " r14", " r15"
++};
++
++static void pfe_command_expt(int argc, char * const argv[])
++{
++ unsigned int id, i, val, addr;
++
++ if (argc == 3)
++ {
++ id = simple_strtoul(argv[2], NULL, 0);
++ addr = EXPT_DUMP_ADDR;
++ printf("Exception information for PE %d:\n", id);
++ for (i = 0; i < EXPT_REG_COUNT; i++)
++ {
++ val = pe_dmem_read(id, addr, 4);
++ val = be32_to_cpu(val);
++ printf("%s:%08x%s", register_names[i], val, (i & 3) == 3 ? "\n" : " ");
++ addr += 4;
++ }
++ }
++ else
++ {
++ printf("Usage: pfe expt <id>\n");
++ }
++}
++
++static void pfe_command_util(int argc, char * const argv[])
++{
++ if (argc == 3 && strcmp(argv[2], "init") == 0)
++ {
++ UTIL_CFG cfg;
++ util_init(&cfg);
++ }
++ else if (argc == 3 && strcmp(argv[2], "reset") == 0)
++ {
++ util_reset();
++ }
++ else if (argc == 3 && strcmp(argv[2], "enable") == 0)
++ {
++ util_enable();
++ }
++ else if (argc == 3 && strcmp(argv[2], "disable") == 0)
++ {
++ util_disable();
++ }
++ else if (argc >= 3 && strcmp(argv[2], "bus") == 0)
++ {
++ if (argc >= 4 && strcmp(argv[3], "read") == 0)
++ {
++ u32 addr;
++ u32 size;
++ u32 val;
++ if (argc != 6)
++ {
++ printf("Usage: pfe util bus read <addr> <size>\n");
++ return;
++ }
++ addr = simple_strtoul(argv[4], NULL, 16);
++ size = simple_strtoul(argv[5], NULL, 16);
++ val = util_bus_read(addr, size);
++ printf("%08x\n", val);
++ }
++ else if (argc >= 4 && strcmp(argv[3], "write") == 0)
++ {
++ u32 val;
++ u32 addr;
++ u32 size;
++ if (argc != 7)
++ {
++ printf("Usage: pfe util bus write <val> <addr> <size>\n");
++ return;
++ }
++ val = simple_strtoul(argv[4], NULL, 16);
++ addr = simple_strtoul(argv[5], NULL, 16);
++ size = simple_strtoul(argv[6], NULL, 16);
++ util_bus_write(val, addr, size);
++ }
++ else
++ {
++ printf("Usage: pfe util bus [read | write] <parameters>\n");
++ }
++ }
++ else
++ {
++ if (argc >= 3 && strcmp(argv[2], "help") != 0)
++ {
++ printf("Unknown option: %s\n", argv[2]);
++ }
++ printf("Usage: pfe util [init | reset | enable | disable | bus] <parameters>\n");
++ }
++}
++
++#if 0
++static void pfe_command_hif(int argc, char *argv[])
++{
++void hif_nocpy_init(void)
++void hif_init(void)
++void hif_tx_enable(void)
++void hif_tx_disable(void)
++void hif_rx_enable(void)
++void hif_rx_disable(void)
++}
++#endif
++
++#define ROUTE_TABLE_START (CONFIG_DDR_PHYS_BASEADDR+ROUTE_TABLE_BASEADDR)
++static void pfe_command_fftest(int argc, char * const argv[])
++{
++ bd_t *bd = gd->bd;
++ struct eth_device *edev_eth0;
++ struct eth_device *edev_eth1;
++
++
++ // open eth0 and eth1
++ edev_eth0 = eth_get_dev_by_name("pfe_eth0");
++ if (!edev_eth0)
++ {
++ printf("Cannot access eth0\n");
++ return;
++ }
++
++ if (eth_write_hwaddr(edev_eth0, "eth", edev_eth0->index))
++ puts("\nWarning: failed to set MAC address for c2000_gemac0\n");
++
++ if (edev_eth0->state != ETH_STATE_ACTIVE)
++ {
++ if (edev_eth0->init(edev_eth0, bd) < 0) {
++ printf("eth0 init failed\n");
++ return;
++ }
++ edev_eth0->state = ETH_STATE_ACTIVE;
++ }
++
++ edev_eth1 = eth_get_dev_by_name("pfe_eth1");
++ if (!edev_eth1)
++ {
++ printf("Cannot access eth1\n");
++ return;
++ }
++
++ if (eth_write_hwaddr(edev_eth1, "eth", edev_eth1->index))
++ puts("\nWarning: failed to set MAC address for c2000_gemac1\n");
++
++ if (edev_eth1->state != ETH_STATE_ACTIVE)
++ {
++ if (edev_eth1->init(edev_eth1, bd) < 0) {
++ printf("eth1 init failed\n");
++ return;
++ }
++ edev_eth1->state = ETH_STATE_ACTIVE;
++ }
++
++}
++
++#ifdef CONFIG_CMD_PFE_START
++static void pfe_command_start(int argc, char * const argv[])
++{
++ printf("Starting PFE \n");
++ ls1012a_gemac_initialize(gd->bd, 0 , "pfe_eth0");
++ ls1012a_gemac_initialize(gd->bd, 1 , "pfe_eth1");
++}
++#endif
++
++
++static int pfe_command(cmd_tbl_t *cmdtp, int flag, int argc,
++ char * const argv[])
++{
++ if (argc == 1 || strcmp(argv[1], "help") == 0)
++ {
++ pfe_command_help();
++ return CMD_RET_SUCCESS;
++ }
++ if (strcmp(argv[1], "firmware") == 0)
++ pfe_command_firmware(argc, argv);
++ else if (strcmp(argv[1], "load") == 0)
++ pfe_command_load(argc, argv);
++#if 0
++ else if (strcmp(argv[1], "lib") == 0)
++ pfe_command_lib(argc, argv);
++#endif
++ else if (strcmp(argv[1], "pe") == 0)
++ pfe_command_pe(argc, argv);
++#if 0
++ else if (strcmp(argv[1], "gemac") == 0)
++ pfe_command_gemac(argc, argv);
++ else if (strcmp(argv[1], "gem") == 0)
++ pfe_command_gem(argc, argv);
++ else if (strcmp(argv[1], "gpi") == 0)
++ pfe_command_gpi(argc, argv);
++#endif
++#if 1
++ else if (strcmp(argv[1], "class") == 0)
++ pfe_command_class(argc, argv);
++ else if (strcmp(argv[1], "tmu") == 0)
++ pfe_command_tmu(argc, argv);
++#endif
++ else if (strcmp(argv[1], "status") == 0)
++ pfe_command_status(argc, argv);
++ else if (strcmp(argv[1], "expt") == 0)
++ pfe_command_expt(argc, argv);
++ else if (strcmp(argv[1], "util") == 0)
++ pfe_command_util(argc, argv);
++#if 0
++ else if (strcmp(argv[1], "hif") == 0)
++ pfe_command_hif(argc, argv);
++#endif
++ else if (strcmp(argv[1], "fftest") == 0)
++ pfe_command_fftest(argc, argv);
++#ifdef CONFIG_CMD_PFE_START
++ else if (strcmp(argv[1], "start") == 0)
++ pfe_command_start(argc, argv);
++#endif
++ else
++ {
++ printf("Unknown option: %s\n", argv[1]);
++ pfe_command_help();
++ return CMD_RET_FAILURE;
++ }
++ return CMD_RET_SUCCESS;
++}
++
++
++U_BOOT_CMD(
++ pfe, 7, 1, pfe_command,
++ "Performs PFE lib utility functions",
++ "Usage: \n"
++ "pfe <options>"
++);
+diff --git a/drivers/net/Makefile b/drivers/net/Makefile
+index 150470c..c683b8f 100644
+--- a/drivers/net/Makefile
++++ b/drivers/net/Makefile
+@@ -72,3 +72,4 @@ obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
+ obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
+ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
+ obj-$(CONFIG_VSC9953) += vsc9953.o
++obj-$(CONFIG_FSL_PPFE) += pfe_eth/
+diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
+new file mode 100644
+index 0000000..1af837d
+--- /dev/null
++++ b/drivers/net/pfe_eth/Makefile
+@@ -0,0 +1 @@
++obj-y += pfe_eth.o pfe_firmware.o pfe.o pfe_driver.o
+diff --git a/drivers/net/pfe_eth/class_sbl_elf.fw b/drivers/net/pfe_eth/class_sbl_elf.fw
+new file mode 100644
+index 0000000..3745d9a
+--- /dev/null
++++ b/drivers/net/pfe_eth/class_sbl_elf.fw
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+\ No newline at end of file
+diff --git a/drivers/net/pfe_eth/hal.h b/drivers/net/pfe_eth/hal.h
+new file mode 100644
+index 0000000..e795fe6
+--- /dev/null
++++ b/drivers/net/pfe_eth/hal.h
+@@ -0,0 +1,64 @@
++/*
++ * (C) Copyright 2011
++ * Author : Mindspeed Technologes
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ * */
++
++#ifndef _HAL_H_
++#define _HAL_H_
++
++#if defined(CONFIG_PLATFORM_PCI)
++/* For ChipIT */
++
++#include <linux/types.h>
++#include <linux/elf.h>
++#include <linux/errno.h>
++#include <linux/pci.h>
++#include <asm/io.h>
++#include <linux/slab.h>
++#include <linux/firmware.h>
++
++
++#define free(x) kfree(x)
++#define xzalloc(x) kmalloc(x, GFP_DMA)
++#define printf printk
++
++//#define dprint(fmt, arg...) printk(fmt, ##arg)
++#define dprint(fmt, arg...)
++
++#else
++
++#include <linux/types.h>
++#include <elf.h>
++#include <common.h>
++//#include <errno.h>
++#include <asm/byteorder.h>
++#include <miiphy.h>
++#include <malloc.h>
++#include <asm/io.h>
++
++
++#include "pfe_eth.h"
++
++#endif
++
++
++#endif /* _HAL_H_ */
++
+diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
+new file mode 100644
+index 0000000..3b5570a
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe.c
+@@ -0,0 +1,1677 @@
++#include "hal.h"
++#include "pfe/pfe.h"
++
++void *cbus_base_addr;
++void *ddr_base_addr;
++unsigned long ddr_phys_base_addr;
++#if 0
++#define dprintf(fmt, arg...) printf(fmt, ##arg)
++#else
++#define dprintf(fmt, arg...)
++#endif
++static struct pe_info pe[MAX_PE];
++
++/** Initializes the PFE library.
++* Must be called before using any of the library functions.
++*
++* @param[in] cbus_base CBUS virtual base address (as mapped in the host CPU address space)
++* @param[in] ddr_base DDR virtual base address (as mapped in the host CPU address space)
++* @param[in] ddr_phys_base DDR physical base address (as mapped in platform)
++*/
++void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base)
++{
++ cbus_base_addr = cbus_base;
++ ddr_base_addr = ddr_base;
++ ddr_phys_base_addr = ddr_phys_base;
++
++ pe[CLASS0_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(0);
++ pe[CLASS0_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(0);
++ pe[CLASS0_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
++ pe[CLASS0_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS0_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS0_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
++
++ pe[CLASS1_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(1);
++ pe[CLASS1_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(1);
++ pe[CLASS1_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
++ pe[CLASS1_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS1_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS1_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
++
++ pe[CLASS2_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(2);
++ pe[CLASS2_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(2);
++ pe[CLASS2_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
++ pe[CLASS2_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS2_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS2_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
++
++ pe[CLASS3_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(3);
++ pe[CLASS3_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(3);
++ pe[CLASS3_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
++ pe[CLASS3_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS3_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS3_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
++
++#if !defined(CONFIG_PLATFORM_PCI)
++ pe[CLASS4_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(4);
++ pe[CLASS4_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(4);
++ pe[CLASS4_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
++ pe[CLASS4_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS4_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS4_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
++
++ pe[CLASS5_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(5);
++ pe[CLASS5_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(5);
++ pe[CLASS5_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
++ pe[CLASS5_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS5_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS5_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
++#endif
++ pe[TMU0_ID].dmem_base_addr = (u32)TMU_DMEM_BASE_ADDR(0);
++ pe[TMU0_ID].pmem_base_addr = (u32)TMU_IMEM_BASE_ADDR(0);
++ pe[TMU0_ID].pmem_size = (u32)TMU_IMEM_SIZE;
++ pe[TMU0_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
++ pe[TMU0_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
++ pe[TMU0_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
++
++#if !defined(CONFIG_TMU_DUMMY)
++ pe[TMU1_ID].dmem_base_addr = (u32)TMU_DMEM_BASE_ADDR(1);
++ pe[TMU1_ID].pmem_base_addr = (u32)TMU_IMEM_BASE_ADDR(1);
++ pe[TMU1_ID].pmem_size = (u32)TMU_IMEM_SIZE;
++ pe[TMU1_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
++ pe[TMU1_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
++ pe[TMU1_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
++
++#if !defined(CONFIG_LS1012A)
++ pe[TMU2_ID].dmem_base_addr = (u32)TMU_DMEM_BASE_ADDR(2);
++ pe[TMU2_ID].pmem_base_addr = (u32)TMU_IMEM_BASE_ADDR(2);
++ pe[TMU2_ID].pmem_size = (u32)TMU_IMEM_SIZE;
++ pe[TMU2_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
++ pe[TMU2_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
++ pe[TMU2_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
++#endif
++
++ pe[TMU3_ID].dmem_base_addr = (u32)TMU_DMEM_BASE_ADDR(3);
++ pe[TMU3_ID].pmem_base_addr = (u32)TMU_IMEM_BASE_ADDR(3);
++ pe[TMU3_ID].pmem_size = (u32)TMU_IMEM_SIZE;
++ pe[TMU3_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
++ pe[TMU3_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
++ pe[TMU3_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
++#endif
++
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++ pe[UTIL_ID].dmem_base_addr = (u32)UTIL_DMEM_BASE_ADDR;
++ pe[UTIL_ID].mem_access_wdata = (void *)UTIL_MEM_ACCESS_WDATA;
++ pe[UTIL_ID].mem_access_addr = (void *)UTIL_MEM_ACCESS_ADDR;
++ pe[UTIL_ID].mem_access_rdata = (void *)UTIL_MEM_ACCESS_RDATA;
++#endif
++}
++
++
++/** Writes a buffer to PE internal memory from the host
++ * through indirect access registers.
++ *
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] src Buffer source address
++ * @param[in] mem_access_addr DMEM destination address (must be 32bit aligned)
++ * @param[in] len Number of bytes to copy
++ */
++void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned int len)
++{
++ u32 offset = 0, val, addr;
++ unsigned int len32 = len >> 2;
++ int i;
++
++ addr = mem_access_addr | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(0, 4);
++
++ for (i = 0; i < len32; i++, offset += 4, src += 4) {
++ val = *(u32 *)src;
++ writel(cpu_to_be32(val), pe[id].mem_access_wdata);
++ writel(addr + offset, pe[id].mem_access_addr);
++ }
++
++ if ((len = (len & 0x3))) {
++ val = 0;
++
++ addr = (mem_access_addr | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset;
++
++ for (i = 0; i < len; i++, src++)
++ val |= (*(u8 *)src) << (8 * i);
++
++ writel(cpu_to_be32(val), pe[id].mem_access_wdata);
++ writel(addr, pe[id].mem_access_addr);
++ }
++}
++
++/** Writes a buffer to PE internal data memory (DMEM) from the host
++ * through indirect access registers.
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] src Buffer source address
++ * @param[in] dst DMEM destination address (must be 32bit aligned)
++ * @param[in] len Number of bytes to copy
++ */
++void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
++{
++ pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst | PE_MEM_ACCESS_DMEM, src, len);
++}
++
++
++/** Writes a buffer to PE internal program memory (PMEM) from the host
++ * through indirect access registers.
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
++ * @param[in] src Buffer source address
++ * @param[in] dst PMEM destination address (must be 32bit aligned)
++ * @param[in] len Number of bytes to copy
++ */
++void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
++{
++ pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size - 1)) | PE_MEM_ACCESS_IMEM, src, len);
++}
++
++
++/** Reads PE internal program memory (IMEM) from the host
++ * through indirect access registers.
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
++ * @param[in] addr PMEM read address (must be aligned on size)
++ * @param[in] size Number of bytes to read (maximum 4, must not cross 32bit boundaries)
++ * @return the data read (in PE endianess, i.e BE).
++ */
++u32 pe_pmem_read(int id, u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++ u32 mask = 0xffffffff >> ((4 - size) << 3);
++ u32 val;
++
++ addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1)) | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_IMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++ writel(addr, pe[id].mem_access_addr);
++ val = be32_to_cpu(readl(pe[id].mem_access_rdata));
++
++ return (val >> (offset << 3)) & mask;
++}
++
++
++/** Writes PE internal data memory (DMEM) from the host
++ * through indirect access registers.
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] addr DMEM write address (must be aligned on size)
++ * @param[in] val Value to write (in PE endianess, i.e BE)
++ * @param[in] size Number of bytes to write (maximum 4, must not cross 32bit boundaries)
++ */
++void pe_dmem_write(int id, u32 val, u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++
++ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++ /* Indirect access interface is byte swapping data being written */
++ writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata);
++ writel(addr, pe[id].mem_access_addr);
++}
++
++
++/** Reads PE internal data memory (DMEM) from the host
++ * through indirect access registers.
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] addr DMEM read address (must be aligned on size)
++ * @param[in] size Number of bytes to read (maximum 4, must not cross 32bit boundaries)
++ * @return the data read (in PE endianess, i.e BE).
++ */
++u32 pe_dmem_read(int id, u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++ u32 mask = 0xffffffff >> ((4 - size) << 3);
++ u32 val;
++
++ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++ writel(addr, pe[id].mem_access_addr);
++
++ /* Indirect access interface is byte swapping data being read */
++ val = be32_to_cpu(readl(pe[id].mem_access_rdata));
++
++ return (val >> (offset << 3)) & mask;
++}
++
++/** This function is used to write to CLASS internal bus peripherals (ccu, pe-lem) from the host
++* through indirect access registers.
++* @param[in] val value to write
++* @param[in] addr Address to write to (must be aligned on size)
++* @param[in] size Number of bytes to write (1, 2 or 4)
++*
++*/
++void class_bus_write(u32 val, u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++
++ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
++
++ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE | (size << 24);
++
++ writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA);
++ writel(addr, CLASS_BUS_ACCESS_ADDR);
++}
++
++
++/** Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host
++* through indirect access registers.
++* @param[in] addr Address to read from (must be aligned on size)
++* @param[in] size Number of bytes to read (1, 2 or 4)
++* @return the read data
++*
++*/
++u32 class_bus_read(u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++ u32 mask = 0xffffffff >> ((4 - size) << 3);
++ u32 val;
++
++ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
++
++ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24);
++
++ writel(addr, CLASS_BUS_ACCESS_ADDR);
++ val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA));
++
++ return (val >> (offset << 3)) & mask;
++}
++
++/** Writes data to the cluster memory (PE_LMEM)
++* @param[in] dst PE LMEM destination address (must be 32bit aligned)
++* @param[in] src Buffer source address
++* @param[in] len Number of bytes to copy
++*/
++void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len)
++{
++ u32 len32 = len >> 2;
++ int i;
++
++ for (i = 0; i < len32; i++, src += 4, dst += 4)
++ class_bus_write(*(u32 *)src, dst, 4);
++
++ if (len & 0x2)
++ {
++ class_bus_write(*(u16 *)src, dst, 2);
++ src += 2;
++ dst += 2;
++ }
++
++ if (len & 0x1)
++ {
++ class_bus_write(*(u8 *)src, dst, 1);
++ src++;
++ dst++;
++ }
++}
++
++/** Writes value to the cluster memory (PE_LMEM)
++* @param[in] dst PE LMEM destination address (must be 32bit aligned)
++* @param[in] val Value to write
++* @param[in] len Number of bytes to write
++*/
++void class_pe_lmem_memset(u32 dst, int val, unsigned int len)
++{
++ u32 len32 = len >> 2;
++ int i;
++
++ val = val | (val << 8) | (val << 16) | (val << 24);
++
++ for (i = 0; i < len32; i++, dst += 4)
++ class_bus_write(val, dst, 4);
++
++ if (len & 0x2)
++ {
++ class_bus_write(val, dst, 2);
++ dst += 2;
++ }
++
++ if (len & 0x1)
++ {
++ class_bus_write(val, dst, 1);
++ dst++;
++ }
++}
++
++/** Reads data from the cluster memory (PE_LMEM)
++* @param[out] dst pointer to the source buffer data are copied to
++* @param[in] len length in bytes of the amount of data to read from cluster memory
++* @param[in] offset offset in bytes in the cluster memory where data are read from
++*/
++void pe_lmem_read(u32 *dst, u32 len, u32 offset)
++{
++ u32 len32 = len >> 2;
++ int i = 0;
++
++ for (i = 0; i < len32; dst++, i++, offset += 4)
++ *dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, 4);
++
++ /* FIXME we may have an out of bounds access on dst */
++ if (len & 0x03)
++ *dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, (len & 0x03));
++}
++
++/** Writes data to the cluster memory (PE_LMEM)
++* @param[in] src pointer to the source buffer data are copied from
++* @param[in] len length in bytes of the amount of data to write to the cluster memory
++* @param[in] offset offset in bytes in the cluster memory where data are written to
++*/
++void pe_lmem_write(u32 *src, u32 len, u32 offset)
++{
++ u32 len32 = len >> 2;
++ int i = 0;
++
++ for (i = 0; i < len32; src++, i++, offset += 4)
++ class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, 4);
++
++ /* FIXME we may have an out of bounds access on src */
++ if (len & 0x03)
++ class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, (len & 0x03));
++}
++
++/** Writes UTIL program memory (DDR) from the host.
++ *
++ * @param[in] addr Address to write (virtual, must be aligned on size)
++ * @param[in] val Value to write (in PE endianess, i.e BE)
++ * @param[in] size Number of bytes to write (2 or 4)
++ */
++static void util_pmem_write(u32 val, void *addr, u8 size)
++{
++ void *addr64 = (void *)((unsigned long)addr & ~0x7);
++ unsigned long off = 8 - ((unsigned long)addr & 0x7) - size;
++
++ //IMEM should be loaded as a 64bit swapped value in a 64bit aligned location
++ if (size == 4)
++ writel(be32_to_cpu(val), addr64 + off);
++ else
++ writew(be16_to_cpu((u16)val), addr64 + off);
++}
++
++
++/** Writes a buffer to UTIL program memory (DDR) from the host.
++ *
++ * @param[in] dst Address to write (virtual, must be at least 16bit aligned)
++ * @param[in] src Buffer to write (in PE endianess, i.e BE, must have same alignment as dst)
++ * @param[in] len Number of bytes to write (must be at least 16bit aligned)
++ */
++static void util_pmem_memcpy(void *dst, const void *src, unsigned int len)
++{
++ unsigned int len32;
++ int i;
++
++ if ((unsigned long)src & 0x2) {
++ util_pmem_write(*(u16 *)src, dst, 2);
++ src += 2;
++ dst += 2;
++ len -= 2;
++ }
++
++ len32 = len >> 2;
++
++ for (i = 0; i < len32; i++, dst += 4, src += 4)
++ util_pmem_write(*(u32 *)src, dst, 4);
++
++ if (len & 0x2)
++ util_pmem_write(*(u16 *)src, dst, len & 0x2);
++}
++
++
++/** Loads an elf section into pmem
++ * Code needs to be at least 16bit aligned and only PROGBITS sections are supported
++ *
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
++ * @param[in] data pointer to the elf firmware
++ * @param[in] shdr pointer to the elf section header
++ *
++ */
++static int pe_load_pmem_section(int id, const void *data, Elf32_Shdr *shdr)
++{
++ u32 offset = be32_to_cpu(shdr->sh_offset);
++ u32 addr = be32_to_cpu(shdr->sh_addr);
++ u32 size = be32_to_cpu(shdr->sh_size);
++ u32 type = be32_to_cpu(shdr->sh_type);
++
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++ if (id == UTIL_ID)
++ {
++ printf("%s: unsuported pmem section for UTIL\n", __func__);
++ return -1;
++ }
++#endif
++
++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
++ {
++ printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
++ __func__, addr, (unsigned long) data + offset);
++
++ return -1;
++ }
++
++ if (addr & 0x1)
++ {
++ printf("%s: load address(%x) is not 16bit aligned\n", __func__, addr);
++ return -1;
++ }
++
++ if (size & 0x1)
++ {
++ printf("%s: load size(%x) is not 16bit aligned\n", __func__, size);
++ return -1;
++ }
++
++ dprintf("pmem pe%d @%x len %d\n",id, addr, size);
++ switch (type)
++ {
++ case SHT_PROGBITS:
++ pe_pmem_memcpy_to32(id, addr, data + offset, size);
++ break;
++
++ default:
++ printf("%s: unsuported section type(%x)\n", __func__, type);
++ return -1;
++ break;
++ }
++
++ return 0;
++}
++
++
++/** Loads an elf section into dmem
++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0
++ *
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] data pointer to the elf firmware
++ * @param[in] shdr pointer to the elf section header
++ *
++ */
++static int pe_load_dmem_section(int id, const void *data, Elf32_Shdr *shdr)
++{
++ u32 offset = be32_to_cpu(shdr->sh_offset);
++ u32 addr = be32_to_cpu(shdr->sh_addr);
++ u32 size = be32_to_cpu(shdr->sh_size);
++ u32 type = be32_to_cpu(shdr->sh_type);
++ u32 size32 = size >> 2;
++ int i;
++
++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
++ {
++ printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
++ __func__, addr, (unsigned long)data + offset);
++
++ return -1;
++ }
++
++ if (addr & 0x3)
++ {
++ printf("%s: load address(%x) is not 32bit aligned\n", __func__, addr);
++ return -1;
++ }
++
++ switch (type)
++ {
++ case SHT_PROGBITS:
++ dprintf("dmem pe%d @%x len %d\n",id, addr, size);
++ pe_dmem_memcpy_to32(id, addr, data + offset, size);
++ break;
++
++ case SHT_NOBITS:
++ dprintf("dmem zero pe%d @%x len %d\n",id, addr, size);
++ for (i = 0; i < size32; i++, addr += 4)
++ pe_dmem_write(id, 0, addr, 4);
++
++ if (size & 0x3)
++ pe_dmem_write(id, 0, addr, size & 0x3);
++
++ break;
++
++ default:
++ printf("%s: unsuported section type(%x)\n", __func__, type);
++ return -1;
++ break;
++ }
++
++ return 0;
++}
++
++
++/** Loads an elf section into DDR
++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0
++ *
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] data pointer to the elf firmware
++ * @param[in] shdr pointer to the elf section header
++ *
++ */
++static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr)
++{
++ u32 offset = be32_to_cpu(shdr->sh_offset);
++ u32 addr = be32_to_cpu(shdr->sh_addr);
++ u32 size = be32_to_cpu(shdr->sh_size);
++ u32 type = be32_to_cpu(shdr->sh_type);
++ u32 flags = be32_to_cpu(shdr->sh_flags);
++
++ switch (type)
++ {
++ case SHT_PROGBITS:
++ dprintf("ddr pe%d @%x len %d\n",id, addr, size);
++ if (flags & SHF_EXECINSTR)
++ {
++ if (id <= CLASS_MAX_ID)
++ {
++ /* DO the loading only once in DDR */
++ if (id == CLASS0_ID)
++ {
++ dprintf("%s: load address(%x) and elf file address(%lx) rcvd\n", __func__, addr, (unsigned long)data + offset);
++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
++ {
++ printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
++ __func__, addr, (unsigned long)data + offset);
++
++ return -1;
++ }
++
++ if (addr & 0x1)
++ {
++ printf("%s: load address(%x) is not 16bit aligned\n", __func__, addr);
++ return -1;
++ }
++
++ if (size & 0x1)
++ {
++ printf("%s: load length(%x) is not 16bit aligned\n", __func__, size);
++ return -1;
++ }
++
++ memcpy(DDR_PFE_TO_VIRT(addr), data + offset, size);
++ }
++ }
++
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++ else if (id == UTIL_ID)
++ {
++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
++ {
++ printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
++ __func__, addr, (unsigned long)data + offset);
++
++ return -1;
++ }
++
++ if (addr & 0x1)
++ {
++ printf("%s: load address(%x) is not 16bit aligned\n", __func__, addr);
++ return -1;
++ }
++
++ if (size & 0x1)
++ {
++ printf("%s: load length(%x) is not 16bit aligned\n", __func__, size);
++ return -1;
++ }
++
++ util_pmem_memcpy((void *)DDR_PFE_TO_VIRT(addr), data + offset, size);
++ }
++#endif
++ else
++ {
++ printf("%s: unsuported ddr section type(%x) for PE(%d)\n", __func__, type, id);
++ return -1;
++ }
++
++ }
++ else
++ {
++ memcpy(DDR_PFE_TO_VIRT(addr), data + offset, size);
++ }
++
++ break;
++
++ case SHT_NOBITS:
++ dprintf("ddr zero pe%d @%x len %d\n",id, addr, size);
++ memset((void *)DDR_PFE_TO_VIRT(addr), 0, size);
++
++ break;
++
++ default:
++ printf("%s: unsuported section type(%x)\n", __func__, type);
++ return -1;
++ break;
++ }
++
++ return 0;
++}
++
++/** Loads an elf section into pe lmem
++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0
++ *
++ * @param[in] id PE identification (CLASS0_ID,..., CLASS5_ID)
++ * @param[in] data pointer to the elf firmware
++ * @param[in] shdr pointer to the elf section header
++ *
++ */
++static int pe_load_pe_lmem_section(int id, const void *data, Elf32_Shdr *shdr)
++{
++ u32 offset = be32_to_cpu(shdr->sh_offset);
++ u32 addr = be32_to_cpu(shdr->sh_addr);
++ u32 size = be32_to_cpu(shdr->sh_size);
++ u32 type = be32_to_cpu(shdr->sh_type);
++
++ if (id > CLASS_MAX_ID)
++ {
++ printf("%s: unsuported pe-lmem section type(%x) for PE(%d)\n", __func__, type, id);
++ return -1;
++ }
++
++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
++ {
++ printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
++ __func__, addr, (unsigned long)data + offset);
++
++ return -1;
++ }
++
++ if (addr & 0x3)
++ {
++ printf("%s: load address(%x) is not 32bit aligned\n", __func__, addr);
++ return -1;
++ }
++ dprintf("lmem pe%d @%x len %d\n",id, addr, size);
++ switch (type)
++ {
++ case SHT_PROGBITS:
++ class_pe_lmem_memcpy_to32(addr, data + offset, size);
++ break;
++
++ case SHT_NOBITS:
++ class_pe_lmem_memset(addr, 0, size);
++ break;
++
++ default:
++ printf("%s: unsuported section type(%x)\n", __func__, type);
++ return -1;
++ break;
++ }
++
++ return 0;
++}
++
++
++/** Loads an elf section into a PE
++ * For now only supports loading a section to dmem (all PE's), pmem (class and tmu PE's),
++ * DDDR (util PE code)
++ *
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] data pointer to the elf firmware
++ * @param[in] shdr pointer to the elf section header
++ *
++ */
++int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr)
++{
++ u32 addr = be32_to_cpu(shdr->sh_addr);
++ u32 size = be32_to_cpu(shdr->sh_size);
++
++ //printf(".");
++ if (IS_DMEM(addr, size))
++ return pe_load_dmem_section(id, data, shdr);
++ else if (IS_PMEM(addr, size))
++ return pe_load_pmem_section(id, data, shdr);
++ else if (IS_PFE_LMEM(addr, size))
++ return 0; /* FIXME */
++ else if (IS_PHYS_DDR(addr, size))
++ return pe_load_ddr_section(id, data, shdr);
++ else if (IS_PE_LMEM(addr, size))
++ return pe_load_pe_lmem_section(id, data, shdr);
++ else {
++ printf("%s: unsuported memory range(%x)\n", __func__, addr);
++ /*FIXME this should be remove after testing UTIL from 0x20000 */
++ //printf("loading DDR section \n");
++ //return pe_load_ddr_section(id, data, shdr);
++// return -1;
++ }
++
++ return 0;
++}
++
++/** This function is used to write to UTIL internal bus peripherals from the host
++* through indirect access registers.
++* @param[in] val 32bits value to write
++* @param[in] addr Address to write to
++* @param[in] size Number of bytes to write
++*
++*/
++void util_bus_write(u32 val, u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++ u32 access_addr;
++
++ access_addr = ((addr & ~0x3) & CLASS_BUS_ACCESS_ADDR_MASK) | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++// writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
++
++ writel(cpu_to_be32(val << (offset << 3)), UTIL_BUS_ACCESS_WDATA);
++ writel(access_addr, UTIL_BUS_ACCESS_ADDR);
++}
++
++
++/** Reads from UTIL internal bus peripherals from the host
++* through indirect access registers.
++* @param[in] addr Address to read from
++* @param[in] size Number of bytes to read
++* @return the read data
++*
++*/
++u32 util_bus_read(u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++ u32 mask = 0xffffffff >> ((4 - size) << 3);
++ u32 access_addr, val;
++
++ access_addr = ((addr & ~0x3) & CLASS_BUS_ACCESS_ADDR_MASK) | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++// writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
++
++ writel(access_addr, UTIL_BUS_ACCESS_ADDR);
++ val = be32_to_cpu(readl(UTIL_BUS_ACCESS_RDATA));
++
++ return (val >> (offset << 3)) & mask;
++}
++
++
++
++/**************************** BMU ***************************/
++
++/** Initializes a BMU block.
++* @param[in] base BMU block base address
++* @param[in] cfg BMU configuration
++*/
++void bmu_init(void *base, BMU_CFG *cfg)
++{
++
++ bmu_disable(base);
++
++ bmu_set_config(base, cfg);
++
++ bmu_reset(base);
++}
++
++/** Resets a BMU block.
++* @param[in] base BMU block base address
++*/
++void bmu_reset(void *base)
++{
++ writel(CORE_SW_RESET, base + BMU_CTRL);
++
++ /* Wait for self clear */
++ while (readl(base + BMU_CTRL) & CORE_SW_RESET) ;
++}
++
++/** Enabled a BMU block.
++* @param[in] base BMU block base address
++*/
++void bmu_enable(void *base)
++{
++ writel (CORE_ENABLE, base + BMU_CTRL);
++}
++
++/** Disables a BMU block.
++* @param[in] base BMU block base address
++*/
++void bmu_disable(void *base)
++{
++ writel (CORE_DISABLE, base + BMU_CTRL);
++}
++
++/** Sets the configuration of a BMU block.
++* @param[in] base BMU block base address
++* @param[in] cfg BMU configuration
++*/
++void bmu_set_config(void *base, BMU_CFG *cfg)
++{
++ writel (cfg->baseaddr, base + BMU_UCAST_BASE_ADDR);
++ writel (cfg->count & 0xffff, base + BMU_UCAST_CONFIG);
++ writel (cfg->size & 0xffff, base + BMU_BUF_SIZE);
++// writel (BMU1_THRES_CNT, base + BMU_THRES);
++
++ /* Interrupts are never used */
++// writel (0x0, base + BMU_INT_SRC);
++ writel (0x0, base + BMU_INT_ENABLE);
++}
++
++
++#if 0 //These are LS1012A functions
++/**************************** GEMAC ***************************/
++
++/** GEMAC block initialization.
++* @param[in] base GEMAC base address (GEMAC0, GEMAC1, GEMAC2)
++* @param[in] cfg GEMAC configuration
++*/
++void gemac_init(void *base, void *cfg)
++{
++ gemac_set_config(base, cfg);
++ gemac_set_bus_width(base, 64);
++}
++
++/** GEMAC set speed.
++* @param[in] base GEMAC base address
++* @param[in] speed GEMAC speed (10, 100 or 1000 Mbps)
++*/
++void gemac_set_speed(void *base, MAC_SPEED gem_speed)
++{
++ u32 val = readl(base + EMAC_NETWORK_CONFIG);
++
++ val = val & ~EMAC_SPEED_MASK;
++
++ switch (gem_speed)
++ {
++ case SPEED_10M:
++ val &= (~EMAC_PCS_ENABLE);
++ break;
++
++ case SPEED_100M:
++ val = val | EMAC_SPEED_100;
++ val &= (~EMAC_PCS_ENABLE);
++ break;
++
++ case SPEED_1000M:
++ val = val | EMAC_SPEED_1000;
++ val &= (~EMAC_PCS_ENABLE);
++ break;
++
++ case SPEED_1000M_PCS:
++ val = val | EMAC_SPEED_1000;
++ val |= EMAC_PCS_ENABLE;
++ break;
++
++ default:
++ val = val | EMAC_SPEED_100;
++ val &= (~EMAC_PCS_ENABLE);
++ break;
++ }
++
++ writel (val, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC set duplex.
++* @param[in] base GEMAC base address
++* @param[in] duplex GEMAC duplex mode (Full, Half)
++*/
++void gemac_set_duplex(void *base, int duplex)
++{
++ u32 val = readl(base + EMAC_NETWORK_CONFIG);
++
++ if (duplex == DUPLEX_HALF)
++ val = (val & ~EMAC_DUPLEX_MASK) | EMAC_HALF_DUP;
++ else
++ val = (val & ~EMAC_DUPLEX_MASK) | EMAC_FULL_DUP;
++
++ writel (val, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC set mode.
++* @param[in] base GEMAC base address
++* @param[in] mode GEMAC operation mode (MII, RMII, RGMII, SGMII)
++*/
++void gemac_set_mode(void *base, int mode)
++{
++ switch (mode)
++ {
++ case GMII:
++ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_GMII_MODE_ENABLE, base + EMAC_CONTROL);
++ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
++ break;
++
++ case RGMII:
++ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_RGMII_MODE_ENABLE, base + EMAC_CONTROL);
++ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
++ break;
++
++ case RMII:
++ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_RMII_MODE_ENABLE, base + EMAC_CONTROL);
++ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
++ break;
++
++ case MII:
++ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_MII_MODE_ENABLE, base + EMAC_CONTROL);
++ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
++ break;
++
++ case SGMII:
++ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | (EMAC_RMII_MODE_DISABLE | EMAC_RGMII_MODE_DISABLE), base + EMAC_CONTROL);
++ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_SGMII_MODE_ENABLE, base + EMAC_NETWORK_CONFIG);
++ break;
++
++ default:
++ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_MII_MODE_ENABLE, base + EMAC_CONTROL);
++ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
++ break;
++ }
++}
++
++/** GEMAC Enable MDIO: Activate the Management interface. This is required to program the PHY
++ * @param[in] base GEMAC base address
++ */
++void gemac_enable_mdio(void *base)
++{
++ u32 data;
++
++ data = readl(base + EMAC_NETWORK_CONTROL);
++ data |= EMAC_MDIO_EN;
++ writel(data, base + EMAC_NETWORK_CONTROL);
++}
++
++/** GEMAC Disable MDIO: Disable the Management interface.
++ * @param[in] base GEMAC base address
++ */
++void gemac_disable_mdio(void *base)
++{
++ u32 data;
++
++ data = readl(base + EMAC_NETWORK_CONTROL);
++ data &= ~EMAC_MDIO_EN;
++ writel(data, base + EMAC_NETWORK_CONTROL);
++}
++
++/** GEMAC Set MDC clock division
++ * @param[in] base GEMAC base address
++ * @param[in] base MDC divider value
++ */
++void gemac_set_mdc_div(void *base, MAC_MDC_DIV gem_mdcdiv)
++{
++ u32 data;
++
++ data = readl(base + EMAC_NETWORK_CONFIG);
++ data &= ~(MDC_DIV_MASK << MDC_DIV_SHIFT);
++ data |= (gem_mdcdiv & MDC_DIV_MASK) << MDC_DIV_SHIFT;
++ writel(data, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC reset function.
++* @param[in] base GEMAC base address
++*/
++void gemac_reset(void *base)
++{
++}
++
++/** GEMAC enable function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONTROL) | EMAC_TX_ENABLE | EMAC_RX_ENABLE, base + EMAC_NETWORK_CONTROL);
++}
++
++/** GEMAC disable function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONTROL) & ~(EMAC_TX_ENABLE | EMAC_RX_ENABLE), base + EMAC_NETWORK_CONTROL);
++}
++
++/** GEMAC set mac address configuration.
++* @param[in] base GEMAC base address
++* @param[in] addr MAC address to be configured
++*/
++void gemac_set_address(void *base, SPEC_ADDR *addr)
++{
++ writel(addr->one.bottom, base + EMAC_SPEC1_ADD_BOT);
++ writel(addr->one.top, base + EMAC_SPEC1_ADD_TOP);
++ writel(addr->two.bottom, base + EMAC_SPEC2_ADD_BOT);
++ writel(addr->two.top, base + EMAC_SPEC2_ADD_TOP);
++ writel(addr->three.bottom, base + EMAC_SPEC3_ADD_BOT);
++ writel(addr->three.top, base + EMAC_SPEC3_ADD_TOP);
++ writel(addr->four.bottom, base + EMAC_SPEC4_ADD_BOT);
++ writel(addr->four.top, base + EMAC_SPEC4_ADD_TOP);
++}
++
++/** GEMAC get mac address configuration.
++* @param[in] base GEMAC base address
++*
++* @return MAC addresses configured
++*/
++SPEC_ADDR gemac_get_address(void *base)
++{
++ SPEC_ADDR addr;
++
++ addr.one.bottom = readl(base + EMAC_SPEC1_ADD_BOT);
++ addr.one.top = readl(base + EMAC_SPEC1_ADD_TOP);
++ addr.two.bottom = readl(base + EMAC_SPEC2_ADD_BOT);
++ addr.two.top = readl(base + EMAC_SPEC2_ADD_TOP);
++ addr.three.bottom = readl(base + EMAC_SPEC3_ADD_BOT);
++ addr.three.top = readl(base + EMAC_SPEC3_ADD_TOP);
++ addr.four.bottom = readl(base + EMAC_SPEC4_ADD_BOT);
++ addr.four.top = readl(base + EMAC_SPEC4_ADD_TOP);
++
++ return addr;
++}
++
++/** GEMAC set specific local addresses of the MAC.
++* Rather than setting up all four specific addresses, this function sets them up individually.
++*
++* @param[in] base GEMAC base address
++* @param[in] addr MAC address to be configured
++*/
++void gemac_set_laddr1(void *base, MAC_ADDR *address)
++{
++ writel(address->bottom, base + EMAC_SPEC1_ADD_BOT);
++ writel(address->top, base + EMAC_SPEC1_ADD_TOP);
++}
++
++
++void gemac_set_laddr2(void *base, MAC_ADDR *address)
++{
++ writel(address->bottom, base + EMAC_SPEC2_ADD_BOT);
++ writel(address->top, base + EMAC_SPEC2_ADD_TOP);
++}
++
++
++void gemac_set_laddr3(void *base, MAC_ADDR *address)
++{
++ writel(address->bottom, base + EMAC_SPEC3_ADD_BOT);
++ writel(address->top, base + EMAC_SPEC3_ADD_TOP);
++}
++
++
++void gemac_set_laddr4(void *base, MAC_ADDR *address)
++{
++ writel(address->bottom, base + EMAC_SPEC4_ADD_BOT);
++ writel(address->top, base + EMAC_SPEC4_ADD_TOP);
++}
++
++void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index)
++{
++ if (entry_index < 5)
++ {
++ writel(address->bottom, base + (entry_index * 8) + EMAC_SPEC1_ADD_BOT);
++ writel(address->top, base + (entry_index * 8) + EMAC_SPEC1_ADD_TOP);
++ }
++ else
++ {
++ writel(address->bottom, base + ((entry_index - 5) * 8) + EMAC_SPEC5_ADD_BOT);
++ writel(address->top, base + ((entry_index - 5) * 8) + EMAC_SPEC5_ADD_TOP);
++ }
++}
++
++/** Get specific local addresses of the MAC.
++* This allows returning of a single specific address stored in the MAC.
++* @param[in] base GEMAC base address
++*
++* @return Specific MAC address 1
++*
++*/
++MAC_ADDR gem_get_laddr1(void *base)
++{
++ MAC_ADDR addr;
++ addr.bottom = readl(base + EMAC_SPEC1_ADD_BOT);
++ addr.top = readl(base + EMAC_SPEC1_ADD_TOP);
++ return addr;
++}
++
++
++MAC_ADDR gem_get_laddr2(void *base)
++{
++ MAC_ADDR addr;
++ addr.bottom = readl(base + EMAC_SPEC2_ADD_BOT);
++ addr.top = readl(base + EMAC_SPEC2_ADD_TOP);
++ return addr;
++}
++
++
++MAC_ADDR gem_get_laddr3(void *base)
++{
++ MAC_ADDR addr;
++ addr.bottom = readl(base + EMAC_SPEC3_ADD_BOT);
++ addr.top = readl(base + EMAC_SPEC3_ADD_TOP);
++ return addr;
++}
++
++
++MAC_ADDR gem_get_laddr4(void *base)
++{
++ MAC_ADDR addr;
++ addr.bottom = readl(base + EMAC_SPEC4_ADD_BOT);
++ addr.top = readl(base + EMAC_SPEC4_ADD_TOP);
++ return addr;
++}
++
++
++MAC_ADDR gem_get_laddrN(void *base, unsigned int entry_index)
++{
++ MAC_ADDR addr;
++
++ if (entry_index < 5)
++ {
++ addr.bottom = readl(base + (entry_index * 8) + EMAC_SPEC1_ADD_BOT);
++ addr.top = readl(base + (entry_index * 8) + EMAC_SPEC1_ADD_TOP);
++ }
++ else
++ {
++ addr.bottom = readl(base + ((entry_index - 5) * 8) + EMAC_SPEC5_ADD_BOT);
++ addr.top = readl(base + ((entry_index - 5) * 8) + EMAC_SPEC5_ADD_TOP);
++ }
++
++ return addr;
++}
++
++/** GEMAC allow frames
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_copy_all(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) & EMAC_ENABLE_COPY_ALL, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC do not allow frames
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_copy_all(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_COPY_ALL, base + EMAC_NETWORK_CONFIG);
++}
++
++
++
++/** GEMAC allow broadcast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_allow_broadcast(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_NO_BROADCAST, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC no broadcast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_no_broadcast(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_NO_BROADCAST, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC enable unicast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_unicast(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_UNICAST, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC disable unicast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_unicast(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_UNICAST, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC enable multicast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_multicast(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_MULTICAST, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC disable multicast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_multicast(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_MULTICAST, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC enable fcs rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_fcs_rx(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_FCS_RX, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC disable fcs rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_fcs_rx(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_FCS_RX, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC enable 1536 rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_1536_rx(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_1536_RX, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC disable 1536 rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_1536_rx(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_1536_RX, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC enable pause rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_pause_rx(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_PAUSE_RX, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC disable pause rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_pause_rx(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_PAUSE_RX, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC enable rx checksum offload function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_rx_checksum_offload(void *base)
++{
++ writel(readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_CHKSUM_RX, base + EMAC_NETWORK_CONFIG);
++ writel(readl(CLASS_L4_CHKSUM_ADDR) | IPV4_CHKSUM_DROP, CLASS_L4_CHKSUM_ADDR);
++}
++
++/** GEMAC disable rx checksum offload function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_rx_checksum_offload(void *base)
++{
++ writel(readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_CHKSUM_RX, base + EMAC_NETWORK_CONFIG);
++ writel(readl(CLASS_L4_CHKSUM_ADDR) & ~IPV4_CHKSUM_DROP, CLASS_L4_CHKSUM_ADDR);
++}
++
++/** Sets Gemac bus width to 64bit
++ * @param[in] base GEMAC base address
++ * @param[in] width gemac bus width to be set possible values are 32/64/128
++ * */
++void gemac_set_bus_width(void *base, int width)
++{
++ u32 val = readl(base + EMAC_NETWORK_CONFIG);
++ switch(width)
++ {
++ case 32:
++ val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_32;
++ case 128:
++ val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_128;
++ case 64:
++ default:
++ val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_64;
++
++ }
++ writel (val, base + EMAC_NETWORK_CONFIG);
++}
++
++/** Sets Gemac configuration.
++* @param[in] base GEMAC base address
++* @param[in] cfg GEMAC configuration
++*/
++void gemac_set_config(void *base, GEMAC_CFG *cfg)
++{
++ gemac_set_mode(base, cfg->mode);
++
++ gemac_set_speed(base, cfg->speed);
++
++ gemac_set_duplex(base,cfg->duplex);
++}
++#endif
++
++/**************************** GPI ***************************/
++
++/** Initializes a GPI block.
++* @param[in] base GPI base address
++* @param[in] cfg GPI configuration
++*/
++void gpi_init(void *base, GPI_CFG *cfg)
++{
++ gpi_reset(base);
++
++ gpi_disable(base);
++
++ gpi_set_config(base, cfg);
++}
++
++/** Resets a GPI block.
++* @param[in] base GPI base address
++*/
++void gpi_reset(void *base)
++{
++ writel (CORE_SW_RESET, base + GPI_CTRL);
++}
++
++/** Enables a GPI block.
++* @param[in] base GPI base address
++*/
++void gpi_enable(void *base)
++{
++ writel (CORE_ENABLE, base + GPI_CTRL);
++}
++
++/** Disables a GPI block.
++* @param[in] base GPI base address
++*/
++void gpi_disable(void *base)
++{
++ writel (CORE_DISABLE, base + GPI_CTRL);
++}
++
++
++/** Sets the configuration of a GPI block.
++* @param[in] base GPI base address
++* @param[in] cfg GPI configuration
++*/
++void gpi_set_config(void *base, GPI_CFG *cfg)
++{
++ writel (CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), base + GPI_LMEM_ALLOC_ADDR);
++ writel (CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL), base + GPI_LMEM_FREE_ADDR);
++ writel (CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL), base + GPI_DDR_ALLOC_ADDR);
++ writel (CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), base + GPI_DDR_FREE_ADDR);
++ writel (CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR);
++ writel (DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET);
++ writel (LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET);
++ writel (0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET);
++ writel (0, base + GPI_DDR_SEC_BUF_DATA_OFFSET);
++ writel ((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, base + GPI_HDR_SIZE);
++ writel ((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE, base + GPI_BUF_SIZE);
++
++ writel (((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) | GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG);
++ writel (cfg->tmlf_txthres, base + GPI_TMLF_TX);
++ writel (cfg->aseq_len, base + GPI_DTX_ASEQ);
++}
++
++/**************************** CLASSIFIER ***************************/
++
++/** Initializes CLASSIFIER block.
++* @param[in] cfg CLASSIFIER configuration
++*/
++void class_init(CLASS_CFG *cfg)
++{
++ class_reset();
++
++ class_disable();
++
++ class_set_config(cfg);
++}
++
++/** Resets CLASSIFIER block.
++*
++*/
++void class_reset(void)
++{
++ writel(CORE_SW_RESET, CLASS_TX_CTRL);
++}
++
++/** Enables all CLASS-PE's cores.
++*
++*/
++void class_enable(void)
++{
++ writel(CORE_ENABLE, CLASS_TX_CTRL);
++}
++
++/** Disables all CLASS-PE's cores.
++*
++*/
++void class_disable(void)
++{
++ writel(CORE_DISABLE, CLASS_TX_CTRL);
++}
++
++/** Sets the configuration of the CLASSIFIER block.
++* @param[in] cfg CLASSIFIER configuration
++*/
++void class_set_config(CLASS_CFG *cfg)
++{
++ if (PLL_CLK_EN == 0)
++ writel(0x0, CLASS_PE_SYS_CLK_RATIO); // Clock ratio: for 1:1 the value is 0
++ else
++ writel(0x1, CLASS_PE_SYS_CLK_RATIO); // Clock ratio: for 1:2 the value is 1
++
++ writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, CLASS_HDR_SIZE);
++ writel(LMEM_BUF_SIZE, CLASS_LMEM_BUF_SIZE);
++ writel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) | CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits), CLASS_ROUTE_HASH_ENTRY_SIZE);
++ writel(HASH_CRC_PORT_IP | QB2BUS_LE, CLASS_ROUTE_MULTI);
++
++ writel(cfg->route_table_baseaddr, CLASS_ROUTE_TABLE_BASE);
++ memset((void *)DDR_PFE_TO_VIRT(cfg->route_table_baseaddr), 0, ROUTE_TABLE_SIZE);
++
++ writel(CLASS_PE0_RO_DM_ADDR0_VAL, CLASS_PE0_RO_DM_ADDR0);
++ writel(CLASS_PE0_RO_DM_ADDR1_VAL, CLASS_PE0_RO_DM_ADDR1);
++ writel(CLASS_PE0_QB_DM_ADDR0_VAL, CLASS_PE0_QB_DM_ADDR0);
++ writel(CLASS_PE0_QB_DM_ADDR1_VAL, CLASS_PE0_QB_DM_ADDR1);
++ writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR), CLASS_TM_INQ_ADDR);
++
++ writel(23, CLASS_AFULL_THRES);
++ writel(23, CLASS_TSQ_FIFO_THRES);
++
++ writel(24, CLASS_MAX_BUF_CNT);
++ writel(24, CLASS_TSQ_MAX_CNT);
++ //writel(1, CLASS_USE_TMU_INQ);
++}
++
++/**************************** TMU ***************************/
++
++void tmu_reset(void)
++{
++ writel(SW_RESET, TMU_CTRL);
++}
++
++/** Initializes TMU block.
++* @param[in] cfg TMU configuration
++*/
++void tmu_init(TMU_CFG *cfg)
++{
++ int q, phyno;
++
++ /* keep in soft reset */
++ writel(SW_RESET, TMU_CTRL);
++
++ /* enable EMAC PHY ports */
++ writel(0x3, TMU_SYS_GENERIC_CONTROL);
++
++ writel(750, TMU_INQ_WATERMARK);
++ writel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR + GPI_INQ_PKTPTR), TMU_PHY0_INQ_ADDR);
++ writel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR + GPI_INQ_PKTPTR), TMU_PHY1_INQ_ADDR);
++#if !defined(CONFIG_LS1012A)
++ writel(CBUS_VIRT_TO_PFE(EGPI3_BASE_ADDR + GPI_INQ_PKTPTR), TMU_PHY2_INQ_ADDR);
++#endif
++ writel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR + GPI_INQ_PKTPTR), TMU_PHY3_INQ_ADDR);
++ writel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR), TMU_PHY4_INQ_ADDR);
++ writel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR), TMU_PHY5_INQ_ADDR);
++ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), TMU_BMU_INQ_ADDR);
++
++ writel(0x3FF, TMU_TDQ0_SCH_CTRL); // enabling all 10 schedulers [9:0] of each TDQ
++ writel(0x3FF, TMU_TDQ1_SCH_CTRL);
++#if !defined(CONFIG_LS1012A)
++ writel(0x3FF, TMU_TDQ2_SCH_CTRL);
++#endif
++ writel(0x3FF, TMU_TDQ3_SCH_CTRL);
++
++
++ if (PLL_CLK_EN == 0)
++ writel(0x0, TMU_PE_SYS_CLK_RATIO); // Clock ratio: for 1:1 the value is 0
++ else
++ writel(0x1, TMU_PE_SYS_CLK_RATIO); // Clock ratio: for 1:2 the value is 1
++
++ //printf("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
++ writel(cfg->llm_base_addr, TMU_LLM_BASE_ADDR); // Extra packet pointers will be stored from this address onwards
++
++ //printf("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
++ writel(cfg->llm_queue_len, TMU_LLM_QUE_LEN);
++ writel(5, TMU_TDQ_IIFG_CFG);
++ writel(DDR_BUF_SIZE, TMU_BMU_BUF_SIZE);
++
++ writel(0x0, TMU_CTRL);
++
++ /* MEM init */
++ //printf("%s: mem init\n", __func__);
++ writel(MEM_INIT, TMU_CTRL);
++
++ while(!(readl(TMU_CTRL) & MEM_INIT_DONE))
++ ;
++
++ /* LLM init */
++ //printf("%s: lmem init\n", __func__);
++ writel(LLM_INIT, TMU_CTRL);
++
++ while(!(readl(TMU_CTRL) & LLM_INIT_DONE))
++ ;
++
++ // set up each queue for tail drop
++ for (phyno = 0; phyno < 4; phyno++)
++ {
++#if !defined(CONFIG_LS1012A)
++ if(phyno = 2) continue;
++#endif
++ for (q = 0; q < 16; q++)
++ {
++ u32 qmax;
++ writel((phyno << 8) | q, TMU_TEQ_CTRL);
++ writel(1 << 22, TMU_TEQ_QCFG);
++ qmax = ((phyno == 3) || (q < 8)) ? 255 : 127;
++ writel(qmax << 18, TMU_TEQ_HW_PROB_CFG2);
++ writel(qmax >> 14, TMU_TEQ_HW_PROB_CFG3);
++ }
++ }
++ writel(0x05, TMU_TEQ_DISABLE_DROPCHK);
++ writel(0, TMU_CTRL);
++}
++
++/** Enables TMU-PE cores.
++* @param[in] pe_mask TMU PE mask
++*/
++void tmu_enable(u32 pe_mask)
++{
++ writel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL);
++}
++
++/** Disables TMU cores.
++* @param[in] pe_mask TMU PE mask
++*/
++void tmu_disable(u32 pe_mask)
++{
++ writel(readl(TMU_TX_CTRL) & ~(pe_mask & 0xF), TMU_TX_CTRL);
++}
++
++/**************************** UTIL ***************************/
++
++/** Resets UTIL block.
++*/
++void util_reset(void)
++{
++ writel(CORE_SW_RESET, UTIL_TX_CTRL);
++}
++
++/** Initializes UTIL block.
++* @param[in] cfg UTIL configuration
++*/
++void util_init(UTIL_CFG *cfg)
++{
++
++ //writel(0x1, UTIL_MISC_REG);
++
++ if (PLL_CLK_EN == 0)
++ writel(0x0, UTIL_PE_SYS_CLK_RATIO); // Clock ratio: for 1:1 the value is 0
++ else
++ writel(0x1, UTIL_PE_SYS_CLK_RATIO); // Clock ratio: for 1:2 the value is 1
++}
++
++/** Enables UTIL-PE core.
++*
++*/
++void util_enable(void)
++{
++ writel(CORE_ENABLE, UTIL_TX_CTRL);
++}
++
++/** Disables UTIL-PE core.
++*
++*/
++void util_disable(void)
++{
++ writel(CORE_DISABLE, UTIL_TX_CTRL);
++}
++
++#if 0
++/** GEMAC PHY Statistics - This function return address of the first statistics register
++* @param[in] base GEMAC base address
++*/
++unsigned int * gemac_get_stats(void *base)
++{
++ return (unsigned int *)(base + EMAC_OCT_TX_BOT);
++}
++#endif
++
++/**************************** HIF ***************************/
++
++/** Initializes HIF no copy block.
++*
++*/
++void hif_nocpy_init(void)
++{
++ writel(4, HIF_NOCPY_TX_PORT_NO);
++ writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), HIF_NOCPY_LMEM_ALLOC_ADDR);
++ writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), HIF_NOCPY_CLASS_ADDR);
++ writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR), HIF_NOCPY_TMU_PORT0_ADDR);
++}
++
++/** Initializes HIF copy block.
++*
++*/
++void hif_init(void)
++{
++ /*Initialize HIF registers*/
++ writel(HIF_RX_POLL_CTRL_CYCLE<<16|HIF_TX_POLL_CTRL_CYCLE, HIF_POLL_CTRL);
++}
++
++/** Enable hif tx DMA and interrupt
++*
++*/
++void hif_tx_enable(void)
++{
++ /*TODO not sure poll_cntrl_en is required or not */
++ writel( HIF_CTRL_DMA_EN, HIF_TX_CTRL);
++ //writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN), HIF_INT_ENABLE);
++}
++
++/** Disable hif tx DMA and interrupt
++*
++*/
++void hif_tx_disable(void)
++{
++ u32 hif_int;
++
++ writel(0, HIF_TX_CTRL);
++
++ hif_int = readl(HIF_INT_ENABLE);
++ hif_int &= HIF_TXPKT_INT_EN;
++ writel(hif_int, HIF_INT_ENABLE);
++}
++
++/** Enable hif rx DMA and interrupt
++*
++*/
++void hif_rx_enable(void)
++{
++ /*TODO not sure poll_cntrl_en is required or not */
++ writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
++ //writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN), HIF_INT_ENABLE);
++}
++
++/** Disable hif rx DMA and interrupt
++*
++*/
++void hif_rx_disable(void)
++{
++ u32 hif_int;
++
++ writel(0, HIF_RX_CTRL);
++
++ hif_int = readl(HIF_INT_ENABLE);
++ hif_int &= HIF_RXPKT_INT_EN;
++ writel(hif_int, HIF_INT_ENABLE);
++
++}
+diff --git a/drivers/net/pfe_eth/pfe/cbus.h b/drivers/net/pfe_eth/pfe/cbus.h
+new file mode 100644
+index 0000000..778fe45
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/cbus.h
+@@ -0,0 +1,74 @@
++#ifndef _CBUS_H_
++#define _CBUS_H_
++
++#define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000)
++#define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000)
++#define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000)
++#define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000)
++#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000)
++#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000)
++#define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000) /* FIXME not documented */
++#define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000) /* FIXME not documented */
++#define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000)
++#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000)
++#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000)
++#define LMEM_SIZE 0x10000
++#define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE)
++#define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000)
++#define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000)
++#if !defined(CONFIG_LS1012A)
++#define EMAC3_BASE_ADDR (CBUS_BASE_ADDR + 0x330000)
++#define EGPI3_BASE_ADDR (CBUS_BASE_ADDR + 0x340000)
++#endif
++#define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000)
++#define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000)
++#define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000)
++
++#define IS_LMEM(addr, len) (((unsigned long)(addr) >= LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= LMEM_END))
++
++/**
++* \defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR
++* XXX_MEM_ACCESS_ADDR register bit definitions.
++* @{
++*/
++#define PE_MEM_ACCESS_WRITE (1<<31) /**< Internal Memory Write. */
++#define PE_MEM_ACCESS_READ (0<<31) /**< Internal Memory Read. */
++#define PE_MEM_ACCESS_IMEM (1<<15)
++#define PE_MEM_ACCESS_DMEM (1<<16)
++#define PE_MEM_ACCESS_BYTE_ENABLE(offset,size) (((((1 << (size)) - 1) << (4 - (offset) - (size))) & 0xf) << 24) /**< Byte Enables of the Internal memory access. These are interpred in BE */
++// @}
++#include "cbus/emac.h"
++#include "cbus/gpi.h"
++#include "cbus/bmu.h"
++#include "cbus/hif.h"
++#include "cbus/tmu_csr.h"
++#include "cbus/class_csr.h"
++#include "cbus/hif_nocpy.h"
++#include "cbus/util_csr.h"
++#include "cbus/gpt.h"
++
++
++/* PFE cores states */
++#define CORE_DISABLE 0x00000000
++#define CORE_ENABLE 0x00000001
++#define CORE_SW_RESET 0x00000002
++
++/* LMEM defines */
++#define LMEM_HDR_SIZE 0x0010
++#define LMEM_BUF_SIZE_LN2 0x7
++#define LMEM_BUF_SIZE (1 << LMEM_BUF_SIZE_LN2)
++
++/* DDR defines */
++#define DDR_HDR_SIZE 0x0100
++#define DDR_BUF_SIZE_LN2 0xb
++#define DDR_BUF_SIZE (1 << DDR_BUF_SIZE_LN2)
++
++
++/* Clock generation through PLL */
++#if defined(CONFIG_PLATFORM_PCI)
++#define PLL_CLK_EN 0
++#else
++#define PLL_CLK_EN 1
++#endif
++
++#endif /* _CBUS_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/cbus/bmu.h b/drivers/net/pfe_eth/pfe/cbus/bmu.h
+new file mode 100644
+index 0000000..f3e5e6d
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/cbus/bmu.h
+@@ -0,0 +1,37 @@
++#ifndef _BMU_H_
++#define _BMU_H_
++
++#define BMU_VERSION 0x000
++#define BMU_CTRL 0x004
++#define BMU_UCAST_CONFIG 0x008
++#define BMU_UCAST_BASE_ADDR 0x00c
++#define BMU_BUF_SIZE 0x010
++#define BMU_BUF_CNT 0x014
++#define BMU_THRES 0x018
++#define BMU_INT_SRC 0x020
++#define BMU_INT_ENABLE 0x024
++#define BMU_ALLOC_CTRL 0x030
++#define BMU_FREE_CTRL 0x034
++#define BMU_FREE_ERR_ADDR 0x038
++#define BMU_CURR_BUF_CNT 0x03c
++#define BMU_MCAST_CNT 0x040
++#define BMU_MCAST_ALLOC_CTRL 0x044
++#define BMU_REM_BUF_CNT 0x048
++#define BMU_LOW_WATERMARK 0x050
++#define BMU_HIGH_WATERMARK 0x054
++#define BMU_INT_MEM_ACCESS 0x100
++
++typedef struct {
++ u32 baseaddr;
++ u32 count;
++ u32 size;
++} BMU_CFG;
++
++
++#define BMU1_BUF_SIZE LMEM_BUF_SIZE_LN2
++#define BMU2_BUF_SIZE DDR_BUF_SIZE_LN2
++
++#define BMU2_MCAST_ALLOC_CTRL BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL
++
++#endif /* _BMU_H_ */
++
+diff --git a/drivers/net/pfe_eth/pfe/cbus/class_csr.h b/drivers/net/pfe_eth/pfe/cbus/class_csr.h
+new file mode 100644
+index 0000000..f3151ec
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/cbus/class_csr.h
+@@ -0,0 +1,206 @@
++#ifndef _CLASS_CSR_H_
++#define _CLASS_CSR_H_
++
++/** @file class_csr.h.
++ * class_csr - block containing all the classifier control and status register. Mapped on CBUS and accessible from all PE's and ARM.
++ */
++
++
++#define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000)
++#define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004)
++#define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010)
++#define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014) /**< (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
++#define CLASS_HDR_SIZE_LMEM(off) ((off) & 0x3f) /**< LMEM header size for the Classifier block.\ Data in the LMEM is written from this offset. */
++#define CLASS_HDR_SIZE_DDR(off) (((off) & 0x1ff) << 16) /**< DDR header size for the Classifier block.\ Data in the DDR is written from this offset. */
++
++#define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020) /**< DMEM address of first [15:0] and second [31:16] buffers on QB side. */
++#define CLASS_PE0_QB_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x024) /**< DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
++
++#define CLASS_PE0_RO_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x060) /**< DMEM address of first [15:0] and second [31:16] buffers on RO side. */
++#define CLASS_PE0_RO_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x064) /**< DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
++
++/** @name Class PE memory access. Allows external PE's and HOST to read/write PMEM/DMEM memory ranges for each classifier PE.
++ */
++//@{
++#define CLASS_MEM_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x100) /**< {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]}, See \ref XXX_MEM_ACCESS_ADDR for details. */
++#define CLASS_MEM_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x104) /**< Internal Memory Access Write Data [31:0] */
++#define CLASS_MEM_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x108) /**< Internal Memory Access Read Data [31:0] */
++//@}
++#define CLASS_TM_INQ_ADDR (CLASS_CSR_BASE_ADDR + 0x114)
++#define CLASS_PE_STATUS (CLASS_CSR_BASE_ADDR + 0x118)
++
++#define CLASS_PHY1_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x11c)
++#define CLASS_PHY1_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x120)
++#define CLASS_PHY1_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x124)
++#define CLASS_PHY1_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x128)
++#define CLASS_PHY1_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x12c)
++#define CLASS_PHY1_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x130)
++#define CLASS_PHY1_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x134)
++#define CLASS_PHY1_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x138)
++#define CLASS_PHY1_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x13c)
++#define CLASS_PHY1_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x140)
++#define CLASS_PHY2_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x144)
++#define CLASS_PHY2_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x148)
++#define CLASS_PHY2_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x14c)
++#define CLASS_PHY2_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x150)
++#define CLASS_PHY2_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x154)
++#define CLASS_PHY2_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x158)
++#define CLASS_PHY2_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x15c)
++#define CLASS_PHY2_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x160)
++#define CLASS_PHY2_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x164)
++#define CLASS_PHY2_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x168)
++#define CLASS_PHY3_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x16c)
++#define CLASS_PHY3_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x170)
++#define CLASS_PHY3_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x174)
++#define CLASS_PHY3_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x178)
++#define CLASS_PHY3_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x17c)
++#define CLASS_PHY3_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x180)
++#define CLASS_PHY3_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x184)
++#define CLASS_PHY3_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x188)
++#define CLASS_PHY3_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x18c)
++#define CLASS_PHY3_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x190)
++#define CLASS_PHY1_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x194)
++#define CLASS_PHY1_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x198)
++#define CLASS_PHY1_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x19c)
++#define CLASS_PHY1_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a0)
++#define CLASS_PHY2_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a4)
++#define CLASS_PHY2_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a8)
++#define CLASS_PHY2_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1ac)
++#define CLASS_PHY2_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b0)
++#define CLASS_PHY3_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b4)
++#define CLASS_PHY3_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b8)
++#define CLASS_PHY3_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1bc)
++#define CLASS_PHY3_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c0)
++#define CLASS_PHY4_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c4)
++#define CLASS_PHY4_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c8)
++#define CLASS_PHY4_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1cc)
++#define CLASS_PHY4_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1d0)
++#define CLASS_PHY4_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d4)
++#define CLASS_PHY4_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d8)
++#define CLASS_PHY4_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1dc)
++#define CLASS_PHY4_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e0)
++#define CLASS_PHY4_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x1e4)
++#define CLASS_PHY4_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e8)
++#define CLASS_PHY4_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x1ec)
++#define CLASS_PHY4_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x1f0)
++#define CLASS_PHY4_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f4)
++#define CLASS_PHY4_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f8)
++
++#define CLASS_PE_SYS_CLK_RATIO (CLASS_CSR_BASE_ADDR + 0x200)
++#define CLASS_AFULL_THRES (CLASS_CSR_BASE_ADDR + 0x204)
++#define CLASS_GAP_BETWEEN_READS (CLASS_CSR_BASE_ADDR + 0x208)
++#define CLASS_MAX_BUF_CNT (CLASS_CSR_BASE_ADDR + 0x20c)
++#define CLASS_TSQ_FIFO_THRES (CLASS_CSR_BASE_ADDR + 0x210)
++#define CLASS_TSQ_MAX_CNT (CLASS_CSR_BASE_ADDR + 0x214)
++#define CLASS_IRAM_DATA_0 (CLASS_CSR_BASE_ADDR + 0x218)
++#define CLASS_IRAM_DATA_1 (CLASS_CSR_BASE_ADDR + 0x21c)
++#define CLASS_IRAM_DATA_2 (CLASS_CSR_BASE_ADDR + 0x220)
++#define CLASS_IRAM_DATA_3 (CLASS_CSR_BASE_ADDR + 0x224)
++
++#define CLASS_BUS_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x228)
++#define CLASS_BUS_ACCESS_ADDR_MASK (0x0001FFFF) //bit 23:0 of PE peripheral address are stored in CLASS_BUS_ACCESS_ADDR
++
++#define CLASS_BUS_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x22c)
++#define CLASS_BUS_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x230)
++
++#define CLASS_ROUTE_HASH_ENTRY_SIZE (CLASS_CSR_BASE_ADDR + 0x234) /**< (route_entry_size[9:0], route_hash_size[23:16] (this is actually ln2(size))) */
++#define CLASS_ROUTE_ENTRY_SIZE(size) ((size) & 0x1ff)
++#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
++
++#define CLASS_ROUTE_TABLE_BASE (CLASS_CSR_BASE_ADDR + 0x238)
++
++#define CLASS_ROUTE_MULTI (CLASS_CSR_BASE_ADDR + 0x23c)
++#define CLASS_SMEM_OFFSET (CLASS_CSR_BASE_ADDR + 0x240)
++#define CLASS_LMEM_BUF_SIZE (CLASS_CSR_BASE_ADDR + 0x244)
++#define CLASS_VLAN_ID (CLASS_CSR_BASE_ADDR + 0x248)
++#define CLASS_BMU1_BUF_FREE (CLASS_CSR_BASE_ADDR + 0x24c)
++#define CLASS_USE_TMU_INQ (CLASS_CSR_BASE_ADDR + 0x250)
++#define CLASS_VLAN_ID1 (CLASS_CSR_BASE_ADDR + 0x254)
++
++#define CLASS_BUS_ACCESS_BASE (CLASS_CSR_BASE_ADDR + 0x258)
++#define CLASS_BUS_ACCESS_BASE_MASK (0xFF000000) //bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE
++
++#define CLASS_HIF_PARSE (CLASS_CSR_BASE_ADDR + 0x25c)
++
++#define CLASS_HOST_PE0_GP (CLASS_CSR_BASE_ADDR + 0x260)
++#define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264)
++#define CLASS_HOST_PE1_GP (CLASS_CSR_BASE_ADDR + 0x268)
++#define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c)
++#define CLASS_HOST_PE2_GP (CLASS_CSR_BASE_ADDR + 0x270)
++#define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274)
++#define CLASS_HOST_PE3_GP (CLASS_CSR_BASE_ADDR + 0x278)
++#define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c)
++#define CLASS_HOST_PE4_GP (CLASS_CSR_BASE_ADDR + 0x280)
++#define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284)
++#define CLASS_HOST_PE5_GP (CLASS_CSR_BASE_ADDR + 0x288)
++#define CLASS_PE5_GP (CLASS_CSR_BASE_ADDR + 0x28c)
++
++#define CLASS_PE_INT_SRC (CLASS_CSR_BASE_ADDR + 0x290)
++#define CLASS_PE_INT_ENABLE (CLASS_CSR_BASE_ADDR + 0x294)
++
++#define CLASS_TPID0_TPID1 (CLASS_CSR_BASE_ADDR + 0x298)
++#define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c)
++
++#define CLASS_L4_CHKSUM_ADDR (CLASS_CSR_BASE_ADDR + 0x2a0)
++
++#define CLASS_PE0_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a4)
++#define CLASS_PE1_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a8)
++#define CLASS_PE2_DEBUG (CLASS_CSR_BASE_ADDR + 0x2ac)
++#define CLASS_PE3_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b0)
++#define CLASS_PE4_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b4)
++#define CLASS_PE5_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b8)
++
++#define CLASS_STATE (CLASS_CSR_BASE_ADDR + 0x2bc)
++
++/* CLASS defines */
++#define CLASS_PBUF_SIZE 0x100 /* Fixed by hardware */
++#define CLASS_PBUF_HEADER_OFFSET 0x80 /* Can be configured */
++
++#define CLASS_PBUF0_BASE_ADDR 0x000 /* Can be configured */
++#define CLASS_PBUF1_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE) /* Can be configured */
++#define CLASS_PBUF2_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE) /* Can be configured */
++#define CLASS_PBUF3_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE) /* Can be configured */
++
++#define CLASS_PBUF0_HEADER_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
++#define CLASS_PBUF1_HEADER_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
++#define CLASS_PBUF2_HEADER_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
++#define CLASS_PBUF3_HEADER_BASE_ADDR (CLASS_PBUF3_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
++
++#define CLASS_PE0_RO_DM_ADDR0_VAL ((CLASS_PBUF1_BASE_ADDR << 16) | CLASS_PBUF0_BASE_ADDR)
++#define CLASS_PE0_RO_DM_ADDR1_VAL ((CLASS_PBUF3_BASE_ADDR << 16) | CLASS_PBUF2_BASE_ADDR)
++
++#define CLASS_PE0_QB_DM_ADDR0_VAL ((CLASS_PBUF1_HEADER_BASE_ADDR << 16) | CLASS_PBUF0_HEADER_BASE_ADDR)
++#define CLASS_PE0_QB_DM_ADDR1_VAL ((CLASS_PBUF3_HEADER_BASE_ADDR << 16) | CLASS_PBUF2_HEADER_BASE_ADDR)
++
++#define CLASS_ROUTE_SIZE 128
++#define CLASS_ROUTE_HASH_BITS 20
++#define CLASS_ROUTE_HASH_MASK ((1 << CLASS_ROUTE_HASH_BITS) - 1)
++
++#define CLASS_ROUTE0_BASE_ADDR 0x400 /* Can be configured */
++#define CLASS_ROUTE1_BASE_ADDR (CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE) /* Can be configured */
++#define CLASS_ROUTE2_BASE_ADDR (CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE) /* Can be configured */
++#define CLASS_ROUTE3_BASE_ADDR (CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE) /* Can be configured */
++
++#define TWO_LEVEL_ROUTE (1 << 0)
++#define PHYNO_IN_HASH (1 << 1)
++#define HW_ROUTE_FETCH (1 << 3)
++#define HW_BRIDGE_FETCH (1 << 5)
++#define IP_ALIGNED (1 << 6)
++#define ARC_HIT_CHECK_EN (1 << 7)
++#define CLASS_TOE (1 << 11)
++#define HASH_NORMAL (0 << 12)
++#define HASH_CRC_PORT (1 << 12)
++#define HASH_CRC_IP (2 << 12)
++#define HASH_CRC_PORT_IP (3 << 12)
++#define QB2BUS_LE (1 << 15)
++
++#define TCP_CHKSUM_DROP (1 << 0)
++#define UDP_CHKSUM_DROP (1 << 1)
++#define IPV4_CHKSUM_DROP (1 << 9)
++
++typedef struct {
++ u32 route_table_baseaddr;
++ u32 route_table_hash_bits;
++} CLASS_CFG;
++
++#endif /* _CLASS_CSR_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/cbus/emac.h b/drivers/net/pfe_eth/pfe/cbus/emac.h
+new file mode 100644
+index 0000000..1f308ce
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/cbus/emac.h
+@@ -0,0 +1,232 @@
++#ifndef _EMAC_H_
++#define _EMAC_H_
++
++#define EMAC_IEVENT_REG 0x004
++#define EMAC_IMASK_REG 0x008
++#define EMAC_R_DES_ACTIVE_REG 0x010
++#define EMAC_X_DES_ACTIVE_REG 0x014
++#define EMAC_ECNTRL_REG 0x024
++#define EMAC_MII_DATA_REG 0x040
++#define EMAC_MII_CTRL_REG 0x044
++#define EMAC_MIB_CTRL_STS_REG 0x064
++#define EMAC_RCNTRL_REG 0x084
++#define EMAC_TCNTRL_REG 0x0C4
++#define EMAC_PHY_ADDR_LOW 0x0E4
++#define EMAC_PHY_ADDR_HIGH 0x0E8
++#define EMAC_TFWR_STR_FWD 0x144
++#define EMAC_RX_SECTIOM_FULL 0x190
++#define EMAC_TX_SECTION_EMPTY 0x1A0
++#define EMAC_TRUNC_FL 0x1B0
++
++#define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */
++#define RMON_T_PACKETS 0x204 /* RMON TX packet count */
++#define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */
++#define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */
++#define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */
++#define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */
++#define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
++#define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */
++#define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
++#define RMON_T_COL 0x224 /* RMON TX collision count */
++#define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */
++#define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */
++#define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */
++#define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */
++#define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */
++#define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */
++#define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */
++#define RMON_T_OCTETS 0x244 /* RMON TX octets */
++#define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */
++#define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */
++#define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */
++#define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */
++#define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */
++#define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */
++#define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */
++#define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */
++#define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */
++#define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */
++#define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */
++#define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */
++#define RMON_R_PACKETS 0x284 /* RMON RX packet count */
++#define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */
++#define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */
++#define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */
++#define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */
++#define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
++#define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */
++#define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
++#define RMON_R_RESVD_O 0x2a4 /* Reserved */
++#define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */
++#define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */
++#define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */
++#define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */
++#define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */
++#define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */
++#define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */
++#define RMON_R_OCTETS 0x2c4 /* RMON RX octets */
++#define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */
++#define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */
++#define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */
++#define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */
++#define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */
++#define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */
++#define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */
++
++
++/* GEMAC definitions and settings */
++
++#define EMAC_PORT_0 0
++#define EMAC_PORT_1 1
++
++/* GEMAC Bit definitions */
++#define EMAC_IEVENT_HBERR 0x80000000
++#define EMAC_IEVENT_BABR 0x40000000
++#define EMAC_IEVENT_BABT 0x20000000
++#define EMAC_IEVENT_GRA 0x10000000
++#define EMAC_IEVENT_TXF 0x08000000
++#define EMAC_IEVENT_TXB 0x04000000
++#define EMAC_IEVENT_RXF 0x02000000
++#define EMAC_IEVENT_RXB 0x01000000
++#define EMAC_IEVENT_MII 0x00800000
++#define EMAC_IEVENT_EBERR 0x00400000
++#define EMAC_IEVENT_LC 0x00200000
++#define EMAC_IEVENT_RL 0x00100000
++#define EMAC_IEVENT_UN 0x00080000
++
++#define EMAC_IMASK_HBERR 0x80000000
++#define EMAC_IMASK_BABR 0x40000000
++#define EMAC_IMASKT_BABT 0x20000000
++#define EMAC_IMASK_GRA 0x10000000
++#define EMAC_IMASKT_TXF 0x08000000
++#define EMAC_IMASK_TXB 0x04000000
++#define EMAC_IMASKT_RXF 0x02000000
++#define EMAC_IMASK_RXB 0x01000000
++#define EMAC_IMASK_MII 0x00800000
++#define EMAC_IMASK_EBERR 0x00400000
++#define EMAC_IMASK_LC 0x00200000
++#define EMAC_IMASKT_RL 0x00100000
++#define EMAC_IMASK_UN 0x00080000
++
++#define EMAC_RCNTRL_MAX_FL_SHIFT 16
++#define EMAC_RCNTRL_LOOP 0x00000001
++#define EMAC_RCNTRL_DRT 0x00000002
++#define EMAC_RCNTRL_MII_MODE 0x00000004
++#define EMAC_RCNTRL_PROM 0x00000008
++#define EMAC_RCNTRL_BC_REJ 0x00000010
++#define EMAC_RCNTRL_FCE 0x00000020
++#define EMAC_RCNTRL_RGMII 0x00000040
++#define EMAC_RCNTRL_SGMII 0x00000080
++#define EMAC_RCNTRL_RMII 0x00000100
++#define EMAC_RCNTRL_RMII_10T 0x00000200
++#define EMAC_RCNTRL_CRC_FWD 0x00004000
++
++#define EMAC_TCNTRL_GTS 0x00000001
++#define EMAC_TCNTRL_HBC 0x00000002
++#define EMAC_TCNTRL_FDEN 0x00000004
++#define EMAC_TCNTRL_TFC_PAUSE 0x00000008
++#define EMAC_TCNTRL_RFC_PAUSE 0x00000010
++
++#define EMAC_ECNTRL_RESET 0x00000001 /* reset the EMAC */
++#define EMAC_ECNTRL_ETHER_EN 0x00000002 /* enable the EMAC */
++#define EMAC_ECNTRL_SPEED 0x00000020
++#define EMAC_ECNTRL_DBSWAP 0x00000100
++
++#define EMAC_X_WMRK_STRFWD 0x00000100
++
++#define EMAC_X_DES_ACTIVE_TDAR 0x01000000
++#define EMAC_R_DES_ACTIVE_RDAR 0x01000000
++
++
++
++/* The possible operating speeds of the MAC, currently supporting 10, 100 and
++ * 1000Mb modes.
++ */
++typedef enum {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS} MAC_SPEED;
++
++#define GMII 1
++#define MII 2
++#define RMII 3
++#define RGMII 4
++#define SGMII 5
++
++#define DUPLEX_HALF 0x00
++#define DUPLEX_FULL 0x01
++
++
++/* Default configuration */
++#define EMAC0_DEFAULT_DUPLEX_MODE FULLDUPLEX
++#define EMAC0_DEFAULT_EMAC_MODE RGMII
++#define EMAC0_DEFAULT_EMAC_SPEED SPEED_1000M
++
++#define EMAC1_DEFAULT_DUPLEX_MODE FULLDUPLEX
++#define EMAC1_DEFAULT_EMAC_MODE SGMII
++#define EMAC1_DEFAULT_EMAC_SPEED SPEED_1000M
++
++/* MII-related definitios */
++#define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
++#define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
++#define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
++#define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
++#define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
++#define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */
++#define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
++
++#define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
++#define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */
++#define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
++#define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */
++
++#define EMAC_MII_DATA_RA(v) ((v & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT)
++#define EMAC_MII_DATA_PA(v) ((v & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_PA_SHIFT)
++#define EMAC_MII_DATA(v) (v & 0xffff)
++
++#define EMAC_MII_SPEED_SHIFT 1
++#define EMAC_HOLDTIME_SHIFT 8
++#define EMAC_HOLDTIME_MASK 0x7
++#define EMAC_HOLDTIME(v) ((v & EMAC_HOLDTIME_MASK) << EMAC_HOLDTIME_SHIFT)
++
++/* The Address organisation for the MAC device. All addresses are split into
++ * two 32-bit register fields. The first one (bottom) is the lower 32-bits of
++ * the address and the other field are the high order bits - this may be 16-bits
++ * in the case of MAC addresses, or 32-bits for the hash address.
++ * In terms of memory storage, the first item (bottom) is assumed to be at a
++ * lower address location than 'top'. i.e. top should be at address location of
++ * 'bottom' + 4 bytes.
++ */
++typedef struct {
++ u32 bottom; /* Lower 32-bits of address. */
++ u32 top; /* Upper 32-bits of address. */
++} MAC_ADDR;
++
++
++/* The following is the organisation of the address filters section of the MAC
++ * registers. The Cadence MAC contains four possible specific address match
++ * addresses, if an incoming frame corresponds to any one of these four
++ * addresses then the frame will be copied to memory.
++ * It is not necessary for all four of the address match registers to be
++ * programmed, this is application dependant.
++ */
++typedef struct {
++ MAC_ADDR one; /* Specific address register 1. */
++ MAC_ADDR two; /* Specific address register 2. */
++ MAC_ADDR three; /* Specific address register 3. */
++ MAC_ADDR four; /* Specific address register 4. */
++} SPEC_ADDR;
++
++typedef struct {
++ u32 mode;
++ u32 speed;
++ u32 duplex;
++} GEMAC_CFG;
++
++/* Internal PHY Registers - SGMII */
++#define PHY_SGMII_CR_PHY_RESET 0x8000
++#define PHY_SGMII_CR_RESET_AN 0x0200
++#define PHY_SGMII_CR_DEF_VAL 0x1140
++#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
++#define PHY_SGMII_IF_MODE_AN 0x0002
++#define PHY_SGMII_IF_MODE_SGMII 0x0001
++
++
++#endif /* _EMAC_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/cbus/gpi.h b/drivers/net/pfe_eth/pfe/cbus/gpi.h
+new file mode 100644
+index 0000000..d2d165f
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/cbus/gpi.h
+@@ -0,0 +1,60 @@
++#ifndef _GPI_H_
++#define _GPI_H_
++
++#define GPI_VERSION 0x00
++#define GPI_CTRL 0x04
++#define GPI_RX_CONFIG 0x08
++#define GPI_HDR_SIZE 0x0c
++#define GPI_BUF_SIZE 0x10
++#define GPI_LMEM_ALLOC_ADDR 0x14
++#define GPI_LMEM_FREE_ADDR 0x18
++#define GPI_DDR_ALLOC_ADDR 0x1c
++#define GPI_DDR_FREE_ADDR 0x20
++#define GPI_CLASS_ADDR 0x24
++#define GPI_DRX_FIFO 0x28
++#define GPI_TRX_FIFO 0x2c
++#define GPI_INQ_PKTPTR 0x30
++#define GPI_DDR_DATA_OFFSET 0x34
++#define GPI_LMEM_DATA_OFFSET 0x38
++#define GPI_TMLF_TX 0x4c
++#define GPI_DTX_ASEQ 0x50
++#define GPI_FIFO_STATUS 0x54
++#define GPI_FIFO_DEBUG 0x58
++#define GPI_TX_PAUSE_TIME 0x5c
++#define GPI_LMEM_SEC_BUF_DATA_OFFSET 0x60
++#define GPI_DDR_SEC_BUF_DATA_OFFSET 0x64
++#define GPI_TOE_CHKSUM_EN 0x68
++#define GPI_OVERRUN_DROPCNT 0x6c
++
++typedef struct {
++ u32 lmem_rtry_cnt;
++ u32 tmlf_txthres;
++ u32 aseq_len;
++} GPI_CFG;
++
++
++/* GPI commons defines */
++#define GPI_LMEM_BUF_EN 0x1
++#define GPI_DDR_BUF_EN 0x1
++
++/* EGPI 1 defines */
++#define EGPI1_LMEM_RTRY_CNT 0x40
++#define EGPI1_TMLF_TXTHRES 0xBC
++#define EGPI1_ASEQ_LEN 0x50
++
++/* EGPI 2 defines */
++#define EGPI2_LMEM_RTRY_CNT 0x40
++#define EGPI2_TMLF_TXTHRES 0xBC
++#define EGPI2_ASEQ_LEN 0x40
++
++/* EGPI 3 defines */
++#define EGPI3_LMEM_RTRY_CNT 0x40
++#define EGPI3_TMLF_TXTHRES 0xBC
++#define EGPI3_ASEQ_LEN 0x40
++
++/* HGPI defines */
++#define HGPI_LMEM_RTRY_CNT 0x40
++#define HGPI_TMLF_TXTHRES 0xBC
++#define HGPI_ASEQ_LEN 0x40
++
++#endif /* _GPI_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/cbus/gpt.h b/drivers/net/pfe_eth/pfe/cbus/gpt.h
+new file mode 100644
+index 0000000..f8c114b
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/cbus/gpt.h
+@@ -0,0 +1,11 @@
++#ifndef _CBUS_GPT_H_
++#define _CBUS_GPT_H_
++
++#define CBUS_GPT_VERSION (CBUS_GPT_BASE_ADDR + 0x00)
++#define CBUS_GPT_STATUS (CBUS_GPT_BASE_ADDR + 0x04)
++#define CBUS_GPT_CONFIG (CBUS_GPT_BASE_ADDR + 0x08)
++#define CBUS_GPT_COUNTER (CBUS_GPT_BASE_ADDR + 0x0c)
++#define CBUS_GPT_PERIOD (CBUS_GPT_BASE_ADDR + 0x10)
++#define CBUS_GPT_WIDTH (CBUS_GPT_BASE_ADDR + 0x14)
++
++#endif /* _CBUS_GPT_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/cbus/hif.h b/drivers/net/pfe_eth/pfe/cbus/hif.h
+new file mode 100644
+index 0000000..a4dd7c2
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/cbus/hif.h
+@@ -0,0 +1,62 @@
++#ifndef _HIF_H_
++#define _HIF_H_
++
++/** @file hif.h.
++ * hif - PFE hif block control and status register. Mapped on CBUS and accessible from all PE's and ARM.
++ */
++#define HIF_VERSION (HIF_BASE_ADDR + 0x00)
++#define HIF_TX_CTRL (HIF_BASE_ADDR + 0x04)
++#define HIF_TX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x08)
++#define HIF_TX_ALLOC (HIF_BASE_ADDR + 0x0c)
++#define HIF_TX_BDP_ADDR (HIF_BASE_ADDR + 0x10)
++#define HIF_TX_STATUS (HIF_BASE_ADDR + 0x14)
++#define HIF_RX_CTRL (HIF_BASE_ADDR + 0x20)
++#define HIF_RX_BDP_ADDR (HIF_BASE_ADDR + 0x24)
++#define HIF_RX_STATUS (HIF_BASE_ADDR + 0x30)
++#define HIF_INT_SRC (HIF_BASE_ADDR + 0x34)
++#define HIF_INT_ENABLE (HIF_BASE_ADDR + 0x38)
++#define HIF_POLL_CTRL (HIF_BASE_ADDR + 0x3c)
++#define HIF_RX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x40)
++#define HIF_RX_ALLOC (HIF_BASE_ADDR + 0x44)
++#define HIF_TX_DMA_STATUS (HIF_BASE_ADDR + 0x48)
++#define HIF_RX_DMA_STATUS (HIF_BASE_ADDR + 0x4c)
++#define HIF_INT_COAL (HIF_BASE_ADDR + 0x50)
++
++/*HIF_INT_SRC/ HIF_INT_ENABLE control bits */
++#define HIF_INT (1 << 0)
++#define HIF_RXBD_INT (1 << 1)
++#define HIF_RXPKT_INT (1 << 2)
++#define HIF_TXBD_INT (1 << 3)
++#define HIF_TXPKT_INT (1 << 4)
++
++/*HIF_TX_CTRL bits */
++#define HIF_CTRL_DMA_EN (1<<0)
++#define HIF_CTRL_BDP_POLL_CTRL_EN (1<<1)
++#define HIF_CTRL_BDP_CH_START_WSTB (1<<2)
++
++/*HIF_INT_ENABLE bits */
++#define HIF_INT_EN (1 << 0)
++#define HIF_RXBD_INT_EN (1 << 1)
++#define HIF_RXPKT_INT_EN (1 << 2)
++#define HIF_TXBD_INT_EN (1 << 3)
++#define HIF_TXPKT_INT_EN (1 << 4)
++
++/*HIF_POLL_CTRL bits*/
++#define HIF_RX_POLL_CTRL_CYCLE 0x0400
++#define HIF_TX_POLL_CTRL_CYCLE 0x0400
++
++/*Buffer descriptor control bits */
++#define BD_CTRL_BUFLEN_MASK (0xffff)
++#define BD_BUF_LEN(x) (x & BD_CTRL_BUFLEN_MASK)
++#define BD_CTRL_CBD_INT_EN (1 << 16)
++#define BD_CTRL_PKT_INT_EN (1 << 17)
++#define BD_CTRL_LIFM (1 << 18)
++#define BD_CTRL_LAST_BD (1 << 19)
++#define BD_CTRL_DIR (1 << 20)
++#define BD_CTRL_PKT_XFER (1 << 24)
++#define BD_CTRL_DESC_EN (1 << 31)
++#define BD_CTRL_PARSE_DISABLE (1 << 25)
++#define BD_CTRL_BRFETCH_DISABLE (1 << 26)
++#define BD_CTRL_RTFETCH_DISABLE (1 << 27)
++
++#endif /* _HIF_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h b/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
+new file mode 100644
+index 0000000..93cb946
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
+@@ -0,0 +1,33 @@
++#ifndef _HIF_NOCPY_H_
++#define _HIF_NOCPY_H_
++
++#define HIF_NOCPY_VERSION (HIF_NOCPY_BASE_ADDR + 0x00)
++#define HIF_NOCPY_TX_CTRL (HIF_NOCPY_BASE_ADDR + 0x04)
++#define HIF_NOCPY_TX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x08)
++#define HIF_NOCPY_TX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x0c)
++#define HIF_NOCPY_TX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x10)
++#define HIF_NOCPY_TX_STATUS (HIF_NOCPY_BASE_ADDR + 0x14)
++#define HIF_NOCPY_RX_CTRL (HIF_NOCPY_BASE_ADDR + 0x20)
++#define HIF_NOCPY_RX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x24)
++#define HIF_NOCPY_RX_STATUS (HIF_NOCPY_BASE_ADDR + 0x30)
++#define HIF_NOCPY_INT_SRC (HIF_NOCPY_BASE_ADDR + 0x34)
++#define HIF_NOCPY_INT_ENABLE (HIF_NOCPY_BASE_ADDR + 0x38)
++#define HIF_NOCPY_POLL_CTRL (HIF_NOCPY_BASE_ADDR + 0x3c)
++#define HIF_NOCPY_RX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x40)
++#define HIF_NOCPY_RX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x44)
++#define HIF_NOCPY_TX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x48)
++#define HIF_NOCPY_RX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x4c)
++#define HIF_NOCPY_RX_INQ0_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x50)
++#define HIF_NOCPY_RX_INQ1_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x54)
++#define HIF_NOCPY_TX_PORT_NO (HIF_NOCPY_BASE_ADDR + 0x60)
++#define HIF_NOCPY_LMEM_ALLOC_ADDR (HIF_NOCPY_BASE_ADDR + 0x64)
++#define HIF_NOCPY_CLASS_ADDR (HIF_NOCPY_BASE_ADDR + 0x68)
++#define HIF_NOCPY_TMU_PORT0_ADDR (HIF_NOCPY_BASE_ADDR + 0x70)
++#define HIF_NOCPY_TMU_PORT1_ADDR (HIF_NOCPY_BASE_ADDR + 0x74)
++#define HIF_NOCPY_TMU_PORT2_ADDR (HIF_NOCPY_BASE_ADDR + 0x7c)
++#define HIF_NOCPY_TMU_PORT3_ADDR (HIF_NOCPY_BASE_ADDR + 0x80)
++#define HIF_NOCPY_TMU_PORT4_ADDR (HIF_NOCPY_BASE_ADDR + 0x84)
++#define HIF_NOCPY_INT_COAL (HIF_NOCPY_BASE_ADDR + 0x90)
++
++
++#endif /* _HIF_NOCPY_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
+new file mode 100644
+index 0000000..cbcbb1f
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
+@@ -0,0 +1,102 @@
++#ifndef _TMU_CSR_H_
++#define _TMU_CSR_H_
++
++#define TMU_VERSION (TMU_CSR_BASE_ADDR + 0x000)
++#define TMU_INQ_WATERMARK (TMU_CSR_BASE_ADDR + 0x004)
++#define TMU_PHY_INQ_PKTPTR (TMU_CSR_BASE_ADDR + 0x008)
++#define TMU_PHY_INQ_PKTINFO (TMU_CSR_BASE_ADDR + 0x00c)
++#define TMU_PHY_INQ_FIFO_CNT (TMU_CSR_BASE_ADDR + 0x010)
++#define TMU_SYS_GENERIC_CONTROL (TMU_CSR_BASE_ADDR + 0x014)
++#define TMU_SYS_GENERIC_STATUS (TMU_CSR_BASE_ADDR + 0x018)
++#define TMU_SYS_GEN_CON0 (TMU_CSR_BASE_ADDR + 0x01c)
++#define TMU_SYS_GEN_CON1 (TMU_CSR_BASE_ADDR + 0x020)
++#define TMU_SYS_GEN_CON2 (TMU_CSR_BASE_ADDR + 0x024)
++#define TMU_SYS_GEN_CON3 (TMU_CSR_BASE_ADDR + 0x028)
++#define TMU_SYS_GEN_CON4 (TMU_CSR_BASE_ADDR + 0x02c)
++#define TMU_TEQ_DISABLE_DROPCHK (TMU_CSR_BASE_ADDR + 0x030)
++#define TMU_TEQ_CTRL (TMU_CSR_BASE_ADDR + 0x034)
++#define TMU_TEQ_QCFG (TMU_CSR_BASE_ADDR + 0x038)
++#define TMU_TEQ_DROP_STAT (TMU_CSR_BASE_ADDR + 0x03c)
++#define TMU_TEQ_QAVG (TMU_CSR_BASE_ADDR + 0x040)
++#define TMU_TEQ_WREG_PROB (TMU_CSR_BASE_ADDR + 0x044)
++#define TMU_TEQ_TRANS_STAT (TMU_CSR_BASE_ADDR + 0x048)
++#define TMU_TEQ_HW_PROB_CFG0 (TMU_CSR_BASE_ADDR + 0x04c)
++#define TMU_TEQ_HW_PROB_CFG1 (TMU_CSR_BASE_ADDR + 0x050)
++#define TMU_TEQ_HW_PROB_CFG2 (TMU_CSR_BASE_ADDR + 0x054)
++#define TMU_TEQ_HW_PROB_CFG3 (TMU_CSR_BASE_ADDR + 0x058)
++#define TMU_TEQ_HW_PROB_CFG4 (TMU_CSR_BASE_ADDR + 0x05c)
++#define TMU_TEQ_HW_PROB_CFG5 (TMU_CSR_BASE_ADDR + 0x060)
++#define TMU_TEQ_HW_PROB_CFG6 (TMU_CSR_BASE_ADDR + 0x064)
++#define TMU_TEQ_HW_PROB_CFG7 (TMU_CSR_BASE_ADDR + 0x068)
++#define TMU_TEQ_HW_PROB_CFG8 (TMU_CSR_BASE_ADDR + 0x06c)
++#define TMU_TEQ_HW_PROB_CFG9 (TMU_CSR_BASE_ADDR + 0x070)
++#define TMU_TEQ_HW_PROB_CFG10 (TMU_CSR_BASE_ADDR + 0x074)
++#define TMU_TEQ_HW_PROB_CFG11 (TMU_CSR_BASE_ADDR + 0x078)
++#define TMU_TEQ_HW_PROB_CFG12 (TMU_CSR_BASE_ADDR + 0x07c)
++#define TMU_TEQ_HW_PROB_CFG13 (TMU_CSR_BASE_ADDR + 0x080)
++#define TMU_TEQ_HW_PROB_CFG14 (TMU_CSR_BASE_ADDR + 0x084)
++#define TMU_TEQ_HW_PROB_CFG15 (TMU_CSR_BASE_ADDR + 0x088)
++#define TMU_TEQ_HW_PROB_CFG16 (TMU_CSR_BASE_ADDR + 0x08c)
++#define TMU_TEQ_HW_PROB_CFG17 (TMU_CSR_BASE_ADDR + 0x090)
++#define TMU_TEQ_HW_PROB_CFG18 (TMU_CSR_BASE_ADDR + 0x094)
++#define TMU_TEQ_HW_PROB_CFG19 (TMU_CSR_BASE_ADDR + 0x098)
++#define TMU_TEQ_HW_PROB_CFG20 (TMU_CSR_BASE_ADDR + 0x09c)
++#define TMU_TEQ_HW_PROB_CFG21 (TMU_CSR_BASE_ADDR + 0x0a0)
++#define TMU_TEQ_HW_PROB_CFG22 (TMU_CSR_BASE_ADDR + 0x0a4)
++#define TMU_TEQ_HW_PROB_CFG23 (TMU_CSR_BASE_ADDR + 0x0a8)
++#define TMU_TEQ_HW_PROB_CFG24 (TMU_CSR_BASE_ADDR + 0x0ac)
++#define TMU_TEQ_HW_PROB_CFG25 (TMU_CSR_BASE_ADDR + 0x0b0)
++#define TMU_TDQ_IIFG_CFG (TMU_CSR_BASE_ADDR + 0x0b4)
++#define TMU_TDQ0_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x0b8) /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY0 */
++#define TMU_LLM_CTRL (TMU_CSR_BASE_ADDR + 0x0bc)
++#define TMU_LLM_BASE_ADDR (TMU_CSR_BASE_ADDR + 0x0c0)
++#define TMU_LLM_QUE_LEN (TMU_CSR_BASE_ADDR + 0x0c4)
++#define TMU_LLM_QUE_HEADPTR (TMU_CSR_BASE_ADDR + 0x0c8)
++#define TMU_LLM_QUE_TAILPTR (TMU_CSR_BASE_ADDR + 0x0cc)
++#define TMU_LLM_QUE_DROPCNT (TMU_CSR_BASE_ADDR + 0x0d0)
++#define TMU_INT_EN (TMU_CSR_BASE_ADDR + 0x0d4)
++#define TMU_INT_SRC (TMU_CSR_BASE_ADDR + 0x0d8)
++#define TMU_INQ_STAT (TMU_CSR_BASE_ADDR + 0x0dc)
++#define TMU_CTRL (TMU_CSR_BASE_ADDR + 0x0e0)
++
++#define TMU_MEM_ACCESS_ADDR (TMU_CSR_BASE_ADDR + 0x0e4) /**< [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory Write [27:24] Byte Enables of the Internal memory access [23:0] Address of the internal memory. This address is used to access both the PM and DM of all the PE's */
++#define TMU_MEM_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x0e8) /**< Internal Memory Access Write Data */
++#define TMU_MEM_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x0ec) /**< Internal Memory Access Read Data. The commands are blocked at the mem_access only */
++
++#define TMU_PHY0_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f0) /**< [31:0] PHY0 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
++#define TMU_PHY1_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f4) /**< [31:0] PHY1 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
++#define TMU_PHY2_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f8) /**< [31:0] PHY2 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
++#define TMU_PHY3_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0fc) /**< [31:0] PHY3 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
++#define TMU_BMU_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x100)
++#define TMU_TX_CTRL (TMU_CSR_BASE_ADDR + 0x104)
++
++#define TMU_BUS_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x108)
++#define TMU_BUS_ACCESS (TMU_CSR_BASE_ADDR + 0x10c)
++#define TMU_BUS_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x110)
++
++#define TMU_PE_SYS_CLK_RATIO (TMU_CSR_BASE_ADDR + 0x114)
++#define TMU_PE_STATUS (TMU_CSR_BASE_ADDR + 0x118)
++#define TMU_TEQ_MAX_THRESHOLD (TMU_CSR_BASE_ADDR + 0x11c)
++#define TMU_PHY4_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x134) /**< [31:0] PHY4 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
++#define TMU_TDQ1_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x138) /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY1 */
++#define TMU_TDQ2_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x13c) /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY2 */
++#define TMU_TDQ3_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x140) /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY3 */
++#define TMU_BMU_BUF_SIZE (TMU_CSR_BASE_ADDR + 0x144)
++#define TMU_PHY5_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x148) /**< [31:0] PHY5 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
++
++#define SW_RESET (1 << 0) /**< Global software reset */
++#define INQ_RESET (1 << 2)
++#define TEQ_RESET (1 << 3)
++#define TDQ_RESET (1 << 4)
++#define PE_RESET (1 << 5)
++#define MEM_INIT (1 << 6)
++#define MEM_INIT_DONE (1 << 7)
++#define LLM_INIT (1 << 8)
++#define LLM_INIT_DONE (1 << 9)
++
++typedef struct {
++ u32 llm_base_addr;
++ u32 llm_queue_len;
++} TMU_CFG;
++
++#endif /* _TMU_CSR_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/cbus/util_csr.h b/drivers/net/pfe_eth/pfe/cbus/util_csr.h
+new file mode 100644
+index 0000000..d67e849
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/cbus/util_csr.h
+@@ -0,0 +1,43 @@
++#ifndef _UTIL_CSR_H_
++#define _UTIL_CSR_H_
++
++#define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000)
++#define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004)
++#define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010)
++
++#define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014)
++
++#define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020)
++#define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024)
++#define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060)
++#define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064)
++
++#define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100)
++#define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104)
++#define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108)
++
++#define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114)
++#define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118)
++
++#define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200)
++#define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204)
++#define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208)
++#define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c)
++#define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210)
++#define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214)
++#define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218)
++#define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c)
++#define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220)
++#define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224)
++
++#define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228)
++#define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c)
++#define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230)
++
++#define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234)
++#define UTIL_MISC_REG (UTIL_CSR_BASE_ADDR + 0x240)
++
++typedef struct {
++} UTIL_CFG;
++
++#endif /* _UTIL_CSR_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/class.h b/drivers/net/pfe_eth/pfe/class.h
+new file mode 100644
+index 0000000..33ad826
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/class.h
+@@ -0,0 +1,142 @@
++#ifndef _CLASS_H_
++#define _CLASS_H_
++
++#define CLASS_DMEM_BASE_ADDR 0x00000000
++#define CLASS_DMEM_SIZE 0x2000
++#define CLASS_DMEM_END (CLASS_DMEM_BASE_ADDR + CLASS_DMEM_SIZE)
++#define CLASS_PMEM_BASE_ADDR 0x00010000
++
++#define CBUS_BASE_ADDR 0xc0000000
++#define CLASS_APB_BASE_ADDR 0xc1000000
++#define CLASS_AHB1_BASE_ADDR 0xc2000000
++#define CLASS_AHB2_BASE_ADDR 0xc3000000
++
++#include "cbus.h"
++
++#define GPT_BASE_ADDR (CLASS_APB_BASE_ADDR + 0x00000)
++#define UART_BASE_ADDR (CLASS_APB_BASE_ADDR + 0x10000)
++#define PERG_BASE_ADDR (CLASS_APB_BASE_ADDR + 0x20000)
++#define EFET_BASE_ADDR (CLASS_APB_BASE_ADDR + 0x40000)
++
++#define MAC_HASH_BASE_ADDR (CLASS_AHB1_BASE_ADDR + 0x30000)
++#define VLAN_HASH_BASE_ADDR (CLASS_AHB1_BASE_ADDR + 0x50000)
++
++#define PE_LMEM_BASE_ADDR (CLASS_AHB2_BASE_ADDR + 0x10000)
++#define PE_LMEM_SIZE 0x8000
++#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
++#define CCU_BASE_ADDR (CLASS_AHB2_BASE_ADDR + 0x20000)
++
++#define IS_DMEM(addr, len) (((unsigned long)(addr) >= CLASS_DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= CLASS_DMEM_END))
++#define IS_PE_LMEM(addr, len) (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PE_LMEM_END))
++
++
++#include "gpt.h"
++#include "uart.h"
++#include "class/perg.h"
++#include "class/efet.h"
++#include "class/mac_hash.h"
++#include "class/vlan_hash.h"
++#include "class/ccu.h"
++
++
++#define CLASS_MAX_PBUFFERS 4
++
++#define PBUF_HWPARSE_OFFSET 0x10 /* Fixed by hardware */
++
++#define PAYLOAD_DMEM_MAX_SIZE (CLASS_PBUF_SIZE - CLASS_PBUF_HEADER_OFFSET - sizeof(class_rx_hdr_t))
++
++#define PHYPORT_0 0x0
++#define PHYPORT_1 0x1
++#define HOST_PORT_NO 0x3
++
++#define ACT_SRC_MAC_REPLACE (1 << (4+0))
++#define ACT_VLAN_REPLACE (1 << (4+3))
++#define ACT_TCPCHKSUM_REPLACE (1 << (4+2))
++#define ACT_VLAN_ADD (1 << (4+1))
++
++#define MIN_PKT_SIZE 56
++
++#define PARSE_ETH_TYPE (1 << 0)
++#define PARSE_VLAN_TYPE (1 << 1)
++#define PARSE_PPPOE_TYPE (1 << 2)
++#define PARSE_ARP_TYPE (1 << 3)
++#define PARSE_MCAST_TYPE (1 << 4)
++#define PARSE_IP_TYPE (1 << 5)
++#define PARSE_IPV6_TYPE (1 << 6)
++#define PARSE_IPV4_TYPE (1 << 7)
++
++#define PARSE_IPX_TYPE (1 << 9)
++
++#define PARSE_UDP_FLOW (1 << 11)
++#define PARSE_TCP_FLOW (1 << 12)
++#define PARSE_ICMP_FLOW (1 << 13)
++#define PARSE_IGMP_FLOW (1 << 14)
++#define PARSE_FRAG_FLOW (1 << 15)
++
++#define PARSE_HIF_PKT (1 << 23)
++#define PARSE_ARC_HIT (1 << 24)
++#define PARSE_PKT_OVERFLOW (1 << 25)
++
++#define PARSE_PROTO_MISMATCH (1 << 28)
++#define PARSE_L3_MISMATCH (1 << 29)
++#define PARSE_L2_MISMATCH (1 << 30)
++#define PARSE_INCOMPLETE (1 << 31)
++
++
++typedef struct _hwparse_t {
++ u16 sid;
++ u16 connid;
++ u8 toevec;
++ u8 pLayer2Hdr;
++ u8 pLayer3Hdr;
++ u8 pLayer4Hdr;
++ u16 vlanid;
++ u16 ifParseFlags;
++ u32 parseFlags;
++ u16 srcport;
++ u16 dstport;
++ u32 proto:8;
++ u32 port:4;
++ u32 hash:20;
++ u64 rte_res_valid:1;
++ u64 vlan_res_valid:1;
++ u64 dst_res_valid:1;
++ u64 src_res_valid:1;
++ u64 vlan_lookup:20;
++ u64 dst_lookup:20;
++ u64 src_lookup:20;
++} hwparse_t;
++
++
++typedef struct {
++ u32 next_ptr; /* ptr to the start of the first DDR buffer */
++ u16 length; /* total packet length */
++ u16 phyno; /* input physical port number */
++ u32 status; /* gemac status bits */
++ u32 res; /* reserved for software usage */
++} class_rx_hdr_t;
++
++
++typedef struct {
++ u8 num_cpy; /* no of copies to send out from RO block, for each there must be a corresponding tx pre-header */
++ u8 dma_len; /* len to be DMAed to DDR mem, including all tx pre-headers */
++ u16 src_addr; /* class dmem source address, pointing to first tx pre-header */
++ u32 dst_addr; /* DDR memory destination address of first tx pre-header, must be so packet data is continuous in DDR */
++ u32 res1; /* reserved for software usage - queue number? */
++ u16 res2; /* reserved for software usage */
++ u16 tsv; /* time stamp val */
++} class_tx_desc_t;
++
++
++typedef struct {
++ u8 start_data_off; /* packet data start offset, relative to start of this tx pre-header */
++ u8 start_buf_off; /* this tx pre-header start offset, relative to start of DDR buffer */
++ u16 pkt_length; /* total packet lenght */
++ u8 act_phyno; /* action phy number */
++ u8 queueno; /* queueno */
++ u16 src_mac_msb; /* indicates src_mac 47:32 */
++ u32 src_mac_lsb; /* indicates src_mac 31:0 */
++ u32 vlanid; /* vlanid */
++} class_tx_hdr_t;
++
++#endif /* _CLASS_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/class/ccu.h b/drivers/net/pfe_eth/pfe/class/ccu.h
+new file mode 100644
+index 0000000..2c43d97
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/class/ccu.h
+@@ -0,0 +1,10 @@
++#ifndef _CCU_H_
++#define _CCU_H_
++
++#define CCU_ADDR (CCU_BASE_ADDR + 0x00)
++#define CCU_CNT (CCU_BASE_ADDR + 0x04)
++#define CCU_STATUS (CCU_BASE_ADDR + 0x08)
++#define CCU_VAL (CCU_BASE_ADDR + 0x0c)
++
++#endif /* _CCU_H_ */
++
+diff --git a/drivers/net/pfe_eth/pfe/class/efet.h b/drivers/net/pfe_eth/pfe/class/efet.h
+new file mode 100644
+index 0000000..4f3cc25
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/class/efet.h
+@@ -0,0 +1,21 @@
++#ifndef _CLASS_EFET_H_
++#define _CLASS_EFET_H_
++
++#define CLASS_EFET_ENTRY_ADDR (EFET_BASE_ADDR + 0x00)
++#define CLASS_EFET_ENTRY_SIZE (EFET_BASE_ADDR + 0x04)
++#define CLASS_EFET_ENTRY_DMEM_ADDR (EFET_BASE_ADDR + 0x08)
++#define CLASS_EFET_ENTRY_STATUS (EFET_BASE_ADDR + 0x0c)
++#define CLASS_EFET_ENTRY_ENDIAN (EFET_BASE_ADDR + 0x10)
++
++#define CBUS2DMEM 0
++#define DMEM2CBUS 1
++
++#define EFET2BUS_LE (1 << 0)
++#define PE2BUS_LE (1 << 1)
++
++void class_efet(u32 cbus_addr, u32 dmem_addr, u32 len, u32 dir);
++void class_efet_wait(void);
++void class_efet_sync(u32 cbus_addr, u32 dmem_addr, u32 len, u32 dir);
++
++#endif /* _CLASS_EFET_H_ */
++
+diff --git a/drivers/net/pfe_eth/pfe/class/mac_hash.h b/drivers/net/pfe_eth/pfe/class/mac_hash.h
+new file mode 100644
+index 0000000..68023b4
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/class/mac_hash.h
+@@ -0,0 +1,28 @@
++#ifndef _MAC_HASH_H_
++#define _MAC_HASH_H_
++
++#define MAC_HASH_REQ1_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x000)
++#define MAC_HASH_REQ2_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x020)
++#define MAC_HASH_REQ3_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x040)
++#define MAC_HASH_REQ4_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x060)
++#define MAC_HASH_REQ5_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x080)
++#define MAC_HASH_REQ6_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x0a0)
++#define MAC_HASH_REQ7_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x0c0)
++#define MAC_HASH_REQ8_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x0e0)
++
++#define MAC_HASH_REQ_CMD(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x000)
++#define MAC_HASH_REQ_MAC1_ADDR(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x004)
++#define MAC_HASH_REQ_MAC2_ADDR(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x008)
++#define MAC_HASH_REQ_MASK1_ADDR(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x00c)
++#define MAC_HASH_REQ_MASK2_ADDR(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x010)
++#define MAC_HASH_REQ_ENTRY(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x014)
++#define MAC_HASH_REQ_STATUS(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x018)
++#define MAC_HASH_REQ_ENTRY_MAYCH(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x01c)
++
++
++#define MAC_HASH_FREELIST_PTR_HEAD (MAC_HASH_BASE_ADDR + 0x100)
++#define MAC_HASH_FREELIST_PTR_TAIL (MAC_HASH_BASE_ADDR + 0x104)
++#define MAC_HASH_FREELIST_ENTRIES_ADDR (MAC_HASH_BASE_ADDR + 0x108)
++
++#endif /* _MAC_HASH_H_ */
++
+diff --git a/drivers/net/pfe_eth/pfe/class/perg.h b/drivers/net/pfe_eth/pfe/class/perg.h
+new file mode 100644
+index 0000000..7297171
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/class/perg.h
+@@ -0,0 +1,21 @@
++#ifndef _PERG_H_
++#define _PERG_H_
++
++#define PERG_QB_BUF_STATUS (PERG_BASE_ADDR + 0x00)
++#define PERG_RO_BUF_STATUS (PERG_BASE_ADDR + 0x04)
++#define PERG_CLR_QB_BUF_STATUS (PERG_BASE_ADDR + 0x08)
++#define PERG_SET_RO_BUF_STATUS (PERG_BASE_ADDR + 0x0c)
++#define PERG_CLR_RO_ERR_PKT (PERG_BASE_ADDR + 0x10)
++#define PERG_CLR_BMU2_ERR_PKT (PERG_BASE_ADDR + 0x14)
++
++#define PERG_ID (PERG_BASE_ADDR + 0x18)
++#define PERG_TIMER1 (PERG_BASE_ADDR + 0x1c)
++#define PERG_TIMER2 (PERG_BASE_ADDR + 0x20)
++#define PERG_BUF1 (PERG_BASE_ADDR + 0x24)
++#define PERG_BUF2 (PERG_BASE_ADDR + 0x28)
++#define PERG_HOST_GP (PERG_BASE_ADDR + 0x2c)
++#define PERG_PE_GP (PERG_BASE_ADDR + 0x30)
++#define PERG_INT_ENABLE (PERG_BASE_ADDR + 0x34)
++#define PERG_INT_SRC (PERG_BASE_ADDR + 0x38)
++
++#endif /* _PERG_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/class/vlan_hash.h b/drivers/net/pfe_eth/pfe/class/vlan_hash.h
+new file mode 100644
+index 0000000..a54ac19
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/class/vlan_hash.h
+@@ -0,0 +1,28 @@
++#ifndef _VLAN_HASH_H_
++#define _VLAN_HASH_H_
++
++#define VLAN_HASH_REQ1_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x000)
++#define VLAN_HASH_REQ2_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x020)
++#define VLAN_HASH_REQ3_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x040)
++#define VLAN_HASH_REQ4_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x060)
++#define VLAN_HASH_REQ5_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x080)
++#define VLAN_HASH_REQ6_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x0a0)
++#define VLAN_HASH_REQ7_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x0c0)
++#define VLAN_HASH_REQ8_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x0e0)
++
++#define VLAN_HASH_REQ_CMD(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x000)
++#define VLAN_HASH_REQ_MAC1_ADDR(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x004)
++#define VLAN_HASH_REQ_MAC2_ADDR(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x008)
++#define VLAN_HASH_REQ_MASK1_ADDR(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x00c)
++#define VLAN_HASH_REQ_MASK2_ADDR(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x010)
++#define VLAN_HASH_REQ_ENTRY(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x014)
++#define VLAN_HASH_REQ_STATUS(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x018)
++#define VLAN_HASH_REQ_ENTRY_MAYCH(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x01c)
++
++
++#define VLAN_HASH_FREELIST_PTR_HEAD (VLAN_HASH_BASE_ADDR + 0x100)
++#define VLAN_HASH_FREELIST_PTR_TAIL (VLAN_HASH_BASE_ADDR + 0x104)
++#define VLAN_HASH_FREELIST_ENTRIES_ADDR (VLAN_HASH_BASE_ADDR + 0x108)
++
++#endif /* _VLAN_HASH_H_ */
++
+diff --git a/drivers/net/pfe_eth/pfe/gpt.h b/drivers/net/pfe_eth/pfe/gpt.h
+new file mode 100644
+index 0000000..d820277
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/gpt.h
+@@ -0,0 +1,11 @@
++#ifndef _GPT_H_
++#define _GPT_H_
++
++#define GPT_VERSION (GPT_BASE_ADDR + 0x00)
++#define GPT_STATUS (GPT_BASE_ADDR + 0x04)
++#define GPT_CONFIG (GPT_BASE_ADDR + 0x08)
++#define GPT_COUNTER (GPT_BASE_ADDR + 0x0c)
++#define GPT_PERIOD (GPT_BASE_ADDR + 0x10)
++#define GPT_WIDTH (GPT_BASE_ADDR + 0x14)
++
++#endif /* _GPT_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/pe.h b/drivers/net/pfe_eth/pfe/pe.h
+new file mode 100644
+index 0000000..a3838f5
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/pe.h
+@@ -0,0 +1,147 @@
++#ifndef _PE_H_
++#define _PE_H_
++
++#include "hal.h"
++
++#define DDR_BASE_ADDR 0x00020000
++#define DDR_END 0x86000000 /* This includes ACP and IRAM areas */
++#define IRAM_BASE_ADDR 0x83000000
++
++#define IS_DDR(addr, len) (((unsigned long)(addr) >= DDR_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= DDR_END))
++
++typedef struct {
++
++} ddr_rx_hdr_t;
++
++typedef struct {
++
++} lmem_rx_hdr_t;
++
++
++typedef struct {
++
++} tmu_rx_hdr_t;
++
++typedef struct {
++
++} tmu_tx_hdr_t;
++
++typedef struct {
++
++} util_rx_hdr_t;
++
++
++struct pe_sync_mailbox
++{
++ u32 stop;
++ u32 stopped;
++};
++
++struct pe_msg_mailbox
++{
++ u32 dst;
++ u32 src;
++ u32 len;
++ u32 request;
++};
++
++/** Basic busy loop delay function
++*
++* @param cycles Number of cycles to delay (actual cpu cycles should be close to 3 x cycles)
++*
++*/
++static inline void delay(u32 cycles)
++{
++ volatile int i;
++
++ for (i = 0; i < cycles; i++);
++}
++
++
++/** Read PE id
++*
++* @return PE id (0 - 5 for CLASS-PE's, 6 - 9 for TMU-PE's, 10 for UTIL-PE)
++*
++*/
++static inline u32 esi_get_mpid(void)
++{
++ u32 mpid;
++
++ asm ("rcsr %0, Configuration, MPID" : "=d" (mpid));
++
++ return mpid;
++}
++
++/** 64bit aligned memory copy using efet.
++* Either the source or destination address must be in DMEM, the other address can be in LMEM or DDR.
++* Source, destination addresses and len must all be 64bit aligned.
++* Uses efet synchronous interface to copy the data.
++*
++* @param dst Destination address to write to (must be 64bit aligned)
++* @param src Source address to read from (must be 64bit aligned)
++* @param len Number of bytes to copy (must be 64bit aligned)
++*
++*/
++void efet_memcpy64(void *dst, void *src, unsigned int len);
++
++
++/** Aligned memory copy using efet.
++* Either the source or destination address must be in DMEM, the other address can be in LMEM or DDR.
++* Both the source and destination must have the same 64bit alignment, there is no restriction on length.
++*
++* @param dst Destination address to write to (must have the same 64bit alignment as src)
++* @param src Source address to read from (must have the same 64bit alignment as dst)
++* @param len Number of bytes to copy
++*
++*/
++void efet_memcpy(void *dst, void *src, unsigned int len);
++
++
++/** 32bit aligned memory copy.
++* Source and destination addresses must be 32bit aligned, there is no restriction on the length.
++*
++* @param dst Destination address (must be 32bit aligned)
++* @param src Source address (must be 32bit aligned)
++* @param len Number of bytes to copy
++*
++*/
++void memcpy_aligned32(void *dst, void *src, unsigned int len);
++
++/** Aligned memory copy.
++* Source and destination addresses must have the same alignment
++* relative to 32bit boundaries (but otherwsie may have any alignment),
++* there is no restriction on the length.
++*
++* @param dst Destination address
++* @param src Source address (must have same 32bit alignment as dst)
++* @param len Number of bytes to copy
++*
++*/
++void memcpy_aligned(void *dst, void *src, unsigned int len);
++
++
++/** Generic memory set.
++* Implements a generic memory set. Not very optimal (uses byte writes for the entire range)
++*
++*
++* @param dst Destination address
++* @param val Value to set memory to
++* @param len Number of bytes to set
++*
++*/
++void memset(void *dst, u8 val, unsigned int len);
++
++/** Generic memory copy.
++* Implements generic memory copy. If source and destination have the same
++* alignment memcpy_aligned() is used, otherwise, we first align the destination
++* to a 32bit boundary (using byte copies) then the src, and finally use a loop
++* of read, shift, write
++*
++* @param dst Destination address
++* @param src Source address
++* @param len Number of bytes to copy
++*
++*/
++void memcpy(void *dst, void *src, unsigned int len);
++
++#endif /* _PE_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/pfe.h b/drivers/net/pfe_eth/pfe/pfe.h
+new file mode 100644
+index 0000000..e8e2221
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/pfe.h
+@@ -0,0 +1,250 @@
++#ifndef _PFE_H_
++#define _PFE_H_
++
++#define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
++#define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) /* Only valid for mem access register interface */
++#define CLASS_DMEM_SIZE 0x00002000
++#define CLASS_IMEM_SIZE 0x00008000
++
++#define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
++#define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20)) /* Only valid for mem access register interface */
++#define TMU_DMEM_SIZE 0x00000800
++#define TMU_IMEM_SIZE 0x00002000
++
++#define UTIL_DMEM_BASE_ADDR 0x00000000
++#define UTIL_DMEM_SIZE 0x00002000
++
++#define PE_LMEM_BASE_ADDR 0xc3010000
++#define PE_LMEM_SIZE 0x8000
++#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
++
++#define DMEM_BASE_ADDR 0x00000000
++#define DMEM_SIZE 0x2000 /**< TMU has less... */
++#define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE)
++
++#define PMEM_BASE_ADDR 0x00010000
++#define PMEM_SIZE 0x8000 /**< TMU has less... */
++#define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE)
++
++
++/* Memory ranges check from PE point of view/memory map */
++#define IS_DMEM(addr, len) (((unsigned long)(addr) >= DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= DMEM_END))
++#define IS_PMEM(addr, len) (((unsigned long)(addr) >= PMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PMEM_END))
++#define IS_PE_LMEM(addr, len) (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PE_LMEM_END))
++
++#define IS_PFE_LMEM(addr, len) (((unsigned long)(addr) >= CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) && (((unsigned long)(addr) + (len)) <= CBUS_VIRT_TO_PFE(LMEM_END)))
++#define IS_PHYS_DDR(addr, len) (((unsigned long)(addr) >= PFE_DDR_PHYS_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PFE_DDR_PHYS_END))
++
++/* Host View Address */
++extern void *cbus_base_addr;
++extern void *ddr_base_addr;
++#define CBUS_BASE_ADDR cbus_base_addr
++#define DDR_BASE_ADDR ddr_base_addr
++
++/* PFE View Address */
++#define PFE_DDR_PHYS_BASE_ADDR 0x03800000 /**< DDR physical base address as seen by PE's. */
++#define PFE_DDR_PHYS_SIZE 0xC000000
++#define PFE_DDR_PHYS_END (PFE_DDR_PHYS_BASE_ADDR + PFE_DDR_PHYS_SIZE)
++#define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /**< CBUS physical base address as seen by PE's. */
++
++/* Host<->PFE Mapping */
++#define DDR_PFE_TO_VIRT(p) ((p ) + 0x80000000)
++#define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) + PFE_CBUS_PHYS_BASE_ADDR)
++#define CBUS_PFE_TO_VIRT(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)
++
++#include "cbus.h"
++
++enum {
++ CLASS0_ID = 0,
++ CLASS1_ID,
++ CLASS2_ID,
++ CLASS3_ID,
++#if !defined(CONFIG_PLATFORM_PCI)
++ CLASS4_ID,
++ CLASS5_ID,
++#endif
++#if !defined(CONFIG_TMU_DUMMY)
++ TMU0_ID,
++ TMU1_ID,
++ TMU2_ID,
++ TMU3_ID,
++#else
++ TMU0_ID,
++#endif
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++ UTIL_ID,
++#endif
++ MAX_PE
++};
++
++#if !defined(CONFIG_PLATFORM_PCI)
++#define CLASS_MASK ((1 << CLASS0_ID) | (1 << CLASS1_ID) | (1 << CLASS2_ID) | (1 << CLASS3_ID) | (1 << CLASS4_ID) | (1 << CLASS5_ID))
++#define CLASS_MAX_ID CLASS5_ID
++#else
++#define CLASS_MASK ((1 << CLASS0_ID) | (1 << CLASS1_ID) | (1 << CLASS2_ID) | (1 << CLASS3_ID))
++#define CLASS_MAX_ID CLASS3_ID
++#endif
++
++#if !defined(CONFIG_TMU_DUMMY)
++#if defined(CONFIG_LS1012A)
++#define TMU_MASK ((1 << TMU0_ID) | (1 << TMU1_ID) | (1 << TMU3_ID))
++#else
++#define TMU_MASK ((1 << TMU0_ID) | (1 << TMU1_ID) | (1 << TMU2_ID) | (1 << TMU3_ID))
++#endif
++#define TMU_MAX_ID TMU3_ID
++#else
++#define TMU_MASK (1 << TMU0_ID)
++#define TMU_MAX_ID TMU0_ID
++#endif
++
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++#define UTIL_MASK (1 << UTIL_ID)
++#endif
++
++struct pe_sync_mailbox
++{
++ u32 stop;
++ u32 stopped;
++};
++
++struct pe_msg_mailbox
++{
++ u32 dst;
++ u32 src;
++ u32 len;
++ u32 request;
++};
++
++/** PE information.
++ * Structure containing PE's specific information. It is used to create
++ * generic C functions common to all PE's.
++ * Before using the library functions this structure needs to be initialized with the different registers virtual addresses
++ * (according to the ARM MMU mmaping). The default initialization supports a virtual == physical mapping.
++ *
++ */
++struct pe_info
++{
++ u32 dmem_base_addr; /**< PE's dmem base address */
++ u32 pmem_base_addr; /**< PE's pmem base address */
++ u32 pmem_size; /**< PE's pmem size */
++
++ void *mem_access_wdata; /**< PE's _MEM_ACCESS_WDATA register address */
++ void *mem_access_addr; /**< PE's _MEM_ACCESS_ADDR register address */
++ void *mem_access_rdata; /**< PE's _MEM_ACCESS_RDATA register address */
++};
++
++
++void pe_lmem_read(u32 *dst, u32 len, u32 offset);
++void pe_lmem_write(u32 *src, u32 len, u32 offset);
++
++void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
++void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
++
++u32 pe_pmem_read(int id, u32 addr, u8 size);
++
++void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
++u32 pe_dmem_read(int id, u32 addr, u8 size);
++void class_bus_write(u32 val, u32 addr, u8 size);
++u32 class_bus_read(u32 addr, u8 size);
++void util_bus_write(u32 val, u32 addr, u8 size);
++u32 util_bus_read(u32 addr, u8 size);
++
++#define class_bus_readl(addr) class_bus_read(addr, 4)
++#define class_bus_readw(addr) class_bus_read(addr, 2)
++#define class_bus_readb(addr) class_bus_read(addr, 1)
++
++#define class_bus_writel(val, addr) class_bus_write(val, addr, 4)
++#define class_bus_writew(val, addr) class_bus_write(val, addr, 2)
++#define class_bus_writeb(val, addr) class_bus_write(val, addr, 1)
++
++#define pe_mem_readl(id, addr) pe_mem_read(id, addr, 4)
++#define pe_mem_readw(id, addr) pe_mem_read(id, addr, 2)
++#define pe_mem_readb(id, addr) pe_mem_read(id, addr, 1)
++
++#define pe_mem_writel(id, val, addr) pe_mem_write(id, val, addr, 4)
++#define pe_mem_writew(id, val, addr) pe_mem_write(id, val, addr, 2)
++#define pe_mem_writeb(id, val, addr) pe_mem_write(id, val, addr, 1)
++
++int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr);
++
++void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base);
++void bmu_init(void *base, BMU_CFG *cfg);
++void bmu_reset(void *base);
++void bmu_enable(void *base);
++void bmu_disable(void *base);
++void bmu_set_config(void *base, BMU_CFG *cfg);
++
++#if 0
++void gemac_init(void *base, void *config);
++void gemac_set_speed(void *base, MAC_SPEED gem_speed);
++void gemac_set_duplex(void *base, int duplex);
++void gemac_set_mode(void *base, int mode);
++void gemac_enable_mdio(void *base);
++void gemac_disable_mdio(void *base);
++void gemac_set_mdc_div(void *base, MAC_MDC_DIV gem_mdcdiv);
++void gemac_enable(void *base);
++void gemac_disable(void *base);
++void gemac_enable_mdio(void *base);
++void gemac_disable_mdio(void *base);
++void gemac_reset(void *base);
++void gemac_set_address(void *base, SPEC_ADDR *addr);
++SPEC_ADDR gemac_get_address(void *base);
++void gemac_set_laddr1(void *base, MAC_ADDR *address);
++void gemac_set_laddr2(void *base, MAC_ADDR *address);
++void gemac_set_laddr3(void *base, MAC_ADDR *address);
++void gemac_set_laddr4(void *base, MAC_ADDR *address);
++void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index);
++MAC_ADDR gem_get_laddr1(void *base);
++MAC_ADDR gem_get_laddr2(void *base);
++MAC_ADDR gem_get_laddr3(void *base);
++MAC_ADDR gem_get_laddr4(void *base);
++MAC_ADDR gem_get_laddrN(void *base, unsigned int entry_index);
++void gemac_set_config(void *base, GEMAC_CFG *cfg);
++void gemac_enable_copy_all(void *base);
++void gemac_disable_copy_all(void *base);
++void gemac_allow_broadcast(void *base);
++void gemac_no_broadcast(void *base);
++void gemac_enable_unicast(void *base);
++void gemac_disable_unicast(void *base);
++void gemac_enable_multicast(void *base);
++void gemac_disable_multicast(void *base);
++void gemac_enable_fcs_rx(void *base);
++void gemac_disable_fcs_rx(void *base);
++void gemac_enable_1536_rx(void *base);
++void gemac_disable_1536_rx(void *base);
++void gemac_enable_pause_rx(void *base);
++void gemac_disable_pause_rx(void *base);
++void gemac_enable_rx_checksum_offload(void *base);
++void gemac_disable_rx_checksum_offload(void *base);
++unsigned int * gemac_get_stats(void *base);
++void gemac_set_bus_width(void *base, int width);
++#endif
++
++void gpi_init(void *base, GPI_CFG *cfg);
++void gpi_reset(void *base);
++void gpi_enable(void *base);
++void gpi_disable(void *base);
++void gpi_set_config(void *base, GPI_CFG *cfg);
++
++void class_init(CLASS_CFG *cfg);
++void class_reset(void);
++void class_enable(void);
++void class_disable(void);
++void class_set_config(CLASS_CFG *cfg);
++
++void tmu_init(TMU_CFG *cfg);
++void tmu_enable(u32 pe_mask);
++void tmu_disable(u32 pe_mask);
++
++void util_init(UTIL_CFG *cfg);
++void util_reset(void);
++void util_enable(void);
++void util_disable(void);
++
++void hif_init(void);
++void hif_tx_enable(void);
++void hif_tx_disable(void);
++void hif_rx_enable(void);
++void hif_rx_disable(void);
++
++#endif /* _PFE_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/tmu.h b/drivers/net/pfe_eth/pfe/tmu.h
+new file mode 100644
+index 0000000..12eaf12
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/tmu.h
+@@ -0,0 +1,48 @@
++#ifndef _TMU_H_
++#define _TMU_H_
++
++#define TMU_DMEM_BASE_ADDR 0x00000000
++#define TMU_PMEM_BASE_ADDR 0x00010000
++
++
++#define CBUS_BASE_ADDR 0xc0000000
++#define TMU_APB_BASE_ADDR 0xc1000000
++
++#include "cbus.h"
++
++#define GPT_BASE_ADDR (TMU_APB_BASE_ADDR + 0x00000)
++#define UART_BASE_ADDR (TMU_APB_BASE_ADDR + 0x10000)
++
++
++#define SHAPER0_BASE_ADDR (TMU_APB_BASE_ADDR + 0x020000)
++#define SHAPER1_BASE_ADDR (TMU_APB_BASE_ADDR + 0x030000)
++#define SHAPER2_BASE_ADDR (TMU_APB_BASE_ADDR + 0x040000)
++#define SHAPER3_BASE_ADDR (TMU_APB_BASE_ADDR + 0x050000)
++#define SHAPER4_BASE_ADDR (TMU_APB_BASE_ADDR + 0x060000)
++#define SHAPER5_BASE_ADDR (TMU_APB_BASE_ADDR + 0x070000)
++#define SHAPER6_BASE_ADDR (TMU_APB_BASE_ADDR + 0x080000)
++#define SHAPER7_BASE_ADDR (TMU_APB_BASE_ADDR + 0x090000)
++#define SHAPER8_BASE_ADDR (TMU_APB_BASE_ADDR + 0x0a0000)
++#define SHAPER9_BASE_ADDR (TMU_APB_BASE_ADDR + 0x0b0000)
++
++#define SCHED0_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1c0000)
++#define SCHED1_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1d0000)
++#define SCHED2_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1e0000)
++#define SCHED3_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1f0000)
++#define SCHED4_BASE_ADDR (TMU_APB_BASE_ADDR + 0x200000)
++#define SCHED5_BASE_ADDR (TMU_APB_BASE_ADDR + 0x210000)
++#define SCHED6_BASE_ADDR (TMU_APB_BASE_ADDR + 0x220000)
++#define SCHED7_BASE_ADDR (TMU_APB_BASE_ADDR + 0x230000)
++
++
++#define PHY_QUEUE_BASE_ADDR (TMU_APB_BASE_ADDR + 0x260000)
++#define SHAPER_STATUS (TMU_APB_BASE_ADDR + 0x270000) /**< [9:0] bitmask of shapers that have positive credit */
++
++
++#include "gpt.h"
++#include "uart.h"
++#include "tmu/shaper.h"
++#include "tmu/sched.h"
++#include "tmu/phy_queue.h"
++
++#endif /* _TMU_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/tmu/phy_queue.h b/drivers/net/pfe_eth/pfe/tmu/phy_queue.h
+new file mode 100644
+index 0000000..9eef9a9
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/tmu/phy_queue.h
+@@ -0,0 +1,31 @@
++#ifndef _PHY_QUEUE_H_
++#define _PHY_QUEUE_H_
++
++#define PHY_QUEUE_SHAPER_STATUS (PHY_QUEUE_BASE_ADDR + 0x00) /**< [28:19] same as SHAPER_STATUS, [18:3] same as QUEUE_STATUS, [2:0] must be zero before a new packet may be dequeued */
++#define QUEUE_STATUS (PHY_QUEUE_BASE_ADDR + 0x04) /**< [15:0] bit mask of input queues with pending packets */
++
++#define QUEUE0_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x08)
++#define QUEUE1_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x0c)
++#define QUEUE2_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x10)
++#define QUEUE3_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x14)
++#define QUEUE4_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x18)
++#define QUEUE5_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x1c)
++#define QUEUE6_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x20)
++#define QUEUE7_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x24)
++#define QUEUE8_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x28)
++#define QUEUE9_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x2c)
++#define QUEUE10_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x30)
++#define QUEUE11_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x34)
++#define QUEUE12_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x38)
++#define QUEUE13_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x3c)
++#define QUEUE14_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x40)
++#define QUEUE15_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x44)
++#define QUEUE_RESULT0 (PHY_QUEUE_BASE_ADDR + 0x48) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY3), [6:0] winner input queue number */
++#define QUEUE_RESULT1 (PHY_QUEUE_BASE_ADDR + 0x4c) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY4), [6:0] winner input queue number */
++#define QUEUE_RESULT2 (PHY_QUEUE_BASE_ADDR + 0x50) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY5), [6:0] winner input queue number */
++#define QUEUE_GBL_PKTLEN (PHY_QUEUE_BASE_ADDR + 0x5c)
++#define QUEUE_GBL_PKTLEN_MASK (PHY_QUEUE_BASE_ADDR + 0x60)
++
++
++
++#endif /* _PHY_QUEUE_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/tmu/sched.h b/drivers/net/pfe_eth/pfe/tmu/sched.h
+new file mode 100644
+index 0000000..0c741cc
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/tmu/sched.h
+@@ -0,0 +1,47 @@
++#ifndef _SCHED_H_
++#define _SCHED_H_
++
++/* Offsets from SCHEDx_BASE_ADDR */
++#define SCHED_CTRL 0x00
++#define SCHED_SLOT_TIME 0x04
++#define SCHED_RES 0x08
++#define SCHED_QUEUE_ALLOC0 0x0c
++#define SCHED_QUEUE_ALLOC1 0x10
++#define SCHED_BW 0x14
++#define SCHED_GUR_DEF_CTR 0x18
++#define SCHED_AVL_CTR 0x1c
++#define SCHED_QU0_WGHT 0x20
++#define SCHED_QU1_WGHT 0x24
++#define SCHED_QU2_WGHT 0x28
++#define SCHED_QU3_WGHT 0x2c
++#define SCHED_QU4_WGHT 0x30
++#define SCHED_QU5_WGHT 0x34
++#define SCHED_QU6_WGHT 0x38
++#define SCHED_QU7_WGHT 0x3c
++#define SCHED_QUE0_DEFICIT_CNT 0x40
++#define SCHED_QUE1_DEFICIT_CNT 0x44
++#define SCHED_QUE2_DEFICIT_CNT 0x48
++#define SCHED_QUE3_DEFICIT_CNT 0x4c
++#define SCHED_QUE4_DEFICIT_CNT 0x50
++#define SCHED_QUE5_DEFICIT_CNT 0x54
++#define SCHED_QUE6_DEFICIT_CNT 0x58
++#define SCHED_QUE7_DEFICIT_CNT 0x5c
++#define SCHED_PKT_LEN 0x60
++
++#define SCHED_CTRL_ALGOTYPE(x) (((x) & 0xf) << 0)
++#define SCHED_CTRL_CALQUOTA(x) (((x) & 0x1) << 4)
++#define SCHED_CTRL_ACTIVE_Q(x) (((x) & 0xff) << 8)
++#define SCHED_CTRL_SHARE_BW(x) (((x) & 0xff) << 16)
++#define SCHED_CTRL_BARROW_BW(x) (((x) & 0xff) << 24)
++
++#define SCHED_QUEUE_ALLOC0_QUEUEA(x) (((x) & 0x1f) << 0)
++#define SCHED_QUEUE_ALLOC0_QUEUEB(x) (((x) & 0x1f) << 8)
++#define SCHED_QUEUE_ALLOC0_QUEUEC(x) (((x) & 0x1f) << 16)
++#define SCHED_QUEUE_ALLOC0_QUEUED(x) (((x) & 0x1f) << 24)
++
++#define SCHED_QUEUE_ALLOC0_RES0(x) (((x) & 0x7) << 5)
++#define SCHED_QUEUE_ALLOC0_RES1(x) (((x) & 0x7) << 13)
++#define SCHED_QUEUE_ALLOC0_RES2(x) (((x) & 0x7) << 21)
++#define SCHED_QUEUE_ALLOC0_RES3(x) (((x) & 0x7) << 29)
++
++#endif /* _SCHED_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/tmu/shaper.h b/drivers/net/pfe_eth/pfe/tmu/shaper.h
+new file mode 100644
+index 0000000..76315f3
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/tmu/shaper.h
+@@ -0,0 +1,19 @@
++#ifndef _SHAPER_H_
++#define _SHAPER_H_
++
++/* Offsets from SHAPPERx_BASE_ADDR */
++#define SHAPER_CTRL 0x00
++#define SHAPER_WEIGHT 0x04
++#define SHAPER_PKT_LEN 0x08
++
++#define SHAPER_CTRL_ENABLE(x) (((x) & 0x1) << 0)
++#define SHAPER_CTRL_QNO(x) (((x) & 0x3f) << 1)
++#define SHAPER_CTRL_CLKDIV(x) (((x) & 0xffff) << 16)
++
++#define SHAPER_WEIGHT_FRACWT(x) (((x) & 0xff) << 0)
++#define SHAPER_WEIGHT_INTWT(x) (((x) & 0x3) << 8)
++#define SHAPER_WEIGHT_MAXCREDIT(x) (((x) & 0x3fffff) << 10)
++
++#define PORT_SHAPER_MASK (1 << 0)
++
++#endif /* _SHAPER_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/uart.h b/drivers/net/pfe_eth/pfe/uart.h
+new file mode 100644
+index 0000000..483d446
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/uart.h
+@@ -0,0 +1,13 @@
++#ifndef _UART_H_
++#define _UART_H_
++
++#define UART_THR (UART_BASE_ADDR + 0x00)
++#define UART_IER (UART_BASE_ADDR + 0x04)
++#define UART_IIR (UART_BASE_ADDR + 0x08)
++#define UART_LCR (UART_BASE_ADDR + 0x0c)
++#define UART_MCR (UART_BASE_ADDR + 0x10)
++#define UART_LSR (UART_BASE_ADDR + 0x14)
++#define UART_MDR (UART_BASE_ADDR + 0x18)
++#define UART_SCRATCH (UART_BASE_ADDR + 0x1c)
++
++#endif /* _UART_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/util.h b/drivers/net/pfe_eth/pfe/util.h
+new file mode 100644
+index 0000000..fb2417c
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/util.h
+@@ -0,0 +1,30 @@
++#ifndef _UTIL_H_
++#define _UTIL_H_
++
++#define UTIL_DMEM_BASE_ADDR 0x00000000
++#define UTIL_DMEM_SIZE 0x00002000
++#define UTIL_DMEM_END (UTIL_DMEM_BASE_ADDR + UTIL_DMEM_SIZE)
++
++#define IS_DMEM(addr, len) (((unsigned long)(addr) >= UTIL_DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= UTIL_DMEM_END))
++
++#define CBUS_BASE_ADDR 0xc0000000
++#define UTIL_APB_BASE_ADDR 0xc1000000
++
++#include "cbus.h"
++
++#define GPT_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x00000)
++#define UART_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x10000)
++#define EAPE_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x20000)
++#define INQ_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x30000)
++#define EFET1_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x40000)
++#define EFET2_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x50000)
++#define EFET3_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x60000)
++
++
++#include "gpt.h"
++#include "uart.h"
++#include "util/eape.h"
++#include "util/inq.h"
++#include "util/efet.h"
++
++#endif /* _UTIL_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/util/eape.h b/drivers/net/pfe_eth/pfe/util/eape.h
+new file mode 100644
+index 0000000..07344dc
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/util/eape.h
+@@ -0,0 +1,10 @@
++#ifndef _EAPE_H_
++#define _EAPE_H_
++
++#define EAPE_STATUS (EAPE_BASE_ADDR + 0x0)
++#define EAPE_INT_ENABLE (EAPE_BASE_ADDR + 0x4)
++#define EAPE_INT_SRC (EAPE_BASE_ADDR + 0x8)
++#define EAPE_HOST_INT_ENABLE (EAPE_BASE_ADDR + 0xc)
++
++
++#endif /* _EAPE_H_ */
+diff --git a/drivers/net/pfe_eth/pfe/util/efet.h b/drivers/net/pfe_eth/pfe/util/efet.h
+new file mode 100644
+index 0000000..12d0310
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/util/efet.h
+@@ -0,0 +1,20 @@
++#ifndef _UTIL_EFET_H_
++#define _UTIL_EFET_H_
++
++#define EFET_ENTRY_ADDR 0x00
++#define EFET_ENTRY_SIZE 0x04
++#define EFET_ENTRY_DMEM_ADDR 0x08
++#define EFET_ENTRY_STATUS 0x0c
++#define EFET_ENTRY_ENDIAN 0x10
++
++#define CBUS2DMEM 0
++#define DMEM2CBUS 1
++
++#define EFET2BUS_LE (1 << 0)
++
++void util_efet(int i, u32 cbus_addr, u32 dmem_addr, u32 len, u8 dir);
++void util_efet_wait(int i);
++void util_efet_sync(int i, u32 cbus_addr, u32 dmem_addr, u32 len, u8 dir);
++
++#endif /* _UTIL_EFET_H_ */
++
+diff --git a/drivers/net/pfe_eth/pfe/util/inq.h b/drivers/net/pfe_eth/pfe/util/inq.h
+new file mode 100644
+index 0000000..73d1acb
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe/util/inq.h
+@@ -0,0 +1,10 @@
++#ifndef _INQ_H_
++#define _INQ_H_
++
++#define INQ_HOST_GP (INQ_BASE_ADDR + 0x00) /* FIXME what are these for ? */
++#define INQ_UPE_GP (INQ_BASE_ADDR + 0x04) /* FIXME what are these for ? */
++
++#define INQ_QB_PKTPTR (INQ_BASE_ADDR + 0x08)
++#define INQ_FIFO_CNT (INQ_BASE_ADDR + 0x0c)
++
++#endif /* _INQ_H_ */
+diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
+new file mode 100644
+index 0000000..ca00e98
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe_driver.c
+@@ -0,0 +1,710 @@
++/*
++ * (C) Copyright 2011
++ * Author : Mindspeed Technologes
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ * */
++
++
++#include "hal.h"
++#include "pfe/pfe.h"
++#include "pfe_driver.h"
++#include "pfe_firmware.h"
++
++
++static struct tx_desc_s *g_tx_desc = NULL;
++static struct rx_desc_s *g_rx_desc = NULL;
++
++#define wmb() asm volatile("dsb st" : : : "memory")
++
++/** HIF Rx interface function
++ * Reads the rx descriptor from the current location (rxToRead).
++ * - If the descriptor has a valid data/pkt, then get the data pointer
++ * - check for the input rx phy number
++ * - increments the rx data pointer by pkt_head_room_size
++ * - decrements the data length by pkt_head_room_size
++ * - handover the packet to caller.
++ *
++ * @param[out] pkt_ptr Pointer to store rx packet pointer
++ * @param[out] phy_port Pointer to store recv phy port
++ *
++ * @return -1 if no packet, else returns length of packet.
++ */
++int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
++{
++ struct rx_desc_s *rx_desc = g_rx_desc;
++ struct bufDesc *bd;
++ int len = -1;
++ //volatile u32 ctrl;
++ struct hif_header_s *hif_header;
++
++ bd = rx_desc->rxBase + rx_desc->rxToRead;
++
++ if (bd->ctrl & BD_CTRL_DESC_EN)
++ return len; //No pending Rx packet
++
++ /* this len include hif_header(8bytes) */
++ len = bd->ctrl & 0xFFFF;
++
++ hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(bd->data);
++
++
++ /* Get the recive port info from the packet */
++ dprint("Pkt recv'd: Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
++ hif_header, len, hif_header->port_no, bd->status);
++
++#if 0
++ {
++ int i;
++ unsigned char *p = (unsigned char *)hif_header;
++ for(i=0; i < len; i++) {
++ if(!(i % 16))
++ printf("\n");
++ printf(" %02x", p[i]);
++ }
++ printf("\n");
++ }
++#endif
++
++ *pkt_ptr = (unsigned int )(hif_header + 1);
++ *phy_port = hif_header->port_no;
++ len -= sizeof(struct hif_header_s);
++#if 0
++ /* reset bd control field */
++ ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR);
++ bd->ctrl = ctrl;
++ bd->status = 0;
++
++ rx_desc->rxToRead = (rx_desc->rxToRead + 1) & (rx_desc->rxRingSize - 1);
++
++ /* Give START_STROBE to BDP to fetch the descriptor __NOW__,
++ * BDP need not to wait for rx_poll_cycle time to fetch the descriptor,
++ * In idle state (ie., no rx pkt), BDP will not fetch
++ * the descriptor even if strobe is given(I think) */
++ writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
++#endif
++ return len;
++}
++
++void pfe_recv_ack(void)
++{
++ struct rx_desc_s *rx_desc = g_rx_desc;
++ struct bufDesc *bd;
++ volatile u32 ctrl;
++
++ bd = rx_desc->rxBase + rx_desc->rxToRead;
++
++ /* reset bd control field */
++ ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR);
++ bd->ctrl = ctrl;
++ bd->status = 0;
++
++ rx_desc->rxToRead = (rx_desc->rxToRead + 1) & (rx_desc->rxRingSize - 1);
++
++ /* Give START_STROBE to BDP to fetch the descriptor __NOW__,
++ * BDP need not to wait for rx_poll_cycle time to fetch the descriptor,
++ * In idle state (ie., no rx pkt), BDP will not fetch
++ * the descriptor even if strobe is given(I think) */
++ writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
++ return;
++}
++
++
++/** HIF Tx interface function
++ * This function sends a single packet to PFE from HIF interface.
++ * - No interrupt indication on tx completion.
++ * - After tx descriptor is updated and TX DMA is enabled.
++ * - To support both chipit and read c2k environment, data is copied to
++ * tx buffers. After verification this copied can be avoided.
++ *
++ * @param[in] phy_port Phy port number to send out this packet
++ * @param[in] data Pointer to the data
++ * @param[in] length Length of the ethernet packet to be transfered.
++ *
++ * @return -1 if tx Q is full, else returns the tx location where the pkt is placed.
++ */
++int pfe_send(int phy_port, void *data, int length)
++{
++ struct tx_desc_s *tx_desc = g_tx_desc;
++ struct bufDesc *bd;
++ struct hif_header_s hif_header;
++ u8 *tx_buf_va;
++ volatile u32 ctrl_word;
++
++ dprint("%s:pkt: %p, len: %d, txBase: %p, txToSend: %d\n", __func__,
++ data, length, tx_desc->txBase, tx_desc->txToSend);
++
++ bd = tx_desc->txBase + tx_desc->txToSend;
++
++ /* check queue-full condition */
++ if (bd->ctrl & BD_CTRL_DESC_EN) {
++ printf("Tx queue full\n");
++ return -1;
++ }
++
++ /* PFE checks for min pkt size */
++ if (length < MIN_PKT_SIZE) {
++ length = MIN_PKT_SIZE;
++ }
++
++ tx_buf_va = (u8 *)DDR_PFE_TO_VIRT(bd->data);
++ dprint("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va, bd->data);
++
++ /* Fill the gemac/phy port number to send this packet out */
++ memset(&hif_header, 0 , sizeof(struct hif_header_s));
++ hif_header.port_no = phy_port;
++
++ memcpy(tx_buf_va, (u8 *)&hif_header, sizeof(struct hif_header_s));
++ memcpy(tx_buf_va + sizeof(struct hif_header_s), data, length);
++ length += sizeof(struct hif_header_s);
++
++#if 0
++ {
++ int i;
++ unsigned char *p = (unsigned char *)tx_buf_va;
++ for(i=0; i < length; i++) {
++ if (!(i % 16)) printf("\n");
++ printf("%02x ", p[i]);
++ }
++ }
++#endif
++
++ dprint("before0: Tx Done, status: %08x, ctrl: %08x\n", bd->status, bd->ctrl);
++
++ /* fill the tx desc */
++ ctrl_word = (u32)(BD_CTRL_DESC_EN | BD_CTRL_LIFM | (length & 0xFFFF));
++ bd->ctrl = ctrl_word;
++ bd->status = 0;
++
++ /* NOTE: This code can be removed after verification */
++#if 1 //SRAM_RETENTION_BUG
++ ctrl_word = 0;
++ bd->status = 0xF0;
++ ctrl_word = bd->ctrl;
++ //printf("0: contrl word: %08x\n", ctrl_word);
++#endif
++ wmb();
++
++ /* Indicate Tx DMA to start fetching the Tx Descriptor,
++ * set START_STOBE */
++ //writel((readl(HIF_TX_CTRL) | HIF_TX_BDP_CH_START_WSTB), HIF_TX_CTRL);
++ //writel((readl(HIF_TX_CTRL) | (HIF_TX_DMA_EN | HIF_TX_BDP_CH_START_WSTB)), HIF_TX_CTRL);
++ writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_TX_CTRL);
++
++ udelay(100);
++
++ return tx_desc->txToSend;
++}
++
++/** HIF to check the Tx done
++ * This function will chceck the tx done indication of the current txToSend locations
++ * if success, moves the txToSend to next location.
++ *
++ * @return -1 if TX ownership bit is not cleared by hw.
++ else on success (tx done copletion) returns zero.
++ */
++int pfe_tx_done(void)
++{
++ struct tx_desc_s *tx_desc = g_tx_desc;
++ struct bufDesc *bd;
++ volatile u32 ctrl_word;
++
++ dprint("%s:txBase: %p, txToSend: %d\n", __func__, tx_desc->txBase, tx_desc->txToSend);
++
++ bd = tx_desc->txBase + tx_desc->txToSend;
++
++ /* check queue-full condition */
++ ctrl_word = bd->ctrl;
++ if (ctrl_word & BD_CTRL_DESC_EN)
++ return -1;
++
++ /* reset the control field */
++ bd->ctrl = 0;
++ //bd->data = (u32)NULL;
++ bd->status = 0;
++
++ dprint("Tx Done : status: %08x, ctrl: %08x\n", bd->status, bd->ctrl);
++
++ /* increment the txtosend index to next location */
++ tx_desc->txToSend = (tx_desc->txToSend + 1) & (tx_desc->txRingSize - 1);
++
++ dprint("Tx next pkt location: %d\n", tx_desc->txToSend);
++
++ return 0;
++}
++#if defined CONFIG_LS1024A
++/** GEMAC initialization
++ * Initializes the GEMAC registers.
++ *
++ * @param[in] gemac_base Pointer to GEMAC reg base
++ * @param[in] mode GEMAC mode to configure (MII config)
++ * @param[in] speed GEMAC speed
++ * @param[in] duplex
++ */
++void pfe_gemac_init(void *gemac_base, u32 mode, u32 speed, u32 duplex)
++{
++ GEMAC_CFG gemac_cfg = {
++ .mode = mode,
++ .speed = speed,
++ .duplex = duplex,
++ };
++
++ dprint("%s: gemac_base=%p\n", __func__, gemac_base);
++
++ gemac_init(gemac_base, &gemac_cfg);
++
++ //gemac_set_loop(gemac_base, LB_NONE);
++ //gemac_disable_copy_all(gemac_base);
++ //gemac_disable_rx_checksum_offload(gemac_base);
++
++ gemac_allow_broadcast(gemac_base);
++ gemac_disable_unicast(gemac_base); /* unicast hash disabled */
++ gemac_disable_multicast(gemac_base); /* multicast hash disabled */
++ gemac_disable_fcs_rx(gemac_base);
++ gemac_disable_1536_rx(gemac_base);
++ gemac_enable_pause_rx(gemac_base);
++ gemac_enable_rx_checksum_offload(gemac_base);
++}
++#endif
++/** Helper function to dump Rx descriptors.
++ */
++void hif_rx_desc_dump(void)
++{
++ struct bufDesc *bd_va;
++ int i;
++ struct rx_desc_s *rx_desc;
++
++ if (g_rx_desc == NULL) {
++ printf("%s: HIF Rx desc no init \n", __func__);
++ return;
++ }
++
++ rx_desc = g_rx_desc;
++ bd_va = rx_desc->rxBase;
++
++ printf("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rxBase, rx_desc->rxBase_pa);
++ for (i=0; i < rx_desc->rxRingSize; i++) {
++// printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
++// bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
++ bd_va++;
++ }
++}
++
++/** HIF Rx Desc initialization function.
++ */
++static int hif_rx_desc_init(struct pfe *pfe)
++{
++ u32 ctrl;
++ struct bufDesc *bd_va;
++ struct bufDesc *bd_pa;
++ struct rx_desc_s *rx_desc;
++ u32 rx_buf_pa;
++ int i;
++
++ /* sanity check */
++ if (g_rx_desc) {
++ printf("%s: HIF Rx desc re-init request\n", __func__);
++ return 0;
++ }
++
++ rx_desc = (struct rx_desc_s *)malloc(sizeof(struct rx_desc_s));
++ if (rx_desc == NULL) {
++ printf("%s:%d:Memory allocation failure\n", __func__, __LINE__);
++ return -1;
++ }
++ memset(rx_desc, 0 , sizeof(struct rx_desc_s));
++
++ /* init: Rx ring buffer */
++ rx_desc->rxRingSize = HIF_RX_DESC_NT;
++
++ /* NOTE: must be 64bit aligned */
++ bd_va = (struct bufDesc *)(pfe->ddr_baseaddr + RX_BD_BASEADDR);
++ bd_pa = (struct bufDesc *)(pfe->ddr_phys_baseaddr + RX_BD_BASEADDR);
++
++ rx_desc->rxBase = bd_va;
++ rx_desc->rxBase_pa = (unsigned long)bd_pa;
++
++ rx_buf_pa = pfe->ddr_phys_baseaddr + HIF_RX_PKT_DDR_BASEADDR;
++
++
++ printf("%s: Rx desc base: %p, base_pa: %08x, desc_count: %d\n",
++ __func__, rx_desc->rxBase, rx_desc->rxBase_pa, rx_desc->rxRingSize);
++
++ memset(bd_va, 0, sizeof(struct bufDesc) * rx_desc->rxRingSize);
++
++ ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
++ for (i=0; i < rx_desc->rxRingSize; i++) {
++ bd_va->next = (u32 )(bd_pa + 1);
++ bd_va->ctrl = ctrl;
++ bd_va->data = rx_buf_pa + (i * MAX_FRAME_SIZE);
++// printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
++// bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
++ bd_va++;
++ bd_pa++;
++ }
++ --bd_va;
++ bd_va->next = (u32 )rx_desc->rxBase_pa;
++
++ /* !!! This is a redundent information for h/w as we are also
++ maintaining next address in the buffer descriptor
++ Posedge: reference code does not using this bit to go back to base address */
++ //bd->ctrl |= BD_CTRL_LAST_BD;
++
++ writel(rx_desc->rxBase_pa, HIF_RX_BDP_ADDR);
++ writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
++
++ g_rx_desc = rx_desc;
++
++ return 0;
++}
++
++/** Helper function to dump Tx Descriptors.
++ */
++void hif_tx_desc_dump(void)
++{
++ struct tx_desc_s *tx_desc;
++ int i;
++ struct bufDesc *bd_va;
++
++ if (g_tx_desc == NULL) {
++ printf("%s: HIF Tx desc no init \n", __func__);
++ return;
++ }
++
++ tx_desc = g_tx_desc;
++ bd_va = tx_desc->txBase;
++
++ printf("HIF tx desc: base_va: %p, base_pa: %08x\n", tx_desc->txBase, tx_desc->txBase_pa);
++ for (i=0; i < tx_desc->txRingSize; i++) {
++// printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
++// bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
++ bd_va++;
++ }
++}
++
++/** HIF Tx descriptor initialization function.
++ */
++static int hif_tx_desc_init(struct pfe *pfe)
++{
++ struct bufDesc *bd_va;
++ struct bufDesc *bd_pa;
++ int i;
++ struct tx_desc_s *tx_desc;
++ u32 tx_buf_pa;
++
++ /* sanity check */
++ if (g_tx_desc) {
++ printf("%s: HIF Tx desc re-init request\n", __func__);
++ return 0;
++ }
++
++ tx_desc = (struct tx_desc_s *)malloc(sizeof(struct tx_desc_s));
++ if (tx_desc == NULL) {
++ printf("%s:%d:Memory allocation failure\n", __func__, __LINE__);
++ return -1;
++ }
++ memset(tx_desc, 0 , sizeof(struct tx_desc_s));
++
++ /* init: Tx ring buffer */
++ tx_desc->txRingSize = HIF_TX_DESC_NT;
++ /* NOTE: must be 64bit aligned */
++ bd_va = (struct bufDesc *)(pfe->ddr_baseaddr + TX_BD_BASEADDR);
++ bd_pa = (struct bufDesc *)(pfe->ddr_phys_baseaddr + TX_BD_BASEADDR);
++
++ tx_desc->txBase_pa = (unsigned long)bd_pa;
++ tx_desc->txBase = bd_va;
++
++ printf("%s: Tx desc_base: %p, base_pa: %08x, desc_count: %d\n",
++ __func__, tx_desc->txBase, tx_desc->txBase_pa, tx_desc->txRingSize);
++
++ memset(bd_va, 0, sizeof(struct bufDesc) * tx_desc->txRingSize);
++
++ tx_buf_pa = pfe->ddr_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR;
++
++ for (i=0; i < tx_desc->txRingSize; i++) {
++ bd_va->next = (u32 )(bd_pa + 1);
++ bd_va->data = tx_buf_pa + (i * MAX_FRAME_SIZE);
++// printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
++// bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
++ bd_va++;
++ bd_pa++;
++ }
++ --bd_va;
++ bd_va->next = (u32 )tx_desc->txBase_pa;
++// printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
++// bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
++
++ /* !!! This is a redundent information for h/w as we are also
++ maintaining next address in the buffer descriptor,
++ Posedge: reference code does not using LAST_BD for moving back to base address */
++ //bd->ctrl |= BD_CTRL_LAST_BD;
++
++ writel(tx_desc->txBase_pa, HIF_TX_BDP_ADDR);
++
++ g_tx_desc = tx_desc;
++
++ return 0;
++}
++
++/** PFE/Class initialization.
++ */
++static void pfe_class_init(struct pfe *pfe)
++{
++ CLASS_CFG class_cfg = {
++ .route_table_baseaddr = pfe->ddr_phys_baseaddr + ROUTE_TABLE_BASEADDR,
++ .route_table_hash_bits = ROUTE_TABLE_HASH_BITS,
++ };
++
++ class_init(&class_cfg);
++ printf("class init complete\n");
++}
++
++/** PFE/TMU initialization.
++ */
++static void pfe_tmu_init(struct pfe *pfe)
++{
++ TMU_CFG tmu_cfg = {
++ .llm_base_addr = pfe->ddr_phys_baseaddr + TMU_LLM_BASEADDR,
++ .llm_queue_len = TMU_LLM_QUEUE_LEN,
++ };
++
++ tmu_init(&tmu_cfg);
++ printf("tmu init complete\n");
++}
++
++/** PFE/BMU (both BMU1 & BMU2) initialization.
++ */
++static void pfe_bmu_init(struct pfe *pfe)
++{
++ BMU_CFG bmu1_cfg = {
++ .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR + BMU1_LMEM_BASEADDR),
++ .count = BMU1_BUF_COUNT,
++ .size = BMU1_BUF_SIZE,
++ };
++
++ BMU_CFG bmu2_cfg = {
++ .baseaddr = pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR,
++ .count = BMU2_BUF_COUNT,
++ .size = BMU2_BUF_SIZE,
++ };
++
++ bmu_init(BMU1_BASE_ADDR, &bmu1_cfg);
++ printf("bmu1 init: done\n");
++
++ bmu_init(BMU2_BASE_ADDR, &bmu2_cfg);
++ printf("bmu2 init: done\n");
++}
++
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++/** PFE/Util initialization function.
++ */
++static void pfe_util_init(struct pfe *pfe)
++{
++ UTIL_CFG util_cfg = { };
++
++ util_init(&util_cfg);
++ printf("util init complete\n");
++}
++#endif
++
++/** PFE/GPI initialization function.
++ * - egpi1, egpi2, egpi3, hgpi
++ */
++static void pfe_gpi_init(struct pfe *pfe)
++{
++ GPI_CFG egpi1_cfg = {
++ .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,
++ .tmlf_txthres = EGPI1_TMLF_TXTHRES,
++ .aseq_len = EGPI1_ASEQ_LEN,
++ };
++
++ GPI_CFG egpi2_cfg = {
++ .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,
++ .tmlf_txthres = EGPI2_TMLF_TXTHRES,
++ .aseq_len = EGPI2_ASEQ_LEN,
++ };
++
++#if 0
++ GPI_CFG egpi3_cfg = {
++ .lmem_rtry_cnt = EGPI3_LMEM_RTRY_CNT,
++ .tmlf_txthres = EGPI3_TMLF_TXTHRES,
++ .aseq_len = EGPI3_ASEQ_LEN,
++ };
++#endif
++
++ GPI_CFG hgpi_cfg = {
++ .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,
++ .tmlf_txthres = HGPI_TMLF_TXTHRES,
++ .aseq_len = HGPI_ASEQ_LEN,
++ };
++
++ gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);
++ printf("GPI1 init complete\n");
++
++ gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);
++ printf("GPI2 init complete\n");
++
++#if 0
++ gpi_init(EGPI3_BASE_ADDR, &egpi3_cfg);
++#endif
++
++ gpi_init(HGPI_BASE_ADDR, &hgpi_cfg);
++ printf("HGPI init complete\n");
++}
++
++
++/** PFE/HIF initialization function.
++ */
++static void pfe_hif_init(struct pfe *pfe)
++{
++ hif_tx_disable();
++ hif_rx_disable();
++
++ hif_tx_desc_init(pfe);
++ hif_rx_desc_init(pfe);
++
++ hif_init();
++
++ hif_tx_enable();
++ hif_rx_enable();
++
++ hif_rx_desc_dump();
++ hif_tx_desc_dump();
++
++ printf("HIF init complete\n");
++}
++
++/** PFE initialization
++ * - Firmware loading (CLASS-PE and TMU-PE)
++ * - BMU1 and BMU2 init
++ * - GEMAC init
++ * - GPI init
++ * - CLASS-PE init
++ * - TMU-PE init
++ * - HIF tx and rx descriptors init
++ *
++ * @param[in] edev Pointer to eth device structure.
++ *
++ * @return 0, on success.
++ */
++static int pfe_hw_init(struct pfe *pfe)
++{
++
++ dprint("%s: start \n", __func__);
++#if defined (CONFIG_LS1012A)
++ /*This clock workaround needed for LS1012 */
++ writel(0x3, CLASS_PE_SYS_CLK_RATIO);
++ writel(0x3, TMU_PE_SYS_CLK_RATIO);
++ writel(0x3, UTIL_PE_SYS_CLK_RATIO);
++ udelay(10);
++#endif
++
++ pfe_class_init(pfe);
++
++ pfe_tmu_init(pfe);
++
++ pfe_bmu_init(pfe);
++
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++ pfe_util_init(pfe);
++#endif
++
++ pfe_gpi_init(pfe);
++
++ pfe_hif_init(pfe);
++
++ bmu_enable(BMU1_BASE_ADDR);
++ printf("bmu1 enabled\n");
++
++ bmu_enable(BMU2_BASE_ADDR);
++ printf("bmu2 enabled\n");
++
++ printf("%s: done\n", __func__);
++
++ /* NOTE: Load PE specific data (if any) */
++
++ return 0;
++}
++
++
++/** PFE probe function.
++ * - Initializes pfe_lib
++ * - pfe hw init
++ * - fw loading and enables PEs
++ * - should be executed once.
++ *
++ * @param[in] pfe Pointer the pfe control block
++ */
++int pfe_probe(struct pfe *pfe)
++{
++ static int init_done = 0;
++
++ if (init_done)
++ return 0;
++
++ printf("cbus_baseaddr: %p, ddr_baseaddr: %p, ddr_phys_baseaddr: %08x\n",
++ pfe->cbus_baseaddr, pfe->ddr_baseaddr, (u32)pfe->ddr_phys_baseaddr);
++
++ pfe_lib_init(pfe->cbus_baseaddr, pfe->ddr_baseaddr, pfe->ddr_phys_baseaddr);
++
++
++ pfe_hw_init(pfe);
++
++ /* Load the class,TM, Util fw
++ * by now pfe is,
++ * - out of reset + disabled + configured,
++ * Fw loading should be done after pfe_hw_init() */
++#ifdef CONFIG_CMD_PFE_START
++ /* It loads firmware from DDR locations Class@0x100000 TMU@0x180000 UTIL@200000*/
++ //For this firmware should be preloaded in DDR
++ //pfe_firmware_init((u8 *)0x80100000, (u8 *)0x80180000, 0x80200000);
++ pfe_firmware_init(NULL, NULL, NULL);
++#else
++ /*It loads default inbuilt sbl firmware */
++ pfe_firmware_init(NULL, NULL, NULL);
++#endif
++
++ init_done = 1;
++
++ return 0;
++}
++
++
++/** PFE remove function
++ * - stopes PEs
++ * - frees tx/rx descriptor resources
++ * - should be called once.
++ *
++ * @param[in] pfe Pointer to pfe control block.
++ */
++int pfe_remove(struct pfe *pfe)
++{
++ if (g_tx_desc) {
++ free(g_tx_desc);
++ }
++
++ if (g_rx_desc) {
++ free(g_rx_desc);
++ }
++
++ pfe_firmware_exit();
++
++ return 0;
++}
++
+diff --git a/drivers/net/pfe_eth/pfe_driver.h b/drivers/net/pfe_eth/pfe_driver.h
+new file mode 100644
+index 0000000..4d2e8b6
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe_driver.h
+@@ -0,0 +1,141 @@
++/*
++ * (C) Copyright 2011
++ * Author : Mindspeed Technologes
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ * */
++
++#ifndef __PFE_DRIVER_H__
++#define __PFE_DRIVER_H__
++
++#include "hal.h"
++
++#include "pfe/pfe.h"
++#include "pfe/cbus.h"
++#include "pfe/cbus/bmu.h"
++
++
++
++typedef struct bufDesc {
++ volatile u32 ctrl;
++ volatile u32 status;
++ volatile u32 data;
++ volatile u32 next;
++ // struct bufDesc *next;
++}__attribute__((packed)) bufDesc_t;
++
++#if defined(CONFIG_PLATFORM_PCI)
++#define HIF_RX_DESC_NT 4
++#define HIF_TX_DESC_NT 4
++#else
++#define HIF_RX_DESC_NT 64
++#define HIF_TX_DESC_NT 64
++#endif
++#define RX_BD_BASEADDR (HIF_DESC_BASEADDR)
++#define TX_BD_BASEADDR (HIF_DESC_BASEADDR + HIF_TX_DESC_SIZE)
++
++#define MIN_PKT_SIZE 56
++#define MAX_FRAME_SIZE 2048
++
++
++typedef struct hif_header_s {
++ u8 port_no; //Carries input port no for host rx packets and output port no for tx pkts
++ u8 reserved0;
++ u32 reserved2;
++} __attribute__((packed)) hif_header_t;
++
++
++typedef struct rx_desc_s {
++ struct bufDesc *rxBase;
++ unsigned int rxBase_pa;
++ int rxToRead;
++ int rxRingSize;
++}rx_desc_t;
++
++typedef struct tx_desc_s {
++ struct bufDesc *txBase;
++ unsigned int txBase_pa;
++ int txToSend;
++ int txRingSize;
++}tx_desc_t;
++
++
++/* The set of statistics registers implemented in the Cadence MAC.
++ * The statistics registers implemented are a subset of all the statistics
++ * available, but contains all the compulsory ones.
++ */
++typedef struct gem_stats{
++ u32 octets_tx_bot; /* Lower 32-bits for number of octets tx'd */
++ u32 octets_tx_top; /* Upper 16-bits for number of octets tx'd */
++ u32 frames_tx; /* Number of frames transmitted OK */
++ u32 broadcast_tx; /* Number of broadcast frames transmitted */
++ u32 multicast_tx; /* Number of multicast frames transmitted */
++ u32 pause_tx; /* Number of pause frames transmitted. */
++ u32 frame64_tx; /* Number of 64byte frames transmitted */
++ u32 frame65_127_tx; /* Number of 65-127 byte frames transmitted */
++ u32 frame128_255_tx; /* Number of 128-255 byte frames transmitted */
++ u32 frame256_511_tx; /* Number of 256-511 byte frames transmitted */
++ u32 frame512_1023_tx; /* Number of 512-1023 byte frames transmitted */
++ u32 frame1024_1518_tx; /* Number of 1024-1518 byte frames transmitted*/
++ u32 frame1519_tx; /* Number of frames greater than 1518 bytes tx*/
++ u32 tx_urun; /* Transmit underrun errors due to DMA */
++ u32 single_col; /* Number of single collision frames */
++ u32 multi_col; /* Number of multi collision frames */
++ u32 excess_col; /* Number of excessive collision frames. */
++ u32 late_col; /* Collisions occuring after slot time */
++ u32 def_tx; /* Frames deferred due to crs */
++ u32 crs_errors; /* Errors caused by crs not being asserted. */
++ u32 octets_rx_bot; /* Lower 32-bits for number of octets rx'd */
++ u32 octets_rx_top; /* Upper 16-bits for number of octets rx'd */
++ u32 frames_rx; /* Number of frames received OK */
++ u32 broadcast_rx; /* Number of broadcast frames received */
++ u32 multicast_rx; /* Number of multicast frames received */
++ u32 pause_rx; /* Number of pause frames received. */
++ u32 frame64_rx; /* Number of 64byte frames received */
++ u32 frame65_127_rx; /* Number of 65-127 byte frames received */
++ u32 frame128_255_rx; /* Number of 128-255 byte frames received */
++ u32 frame256_511_rx; /* Number of 256-511 byte frames received */
++ u32 frame512_1023_rx; /* Number of 512-1023 byte frames received */
++ u32 frame1024_1518_rx; /* Number of 1024-1518 byte frames received*/
++ u32 frame1519_rx; /* Number of frames greater than 1518 bytes rx*/
++ u32 usize_frames; /* Frames received less than min of 64 bytes */
++ u32 excess_length; /* Number of excessive length frames rx */
++ u32 jabbers; /* Excessive length + crc or align errors. */
++ u32 fcs_errors; /* Number of frames received with crc errors */
++ u32 length_check_errors;/* Number of frames with incorrect length */
++ u32 rx_symbol_errors; /* Number of times rx_er asserted during rx */
++ u32 align_errors; /* Frames received without integer no. bytes */
++ u32 rx_res_errors; /* Number of times buffers ran out during rx */
++ u32 rx_orun; /* Receive overrun errors due to DMA */
++ u32 ip_cksum; /* IP header checksum errors */
++ u32 tcp_cksum; /* TCP checksum errors */
++ u32 udp_cksum; /* UDP checksum errors */
++} volatile GEM_STATS;
++
++
++int pfe_send(int phy_port, void *data, int length);
++int pfe_recv(unsigned int *pkt_ptr, int *phy_port);
++void pfe_recv_ack(void);
++int pfe_tx_done(void);
++void pfe_gem_enable_all(void);
++void pfe_gemac_init(void *gemac_base, u32 mode, u32 speed, u32 duplex);
++
++
++#endif
++
+diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
+new file mode 100644
+index 0000000..40ac095
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe_eth.c
+@@ -0,0 +1,521 @@
++#include <common.h>
++#include <config.h>
++//#include <asm/arch/hardware.h>
++#include <asm/byteorder.h>
++#include <net.h>
++#include <command.h>
++#include <miiphy.h>
++#include "pfe_eth.h"
++
++struct gemac_s gem_info[] = {
++ /* PORT_0 configuration */
++ {
++ /* GEMAC config */
++ .gemac_mode = GMII,
++ .gemac_speed = SPEED_1000M,
++ .gemac_duplex = DUPLEX_FULL,
++
++ /* phy iface */
++ .phy_address = EMAC1_PHY_ADDR,
++ .phy_mode = PHY_INTERFACE_MODE_SGMII,
++ },
++ /* PORT_1 configuration */
++ {
++ /* GEMAC config */
++ .gemac_mode = GMII,
++ .gemac_speed = SPEED_1000M,
++ .gemac_duplex = DUPLEX_FULL,
++
++ /* phy iface */
++ .phy_address = EMAC2_PHY_ADDR,
++ .phy_mode = PHY_INTERFACE_MODE_RGMII,
++ },
++};
++
++#define MAX_GEMACS 2
++
++static struct ls1012a_eth_dev *gemac_list[MAX_GEMACS];
++
++/* Max MII register/address (we support) */
++#define MII_REGISTER_MAX 31
++#define MII_ADDRESS_MAX 31
++
++#define MDIO_TIMEOUT 5000
++
++
++static void ls1012a_gemac_enable(void *gemac_base)
++{
++ writel(readl(gemac_base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
++}
++
++static void ls1012a_gemac_dsable(void *gemac_base)
++{
++ writel(readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
++}
++
++static void ls1012a_gemac_set_mode(void *gemac_base, u32 mode)
++{
++}
++
++static void ls1012a_gemac_set_speed(void *gemac_base, u32 speed)
++{
++ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
++ u32 ecr = readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
++ u32 rcr = readl(gemac_base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
++ u32 rgmii_pcr = in_be32(&scfg->rgmiipcr) & ~(SCFG_RGMIIPCR_SETSP_1000M|SCFG_RGMIIPCR_SETSP_10M);
++
++ if (speed == _1000BASET) {
++ ecr |= EMAC_ECNTRL_SPEED;
++ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M;
++ }
++ else if (speed != _100BASET){
++ rcr |= EMAC_RCNTRL_RMII_10T;
++ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M;
++ }
++
++ writel(ecr, gemac_base + EMAC_ECNTRL_REG);
++ out_be32(&scfg->rgmiipcr, rgmii_pcr | SCFG_RGMIIPCR_SETFD);
++
++ /* remove loop back */
++ rcr &= ~EMAC_RCNTRL_LOOP;
++ /* enable flow control */
++ rcr |= EMAC_RCNTRL_FCE;
++
++ /* Enable MII mode */
++ rcr |= EMAC_RCNTRL_MII_MODE;
++
++ /* CRC field is stripped from the frame */
++ //rcr |= EMAC_RCNTRL_CRC_FWD;
++
++ /* Enable promiscuous mode
++ FIXME should be removed later*/
++ //rcr |= EMAC_RCNTRL_PROM;
++ writel(rcr, gemac_base + EMAC_RCNTRL_REG);
++
++ /*Enable Tx full duplex */
++ writel(readl(gemac_base + EMAC_TCNTRL_REG ) | EMAC_TCNTRL_FDEN, gemac_base + EMAC_TCNTRL_REG);
++
++}
++
++static void ls1012a_gemac_set_ethaddr(void *gemac_base, uchar *mac)
++{
++ writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], gemac_base + EMAC_PHY_ADDR_LOW);
++ writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, gemac_base + EMAC_PHY_ADDR_HIGH);
++}
++
++/** Stops or Disables GEMAC pointing to this eth iface.
++ *
++ * @param[in] edev Pointer to eth device structure.
++ *
++ * @return none
++ */
++static void ls1012a_eth_halt(struct eth_device *edev)
++{
++ struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)edev->priv;
++
++ ls1012a_gemac_enable(priv->gem->gemac_base);
++
++ gpi_disable(priv->gem->egpi_base);
++
++ return;
++}
++
++static int ls1012a_eth_init(struct eth_device *dev, bd_t * bd)
++{
++ struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)dev->priv;
++ struct gemac_s *gem = priv->gem;
++ int speed;
++ int tmp;
++
++ /* set ethernet mac address */
++ ls1012a_gemac_set_ethaddr(gem->gemac_base, dev->enetaddr);
++
++ //MAC will be always in GMII mode, it doesn't change with the link speed.
++ //ls1012a_gemac_set_mode(gem->gemac_base, gem->gemac_mode);
++
++ writel(0x00000004, gem->gemac_base + EMAC_TFWR_STR_FWD);
++ writel(0x00000005, gem->gemac_base + EMAC_RX_SECTIOM_FULL);
++ writel(0x00003fff, gem->gemac_base + EMAC_TRUNC_FL);
++ writel(0x00000030, gem->gemac_base + EMAC_TX_SECTION_EMPTY);
++ writel(0x00000000, gem->gemac_base + EMAC_MIB_CTRL_STS_REG);
++
++#ifndef CONFIG_EMU
++#ifdef CONFIG_PHYLIB
++ /* Start up the PHY */
++ //if(gem->phy_mode != PHY_INTERFACE_MODE_SGMII) {
++ if (phy_startup(priv->phydev)) {
++ printf("Could not initialize PHY %s\n",
++ priv->phydev->dev->name);
++ return -1;
++ }
++ speed = priv->phydev->speed;
++ printf("Speed detected %x\n", speed);
++ if(priv->phydev->duplex == DUPLEX_HALF) {
++ printf("Half duplex not supported \n");
++ return -1;
++ }
++#endif
++#else
++ /*in emulator it is always 1000Mbps */
++ speed = _1000BASET;
++#endif
++ ls1012a_gemac_set_speed(gem->gemac_base, speed);
++
++ /* Enable GPI */
++ gpi_enable(gem->egpi_base);
++
++ /* Enable GEMAC */
++ ls1012a_gemac_enable(gem->gemac_base);
++
++ return 0;
++
++}
++
++static int ls1012a_eth_send(struct eth_device *dev, void *data, int length)
++{
++ struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)dev->priv;
++
++ int rc;
++ int i=0;
++
++ rc = pfe_send(priv->gemac_port, data, length);
++
++ if (rc < 0) {
++ printf("Tx Q full\n");
++ return 0;
++ }
++
++ while (1) {
++ rc = pfe_tx_done();
++ if (rc == 0)
++ break;
++
++ udelay(100);
++ i++;
++ if(i == 30000)
++ printf("Tx timeout, send failed\n");
++ break;
++
++ }
++
++ return 0;
++}
++
++static int ls1012a_eth_recv(struct eth_device *dev)
++{
++ struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)dev->priv;
++ u32 pkt_buf;
++ int len;
++ int phy_port;
++
++ len = pfe_recv(&pkt_buf, &phy_port);
++
++ if (len < 0)
++ return 0; //no packet in rx
++
++ dprint("Rx pkt: pkt_buf(%08x), phy_port(%d), len(%d)\n", pkt_buf, phy_port, len);
++ if (phy_port != priv->gemac_port) {
++ printf("Rx pkt not on expected port\n");
++ pfe_recv_ack();
++ return 0;
++ }
++
++ // Pass the packet up to the protocol layers.
++ net_process_received_packet((uchar *)pkt_buf, len);
++
++ pfe_recv_ack();
++ return 0;
++}
++
++#if defined(CONFIG_PHYLIB)
++
++#define MDIO_TIMEOUT 5000
++static int ls1012a_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, int reg_addr)
++{
++ void *reg_base = bus->priv;
++ u32 reg;
++ u32 phy;
++ u32 reg_data;
++ u16 val;
++ int timeout = MDIO_TIMEOUT;
++
++ reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT);
++ phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
++
++ reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD | EMAC_MII_DATA_TA | phy | reg );
++
++ //dprint("%s write data %x %x %x\n", __func__, reg_data, reg_addr, phy_addr);
++ writel(reg_data, reg_base + EMAC_MII_DATA_REG);
++
++ /*
++ * wait for the MII interrupt
++ */
++ while(!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII))
++ {
++ if (timeout-- <= 0) {
++ printf("Phy MDIO read/write timeout\n");
++ return -1;
++ }
++ }
++
++ /*
++ * clear MII interrupt
++ */
++ writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
++
++ /*
++ * it's now safe to read the PHY's register
++ */
++ val = (u16)readl(reg_base + EMAC_MII_DATA_REG);
++ dprint("%s: %x phy: %02x reg:%02x val:%#x\n", __func__, reg_base, phy_addr, reg_addr, val);
++
++ return val;
++}
++
++static int ls1012a_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, int reg_addr, u16 data)
++{
++ void *reg_base = bus->priv;
++ u32 reg;
++ u32 phy;
++ u32 reg_data;
++ int timeout = MDIO_TIMEOUT;
++ int val;
++
++ reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT);
++ phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
++
++ reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR | EMAC_MII_DATA_TA | phy | reg | data);
++
++ //dprint("%s write data %x\n", __func__, reg_data);
++ writel(reg_data, reg_base + EMAC_MII_DATA_REG);
++
++ /*
++ * wait for the MII interrupt
++ */
++ while(!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII))
++ {
++ if (timeout-- <= 0) {
++ printf("Phy MDIO read/write timeout\n");
++ return -1;
++ }
++ }
++
++ /*
++ * clear MII interrupt
++ */
++ writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
++
++ dprint("%s: phy: %02x reg:%02x val:%#x\n", __func__, phy_addr, reg_addr, data);
++
++ return val;
++}
++
++
++struct mii_dev *ls1012a_mdio_init(struct mdio_info *mdio_info)
++{
++ struct mii_dev *bus;
++ int ret;
++ u32 mdio_speed;
++ u32 pclk = 250000000;
++
++ bus = mdio_alloc();
++ if (!bus) {
++ printf("mdio_alloc failed\n");
++ return NULL;
++ }
++ bus->read = ls1012a_phy_read;
++ bus->write = ls1012a_phy_write;
++ /* MAC1 MDIO used to communicate with external PHYS */
++ bus->priv = mdio_info->reg_base;
++ sprintf(bus->name, mdio_info->name);
++
++ /*configure mdio speed */
++ mdio_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT);
++ mdio_speed |= EMAC_HOLDTIME(0x4);
++ writel(mdio_speed, mdio_info->reg_base + EMAC_MII_CTRL_REG);
++
++ ret = mdio_register(bus);
++ if (ret) {
++ printf("mdio_register failed\n");
++ free(bus);
++ return NULL;
++ }
++ return bus;
++}
++
++static void ls1012a_configure_serdes(struct ls1012a_eth_dev *priv)
++{
++ struct mii_dev bus;
++ int value,sgmii_2500=0;
++
++ printf("%s %d\n", __func__, priv->gemac_port);
++ /* PCS configuration done with corresponding GEMAC */
++ bus.priv = priv->gem->gemac_base;
++
++ ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0);
++ ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1);
++ ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x2);
++ ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x3);
++#if 0
++ /*These settings taken from validtion team */
++ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x8000);
++ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, 0xb); //3 in case our code
++ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, 0x1a1);
++ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0x400);
++ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x0);
++ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x1140);
++ return;
++#endif
++
++ /*Reset serdes */
++ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x8000);
++
++ /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
++ value = PHY_SGMII_IF_MODE_SGMII;
++ if (!sgmii_2500)
++ value |= PHY_SGMII_IF_MODE_AN;
++
++ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
++
++ /* Dev ability according to SGMII specification */
++ value = PHY_SGMII_DEV_ABILITY_SGMII;
++ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
++
++ /* Adjust link timer for SGMII -
++ 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
++ //ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
++ //ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
++
++ //These values taken from validation team
++ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x0);
++ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0x400);
++
++ /* Restart AN */
++ value = PHY_SGMII_CR_DEF_VAL;
++ if (!sgmii_2500)
++ value |= PHY_SGMII_CR_RESET_AN;
++ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
++
++
++}
++
++void ls1012a_set_mdio(int dev_id, struct mii_dev *bus)
++{
++ gem_info[dev_id].bus = bus;
++}
++
++void ls1012a_set_phy_address_mode(int dev_id, int phy_id, int phy_mode)
++{
++ gem_info[dev_id].phy_address = phy_id;
++ gem_info[dev_id].phy_mode = phy_mode;
++}
++
++int ls1012a_phy_configure(struct ls1012a_eth_dev *priv, int dev_id, int phy_id)
++{
++ struct phy_device *phydev = NULL;
++ struct eth_device *dev = priv->dev;
++ struct gemac_s *gem = priv->gem;
++ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
++
++ //Configure SGMII PCS
++ if(gem->phy_mode == PHY_INTERFACE_MODE_SGMII ||
++ gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500)
++ {
++ //printf("Select MDIO from serdes\n");
++ out_be32(&scfg->mdioselcr, 0x00000000);
++ ls1012a_configure_serdes(priv);
++ }
++
++ /*By this time on-chip SGMII initialization is done
++ * we can swith mdio interface to external PHYs */
++ //printf("Select MDIO from PAD\n");
++ out_be32(&scfg->mdioselcr, 0x80000000);
++
++ if(! gem->bus) return -1;
++ phydev = phy_connect(gem->bus, phy_id, dev, gem->phy_mode);
++ if (!phydev) {
++ printf("phy_connect failed\n");
++ return -1;
++ }
++
++ phy_config(phydev);
++
++ priv->phydev = phydev;
++
++ return 0;
++}
++#endif
++
++int ls1012a_gemac_initialize(bd_t * bis, int dev_id, char *devname)
++{
++ struct eth_device *dev;
++ struct ls1012a_eth_dev *priv;
++ struct pfe *pfe;
++ int i;
++
++ if(dev_id > 1)
++ {
++ printf("Invalid port\n");
++ return -1;
++ }
++
++ dev = (struct eth_device *)malloc(sizeof(struct eth_device));
++ if (!dev)
++ return -1;
++
++ memset(dev, 0, sizeof(struct eth_device));
++
++ priv = (struct ls1012a_eth_dev *)malloc(sizeof(struct ls1012a_eth_dev));
++ if (!priv)
++ return -1;
++
++ gemac_list[dev_id] = priv;
++ priv->gemac_port = dev_id;
++ priv->gem = &gem_info[priv->gemac_port];
++ priv->dev = dev;
++
++ pfe = &priv->pfe;
++
++ pfe->cbus_baseaddr = (void *)CONFIG_SYS_PPFE_ADDR;
++ pfe->ddr_baseaddr = (void *)CONFIG_DDR_PPFE_BASEADDR;
++ pfe->ddr_phys_baseaddr = (unsigned long)CONFIG_DDR_PPFE_PHYS_BASEADDR;
++
++ sprintf(dev->name, devname);
++ dev->priv = priv;
++ dev->init = ls1012a_eth_init;
++ dev->halt = ls1012a_eth_halt;
++ dev->send = ls1012a_eth_send;
++ dev->recv = ls1012a_eth_recv;
++
++ /* Tell u-boot to get the addr from the env */
++ for (i = 0; i < 6; i++)
++ dev->enetaddr[i] = 0;
++
++ pfe_probe(pfe);
++
++ switch(priv->gemac_port) {
++ case EMAC_PORT_0:
++ default:
++ priv->gem->gemac_base = EMAC1_BASE_ADDR;
++ priv->gem->egpi_base = EGPI1_BASE_ADDR;
++ break;
++ case EMAC_PORT_1:
++ priv->gem->gemac_base = EMAC2_BASE_ADDR;
++ priv->gem->egpi_base = EGPI2_BASE_ADDR;
++ break;
++ }
++
++
++#ifndef CONFIG_EMU
++#if defined(CONFIG_PHYLIB)
++ if(ls1012a_phy_configure(priv, dev_id, gem_info[priv->gemac_port].phy_address))
++ return -1;
++#else
++ #error ("Please enable CONFIG_PHYLIB")
++#endif
++#endif
++
++ eth_register(dev);
++
++ return 0;
++}
+diff --git a/drivers/net/pfe_eth/pfe_eth.h b/drivers/net/pfe_eth/pfe_eth.h
+new file mode 100644
+index 0000000..dfcc00e
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe_eth.h
+@@ -0,0 +1,161 @@
++/*
++ * (C) Copyright 2011
++ * Author : Mindspeed Technologes
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ * */
++
++#ifndef _LS1012a_ETH_H_
++#define _LS1012a_ETH_H_
++
++
++#include "pfe_driver.h"
++
++#ifndef SZ_1K
++#define SZ_1K 1024
++#endif
++
++#ifndef SZ_1M
++#define SZ_1M (1024 * 1024)
++#endif
++
++#define BMU2_DDR_BASEADDR 0
++#define BMU2_BUF_COUNT (3 * SZ_1K)
++#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
++
++#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
++#define TMU_LLM_QUEUE_LEN (16 * 256) /**< Must be power of two and at least 16 * 8 = 128 bytes */
++#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
++
++#define HIF_RX_PKT_DDR_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
++#define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE)
++#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
++#define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE)
++
++#define HIF_DESC_BASEADDR (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
++#define HIF_RX_DESC_SIZE (16*HIF_RX_DESC_NT)
++#define HIF_TX_DESC_SIZE (16*HIF_TX_DESC_NT)
++#define HIF_DESC_SIZE (HIF_RX_DESC_SIZE + HIF_TX_DESC_SIZE)
++
++//#define FPPDIAG_CTL_BASE_ADDR (HIF_DESC_BASEADDR + HIF_DESC_SIZE)
++#define FPPDIAG_CTL_BASE_ADDR 0x700000
++#define FPPDIAG_CTL_SIZE 256 /**< Must be at least 11*8 bytes */
++#define FPPDIAG_PAGE_BASE_ADDR (FPPDIAG_CTL_BASE_ADDR + FPPDIAG_CTL_SIZE)
++#define FPPDIAG_PAGE_TOTAL_SIZE (11 * 256) /**< 256 bytes per PE, 11 PEs */
++
++//#define UTIL_CODE_BASEADDR (FPPDIAG_PAGE_BASE_ADDR + FPPDIAG_PAGE_TOTAL_SIZE)
++#define UTIL_CODE_BASEADDR 0x780000
++#define UTIL_CODE_SIZE (128 * SZ_1K)
++
++#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
++#define UTIL_DDR_DATA_SIZE (64 * SZ_1K)
++
++#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
++#define CLASS_DDR_DATA_SIZE (32 * SZ_1K)
++
++#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
++#define TMU_DDR_DATA_SIZE (32 * SZ_1K)
++
++//#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
++#define ROUTE_TABLE_BASEADDR 0x800000
++#define ROUTE_TABLE_HASH_BITS_MAX 15 /**< 32K entries */
++#define ROUTE_TABLE_HASH_BITS 8 /**< 256 entries */
++#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS_MAX) * CLASS_ROUTE_SIZE)
++
++#define PFE_TOTAL_DATA_SIZE (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
++
++#if PFE_TOTAL_DATA_SIZE > (12 * SZ_1M)
++#error DDR mapping above 12MiB
++#endif
++
++/* LMEM Mapping */
++#define BMU1_LMEM_BASEADDR 0
++#define BMU1_BUF_COUNT 256
++#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
++
++
++#define CONFIG_DDR_PPFE_PHYS_BASEADDR 0x03800000
++#define CONFIG_DDR_PPFE_BASEADDR 0x83800000
++
++
++#define GEMAC_NO_PHY 1
++#define GEMAC_HAVE_SWITCH_PHY 2
++#define GEMAC_HAVE_SWITCH 4
++
++
++typedef struct gemac_s {
++
++ void *gemac_base;
++ void *egpi_base;
++
++ /* GEMAC config */
++ int gemac_mode;
++ int gemac_speed;
++ int gemac_duplex;
++ int flags;
++ /* phy iface */
++ int phy_address;
++ int phy_mode;
++ struct mii_dev *bus;
++
++} gemac_t;
++
++struct mdio_info {
++ void *reg_base;
++ char *name;
++};
++
++
++struct pfe {
++ unsigned long ddr_phys_baseaddr;
++ void *ddr_baseaddr;
++ void *cbus_baseaddr;
++};
++
++
++typedef struct ls1012a_eth_dev {
++
++ int gemac_port;
++
++ struct gemac_s *gem;
++ struct pfe pfe;
++
++ struct eth_device *dev;
++#ifdef CONFIG_PHYLIB
++ struct phy_device *phydev;
++#endif
++} ls1012a_eth_dev_t;
++
++
++struct firmware {
++ u8 *data;
++};
++
++
++int pfe_probe(struct pfe *pfe);
++int pfe_remove(struct pfe *pfe);
++
++
++//#define dprint(fmt, arg...) printf(fmt, ##arg)
++#define dprint(fmt, arg...)
++//#define dprint printf
++
++
++#endif //_LS1012a_ETH_H_
++
+diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
+new file mode 100644
+index 0000000..165eb3c
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe_firmware.c
+@@ -0,0 +1,193 @@
++
++
++/** @file
++ * Contains all the functions to handle parsing and loading of PE firmware files.
++ */
++
++#include "hal.h"
++#include "pfe_firmware.h"
++#include "pfe/pfe.h"
++
++
++/* CLASS-PE ELF file content */
++unsigned char class_fw_data[] __attribute__((aligned(sizeof(int)))) = {
++#include CLASS_FIRMWARE_FILENAME
++};
++
++/* TMU-PE ELF file content */
++unsigned char tmu_fw_data[] __attribute__((aligned(sizeof(int)))) = {
++#include TMU_FIRMWARE_FILENAME
++};
++
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++unsigned char util_fw_data[] = {
++#include UTIL_FIRMWARE_FILENAME
++};
++#endif
++
++/** PFE elf firmware loader.
++* Loads an elf firmware image into a list of PE's (specified using a bitmask)
++*
++* @param pe_mask Mask of PE id's to load firmware to
++* @param fw Pointer to the firmware image
++*
++* @return 0 on sucess, a negative value on error
++*
++*/
++int pfe_load_elf(int pe_mask, const struct firmware *fw)
++{
++ Elf32_Ehdr *elf_hdr = (Elf32_Ehdr *)fw->data;
++ Elf32_Half sections = be16_to_cpu(elf_hdr->e_shnum);
++ Elf32_Shdr *shdr = (Elf32_Shdr *) (fw->data + be32_to_cpu(elf_hdr->e_shoff));
++ int id, section;
++ int rc;
++
++ printf("%s: no of sections: %d\n", __func__, sections);
++
++ /* Some sanity checks */
++ if (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG))
++ {
++ printf("%s: incorrect elf magic number\n", __func__);
++ return -1;
++ }
++
++ if (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32)
++ {
++ printf("%s: incorrect elf class(%x)\n", __func__, elf_hdr->e_ident[EI_CLASS]);
++ return -1;
++ }
++
++ if (elf_hdr->e_ident[EI_DATA] != ELFDATA2MSB)
++ {
++ printf("%s: incorrect elf data(%x)\n", __func__, elf_hdr->e_ident[EI_DATA]);
++ return -1;
++ }
++
++ if (be16_to_cpu(elf_hdr->e_type) != ET_EXEC)
++ {
++ printf("%s: incorrect elf file type(%x)\n", __func__, be16_to_cpu(elf_hdr->e_type));
++ return -1;
++ }
++
++ for (section = 0; section < sections; section++, shdr++)
++ {
++ if (!(be32_to_cpu(shdr->sh_flags) & (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR)))
++ continue;
++ for (id = 0; id < MAX_PE; id++)
++ if (pe_mask & (1 << id))
++ {
++ rc = pe_load_elf_section(id, fw->data, shdr);
++ if (rc < 0)
++ goto err;
++ }
++ //printf("\n");
++ }
++
++ return 0;
++
++err:
++ return rc;
++}
++
++/** PFE firmware initialization.
++* Loads different firmware files from filesystem.
++* Initializes PE IMEM/DMEM and UTIL-PE DDR
++* Initializes control path symbol addresses (by looking them up in the elf firmware files
++* Takes PE's out of reset
++*
++* @return 0 on sucess, a negative value on error
++*
++*/
++int pfe_firmware_init(u8 *class_fw_loc, u8 *tmu_fw_loc, u8 *util_fw_loc)
++{
++ struct firmware class_fw, tmu_fw;
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++ struct firmware util_fw;
++#endif
++ int rc = 0;
++
++ printf("%s\n", __func__);
++#if 0
++ /*This testing purpose only */
++ printf("Copying default fw \n");
++ memcpy(class_fw_loc, class_fw_data, sizeof(class_fw_data));
++ memcpy(tmu_fw_loc, tmu_fw_data, sizeof(tmu_fw_data));
++ memcpy(util_fw_loc, util_fw_data, sizeof(util_fw_data));
++#endif
++
++ if (class_fw_loc)
++ class_fw.data = class_fw_loc;
++ else
++ class_fw.data = class_fw_data;
++
++ if (tmu_fw_loc)
++ tmu_fw.data = tmu_fw_loc;
++ else
++ tmu_fw.data = tmu_fw_data;
++
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++ if (util_fw_loc)
++ util_fw.data = util_fw_loc;
++ else
++ util_fw.data = util_fw_data;
++#endif
++
++ rc = pfe_load_elf(CLASS_MASK, &class_fw);
++ if (rc < 0) {
++ printf("%s: class firmware load failed\n", __func__);
++ goto err3;
++ }
++
++ printf("%s: class firmware loaded\n", __func__);
++
++ rc = pfe_load_elf(TMU_MASK, &tmu_fw);
++ if (rc < 0) {
++ printf("%s: tmu firmware load failed\n", __func__);
++ goto err3;
++ }
++
++ printf("%s: tmu firmware loaded\n", __func__);
++
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++ rc = pfe_load_elf(UTIL_MASK, &util_fw);
++ if (rc < 0) {
++ printf("%s: util firmware load failed\n", __func__);
++ goto err3;
++ }
++
++ printf("%s: util firmware loaded\n", __func__);
++
++ util_enable();
++#endif
++
++#if defined(CONFIG_LS1012A)
++ tmu_enable(0xb);
++#else
++ tmu_enable(0xf);
++#endif
++ class_enable();
++
++ gpi_enable(HGPI_BASE_ADDR);
++
++
++err3:
++ return rc;
++}
++
++/** PFE firmware cleanup
++* Puts PE's in reset
++*
++*
++*/
++void pfe_firmware_exit(void)
++{
++ printf("%s\n", __func__);
++
++ class_disable();
++ tmu_disable(0xf);
++#if !defined(CONFIG_UTIL_PE_DISABLED)
++ util_disable();
++#endif
++ hif_tx_disable();
++ hif_rx_disable();
++}
+diff --git a/drivers/net/pfe_eth/pfe_firmware.h b/drivers/net/pfe_eth/pfe_firmware.h
+new file mode 100644
+index 0000000..2823162
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe_firmware.h
+@@ -0,0 +1,20 @@
++
++
++/** @file
++ * Contains all the defines to handle parsing and loading of PE firmware files.
++ */
++
++#ifndef __PFE_FIRMWARE_H__
++#define __PFE_FIRMWARE_H__
++
++
++#define CLASS_FIRMWARE_FILENAME "class_sbl_elf.fw"
++#define TMU_FIRMWARE_FILENAME "tmu_sbl_elf.fw"
++#define UTIL_FIRMWARE_FILENAME "util_sbl_elf.fw"
++
++
++int pfe_firmware_init(u8 * clasS_fw_loc, u8 *tmu_fw_loc, u8 *util_fw_loc);
++void pfe_firmware_exit(void);
++
++
++#endif
+diff --git a/drivers/net/pfe_eth/pfe_mod.h b/drivers/net/pfe_eth/pfe_mod.h
+new file mode 100644
+index 0000000..9436b72
+--- /dev/null
++++ b/drivers/net/pfe_eth/pfe_mod.h
+@@ -0,0 +1,140 @@
++/*
++ * (C) Copyright 2011
++ * Author : Mindspeed Technologes
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ * */
++
++
++#ifndef _PFE_MOD_H_
++#define _PFE_MOD_H_
++
++#include <linux/device.h>
++
++#include "pfe/pfe.h"
++#include "pfe/cbus.h"
++#include "pfe/cbus/bmu.h"
++
++#include "pfe_driver.h"
++
++struct pfe;
++
++
++struct pfe {
++ unsigned long ddr_phys_baseaddr;
++ void *ddr_baseaddr;
++ void *cbus_baseaddr;
++ void *apb_baseaddr;
++ void *iram_baseaddr;
++ int hif_irq;
++ struct device *dev;
++ struct pci_dev *pdev;
++
++#if 0
++ struct pfe_ctrl ctrl;
++ struct pfe_hif hif;
++ struct pfe_eth eth;
++#endif
++};
++
++extern struct pfe *pfe;
++
++int pfe_probe(struct pfe *pfe);
++int pfe_remove(struct pfe *pfe);
++
++#ifndef SZ_1K
++#define SZ_1K 1024
++#endif
++
++#ifndef SZ_1M
++#define SZ_1M (1024 * 1024)
++#endif
++
++/* DDR Mapping */
++#if !defined(CONFIG_PLATFORM_PCI)
++#define UTIL_CODE_BASEADDR 0
++#define UTIL_CODE_SIZE (128 * SZ_1K)
++#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
++#define UTIL_DDR_DATA_SIZE (64 * SZ_1K)
++#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
++#define CLASS_DDR_DATA_SIZE (32 * SZ_1K)
++#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
++#define TMU_DDR_DATA_SIZE (32 * SZ_1K)
++#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
++#define ROUTE_TABLE_HASH_BITS 15 /**< 32K entries */
++#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
++#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
++#define BMU2_BUF_COUNT (4096 - 256) /**< This is to get a total DDR size of 12MiB */
++#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
++#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
++#define TMU_LLM_QUEUE_LEN (16 * 256) /**< Must be power of two and at least 16 * 8 = 128 bytes */
++#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
++
++#if (TMU_LLM_BASEADDR + TMU_LLM_SIZE) > 0xC00000
++#error DDR mapping above 12MiB
++#endif
++
++#else
++
++#define UTIL_CODE_BASEADDR 0
++#if defined(CONFIG_UTIL_PE_DISABLED)
++#define UTIL_CODE_SIZE (0 * SZ_1K)
++#else
++#define UTIL_CODE_SIZE (8 * SZ_1K)
++#endif
++#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
++#define UTIL_DDR_DATA_SIZE (0 * SZ_1K)
++#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
++#define CLASS_DDR_DATA_SIZE (0 * SZ_1K)
++#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
++#define TMU_DDR_DATA_SIZE (0 * SZ_1K)
++#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
++#define ROUTE_TABLE_HASH_BITS 5 /**< 32 entries */
++#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
++#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
++#define BMU2_BUF_COUNT 8
++#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
++#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
++#define TMU_LLM_QUEUE_LEN (16 * 8) /**< Must be power of two and at least 16 * 8 = 128 bytes */
++#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
++#define HIF_DESC_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
++#define HIF_RX_DESC_SIZE (16*HIF_RX_DESC_NT)
++#define HIF_TX_DESC_SIZE (16*HIF_TX_DESC_NT)
++#define HIF_DESC_SIZE (HIF_RX_DESC_SIZE + HIF_TX_DESC_SIZE)
++#define HIF_RX_PKT_DDR_BASEADDR (HIF_DESC_BASEADDR + HIF_DESC_SIZE)
++#define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE)
++#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
++#define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE)
++#define ROUTE_BASEADDR (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
++#define ROUTE_SIZE (2 * CLASS_ROUTE_SIZE)
++
++#if (ROUTE_BASEADDR + ROUTE_SIZE) > 0x10000
++#error DDR mapping above 64KiB
++#endif
++
++#define PFE_HOST_TO_PCI(addr) (((u32)addr)- ((u32)DDR_BASE_ADDR))
++#define PFE_PCI_TO_HOST(addr) (((u32)addr)+ ((u32)DDR_BASE_ADDR))
++#endif
++
++/* LMEM Mapping */
++#define BMU1_LMEM_BASEADDR 0
++#define BMU1_BUF_COUNT 256
++#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
++
++#endif /* _PFE_MOD_H */
+diff --git a/drivers/net/pfe_eth/tmu_sbl_elf.fw b/drivers/net/pfe_eth/tmu_sbl_elf.fw
+new file mode 100644
+index 0000000..d9e8409
+--- /dev/null
++++ b/drivers/net/pfe_eth/tmu_sbl_elf.fw
+@@ -0,0 +1 @@
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+diff --git a/drivers/net/pfe_eth/util_sbl_elf.fw b/drivers/net/pfe_eth/util_sbl_elf.fw
+new file mode 100644
+index 0000000..7a34b86
+--- /dev/null
++++ b/drivers/net/pfe_eth/util_sbl_elf.fw
+@@ -0,0 +1 @@
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+\ No newline at end of file
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 07ef7c6..3c4ab6c 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -109,6 +109,16 @@
+ #define CONFIG_CMD_PING
+ #undef CONFIG_CMD_IMLS
+
++/* PPFE */
++#define CONFIG_FSL_PPFE
++
++#ifdef CONFIG_FSL_PPFE
++#define CONFIG_CMD_PFE_START
++#define CONFIG_CMD_PFE_COMMANDS
++#define CONFIG_UTIL_PE_DISABLED
++
++#endif
++
+
+ #define CONFIG_ARCH_EARLY_INIT_R
+
+diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
+index 488811b..1fa7b6f 100644
+--- a/include/configs/ls1012aqds.h
++++ b/include/configs/ls1012aqds.h
+@@ -14,16 +14,14 @@
+ #define CONFIG_CHIP_SELECTS_PER_CTRL 1
+ #define CONFIG_NR_DRAM_BANKS 2
+
+-#ifdef CONFIG_SYS_DPAA_FMAN
+-#define CONFIG_FMAN_ENET
++#ifdef CONFIG_FSL_PPFE
++/*#define CONFIG_CMD_PFE_START */
++#define EMAC1_PHY_ADDR 0x1e
++#define EMAC2_PHY_ADDR 0x1
+ #define CONFIG_PHYLIB
+ #define CONFIG_PHY_VITESSE
+ #define CONFIG_PHY_REALTEK
+-#define RGMII_PHY1_ADDR 0x1
+-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+-#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
++#define RGMII_RESET_WA
+ #endif
+
+ /* MMC */
+@@ -142,6 +140,7 @@
+ #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+ #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
++
+ /* DSPI */
+ #define CONFIG_FSL_DSPI
+ #define CONFIG_FSL_DSPI1
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index 1629e19..1b72bf1 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -19,10 +19,12 @@
+ #define CONFIG_SYS_MEMTEST_START 0x80000000
+ #define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
++#ifdef CONFIG_FSL_PPFE
++#define EMAC1_PHY_ADDR 0x2
++#define EMAC2_PHY_ADDR 0x1
+ #define CONFIG_PHYLIB
+ #define CONFIG_PHY_REALTEK
+-#define SGMII_PHY1_ADDR 0x0
+-#define RGMII_PHY2_ADDR 0x1
++#endif
+
+ /*
+ * USB
+--
+1.7.9.5
+
--- /dev/null
+From 63acb257c32bd86abbad5abcc002d6c78b72f0ab Mon Sep 17 00:00:00 2001
+From: Anji J <anji.jagarlmudi@freescale.com>
+Date: Mon, 16 May 2016 20:21:38 +0530
+Subject: [PATCH 42/93] DNCPE-138 Rest external PHYs
+
+Need to reset external PHYs through IO expander for proper function.
+
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ board/freescale/ls1012ardb/eth.c | 14 ++++++++++++++
+ include/configs/ls1012ardb.h | 9 +++++++++
+ 2 files changed, 23 insertions(+)
+
+diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
+index 29830e8..24fdd83 100644
+--- a/board/freescale/ls1012ardb/eth.c
++++ b/board/freescale/ls1012ardb/eth.c
+@@ -20,6 +20,20 @@
+
+ #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+
++
++void reset_phy(void)
++{
++
++ /*Through reset IO expander reset both RGMII and SGMII PHYs */
++ i2c_reg_write(CONFIG_SYS_I2C_RESET_IO_EXPANDER, 6, __PHY_MASK);
++ i2c_reg_write(CONFIG_SYS_I2C_RESET_IO_EXPANDER, 2, __PHY_ETH2_MASK);
++ mdelay(10);
++ i2c_reg_write(CONFIG_SYS_I2C_RESET_IO_EXPANDER, 2, __PHY_ETH1_MASK);
++ mdelay(10);
++ i2c_reg_write(CONFIG_SYS_I2C_RESET_IO_EXPANDER, 2, 0xFF);
++ mdelay(50);
++}
++
+ int board_eth_init(bd_t *bis)
+ {
+ #ifdef CONFIG_FSL_PPFE
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index 1b72bf1..23722e0 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -24,6 +24,7 @@
+ #define EMAC2_PHY_ADDR 0x1
+ #define CONFIG_PHYLIB
+ #define CONFIG_PHY_REALTEK
++#define CONFIG_RESET_PHY_R
+ #endif
+
+ /*
+@@ -128,6 +129,14 @@
+ #define __SW_REV_A 0xF8
+ #define __SW_REV_B 0xF0
+
++/*
++ *I2C RESET expander
++ */
++#define CONFIG_SYS_I2C_RESET_IO_EXPANDER 0x25
++#define __PHY_MASK 0xF9
++#define __PHY_ETH2_MASK 0xFB
++#define __PHY_ETH1_MASK 0xFD
++
+ #define CONFIG_CMD_MEMINFO
+ #define CONFIG_CMD_MEMTEST
+ #define CONFIG_SYS_MEMTEST_START 0x80000000
+--
+1.7.9.5
+
--- /dev/null
+From b17d75d2c1dc6cd1d55bcddbf7d3d4242e85e88e Mon Sep 17 00:00:00 2001
+From: Anji J <anji.jagarlmudi@freescale.com>
+Date: Fri, 20 May 2016 15:25:12 +0530
+Subject: [PATCH 43/93] DNCPE-296 PFE reset workaround
+
+LS1012A PFE doesn't have global reset control.
+Due to this Linux pfe doesn't work when it was started at U-boot
+This patch provides U-boot command to stop pfe, that should be used before starting Linux.
+
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ common/cmd_pfe_commands.c | 83 +++++++++++++++++++++++++++++++++++-
+ drivers/net/pfe_eth/pfe/cbus/hif.h | 3 ++
+ drivers/net/pfe_eth/pfe/pfe.h | 2 +
+ drivers/net/pfe_eth/pfe_driver.c | 58 ++++++++++++++++++++-----
+ drivers/net/pfe_eth/pfe_eth.c | 6 +--
+ 5 files changed, 136 insertions(+), 16 deletions(-)
+
+diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
+index f9f92c7..0e22097 100644
+--- a/common/cmd_pfe_commands.c
++++ b/common/cmd_pfe_commands.c
+@@ -35,6 +35,7 @@
+ #include "../drivers/net/pfe_eth/pfe/cbus/gpi.h"
+ DECLARE_GLOBAL_DATA_PTR;
+
++void hif_rx_desc_disable(void);
+ int pfe_load_elf(int pe_mask, const struct firmware *fw);
+ int ls1012a_gemac_initialize(bd_t * bis, int dev_id, char *devname);
+
+@@ -593,7 +594,9 @@ void bmu(int id, void *base)
+ }
+
+ #define PESTATUS_ADDR_CLASS 0x800
++#define PEMBOX_ADDR_CLASS 0x890
+ #define PESTATUS_ADDR_TMU 0x80
++#define PEMBOX_ADDR_TMU 0x290
+ #define PESTATUS_ADDR_UTIL 0x0
+
+ static void pfe_pe_status(int argc, char * const argv[])
+@@ -857,7 +860,6 @@ void hif_rx_enable(void)
+ void hif_rx_disable(void)
+ }
+ #endif
+-
+ #define ROUTE_TABLE_START (CONFIG_DDR_PHYS_BASEADDR+ROUTE_TABLE_BASEADDR)
+ static void pfe_command_fftest(int argc, char * const argv[])
+ {
+@@ -865,7 +867,6 @@ static void pfe_command_fftest(int argc, char * const argv[])
+ struct eth_device *edev_eth0;
+ struct eth_device *edev_eth1;
+
+-
+ // open eth0 and eth1
+ edev_eth0 = eth_get_dev_by_name("pfe_eth0");
+ if (!edev_eth0)
+@@ -916,6 +917,80 @@ static void pfe_command_start(int argc, char * const argv[])
+ }
+ #endif
+
++#ifdef PFE_LS1012A_RESET_WA
++/*This function sends a dummy packet to HIF through TMU3 */
++static void send_dummy_pkt_to_hif(void)
++{
++ u32 buf;
++ static u32 dummy_pkt[] = {
++ 0x4200800a, 0x01000003, 0x00018100, 0x00000000,
++ 0x33221100, 0x2b785544, 0xd73093cb, 0x01000608,
++ 0x04060008, 0x2b780200, 0xd73093cb, 0x0a01a8c0,
++ 0x33221100, 0xa8c05544, 0x00000301, 0x00000000,
++ 0x00000000, 0x00000000, 0x00000000, 0xbe86c51f };
++
++ /*Allocate BMU2 buffer */
++ buf = readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL);
++
++ printf("Sending a dummy pkt to HIF %x\n", buf);
++ buf += 0x80;
++ memcpy((void *)DDR_PFE_TO_VIRT(buf), dummy_pkt, sizeof(dummy_pkt));
++ /*Write length and pkt to TMU*/
++ writel(0x03000042, TMU_PHY_INQ_PKTPTR);
++ writel(buf, TMU_PHY_INQ_PKTINFO);
++
++}
++
++static void pfe_command_stop(int argc, char * const argv[])
++{
++ int id;
++ u32 rx_status;
++ printf("Stopping PFE \n");
++
++ /*Mark all descriptors as LAST_BD */
++ hif_rx_desc_disable();
++
++ /*If HIF Rx BDP is busy send a dummy packet */
++ rx_status = readl(HIF_RX_STATUS);
++ printf("rx_status %x %x\n",rx_status, BDP_CSR_RX_DMA_ACTV);
++ if(rx_status & BDP_CSR_RX_DMA_ACTV)
++ send_dummy_pkt_to_hif();
++ udelay(10);
++
++ if(readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)
++ printf("Unable to stop HIF\n");
++
++ /*Disable Class PEs */
++
++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++)
++ {
++ printf("Stop %d\n", id);
++ /*Inform PE to stop */
++ pe_dmem_write(id, cpu_to_be32(1), PEMBOX_ADDR_CLASS, 4);
++ udelay(10);
++
++ printf("Reading %d\n", id);
++ /*Read status */
++ if(!pe_dmem_read(id, PEMBOX_ADDR_CLASS+4, 4))
++ printf("Failed to stop PE%d\n", id);
++ }
++ /*Disable TMU PEs */
++ for (id = TMU0_ID; id <= TMU_MAX_ID; id++)
++ {
++ if(id == TMU2_ID) continue;
++
++ printf("Stop %d\n", id);
++ /*Inform PE to stop */
++ pe_dmem_write(id, 1, PEMBOX_ADDR_TMU, 4);
++ udelay(10);
++
++ printf("Reading %d\n", id);
++ /*Read status */
++ if(!pe_dmem_read(id, PEMBOX_ADDR_TMU+4, 4))
++ printf("Failed to stop PE%d\n", id);
++ }
++}
++#endif
+
+ static int pfe_command(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+@@ -965,6 +1040,10 @@ static int pfe_command(cmd_tbl_t *cmdtp, int flag, int argc,
+ else if (strcmp(argv[1], "start") == 0)
+ pfe_command_start(argc, argv);
+ #endif
++#ifdef PFE_LS1012A_RESET_WA
++ else if (strcmp(argv[1], "stop") == 0)
++ pfe_command_stop(argc, argv);
++#endif
+ else
+ {
+ printf("Unknown option: %s\n", argv[1]);
+diff --git a/drivers/net/pfe_eth/pfe/cbus/hif.h b/drivers/net/pfe_eth/pfe/cbus/hif.h
+index a4dd7c2..2329faa 100644
+--- a/drivers/net/pfe_eth/pfe/cbus/hif.h
++++ b/drivers/net/pfe_eth/pfe/cbus/hif.h
+@@ -34,6 +34,9 @@
+ #define HIF_CTRL_BDP_POLL_CTRL_EN (1<<1)
+ #define HIF_CTRL_BDP_CH_START_WSTB (1<<2)
+
++/*HIF_RX_STATUS bits */
++#define BDP_CSR_RX_DMA_ACTV (1<<16)
++
+ /*HIF_INT_ENABLE bits */
+ #define HIF_INT_EN (1 << 0)
+ #define HIF_RXBD_INT_EN (1 << 1)
+diff --git a/drivers/net/pfe_eth/pfe/pfe.h b/drivers/net/pfe_eth/pfe/pfe.h
+index e8e2221..6994a20 100644
+--- a/drivers/net/pfe_eth/pfe/pfe.h
++++ b/drivers/net/pfe_eth/pfe/pfe.h
+@@ -1,6 +1,8 @@
+ #ifndef _PFE_H_
+ #define _PFE_H_
+
++#define PFE_LS1012A_RESET_WA
++
+ #define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
+ #define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) /* Only valid for mem access register interface */
+ #define CLASS_DMEM_SIZE 0x00002000
+diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
+index ca00e98..b06a352 100644
+--- a/drivers/net/pfe_eth/pfe_driver.c
++++ b/drivers/net/pfe_eth/pfe_driver.c
+@@ -51,13 +51,18 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
+ struct rx_desc_s *rx_desc = g_rx_desc;
+ struct bufDesc *bd;
+ int len = -1;
+- //volatile u32 ctrl;
++ volatile u32 ctrl;
+ struct hif_header_s *hif_header;
+
+ bd = rx_desc->rxBase + rx_desc->rxToRead;
+
+- if (bd->ctrl & BD_CTRL_DESC_EN)
++ if (bd->ctrl & BD_CTRL_DESC_EN) {
++ if(!(readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)){
++ /*If BDP is not active give write strobe */
++ writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
++ }
+ return len; //No pending Rx packet
++ }
+
+ /* this len include hif_header(8bytes) */
+ len = bd->ctrl & 0xFFFF;
+@@ -69,7 +74,7 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
+ dprint("Pkt recv'd: Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
+ hif_header, len, hif_header->port_no, bd->status);
+
+-#if 0
++#if DEBUG
+ {
+ int i;
+ unsigned char *p = (unsigned char *)hif_header;
+@@ -85,20 +90,26 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
+ *pkt_ptr = (unsigned int )(hif_header + 1);
+ *phy_port = hif_header->port_no;
+ len -= sizeof(struct hif_header_s);
+-#if 0
++
++#if defined(PFE_LS1012A_RESET_WA)
+ /* reset bd control field */
+- ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR);
++ ctrl = (MAX_FRAME_SIZE | BD_CTRL_LAST_BD | BD_CTRL_LIFM | BD_CTRL_DESC_EN | BD_CTRL_DIR);
++#else
++ /* reset bd control field */
++ ctrl = (MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN | BD_CTRL_DIR);
++ /* If we use BD_CTRL_LAST_BD, rxToRead never changes */
++ rx_desc->rxToRead = (rx_desc->rxToRead + 1) & (rx_desc->rxRingSize - 1);
++#endif
+ bd->ctrl = ctrl;
+ bd->status = 0;
+
+- rx_desc->rxToRead = (rx_desc->rxToRead + 1) & (rx_desc->rxRingSize - 1);
+
+ /* Give START_STROBE to BDP to fetch the descriptor __NOW__,
+ * BDP need not to wait for rx_poll_cycle time to fetch the descriptor,
+ * In idle state (ie., no rx pkt), BDP will not fetch
+ * the descriptor even if strobe is given(I think) */
+ writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
+-#endif
++
+ return len;
+ }
+
+@@ -298,14 +309,37 @@ void hif_rx_desc_dump(void)
+ rx_desc = g_rx_desc;
+ bd_va = rx_desc->rxBase;
+
+- printf("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rxBase, rx_desc->rxBase_pa);
++ dprint("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rxBase, rx_desc->rxBase_pa);
+ for (i=0; i < rx_desc->rxRingSize; i++) {
+-// printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
+-// bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
++ dprint("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
++ bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
++ bd_va++;
++ }
++}
++
++/** This function mark all Rx descriptors as LAST_BD.
++ */
++void hif_rx_desc_disable(void)
++{
++ int i;
++ struct rx_desc_s *rx_desc;
++ struct bufDesc *bd_va;
++
++ if (g_rx_desc == NULL) {
++ printf("%s: HIF Rx desc not initialized \n", __func__);
++ return;
++ }
++
++ rx_desc = g_rx_desc;
++ bd_va = rx_desc->rxBase;
++
++ for (i=0; i < rx_desc->rxRingSize; i++) {
++ bd_va->ctrl |= BD_CTRL_LAST_BD;
+ bd_va++;
+ }
+ }
+
++
+ /** HIF Rx Desc initialization function.
+ */
+ static int hif_rx_desc_init(struct pfe *pfe)
+@@ -348,7 +382,11 @@ static int hif_rx_desc_init(struct pfe *pfe)
+
+ memset(bd_va, 0, sizeof(struct bufDesc) * rx_desc->rxRingSize);
+
++#if defined(PFE_LS1012A_RESET_WA)
++ ctrl = (MAX_FRAME_SIZE | BD_CTRL_LAST_BD | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
++#else
+ ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
++#endif
+ for (i=0; i < rx_desc->rxRingSize; i++) {
+ bd_va->next = (u32 )(bd_pa + 1);
+ bd_va->ctrl = ctrl;
+diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
+index 40ac095..40f2c39 100644
+--- a/drivers/net/pfe_eth/pfe_eth.c
++++ b/drivers/net/pfe_eth/pfe_eth.c
+@@ -48,7 +48,7 @@ static void ls1012a_gemac_enable(void *gemac_base)
+ writel(readl(gemac_base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
+ }
+
+-static void ls1012a_gemac_dsable(void *gemac_base)
++static void ls1012a_gemac_disable(void *gemac_base)
+ {
+ writel(readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
+ }
+@@ -113,7 +113,7 @@ static void ls1012a_eth_halt(struct eth_device *edev)
+ {
+ struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)edev->priv;
+
+- ls1012a_gemac_enable(priv->gem->gemac_base);
++ ls1012a_gemac_disable(priv->gem->gemac_base);
+
+ gpi_disable(priv->gem->egpi_base);
+
+@@ -216,14 +216,12 @@ static int ls1012a_eth_recv(struct eth_device *dev)
+ dprint("Rx pkt: pkt_buf(%08x), phy_port(%d), len(%d)\n", pkt_buf, phy_port, len);
+ if (phy_port != priv->gemac_port) {
+ printf("Rx pkt not on expected port\n");
+- pfe_recv_ack();
+ return 0;
+ }
+
+ // Pass the packet up to the protocol layers.
+ net_process_received_packet((uchar *)pkt_buf, len);
+
+- pfe_recv_ack();
+ return 0;
+ }
+
+--
+1.7.9.5
+
--- /dev/null
+From fe0ffa96c83e318d6b99fe31b5d121bdb05247f7 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Tue, 24 May 2016 14:52:59 +0530
+Subject: [PATCH 44/93] armv8: fsl-layerscape: Add support of GPIO structure
+
+[context adjustment]
+
+Layerscape supports GPIO registers to conrol GPIO singals.
+
+Add support of GPIO structure to enable GPIO access.
+
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index a264f9a..58c7205 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -44,6 +44,7 @@
+ #define CONFIG_SYS_PPFE_ADDR (CONFIG_SYS_IMMR + 0x3000000)
+ #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
+ #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
++#define CONFIG_SYS_GPIO1_ADDR (CONFIG_SYS_IMMR + 0x300000)
+
+ #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
+
+@@ -650,6 +651,15 @@ struct ccsr_cci400 {
+ u8 res_e004[0x10000 - 0xe004];
+ };
+
++typedef struct ccsr_gpio {
++ u32 gpdir;
++ u32 gpodr;
++ u32 gpdat;
++ u32 gpier;
++ u32 gpimr;
++ u32 gpicr;
++} ccsr_gpio_t;
++
+ /* MMU 500 */
+ #define SMMU_SCR0 (SMMU_BASE + 0x0)
+ #define SMMU_SCR1 (SMMU_BASE + 0x4)
+--
+1.7.9.5
+
--- /dev/null
+From 691deae097b2583a4e9890307c684ce9f58aca78 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Tue, 24 May 2016 15:03:33 +0530
+Subject: [PATCH 45/93] board/freescale/ls1012afrdm: Add support of Ethernet
+
+Add support of SGMII Ethernet present on FRDM board.
+Also add support of PHY reset.
+
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ board/freescale/ls1012afrdm/Makefile | 1 +
+ board/freescale/ls1012afrdm/eth.c | 86 +++++++++++++++++++++++++++++
+ board/freescale/ls1012afrdm/ls1012afrdm.c | 5 --
+ include/configs/ls1012afrdm.h | 5 ++
+ 4 files changed, 92 insertions(+), 5 deletions(-)
+ create mode 100644 board/freescale/ls1012afrdm/eth.c
+
+diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
+index dbfa2ce..1364f22 100644
+--- a/board/freescale/ls1012afrdm/Makefile
++++ b/board/freescale/ls1012afrdm/Makefile
+@@ -5,3 +5,4 @@
+ #
+
+ obj-y += ls1012afrdm.o
++obj-y += eth.o
+diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c
+new file mode 100644
+index 0000000..8ae3f45
+--- /dev/null
++++ b/board/freescale/ls1012afrdm/eth.c
+@@ -0,0 +1,86 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <netdev.h>
++#include <fm_eth.h>
++#include <fsl_mdio.h>
++#include <malloc.h>
++#include <fsl_dtsec.h>
++#include <asm/arch/soc.h>
++#include <asm/arch-fsl-layerscape/config.h>
++#include <asm/arch/fsl_serdes.h>
++
++#include "../../../drivers/net/pfe_eth/pfe_eth.h"
++#include <asm/arch-fsl-layerscape/immap_lsch2.h>
++
++#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
++
++#define MASK_ETH_PHY_RST 0x00000100
++
++void reset_phy(void)
++{
++ unsigned int val;
++ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_GPIO1_ADDR);
++
++ setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST);
++
++ val = in_be32(&pgpio->gpdat);
++ setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST);
++ mdelay(10);
++
++ val = in_be32(&pgpio->gpdat);
++ setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST);
++ mdelay(50);
++}
++
++int board_eth_init(bd_t *bis)
++{
++#ifdef CONFIG_FSL_PPFE
++ struct mii_dev *bus;
++ struct mdio_info mac1_mdio_info;
++ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
++
++
++ /*TODO Following config should be done for all boards, where is the right place to put this */
++ out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
++ out_be32(&scfg->pfebsbcr, in_be32(&scfg->pfebsbcr) | SCFG_PPFEASBCR_AWCACHE0);
++
++ /*CCI-400 QoS settings for PFE */
++ out_be32(&scfg->wr_qos1, 0x0ff00000);
++ out_be32(&scfg->rd_qos1, 0x0ff00000);
++
++ /* Set RGMII into 1G + Full duplex mode */
++ out_be32(&scfg->rgmiipcr, in_be32(&scfg->rgmiipcr) | (SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETFD));
++
++
++ out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x520), 0xFFFFFFFF);
++ out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x524), 0xFFFFFFFF);
++
++ mac1_mdio_info.reg_base = (void *)0x04200000; /*EMAC1_BASE_ADDR*/
++ mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
++
++ bus = ls1012a_mdio_init(&mac1_mdio_info);
++ if(!bus)
++ {
++ printf("Failed to register mdio \n");
++ return -1;
++ }
++
++ /*MAC1 */
++ ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
++ ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
++
++ /*MAC2 */
++ ls1012a_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
++ ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
++
++
++ cpu_eth_init(bis);
++#endif
++ return pci_eth_init(bis);
++}
+diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
+index 6be8951..6856250 100644
+--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
++++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
+@@ -133,11 +133,6 @@ int dram_init(void)
+ return 0;
+ }
+
+-int board_eth_init(bd_t *bis)
+-{
+- return pci_eth_init(bis);
+-}
+-
+ int board_early_init_f(void)
+ {
+ fsl_lsch2_early_init_f();
+diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
+index 3231ab7..5e619c1 100644
+--- a/include/configs/ls1012afrdm.h
++++ b/include/configs/ls1012afrdm.h
+@@ -18,8 +18,13 @@
+ #define CONFIG_SYS_MEMTEST_START 0x80000000
+ #define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
++#ifdef CONFIG_FSL_PPFE
++#define EMAC1_PHY_ADDR 0x2
++#define EMAC2_PHY_ADDR 0x1
+ #define CONFIG_PHYLIB
+ #define CONFIG_PHY_REALTEK
++#define CONFIG_RESET_PHY_R
++#endif
+ /*
+ * USB
+ */
+--
+1.7.9.5
+
--- /dev/null
+From ff5e4bb56636eb807f653a0e1ce5c7c721543e01 Mon Sep 17 00:00:00 2001
+From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Date: Wed, 25 May 2016 17:57:25 +0530
+Subject: [PATCH 46/93] Correcting address for PFE Driver
+
+[context adjustment]
+
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index 58c7205..a7bc2a4 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -44,7 +44,7 @@
+ #define CONFIG_SYS_PPFE_ADDR (CONFIG_SYS_IMMR + 0x3000000)
+ #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
+ #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
+-#define CONFIG_SYS_GPIO1_ADDR (CONFIG_SYS_IMMR + 0x300000)
++#define CONFIG_SYS_GPIO1_ADDR (CONFIG_SYS_IMMR + 0x1300000)
+
+ #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
+
+--
+1.7.9.5
+
--- /dev/null
+From 61bb1dceefdb4c08ff69e7e40a766a404421206f Mon Sep 17 00:00:00 2001
+From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Date: Fri, 27 May 2016 13:16:43 +0530
+Subject: [PATCH 47/93] Enable second SGMII 1G interface
+
+Enable second SGMII 1G interface on LS1012A Freedom Board
+
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+---
+ board/freescale/ls1012afrdm/eth.c | 14 ++++++++++++++
+ drivers/net/pfe_eth/pfe_eth.c | 2 +-
+ 2 files changed, 15 insertions(+), 1 deletion(-)
+
+diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c
+index 8ae3f45..90ed66b 100644
+--- a/board/freescale/ls1012afrdm/eth.c
++++ b/board/freescale/ls1012afrdm/eth.c
+@@ -19,6 +19,7 @@
+ #include <asm/arch-fsl-layerscape/immap_lsch2.h>
+
+ #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
++#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+ #define MASK_ETH_PHY_RST 0x00000100
+
+@@ -71,6 +72,19 @@ int board_eth_init(bd_t *bis)
+ return -1;
+ }
+
++ /*We don't really need this MDIO bus,
++ * this is called just to initialize EMAC2 MDIO interface*/
++ mac1_mdio_info.reg_base = (void *)0x04220000; /*EMAC2_BASE_ADDR*/
++ mac1_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
++
++ bus = ls1012a_mdio_init(&mac1_mdio_info);
++ if(!bus)
++ {
++ printf("Failed to register mdio \n");
++ return -1;
++ }
++
++
+ /*MAC1 */
+ ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+ ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
+diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
+index 40f2c39..4aa318d 100644
+--- a/drivers/net/pfe_eth/pfe_eth.c
++++ b/drivers/net/pfe_eth/pfe_eth.c
+@@ -348,7 +348,7 @@ static void ls1012a_configure_serdes(struct ls1012a_eth_dev *priv)
+
+ printf("%s %d\n", __func__, priv->gemac_port);
+ /* PCS configuration done with corresponding GEMAC */
+- bus.priv = priv->gem->gemac_base;
++ bus.priv = gem_info[priv->gemac_port].gemac_base;
+
+ ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0);
+ ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1);
+--
+1.7.9.5
+
--- /dev/null
+From a75fda9a1a7d635d1714df52068cc9fb7988e2c7 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Fri, 3 Jun 2016 11:40:09 +0800
+Subject: [PATCH 48/93] armv8: ls1012a: enable sdhc2 support
+
+A previous patch shifting board specific configurations missed
+the sdhc2 support. This patch is to fix it.
+
+Fixes: df5f76d71e30 ("Shift board specific configurations")
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ include/configs/ls1012aqds.h | 2 ++
+ include/configs/ls1012ardb.h | 2 ++
+ 2 files changed, 4 insertions(+)
+
+diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
+index 1fa7b6f..cc8e0fc 100644
+--- a/include/configs/ls1012aqds.h
++++ b/include/configs/ls1012aqds.h
+@@ -30,6 +30,8 @@
+ #ifdef CONFIG_MMC
+ #define CONFIG_CMD_MMC
+ #define CONFIG_FSL_ESDHC
++#define CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
++#define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
+ #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_CMD_FAT
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index 23722e0..2eee84a 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -64,6 +64,8 @@
+ #ifdef CONFIG_MMC
+ #define CONFIG_CMD_MMC
+ #define CONFIG_FSL_ESDHC
++#define CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
++#define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
+ #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_CMD_FAT
+--
+1.7.9.5
+
--- /dev/null
+From 1b9cf577511123dd05e1d3b1fe7fd5db43b6097f Mon Sep 17 00:00:00 2001
+From: Anji J <anji.jagarlmudi@freescale.com>
+Date: Wed, 25 May 2016 13:40:13 +0530
+Subject: [PATCH 49/93] DNCPE-296 PFE reset woraround fix
+
+- Linux driver depends on U-boot TMU initialization,
+ but U-boot tmu initialization is not as expected by Linux driver.
+- Align U-boot TMU initialization with Linux driver
+- LLM base address in DDR changed to match with Linux driver expectation.
+- Remove unwanted pfe_mod.h
+- Start PFE/network at bootup time.
+---
+ common/cmd_pfe_commands.c | 9 +-
+ drivers/net/pfe_eth/pfe.c | 16 ++--
+ drivers/net/pfe_eth/pfe/cbus/tmu_csr.h | 7 ++
+ drivers/net/pfe_eth/pfe_eth.h | 9 +-
+ drivers/net/pfe_eth/pfe_mod.h | 140 --------------------------------
+ include/configs/ls1012a_common.h | 1 -
+ 6 files changed, 24 insertions(+), 158 deletions(-)
+ delete mode 100644 drivers/net/pfe_eth/pfe_mod.h
+
+diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
+index 0e22097..ca479d7 100644
+--- a/common/cmd_pfe_commands.c
++++ b/common/cmd_pfe_commands.c
+@@ -932,7 +932,7 @@ static void send_dummy_pkt_to_hif(void)
+ /*Allocate BMU2 buffer */
+ buf = readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL);
+
+- printf("Sending a dummy pkt to HIF %x\n", buf);
++ debug("Sending a dummy pkt to HIF %x\n", buf);
+ buf += 0x80;
+ memcpy((void *)DDR_PFE_TO_VIRT(buf), dummy_pkt, sizeof(dummy_pkt));
+ /*Write length and pkt to TMU*/
+@@ -945,14 +945,13 @@ static void pfe_command_stop(int argc, char * const argv[])
+ {
+ int id;
+ u32 rx_status;
+- printf("Stopping PFE \n");
++ printf("Stopping PFE... \n");
+
+ /*Mark all descriptors as LAST_BD */
+ hif_rx_desc_disable();
+
+ /*If HIF Rx BDP is busy send a dummy packet */
+ rx_status = readl(HIF_RX_STATUS);
+- printf("rx_status %x %x\n",rx_status, BDP_CSR_RX_DMA_ACTV);
+ if(rx_status & BDP_CSR_RX_DMA_ACTV)
+ send_dummy_pkt_to_hif();
+ udelay(10);
+@@ -964,12 +963,10 @@ static void pfe_command_stop(int argc, char * const argv[])
+
+ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++)
+ {
+- printf("Stop %d\n", id);
+ /*Inform PE to stop */
+ pe_dmem_write(id, cpu_to_be32(1), PEMBOX_ADDR_CLASS, 4);
+ udelay(10);
+
+- printf("Reading %d\n", id);
+ /*Read status */
+ if(!pe_dmem_read(id, PEMBOX_ADDR_CLASS+4, 4))
+ printf("Failed to stop PE%d\n", id);
+@@ -979,12 +976,10 @@ static void pfe_command_stop(int argc, char * const argv[])
+ {
+ if(id == TMU2_ID) continue;
+
+- printf("Stop %d\n", id);
+ /*Inform PE to stop */
+ pe_dmem_write(id, 1, PEMBOX_ADDR_TMU, 4);
+ udelay(10);
+
+- printf("Reading %d\n", id);
+ /*Read status */
+ if(!pe_dmem_read(id, PEMBOX_ADDR_TMU+4, 4))
+ printf("Failed to stop PE%d\n", id);
+diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
+index 3b5570a..2c31cad 100644
+--- a/drivers/net/pfe_eth/pfe.c
++++ b/drivers/net/pfe_eth/pfe.c
+@@ -1489,17 +1489,16 @@ void tmu_init(TMU_CFG *cfg)
+ writel(0x3FF, TMU_TDQ2_SCH_CTRL);
+ #endif
+ writel(0x3FF, TMU_TDQ3_SCH_CTRL);
+-
+-
++
+ if (PLL_CLK_EN == 0)
+ writel(0x0, TMU_PE_SYS_CLK_RATIO); // Clock ratio: for 1:1 the value is 0
+ else
+ writel(0x1, TMU_PE_SYS_CLK_RATIO); // Clock ratio: for 1:2 the value is 1
+
+- //printf("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
++ debug("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
+ writel(cfg->llm_base_addr, TMU_LLM_BASE_ADDR); // Extra packet pointers will be stored from this address onwards
+-
+- //printf("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
++
++ debug("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
+ writel(cfg->llm_queue_len, TMU_LLM_QUE_LEN);
+ writel(5, TMU_TDQ_IIFG_CFG);
+ writel(DDR_BUF_SIZE, TMU_BMU_BUF_SIZE);
+@@ -1531,7 +1530,12 @@ void tmu_init(TMU_CFG *cfg)
+ u32 qmax;
+ writel((phyno << 8) | q, TMU_TEQ_CTRL);
+ writel(1 << 22, TMU_TEQ_QCFG);
+- qmax = ((phyno == 3) || (q < 8)) ? 255 : 127;
++
++ if (phyno == 3)
++ qmax = DEFAULT_TMU3_QDEPTH;
++ else
++ qmax = (q == 0) ? DEFAULT_Q0_QDEPTH : DEFAULT_MAX_QDEPTH;
++
+ writel(qmax << 18, TMU_TEQ_HW_PROB_CFG2);
+ writel(qmax >> 14, TMU_TEQ_HW_PROB_CFG3);
+ }
+diff --git a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
+index cbcbb1f..64fad04 100644
+--- a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
++++ b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
+@@ -93,10 +93,17 @@
+ #define MEM_INIT_DONE (1 << 7)
+ #define LLM_INIT (1 << 8)
+ #define LLM_INIT_DONE (1 << 9)
++#define ECC_MEM_INIT_DONE (1<<10)
+
+ typedef struct {
+ u32 llm_base_addr;
+ u32 llm_queue_len;
+ } TMU_CFG;
+
++/* Not HW related for pfe_ctrl / pfe common defines */
++#define DEFAULT_MAX_QDEPTH 80
++#define DEFAULT_Q0_QDEPTH 511 //We keep one large queue for host tx qos
++#define DEFAULT_TMU3_QDEPTH 127
++
++
+ #endif /* _TMU_CSR_H_ */
+diff --git a/drivers/net/pfe_eth/pfe_eth.h b/drivers/net/pfe_eth/pfe_eth.h
+index dfcc00e..c16b8c0 100644
+--- a/drivers/net/pfe_eth/pfe_eth.h
++++ b/drivers/net/pfe_eth/pfe_eth.h
+@@ -39,11 +39,8 @@
+ #define BMU2_BUF_COUNT (3 * SZ_1K)
+ #define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
+
+-#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
+-#define TMU_LLM_QUEUE_LEN (16 * 256) /**< Must be power of two and at least 16 * 8 = 128 bytes */
+-#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
+
+-#define HIF_RX_PKT_DDR_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
++#define HIF_RX_PKT_DDR_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
+ #define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE)
+ #define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
+ #define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE)
+@@ -72,6 +69,10 @@
+ #define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
+ #define TMU_DDR_DATA_SIZE (32 * SZ_1K)
+
++#define TMU_LLM_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
++#define TMU_LLM_QUEUE_LEN (16 * 256) /**< Must be power of two and at least 16 * 8 = 128 bytes */
++#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
++
+ //#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
+ #define ROUTE_TABLE_BASEADDR 0x800000
+ #define ROUTE_TABLE_HASH_BITS_MAX 15 /**< 32K entries */
+diff --git a/drivers/net/pfe_eth/pfe_mod.h b/drivers/net/pfe_eth/pfe_mod.h
+deleted file mode 100644
+index 9436b72..0000000
+--- a/drivers/net/pfe_eth/pfe_mod.h
++++ /dev/null
+@@ -1,140 +0,0 @@
+-/*
+- * (C) Copyright 2011
+- * Author : Mindspeed Technologes
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- * */
+-
+-
+-#ifndef _PFE_MOD_H_
+-#define _PFE_MOD_H_
+-
+-#include <linux/device.h>
+-
+-#include "pfe/pfe.h"
+-#include "pfe/cbus.h"
+-#include "pfe/cbus/bmu.h"
+-
+-#include "pfe_driver.h"
+-
+-struct pfe;
+-
+-
+-struct pfe {
+- unsigned long ddr_phys_baseaddr;
+- void *ddr_baseaddr;
+- void *cbus_baseaddr;
+- void *apb_baseaddr;
+- void *iram_baseaddr;
+- int hif_irq;
+- struct device *dev;
+- struct pci_dev *pdev;
+-
+-#if 0
+- struct pfe_ctrl ctrl;
+- struct pfe_hif hif;
+- struct pfe_eth eth;
+-#endif
+-};
+-
+-extern struct pfe *pfe;
+-
+-int pfe_probe(struct pfe *pfe);
+-int pfe_remove(struct pfe *pfe);
+-
+-#ifndef SZ_1K
+-#define SZ_1K 1024
+-#endif
+-
+-#ifndef SZ_1M
+-#define SZ_1M (1024 * 1024)
+-#endif
+-
+-/* DDR Mapping */
+-#if !defined(CONFIG_PLATFORM_PCI)
+-#define UTIL_CODE_BASEADDR 0
+-#define UTIL_CODE_SIZE (128 * SZ_1K)
+-#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
+-#define UTIL_DDR_DATA_SIZE (64 * SZ_1K)
+-#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
+-#define CLASS_DDR_DATA_SIZE (32 * SZ_1K)
+-#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
+-#define TMU_DDR_DATA_SIZE (32 * SZ_1K)
+-#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
+-#define ROUTE_TABLE_HASH_BITS 15 /**< 32K entries */
+-#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
+-#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
+-#define BMU2_BUF_COUNT (4096 - 256) /**< This is to get a total DDR size of 12MiB */
+-#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
+-#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
+-#define TMU_LLM_QUEUE_LEN (16 * 256) /**< Must be power of two and at least 16 * 8 = 128 bytes */
+-#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
+-
+-#if (TMU_LLM_BASEADDR + TMU_LLM_SIZE) > 0xC00000
+-#error DDR mapping above 12MiB
+-#endif
+-
+-#else
+-
+-#define UTIL_CODE_BASEADDR 0
+-#if defined(CONFIG_UTIL_PE_DISABLED)
+-#define UTIL_CODE_SIZE (0 * SZ_1K)
+-#else
+-#define UTIL_CODE_SIZE (8 * SZ_1K)
+-#endif
+-#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
+-#define UTIL_DDR_DATA_SIZE (0 * SZ_1K)
+-#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
+-#define CLASS_DDR_DATA_SIZE (0 * SZ_1K)
+-#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
+-#define TMU_DDR_DATA_SIZE (0 * SZ_1K)
+-#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
+-#define ROUTE_TABLE_HASH_BITS 5 /**< 32 entries */
+-#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
+-#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
+-#define BMU2_BUF_COUNT 8
+-#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
+-#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
+-#define TMU_LLM_QUEUE_LEN (16 * 8) /**< Must be power of two and at least 16 * 8 = 128 bytes */
+-#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
+-#define HIF_DESC_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
+-#define HIF_RX_DESC_SIZE (16*HIF_RX_DESC_NT)
+-#define HIF_TX_DESC_SIZE (16*HIF_TX_DESC_NT)
+-#define HIF_DESC_SIZE (HIF_RX_DESC_SIZE + HIF_TX_DESC_SIZE)
+-#define HIF_RX_PKT_DDR_BASEADDR (HIF_DESC_BASEADDR + HIF_DESC_SIZE)
+-#define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE)
+-#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
+-#define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE)
+-#define ROUTE_BASEADDR (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
+-#define ROUTE_SIZE (2 * CLASS_ROUTE_SIZE)
+-
+-#if (ROUTE_BASEADDR + ROUTE_SIZE) > 0x10000
+-#error DDR mapping above 64KiB
+-#endif
+-
+-#define PFE_HOST_TO_PCI(addr) (((u32)addr)- ((u32)DDR_BASE_ADDR))
+-#define PFE_PCI_TO_HOST(addr) (((u32)addr)+ ((u32)DDR_BASE_ADDR))
+-#endif
+-
+-/* LMEM Mapping */
+-#define BMU1_LMEM_BASEADDR 0
+-#define BMU1_BUF_COUNT 256
+-#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
+-
+-#endif /* _PFE_MOD_H */
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 3c4ab6c..57fc057 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -113,7 +113,6 @@
+ #define CONFIG_FSL_PPFE
+
+ #ifdef CONFIG_FSL_PPFE
+-#define CONFIG_CMD_PFE_START
+ #define CONFIG_CMD_PFE_COMMANDS
+ #define CONFIG_UTIL_PE_DISABLED
+
+--
+1.7.9.5
+
--- /dev/null
+From 101bee08b8441f279df657d4a45868de3f976c0c Mon Sep 17 00:00:00 2001
+From: Anji J <anji.jagarlmudi@freescale.com>
+Date: Thu, 26 May 2016 15:58:48 +0530
+Subject: [PATCH 50/93] DNCPE-138 Rest external PHYs before driver starts
+
+- Disable CONFIG_RESET_PHY_R, it is resetting PHYs after driver started.
+- Call reset_phy() before driver initialization.
+- Update bootcmd to stop pfe before kernel starts.
+---
+ board/freescale/ls1012ardb/eth.c | 1 +
+ include/configs/ls1012a_common.h | 2 +-
+ include/configs/ls1012ardb.h | 1 -
+ 3 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
+index 24fdd83..638db95 100644
+--- a/board/freescale/ls1012ardb/eth.c
++++ b/board/freescale/ls1012ardb/eth.c
+@@ -41,6 +41,7 @@ int board_eth_init(bd_t *bis)
+ struct mdio_info mac1_mdio_info;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
++ reset_phy();
+
+ /*TODO Following config should be done for all boards, where is the right place to put this */
+ out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 57fc057..2895e7a 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -152,7 +152,7 @@
+ #else
+ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
+ "earlycon=uart8250,mmio,0x21c0500"
+-#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
++#define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\
+ "$kernel_start $kernel_size && "\
+ "bootm $kernel_load"
+ #endif
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index 2eee84a..e94df74 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -24,7 +24,6 @@
+ #define EMAC2_PHY_ADDR 0x1
+ #define CONFIG_PHYLIB
+ #define CONFIG_PHY_REALTEK
+-#define CONFIG_RESET_PHY_R
+ #endif
+
+ /*
+--
+1.7.9.5
+
--- /dev/null
+From 4332e5748301df5b608f894e451999f873bda307 Mon Sep 17 00:00:00 2001
+From: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
+Date: Wed, 1 Jun 2016 05:18:38 +0530
+Subject: [PATCH 51/93] PPFE warnings Fix
+
+Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
+---
+ Makefile | 1 +
+ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 1 +
+ board/freescale/ls1012aqds/eth.c | 4 ++--
+ board/freescale/ls1012ardb/eth.c | 1 +
+ common/cmd_pfe_commands.c | 7 +++++--
+ drivers/net/pfe_eth/pfe.c | 7 ++++---
+ drivers/net/pfe_eth/pfe/pfe.h | 2 +-
+ drivers/net/pfe_eth/pfe_driver.c | 8 ++++----
+ drivers/net/pfe_eth/pfe_eth.c | 7 +------
+ drivers/net/pfe_eth/pfe_eth.h | 6 +++++-
+ drivers/net/pfe_eth/pfe_firmware.c | 2 +-
+ 11 files changed, 26 insertions(+), 20 deletions(-)
+
+diff --git a/Makefile b/Makefile
+index 100de92..1c2818c 100644
+--- a/Makefile
++++ b/Makefile
+@@ -612,6 +612,7 @@ UBOOTINCLUDE := \
+ $(if $(CONFIG_SYS_THUMB_BUILD), $(if $(CONFIG_HAS_THUMB2),, \
+ -I$(srctree)/arch/$(ARCH)/thumb1/include),) \
+ -I$(srctree)/arch/$(ARCH)/include \
++ -I$(srctree)/drivers/net/pfe_eth \
+ -include $(srctree)/include/linux/kconfig.h
+
+ NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+index 8f59577..bfd7078 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+@@ -20,6 +20,7 @@
+ #include <fm_eth.h>
+ #include <fsl_debug_server.h>
+ #include <fsl-mc/fsl_mc.h>
++#include <pfe_eth.h>
+ #ifdef CONFIG_FSL_ESDHC
+ #include <fsl_esdhc.h>
+ #endif
+diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
+index 1bd7c9d..6fbbdbe 100644
+--- a/board/freescale/ls1012aqds/eth.c
++++ b/board/freescale/ls1012aqds/eth.c
+@@ -27,8 +27,6 @@
+
+ #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+
+-static int mdio_mux[NUM_FM_PORTS];
+-
+ static const char * const mdio_names[] = {
+ "NULL",
+ "LS1012AQDS_MDIO_RGMII",
+@@ -85,6 +83,8 @@ static int ls1012aqds_mdio_reset(struct mii_dev *bus)
+
+ if(priv->realbus->reset)
+ return priv->realbus->reset(priv->realbus);
++ else
++ return -1;
+ }
+
+ static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
+diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
+index 638db95..7b0e450 100644
+--- a/board/freescale/ls1012ardb/eth.c
++++ b/board/freescale/ls1012ardb/eth.c
+@@ -17,6 +17,7 @@
+
+ #include "../../../drivers/net/pfe_eth/pfe_eth.h"
+ #include <asm/arch-fsl-layerscape/immap_lsch2.h>
++#include <i2c.h>
+
+ #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+
+diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
+index ca479d7..84999a6 100644
+--- a/common/cmd_pfe_commands.c
++++ b/common/cmd_pfe_commands.c
+@@ -602,7 +602,6 @@ void bmu(int id, void *base)
+ static void pfe_pe_status(int argc, char * const argv[])
+ {
+ int do_clear = 0;
+- int j;
+ u32 id;
+ u32 dmem_addr;
+ u32 cpu_state;
+@@ -612,9 +611,11 @@ static void pfe_pe_status(int argc, char * const argv[])
+ u32 drop;
+ char statebuf[5];
+ u32 class_debug_reg = 0;
++#ifdef CONFIG_PFE_WARN_WA
+ u32 debug_indicator;
+ u32 debug[16];
+-
++ int j;
++#endif
+ if (argc == 4 && strcmp(argv[3], "clear") == 0)
+ do_clear = 1;
+
+@@ -684,6 +685,7 @@ static void pfe_pe_status(int argc, char * const argv[])
+ statebuf, cpu_to_be32(activity_counter),
+ cpu_to_be32(rx), cpu_to_be32(tx), cpu_to_be32(drop));
+ }
++#ifdef CONFIG_PFE_WARN_WA
+ debug_indicator = pe_dmem_read(id, dmem_addr, 4);
+ dmem_addr += 4;
+ if (debug_indicator == cpu_to_be32('DBUG'))
+@@ -705,6 +707,7 @@ static void pfe_pe_status(int argc, char * const argv[])
+ printf("%08x%s", cpu_to_be32(debug[j]), (j & 0x7) == 0x7 || j == last - 1 ? "\n" : " ");
+ }
+ }
++#endif
+ }
+
+ }
+diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
+index 2c31cad..94cfe4e 100644
+--- a/drivers/net/pfe_eth/pfe.c
++++ b/drivers/net/pfe_eth/pfe.c
+@@ -368,6 +368,7 @@ void pe_lmem_write(u32 *src, u32 len, u32 offset)
+ class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, (len & 0x03));
+ }
+
++#if !defined(CONFIG_UTIL_PE_DISABLED)
+ /** Writes UTIL program memory (DDR) from the host.
+ *
+ * @param[in] addr Address to write (virtual, must be aligned on size)
+@@ -413,7 +414,7 @@ static void util_pmem_memcpy(void *dst, const void *src, unsigned int len)
+ if (len & 0x2)
+ util_pmem_write(*(u16 *)src, dst, len & 0x2);
+ }
+-
++#endif
+
+ /** Loads an elf section into pmem
+ * Code needs to be at least 16bit aligned and only PROGBITS sections are supported
+@@ -581,7 +582,7 @@ static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr)
+ return -1;
+ }
+
+- memcpy(DDR_PFE_TO_VIRT(addr), data + offset, size);
++ memcpy((void *)DDR_PFE_TO_VIRT(addr), data + offset, size);
+ }
+ }
+
+@@ -620,7 +621,7 @@ static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr)
+ }
+ else
+ {
+- memcpy(DDR_PFE_TO_VIRT(addr), data + offset, size);
++ memcpy((void *)DDR_PFE_TO_VIRT(addr), data + offset, size);
+ }
+
+ break;
+diff --git a/drivers/net/pfe_eth/pfe/pfe.h b/drivers/net/pfe_eth/pfe/pfe.h
+index 6994a20..9445155 100644
+--- a/drivers/net/pfe_eth/pfe/pfe.h
++++ b/drivers/net/pfe_eth/pfe/pfe.h
+@@ -50,7 +50,7 @@ extern void *ddr_base_addr;
+ #define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /**< CBUS physical base address as seen by PE's. */
+
+ /* Host<->PFE Mapping */
+-#define DDR_PFE_TO_VIRT(p) ((p ) + 0x80000000)
++#define DDR_PFE_TO_VIRT(p) ((unsigned long int)((p ) + 0x80000000))
+ #define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) + PFE_CBUS_PHYS_BASE_ADDR)
+ #define CBUS_PFE_TO_VIRT(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)
+
+diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
+index b06a352..2f4c385 100644
+--- a/drivers/net/pfe_eth/pfe_driver.c
++++ b/drivers/net/pfe_eth/pfe_driver.c
+@@ -87,7 +87,7 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
+ }
+ #endif
+
+- *pkt_ptr = (unsigned int )(hif_header + 1);
++ *pkt_ptr = (unsigned long)(hif_header + 1);
+ *phy_port = hif_header->port_no;
+ len -= sizeof(struct hif_header_s);
+
+@@ -174,7 +174,7 @@ int pfe_send(int phy_port, void *data, int length)
+ length = MIN_PKT_SIZE;
+ }
+
+- tx_buf_va = (u8 *)DDR_PFE_TO_VIRT(bd->data);
++ tx_buf_va = (void *)DDR_PFE_TO_VIRT(bd->data);
+ dprint("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va, bd->data);
+
+ /* Fill the gemac/phy port number to send this packet out */
+@@ -388,7 +388,7 @@ static int hif_rx_desc_init(struct pfe *pfe)
+ ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
+ #endif
+ for (i=0; i < rx_desc->rxRingSize; i++) {
+- bd_va->next = (u32 )(bd_pa + 1);
++ bd_va->next = (unsigned long)(bd_pa + 1);
+ bd_va->ctrl = ctrl;
+ bd_va->data = rx_buf_pa + (i * MAX_FRAME_SIZE);
+ // printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
+@@ -476,7 +476,7 @@ static int hif_tx_desc_init(struct pfe *pfe)
+ tx_buf_pa = pfe->ddr_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR;
+
+ for (i=0; i < tx_desc->txRingSize; i++) {
+- bd_va->next = (u32 )(bd_pa + 1);
++ bd_va->next = (unsigned long)(bd_pa + 1);
+ bd_va->data = tx_buf_pa + (i * MAX_FRAME_SIZE);
+ // printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
+ // bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
+diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
+index 4aa318d..4a935ca 100644
+--- a/drivers/net/pfe_eth/pfe_eth.c
++++ b/drivers/net/pfe_eth/pfe_eth.c
+@@ -53,10 +53,6 @@ static void ls1012a_gemac_disable(void *gemac_base)
+ writel(readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
+ }
+
+-static void ls1012a_gemac_set_mode(void *gemac_base, u32 mode)
+-{
+-}
+-
+ static void ls1012a_gemac_set_speed(void *gemac_base, u32 speed)
+ {
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+@@ -125,7 +121,6 @@ static int ls1012a_eth_init(struct eth_device *dev, bd_t * bd)
+ struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)dev->priv;
+ struct gemac_s *gem = priv->gem;
+ int speed;
+- int tmp;
+
+ /* set ethernet mac address */
+ ls1012a_gemac_set_ethaddr(gem->gemac_base, dev->enetaddr);
+@@ -220,7 +215,7 @@ static int ls1012a_eth_recv(struct eth_device *dev)
+ }
+
+ // Pass the packet up to the protocol layers.
+- net_process_received_packet((uchar *)pkt_buf, len);
++ net_process_received_packet((void *)(long int)pkt_buf, len);
+
+ return 0;
+ }
+diff --git a/drivers/net/pfe_eth/pfe_eth.h b/drivers/net/pfe_eth/pfe_eth.h
+index c16b8c0..af6191d 100644
+--- a/drivers/net/pfe_eth/pfe_eth.h
++++ b/drivers/net/pfe_eth/pfe_eth.h
+@@ -26,6 +26,7 @@
+
+
+ #include "pfe_driver.h"
++#include <phy.h>
+
+ #ifndef SZ_1K
+ #define SZ_1K 1024
+@@ -151,7 +152,10 @@ struct firmware {
+
+ int pfe_probe(struct pfe *pfe);
+ int pfe_remove(struct pfe *pfe);
+-
++struct mii_dev *ls1012a_mdio_init(struct mdio_info *mdio_info);
++void ls1012a_set_mdio(int dev_id, struct mii_dev *bus);
++void ls1012a_set_phy_address_mode(int dev_id, int phy_id, int phy_mode);
++int ls1012a_gemac_initialize(bd_t * bis, int dev_id, char *devname);
+
+ //#define dprint(fmt, arg...) printf(fmt, ##arg)
+ #define dprint(fmt, arg...)
+diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
+index 165eb3c..5957afd 100644
+--- a/drivers/net/pfe_eth/pfe_firmware.c
++++ b/drivers/net/pfe_eth/pfe_firmware.c
+@@ -45,7 +45,7 @@ int pfe_load_elf(int pe_mask, const struct firmware *fw)
+ printf("%s: no of sections: %d\n", __func__, sections);
+
+ /* Some sanity checks */
+- if (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG))
++ if (strncmp((char *)&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG))
+ {
+ printf("%s: incorrect elf magic number\n", __func__);
+ return -1;
+--
+1.7.9.5
+
--- /dev/null
+From e6ab05ee921fe2c8ae2dabdd5c1f27e2ff2446cb Mon Sep 17 00:00:00 2001
+From: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
+Date: Mon, 13 Jun 2016 07:37:52 +0530
+Subject: [PATCH 52/93] Add Freescale Copyright in PPFE driver
+
+Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
+---
+ board/freescale/ls1012ardb/eth.c | 2 +-
+ common/cmd_gemac_stat.c | 25 ++++---------------------
+ common/cmd_pfe_commands.c | 25 ++++---------------------
+ drivers/net/pfe_eth/Makefile | 4 ++++
+ drivers/net/pfe_eth/hal.h | 26 ++++----------------------
+ drivers/net/pfe_eth/pfe.c | 5 +++++
+ drivers/net/pfe_eth/pfe/cbus.h | 5 +++++
+ drivers/net/pfe_eth/pfe/cbus/bmu.h | 5 +++++
+ drivers/net/pfe_eth/pfe/cbus/class_csr.h | 5 +++++
+ drivers/net/pfe_eth/pfe/cbus/emac.h | 5 +++++
+ drivers/net/pfe_eth/pfe/cbus/gpi.h | 5 +++++
+ drivers/net/pfe_eth/pfe/cbus/gpt.h | 5 +++++
+ drivers/net/pfe_eth/pfe/cbus/hif.h | 5 +++++
+ drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h | 5 +++++
+ drivers/net/pfe_eth/pfe/cbus/tmu_csr.h | 5 +++++
+ drivers/net/pfe_eth/pfe/cbus/util_csr.h | 5 +++++
+ drivers/net/pfe_eth/pfe/class.h | 5 +++++
+ drivers/net/pfe_eth/pfe/class/ccu.h | 5 +++++
+ drivers/net/pfe_eth/pfe/class/efet.h | 5 +++++
+ drivers/net/pfe_eth/pfe/class/mac_hash.h | 5 +++++
+ drivers/net/pfe_eth/pfe/class/perg.h | 5 +++++
+ drivers/net/pfe_eth/pfe/class/vlan_hash.h | 5 +++++
+ drivers/net/pfe_eth/pfe/gpt.h | 5 +++++
+ drivers/net/pfe_eth/pfe/pe.h | 5 +++++
+ drivers/net/pfe_eth/pfe/pfe.h | 5 +++++
+ drivers/net/pfe_eth/pfe/tmu.h | 5 +++++
+ drivers/net/pfe_eth/pfe/tmu/phy_queue.h | 5 +++++
+ drivers/net/pfe_eth/pfe/tmu/sched.h | 5 +++++
+ drivers/net/pfe_eth/pfe/tmu/shaper.h | 5 +++++
+ drivers/net/pfe_eth/pfe/uart.h | 5 +++++
+ drivers/net/pfe_eth/pfe/util/eape.h | 5 +++++
+ drivers/net/pfe_eth/pfe/util/efet.h | 5 +++++
+ drivers/net/pfe_eth/pfe/util/inq.h | 5 +++++
+ drivers/net/pfe_eth/pfe_driver.c | 27 ++++-----------------------
+ drivers/net/pfe_eth/pfe_driver.h | 26 ++++----------------------
+ drivers/net/pfe_eth/pfe_eth.c | 5 +++++
+ drivers/net/pfe_eth/pfe_eth.h | 26 ++++----------------------
+ drivers/net/pfe_eth/pfe_firmware.c | 6 +++++-
+ drivers/net/pfe_eth/pfe_firmware.h | 6 +++++-
+ 39 files changed, 184 insertions(+), 134 deletions(-)
+
+diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
+index 7b0e450..34ba56d 100644
+--- a/board/freescale/ls1012ardb/eth.c
++++ b/board/freescale/ls1012ardb/eth.c
+@@ -1,7 +1,7 @@
+ /*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+- * SPDX-License-Identifier: GPL-2.0+
++ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+ #include <common.h>
+diff --git a/common/cmd_gemac_stat.c b/common/cmd_gemac_stat.c
+index 49bb1aa..fb621a2 100644
+--- a/common/cmd_gemac_stat.c
++++ b/common/cmd_gemac_stat.c
+@@ -1,25 +1,8 @@
+ /*
+- * (C) Copyright 2003
+- * Author : Laurent Brando (Mindspeed Technologies)
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+
+ /**
+ * @file
+diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
+index 84999a6..92917e0 100644
+--- a/common/cmd_pfe_commands.c
++++ b/common/cmd_pfe_commands.c
+@@ -1,25 +1,8 @@
+ /*
+- * (C) Copyright 2012
+- * Author : Bill Westland (Mindspeed Technologies)
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+
+ /**
+ * @file
+diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
+index 1af837d..bc45d8f 100644
+--- a/drivers/net/pfe_eth/Makefile
++++ b/drivers/net/pfe_eth/Makefile
+@@ -1 +1,5 @@
++# Copyright (C) 2016 Freescale Semiconductor Inc.
++#
++# SPDX-License-Identifier:GPL-2.0+
++
+ obj-y += pfe_eth.o pfe_firmware.o pfe.o pfe_driver.o
+diff --git a/drivers/net/pfe_eth/hal.h b/drivers/net/pfe_eth/hal.h
+index e795fe6..ff510ac 100644
+--- a/drivers/net/pfe_eth/hal.h
++++ b/drivers/net/pfe_eth/hal.h
+@@ -1,26 +1,8 @@
+ /*
+- * (C) Copyright 2011
+- * Author : Mindspeed Technologes
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- * */
+-
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _HAL_H_
+ #define _HAL_H_
+
+diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
+index 94cfe4e..68cf23a 100644
+--- a/drivers/net/pfe_eth/pfe.c
++++ b/drivers/net/pfe_eth/pfe.c
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #include "hal.h"
+ #include "pfe/pfe.h"
+
+diff --git a/drivers/net/pfe_eth/pfe/cbus.h b/drivers/net/pfe_eth/pfe/cbus.h
+index 778fe45..d46a765 100644
+--- a/drivers/net/pfe_eth/pfe/cbus.h
++++ b/drivers/net/pfe_eth/pfe/cbus.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _CBUS_H_
+ #define _CBUS_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/cbus/bmu.h b/drivers/net/pfe_eth/pfe/cbus/bmu.h
+index f3e5e6d..fd37570 100644
+--- a/drivers/net/pfe_eth/pfe/cbus/bmu.h
++++ b/drivers/net/pfe_eth/pfe/cbus/bmu.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _BMU_H_
+ #define _BMU_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/cbus/class_csr.h b/drivers/net/pfe_eth/pfe/cbus/class_csr.h
+index f3151ec..4c2c3fa 100644
+--- a/drivers/net/pfe_eth/pfe/cbus/class_csr.h
++++ b/drivers/net/pfe_eth/pfe/cbus/class_csr.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _CLASS_CSR_H_
+ #define _CLASS_CSR_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/cbus/emac.h b/drivers/net/pfe_eth/pfe/cbus/emac.h
+index 1f308ce..aead064 100644
+--- a/drivers/net/pfe_eth/pfe/cbus/emac.h
++++ b/drivers/net/pfe_eth/pfe/cbus/emac.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _EMAC_H_
+ #define _EMAC_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/cbus/gpi.h b/drivers/net/pfe_eth/pfe/cbus/gpi.h
+index d2d165f..7792d6c 100644
+--- a/drivers/net/pfe_eth/pfe/cbus/gpi.h
++++ b/drivers/net/pfe_eth/pfe/cbus/gpi.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _GPI_H_
+ #define _GPI_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/cbus/gpt.h b/drivers/net/pfe_eth/pfe/cbus/gpt.h
+index f8c114b..0ec5fdc 100644
+--- a/drivers/net/pfe_eth/pfe/cbus/gpt.h
++++ b/drivers/net/pfe_eth/pfe/cbus/gpt.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _CBUS_GPT_H_
+ #define _CBUS_GPT_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/cbus/hif.h b/drivers/net/pfe_eth/pfe/cbus/hif.h
+index 2329faa..45bc0b2 100644
+--- a/drivers/net/pfe_eth/pfe/cbus/hif.h
++++ b/drivers/net/pfe_eth/pfe/cbus/hif.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _HIF_H_
+ #define _HIF_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h b/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
+index 93cb946..55ddc8c 100644
+--- a/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
++++ b/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _HIF_NOCPY_H_
+ #define _HIF_NOCPY_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
+index 64fad04..058874e 100644
+--- a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
++++ b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _TMU_CSR_H_
+ #define _TMU_CSR_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/cbus/util_csr.h b/drivers/net/pfe_eth/pfe/cbus/util_csr.h
+index d67e849..14079db 100644
+--- a/drivers/net/pfe_eth/pfe/cbus/util_csr.h
++++ b/drivers/net/pfe_eth/pfe/cbus/util_csr.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _UTIL_CSR_H_
+ #define _UTIL_CSR_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/class.h b/drivers/net/pfe_eth/pfe/class.h
+index 33ad826..87b1399 100644
+--- a/drivers/net/pfe_eth/pfe/class.h
++++ b/drivers/net/pfe_eth/pfe/class.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _CLASS_H_
+ #define _CLASS_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/class/ccu.h b/drivers/net/pfe_eth/pfe/class/ccu.h
+index 2c43d97..605ac16 100644
+--- a/drivers/net/pfe_eth/pfe/class/ccu.h
++++ b/drivers/net/pfe_eth/pfe/class/ccu.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _CCU_H_
+ #define _CCU_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/class/efet.h b/drivers/net/pfe_eth/pfe/class/efet.h
+index 4f3cc25..7ef2978 100644
+--- a/drivers/net/pfe_eth/pfe/class/efet.h
++++ b/drivers/net/pfe_eth/pfe/class/efet.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _CLASS_EFET_H_
+ #define _CLASS_EFET_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/class/mac_hash.h b/drivers/net/pfe_eth/pfe/class/mac_hash.h
+index 68023b4..ca24ca5 100644
+--- a/drivers/net/pfe_eth/pfe/class/mac_hash.h
++++ b/drivers/net/pfe_eth/pfe/class/mac_hash.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _MAC_HASH_H_
+ #define _MAC_HASH_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/class/perg.h b/drivers/net/pfe_eth/pfe/class/perg.h
+index 7297171..dbb5a3b 100644
+--- a/drivers/net/pfe_eth/pfe/class/perg.h
++++ b/drivers/net/pfe_eth/pfe/class/perg.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _PERG_H_
+ #define _PERG_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/class/vlan_hash.h b/drivers/net/pfe_eth/pfe/class/vlan_hash.h
+index a54ac19..cdad97c 100644
+--- a/drivers/net/pfe_eth/pfe/class/vlan_hash.h
++++ b/drivers/net/pfe_eth/pfe/class/vlan_hash.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _VLAN_HASH_H_
+ #define _VLAN_HASH_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/gpt.h b/drivers/net/pfe_eth/pfe/gpt.h
+index d820277..6fce042 100644
+--- a/drivers/net/pfe_eth/pfe/gpt.h
++++ b/drivers/net/pfe_eth/pfe/gpt.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _GPT_H_
+ #define _GPT_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/pe.h b/drivers/net/pfe_eth/pfe/pe.h
+index a3838f5..ac8cbf2 100644
+--- a/drivers/net/pfe_eth/pfe/pe.h
++++ b/drivers/net/pfe_eth/pfe/pe.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _PE_H_
+ #define _PE_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/pfe.h b/drivers/net/pfe_eth/pfe/pfe.h
+index 9445155..ac1ecb8 100644
+--- a/drivers/net/pfe_eth/pfe/pfe.h
++++ b/drivers/net/pfe_eth/pfe/pfe.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _PFE_H_
+ #define _PFE_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/tmu.h b/drivers/net/pfe_eth/pfe/tmu.h
+index 12eaf12..dd697be 100644
+--- a/drivers/net/pfe_eth/pfe/tmu.h
++++ b/drivers/net/pfe_eth/pfe/tmu.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _TMU_H_
+ #define _TMU_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/tmu/phy_queue.h b/drivers/net/pfe_eth/pfe/tmu/phy_queue.h
+index 9eef9a9..b9a0925 100644
+--- a/drivers/net/pfe_eth/pfe/tmu/phy_queue.h
++++ b/drivers/net/pfe_eth/pfe/tmu/phy_queue.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _PHY_QUEUE_H_
+ #define _PHY_QUEUE_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/tmu/sched.h b/drivers/net/pfe_eth/pfe/tmu/sched.h
+index 0c741cc..954dc8f 100644
+--- a/drivers/net/pfe_eth/pfe/tmu/sched.h
++++ b/drivers/net/pfe_eth/pfe/tmu/sched.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _SCHED_H_
+ #define _SCHED_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/tmu/shaper.h b/drivers/net/pfe_eth/pfe/tmu/shaper.h
+index 76315f3..81c367d 100644
+--- a/drivers/net/pfe_eth/pfe/tmu/shaper.h
++++ b/drivers/net/pfe_eth/pfe/tmu/shaper.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _SHAPER_H_
+ #define _SHAPER_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/uart.h b/drivers/net/pfe_eth/pfe/uart.h
+index 483d446..2268430 100644
+--- a/drivers/net/pfe_eth/pfe/uart.h
++++ b/drivers/net/pfe_eth/pfe/uart.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _UART_H_
+ #define _UART_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/util/eape.h b/drivers/net/pfe_eth/pfe/util/eape.h
+index 07344dc..77af2d4 100644
+--- a/drivers/net/pfe_eth/pfe/util/eape.h
++++ b/drivers/net/pfe_eth/pfe/util/eape.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _EAPE_H_
+ #define _EAPE_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/util/efet.h b/drivers/net/pfe_eth/pfe/util/efet.h
+index 12d0310..eed87fe 100644
+--- a/drivers/net/pfe_eth/pfe/util/efet.h
++++ b/drivers/net/pfe_eth/pfe/util/efet.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _UTIL_EFET_H_
+ #define _UTIL_EFET_H_
+
+diff --git a/drivers/net/pfe_eth/pfe/util/inq.h b/drivers/net/pfe_eth/pfe/util/inq.h
+index 73d1acb..7ee008b 100644
+--- a/drivers/net/pfe_eth/pfe/util/inq.h
++++ b/drivers/net/pfe_eth/pfe/util/inq.h
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _INQ_H_
+ #define _INQ_H_
+
+diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
+index 2f4c385..e252fcf 100644
+--- a/drivers/net/pfe_eth/pfe_driver.c
++++ b/drivers/net/pfe_eth/pfe_driver.c
+@@ -1,27 +1,8 @@
+ /*
+- * (C) Copyright 2011
+- * Author : Mindspeed Technologes
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- * */
+-
+-
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #include "hal.h"
+ #include "pfe/pfe.h"
+ #include "pfe_driver.h"
+diff --git a/drivers/net/pfe_eth/pfe_driver.h b/drivers/net/pfe_eth/pfe_driver.h
+index 4d2e8b6..2ef8e5c 100644
+--- a/drivers/net/pfe_eth/pfe_driver.h
++++ b/drivers/net/pfe_eth/pfe_driver.h
+@@ -1,26 +1,8 @@
+ /*
+- * (C) Copyright 2011
+- * Author : Mindspeed Technologes
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- * */
+-
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef __PFE_DRIVER_H__
+ #define __PFE_DRIVER_H__
+
+diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
+index 4a935ca..528ede9 100644
+--- a/drivers/net/pfe_eth/pfe_eth.c
++++ b/drivers/net/pfe_eth/pfe_eth.c
+@@ -1,3 +1,8 @@
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #include <common.h>
+ #include <config.h>
+ //#include <asm/arch/hardware.h>
+diff --git a/drivers/net/pfe_eth/pfe_eth.h b/drivers/net/pfe_eth/pfe_eth.h
+index af6191d..358fa58 100644
+--- a/drivers/net/pfe_eth/pfe_eth.h
++++ b/drivers/net/pfe_eth/pfe_eth.h
+@@ -1,26 +1,8 @@
+ /*
+- * (C) Copyright 2011
+- * Author : Mindspeed Technologes
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- * */
+-
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+ #ifndef _LS1012a_ETH_H_
+ #define _LS1012a_ETH_H_
+
+diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
+index 5957afd..e190514 100644
+--- a/drivers/net/pfe_eth/pfe_firmware.c
++++ b/drivers/net/pfe_eth/pfe_firmware.c
+@@ -1,4 +1,8 @@
+-
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+
+ /** @file
+ * Contains all the functions to handle parsing and loading of PE firmware files.
+diff --git a/drivers/net/pfe_eth/pfe_firmware.h b/drivers/net/pfe_eth/pfe_firmware.h
+index 2823162..ecae3e3 100644
+--- a/drivers/net/pfe_eth/pfe_firmware.h
++++ b/drivers/net/pfe_eth/pfe_firmware.h
+@@ -1,4 +1,8 @@
+-
++/*
++* Copyright (C) 2016 Freescale Semiconductor Inc.
++*
++* SPDX-License-Identifier:GPL-2.0+
++*/
+
+ /** @file
+ * Contains all the defines to handle parsing and loading of PE firmware files.
+--
+1.7.9.5
+
--- /dev/null
+From 9722009432a5553b11c8e0a04a275654de11dbc4 Mon Sep 17 00:00:00 2001
+From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Date: Mon, 13 Jun 2016 16:33:06 +0530
+Subject: [PATCH 53/93] armv8: arch-fsl-layerscape: Update name of Soc
+
+Update the name of the Soc.
+
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+---
+ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+index e4ff990..7a943be 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+@@ -8,13 +8,13 @@
+ #define _FSL_LAYERSCAPE_CPU_H
+
+ static struct cpu_type cpu_type_list[] = {
+- CPU_TYPE_ENTRY(LS2080, LS2080, 8),
+- CPU_TYPE_ENTRY(LS2085, LS2085, 8),
+- CPU_TYPE_ENTRY(LS2045, LS2045, 4),
+- CPU_TYPE_ENTRY(LS1043, LS1043, 4),
+- CPU_TYPE_ENTRY(LS1023, LS1023, 2),
+- CPU_TYPE_ENTRY(LS2040, LS2040, 4),
+- CPU_TYPE_ENTRY(LS1012, LS1012, 1),
++ CPU_TYPE_ENTRY(LS2080A, LS2080, 8),
++ CPU_TYPE_ENTRY(LS2085A, LS2085, 8),
++ CPU_TYPE_ENTRY(LS2045A, LS2045, 4),
++ CPU_TYPE_ENTRY(LS1043A, LS1043, 4),
++ CPU_TYPE_ENTRY(LS1023A, LS1023, 2),
++ CPU_TYPE_ENTRY(LS2040A, LS2040, 4),
++ CPU_TYPE_ENTRY(LS1012A, LS1012, 1),
+ };
+
+ #ifndef CONFIG_SYS_DCACHE_OFF
+--
+1.7.9.5
+
--- /dev/null
+From 0ecab71ba6f860a831288337d96b0f4b0fbf12c6 Mon Sep 17 00:00:00 2001
+From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Date: Mon, 13 Jun 2016 17:29:59 +0530
+Subject: [PATCH 54/93] armv8: fsl-layerscape: Update DDR timings
+
+DDR timigs displayed for LS1012A were half of true value.
+Updated DDR value to 1000 MT/s.
+
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+---
+ .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+index 63e5bed..a4dde5b 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+@@ -92,9 +92,10 @@ void get_sys_info(struct sys_info *sys_info)
+ freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+ }
+
+- if (ver == SVR_LS1012)
++ if (ver == SVR_LS1012){
+ sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
+-
++ sys_info->freq_ddrbus *=2;
++ }
+ #define HWA_CGA_M1_CLK_SEL 0xe0000000
+ #define HWA_CGA_M1_CLK_SHIFT 29
+ #ifdef CONFIG_SYS_DPAA_FMAN
+--
+1.7.9.5
+
--- /dev/null
+From 0431dc26df78b00cef190f45f203a1598b4ba428 Mon Sep 17 00:00:00 2001
+From: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
+Date: Tue, 14 Jun 2016 10:07:41 +0530
+Subject: [PATCH 55/93] Add License file for PPFE firmware bins
+
+Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ drivers/net/pfe_eth/Freescale-Binary-EULA.txt | 80 +++++++++++++++++++++++++
+ 1 file changed, 80 insertions(+)
+ create mode 100644 drivers/net/pfe_eth/Freescale-Binary-EULA.txt
+
+diff --git a/drivers/net/pfe_eth/Freescale-Binary-EULA.txt b/drivers/net/pfe_eth/Freescale-Binary-EULA.txt
+new file mode 100644
+index 0000000..628fa93
+--- /dev/null
++++ b/drivers/net/pfe_eth/Freescale-Binary-EULA.txt
+@@ -0,0 +1,80 @@
++Copyright © 2016, Freescale Semiconductor, Inc. All rights reserved.
++
++Software License Agreement (.Agreement.)
++
++ANY USE, REPRODUCTION, OR DISTRIBUTION OF THE ACCOMPANYING BINARY SOFTWARE
++CONSTITUTES LICENSEE'S ACCEPTANCE OF THE TERMS AND CONDITIONS OF THIS
++AGREEMENT.
++
++Licensed Software. .Binary Software. means software in binary form specified
++in ANNEX A Subject to the terms and conditions of this Agreement, Freescale
++Semiconductor, Inc., a 100% affiliated company of NXP Semiconductors N.V.
++which will be renamed in due course ("NXP"), grants to Licensee a worldwide,
++non-exclusive, and royalty-free license to use, reproduce, and distribute the
++Binary Software in its complete and unmodified binary form as provided by NXP.
++
++Restrictions. Licensee must reproduce the NXP copyright notice above with each
++binary copy of the Binary Software. Licensee must not reverse engineer,
++decompile, disassemble or modify in any way the Binary Software. Licensee must
++not use the Binary Software in violation of any applicable law or regulation.
++This Agreement shall automatically terminate upon Licensee's breach of any
++term or condition of this Agreement in which case, Licensee shall destroy all
++copies of the Binary Software.
++
++Warranty Disclaimer. TO THE MAXIMUM EXTENT PERMITTED BY LAW, NXP EXPRESSLY
++DISCLAIMS ANY WARRANTY FOR THE BINARY SOFTWARE. THE BINARY SOFTWARE IS
++PROVIDED .AS IS., WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED,
++INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF MERCHANTABILITY,
++FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. LICENSEE ASSUMES
++THE ENTIRE RISK ARISING OUT OF THE USE OR PERFORMANCE OF THE BINARY SOFTWARE,
++OR ANY SYSTEMS LICENSEE DESIGNS USING THE BINARY SOFTWARE (IF ANY). WITHOUT
++LIMITING THE GENERALITY OF THE FOREGOING, NXP DOES NOT WARRANT THAT THE BINARY
++SOFTWARE IS ERROR-FREE OR WILL OPERATE WITHOUT INTERRUPTION, AND NXP GRANTS
++NO WARRANTY REGARDING ITS USE OR THE RESULTS THEREFROM, INCLUDING ITS
++CORRECTNESS, ACCURACY, OR RELIABILITY.
++
++Limitation of Liability. IN NO EVENT WILL NXP, OR ANY OF NXP'S LICENSORS HAVE
++ANY LIABILITY HEREUNDER FOR ANY INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES,
++HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER FOR BREACH OF CONTRACT,
++TORT (INCLUDING NEGLIGENCE), OR OTHERWISE, ARISING OUT OF THIS AGREEMENT,
++ INCLUDING DAMAGES FOR LOSS OF PROFITS, OR THE COST OF PROCUREMENT OF
++ SUBSTITUTE GOODS, EVEN IF SUCH PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
++ SUCH DAMAGES. NXP.S TOTAL LIABILITY FOR ALL COSTS, DAMAGES, CLAIMS, OR LOSSES
++ WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT OR THE BINARY
++ SOFTWARE SUPPLIED UNDER THIS AGREEMENT IS LIMITED TO THE AGGREGATE AMOUNT PAID
++ BY LICENSEE TO NXP IN CONNECTION WITH THE BINARY SOFTWARE TO WHICH LOSSES OR
++ DAMAGES ARE CLAIMED.
++
++Trade Compliance. Licensee shall comply with all applicable export and import
++ control laws and regulations including but not limited to the US Export
++ Administration Regulation (including prohibited party lists issued by other
++ federal governments), Catch-all regulations and all national and international
++ embargoes. Licensee will not knowingly transfer, divert, export or re-export,
++ directly or indirectly, any product, software, including software source code,
++ or technology restricted by such regulations or by other applicable national
++ regulations, received from the other party under this Agreement, or any direct
++ product of such software or technical data to any person, firm, entity, country
++ or destination to which such transfer, diversion, export or re-export is
++ restricted or prohibited, without obtaining prior written authorization from
++ the applicable competent government authorities to the extent required by
++ those laws.
++
++Restrictions, Warranty Disclaimer, Limitation of Liability, Trade Compliance,
++ and Governing Law shall survive termination or expiration of this Agreement.
++
++Governing Law. This Agreement will be governed by, construed, and enforced in
++ accordance with the laws of the State of Texas, USA, without regard to
++ conflicts of laws principles, will apply to all matters relating to this
++ Agreement or the binary software, and Licensee agrees that any litigation will
++ be subject to the exclusive jurisdiction of the state or federal courts Texas,
++ USA. The United Nations Convention on Contracts for the International Sale of
++ Goods will not apply to this Agreement.
++
++
++ANNEX A
++BINARY SOFTWARE
++Only software in binary form may be provided under this Agreement
++Here is a list of software covered by this Agreement:
++class_sbl_elf.fw
++tmu_sbl_elf.fw
++util_sbl_elf.fw
+--
+1.7.9.5
+
--- /dev/null
+From 22424b4b25faefec704556d47751ad54c811ee09 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Wed, 15 Jun 2016 15:45:12 +0800
+Subject: [PATCH 56/93] mmc: fsl_esdhc: disable sdhc2 when no card inserted
+ for ls1012aqds
+
+This is a temporary workaround patch for ls1012aqds becasue there
+was host controller hardware issue found on some QDS boards when
+there was no eMMC adapter card inserted. This would cause below
+continious error messages in linux. So this patch is to disable
+sdhc2 when finding there isn't card inserted.
+"mmc1: Controller never released inhibit bit(s)."
+
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ board/freescale/ls1012aqds/ls1012aqds.c | 11 +++++++++++
+ drivers/mmc/fsl_esdhc.c | 9 +++++++++
+ include/fdt_support.h | 4 +++-
+ 3 files changed, 23 insertions(+), 1 deletion(-)
+
+diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
+index b7365e8..56004ea 100644
+--- a/board/freescale/ls1012aqds/ls1012aqds.c
++++ b/board/freescale/ls1012aqds/ls1012aqds.c
+@@ -161,6 +161,17 @@ int select_i2c_ch_pca9547(u8 ch)
+ return 0;
+ }
+
++int mmc_check_sdhc2_card(void)
++{
++ u8 card_id;
++
++ card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
++ if (card_id == 0x7)
++ return 0;
++ else
++ return 1;
++}
++
+ int dram_init(void)
+ {
+ mmdc_init();
+diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
+index 2c6e175..98f3cca 100644
+--- a/drivers/mmc/fsl_esdhc.c
++++ b/drivers/mmc/fsl_esdhc.c
+@@ -774,6 +774,11 @@ int fsl_esdhc_mmc_init(bd_t *bis)
+ #endif
+ }
+
++__weak int mmc_check_sdhc2_card(void)
++{
++ return 1;
++}
++
+ #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+ void mmc_adapter_card_type_ident(void)
+ {
+@@ -817,6 +822,7 @@ void mmc_adapter_card_type_ident(void)
+ void fdt_fixup_esdhc(void *blob, bd_t *bd)
+ {
+ const char *compat = "fsl,esdhc";
++ const char *compat1 = "fsl,ls1012a-esdhc1";
+
+ #ifdef CONFIG_FSL_ESDHC_PIN_MUX
+ if (!hwconfig("esdhc")) {
+@@ -839,5 +845,8 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd)
+ #endif
+ do_fixup_by_compat(blob, compat, "status", "okay",
+ 4 + 1, 1);
++ if (!mmc_check_sdhc2_card())
++ do_fixup_by_compat(blob, compat1, "status", "disabled",
++ 4 + 1, 1);
+ }
+ #endif
+diff --git a/include/fdt_support.h b/include/fdt_support.h
+index 296add0..2e66eb1 100644
+--- a/include/fdt_support.h
++++ b/include/fdt_support.h
+@@ -240,7 +240,9 @@ int arch_fixup_memory_node(void *blob);
+
+ int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width,
+ u32 height, u32 stride, const char *format);
+-
++#ifdef CONFIG_FSL_ESDHC
++int mmc_check_sdhc2_card(void);
++#endif
+ #endif /* ifdef CONFIG_OF_LIBFDT */
+
+ #ifdef USE_HOSTCC
+--
+1.7.9.5
+
--- /dev/null
+From 0ff26c3761e5a17d21e7ee0bd9a2068f55c84d55 Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Wed, 15 Jun 2016 14:57:08 +0800
+Subject: [PATCH 57/93] driver: spi: Fix DSPI bug after adding exceed 16MB for
+ QSPI
+
+=> sf probe 1:0
+SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total
+16 MiB
+=> mw.l 80000000 55555555 1100
+=> mw.l 80020000 aaaaaaaa 1100
+=> sf erase 0 +1100
+SF: 65536 bytes @ 0x0 Erased: OK
+=> sf write 80020000 0 1100
+device 0 offset 0x0, size 0x1100
+SF: 4352 bytes @ 0x0 Written: OK
+=> sf read 80000000 0 1100
+device 0 offset 0x0, size 0x1100
+SF: 4352 bytes @ 0x0 Read: OK
+=> cmp.b 80000000 80020000 1100
+byte at 0x00000000800010fe (0xff) != byte at 0x00000000800210fe (0xaa)
+Total of 4350 byte(s) were the same
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi/spi_flash.c | 21 +++++++++++++++------
+ 1 file changed, 15 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
+index b0f09ab..e04bd55 100644
+--- a/drivers/mtd/spi/spi_flash.c
++++ b/drivers/mtd/spi/spi_flash.c
+@@ -326,8 +326,11 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+ return -EINVAL;
+ }
+ }
++ if (flash->size > SPI_FLASH_16MB_BOUN)
++ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
++ else
++ cmdsz = SPI_FLASH_CMD_LEN;
+
+- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
+ cmd = calloc(1, cmdsz);
+ if (!cmd) {
+ debug("SF: Failed to allocate cmd\n");
+@@ -353,7 +356,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+ debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
+ cmd[2], cmd[3], erase_addr);
+
+- ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
++ ret = spi_flash_write_common(flash, cmd, cmdsz, NULL, 0);
+ if (ret < 0) {
+ debug("SF: erase failed\n");
+ break;
+@@ -385,8 +388,10 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ return -EINVAL;
+ }
+ }
+-
+- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
++ if (flash->size > SPI_FLASH_16MB_BOUN)
++ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
++ else
++ cmdsz = SPI_FLASH_CMD_LEN;
+ cmd = calloc(1, cmdsz);
+ if (!cmd) {
+ debug("SF: Failed to allocate cmd\n");
+@@ -418,7 +423,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
+ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+
+- ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
++ ret = spi_flash_write_common(flash, cmd, cmdsz,
+ buf + actual, chunk_len);
+ if (ret < 0) {
+ debug("SF: write failed\n");
+@@ -482,7 +487,11 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
+ return 0;
+ }
+
+- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
++ if (flash->size > SPI_FLASH_16MB_BOUN)
++ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
++ else
++ cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
++
+ cmd = calloc(1, cmdsz);
+ if (!cmd) {
+ debug("SF: Failed to allocate cmd\n");
+--
+1.7.9.5
+
--- /dev/null
+From 0499ca266f668c9d72217631151f3b6e15350134 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Wed, 15 Jun 2016 17:42:51 +0530
+Subject: [PATCH 58/93] mmc: fsl_esdhc: disable sdhc2 when no card inserted
+ for ls1012ardb
+
+This is a temporary workaround patch for ls1012ardb becasue there
+was host controller hardware issue found on some RDB boards when
+there was no eMMC adapter card inserted. This would cause below
+continious error messages in linux. So this patch is to disable
+sdhc2 when finding there isn't card inserted.
+"mmc1: Controller never released inhibit bit(s)."
+
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ board/freescale/ls1012ardb/ls1012ardb.c | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
+index 90cbd5e..ad4d8ee 100644
+--- a/board/freescale/ls1012ardb/ls1012ardb.c
++++ b/board/freescale/ls1012ardb/ls1012ardb.c
+@@ -171,6 +171,30 @@ int board_early_init_f(void)
+ return 0;
+ }
+
++int mmc_check_sdhc2_card(void)
++{
++ u8 io = 0;
++ u8 is_card = 0;
++
++ /* Initialize i2c early for Serial flash bank information */
++ i2c_set_bus_num(0);
++
++ if (i2c_read(I2C_MUX_IO1_ADDR, 0, 1, &io, 1) < 0) {
++ printf("Error reading i2c boot information!\n");
++ return 0; /* Don't want to hang() on this error */
++ }
++
++ io = io & 0x0c;
++
++ switch (io) {
++ case 0:
++ case 8:
++ is_card = 1;
++ }
++
++ return is_card;
++}
++
+ int board_init(void)
+ {
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+--
+1.7.9.5
+
--- /dev/null
+From 4df84c450d7ce450986e5f1dc5e7ab164b9e0e32 Mon Sep 17 00:00:00 2001
+From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Date: Fri, 17 Jun 2016 10:04:34 +0530
+Subject: [PATCH 59/93] armv8: ls1012a: Make FAT and EXT2 commands support
+ common
+
+Makes FAT and EXT2 commands support common for LS1012A QDS,
+RDB and FRDM.
+
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+---
+ include/configs/ls1012a_common.h | 5 +++++
+ include/configs/ls1012afrdm.h | 1 -
+ include/configs/ls1012aqds.h | 6 ------
+ include/configs/ls1012ardb.h | 6 ------
+ 4 files changed, 5 insertions(+), 13 deletions(-)
+
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 2895e7a..7c0e64f 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -184,6 +184,11 @@
+ #define CONFIG_CMD_BOOTZ
+ #define CONFIG_CMDLINE_TAG
+
++/* Used by SCSI, MMC and USB */
++#define CONFIG_CMD_FAT
++#define CONFIG_DOS_PARTITION
++#define CONFIG_CMD_EXT2
++
+ #include <asm/fsl_secure_boot.h>
+
+ #endif /* __LS1012A_COMMON_H */
+diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
+index 5e619c1..432317d 100644
+--- a/include/configs/ls1012afrdm.h
++++ b/include/configs/ls1012afrdm.h
+@@ -38,7 +38,6 @@
+ #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+ #define CONFIG_CMD_USB
+ #define CONFIG_USB_STORAGE
+-#define CONFIG_CMD_EXT2
+
+ #define CONFIG_USB_DWC3
+ #define CONFIG_USB_DWC3_GADGET
+diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
+index cc8e0fc..c06cfbd 100644
+--- a/include/configs/ls1012aqds.h
++++ b/include/configs/ls1012aqds.h
+@@ -34,8 +34,6 @@
+ #define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
+ #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+ #define CONFIG_GENERIC_MMC
+-#define CONFIG_CMD_FAT
+-#define CONFIG_DOS_PARTITION
+ #endif
+ #endif /* CONFIG_EMU */
+
+@@ -45,9 +43,6 @@
+ #define CONFIG_SCSI_AHCI
+ #define CONFIG_SCSI_AHCI_PLAT
+ #define CONFIG_CMD_SCSI
+-#define CONFIG_CMD_FAT
+-#define CONFIG_CMD_EXT2
+-#define CONFIG_DOS_PARTITION
+ #define CONFIG_BOARD_LATE_INIT
+
+ #define CONFIG_SYS_SATA AHCI_BASE_ADDR
+@@ -204,7 +199,6 @@
+ #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
+ #define CONFIG_CMD_USB
+ #define CONFIG_USB_STORAGE
+-#define CONFIG_CMD_EXT2
+
+ #define CONFIG_USB_DWC3
+ #define CONFIG_USB_DWC3_GADGET
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index e94df74..f6b3f28 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -39,7 +39,6 @@
+ #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+ #define CONFIG_CMD_USB
+ #define CONFIG_USB_STORAGE
+-#define CONFIG_CMD_EXT2
+
+ #define CONFIG_USB_DWC3
+ #define CONFIG_USB_DWC3_GADGET
+@@ -67,8 +66,6 @@
+ #define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
+ #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+ #define CONFIG_GENERIC_MMC
+-#define CONFIG_CMD_FAT
+-#define CONFIG_DOS_PARTITION
+ #endif
+ #endif /* CONFIG_EMU */
+
+@@ -78,9 +75,6 @@
+ #define CONFIG_SCSI_AHCI
+ #define CONFIG_SCSI_AHCI_PLAT
+ #define CONFIG_CMD_SCSI
+-#define CONFIG_CMD_FAT
+-#define CONFIG_CMD_EXT2
+-#define CONFIG_DOS_PARTITION
+ #define CONFIG_BOARD_LATE_INIT
+
+ #define CONFIG_SYS_SATA AHCI_BASE_ADDR
+--
+1.7.9.5
+
--- /dev/null
+From 4733ade3cdc2b2fcc960d72b6ad9009a3ada38cf Mon Sep 17 00:00:00 2001
+From: Tang Yuantian <Yuantian.Tang@nxp.com>
+Date: Fri, 24 Jun 2016 10:59:46 +0800
+Subject: [PATCH 60/93] ls1012: sata: add sata support
+
+So add sata configuation for ls1012 soc.
+
+Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 9 +++++++++
+ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 7 +++++++
+ 2 files changed, 16 insertions(+)
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+index 0a170eb..ab902ce 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+@@ -328,10 +328,19 @@ int sata_init(void)
+ {
+ struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
+
++#if defined(CONFIG_LS1043A)
+ out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
+ out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
+ out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
++#elif defined(CONFIG_LS1012A)
++ out_le32(&ccsr_ahci->ppcfg, LS1012A_PORT_PHY1);
++ out_le32(&ccsr_ahci->pp2c, LS1012A_PORT_PHY2);
++ out_le32(&ccsr_ahci->pp3c, LS1012A_PORT_PHY3);
++ out_le32(&ccsr_ahci->pp4c, LS1012A_PORT_PHY4);
++ out_le32(&ccsr_ahci->pp5c, LS1012A_PORT_PHY5);
++ out_le32(&ccsr_ahci->ptc, LS1012A_PORT_TRANS);
++#endif
+
+ ahci_init((void __iomem *)CONFIG_SYS_SATA);
+ scsi_scan(0);
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+index 0822b49..8071114 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+@@ -60,6 +60,13 @@ struct cpu_type {
+ #define AHCI_PORT_PHY_3_CFG 0x0e081509
+ #define AHCI_PORT_TRANS_CFG 0x08000029
+
++#define LS1012A_PORT_PHY1 0xa003fffe
++#define LS1012A_PORT_PHY2 0x28184d1b
++#define LS1012A_PORT_PHY3 0x0e081906
++#define LS1012A_PORT_PHY4 0x064a0813
++#define LS1012A_PORT_PHY5 0x3ffc96a4
++#define LS1012A_PORT_TRANS 0x08000029
++
+ /* AHCI (sata) register map */
+ struct ccsr_ahci {
+ u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
+--
+1.7.9.5
+
--- /dev/null
+From e84c8c3f444aae4359cd4d60fabd3d2145d011b5 Mon Sep 17 00:00:00 2001
+From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Date: Fri, 24 Jun 2016 11:03:38 +0530
+Subject: [PATCH 61/93] ARMv8: freescale: Consolidate PPA flags under a single
+ flag
+
+[context adjustment]
+
+LS1012A places PPA binary on QSPI flash instead of NOR.
+So, depricating CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of
+CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code
+by addition of a new QSPI specific flag.
+
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 4 ++--
+ arch/arm/include/asm/fsl_secure_boot.h | 2 +-
+ include/configs/ls1043ardb.h | 4 ++--
+ 3 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
+index 116e164..8986260 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
+@@ -163,7 +163,7 @@ static int ppa_parse_firmware_fit_image(const void **raw_image_addr,
+ void *ppa_addr;
+ int ret;
+
+-#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
++#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
+ ppa_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
+ #else
+ #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
+@@ -197,7 +197,7 @@ int sec_firmware_validate(void)
+ {
+ void *ppa_addr;
+
+-#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
++#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
+ ppa_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
+ #else
+ #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
+diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
+index c973255..b2e9105 100644
+--- a/arch/arm/include/asm/fsl_secure_boot.h
++++ b/arch/arm/include/asm/fsl_secure_boot.h
+@@ -104,7 +104,7 @@
+ #endif
+
+ #ifdef CONFIG_FSL_LS_PPA
+-#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
++#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
+ #ifdef CONFIG_LS1043A
+ #define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x600c0000
+ #endif
+diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
+index af8b441..46818e8 100644
+--- a/include/configs/ls1043ardb.h
++++ b/include/configs/ls1043ardb.h
+@@ -14,8 +14,8 @@
+ #define CONFIG_ARMV8_PSCI
+ #define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
+
+-#define CONFIG_SYS_LS_PPA_FW_IN_NOR
+-#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
++#define CONFIG_SYS_LS_PPA_FW_IN_XIP
++#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
+ #define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000
+ #endif
+ #endif
+--
+1.7.9.5
+
--- /dev/null
+From f1b3374b2f99b30795423a4ae514e634bb84a1d9 Mon Sep 17 00:00:00 2001
+From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Date: Fri, 24 Jun 2016 10:32:59 +0530
+Subject: [PATCH 62/93] ARMv8: freescale: Fix the address map of SCFG
+
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+---
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index a7bc2a4..696d0a3 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -450,7 +450,7 @@ struct ccsr_scfg {
+ u32 pfebsbcr;
+ u8 res_460[0x484-0x460];
+ u32 mdioselcr;
+- u8 res_468[0x600-0x468];
++ u8 res_488[0x600-0x488];
+ u32 scratchrw[4];
+ u8 res_610[0x680-0x610];
+ u32 corebcr;
+--
+1.7.9.5
+
--- /dev/null
+From 1882af9f2c7533c6cd2dea5811b4e69f9a151f29 Mon Sep 17 00:00:00 2001
+From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Date: Fri, 24 Jun 2016 10:45:39 +0530
+Subject: [PATCH 63/93] board: freescale: ls1012a: Enable secure DDR on
+ LS1012A platforms
+
+PPA binary needs to be relocated on secure DDR, hence marking out
+a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag
+is set
+
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+---
+ arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++
+ board/freescale/ls1012afrdm/ls1012afrdm.c | 28 +++++++++++++++++++++
+ board/freescale/ls1012aqds/ls1012aqds.c | 28 +++++++++++++++++++++
+ board/freescale/ls1012ardb/ls1012ardb.c | 28 +++++++++++++++++++++
+ include/configs/ls1012a_common.h | 1 +
+ 5 files changed, 88 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
+index 679be6c..efaa79a 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
+@@ -222,6 +222,9 @@
+ #define GICD_BASE 0x01401000
+ #define GICC_BASE 0x01402000
+
++#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
++#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
++
+ #define CONFIG_SYS_FSL_CCSR_GUR_BE
+ #define CONFIG_SYS_FSL_CCSR_SCFG_BE
+ #define CONFIG_SYS_FSL_ESDHC_BE
+diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
+index 6856250..c691a76 100644
+--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
++++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
+@@ -176,3 +176,31 @@ int ft_board_setup(void *blob, bd_t *bd)
+
+ return 0;
+ }
++
++void dram_init_banksize(void)
++{
++ /*
++ * gd->secure_ram tracks the location of secure memory.
++ * It was set as if the memory starts from 0.
++ * The address needs to add the offset of its bank.
++ */
++ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
++ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
++ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
++ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
++ gd->bd->bi_dram[1].size = gd->ram_size -
++ CONFIG_SYS_DDR_BLOCK1_SIZE;
++#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
++ gd->secure_ram = gd->bd->bi_dram[1].start +
++ gd->secure_ram -
++ CONFIG_SYS_DDR_BLOCK1_SIZE;
++ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
++#endif
++ } else {
++ gd->bd->bi_dram[0].size = gd->ram_size;
++#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
++ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
++ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
++#endif
++ }
++}
+diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
+index 56004ea..516f0c3 100644
+--- a/board/freescale/ls1012aqds/ls1012aqds.c
++++ b/board/freescale/ls1012aqds/ls1012aqds.c
+@@ -240,3 +240,31 @@ int ft_board_setup(void *blob, bd_t *bd)
+ return 0;
+ }
+ #endif
++
++void dram_init_banksize(void)
++{
++ /*
++ * gd->secure_ram tracks the location of secure memory.
++ * It was set as if the memory starts from 0.
++ * The address needs to add the offset of its bank.
++ */
++ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
++ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
++ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
++ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
++ gd->bd->bi_dram[1].size = gd->ram_size -
++ CONFIG_SYS_DDR_BLOCK1_SIZE;
++#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
++ gd->secure_ram = gd->bd->bi_dram[1].start +
++ gd->secure_ram -
++ CONFIG_SYS_DDR_BLOCK1_SIZE;
++ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
++#endif
++ } else {
++ gd->bd->bi_dram[0].size = gd->ram_size;
++#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
++ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
++ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
++#endif
++ }
++}
+diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
+index ad4d8ee..8340f14 100644
+--- a/board/freescale/ls1012ardb/ls1012ardb.c
++++ b/board/freescale/ls1012ardb/ls1012ardb.c
+@@ -235,3 +235,31 @@ int ft_board_setup(void *blob, bd_t *bd)
+
+ return 0;
+ }
++
++void dram_init_banksize(void)
++{
++ /*
++ * gd->secure_ram tracks the location of secure memory.
++ * It was set as if the memory starts from 0.
++ * The address needs to add the offset of its bank.
++ */
++ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
++ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
++ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
++ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
++ gd->bd->bi_dram[1].size = gd->ram_size -
++ CONFIG_SYS_DDR_BLOCK1_SIZE;
++#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
++ gd->secure_ram = gd->bd->bi_dram[1].start +
++ gd->secure_ram -
++ CONFIG_SYS_DDR_BLOCK1_SIZE;
++ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
++#endif
++ } else {
++ gd->bd->bi_dram[0].size = gd->ram_size;
++#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
++ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
++ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
++#endif
++ }
++}
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 7c0e64f..4c7c697 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -36,6 +36,7 @@
+ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+ #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
++#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
+
+ /* Generic Timer Definitions */
+ #define COUNTER_FREQUENCY 25000000 /* 12MHz */
+--
+1.7.9.5
+
--- /dev/null
+From 31f17073ffb1501574ad4cb8dffd507dee40e69a Mon Sep 17 00:00:00 2001
+From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Date: Thu, 16 Jun 2016 13:49:17 +0530
+Subject: [PATCH 64/93] board: freescale: ls1012a: Intergrate and enable PPA
+ on LS1012ARDB
+
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+---
+ board/freescale/ls1012ardb/ls1012ardb.c | 10 ++++++++++
+ include/configs/ls1012ardb.h | 9 +++++++++
+ 2 files changed, 19 insertions(+)
+
+diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
+index 8340f14..7f7503c 100644
+--- a/board/freescale/ls1012ardb/ls1012ardb.c
++++ b/board/freescale/ls1012ardb/ls1012ardb.c
+@@ -198,6 +198,9 @@ int mmc_check_sdhc2_card(void)
+ int board_init(void)
+ {
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
++#ifdef CONFIG_FSL_LS_PPA
++ u64 ppa_entry;
++#endif
+ /*
+ * Set CCI-400 control override register to enable barrier
+ * transaction
+@@ -216,6 +219,13 @@ int board_init(void)
+ sec_init();
+ #endif
+
++#ifdef CONFIG_FSL_LS_PPA
++ ppa_init_pre(&ppa_entry);
++
++ if (ppa_entry)
++ ppa_init_entry((void *)ppa_entry);
++#endif
++
+ return 0;
+ }
+
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index f6b3f28..fdaea3e 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -9,6 +9,15 @@
+
+ #include "ls1012a_common.h"
+
++#define CONFIG_FSL_LS_PPA
++#if defined(CONFIG_FSL_LS_PPA)
++#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
++
++#define CONFIG_SYS_LS_PPA_FW_IN_XIP
++#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
++#define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000
++#endif
++#endif
+
+ #define CONFIG_DIMM_SLOTS_PER_CTLR 1
+ #define CONFIG_CHIP_SELECTS_PER_CTRL 1
+--
+1.7.9.5
+
--- /dev/null
+From 39f95bb22c03b18ac6c4ef1b4485414dd4a303cb Mon Sep 17 00:00:00 2001
+From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Date: Fri, 24 Jun 2016 14:37:42 +0530
+Subject: [PATCH 65/93] docs: fsl-ppa: Add documentation for PPA trusted FW
+
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+---
+ doc/README.fsl-ppa | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+ create mode 100644 doc/README.fsl-ppa
+
+diff --git a/doc/README.fsl-ppa b/doc/README.fsl-ppa
+new file mode 100644
+index 0000000..76cd01f
+--- /dev/null
++++ b/doc/README.fsl-ppa
+@@ -0,0 +1,26 @@
++PPA FW for U-boot
++
++Summary
++=======
++PPA is a trusted firmware for ARMv8 , that handles smc calls from lower
++exception levels, like power state co-ordination interface call or
++smc calls to trusted OS from the Linux kernel.
++
++Notes
++=====
++
++1. Currenly, u-boot run at the highest exception level processor
++ supported, which is EL3 in case of ARMv8, if PPA FW is incorporated
++ U-boot copies it to secure location in DDR.
++2. During init U-boot passes control to PPA FW and before returning
++ the core jumps to EL2.
++
++Using PPA
++=========
++1. Ensure CONFIG_FSL_LS_PPA is set for your platform
++2. Program PPA binary on address CONFIG_SYS_LS_PPA_FW_ADDR on flash
++
++Contributors
++============
++ Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
++ Abhimanyu Saini <abhimanyu.saini@nxp.com>
+--
+1.7.9.5
+
--- /dev/null
+From 35efc0f34b56ca9d5fb5d080d5de0833ded7e3b8 Mon Sep 17 00:00:00 2001
+From: Anji J <anji.jagarlmudi@freescale.com>
+Date: Tue, 21 Jun 2016 13:25:12 +0530
+Subject: [PATCH 66/93] armv8:pfe Enable UDP checksum for proper tftp
+ operation
+
+1. Add CONFIG_UDP_CHECKSUM flag to perform UDP checksum in S/W
+ instead of hardware
+2. Rx descriptor model changed back to original
+ removed strobe mode
+3. Send more than one dummy packets to bring HIF BD to idle state
+
+Signed-off-by: Anji J <anji.jagarlmudi@freescale.com>
+---
+ common/cmd_pfe_commands.c | 12 +++++++-----
+ drivers/net/pfe_eth/pfe_driver.c | 19 +++----------------
+ include/configs/ls1012a_common.h | 1 +
+ 3 files changed, 11 insertions(+), 21 deletions(-)
+
+diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
+index 92917e0..3575ad4 100644
+--- a/common/cmd_pfe_commands.c
++++ b/common/cmd_pfe_commands.c
+@@ -929,7 +929,7 @@ static void send_dummy_pkt_to_hif(void)
+
+ static void pfe_command_stop(int argc, char * const argv[])
+ {
+- int id;
++ int id, hif_stop_loop = 10;
+ u32 rx_status;
+ printf("Stopping PFE... \n");
+
+@@ -937,10 +937,12 @@ static void pfe_command_stop(int argc, char * const argv[])
+ hif_rx_desc_disable();
+
+ /*If HIF Rx BDP is busy send a dummy packet */
+- rx_status = readl(HIF_RX_STATUS);
+- if(rx_status & BDP_CSR_RX_DMA_ACTV)
+- send_dummy_pkt_to_hif();
+- udelay(10);
++ do {
++ rx_status = readl(HIF_RX_STATUS);
++ if (rx_status & BDP_CSR_RX_DMA_ACTV)
++ send_dummy_pkt_to_hif();
++ udelay(10);
++ } while (hif_stop_loop--);
+
+ if(readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)
+ printf("Unable to stop HIF\n");
+diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
+index e252fcf..6774fb4 100644
+--- a/drivers/net/pfe_eth/pfe_driver.c
++++ b/drivers/net/pfe_eth/pfe_driver.c
+@@ -37,13 +37,8 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
+
+ bd = rx_desc->rxBase + rx_desc->rxToRead;
+
+- if (bd->ctrl & BD_CTRL_DESC_EN) {
+- if(!(readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)){
+- /*If BDP is not active give write strobe */
+- writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
+- }
++ if (bd->ctrl & BD_CTRL_DESC_EN)
+ return len; //No pending Rx packet
+- }
+
+ /* this len include hif_header(8bytes) */
+ len = bd->ctrl & 0xFFFF;
+@@ -72,15 +67,10 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
+ *phy_port = hif_header->port_no;
+ len -= sizeof(struct hif_header_s);
+
+-#if defined(PFE_LS1012A_RESET_WA)
+- /* reset bd control field */
+- ctrl = (MAX_FRAME_SIZE | BD_CTRL_LAST_BD | BD_CTRL_LIFM | BD_CTRL_DESC_EN | BD_CTRL_DIR);
+-#else
+ /* reset bd control field */
+ ctrl = (MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN | BD_CTRL_DIR);
+- /* If we use BD_CTRL_LAST_BD, rxToRead never changes */
+ rx_desc->rxToRead = (rx_desc->rxToRead + 1) & (rx_desc->rxRingSize - 1);
+-#endif
++
+ bd->ctrl = ctrl;
+ bd->status = 0;
+
+@@ -363,11 +353,8 @@ static int hif_rx_desc_init(struct pfe *pfe)
+
+ memset(bd_va, 0, sizeof(struct bufDesc) * rx_desc->rxRingSize);
+
+-#if defined(PFE_LS1012A_RESET_WA)
+- ctrl = (MAX_FRAME_SIZE | BD_CTRL_LAST_BD | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
+-#else
+ ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
+-#endif
++
+ for (i=0; i < rx_desc->rxRingSize; i++) {
+ bd_va->next = (unsigned long)(bd_pa + 1);
+ bd_va->ctrl = ctrl;
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 4c7c697..47b8ec3 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -116,6 +116,7 @@
+ #ifdef CONFIG_FSL_PPFE
+ #define CONFIG_CMD_PFE_COMMANDS
+ #define CONFIG_UTIL_PE_DISABLED
++#define CONFIG_UDP_CHECKSUM
+
+ #endif
+
+--
+1.7.9.5
+
--- /dev/null
+From 8b6c309e5e55670f429730449d9921987636c8ec Mon Sep 17 00:00:00 2001
+From: Calvin Johnson <calvin.johnson@freescale.com>
+Date: Wed, 8 Jun 2016 17:04:58 +0530
+Subject: [PATCH 67/93] armv8: ls1012a: DDR optmizations
+
+Enable DDR row-bank-column decoding. DDR address will
+be decoded as row-bank-column instead of bank-row-column.
+This will improve performance of serial data transfers.
+
+Refresh cycle value must be selected based on the frequency
+of DDR. tREFI = 7.8 us as per JEDEC. The value for MDREF[REF_CNT]
+should be based on round up (tREFI/tCK) formula. For 500MHz, mdref
+value should be 0x0f3c8000.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+---
+ board/freescale/ls1012afrdm/ls1012afrdm.c | 4 ++--
+ board/freescale/ls1012aqds/ls1012aqds.c | 4 ++--
+ board/freescale/ls1012ardb/ls1012ardb.c | 4 ++--
+ 3 files changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
+index c691a76..4b7902a 100644
+--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
++++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
+@@ -59,7 +59,7 @@ void mmdc_init(void)
+ out_be32(&mmdc->mdcfg2, 0x01ff00db);
+
+ /* other parms */
+- out_be32(&mmdc->mdmisc, 0x00000680);
++ out_be32(&mmdc->mdmisc, 0x00001680);
+ out_be32(&mmdc->mpmur0, 0x00000800);
+ out_be32(&mmdc->mdrwd, 0x00002000);
+ out_be32(&mmdc->mpodtctrl, 0x0000022a);
+@@ -118,7 +118,7 @@ void mmdc_init(void)
+ out_be32(&mmdc->mapsr, 0x00001067);
+
+ /* refresh scheme */
+- set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
++ set_wait_for_bits_clear(&mmdc->mdref, 0x0f3c8000, 0x00000001);
+
+ /* disable CON_REQ */
+ out_be32(&mmdc->mdscr, 0x0);
+diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
+index 516f0c3..4ae8def 100644
+--- a/board/freescale/ls1012aqds/ls1012aqds.c
++++ b/board/freescale/ls1012aqds/ls1012aqds.c
+@@ -82,7 +82,7 @@ void mmdc_init(void)
+ out_be32(&mmdc->mdcfg2, 0x01ff00db);
+
+ /* other parms */
+- out_be32(&mmdc->mdmisc, 0x00000680);
++ out_be32(&mmdc->mdmisc, 0x00001680);
+ out_be32(&mmdc->mpmur0, 0x00000800);
+ out_be32(&mmdc->mdrwd, 0x00002000);
+ out_be32(&mmdc->mpodtctrl, 0x0000022a);
+@@ -142,7 +142,7 @@ void mmdc_init(void)
+ out_be32(&mmdc->mapsr, 0x00001067);
+
+ /* refresh scheme */
+- set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
++ set_wait_for_bits_clear(&mmdc->mdref, 0x0f3c8000, 0x00000001);
+
+ /* disable CON_REQ */
+ out_be32(&mmdc->mdscr, 0x0);
+diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
+index 7f7503c..06e1f6b 100644
+--- a/board/freescale/ls1012ardb/ls1012ardb.c
++++ b/board/freescale/ls1012ardb/ls1012ardb.c
+@@ -88,7 +88,7 @@ void mmdc_init(void)
+ out_be32(&mmdc->mdcfg2, 0x01ff00db);
+
+ /* other parms */
+- out_be32(&mmdc->mdmisc, 0x00000680);
++ out_be32(&mmdc->mdmisc, 0x00001680);
+ out_be32(&mmdc->mpmur0, 0x00000800);
+ out_be32(&mmdc->mdrwd, 0x00002000);
+ out_be32(&mmdc->mpodtctrl, 0x0000022a);
+@@ -148,7 +148,7 @@ void mmdc_init(void)
+ out_be32(&mmdc->mapsr, 0x00001067);
+
+ /* refresh scheme */
+- set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
++ set_wait_for_bits_clear(&mmdc->mdref, 0x0f3c8000, 0x00000001);
+
+ /* disable CON_REQ */
+ out_be32(&mmdc->mdscr, 0x0);
+--
+1.7.9.5
+
--- /dev/null
+From 7715b8d4b833dfe3d997f21c8055d33975ed84c8 Mon Sep 17 00:00:00 2001
+From: Calvin Johnson <calvin.johnson@nxp.com>
+Date: Wed, 29 Jun 2016 16:03:33 +0530
+Subject: [PATCH 68/93] driver: pfe_eth: use #ifdef instead of #if
+
+There is no need of checking the value of DEBUG,
+so use #ifdef preprocessor directive instead of #if.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+---
+ drivers/net/pfe_eth/pfe_driver.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
+index 6774fb4..a3a3e49 100644
+--- a/drivers/net/pfe_eth/pfe_driver.c
++++ b/drivers/net/pfe_eth/pfe_driver.c
+@@ -50,7 +50,7 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
+ dprint("Pkt recv'd: Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
+ hif_header, len, hif_header->port_no, bd->status);
+
+-#if DEBUG
++#ifdef DEBUG
+ {
+ int i;
+ unsigned char *p = (unsigned char *)hif_header;
+--
+1.7.9.5
+
--- /dev/null
+From 4f217aaf4bca500f13b4c560a6bbb3708c8e5dc2 Mon Sep 17 00:00:00 2001
+From: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
+Date: Fri, 1 Jul 2016 04:37:53 +0530
+Subject: [PATCH 69/93] armv8:pfe:frdm Reset external PHYs before driver
+ starts
+
+- Disable CONFIG_RESET_PHY_R, it is resetting PHYs after driver started
+- Call reset_phy() before driver initialization
+
+Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
+Signed-off-by: Anji J <anji.jagarlmudi@freescale.com>
+---
+ board/freescale/ls1012afrdm/eth.c | 1 +
+ include/configs/ls1012afrdm.h | 1 -
+ 2 files changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c
+index 90ed66b..be17310 100644
+--- a/board/freescale/ls1012afrdm/eth.c
++++ b/board/freescale/ls1012afrdm/eth.c
+@@ -46,6 +46,7 @@ int board_eth_init(bd_t *bis)
+ struct mdio_info mac1_mdio_info;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
++ reset_phy();
+
+ /*TODO Following config should be done for all boards, where is the right place to put this */
+ out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
+diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
+index 432317d..3de0cea 100644
+--- a/include/configs/ls1012afrdm.h
++++ b/include/configs/ls1012afrdm.h
+@@ -23,7 +23,6 @@
+ #define EMAC2_PHY_ADDR 0x1
+ #define CONFIG_PHYLIB
+ #define CONFIG_PHY_REALTEK
+-#define CONFIG_RESET_PHY_R
+ #endif
+ /*
+ * USB
+--
+1.7.9.5
+
--- /dev/null
+From 3df085e06da99123410e2394c8c6764ab0e98f3a Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Mon, 11 Jul 2016 16:18:28 +0530
+Subject: [PATCH 70/93] board: ls1012afrdm: overwrite
+ CONFIG_EXTRA_ENV_SETTINGS
+
+Kernel load address for ls1012afrdm is 0x96000000 because it has
+512MB of DDR.
+
+So overwrite CONFIG_EXTRA_ENV_SETTINGS with updated kernel_load
+address.
+
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ include/configs/ls1012afrdm.h | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
+index 3de0cea..622c774 100644
+--- a/include/configs/ls1012afrdm.h
++++ b/include/configs/ls1012afrdm.h
+@@ -59,4 +59,20 @@
+ #define CONFIG_SYS_MEMTEST_START 0x80000000
+ #define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
++#undef CONFIG_EXTRA_ENV_SETTINGS
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ "initrd_high=0xffffffff\0" \
++ "verify=no\0" \
++ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
++ "loadaddr=0x80100000\0" \
++ "kernel_addr=0x100000\0" \
++ "ramdisk_addr=0x800000\0" \
++ "ramdisk_size=0x2000000\0" \
++ "fdt_high=0xffffffffffffffff\0" \
++ "initrd_high=0xffffffffffffffff\0" \
++ "kernel_start=0xa00000\0" \
++ "kernel_load=0x96000000\0" \
++ "kernel_size=0x2800000\0" \
++ "console=ttyAMA0,38400n8\0"
++
+ #endif /* __LS1012ARDB_H__ */
+--
+1.7.9.5
+
--- /dev/null
+From e2a5bba97cd6e42b2b631bd17012aa26ffdb5f67 Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Tue, 12 Jul 2016 10:30:08 +0800
+Subject: [PATCH 71/93] driver: fsl_qspi: disable AHB buffer prefetch
+
+Errata: A-009282: QuadSPI data pre-fetch can result in incorrect data
+When we enable the CONFIG_SYS_FSL_QSPI_AHB, we need this errata workaround.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/spi/fsl_qspi.c | 12 +++++++++++-
+ include/configs/ls1012a_common.h | 1 +
+ 2 files changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
+index 09759fa..f1c87f5 100644
+--- a/drivers/spi/fsl_qspi.c
++++ b/drivers/spi/fsl_qspi.c
+@@ -441,13 +441,23 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
+ static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
+ {
+ struct fsl_qspi_regs *regs = priv->regs;
++ int rx_size = 0x80;
+
+ /* AHB configuration for access buffer 0/1/2 .*/
+ qspi_write32(priv->flags, ®s->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
+ qspi_write32(priv->flags, ®s->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
+ qspi_write32(priv->flags, ®s->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
++
++#ifdef CONFIG_SYS_FSL_ERRATUM_A009282
++ /*A-009282: QuadSPI data pre-fetch can result in incorrect data
++ *Workaround: Keep the read data size to 64 bits (8 Bytes), which
++ *disables the prefetch on the AHB buffer,and prevents this issue
++ *from occurring.
++ */
++ rx_size = 0x1;
++#endif
+ qspi_write32(priv->flags, ®s->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
+- (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
++ (rx_size << QSPI_BUF3CR_ADATSZ_SHIFT));
+
+ /* We only use the buffer3 */
+ qspi_write32(priv->flags, ®s->buf0ind, 0);
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 47b8ec3..f0ae355 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -68,6 +68,7 @@
+ #define FSL_QSPI_FLASH_SIZE (1 << 26)
+ #define FSL_QSPI_FLASH_NUM 2
+ #define CONFIG_SYS_FSL_QSPI_AHB
++#define CONFIG_SYS_FSL_ERRATUM_A009282
+
+ /*
+ * Environment
+--
+1.7.9.5
+
--- /dev/null
+From 31d5393ea4defd3872dc07264912f60ad627782b Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Tue, 12 Jul 2016 11:29:52 +0800
+Subject: [PATCH 72/93] driver: spi: fsl-qspi: remove compile Warnings
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Warnins log:
+drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’:
+drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
+ memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/spi/fsl_qspi.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
+index f1c87f5..f521fe2 100644
+--- a/drivers/spi/fsl_qspi.c
++++ b/drivers/spi/fsl_qspi.c
+@@ -389,6 +389,7 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
+ {
+ struct fsl_qspi_regs *regs = priv->regs;
+ u32 mcr_reg;
++ void *rx_addr = NULL;
+
+ mcr_reg = qspi_read32(priv->flags, ®s->mcr);
+
+@@ -396,8 +397,9 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
+ QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
+ QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+
++ rx_addr += priv->cur_amba_base + priv->sf_addr;
+ /* Read out the data directly from the AHB buffer. */
+- memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
++ memcpy(rxbuf, rx_addr, len);
+
+ qspi_write32(priv->flags, ®s->mcr, mcr_reg);
+ }
+--
+1.7.9.5
+
--- /dev/null
+From 3c41e8827ddcff313a518de19d630a42bbdca3b1 Mon Sep 17 00:00:00 2001
+From: Anji J <anji.jagarlmudi@freescale.com>
+Date: Fri, 8 Jul 2016 20:05:37 +0530
+Subject: [PATCH 73/93] armv8:pfe Change MDIO HOLDTIME value to 5
+
+Per design/validation team suggestion use HOLDTIME value as 5.
+
+Signed-off-by: Anji J <anji.jagarlmudi@freescale.com>
+---
+ drivers/net/pfe_eth/pfe_eth.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
+index 528ede9..9a90b38 100644
+--- a/drivers/net/pfe_eth/pfe_eth.c
++++ b/drivers/net/pfe_eth/pfe_eth.c
+@@ -329,7 +329,7 @@ struct mii_dev *ls1012a_mdio_init(struct mdio_info *mdio_info)
+
+ /*configure mdio speed */
+ mdio_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT);
+- mdio_speed |= EMAC_HOLDTIME(0x4);
++ mdio_speed |= EMAC_HOLDTIME(0x5);
+ writel(mdio_speed, mdio_info->reg_base + EMAC_MII_CTRL_REG);
+
+ ret = mdio_register(bus);
+--
+1.7.9.5
+
--- /dev/null
+From f95f8ebd8d55ccc27e1615b251450915a1c14315 Mon Sep 17 00:00:00 2001
+From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Date: Tue, 12 Jul 2016 14:17:17 +0530
+Subject: [PATCH 74/93] board: freescale: ls1012a: Intergrate and enable PPA
+ on LS1012AFRDM
+
+Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+---
+ board/freescale/ls1012afrdm/ls1012afrdm.c | 9 +++++++++
+ include/configs/ls1012afrdm.h | 12 ++++++++++++
+ 2 files changed, 21 insertions(+)
+
+diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
+index 4b7902a..04f8f9a 100644
+--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
++++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
+@@ -143,6 +143,9 @@ int board_early_init_f(void)
+ int board_init(void)
+ {
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
++#ifdef CONFIG_FSL_LS_PPA
++ u64 ppa_entry;
++#endif
+ /*
+ * Set CCI-400 control override register to enable barrier
+ * transaction
+@@ -157,6 +160,12 @@ int board_init(void)
+ enable_layerscape_ns_access();
+ #endif
+
++#ifdef CONFIG_FSL_LS_PPA
++ ppa_init_pre(&ppa_entry);
++
++ if (ppa_entry)
++ ppa_init_entry((void *)ppa_entry);
++#endif
+ return 0;
+ }
+
+diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
+index 622c774..26e3640 100644
+--- a/include/configs/ls1012afrdm.h
++++ b/include/configs/ls1012afrdm.h
+@@ -9,6 +9,18 @@
+
+ #include "ls1012a_common.h"
+
++#ifndef CONFIG_SECURE_BOOT
++#define CONFIG_FSL_LS_PPA
++#if defined(CONFIG_FSL_LS_PPA)
++#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
++
++#define CONFIG_SYS_LS_PPA_FW_IN_XIP
++#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
++#define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000
++#endif
++#endif
++#endif
++
+ #define CONFIG_DIMM_SLOTS_PER_CTLR 1
+ #define CONFIG_CHIP_SELECTS_PER_CTRL 1
+ #define CONFIG_NR_DRAM_BANKS 2
+--
+1.7.9.5
+
--- /dev/null
+From d2effd68c77b4965d74ac2a6154d668e24a6dd9f Mon Sep 17 00:00:00 2001
+From: Chenhui Zhao <chenhui.zhao@nxp.com>
+Date: Fri, 8 Jul 2016 16:01:31 +0800
+Subject: [PATCH 75/93] arm: ls1012ardb: add CONFIG_ARMV8_PSCI
+
+[context adjustment]
+
+Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ include/configs/ls1012ardb.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index fdaea3e..e97c1f9 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -11,6 +11,7 @@
+
+ #define CONFIG_FSL_LS_PPA
+ #if defined(CONFIG_FSL_LS_PPA)
++#define CONFIG_ARMV8_PSCI
+ #define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
+
+ #define CONFIG_SYS_LS_PPA_FW_IN_XIP
+--
+1.7.9.5
+
--- /dev/null
+From ed6728fa22b4f09f6083d4c8b135f4b89487fee6 Mon Sep 17 00:00:00 2001
+From: Chenhui Zhao <chenhui.zhao@nxp.com>
+Date: Wed, 13 Jul 2016 13:05:19 +0800
+Subject: [PATCH 76/93] arm: ls1012afrdm: add CONFIG_ARMV8_PSCI
+
+Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
+---
+ include/configs/ls1012afrdm.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
+index 26e3640..0e35fe9 100644
+--- a/include/configs/ls1012afrdm.h
++++ b/include/configs/ls1012afrdm.h
+@@ -12,6 +12,7 @@
+ #ifndef CONFIG_SECURE_BOOT
+ #define CONFIG_FSL_LS_PPA
+ #if defined(CONFIG_FSL_LS_PPA)
++#define CONFIG_ARMV8_PSCI
+ #define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
+
+ #define CONFIG_SYS_LS_PPA_FW_IN_XIP
+--
+1.7.9.5
+
--- /dev/null
+From 2203e9045d8d113e1ecceddcbebcf78c66af557f Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Wed, 13 Jul 2016 15:49:12 +0530
+Subject: [PATCH 77/93] board: ls1012aqds: Avoid reset masking
+
+FPGA regiser RST_MASK1 control reset masking for I2C, USB,
+Mem and EPHY1.
+
+This register was being masked during initial debugging of
+RGMII. It is not required
+
+So avoid masking of these device to send reset signals during
+soft-reset.
+
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ board/freescale/ls1012aqds/eth.c | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
+index 6fbbdbe..04d621c 100644
+--- a/board/freescale/ls1012aqds/eth.c
++++ b/board/freescale/ls1012aqds/eth.c
+@@ -156,12 +156,6 @@ int board_eth_init(bd_t *bis)
+ data8 |= 0x2;
+ QIXIS_WRITE(rst_frc[0], data8);
+ data8 = QIXIS_READ(rst_frc[0]);
+-
+- data8 = QIXIS_READ(res8[6]);
+- data8 |= 0xff;
+- QIXIS_WRITE(res8[6], data8);
+- data8 = QIXIS_READ(res8[6]);
+-
+ #endif
+
+ mac1_mdio_info.reg_base = (void *)0x04200000; /*EMAC1_BASE_ADDR*/
+--
+1.7.9.5
+
--- /dev/null
+From 50450fdcc39c3863351d52c290e77b664df33ed6 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Wed, 13 Jul 2016 15:49:22 +0530
+Subject: [PATCH 78/93] board: ls1012aqds: Update LBMAP_MASK and RST_CTL_RESET
+
+~QIXIS_LBMAP_MASK is being used in code. So define inverse value
+LBMAP_MASK.
+
+Aslo, update QIXIS_RST_CTL_RESET value to keep RST_CTL[REQ_MOD]
+as 0b11 i.e. PORESET.
+
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ include/configs/ls1012aqds.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
+index c06cfbd..418bd54 100644
+--- a/include/configs/ls1012aqds.h
++++ b/include/configs/ls1012aqds.h
+@@ -89,11 +89,11 @@
+ #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+ #define QIXIS_LBMAP_BRDCFG_REG 0x04
+ #define QIXIS_LBMAP_SWITCH 6
+-#define QIXIS_LBMAP_MASK 0xf7
++#define QIXIS_LBMAP_MASK 0x08
+ #define QIXIS_LBMAP_SHIFT 0
+ #define QIXIS_LBMAP_DFLTBANK 0x00
+ #define QIXIS_LBMAP_ALTBANK 0x08
+-#define QIXIS_RST_CTL_RESET 0x41
++#define QIXIS_RST_CTL_RESET 0x31
+ #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+ #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+--
+1.7.9.5
+
--- /dev/null
+From 908e56f27baaad552e82f4e670108be9b4db67b6 Mon Sep 17 00:00:00 2001
+From: Anji J <anji.jagarlmudi@freescale.com>
+Date: Thu, 7 Jul 2016 12:53:15 +0530
+Subject: [PATCH 79/93] armv8:pfe Update class firmware
+
+This class firmware does the UDP/TCP checksum validation.
+Remove CONFIG_UDP_CHECKSUM
+
+Signed-off-by: Anji J <anji.jagarlmudi@freescale.com>
+---
+ drivers/net/pfe_eth/class_sbl_elf.fw | 2 +-
+ include/configs/ls1012a_common.h | 1 -
+ 2 files changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/net/pfe_eth/class_sbl_elf.fw b/drivers/net/pfe_eth/class_sbl_elf.fw
+index 3745d9a..10418ed 100644
+--- a/drivers/net/pfe_eth/class_sbl_elf.fw
++++ b/drivers/net/pfe_eth/class_sbl_elf.fw
+@@ -1 +1 @@
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6,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+\ No newline at end of file
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index f0ae355..0d64889 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -117,7 +117,6 @@
+ #ifdef CONFIG_FSL_PPFE
+ #define CONFIG_CMD_PFE_COMMANDS
+ #define CONFIG_UTIL_PE_DISABLED
+-#define CONFIG_UDP_CHECKSUM
+
+ #endif
+
+--
+1.7.9.5
+
--- /dev/null
+From b43d6d42d734e78bd9b805a62f2a64933c144a41 Mon Sep 17 00:00:00 2001
+From: Sumit Garg <sumit.garg@nxp.com>
+Date: Thu, 14 Jul 2016 07:20:02 -0400
+Subject: [PATCH 80/93] ls1012ardb: PPA: Enable PPA validation in case of
+ secure boot
+
+As part of Secure Boot Chain of trust, enable validation of PPA image
+before the image is started.
+
+Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
+---
+ arch/arm/include/asm/fsl_secure_boot.h | 2 ++
+ include/configs/ls1012a_common.h | 2 --
+ include/configs/ls1012ardb.h | 2 ++
+ 3 files changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
+index b2e9105..0580fcd 100644
+--- a/arch/arm/include/asm/fsl_secure_boot.h
++++ b/arch/arm/include/asm/fsl_secure_boot.h
+@@ -107,6 +107,8 @@
+ #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
+ #ifdef CONFIG_LS1043A
+ #define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x600c0000
++#else
++#define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x40480000
+ #endif
+ #else
+ #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 0d64889..7e935ad 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -191,6 +191,4 @@
+ #define CONFIG_DOS_PARTITION
+ #define CONFIG_CMD_EXT2
+
+-#include <asm/fsl_secure_boot.h>
+-
+ #endif /* __LS1012A_COMMON_H */
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index e97c1f9..d78edd2 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -149,4 +149,6 @@
+
+ #define CONFIG_FSL_CAAM /* Enable CAAM */
+
++#include <asm/fsl_secure_boot.h>
++
+ #endif /* __LS1012ARDB_H__ */
+--
+1.7.9.5
+
--- /dev/null
+From 5d4a46fe8847d26112764c5768ff00f839fb3810 Mon Sep 17 00:00:00 2001
+From: Sumit Garg <sumit.garg@nxp.com>
+Date: Tue, 12 Jul 2016 14:05:34 -0400
+Subject: [PATCH 81/93] crypto/fsl: Update blob cmd to accept 64bit addresses
+
+Update blob cmd to accept 64bit source, key modifier and destination
+addresses. Also correct output result print format for fsl specific
+implementation of blob cmd.
+
+Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
+---
+ common/cmd_blob.c | 2 +-
+ drivers/crypto/fsl/fsl_blob.c | 13 ++++++++++---
+ 2 files changed, 11 insertions(+), 4 deletions(-)
+
+diff --git a/common/cmd_blob.c b/common/cmd_blob.c
+index ac8b268..bdd4cfd 100644
+--- a/common/cmd_blob.c
++++ b/common/cmd_blob.c
+@@ -54,7 +54,7 @@ __weak int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
+ */
+ static int do_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ {
+- uint32_t key_addr, src_addr, dst_addr, len;
++ ulong key_addr, src_addr, dst_addr, len;
+ uint8_t *km_ptr, *src_ptr, *dst_ptr;
+ int enc, ret = 0;
+
+diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c
+index 8b25921..d24b8fc 100644
+--- a/drivers/crypto/fsl/fsl_blob.c
++++ b/drivers/crypto/fsl/fsl_blob.c
+@@ -18,7 +18,7 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
+ int ret, i = 0;
+ u32 *desc;
+
+- printf("\nDecapsulating data to form blob\n");
++ printf("\nDecapsulating blob to get data\n");
+ desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
+ if (!desc) {
+ debug("Not enough memory for descriptor allocation\n");
+@@ -27,12 +27,15 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
+
+ inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len);
+
++ debug("Descriptor dump:\n");
+ for (i = 0; i < 14; i++)
+- printf("%x\n", *(desc + i));
++ debug("Word[%d]: %08x\n", i, *(desc + i));
+ ret = run_descriptor_jr(desc);
+
+ if (ret)
+ printf("Error in Decapsulation %d\n", ret);
++ else
++ printf("Decapsulation Success\n");
+
+ free(desc);
+ return ret;
+@@ -51,12 +54,16 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
+ }
+
+ inline_cnstr_jobdesc_blob_encap(desc, key_mod, src, dst, len);
++
++ debug("Descriptor dump:\n");
+ for (i = 0; i < 14; i++)
+- printf("%x\n", *(desc + i));
++ debug("Word[%d]: %08x\n", i, *(desc + i));
+ ret = run_descriptor_jr(desc);
+
+ if (ret)
+ printf("Error in Encapsulation %d\n", ret);
++ else
++ printf("Encapsulation Success\n");
+
+ free(desc);
+ return ret;
+--
+1.7.9.5
+
--- /dev/null
+From 9e157635c191762624c066d14e360e972aa1ad0f Mon Sep 17 00:00:00 2001
+From: Shengzhou Liu <Shengzhou.Liu@nxp.com>
+Date: Wed, 20 Jul 2016 15:44:58 +0800
+Subject: [PATCH 82/93] armv8: ls1012a: Update DDR timing
+
+Update MMDC timing CL-tRCD-tRP to 7-7-7.
+
+Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
+---
+ board/freescale/ls1012afrdm/ls1012afrdm.c | 2 +-
+ board/freescale/ls1012aqds/ls1012aqds.c | 2 +-
+ board/freescale/ls1012ardb/ls1012ardb.c | 2 +-
+ 3 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
+index 04f8f9a..a152a18 100644
+--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
++++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
+@@ -55,7 +55,7 @@ void mmdc_init(void)
+ /* configure timing parms */
+ out_be32(&mmdc->mdotc, 0x12554000);
+ out_be32(&mmdc->mdcfg0, 0xbabf7954);
+- out_be32(&mmdc->mdcfg1, 0xff328f64);
++ out_be32(&mmdc->mdcfg1, 0xdb328f64);
+ out_be32(&mmdc->mdcfg2, 0x01ff00db);
+
+ /* other parms */
+diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
+index 4ae8def..7bdb591 100644
+--- a/board/freescale/ls1012aqds/ls1012aqds.c
++++ b/board/freescale/ls1012aqds/ls1012aqds.c
+@@ -78,7 +78,7 @@ void mmdc_init(void)
+ /* configure timing parms */
+ out_be32(&mmdc->mdotc, 0x12554000);
+ out_be32(&mmdc->mdcfg0, 0xbabf7954);
+- out_be32(&mmdc->mdcfg1, 0xff328f64);
++ out_be32(&mmdc->mdcfg1, 0xdb328f64);
+ out_be32(&mmdc->mdcfg2, 0x01ff00db);
+
+ /* other parms */
+diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
+index 06e1f6b..ac51d56 100644
+--- a/board/freescale/ls1012ardb/ls1012ardb.c
++++ b/board/freescale/ls1012ardb/ls1012ardb.c
+@@ -84,7 +84,7 @@ void mmdc_init(void)
+ /* configure timing parms */
+ out_be32(&mmdc->mdotc, 0x12554000);
+ out_be32(&mmdc->mdcfg0, 0xbabf7954);
+- out_be32(&mmdc->mdcfg1, 0xff328f64);
++ out_be32(&mmdc->mdcfg1, 0xdb328f64);
+ out_be32(&mmdc->mdcfg2, 0x01ff00db);
+
+ /* other parms */
+--
+1.7.9.5
+
--- /dev/null
+From db48271175c0566bb5e59776a23297d64aec9fcd Mon Sep 17 00:00:00 2001
+From: Alison Wang <b18965@freescale.com>
+Date: Thu, 21 Jul 2016 18:13:29 +0800
+Subject: [PATCH 83/93] armv8: fsl-layerscape: Fix the conflict between PPA
+ and AArch32 support
+
+As there is conflict between PPA and AArch32 support, this patch is to
+add a new defconfig for AArch32 support and move the definition for PPA
+to the board defconfig.
+
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+---
+ configs/ls1012afrdm_aarch32_qspi_defconfig | 11 +++++++++++
+ configs/ls1012afrdm_qspi_defconfig | 1 +
+ configs/ls1012ardb_aarch32_qspi_defconfig | 11 +++++++++++
+ configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 1 +
+ configs/ls1012ardb_qspi_defconfig | 1 +
+ include/configs/ls1012afrdm.h | 1 -
+ include/configs/ls1012ardb.h | 1 -
+ 7 files changed, 25 insertions(+), 2 deletions(-)
+ create mode 100644 configs/ls1012afrdm_aarch32_qspi_defconfig
+ create mode 100644 configs/ls1012ardb_aarch32_qspi_defconfig
+
+diff --git a/configs/ls1012afrdm_aarch32_qspi_defconfig b/configs/ls1012afrdm_aarch32_qspi_defconfig
+new file mode 100644
+index 0000000..1bb9080
+--- /dev/null
++++ b/configs/ls1012afrdm_aarch32_qspi_defconfig
+@@ -0,0 +1,11 @@
++CONFIG_ARM=y
++CONFIG_TARGET_LS1012AFRDM=y
++CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
++# CONFIG_CMD_IMLS is not set
++# CONFIG_FSL_LS_PPA is not set
++CONFIG_SYS_NS16550=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
++CONFIG_OF_CONTROL=y
++CONFIG_DM=y
++CONFIG_SPI_FLASH=y
++CONFIG_DM_SPI=y
+diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
+index e27181c..1f69db7 100644
+--- a/configs/ls1012afrdm_qspi_defconfig
++++ b/configs/ls1012afrdm_qspi_defconfig
+@@ -2,6 +2,7 @@ CONFIG_ARM=y
+ CONFIG_TARGET_LS1012AFRDM=y
+ CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+ # CONFIG_CMD_IMLS is not set
++CONFIG_FSL_LS_PPA=y
+ CONFIG_SYS_NS16550=y
+ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
+ CONFIG_OF_CONTROL=y
+diff --git a/configs/ls1012ardb_aarch32_qspi_defconfig b/configs/ls1012ardb_aarch32_qspi_defconfig
+new file mode 100644
+index 0000000..df16f3b
+--- /dev/null
++++ b/configs/ls1012ardb_aarch32_qspi_defconfig
+@@ -0,0 +1,11 @@
++CONFIG_ARM=y
++CONFIG_TARGET_LS1012ARDB=y
++CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
++# CONFIG_CMD_IMLS is not set
++# CONFIG_FSL_LS_PPA is not set
++CONFIG_SYS_NS16550=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
++CONFIG_OF_CONTROL=y
++CONFIG_DM=y
++CONFIG_SPI_FLASH=y
++CONFIG_DM_SPI=y
+diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+index 92a95a8..4091503 100644
+--- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
++++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+@@ -2,6 +2,7 @@ CONFIG_ARM=y
+ CONFIG_TARGET_LS1012ARDB=y
+ CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,SECURE_BOOT"
+ # CONFIG_CMD_IMLS is not set
++# CONFIG_FSL_LS_PPA is not set
+ CONFIG_SYS_NS16550=y
+ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+ CONFIG_OF_CONTROL=y
+diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
+index f819038..e025247 100644
+--- a/configs/ls1012ardb_qspi_defconfig
++++ b/configs/ls1012ardb_qspi_defconfig
+@@ -2,6 +2,7 @@ CONFIG_ARM=y
+ CONFIG_TARGET_LS1012ARDB=y
+ CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+ # CONFIG_CMD_IMLS is not set
++CONFIG_FSL_LS_PPA=y
+ CONFIG_SYS_NS16550=y
+ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+ CONFIG_OF_CONTROL=y
+diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
+index 0e35fe9..a736687 100644
+--- a/include/configs/ls1012afrdm.h
++++ b/include/configs/ls1012afrdm.h
+@@ -10,7 +10,6 @@
+ #include "ls1012a_common.h"
+
+ #ifndef CONFIG_SECURE_BOOT
+-#define CONFIG_FSL_LS_PPA
+ #if defined(CONFIG_FSL_LS_PPA)
+ #define CONFIG_ARMV8_PSCI
+ #define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index d78edd2..400fa61 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -9,7 +9,6 @@
+
+ #include "ls1012a_common.h"
+
+-#define CONFIG_FSL_LS_PPA
+ #if defined(CONFIG_FSL_LS_PPA)
+ #define CONFIG_ARMV8_PSCI
+ #define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
+--
+1.7.9.5
+
--- /dev/null
+From 257802b8b8640e58e4a2001031f18facf056908e Mon Sep 17 00:00:00 2001
+From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Date: Mon, 25 Jul 2016 16:41:24 +0530
+Subject: [PATCH 84/93] armv8: fsl-layerscape: Moving FSL_LS_PPA flag to
+ EXTRA_OPTIONS
+
+Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+---
+ configs/ls1012afrdm_qspi_defconfig | 3 +--
+ configs/ls1012ardb_qspi_defconfig | 3 +--
+ 2 files changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
+index 1f69db7..0d1b0f3 100644
+--- a/configs/ls1012afrdm_qspi_defconfig
++++ b/configs/ls1012afrdm_qspi_defconfig
+@@ -1,8 +1,7 @@
+ CONFIG_ARM=y
+ CONFIG_TARGET_LS1012AFRDM=y
+-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
++CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT, FSL_LS_PPA"
+ # CONFIG_CMD_IMLS is not set
+-CONFIG_FSL_LS_PPA=y
+ CONFIG_SYS_NS16550=y
+ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
+ CONFIG_OF_CONTROL=y
+diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
+index e025247..00e4dd2 100644
+--- a/configs/ls1012ardb_qspi_defconfig
++++ b/configs/ls1012ardb_qspi_defconfig
+@@ -1,8 +1,7 @@
+ CONFIG_ARM=y
+ CONFIG_TARGET_LS1012ARDB=y
+-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
++CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT, FSL_LS_PPA"
+ # CONFIG_CMD_IMLS is not set
+-CONFIG_FSL_LS_PPA=y
+ CONFIG_SYS_NS16550=y
+ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+ CONFIG_OF_CONTROL=y
+--
+1.7.9.5
+
--- /dev/null
+From 0d3ccab8ba94f0cb1f5cb1c1391a79619c040f1c Mon Sep 17 00:00:00 2001
+From: Sumit Garg <sumit.garg@nxp.com>
+Date: Tue, 26 Jul 2016 07:43:41 -0400
+Subject: [PATCH 85/93] armv8: fsl-layerscape: Enable FSL_LS_PPA in Secure
+ boot target
+
+Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
+---
+ configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+index 4091503..bb9099b 100644
+--- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
++++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+@@ -1,8 +1,7 @@
+ CONFIG_ARM=y
+ CONFIG_TARGET_LS1012ARDB=y
+-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,SECURE_BOOT"
++CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT, FSL_LS_PPA, SECURE_BOOT"
+ # CONFIG_CMD_IMLS is not set
+-# CONFIG_FSL_LS_PPA is not set
+ CONFIG_SYS_NS16550=y
+ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+ CONFIG_OF_CONTROL=y
+--
+1.7.9.5
+
--- /dev/null
+From 986172ece10eee928ce66597d76f3f40ac3d25f7 Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Mon, 8 Aug 2016 14:24:13 +0800
+Subject: [PATCH 86/93] driver: spi: add spansion s25fs-s family
+ protect/unprotect
+
+In order to support spansion s25fs512s flash protect/unprotect:
+
+[1] Fill callbak flash->lock/unlock/is_locked by spansion_lock/
+unlock/is_locked.
+
+[2] Achieve protect/unprotected by operating sr1nv, cr1nv.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi/spi_flash.c | 194 +++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 194 insertions(+)
+
+diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
+index e04bd55..87a92e9 100644
+--- a/drivers/mtd/spi/spi_flash.c
++++ b/drivers/mtd/spi/spi_flash.c
+@@ -877,6 +877,193 @@ int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len)
+ }
+ #endif
+
++#if defined(CONFIG_SPI_FLASH_SPANSION)
++/*
++ * Return 1 if the entire region is locked, 0 otherwise
++ */
++static int spansion_is_locked_sr(struct spi_flash *flash, u32 ofs, u32 len,
++ u8 sr)
++{
++ loff_t lock_offs;
++ u32 lock_len;
++
++ stm_get_locked_range(flash, sr, &lock_offs, &lock_len);
++
++ return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
++}
++
++/*
++ * Check if a region of the flash is (completely) locked. See spansion_lock() for
++ * more info.
++ *
++ * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
++ * negative on errors.
++ */
++int spansion_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
++{
++ u8 cmd[4];
++ u32 sr1nv_offset = 0x0;
++ u8 sr1nv;
++ int ret;
++
++ cmd[0] = CMD_SPANSION_RDAR;
++ cmd[1] = sr1nv_offset >> 16;
++ cmd[2] = sr1nv_offset >> 8;
++ cmd[3] = sr1nv_offset >> 0;
++
++ ret = spi_flash_cmd_read(flash->spi, cmd, 4, &sr1nv, 1);
++ if (ret)
++ return -EIO;
++
++ return spansion_is_locked_sr(flash, ofs, len, sr1nv);
++}
++
++/*
++ * Lock a region of the flash. Compatible with Spansion s25fs-s family flash.
++ * Supports only the block protection bits BP{0,1,2} in the Status Register-1
++ * Non-Volatile(SR1NV).
++ *
++ * Sample table portion for 64MB flash (S25FS512S):
++ * Configuration Register-1 Non-Volatile(CR1NV[5])== 0
++ *
++ * | BP2 | BP1 | BP0 | Prot Length | Protected Portion
++ * ------------------------------------------------------------
++ * | 0 | 0 | 0 | NONE | NONE
++ * | 0 | 0 | 1 | 1 MB | Upper 1/64
++ * | 0 | 1 | 0 | 2 MB | Upper 1/32
++ * | 0 | 1 | 1 | 4 MB | Upper 1/16
++ * | 1 | 0 | 0 | 8 MB | Upper 1/8
++ * | 1 | 0 | 1 | 16 MB | Upper 1/4
++ * | 1 | 1 | 0 | 32 MB | Upper 1/2
++ * | 1 | 1 | 1 | 64 MB | ALL
++ *
++ * When CR1NV[5] == 1, the Lower memory array are protected.
++ *
++ * Returns negative on errors, 0 on success.
++ */
++int spansion_lock(struct spi_flash *flash, u32 ofs, size_t len)
++{
++ u8 status_old, status_new;
++ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
++ u8 shift = ffs(mask) - 1, pow, val;
++ int ret;
++ u8 cmd[4];
++ u32 sr1nv_offset = 0x0;
++ u8 sr1nv;
++
++ cmd[0] = CMD_SPANSION_RDAR;
++ cmd[1] = sr1nv_offset >> 16;
++ cmd[2] = sr1nv_offset >> 8;
++ cmd[3] = sr1nv_offset >> 0;
++
++ ret = spi_flash_cmd_read(flash->spi, cmd, 4, &sr1nv, 1);
++ if (ret)
++ return -EIO;
++ status_old = sr1nv;
++
++ /* SPI NOR always locks to the end */
++ if (ofs + len != flash->size) {
++ /* Does combined region extend to end? */
++ if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len,
++ status_old))
++ return -EINVAL;
++ len = flash->size - ofs;
++ }
++
++ /*
++ * Need smallest pow such that:
++ *
++ * 1 / (2^pow) <= (len / size)
++ *
++ * so (assuming power-of-2 size) we do:
++ *
++ * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
++ */
++ pow = ilog2(flash->size) - ilog2(len);
++ val = mask - (pow << shift);
++ if (val & ~mask)
++ return -EINVAL;
++
++ /* Don't "lock" with no region! */
++ if (!(val & mask))
++ return -EINVAL;
++
++ status_new = (status_old & ~mask) | val;
++
++ /* Only modify protection if it will not unlock other areas */
++ if ((status_new & mask) <= (status_old & mask))
++ return -EINVAL;
++
++ cmd[0] = CMD_SPANSION_WRAR;
++ ret = spi_flash_cmd_write(flash->spi, cmd, 4, &status_new, 1);
++ if (ret)
++ return -EIO;
++
++ return 0;
++}
++
++/*
++ * Unlock a region of the flash. See spansion_lock() for more info
++ *
++ * Returns negative on errors, 0 on success.
++ */
++int spansion_unlock(struct spi_flash *flash, u32 ofs, size_t len)
++{
++ uint8_t status_old, status_new;
++ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
++ u8 shift = ffs(mask) - 1, pow, val;
++ int ret;
++
++ u8 cmd[4];
++ u32 sr1nv_offset = 0x0;
++ u8 sr1nv;
++
++ cmd[0] = CMD_SPANSION_RDAR;
++ cmd[1] = sr1nv_offset >> 16;
++ cmd[2] = sr1nv_offset >> 8;
++ cmd[3] = sr1nv_offset >> 0;
++
++ ret = spi_flash_cmd_read(flash->spi, cmd, 4, &sr1nv, 1);
++ if (ret)
++ return -EIO;
++ status_old = sr1nv;
++
++ /* Cannot unlock; would unlock larger region than requested */
++ if (spansion_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size,
++ status_old))
++ return -EINVAL;
++ /*
++ * Need largest pow such that:
++ *
++ * 1 / (2^pow) >= (len / size)
++ *
++ * so (assuming power-of-2 size) we do:
++ *
++ * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
++ */
++ pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len));
++ if (ofs + len == flash->size) {
++ val = 0; /* fully unlocked */
++ } else {
++ val = mask - (pow << shift);
++ /* Some power-of-two sizes are not supported */
++ if (val & ~mask)
++ return -EINVAL;
++ }
++ status_new = (status_old & ~mask) | val;
++
++ /* Only modify protection if it will not lock other areas */
++ if ((status_new & mask) >= (status_old & mask))
++ return -EINVAL;
++
++ cmd[0] = CMD_SPANSION_WRAR;
++ ret = spi_flash_cmd_write(flash->spi, cmd, 4, &status_new, 1);
++ if (ret)
++ return -EIO;
++
++ return 0;
++}
++#endif
+
+ #ifdef CONFIG_SPI_FLASH_MACRONIX
+ static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+@@ -1132,6 +1319,13 @@ int spi_flash_scan(struct spi_flash *flash)
+ flash->flash_is_locked = stm_is_locked;
+ #endif
+ break;
++#if defined(CONFIG_SPI_FLASH_SPANSION)
++ case SPI_FLASH_CFI_MFR_SPANSION:
++ flash->flash_lock = spansion_lock;
++ flash->flash_unlock = spansion_unlock;
++ flash->flash_is_locked = spansion_is_locked;
++#endif
++ break;
+ default:
+ debug("SF: Lock ops not supported for %02x flash\n", idcode[0]);
+ }
+--
+1.7.9.5
+
--- /dev/null
+From 5610e5d9a759ecf48eccc1271aea8f8bc3399b50 Mon Sep 17 00:00:00 2001
+From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Date: Wed, 17 Aug 2016 18:31:53 +0530
+Subject: [PATCH 87/93] armv8/ls1012a: Update bootargs
+
+Add optimization parameters like "quiet" in bootargs to reduce the system
+boot time
+
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
+---
+ include/configs/ls1012a_common.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 7e935ad..0489492 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -153,7 +153,7 @@
+ #define CONFIG_BOOTCOMMAND "bootm $kernel_load"
+ #else
+ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
+- "earlycon=uart8250,mmio,0x21c0500"
++ "earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+ #define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\
+ "$kernel_start $kernel_size && "\
+ "bootm $kernel_load"
+--
+1.7.9.5
+
--- /dev/null
+From b045189aef457833face5d7c4506e908289d2bfe Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Thu, 18 Aug 2016 11:24:46 +0800
+Subject: [PATCH 88/93] driver: spi: enable stm_get_locked_range() for
+ spansion flash
+
+stm_get_locked_range() is also applicable for spansion flash, So we can
+share it.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi/spi_flash.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
+index 87a92e9..d69d2c3 100644
+--- a/drivers/mtd/spi/spi_flash.c
++++ b/drivers/mtd/spi/spi_flash.c
+@@ -702,7 +702,8 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
+ }
+ #endif
+
+-#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
++#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) || \
++ defined(CONFIG_SPI_FLASH_SPANSION)
+ static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
+ u32 *len)
+ {
+--
+1.7.9.5
+
--- /dev/null
+From 17c9f2a306b56d5ec5e5c54ce9abba6926831c46 Mon Sep 17 00:00:00 2001
+From: Yutang Jiang <yutang.jiang@nxp.com>
+Date: Fri, 23 Sep 2016 04:21:38 +0800
+Subject: [PATCH 89/93] driver: spi: fix id enclosure error
+
+Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
+---
+ drivers/mtd/spi/spi_flash.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
+index d69d2c3..dcb1628 100644
+--- a/drivers/mtd/spi/spi_flash.c
++++ b/drivers/mtd/spi/spi_flash.c
+@@ -1206,9 +1206,7 @@ int spi_flash_scan(struct spi_flash *flash)
+ u8 idcode[5];
+ u8 cmd;
+ int ret;
+-#ifdef CONFIG_SPI_FLASH_SPANSION
+ u8 id[6];
+-#endif
+
+ /* Read the ID codes */
+ ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
+--
+1.7.9.5
+
--- /dev/null
+From 0a8ebc8b855275b5fa035f33a964316d2b7b9a9e Mon Sep 17 00:00:00 2001
+From: Yutang Jiang <yutang.jiang@nxp.com>
+Date: Fri, 23 Sep 2016 04:34:29 +0800
+Subject: [PATCH 90/93] ls1012: add CONFIG_SYS_FSL_MAX_NUM_OF_SEC define
+
+Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
+---
+ arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
+index efaa79a..f1eb0d7 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
+@@ -246,6 +246,7 @@
+ #define CONFIG_SYS_FSL_SFP_BE
+ #define CONFIG_SYS_FSL_SRK_LE
+ #define CONFIG_KEY_REVOCATION
++#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+
+ #else
+ #error SoC not defined
+--
+1.7.9.5
+
--- /dev/null
+From da79bd42be7226c6db58b21b1fed595587d8dcaa Mon Sep 17 00:00:00 2001
+From: Yutang Jiang <yutang.jiang@nxp.com>
+Date: Tue, 18 Oct 2016 18:44:23 +0800
+Subject: [PATCH 91/93] armv8: fsl-layerscape: ls1012ardb: configs: disable
+ FSL_LS_PPA and remove aarch32 config
+
+Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
+---
+ configs/ls1012ardb_aarch32_qspi_defconfig | 11 -----------
+ configs/ls1012ardb_qspi_defconfig | 3 ++-
+ 2 files changed, 2 insertions(+), 12 deletions(-)
+ delete mode 100644 configs/ls1012ardb_aarch32_qspi_defconfig
+
+diff --git a/configs/ls1012ardb_aarch32_qspi_defconfig b/configs/ls1012ardb_aarch32_qspi_defconfig
+deleted file mode 100644
+index df16f3b..0000000
+--- a/configs/ls1012ardb_aarch32_qspi_defconfig
++++ /dev/null
+@@ -1,11 +0,0 @@
+-CONFIG_ARM=y
+-CONFIG_TARGET_LS1012ARDB=y
+-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+-# CONFIG_CMD_IMLS is not set
+-# CONFIG_FSL_LS_PPA is not set
+-CONFIG_SYS_NS16550=y
+-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+-CONFIG_OF_CONTROL=y
+-CONFIG_DM=y
+-CONFIG_SPI_FLASH=y
+-CONFIG_DM_SPI=y
+diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
+index 00e4dd2..df16f3b 100644
+--- a/configs/ls1012ardb_qspi_defconfig
++++ b/configs/ls1012ardb_qspi_defconfig
+@@ -1,7 +1,8 @@
+ CONFIG_ARM=y
+ CONFIG_TARGET_LS1012ARDB=y
+-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT, FSL_LS_PPA"
++CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+ # CONFIG_CMD_IMLS is not set
++# CONFIG_FSL_LS_PPA is not set
+ CONFIG_SYS_NS16550=y
+ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+ CONFIG_OF_CONTROL=y
+--
+1.7.9.5
+
--- /dev/null
+From b0f227f32f898bdf52f4ecafc83d1e2f1d6ee6ec Mon Sep 17 00:00:00 2001
+From: Yutang Jiang <yutang.jiang@nxp.com>
+Date: Thu, 27 Oct 2016 23:47:43 +0800
+Subject: [PATCH 92/93] armv8: set openwrt/lede default boot env for
+ ls1012ardb
+
+Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
+---
+ include/configs/ls1012a_common.h | 28 +++++++++++++++++++++++++++-
+ 1 file changed, 27 insertions(+), 1 deletion(-)
+
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 0489492..b23ba4f 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -130,6 +130,24 @@
+
+ #define CONFIG_DISPLAY_CPUINFO
+
++#define WRTBOOT_DEFAULT "pfe stop && sf probe 0:0 && setenv bootargs " \
++ "root=/dev/mtdblock5 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200 " \
++ "earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1M(rcw)," \
++ "1M(u-boot),1M(u-boot-env),1M(dtb),5M(kernel),23M(rootfs),32M(user)" \
++ " && sf read $fdtaddr 0x300000 100000 && " \
++ "sf read $loadaddr 0x400000 500000 && bootm $loadaddr - $fdtaddr"
++
++#define WRTBOOT_EXT4RFS "pfe stop && sf probe 0:0 && setenv bootargs " \
++ "root=/dev/mtdblock5 rootfstype=ext4 noinitrd console=ttyS0,115200 " \
++ "earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1M(rcw)," \
++ "1M(u-boot),1M(u-boot-env),1M(dtb),5M(kernel),23M(ext4rfs),32M(user)" \
++ " && sf read $fdtaddr 0x300000 100000 && " \
++ "sf read $loadaddr 0x400000 500000 && bootm $loadaddr - $fdtaddr"
++
++#define WRTUPDATE_DEFAULT " sf probe 0:0 && tftp 0xa0000000 <tftp_folder>/" \
++ "lede-layerscape-64b-ls1012ardb-squashfs-firmware.ext4.bin && protect off all" \
++ " && sf erase 0 $filesize && sf write 0xa0000000 0 $filesize; reset"
++
+ /* Initial environment variables */
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ "initrd_high=0xffffffff\0" \
+@@ -144,6 +162,12 @@
+ "kernel_start=0xa00000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
++ "loadaddr=82000000\0" \
++ "ramdiskaddr=88000000\0" \
++ "fdtaddr=8f000000\0" \
++ "wrtboot=" WRTBOOT_DEFAULT "\0" \
++ "wrtboot_ext4rfs=" WRTBOOT_EXT4RFS "\0" \
++ "wrtupdate=" WRTUPDATE_DEFAULT "\0" \
+ "console=ttyAMA0,38400n8\0"
+
+ #ifdef CONFIG_EMU
+@@ -158,7 +182,9 @@
+ "$kernel_start $kernel_size && "\
+ "bootm $kernel_load"
+ #endif
+-#define CONFIG_BOOTDELAY 10
++#define CONFIG_BOOTDELAY 3
++#undef CONFIG_BOOTCOMMAND
++#define CONFIG_BOOTCOMMAND "run wrtboot_ext4rfs"
+
+ /* Monitor Command Prompt */
+ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+--
+1.7.9.5
+
--- /dev/null
+From f13ff4fe020c9018eb5a472b7c8a69a54e45ce29 Mon Sep 17 00:00:00 2001
+From: Yutang Jiang <yutang.jiang@nxp.com>
+Date: Tue, 18 Oct 2016 22:37:17 +0800
+Subject: [PATCH 93/93] add byte_swap.tcl script for uboot can run/save in
+ qspi flash
+
+Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
+---
+ Makefile | 1 +
+ byte_swap.tcl | 36 ++++++++++++++++++++++++++++++++++++
+ 2 files changed, 37 insertions(+)
+ create mode 100755 byte_swap.tcl
+
+diff --git a/Makefile b/Makefile
+index 1c2818c..b73375f 100644
+--- a/Makefile
++++ b/Makefile
+@@ -836,6 +836,7 @@ dtbs dts/dt.dtb: checkdtc u-boot
+
+ u-boot-dtb.bin: u-boot.bin dts/dt.dtb FORCE
+ $(call if_changed,cat)
++ tclsh byte_swap.tcl u-boot-dtb.bin u-boot-swap.bin 8
+
+ %.imx: %.bin
+ $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
+diff --git a/byte_swap.tcl b/byte_swap.tcl
+new file mode 100755
+index 0000000..a4e8008
+--- /dev/null
++++ b/byte_swap.tcl
+@@ -0,0 +1,36 @@
++puts $argv
++set i_file [lindex $argv 0]
++set o_file [lindex $argv 1]
++set num_b [lindex $argv 2]
++puts ""
++
++set fileid_i [open $i_file "r"]
++set fileid_o [open $o_file "w+"]
++fconfigure $fileid_i -translation {binary binary}
++fconfigure $fileid_o -translation {binary binary}
++
++set old_bin [read $fileid_i]
++set new_bin {}
++set old_length [string length $old_bin]
++set old_rem [expr $old_length % $num_b]
++if {$old_rem != 0} {
++ for {set i 0} {$i< [expr $num_b - $old_rem]} {incr i 1} {
++ append old_bin y
++ }
++}
++for {set i 0} {$i<[string length $old_bin]} {incr i $num_b} {
++ for {set j $num_b} {$j>0} {incr j -1} {
++ append new_bin [string index $old_bin [expr $i+($j-1)]]
++ }
++}
++
++for {set i 0} {$i<[string length $old_bin]} {incr i $num_b} {
++ set binValue [string range $old_bin [expr $i+0] [expr $i+($num_b-1)]]
++ binary scan $binValue H[expr $num_b*2] hexValue
++
++ set binValue [string range $new_bin [expr $i+0] [expr $i+($num_b-1)]]
++ binary scan $binValue H[expr $num_b*2] hexValue
++}
++
++puts -nonewline $fileid_o $new_bin
++close $fileid_o
+--
+1.7.9.5
+
--- /dev/null
+#
+# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=ppfe
+PKG_VERSION:=v1.0
+PKG_RELEASE:=1
+
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
+PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
+PKG_SOURCE_URL:=https://github.com/fsl-jyt/ppfe.git
+PKG_SOURCE_VERSION:=b9bb5cc690c0aab2592eb9d443ef55cc9dff8557
+PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
+
+PKG_LICENSE:=GPL-2.0 GPL-2.0+
+PKG_LICENSE_FILES:=Licenses/README
+
+include $(INCLUDE_DIR)/package.mk
+
+define ppfe/Default
+ TITLE:=
+ CONFIG:=
+endef
+
+define ppfe/ls1012ardb
+ TITLE:=PPFE firmware $(PKG_NAME)-$(PKG_VERSION) for NXP ls1012a Dev Board\
+ (must enable CONFIG_NO_STRIP=y for avoid firmware be broke)
+ CONFIG:=ls1012a/Freescale-Binary-EULA ls1012a/ppfe_class_ls1012a.elf ls1012a/ppfe_tmu_ls1012a.elf
+endef
+
+PPFES := \
+ ls1012ardb
+
+define Package/ppfe/template
+define Package/ppfe-$(1)
+ SECTION:=firmware
+ CATEGORY:=Firmware
+ DEPENDS:=@TARGET_layerscape
+ TITLE:=$(2)
+ URL:=https://github.com/fsl-jyt/ppfe.git
+ VARIANT:=$(1)
+ MAINTAINER:=Jiang Yutang <jiangyutang1978@gmail.com>
+endef
+endef
+
+define BuildPPFEPackage
+ $(eval $(ppfe/Default))
+ $(eval $(ppfe/$(1)))
+ $(call Package/ppfe/template,$(1),$(TITLE))
+endef
+
+ifdef BUILD_VARIANT
+$(eval $(call ppfe/$(BUILD_VARIANT)))
+PPFE_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
+endif
+
+define Build/Compile
+endef
+
+define Package/ppfe/install/default
+ $(INSTALL_DIR) $(1)/lib/firmware
+ $(foreach i,$(PPFE_CONFIG), \
+ $(INSTALL_DATA) $(PKG_BUILD_DIR)/$(i) $(1)/lib/firmware/ ;\
+ )
+endef
+
+define Package/ppfe/install/template
+define Package/ppfe-$(1)/install
+ $(call Package/ppfe/install/default,$$(1),$(2))
+endef
+endef
+
+$(foreach p,$(PPFES), \
+ $(eval $(call Package/ppfe/install/template,$(p),$(p))) \
+)
+
+$(foreach p,$(PPFES), \
+ $(eval $(call BuildPPFEPackage,$(p))) \
+ $(eval $(call BuildPackage,ppfe-$(p))) \
+)
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
PKG_SOURCE_URL:=https://github.com/fsl-jyt/rcw.git
-PKG_SOURCE_VERSION:=4c74045c34375ee0cf6a9bbd57ef8f00a5a01fd6
+PKG_SOURCE_VERSION:=e101d1207f402c7b761990a3e6681fdae8f253e3
PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
CONFIG=ls1043ardb-rcw.bin
endef
+define rcw/ls1012ardb
+ TITLE=RCW binary $(PKG_NAME)-$(PKG_VERSION) for NXP ls1012ardb 64b/32b Dev Board
+ CONFIG=ls1012ardb-rcw.bin
+endef
+
RCWS := \
- ls1043ardb
+ ls1043ardb \
+ ls1012ardb
define Package/rcw/template
define Package/rcw-layerscape-$(1)
DEFAULT_PACKAGES+= \
rcw-layerscape-ls1043ardb uboot-layerscape-$(SUBTARGET)-ls1043ardb \
- fman-layerscape-ls1043ardb
+ fman-layerscape-ls1043ardb \
+ rcw-layerscape-ls1012ardb uboot-layerscape-$(SUBTARGET)-ls1012ardb \
+ kmod-ppfe ppfe-ls1012ardb
$(eval $(call Profile,Default))
--- /dev/null
+# Put your custom commands here that should be executed once
+# the system init finished. By default this file does nothing.
+modprobe pfe.ko
+exit 0
CONFIG_VITESSE_PHY=y
CONFIG_XPS=y
CONFIG_ZLIB_INFLATE=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_SPI_FSL_QUADSPI=y
dd if=$(DTS_DIR)/$(1).dtb >> $@
endef
+define Build/append-ls-rootfs-ext4
+ $(STAGING_DIR_HOST)/bin/make_ext4fs -l $(word 2,$(1)) -b 4096 -i 6000 -m 0 -J $(KDIR)/$(word 1,$(1))-$(word 2,$(1)).root.ext4 $(TARGET_DIR)
+ dd if=$(KDIR)/$(word 1,$(1))-$(word 2,$(1)).root.ext4 >> $@
+endef
+
define Device/Default
PROFILES = Default
FILESYSTEMS := squashfs
endef
TARGET_DEVICES += ls1043ardb
+define Device/ls1012ardb
+ DEVICE_TITLE := ls1012ardb-$(SUBTARGET)
+ DEVICE_PACKAGES += rcw-layerscape-ls1012ardb uboot-layerscape-$(SUBTARGET)-ls1012ardb kmod-ppfe ppfe-ls1012ardb
+ifeq ($(SUBTARGET),64b)
+ DEVICE_DTS = freescale/fsl-ls1012a-rdb
+endif
+ifeq ($(SUBTARGET),32b)
+ DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls1012a-rdb
+endif
+ IMAGE/firmware.bin = append-ls-rcw $(1) | pad-to 1M | append-ls-uboot $(1) | pad-to 3M | \
+ append-ls-dtb $$(DEVICE_DTS) | pad-to 4M | append-kernel | pad-to 9M | \
+ append-rootfs | pad-to 32M | check-size 33554433
+ IMAGES += firmware.ext4.bin
+ IMAGE/firmware.ext4.bin = append-ls-rcw $(1) | pad-to 1M | append-ls-uboot $(1) | pad-to 3M | \
+ append-ls-dtb $$(DEVICE_DTS) | pad-to 4M | append-kernel | pad-to 9M | \
+ append-ls-rootfs-ext4 $(1) 23M | check-size 33554433
+endef
+TARGET_DEVICES += ls1012ardb
+
$(eval $(call BuildImage))
--- /dev/null
+#
+# Copyright (C) Jiang Yutang <jiangyutang1978@gmail.com>
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+define KernelPackage/ppfe
+ SUBMENU:=$(NETWORK_DEVICES_MENU)
+ TITLE:=Freescale PPFE Driver support
+ KCONFIG:=CONFIG_FSL_PPFE
+ FILES:=$(LINUX_DIR)/drivers/staging/fsl_ppfe/pfe.ko
+ AUTOLOAD:=$(call AutoLoad,35,ppfe)
+endef
+
+define KernelPackage/ppfe/description
+ Kernel modules for Freescale PPFE Driver support.
+endef
+
+$(eval $(call KernelPackage,ppfe))
--- /dev/null
+From f560fdb9d71aaf3adc54341a1650577c78495df9 Mon Sep 17 00:00:00 2001
+From: Brian Norris <computersforpeace@gmail.com>
+Date: Fri, 30 Oct 2015 20:33:22 -0700
+Subject: [PATCH 074/113] mtd: {nand,spi-nor}: assign MTD of_node
+
+We should pass along our flash DT node to the MTD layer, so it can set
+up ofpart for us.
+
+cherry-pick{
+remove the code:
+drivers/mtd/nand/nand_base.c | 3 +
+commit:3e63b26bdd4069c3df2cd7ce7217a21d06801b41
+}
+
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -1217,6 +1217,7 @@ int spi_nor_scan(struct spi_nor *nor, co
+ mtd->flags |= MTD_NO_ERASE;
+
+ mtd->dev.parent = dev;
++ mtd_set_of_node(mtd, np);
+ nor->page_size = info->page_size;
+ mtd->writebufsize = nor->page_size;
+
--- /dev/null
+From f906ec330da9aa83de5382653436be36273c63d3 Mon Sep 17 00:00:00 2001
+From: Brian Norris <computersforpeace@gmail.com>
+Date: Fri, 30 Oct 2015 20:33:24 -0700
+Subject: [PATCH 075/113] mtd: spi-nor: convert to spi_nor_{get,
+ set}_flash_node()
+
+Used semantic patch with 'make coccicheck MODE=patch COCCI=script.cocci':
+
+---8<----
+virtual patch
+
+@@
+struct spi_nor b;
+struct spi_nor *c;
+expression d;
+@@
+(
+-(b).flash_node = (d)
++spi_nor_set_flash_node(&b, d)
+|
+-(c)->flash_node = (d)
++spi_nor_set_flash_node(c, d)
+)
+---8<----
+
+And a manual conversion for the one use of spi_nor_get_flash_node().
+
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+---
+ drivers/mtd/devices/m25p80.c | 2 +-
+ drivers/mtd/spi-nor/fsl-quadspi.c | 2 +-
+ drivers/mtd/spi-nor/nxp-spifi.c | 2 +-
+ drivers/mtd/spi-nor/spi-nor.c | 2 +-
+ 4 files changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -221,7 +221,7 @@ static int m25p_probe(struct spi_device
+ nor->read_reg = m25p80_read_reg;
+
+ nor->dev = &spi->dev;
+- nor->flash_node = spi->dev.of_node;
++ spi_nor_set_flash_node(nor, spi->dev.of_node);
+ nor->priv = flash;
+
+ spi_set_drvdata(spi, flash);
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -1013,7 +1013,7 @@ static int fsl_qspi_probe(struct platfor
+ mtd = &nor->mtd;
+
+ nor->dev = dev;
+- nor->flash_node = np;
++ spi_nor_set_flash_node(nor, np);
+ nor->priv = q;
+
+ /* fill the hooks */
+--- a/drivers/mtd/spi-nor/nxp-spifi.c
++++ b/drivers/mtd/spi-nor/nxp-spifi.c
+@@ -330,7 +330,7 @@ static int nxp_spifi_setup_flash(struct
+ writel(ctrl, spifi->io_base + SPIFI_CTRL);
+
+ spifi->nor.dev = spifi->dev;
+- spifi->nor.flash_node = np;
++ spi_nor_set_flash_node(&spifi->nor, np);
+ spifi->nor.priv = spifi;
+ spifi->nor.read = nxp_spifi_read;
+ spifi->nor.write = nxp_spifi_write;
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -1111,7 +1111,7 @@ int spi_nor_scan(struct spi_nor *nor, co
+ const struct flash_info *info = NULL;
+ struct device *dev = nor->dev;
+ struct mtd_info *mtd = &nor->mtd;
+- struct device_node *np = nor->flash_node;
++ struct device_node *np = spi_nor_get_flash_node(nor);
+ int ret;
+ int i;
+
--- /dev/null
+From e36da6d0a0841ea3a75d5189057bd020d737e71a Mon Sep 17 00:00:00 2001
+From: Brian Norris <computersforpeace@gmail.com>
+Date: Fri, 30 Oct 2015 20:33:26 -0700
+Subject: [PATCH 076/113] mtd: spi-nor: drop unnecessary partition parser data
+
+Now that the SPI-NOR/MTD framework pass the 'flash_node' through to the
+partition parsing code, we don't have to do it ourselves.
+
+Also convert to mtd_device_register(), since we don't need the 2nd and
+3rd parameters anymore.
+
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+---
+ drivers/mtd/devices/m25p80.c | 8 ++------
+ drivers/mtd/spi-nor/fsl-quadspi.c | 4 +---
+ drivers/mtd/spi-nor/nxp-spifi.c | 4 +---
+ 3 files changed, 4 insertions(+), 12 deletions(-)
+
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -197,7 +197,6 @@ static int m25p80_erase(struct spi_nor *
+ */
+ static int m25p_probe(struct spi_device *spi)
+ {
+- struct mtd_part_parser_data ppdata;
+ struct flash_platform_data *data;
+ struct m25p *flash;
+ struct spi_nor *nor;
+@@ -249,11 +248,8 @@ static int m25p_probe(struct spi_device
+ if (ret)
+ return ret;
+
+- ppdata.of_node = spi->dev.of_node;
+-
+- return mtd_device_parse_register(&nor->mtd, NULL, &ppdata,
+- data ? data->parts : NULL,
+- data ? data->nr_parts : 0);
++ return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
++ data ? data->nr_parts : 0);
+ }
+
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -927,7 +927,6 @@ static void fsl_qspi_unprep(struct spi_n
+ static int fsl_qspi_probe(struct platform_device *pdev)
+ {
+ struct device_node *np = pdev->dev.of_node;
+- struct mtd_part_parser_data ppdata;
+ struct device *dev = &pdev->dev;
+ struct fsl_qspi *q;
+ struct resource *res;
+@@ -1038,8 +1037,7 @@ static int fsl_qspi_probe(struct platfor
+ if (ret)
+ goto mutex_failed;
+
+- ppdata.of_node = np;
+- ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
++ ret = mtd_device_register(mtd, NULL, 0);
+ if (ret)
+ goto mutex_failed;
+
+--- a/drivers/mtd/spi-nor/nxp-spifi.c
++++ b/drivers/mtd/spi-nor/nxp-spifi.c
+@@ -271,7 +271,6 @@ static void nxp_spifi_dummy_id_read(stru
+ static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
+ struct device_node *np)
+ {
+- struct mtd_part_parser_data ppdata;
+ enum read_mode flash_read;
+ u32 ctrl, property;
+ u16 mode = 0;
+@@ -361,8 +360,7 @@ static int nxp_spifi_setup_flash(struct
+ return ret;
+ }
+
+- ppdata.of_node = np;
+- ret = mtd_device_parse_register(&spifi->nor.mtd, NULL, &ppdata, NULL, 0);
++ ret = mtd_device_register(&spifi->nor.mtd, NULL, 0);
+ if (ret) {
+ dev_err(spifi->dev, "mtd device parse failed\n");
+ return ret;
--- /dev/null
+From a2f87e7df641b482e217f5b0efbaf41f6b8a0cf6 Mon Sep 17 00:00:00 2001
+From: Brian Norris <computersforpeace@gmail.com>
+Date: Fri, 30 Oct 2015 20:33:20 -0700
+Subject: [PATCH 077/113] mtd: add get/set of_node/flash_node helpers
+
+We are going to begin using the mtd->dev.of_node field for MTD device
+nodes, so let's add helpers for it. Also, we'll be making some
+conversions on spi_nor (and nand_chip eventually) too, so get that ready
+with their own helpers.
+
+commit:28b8b26b308e656edfa9467867d5f79212da2ec3
+delete the include/linux/mtd/nand.h
+just upgrade the code about spi.
+
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
+---
+ include/linux/mtd/mtd.h | 11 +++++++++++
+ include/linux/mtd/spi-nor.h | 11 +++++++++++
+ 2 files changed, 22 insertions(+)
+
+--- a/include/linux/mtd/mtd.h
++++ b/include/linux/mtd/mtd.h
+@@ -258,6 +258,17 @@ struct mtd_info {
+ int usecount;
+ };
+
++static inline void mtd_set_of_node(struct mtd_info *mtd,
++ struct device_node *np)
++{
++ mtd->dev.of_node = np;
++}
++
++static inline struct device_node *mtd_get_of_node(struct mtd_info *mtd)
++{
++ return mtd->dev.of_node;
++}
++
+ int mtd_erase(struct mtd_info *mtd, struct erase_info *instr);
+ int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
+ void **virt, resource_size_t *phys);
+--- a/include/linux/mtd/spi-nor.h
++++ b/include/linux/mtd/spi-nor.h
+@@ -184,6 +184,17 @@ struct spi_nor {
+ void *priv;
+ };
+
++static inline void spi_nor_set_flash_node(struct spi_nor *nor,
++ struct device_node *np)
++{
++ nor->flash_node = np;
++}
++
++static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
++{
++ return nor->flash_node;
++}
++
+ /**
+ * spi_nor_scan() - scan the SPI NOR
+ * @nor: the spi_nor structure
--- /dev/null
+From df36b4601bc9f84684249a26eb39b818d6785fb8 Mon Sep 17 00:00:00 2001
+From: Brian Norris <computersforpeace@gmail.com>
+Date: Fri, 30 Oct 2015 20:33:27 -0700
+Subject: [PATCH 078/113] mtd: spi-nor: drop flash_node field
+
+We can just alias to the MTD of_node.
+
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 1 -
+ include/linux/mtd/spi-nor.h | 6 ++----
+ 2 files changed, 2 insertions(+), 5 deletions(-)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -1217,7 +1217,6 @@ int spi_nor_scan(struct spi_nor *nor, co
+ mtd->flags |= MTD_NO_ERASE;
+
+ mtd->dev.parent = dev;
+- mtd_set_of_node(mtd, np);
+ nor->page_size = info->page_size;
+ mtd->writebufsize = nor->page_size;
+
+--- a/include/linux/mtd/spi-nor.h
++++ b/include/linux/mtd/spi-nor.h
+@@ -123,7 +123,6 @@ enum spi_nor_option_flags {
+ * @mtd: point to a mtd_info structure
+ * @lock: the lock for the read/write/erase/lock/unlock operations
+ * @dev: point to a spi device, or a spi nor controller device.
+- * @flash_node: point to a device node describing this flash instance.
+ * @page_size: the page size of the SPI NOR
+ * @addr_width: number of address bytes
+ * @erase_opcode: the opcode for erasing a sector
+@@ -154,7 +153,6 @@ struct spi_nor {
+ struct mtd_info mtd;
+ struct mutex lock;
+ struct device *dev;
+- struct device_node *flash_node;
+ u32 page_size;
+ u8 addr_width;
+ u8 erase_opcode;
+@@ -187,12 +185,12 @@ struct spi_nor {
+ static inline void spi_nor_set_flash_node(struct spi_nor *nor,
+ struct device_node *np)
+ {
+- nor->flash_node = np;
++ mtd_set_of_node(&nor->mtd, np);
+ }
+
+ static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
+ {
+- return nor->flash_node;
++ return mtd_get_of_node(&nor->mtd);
+ }
+
+ /**
--- /dev/null
+From 3ea419cf269832f5743d9b5ad75ece5178b02b09 Mon Sep 17 00:00:00 2001
+From: Brian Norris <computersforpeace@gmail.com>
+Date: Fri, 30 Oct 2015 12:56:22 -0700
+Subject: [PATCH 079/113] mtd: spi-nor: remove unnecessary leading space from
+ dbg print
+
+As Cyrille noted [1], this line is wrong.
+
+[1] http://lists.infradead.org/pipermail/linux-mtd/2015-September/061725.html
+
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+Cc: Cyrille Pitchen <cyrille.pitchen@atmel.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -860,7 +860,7 @@ static const struct flash_info *spi_nor_
+
+ tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
+ if (tmp < 0) {
+- dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
++ dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
+ return ERR_PTR(tmp);
+ }
+
--- /dev/null
+From bd02decd1ad7cc883ce388e769a34a3c402b90c4 Mon Sep 17 00:00:00 2001
+From: Brian Norris <computersforpeace@gmail.com>
+Date: Mon, 16 Nov 2015 10:45:30 -0800
+Subject: [PATCH 080/113] mtd: fsl-quadspi: possible NULL dereference
+
+It is theoretically possible to probe this driver without a matching
+device tree, so let's guard against this.
+
+Also, use the of_device_get_match_data() helper to make this a bit
+simpler.
+
+Coverity complained about this one.
+
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+Acked-by: Han xu <han.xu@freescale.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -269,7 +269,7 @@ struct fsl_qspi {
+ struct clk *clk, *clk_en;
+ struct device *dev;
+ struct completion c;
+- struct fsl_qspi_devtype_data *devtype_data;
++ const struct fsl_qspi_devtype_data *devtype_data;
+ u32 nor_size;
+ u32 nor_num;
+ u32 clk_rate;
+@@ -933,8 +933,6 @@ static int fsl_qspi_probe(struct platfor
+ struct spi_nor *nor;
+ struct mtd_info *mtd;
+ int ret, i = 0;
+- const struct of_device_id *of_id =
+- of_match_device(fsl_qspi_dt_ids, &pdev->dev);
+
+ q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
+ if (!q)
+@@ -945,7 +943,9 @@ static int fsl_qspi_probe(struct platfor
+ return -ENODEV;
+
+ q->dev = dev;
+- q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data;
++ q->devtype_data = of_device_get_match_data(dev);
++ if (!q->devtype_data)
++ return -ENODEV;
+ platform_set_drvdata(pdev, q);
+
+ /* find the resources */
--- /dev/null
+From 56bd0e13d8bc3b4486251b10ac9d2ba7434c21ee Mon Sep 17 00:00:00 2001
+From: Brian Norris <computersforpeace@gmail.com>
+Date: Tue, 10 Nov 2015 12:15:27 -0800
+Subject: [PATCH 081/113] mtd: spi-nor: provide default erase_sector
+ implementation
+
+Some spi-nor drivers perform sector erase by duplicating their
+write_reg() command. Let's not require that the driver fill this out,
+and provide a default instead.
+
+Tested on m25p80.c and Medatek's MT8173 SPI NOR flash driver.
+
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 37 +++++++++++++++++++++++++++++++++----
+ include/linux/mtd/spi-nor.h | 3 ++-
+ 2 files changed, 35 insertions(+), 5 deletions(-)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -38,6 +38,7 @@
+ #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
+
+ #define SPI_NOR_MAX_ID_LEN 6
++#define SPI_NOR_MAX_ADDR_WIDTH 4
+
+ struct flash_info {
+ char *name;
+@@ -313,6 +314,29 @@ static void spi_nor_unlock_and_unprep(st
+ }
+
+ /*
++ * Initiate the erasure of a single sector
++ */
++static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
++{
++ u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
++ int i;
++
++ if (nor->erase)
++ return nor->erase(nor, addr);
++
++ /*
++ * Default implementation, if driver doesn't have a specialized HW
++ * control
++ */
++ for (i = nor->addr_width - 1; i >= 0; i--) {
++ buf[i] = addr & 0xff;
++ addr >>= 8;
++ }
++
++ return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
++}
++
++/*
+ * Erase an address range on the nor chip. The address range may extend
+ * one or more erase sectors. Return an error is there is a problem erasing.
+ */
+@@ -371,10 +395,9 @@ static int spi_nor_erase(struct mtd_info
+ while (len) {
+ write_enable(nor);
+
+- if (nor->erase(nor, addr)) {
+- ret = -EIO;
++ ret = spi_nor_erase_sector(nor, addr);
++ if (ret)
+ goto erase_err;
+- }
+
+ addr += mtd->erasesize;
+ len -= mtd->erasesize;
+@@ -1098,7 +1121,7 @@ static int set_quad_mode(struct spi_nor
+ static int spi_nor_check(struct spi_nor *nor)
+ {
+ if (!nor->dev || !nor->read || !nor->write ||
+- !nor->read_reg || !nor->write_reg || !nor->erase) {
++ !nor->read_reg || !nor->write_reg) {
+ pr_err("spi-nor: please fill all the necessary fields!\n");
+ return -EINVAL;
+ }
+@@ -1299,6 +1322,12 @@ int spi_nor_scan(struct spi_nor *nor, co
+ nor->addr_width = 3;
+ }
+
++ if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
++ dev_err(dev, "address width is too large: %u\n",
++ nor->addr_width);
++ return -EINVAL;
++ }
++
+ nor->read_dummy = spi_nor_read_dummy_cycles(nor);
+
+ dev_info(dev, "%s (%lld Kbytes)\n", info->name,
+--- a/include/linux/mtd/spi-nor.h
++++ b/include/linux/mtd/spi-nor.h
+@@ -142,7 +142,8 @@ enum spi_nor_option_flags {
+ * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
+ * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
+ * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
+- * at the offset @offs
++ * at the offset @offs; if not provided by the driver,
++ * spi-nor will send the erase opcode via write_reg()
+ * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
+ * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
+ * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
--- /dev/null
+From 30e609daed95664824e95344e85c7eaedd1bfcf3 Mon Sep 17 00:00:00 2001
+From: Ricardo Ribalda <ricardo.ribalda@gmail.com>
+Date: Mon, 30 Nov 2015 20:41:17 +0100
+Subject: [PATCH 083/113] mtd: spi-nor: Fix error message with unrecognized
+ JEDEC
+
+The error message was:
+
+m25p80 spi32766.0: unrecognized JEDEC id bytes: 00, 0, 0
+
+The new error message:
+
+m25p80 spi32766.0: unrecognized JEDEC id bytes: 00, 00, 00
+
+Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -894,7 +894,7 @@ static const struct flash_info *spi_nor_
+ return &spi_nor_ids[tmp];
+ }
+ }
+- dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %2x, %2x\n",
++ dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
+ id[0], id[1], id[2]);
+ return ERR_PTR(-ENODEV);
+ }
--- /dev/null
+From 9e473594776da97245049019f1d1e9608ff1214a Mon Sep 17 00:00:00 2001
+From: Heiner Kallweit <hkallweit1@gmail.com>
+Date: Tue, 17 Nov 2015 20:18:54 +0100
+Subject: [PATCH 084/113] mtd: spi-nor: fix error handling in spi_nor_erase
+
+The documenting comment of mtd_erase in mtdcore.c states:
+Device drivers are supposed to call instr->callback() whenever
+the operation completes, even if it completes with a failure.
+
+Currently the callback isn't called in case of failure. Fix this.
+
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 8 ++------
+ 1 file changed, 2 insertions(+), 6 deletions(-)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -410,17 +410,13 @@ static int spi_nor_erase(struct mtd_info
+
+ write_disable(nor);
+
++erase_err:
+ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
+
+- instr->state = MTD_ERASE_DONE;
++ instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE;
+ mtd_erase_callback(instr);
+
+ return ret;
+-
+-erase_err:
+- spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
+- instr->state = MTD_ERASE_FAILED;
+- return ret;
+ }
+
+ static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
--- /dev/null
+From d05c68e35f42a46b352d2a4bdaef9954c946e20a Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Fri, 20 Nov 2015 16:26:11 -0200
+Subject: [PATCH 085/113] mtd: spi-nor: Check the return value from read_sr()
+
+[context adjustment]
+
+We should better check the return value from read_sr() and
+propagate it in the case of error.
+
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -478,11 +478,13 @@ static int stm_is_locked_sr(struct spi_n
+ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
+ {
+ struct mtd_info *mtd = &nor->mtd;
+- u8 status_old, status_new;
++ int status_old, status_new;
+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
+ u8 shift = ffs(mask) - 1, pow, val;
+
+ status_old = read_sr(nor);
++ if (status_old < 0)
++ return status_old;
+
+ /* SPI NOR always locks to the end */
+ if (ofs + len != mtd->size) {
+@@ -528,11 +530,13 @@ static int stm_lock(struct spi_nor *nor,
+ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
+ {
+ struct mtd_info *mtd = &nor->mtd;
+- uint8_t status_old, status_new;
++ int status_old, status_new;
+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
+ u8 shift = ffs(mask) - 1, pow, val;
+
+ status_old = read_sr(nor);
++ if (status_old < 0)
++ return status_old;
+
+ /* Cannot unlock; would unlock larger region than requested */
+ if (stm_is_locked_sr(nor, ofs - mtd->erasesize, mtd->erasesize,
+@@ -1036,6 +1040,8 @@ static int macronix_quad_enable(struct s
+ int ret, val;
+
+ val = read_sr(nor);
++ if (val < 0)
++ return val;
+ write_enable(nor);
+
+ write_sr(nor, val | SR_QUAD_EN_MX);
--- /dev/null
+From 3a06c61b48fbc23046928275e37a693e1055ae74 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ezequiel=20Garc=C3=ADa?= <ezequiel@vanguardiasur.com.ar>
+Date: Mon, 28 Dec 2015 17:54:51 -0300
+Subject: [PATCH 086/113] mtd: spi-nor: wait until lock/unlock operations are
+ ready
+
+On Micron and Numonyx devices, the status register write command
+(WRSR), raises a work-in-progress bit (WIP) on the status register.
+The datasheets for these devices specify that while the status
+register write is in progress, the status register WIP bit can still
+be read to check the end of the operation.
+
+This commit adds a wait_till_ready call on lock/unlock operations,
+which is required for Micron and Numonyx but should be harmless for
+others. This is needed to prevent applications from issuing erase or
+program operations before the unlock operation is completed.
+
+Reported-by: Stas Sergeev <stsp@list.ru>
+Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -481,6 +481,7 @@ static int stm_lock(struct spi_nor *nor,
+ int status_old, status_new;
+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
+ u8 shift = ffs(mask) - 1, pow, val;
++ int ret;
+
+ status_old = read_sr(nor);
+ if (status_old < 0)
+@@ -519,7 +520,10 @@ static int stm_lock(struct spi_nor *nor,
+ return -EINVAL;
+
+ write_enable(nor);
+- return write_sr(nor, status_new);
++ ret = write_sr(nor, status_new);
++ if (ret)
++ return ret;
++ return spi_nor_wait_till_ready(nor);
+ }
+
+ /*
+@@ -533,6 +537,7 @@ static int stm_unlock(struct spi_nor *no
+ int status_old, status_new;
+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
+ u8 shift = ffs(mask) - 1, pow, val;
++ int ret;
+
+ status_old = read_sr(nor);
+ if (status_old < 0)
+@@ -569,7 +574,10 @@ static int stm_unlock(struct spi_nor *no
+ return -EINVAL;
+
+ write_enable(nor);
+- return write_sr(nor, status_new);
++ ret = write_sr(nor, status_new);
++ if (ret)
++ return ret;
++ return spi_nor_wait_till_ready(nor);
+ }
+
+ /*
--- /dev/null
+From c58b398221d88ac0db29c3bb7522a4f48dfa102c Mon Sep 17 00:00:00 2001
+From: Yuan Yao <yao.yuan@freescale.com>
+Date: Tue, 17 Nov 2015 16:13:47 +0800
+Subject: [PATCH 087/113] mtd: spi-nor: fsl-quadspi: add big-endian support
+
+Add R/W functions for big- or little-endian registers:
+The qSPI controller's endian is independent of the CPU core's endian.
+So far, the qSPI have two versions for big-endian and little-endian.
+
+Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
+Acked-by: Han xu <han.xu@freescale.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 157 +++++++++++++++++++++++--------------
+ 1 file changed, 97 insertions(+), 60 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -275,6 +275,7 @@ struct fsl_qspi {
+ u32 clk_rate;
+ unsigned int chip_base_addr; /* We may support two chips. */
+ bool has_second_chip;
++ bool big_endian;
+ struct mutex lock;
+ struct pm_qos_request pm_qos_req;
+ };
+@@ -300,6 +301,28 @@ static inline int needs_wakeup_wait_mode
+ }
+
+ /*
++ * R/W functions for big- or little-endian registers:
++ * The qSPI controller's endian is independent of the CPU core's endian.
++ * So far, although the CPU core is little-endian but the qSPI have two
++ * versions for big-endian and little-endian.
++ */
++static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
++{
++ if (q->big_endian)
++ iowrite32be(val, addr);
++ else
++ iowrite32(val, addr);
++}
++
++static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
++{
++ if (q->big_endian)
++ return ioread32be(addr);
++ else
++ return ioread32(addr);
++}
++
++/*
+ * An IC bug makes us to re-arrange the 32-bit data.
+ * The following chips, such as IMX6SLX, have fixed this bug.
+ */
+@@ -310,14 +333,14 @@ static inline u32 fsl_qspi_endian_xchg(s
+
+ static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
+ {
+- writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+- writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
++ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
++ qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+ }
+
+ static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
+ {
+- writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+- writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
++ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
++ qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
+ }
+
+ static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
+@@ -326,8 +349,8 @@ static irqreturn_t fsl_qspi_irq_handler(
+ u32 reg;
+
+ /* clear interrupt */
+- reg = readl(q->iobase + QUADSPI_FR);
+- writel(reg, q->iobase + QUADSPI_FR);
++ reg = qspi_readl(q, q->iobase + QUADSPI_FR);
++ qspi_writel(q, reg, q->iobase + QUADSPI_FR);
+
+ if (reg & QUADSPI_FR_TFF_MASK)
+ complete(&q->c);
+@@ -348,7 +371,7 @@ static void fsl_qspi_init_lut(struct fsl
+
+ /* Clear all the LUT table */
+ for (i = 0; i < QUADSPI_LUT_NUM; i++)
+- writel(0, base + QUADSPI_LUT_BASE + i * 4);
++ qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
+
+ /* Quad Read */
+ lut_base = SEQID_QUAD_READ * 4;
+@@ -364,14 +387,15 @@ static void fsl_qspi_init_lut(struct fsl
+ dummy = 8;
+ }
+
+- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
++ qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+ base + QUADSPI_LUT(lut_base));
+- writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
++ qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
+ base + QUADSPI_LUT(lut_base + 1));
+
+ /* Write enable */
+ lut_base = SEQID_WREN * 4;
+- writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
++ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
++ base + QUADSPI_LUT(lut_base));
+
+ /* Page Program */
+ lut_base = SEQID_PP * 4;
+@@ -385,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl
+ addrlen = ADDR32BIT;
+ }
+
+- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
++ qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+ base + QUADSPI_LUT(lut_base));
+- writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
++ qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
++ base + QUADSPI_LUT(lut_base + 1));
+
+ /* Read Status */
+ lut_base = SEQID_RDSR * 4;
+- writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1),
++ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
++ LUT1(FSL_READ, PAD1, 0x1),
+ base + QUADSPI_LUT(lut_base));
+
+ /* Erase a sector */
+@@ -400,40 +426,46 @@ static void fsl_qspi_init_lut(struct fsl
+ cmd = q->nor[0].erase_opcode;
+ addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
+
+- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
++ qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+ base + QUADSPI_LUT(lut_base));
+
+ /* Erase the whole chip */
+ lut_base = SEQID_CHIP_ERASE * 4;
+- writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
++ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
+ base + QUADSPI_LUT(lut_base));
+
+ /* READ ID */
+ lut_base = SEQID_RDID * 4;
+- writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(FSL_READ, PAD1, 0x8),
++ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) |
++ LUT1(FSL_READ, PAD1, 0x8),
+ base + QUADSPI_LUT(lut_base));
+
+ /* Write Register */
+ lut_base = SEQID_WRSR * 4;
+- writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(FSL_WRITE, PAD1, 0x2),
++ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) |
++ LUT1(FSL_WRITE, PAD1, 0x2),
+ base + QUADSPI_LUT(lut_base));
+
+ /* Read Configuration Register */
+ lut_base = SEQID_RDCR * 4;
+- writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(FSL_READ, PAD1, 0x1),
++ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) |
++ LUT1(FSL_READ, PAD1, 0x1),
+ base + QUADSPI_LUT(lut_base));
+
+ /* Write disable */
+ lut_base = SEQID_WRDI * 4;
+- writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));
++ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI),
++ base + QUADSPI_LUT(lut_base));
+
+ /* Enter 4 Byte Mode (Micron) */
+ lut_base = SEQID_EN4B * 4;
+- writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));
++ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B),
++ base + QUADSPI_LUT(lut_base));
+
+ /* Enter 4 Byte Mode (Spansion) */
+ lut_base = SEQID_BRWR * 4;
+- writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));
++ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
++ base + QUADSPI_LUT(lut_base));
+
+ fsl_qspi_lock_lut(q);
+ }
+@@ -488,15 +520,16 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
+ q->chip_base_addr, addr, len, cmd);
+
+ /* save the reg */
+- reg = readl(base + QUADSPI_MCR);
++ reg = qspi_readl(q, base + QUADSPI_MCR);
+
+- writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR);
+- writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
++ qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
++ base + QUADSPI_SFAR);
++ qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
+ base + QUADSPI_RBCT);
+- writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
++ qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
+
+ do {
+- reg2 = readl(base + QUADSPI_SR);
++ reg2 = qspi_readl(q, base + QUADSPI_SR);
+ if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
+ udelay(1);
+ dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
+@@ -507,21 +540,22 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
+
+ /* trigger the LUT now */
+ seqid = fsl_qspi_get_seqid(q, cmd);
+- writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR);
++ qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
++ base + QUADSPI_IPCR);
+
+ /* Wait for the interrupt. */
+ if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
+ dev_err(q->dev,
+ "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
+- cmd, addr, readl(base + QUADSPI_FR),
+- readl(base + QUADSPI_SR));
++ cmd, addr, qspi_readl(q, base + QUADSPI_FR),
++ qspi_readl(q, base + QUADSPI_SR));
+ err = -ETIMEDOUT;
+ } else {
+ err = 0;
+ }
+
+ /* restore the MCR */
+- writel(reg, base + QUADSPI_MCR);
++ qspi_writel(q, reg, base + QUADSPI_MCR);
+
+ return err;
+ }
+@@ -533,7 +567,7 @@ static void fsl_qspi_read_data(struct fs
+ int i = 0;
+
+ while (len > 0) {
+- tmp = readl(q->iobase + QUADSPI_RBDR + i * 4);
++ tmp = qspi_readl(q, q->iobase + QUADSPI_RBDR + i * 4);
+ tmp = fsl_qspi_endian_xchg(q, tmp);
+ dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
+ q->chip_base_addr, tmp);
+@@ -561,9 +595,9 @@ static inline void fsl_qspi_invalid(stru
+ {
+ u32 reg;
+
+- reg = readl(q->iobase + QUADSPI_MCR);
++ reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
+ reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
+- writel(reg, q->iobase + QUADSPI_MCR);
++ qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
+
+ /*
+ * The minimum delay : 1 AHB + 2 SFCK clocks.
+@@ -572,7 +606,7 @@ static inline void fsl_qspi_invalid(stru
+ udelay(1);
+
+ reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
+- writel(reg, q->iobase + QUADSPI_MCR);
++ qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
+ }
+
+ static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
+@@ -586,20 +620,20 @@ static int fsl_qspi_nor_write(struct fsl
+ q->chip_base_addr, to, count);
+
+ /* clear the TX FIFO. */
+- tmp = readl(q->iobase + QUADSPI_MCR);
+- writel(tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
++ tmp = qspi_readl(q, q->iobase + QUADSPI_MCR);
++ qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
+
+ /* fill the TX data to the FIFO */
+ for (j = 0, i = ((count + 3) / 4); j < i; j++) {
+ tmp = fsl_qspi_endian_xchg(q, *txbuf);
+- writel(tmp, q->iobase + QUADSPI_TBDR);
++ qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
+ txbuf++;
+ }
+
+ /* fill the TXFIFO upto 16 bytes for i.MX7d */
+ if (needs_fill_txfifo(q))
+ for (; i < 4; i++)
+- writel(tmp, q->iobase + QUADSPI_TBDR);
++ qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
+
+ /* Trigger it */
+ ret = fsl_qspi_runcmd(q, opcode, to, count);
+@@ -615,10 +649,10 @@ static void fsl_qspi_set_map_addr(struct
+ int nor_size = q->nor_size;
+ void __iomem *base = q->iobase;
+
+- writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
+- writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
+- writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
+- writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
++ qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
++ qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
++ qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
++ qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
+ }
+
+ /*
+@@ -640,24 +674,26 @@ static void fsl_qspi_init_abh_read(struc
+ int seqid;
+
+ /* AHB configuration for access buffer 0/1/2 .*/
+- writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
+- writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
+- writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
++ qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
++ qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
++ qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
+ /*
+ * Set ADATSZ with the maximum AHB buffer size to improve the
+ * read performance.
+ */
+- writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8)
+- << QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR);
++ qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
++ ((q->devtype_data->ahb_buf_size / 8)
++ << QUADSPI_BUF3CR_ADATSZ_SHIFT),
++ base + QUADSPI_BUF3CR);
+
+ /* We only use the buffer3 */
+- writel(0, base + QUADSPI_BUF0IND);
+- writel(0, base + QUADSPI_BUF1IND);
+- writel(0, base + QUADSPI_BUF2IND);
++ qspi_writel(q, 0, base + QUADSPI_BUF0IND);
++ qspi_writel(q, 0, base + QUADSPI_BUF1IND);
++ qspi_writel(q, 0, base + QUADSPI_BUF2IND);
+
+ /* Set the default lut sequence for AHB Read. */
+ seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
+- writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
++ qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
+ q->iobase + QUADSPI_BFGENCR);
+ }
+
+@@ -713,7 +749,7 @@ static int fsl_qspi_nor_setup(struct fsl
+ return ret;
+
+ /* Reset the module */
+- writel(QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
++ qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
+ base + QUADSPI_MCR);
+ udelay(1);
+
+@@ -721,24 +757,24 @@ static int fsl_qspi_nor_setup(struct fsl
+ fsl_qspi_init_lut(q);
+
+ /* Disable the module */
+- writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
++ qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
+ base + QUADSPI_MCR);
+
+- reg = readl(base + QUADSPI_SMPR);
+- writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK
++ reg = qspi_readl(q, base + QUADSPI_SMPR);
++ qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
+ | QUADSPI_SMPR_FSPHS_MASK
+ | QUADSPI_SMPR_HSENA_MASK
+ | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
+
+ /* Enable the module */
+- writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
++ qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
+ base + QUADSPI_MCR);
+
+ /* clear all interrupt status */
+- writel(0xffffffff, q->iobase + QUADSPI_FR);
++ qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
+
+ /* enable the interrupt */
+- writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
++ qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
+
+ return 0;
+ }
+@@ -954,6 +990,7 @@ static int fsl_qspi_probe(struct platfor
+ if (IS_ERR(q->iobase))
+ return PTR_ERR(q->iobase);
+
++ q->big_endian = of_property_read_bool(np, "big-endian");
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "QuadSPI-memory");
+ if (!devm_request_mem_region(dev, res->start, resource_size(res),
+@@ -1101,8 +1138,8 @@ static int fsl_qspi_remove(struct platfo
+ }
+
+ /* disable the hardware */
+- writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
+- writel(0x0, q->iobase + QUADSPI_RSER);
++ qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
++ qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
+
+ mutex_destroy(&q->lock);
+
--- /dev/null
+From da44c1517526822e73642fc71b034de8fc7d2b43 Mon Sep 17 00:00:00 2001
+From: Yuan Yao <yao.yuan@freescale.com>
+Date: Tue, 17 Nov 2015 16:44:45 +0800
+Subject: [PATCH 088/113] mtd: spi-nor: fsl-quadspi: add support for ls1021a
+
+[context adjustment]
+
+LS1021a also support Freescale Quad SPI controller.
+Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI
+selectable for LS1021A SOC hardwares.
+
+Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
+Acked-by: Han xu <han.xu@freescale.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ drivers/mtd/spi-nor/Kconfig | 2 +-
+ drivers/mtd/spi-nor/fsl-quadspi.c | 10 ++++++++++
+ 2 files changed, 11 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/spi-nor/Kconfig
++++ b/drivers/mtd/spi-nor/Kconfig
+@@ -23,7 +23,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS
+
+ config SPI_FSL_QUADSPI
+ tristate "Freescale Quad SPI controller"
+- depends on ARCH_MXC || COMPILE_TEST
++ depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ This enables support for the Quad SPI controller in master mode.
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -213,6 +213,7 @@ enum fsl_qspi_devtype {
+ FSL_QUADSPI_IMX6SX,
+ FSL_QUADSPI_IMX7D,
+ FSL_QUADSPI_IMX6UL,
++ FSL_QUADSPI_LS1021A,
+ };
+
+ struct fsl_qspi_devtype_data {
+@@ -258,6 +259,14 @@ static struct fsl_qspi_devtype_data imx6
+ | QUADSPI_QUIRK_4X_INT_CLK,
+ };
+
++static struct fsl_qspi_devtype_data ls1021a_data = {
++ .devtype = FSL_QUADSPI_LS1021A,
++ .rxfifo = 128,
++ .txfifo = 64,
++ .ahb_buf_size = 1024,
++ .driver_data = 0,
++};
++
+ #define FSL_QSPI_MAX_CHIP 4
+ struct fsl_qspi {
+ struct spi_nor nor[FSL_QSPI_MAX_CHIP];
+@@ -812,6 +821,7 @@ static const struct of_device_id fsl_qsp
+ { .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
+ { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
+ { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
++ { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
+ { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
--- /dev/null
+From 9c6153130081ef2c109e2a243a598f2bc0dc6413 Mon Sep 17 00:00:00 2001
+From: Yuan Yao <yao.yuan@freescale.com>
+Date: Tue, 17 Nov 2015 17:06:47 +0800
+Subject: [PATCH 089/113] mtd: spi-nor: fsl-quadspi: add support for
+ layerscape
+
+[context adjustment]
+
+LS1043a and LS2080A in the Layerscape family also support Freescale Quad
+SPI, make Quad SPI selectable for these hardwares.
+
+Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ drivers/mtd/spi-nor/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mtd/spi-nor/Kconfig
++++ b/drivers/mtd/spi-nor/Kconfig
+@@ -23,7 +23,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS
+
+ config SPI_FSL_QUADSPI
+ tristate "Freescale Quad SPI controller"
+- depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST
++ depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ This enables support for the Quad SPI controller in master mode.
--- /dev/null
+From 2c5a3db21926e9ebfd7a32e3c36a3256ed84903c Mon Sep 17 00:00:00 2001
+From: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
+Date: Thu, 19 Nov 2015 20:25:24 +0800
+Subject: [PATCH 090/113] mtd: spi-nor: Add SPI NOR layer PM support
+
+[context adjustment]
+
+Add the Power Management API in SPI NOR framework.
+The Power Management system will turn off power supply to SPI flash
+when system suspending, and then the SPI flash will be in the reset
+state after system resuming. As a result, the status&configurations
+of SPI flash driver will mismatch with its current hardware state.
+So reinitialize SPI flash to make sure it is resumed to the correct
+state.
+And the SPI NOR layer just do common configuration depending on the
+records in structure spi_nor.
+
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 74 ++++++++++++++++++++++++++++++++++-------
+ include/linux/mtd/spi-nor.h | 9 +++++
+ 2 files changed, 71 insertions(+), 12 deletions(-)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -1139,6 +1139,26 @@ static int spi_nor_check(struct spi_nor
+ return 0;
+ }
+
++/*
++ * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
++ * with the software protection bits set
++ */
++static int spi_nor_unprotect_on_powerup(struct spi_nor *nor)
++{
++ const struct flash_info *info = NULL;
++ int ret = 0;
++
++ info = spi_nor_read_id(nor);
++ if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
++ JEDEC_MFR(info) == SNOR_MFR_INTEL ||
++ JEDEC_MFR(info) == SNOR_MFR_SST) {
++ write_enable(nor);
++ ret = write_sr(nor, 0);
++ }
++
++ return ret;
++}
++
+ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
+ {
+ const struct flash_info *info = NULL;
+@@ -1186,18 +1206,9 @@ int spi_nor_scan(struct spi_nor *nor, co
+
+ mutex_init(&nor->lock);
+
+- /*
+- * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
+- * with the software protection bits set
+- */
+-
+- if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
+- JEDEC_MFR(info) == SNOR_MFR_INTEL ||
+- JEDEC_MFR(info) == SNOR_MFR_MACRONIX ||
+- JEDEC_MFR(info) == SNOR_MFR_SST) {
+- write_enable(nor);
+- write_sr(nor, 0);
+- }
++ ret = spi_nor_unprotect_on_powerup(nor);
++ if (ret)
++ return ret;
+
+ if (!mtd->name)
+ mtd->name = dev_name(dev);
+@@ -1363,6 +1374,45 @@ int spi_nor_scan(struct spi_nor *nor, co
+ }
+ EXPORT_SYMBOL_GPL(spi_nor_scan);
+
++static int spi_nor_hw_reinit(struct spi_nor *nor)
++{
++ const struct flash_info *info = NULL;
++ struct device *dev = nor->dev;
++ int ret;
++
++ info = spi_nor_read_id(nor);
++
++ ret = spi_nor_unprotect_on_powerup(nor);
++ if (ret)
++ return ret;
++
++ if (nor->flash_read == SPI_NOR_QUAD) {
++ ret = set_quad_mode(nor, info);
++ if (ret) {
++ dev_err(dev, "quad mode not supported\n");
++ return ret;
++ }
++ }
++
++ if (nor->addr_width == 4 &&
++ JEDEC_MFR(info) != SNOR_MFR_SPANSION)
++ set_4byte(nor, info, 1);
++
++ return 0;
++}
++
++int spi_nor_suspend(struct spi_nor *nor)
++{
++ return 0;
++}
++EXPORT_SYMBOL_GPL(spi_nor_suspend);
++
++int spi_nor_resume(struct spi_nor *nor)
++{
++ return spi_nor_hw_reinit(nor);
++}
++EXPORT_SYMBOL_GPL(spi_nor_resume);
++
+ static const struct flash_info *spi_nor_match_id(const char *name)
+ {
+ const struct flash_info *id = spi_nor_ids;
+--- a/include/linux/mtd/spi-nor.h
++++ b/include/linux/mtd/spi-nor.h
+@@ -210,4 +210,13 @@ static inline struct device_node *spi_no
+ */
+ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode);
+
++/**
++ * spi_nor_suspend/resume() - the SPI NOR layer PM API
++ * @nor: the spi_nor structure
++ *
++ * Return: 0 for success, others for failure.
++ */
++int spi_nor_suspend(struct spi_nor *nor);
++int spi_nor_resume(struct spi_nor *nor);
++
+ #endif
--- /dev/null
+From 0a8079b232e9188ba267e37e20f192bed6c2b29b Mon Sep 17 00:00:00 2001
+From: Michal Suchanek <hramrach@gmail.com>
+Date: Wed, 2 Dec 2015 10:38:19 +0000
+Subject: [PATCH 091/113] mtd: spi-nor: change return value of read/write
+
+Change the return value of spi-nor device read and write methods to
+allow returning amount of data transferred and errors as
+read(2)/write(2) does.
+
+Signed-off-by: Michal Suchanek <hramrach@gmail.com>
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
+---
+ drivers/mtd/devices/m25p80.c | 5 +++--
+ drivers/mtd/spi-nor/fsl-quadspi.c | 5 +++--
+ include/linux/mtd/spi-nor.h | 4 ++--
+ 3 files changed, 8 insertions(+), 6 deletions(-)
+
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -73,7 +73,7 @@ static int m25p80_write_reg(struct spi_n
+ return spi_write(spi, flash->command, len + 1);
+ }
+
+-static void m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
++static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+ {
+ struct m25p *flash = nor->priv;
+@@ -101,6 +101,7 @@ static void m25p80_write(struct spi_nor
+ spi_sync(spi, &m);
+
+ *retlen += m.actual_length - cmd_sz;
++ return 0;
+ }
+
+ static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor)
+@@ -119,7 +120,7 @@ static inline unsigned int m25p80_rx_nbi
+ * Read an address range from the nor chip. The address range
+ * may be any size provided it is within the physical boundaries.
+ */
+-static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
++static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+ {
+ struct m25p *flash = nor->priv;
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -868,7 +868,7 @@ static int fsl_qspi_write_reg(struct spi
+ return ret;
+ }
+
+-static void fsl_qspi_write(struct spi_nor *nor, loff_t to,
++static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to,
+ size_t len, size_t *retlen, const u_char *buf)
+ {
+ struct fsl_qspi *q = nor->priv;
+@@ -878,9 +878,10 @@ static void fsl_qspi_write(struct spi_no
+
+ /* invalid the data in the AHB buffer. */
+ fsl_qspi_invalid(q);
++ return 0;
+ }
+
+-static int fsl_qspi_read(struct spi_nor *nor, loff_t from,
++static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
+ size_t len, size_t *retlen, u_char *buf)
+ {
+ struct fsl_qspi *q = nor->priv;
+--- a/include/linux/mtd/spi-nor.h
++++ b/include/linux/mtd/spi-nor.h
+@@ -170,9 +170,9 @@ struct spi_nor {
+ int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
+ int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
+
+- int (*read)(struct spi_nor *nor, loff_t from,
++ ssize_t (*read)(struct spi_nor *nor, loff_t from,
+ size_t len, size_t *retlen, u_char *read_buf);
+- void (*write)(struct spi_nor *nor, loff_t to,
++ ssize_t (*write)(struct spi_nor *nor, loff_t to,
+ size_t len, size_t *retlen, const u_char *write_buf);
+ int (*erase)(struct spi_nor *nor, loff_t offs);
+
--- /dev/null
+From 99768b3062501b05810fb62545279da3a4371ca0 Mon Sep 17 00:00:00 2001
+From: Michal Suchanek <hramrach@gmail.com>
+Date: Wed, 2 Dec 2015 10:38:19 +0000
+Subject: [PATCH 092/113] mtd: fsl-quadspi: return amount of data read/written
+ or error
+
+Return amount of data read/written or error as read(2)/write(2) does.
+
+Signed-off-by: Michal Suchanek <hramrach@gmail.com>
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 18 +++++++++++-------
+ 1 file changed, 11 insertions(+), 7 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -618,7 +618,7 @@ static inline void fsl_qspi_invalid(stru
+ qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
+ }
+
+-static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
++static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
+ u8 opcode, unsigned int to, u32 *txbuf,
+ unsigned count, size_t *retlen)
+ {
+@@ -647,8 +647,11 @@ static int fsl_qspi_nor_write(struct fsl
+ /* Trigger it */
+ ret = fsl_qspi_runcmd(q, opcode, to, count);
+
+- if (ret == 0 && retlen)
+- *retlen += count;
++ if (ret == 0) {
++ if (retlen)
++ *retlen += count;
++ return count;
++ }
+
+ return ret;
+ }
+@@ -860,6 +863,8 @@ static int fsl_qspi_write_reg(struct spi
+ } else if (len > 0) {
+ ret = fsl_qspi_nor_write(q, nor, opcode, 0,
+ (u32 *)buf, len, NULL);
++ if (ret > 0)
++ return 0;
+ } else {
+ dev_err(q->dev, "invalid cmd %d\n", opcode);
+ ret = -EINVAL;
+@@ -873,12 +878,12 @@ static ssize_t fsl_qspi_write(struct spi
+ {
+ struct fsl_qspi *q = nor->priv;
+
+- fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
++ ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
+ (u32 *)buf, len, retlen);
+
+ /* invalid the data in the AHB buffer. */
+ fsl_qspi_invalid(q);
+- return 0;
++ return ret;
+ }
+
+ static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
+@@ -924,8 +929,7 @@ static ssize_t fsl_qspi_read(struct spi_
+ memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
+ len);
+
+- *retlen += len;
+- return 0;
++ return len;
+ }
+
+ static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
--- /dev/null
+From 8527843351169d999995d331bbdad75560ccafb2 Mon Sep 17 00:00:00 2001
+From: Michal Suchanek <hramrach@gmail.com>
+Date: Wed, 2 Dec 2015 10:38:20 +0000
+Subject: [PATCH 093/113] mtd: spi-nor: check return value from read/write
+
+SPI NOR hardware drivers now return useful value from their read/write
+functions so check them.
+
+Signed-off-by: Michal Suchanek <hramrach@gmail.com>
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 50 +++++++++++++++++++++++++++++------------
+ 1 file changed, 36 insertions(+), 14 deletions(-)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -922,7 +922,10 @@ static int spi_nor_read(struct mtd_info
+ ret = nor->read(nor, from, len, retlen, buf);
+
+ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
+- return ret;
++ if (ret < 0)
++ return ret;
++
++ return 0;
+ }
+
+ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
+@@ -948,10 +951,14 @@ static int sst_write(struct mtd_info *mt
+ nor->program_opcode = SPINOR_OP_BP;
+
+ /* write one byte. */
+- nor->write(nor, to, 1, retlen, buf);
++ ret = nor->write(nor, to, 1, retlen, buf);
++ if (ret < 0)
++ goto sst_write_err;
++ WARN(ret != 1, "While writing 1 byte written %i bytes\n",
++ (int)ret);
+ ret = spi_nor_wait_till_ready(nor);
+ if (ret)
+- goto time_out;
++ goto sst_write_err;
+ }
+ to += actual;
+
+@@ -960,10 +967,14 @@ static int sst_write(struct mtd_info *mt
+ nor->program_opcode = SPINOR_OP_AAI_WP;
+
+ /* write two bytes. */
+- nor->write(nor, to, 2, retlen, buf + actual);
++ ret = nor->write(nor, to, 2, retlen, buf + actual);
++ if (ret < 0)
++ goto sst_write_err;
++ WARN(ret != 2, "While writing 2 bytes written %i bytes\n",
++ (int)ret);
+ ret = spi_nor_wait_till_ready(nor);
+ if (ret)
+- goto time_out;
++ goto sst_write_err;
+ to += 2;
+ nor->sst_write_second = true;
+ }
+@@ -972,21 +983,24 @@ static int sst_write(struct mtd_info *mt
+ write_disable(nor);
+ ret = spi_nor_wait_till_ready(nor);
+ if (ret)
+- goto time_out;
++ goto sst_write_err;
+
+ /* Write out trailing byte if it exists. */
+ if (actual != len) {
+ write_enable(nor);
+
+ nor->program_opcode = SPINOR_OP_BP;
+- nor->write(nor, to, 1, retlen, buf + actual);
+-
++ ret = nor->write(nor, to, 1, retlen, buf + actual);
++ if (ret < 0)
++ goto sst_write_err;
++ WARN(ret != 1, "While writing 1 byte written %i bytes\n",
++ (int)ret);
+ ret = spi_nor_wait_till_ready(nor);
+ if (ret)
+- goto time_out;
++ goto sst_write_err;
+ write_disable(nor);
+ }
+-time_out:
++sst_write_err:
+ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
+ return ret;
+ }
+@@ -1015,14 +1029,18 @@ static int spi_nor_write(struct mtd_info
+
+ /* do all the bytes fit onto one page? */
+ if (page_offset + len <= nor->page_size) {
+- nor->write(nor, to, len, retlen, buf);
++ ret = nor->write(nor, to, len, retlen, buf);
++ if (ret < 0)
++ goto write_err;
+ } else {
+ /* the size of data remaining on the first page */
+ page_size = nor->page_size - page_offset;
+- nor->write(nor, to, page_size, retlen, buf);
++ ret = nor->write(nor, to, page_size, retlen, buf);
++ if (ret < 0)
++ goto write_err;
+
+ /* write everything in nor->page_size chunks */
+- for (i = page_size; i < len; i += page_size) {
++ for (i = ret; i < len; ) {
+ page_size = len - i;
+ if (page_size > nor->page_size)
+ page_size = nor->page_size;
+@@ -1033,7 +1051,11 @@ static int spi_nor_write(struct mtd_info
+
+ write_enable(nor);
+
+- nor->write(nor, to + i, page_size, retlen, buf + i);
++ ret = nor->write(nor, to + i, page_size, retlen,
++ buf + i);
++ if (ret < 0)
++ goto write_err;
++ i += ret;
+ }
+ }
+
--- /dev/null
+From a99477d72b500b48cb3614aad0ce096fe4e3f437 Mon Sep 17 00:00:00 2001
+From: Michal Suchanek <hramrach@gmail.com>
+Date: Wed, 2 Dec 2015 10:38:20 +0000
+Subject: [PATCH 094/113] mtd: spi-nor: stop passing around retlen
+
+[context adjustment]
+not apply changes of drivers/mtd/devices/m25p80.c
+#################
+@@ -74,7 +74,7 @@ static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+ }
+
+ static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
+- size_t *retlen, const u_char *buf)
++ const u_char *buf)
+ {
+ struct m25p *flash = nor->priv;
+ struct spi_device *spi = flash->spi;
+@@ -106,7 +106,6 @@ static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
+ ret = m.actual_length - cmd_sz;
+ if (ret < 0)
+ return -EIO;
+- *retlen += ret;
+ return ret;
+ }
+
+@@ -127,7 +126,7 @@ static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor)
+ * may be any size provided it is within the physical boundaries.
+ */
+ static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
+- size_t *retlen, u_char *buf)
++ u_char *buf)
+ {
+ struct m25p *flash = nor->priv;
+ struct spi_device *spi = flash->spi;
+@@ -161,7 +160,6 @@ static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
+ ret = m.actual_length - m25p_cmdsz(nor) - dummy;
+ if (ret < 0)
+ return -EIO;
+- *retlen += ret;
+ return ret;
+ }
+
+#################
+
+Do not pass retlen to hardware driver read/write functions. Update it in
+spi-nor generic driver instead.
+
+Signed-off-by: Michal Suchanek <hramrach@gmail.com>
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 16 ++++++----------
+ drivers/mtd/spi-nor/spi-nor.c | 21 +++++++++++++--------
+ include/linux/mtd/spi-nor.h | 4 ++--
+ 3 files changed, 21 insertions(+), 20 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -620,7 +620,7 @@ static inline void fsl_qspi_invalid(stru
+
+ static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
+ u8 opcode, unsigned int to, u32 *txbuf,
+- unsigned count, size_t *retlen)
++ unsigned count)
+ {
+ int ret, i, j;
+ u32 tmp;
+@@ -647,11 +647,8 @@ static ssize_t fsl_qspi_nor_write(struct
+ /* Trigger it */
+ ret = fsl_qspi_runcmd(q, opcode, to, count);
+
+- if (ret == 0) {
+- if (retlen)
+- *retlen += count;
++ if (ret == 0)
+ return count;
+- }
+
+ return ret;
+ }
+@@ -862,7 +859,7 @@ static int fsl_qspi_write_reg(struct spi
+
+ } else if (len > 0) {
+ ret = fsl_qspi_nor_write(q, nor, opcode, 0,
+- (u32 *)buf, len, NULL);
++ (u32 *)buf, len);
+ if (ret > 0)
+ return 0;
+ } else {
+@@ -874,12 +871,11 @@ static int fsl_qspi_write_reg(struct spi
+ }
+
+ static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to,
+- size_t len, size_t *retlen, const u_char *buf)
++ size_t len, const u_char *buf)
+ {
+ struct fsl_qspi *q = nor->priv;
+-
+ ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
+- (u32 *)buf, len, retlen);
++ (u32 *)buf, len);
+
+ /* invalid the data in the AHB buffer. */
+ fsl_qspi_invalid(q);
+@@ -887,7 +883,7 @@ static ssize_t fsl_qspi_write(struct spi
+ }
+
+ static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
+- size_t len, size_t *retlen, u_char *buf)
++ size_t len, u_char *buf)
+ {
+ struct fsl_qspi *q = nor->priv;
+ u8 cmd = nor->read_opcode;
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -919,12 +919,13 @@ static int spi_nor_read(struct mtd_info
+ if (ret)
+ return ret;
+
+- ret = nor->read(nor, from, len, retlen, buf);
++ ret = nor->read(nor, from, len, buf);
+
+ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
+ if (ret < 0)
+ return ret;
+
++ *retlen += ret;
+ return 0;
+ }
+
+@@ -951,7 +952,7 @@ static int sst_write(struct mtd_info *mt
+ nor->program_opcode = SPINOR_OP_BP;
+
+ /* write one byte. */
+- ret = nor->write(nor, to, 1, retlen, buf);
++ ret = nor->write(nor, to, 1, buf);
+ if (ret < 0)
+ goto sst_write_err;
+ WARN(ret != 1, "While writing 1 byte written %i bytes\n",
+@@ -967,7 +968,7 @@ static int sst_write(struct mtd_info *mt
+ nor->program_opcode = SPINOR_OP_AAI_WP;
+
+ /* write two bytes. */
+- ret = nor->write(nor, to, 2, retlen, buf + actual);
++ ret = nor->write(nor, to, 2, buf + actual);
+ if (ret < 0)
+ goto sst_write_err;
+ WARN(ret != 2, "While writing 2 bytes written %i bytes\n",
+@@ -990,7 +991,7 @@ static int sst_write(struct mtd_info *mt
+ write_enable(nor);
+
+ nor->program_opcode = SPINOR_OP_BP;
+- ret = nor->write(nor, to, 1, retlen, buf + actual);
++ ret = nor->write(nor, to, 1, buf + actual);
+ if (ret < 0)
+ goto sst_write_err;
+ WARN(ret != 1, "While writing 1 byte written %i bytes\n",
+@@ -999,8 +1000,10 @@ static int sst_write(struct mtd_info *mt
+ if (ret)
+ goto sst_write_err;
+ write_disable(nor);
++ actual += 1;
+ }
+ sst_write_err:
++ *retlen += actual;
+ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
+ return ret;
+ }
+@@ -1029,15 +1032,17 @@ static int spi_nor_write(struct mtd_info
+
+ /* do all the bytes fit onto one page? */
+ if (page_offset + len <= nor->page_size) {
+- ret = nor->write(nor, to, len, retlen, buf);
++ ret = nor->write(nor, to, len, buf);
+ if (ret < 0)
+ goto write_err;
++ *retlen += ret;
+ } else {
+ /* the size of data remaining on the first page */
+ page_size = nor->page_size - page_offset;
+- ret = nor->write(nor, to, page_size, retlen, buf);
++ ret = nor->write(nor, to, page_size, buf);
+ if (ret < 0)
+ goto write_err;
++ *retlen += ret;
+
+ /* write everything in nor->page_size chunks */
+ for (i = ret; i < len; ) {
+@@ -1051,10 +1056,10 @@ static int spi_nor_write(struct mtd_info
+
+ write_enable(nor);
+
+- ret = nor->write(nor, to + i, page_size, retlen,
+- buf + i);
++ ret = nor->write(nor, to + i, page_size, buf + i);
+ if (ret < 0)
+ goto write_err;
++ *retlen += ret;
+ i += ret;
+ }
+ }
+--- a/include/linux/mtd/spi-nor.h
++++ b/include/linux/mtd/spi-nor.h
+@@ -171,9 +171,9 @@ struct spi_nor {
+ int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
+
+ ssize_t (*read)(struct spi_nor *nor, loff_t from,
+- size_t len, size_t *retlen, u_char *read_buf);
++ size_t len, u_char *read_buf);
+ ssize_t (*write)(struct spi_nor *nor, loff_t to,
+- size_t len, size_t *retlen, const u_char *write_buf);
++ size_t len, const u_char *write_buf);
+ int (*erase)(struct spi_nor *nor, loff_t offs);
+
+ int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
--- /dev/null
+From 93b40e12f7e580a41c4aee5597579cc539fd8544 Mon Sep 17 00:00:00 2001
+From: Michal Suchanek <hramrach@gmail.com>
+Date: Wed, 2 Dec 2015 10:38:20 +0000
+Subject: [PATCH 095/113] mtd: spi-nor: simplify write loop
+
+The spi-nor write loop assumes that what is passed to the hardware
+driver write() is what gets written.
+
+When write() writes less than page size at once data is dropped on the
+floor. Check the amount of data writen and exit if it does not match
+requested amount.
+
+Signed-off-by: Michal Suchanek <hramrach@gmail.com>
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 58 ++++++++++++++++++-----------------------
+ 1 file changed, 25 insertions(+), 33 deletions(-)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -1017,8 +1017,8 @@ static int spi_nor_write(struct mtd_info
+ size_t *retlen, const u_char *buf)
+ {
+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
+- u32 page_offset, page_size, i;
+- int ret;
++ size_t page_offset, page_remain, i;
++ ssize_t ret;
+
+ dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
+
+@@ -1026,45 +1026,37 @@ static int spi_nor_write(struct mtd_info
+ if (ret)
+ return ret;
+
+- write_enable(nor);
++ for (i = 0; i < len; ) {
++ ssize_t written;
+
+- page_offset = to & (nor->page_size - 1);
+-
+- /* do all the bytes fit onto one page? */
+- if (page_offset + len <= nor->page_size) {
+- ret = nor->write(nor, to, len, buf);
+- if (ret < 0)
+- goto write_err;
+- *retlen += ret;
+- } else {
++ page_offset = to & (nor->page_size - 1);
++ WARN_ONCE(page_offset,
++ "Writing at offset %zu into a NOR page. Writing partial pages may decrease reliability and increase wear of NOR flash.",
++ page_offset);
+ /* the size of data remaining on the first page */
+- page_size = nor->page_size - page_offset;
+- ret = nor->write(nor, to, page_size, buf);
++ page_remain = min_t(size_t,
++ nor->page_size - page_offset, len - i);
++
++ write_enable(nor);
++ ret = nor->write(nor, to + i, page_remain, buf + i);
+ if (ret < 0)
+ goto write_err;
+- *retlen += ret;
++ written = ret;
+
+- /* write everything in nor->page_size chunks */
+- for (i = ret; i < len; ) {
+- page_size = len - i;
+- if (page_size > nor->page_size)
+- page_size = nor->page_size;
+-
+- ret = spi_nor_wait_till_ready(nor);
+- if (ret)
+- goto write_err;
+-
+- write_enable(nor);
+-
+- ret = nor->write(nor, to + i, page_size, buf + i);
+- if (ret < 0)
+- goto write_err;
+- *retlen += ret;
+- i += ret;
++ ret = spi_nor_wait_till_ready(nor);
++ if (ret)
++ goto write_err;
++ *retlen += written;
++ i += written;
++ if (written != page_remain) {
++ dev_err(nor->dev,
++ "While writing %zu bytes written %zd bytes\n",
++ page_remain, written);
++ ret = -EIO;
++ goto write_err;
+ }
+ }
+
+- ret = spi_nor_wait_till_ready(nor);
+ write_err:
+ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
+ return ret;
--- /dev/null
+From b5929f91416d64afacf46c649f38cc8f0eea50d2 Mon Sep 17 00:00:00 2001
+From: Michal Suchanek <hramrach@gmail.com>
+Date: Wed, 2 Dec 2015 10:38:20 +0000
+Subject: [PATCH 096/113] mtd: spi-nor: add read loop
+
+mtdblock and ubi do not handle the situation when read returns less data
+than requested. Loop in spi-nor until buffer is filled or an error is
+returned.
+
+Signed-off-by: Michal Suchanek <hramrach@gmail.com>
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 20 ++++++++++++++------
+ 1 file changed, 14 insertions(+), 6 deletions(-)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -919,14 +919,22 @@ static int spi_nor_read(struct mtd_info
+ if (ret)
+ return ret;
+
+- ret = nor->read(nor, from, len, buf);
++ while (len) {
++ ret = nor->read(nor, from, len, buf);
++ if (ret <= 0)
++ goto read_err;
+
+- spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
+- if (ret < 0)
+- return ret;
++ WARN_ON(ret > len);
++ *retlen += ret;
++ buf += ret;
++ from += ret;
++ len -= ret;
++ }
++ ret = 0;
+
+- *retlen += ret;
+- return 0;
++read_err:
++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
++ return ret;
+ }
+
+ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
--- /dev/null
+From 5c315652c1b43a6a3abe48c2842cde822ac0ff3c Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <B56489@freescale.com>
+Date: Wed, 20 Jan 2016 18:40:31 +0800
+Subject: [PATCH 097/113] mtd:fsl-quadspi:use the property fields of SPI-NOR
+
+We can get the read/write/erase opcode from the spi nor framework
+directly. This patch uses the information stored in the SPI-NOR to
+remove the hardcode in the fsl_qspi_init_lut().
+
+Signed-off-by: Yunhui Cui <B56489@freescale.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 40 +++++++++++--------------------------
+ 1 file changed, 12 insertions(+), 28 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl
+ void __iomem *base = q->iobase;
+ int rxfifo = q->devtype_data->rxfifo;
+ u32 lut_base;
+- u8 cmd, addrlen, dummy;
+ int i;
+
++ struct spi_nor *nor = &q->nor[0];
++ u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
++ u8 read_op = nor->read_opcode;
++ u8 read_dm = nor->read_dummy;
++
+ fsl_qspi_unlock_lut(q);
+
+ /* Clear all the LUT table */
+@@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl
+ /* Quad Read */
+ lut_base = SEQID_QUAD_READ * 4;
+
+- if (q->nor_size <= SZ_16M) {
+- cmd = SPINOR_OP_READ_1_1_4;
+- addrlen = ADDR24BIT;
+- dummy = 8;
+- } else {
+- /* use the 4-byte address */
+- cmd = SPINOR_OP_READ_1_1_4;
+- addrlen = ADDR32BIT;
+- dummy = 8;
+- }
+-
+- qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
++ qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
+ base + QUADSPI_LUT(lut_base));
+- qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
++ qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
++ LUT1(FSL_READ, PAD4, rxfifo),
+ base + QUADSPI_LUT(lut_base + 1));
+
+ /* Write enable */
+@@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl
+ /* Page Program */
+ lut_base = SEQID_PP * 4;
+
+- if (q->nor_size <= SZ_16M) {
+- cmd = SPINOR_OP_PP;
+- addrlen = ADDR24BIT;
+- } else {
+- /* use the 4-byte address */
+- cmd = SPINOR_OP_PP;
+- addrlen = ADDR32BIT;
+- }
+-
+- qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
++ qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
++ LUT1(ADDR, PAD1, addrlen),
+ base + QUADSPI_LUT(lut_base));
+ qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
+ base + QUADSPI_LUT(lut_base + 1));
+@@ -432,10 +418,8 @@ static void fsl_qspi_init_lut(struct fsl
+ /* Erase a sector */
+ lut_base = SEQID_SE * 4;
+
+- cmd = q->nor[0].erase_opcode;
+- addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
+-
+- qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
++ qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
++ LUT1(ADDR, PAD1, addrlen),
+ base + QUADSPI_LUT(lut_base));
+
+ /* Erase the whole chip */
--- /dev/null
+From c8f9be7df954fce18e96074af3f07aa5f75399e0 Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <B56489@freescale.com>
+Date: Wed, 20 Jan 2016 15:52:25 +0800
+Subject: [PATCH 098/113] mtd: fsl-quadspi: Rename SEQID_QUAD_READ to
+ SEQID_READ
+
+There are some read modes for flash, such as NORMAL, FAST,
+QUAD, DDR QUAD. These modes will use the identical lut table base
+So rename SEQID_QUAD_READ to SEQID_READ.
+
+Signed-off-by: Yunhui Cui <B56489@freescale.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -193,7 +193,7 @@
+ #define QUADSPI_LUT_NUM 64
+
+ /* SEQID -- we can have 16 seqids at most. */
+-#define SEQID_QUAD_READ 0
++#define SEQID_READ 0
+ #define SEQID_WREN 1
+ #define SEQID_WRDI 2
+ #define SEQID_RDSR 3
+@@ -386,8 +386,8 @@ static void fsl_qspi_init_lut(struct fsl
+ for (i = 0; i < QUADSPI_LUT_NUM; i++)
+ qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
+
+- /* Quad Read */
+- lut_base = SEQID_QUAD_READ * 4;
++ /* Read */
++ lut_base = SEQID_READ * 4;
+
+ qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
+ base + QUADSPI_LUT(lut_base));
+@@ -468,7 +468,7 @@ static int fsl_qspi_get_seqid(struct fsl
+ {
+ switch (cmd) {
+ case SPINOR_OP_READ_1_1_4:
+- return SEQID_QUAD_READ;
++ return SEQID_READ;
+ case SPINOR_OP_WREN:
+ return SEQID_WREN;
+ case SPINOR_OP_WRDI:
--- /dev/null
+From c501cdf57682265b72a8180c06e4a01dc2978375 Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <B56489@freescale.com>
+Date: Mon, 1 Feb 2016 18:26:23 +0800
+Subject: [PATCH 099/113] mtd:spi-nor:fsl-quadspi:Add fast-read mode support
+
+The qspi driver add generic fast-read mode for different
+flash venders. There are some different board flash work on
+different mode, such fast-read, quad-mode.
+So we have to modify the third entrace parameter of spi_nor_scan().
+
+Signed-off-by: Yunhui Cui <B56489@freescale.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 27 +++++++++++++++++++++------
+ 1 file changed, 21 insertions(+), 6 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -389,11 +389,21 @@ static void fsl_qspi_init_lut(struct fsl
+ /* Read */
+ lut_base = SEQID_READ * 4;
+
+- qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
+- base + QUADSPI_LUT(lut_base));
+- qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
+- LUT1(FSL_READ, PAD4, rxfifo),
+- base + QUADSPI_LUT(lut_base + 1));
++ if (nor->flash_read == SPI_NOR_FAST) {
++ qspi_writel(q, LUT0(CMD, PAD1, read_op) |
++ LUT1(ADDR, PAD1, addrlen),
++ base + QUADSPI_LUT(lut_base));
++ qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
++ LUT1(FSL_READ, PAD1, rxfifo),
++ base + QUADSPI_LUT(lut_base + 1));
++ } else if (nor->flash_read == SPI_NOR_QUAD) {
++ qspi_writel(q, LUT0(CMD, PAD1, read_op) |
++ LUT1(ADDR, PAD1, addrlen),
++ base + QUADSPI_LUT(lut_base));
++ qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
++ LUT1(FSL_READ, PAD4, rxfifo),
++ base + QUADSPI_LUT(lut_base + 1));
++ }
+
+ /* Write enable */
+ lut_base = SEQID_WREN * 4;
+@@ -468,6 +478,7 @@ static int fsl_qspi_get_seqid(struct fsl
+ {
+ switch (cmd) {
+ case SPINOR_OP_READ_1_1_4:
++ case SPINOR_OP_READ_FAST:
+ return SEQID_READ;
+ case SPINOR_OP_WREN:
+ return SEQID_WREN;
+@@ -964,6 +975,7 @@ static int fsl_qspi_probe(struct platfor
+ struct spi_nor *nor;
+ struct mtd_info *mtd;
+ int ret, i = 0;
++ enum read_mode mode = SPI_NOR_QUAD;
+
+ q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
+ if (!q)
+@@ -1065,7 +1077,10 @@ static int fsl_qspi_probe(struct platfor
+ /* set the chip address for READID */
+ fsl_qspi_set_base_addr(q, nor);
+
+- ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
++ ret = of_property_read_bool(np, "m25p,fast-read");
++ mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD;
++
++ ret = spi_nor_scan(nor, NULL, mode);
+ if (ret)
+ goto mutex_failed;
+
--- /dev/null
+From e892dea7229d56b75c46a76b9039f9e179584a91 Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <B56489@freescale.com>
+Date: Mon, 1 Feb 2016 18:48:49 +0800
+Subject: [PATCH 100/113] mtd:spi_nor: Disable Micron flash HW protection
+
+For Micron family ,The status register write enable/disable bit,
+provides hardware data protection for the device.
+When the enable/disable bit is set to 1, the status register
+nonvolatile bits become read-only and the WRITE STATUS REGISTER
+operation will not execute.
+
+Signed-off-by: Yunhui Cui <B56489@freescale.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -39,6 +39,7 @@
+
+ #define SPI_NOR_MAX_ID_LEN 6
+ #define SPI_NOR_MAX_ADDR_WIDTH 4
++#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f
+
+ struct flash_info {
+ char *name;
+@@ -1237,6 +1238,14 @@ int spi_nor_scan(struct spi_nor *nor, co
+ if (ret)
+ return ret;
+
++ if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
++ ret = read_sr(nor);
++ ret &= SPI_NOR_MICRON_WRITE_ENABLE;
++
++ write_enable(nor);
++ write_sr(nor, ret);
++ }
++
+ if (!mtd->name)
+ mtd->name = dev_name(dev);
+ mtd->priv = nor;
--- /dev/null
+From acfc6e9b34b3b3ca0d8bbe366dd08b0fac21c740 Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Tue, 2 Feb 2016 12:21:12 +0800
+Subject: [PATCH 101/113] mtd: spi-nor: fsl-quadspi: extend support for some
+ special requerment.
+
+Add extra info in LUT table to support some special requerments.
+Spansion S25FS-S family flash need some special operations.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 44 +++++++++++++++++++++++++++++++++++--
+ include/linux/mtd/spi-nor.h | 4 ++++
+ 2 files changed, 46 insertions(+), 2 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -205,6 +205,9 @@
+ #define SEQID_RDCR 9
+ #define SEQID_EN4B 10
+ #define SEQID_BRWR 11
++#define SEQID_RDAR 12
++#define SEQID_WRAR 13
++
+
+ #define QUADSPI_MIN_IOMAP SZ_4M
+
+@@ -470,6 +473,28 @@ static void fsl_qspi_init_lut(struct fsl
+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
+ base + QUADSPI_LUT(lut_base));
+
++ /*
++ * Read any device register.
++ * Used for Spansion S25FS-S family flash only.
++ */
++ lut_base = SEQID_RDAR * 4;
++ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
++ LUT1(ADDR, PAD1, ADDR24BIT),
++ base + QUADSPI_LUT(lut_base));
++ qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
++ base + QUADSPI_LUT(lut_base + 1));
++
++ /*
++ * Write any device register.
++ * Used for Spansion S25FS-S family flash only.
++ */
++ lut_base = SEQID_WRAR * 4;
++ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_WRAR) |
++ LUT1(ADDR, PAD1, ADDR24BIT),
++ base + QUADSPI_LUT(lut_base));
++ qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
++ base + QUADSPI_LUT(lut_base + 1));
++
+ fsl_qspi_lock_lut(q);
+ }
+
+@@ -477,9 +502,15 @@ static void fsl_qspi_init_lut(struct fsl
+ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
+ {
+ switch (cmd) {
++ case SPINOR_OP_READ4_1_1_4:
+ case SPINOR_OP_READ_1_1_4:
+ case SPINOR_OP_READ_FAST:
++ case SPINOR_OP_READ4_FAST:
+ return SEQID_READ;
++ case SPINOR_OP_SPANSION_RDAR:
++ return SEQID_RDAR;
++ case SPINOR_OP_SPANSION_WRAR:
++ return SEQID_WRAR;
+ case SPINOR_OP_WREN:
+ return SEQID_WREN;
+ case SPINOR_OP_WRDI:
+@@ -491,6 +522,7 @@ static int fsl_qspi_get_seqid(struct fsl
+ case SPINOR_OP_CHIP_ERASE:
+ return SEQID_CHIP_ERASE;
+ case SPINOR_OP_PP:
++ case SPINOR_OP_PP_4B:
+ return SEQID_PP;
+ case SPINOR_OP_RDID:
+ return SEQID_RDID;
+@@ -830,8 +862,12 @@ static int fsl_qspi_read_reg(struct spi_
+ {
+ int ret;
+ struct fsl_qspi *q = nor->priv;
++ u32 to = 0;
++
++ if (opcode == SPINOR_OP_SPANSION_RDAR)
++ memcpy(&to, nor->cmd_buf, 4);
+
+- ret = fsl_qspi_runcmd(q, opcode, 0, len);
++ ret = fsl_qspi_runcmd(q, opcode, to, len);
+ if (ret)
+ return ret;
+
+@@ -843,9 +879,13 @@ static int fsl_qspi_write_reg(struct spi
+ {
+ struct fsl_qspi *q = nor->priv;
+ int ret;
++ u32 to = 0;
++
++ if (opcode == SPINOR_OP_SPANSION_WRAR)
++ memcpy(&to, nor->cmd_buf, 4);
+
+ if (!buf) {
+- ret = fsl_qspi_runcmd(q, opcode, 0, 1);
++ ret = fsl_qspi_runcmd(q, opcode, to, 1);
+ if (ret)
+ return ret;
+
+--- a/include/linux/mtd/spi-nor.h
++++ b/include/linux/mtd/spi-nor.h
+@@ -74,6 +74,10 @@
+ /* Used for Spansion flashes only. */
+ #define SPINOR_OP_BRWR 0x17 /* Bank register write */
+
++/* Used for Spansion S25FS-S family flash only. */
++#define SPINOR_OP_SPANSION_RDAR 0x65 /* Read any device register */
++#define SPINOR_OP_SPANSION_WRAR 0x71 /* Write any device register */
++
+ /* Used for Micron flashes only. */
+ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
+ #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
--- /dev/null
+From d2d88e3432d68b11b0add84bd15a3aadaf44f1c1 Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <B56489@freescale.com>
+Date: Mon, 28 Dec 2015 18:25:56 +0800
+Subject: [PATCH 102/113] mtd: spi-nor: fsl-quadspi:Support qspi for ls2080a
+
+There is a hardware feature that qspi_amba_base is added
+internally by SOC design on ls2080a. So as to software, the driver
+need support to the feature.
+
+Signed-off-by: Yunhui Cui <B56489@freescale.com>
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 24 ++++++++++++++++++++++--
+ 1 file changed, 22 insertions(+), 2 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -41,6 +41,8 @@
+ #define QUADSPI_QUIRK_TKT253890 (1 << 2)
+ /* Controller cannot wake up from wait mode, TKT245618 */
+ #define QUADSPI_QUIRK_TKT245618 (1 << 3)
++/* QSPI_AMBA_BASE is internally added by SOC design */
++#define QUADSPI_AMBA_BASE_INTERNAL (0x10000)
+
+ /* The registers */
+ #define QUADSPI_MCR 0x00
+@@ -217,6 +219,7 @@ enum fsl_qspi_devtype {
+ FSL_QUADSPI_IMX7D,
+ FSL_QUADSPI_IMX6UL,
+ FSL_QUADSPI_LS1021A,
++ FSL_QUADSPI_LS2080A,
+ };
+
+ struct fsl_qspi_devtype_data {
+@@ -270,6 +273,14 @@ static struct fsl_qspi_devtype_data ls10
+ .driver_data = 0,
+ };
+
++static struct fsl_qspi_devtype_data ls2080a_data = {
++ .devtype = FSL_QUADSPI_LS2080A,
++ .rxfifo = 128,
++ .txfifo = 64,
++ .ahb_buf_size = 1024,
++ .driver_data = QUADSPI_AMBA_BASE_INTERNAL,
++};
++
+ #define FSL_QSPI_MAX_CHIP 4
+ struct fsl_qspi {
+ struct spi_nor nor[FSL_QSPI_MAX_CHIP];
+@@ -312,6 +323,11 @@ static inline int needs_wakeup_wait_mode
+ return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
+ }
+
++static inline int has_added_amba_base_internal(struct fsl_qspi *q)
++{
++ return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL;
++}
++
+ /*
+ * R/W functions for big- or little-endian registers:
+ * The qSPI controller's endian is independent of the CPU core's endian.
+@@ -558,8 +574,11 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
+ /* save the reg */
+ reg = qspi_readl(q, base + QUADSPI_MCR);
+
+- qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
+- base + QUADSPI_SFAR);
++ if (has_added_amba_base_internal(q))
++ qspi_writel(q, q->chip_base_addr + addr, base + QUADSPI_SFAR);
++ else
++ qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
++ base + QUADSPI_SFAR);
+ qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
+ base + QUADSPI_RBCT);
+ qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
+@@ -849,6 +868,7 @@ static const struct of_device_id fsl_qsp
+ { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
+ { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
+ { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
++ { .compatible = "fsl,ls2080a-qspi", .data = (void *)&ls2080a_data, },
+ { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
--- /dev/null
+From 0878404f549021e7fe0a49ae0454cf53fd452add Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Tue, 2 Feb 2016 12:00:27 +0800
+Subject: [PATCH 103/113] mtd: spi-nor: Support R/W for S25FS-S family flash
+
+With the physical sectors combination, S25FS-S family flash
+requires some special operations for read/write functions.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 60 +++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 60 insertions(+)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -40,6 +40,10 @@
+ #define SPI_NOR_MAX_ID_LEN 6
+ #define SPI_NOR_MAX_ADDR_WIDTH 4
+ #define SPI_NOR_MICRON_WRITE_ENABLE 0x7f
++/* Added for S25FS-S family flash */
++#define SPINOR_CONFIG_REG3_OFFSET 0x800004
++#define CR3V_4KB_ERASE_UNABLE 0x8
++#define SPINOR_S25FS_FAMILY_ID 0x81
+
+ struct flash_info {
+ char *name;
+@@ -73,6 +77,8 @@ struct flash_info {
+ };
+
+ #define JEDEC_MFR(info) ((info)->id[0])
++#define EXT_ID(info) ((info)->id[5])
++
+
+ static const struct flash_info *spi_nor_match_id(const char *name);
+
+@@ -784,6 +790,7 @@ static const struct flash_info spi_nor_i
+ */
+ { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
++ { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, 0)},
+ { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
+ { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+@@ -908,6 +915,53 @@ static const struct flash_info *spi_nor_
+ return ERR_PTR(-ENODEV);
+ }
+
++/*
++ * The S25FS-S family physical sectors may be configured as a
++ * hybrid combination of eight 4-kB parameter sectors
++ * at the top or bottom of the address space with all
++ * but one of the remaining sectors being uniform size.
++ * The Parameter Sector Erase commands (20h or 21h) must
++ * be used to erase the 4-kB parameter sectors individually.
++ * The Sector (uniform sector) Erase commands (D8h or DCh)
++ * must be used to erase any of the remaining
++ * sectors, including the portion of highest or lowest address
++ * sector that is not overlaid by the parameter sectors.
++ * The uniform sector erase command has no effect on parameter sectors.
++ */
++static int spansion_s25fs_disable_4kb_erase(struct spi_nor *nor)
++{
++ struct fsl_qspi *q;
++ u32 cr3v_addr = SPINOR_CONFIG_REG3_OFFSET;
++ u8 cr3v = 0x0;
++ int ret = 0x0;
++
++ q = nor->priv;
++
++ nor->cmd_buf[2] = cr3v_addr >> 16;
++ nor->cmd_buf[1] = cr3v_addr >> 8;
++ nor->cmd_buf[0] = cr3v_addr >> 0;
++
++ ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
++ if (ret)
++ return ret;
++ if (cr3v & CR3V_4KB_ERASE_UNABLE)
++ return 0;
++ ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
++ if (ret)
++ return ret;
++ cr3v = CR3V_4KB_ERASE_UNABLE;
++ nor->program_opcode = SPINOR_OP_SPANSION_WRAR;
++ nor->write(nor, cr3v_addr, 1, &cr3v);
++
++ ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
++ if (ret)
++ return ret;
++ if (!(cr3v & CR3V_4KB_ERASE_UNABLE))
++ return -EPERM;
++
++ return 0;
++}
++
+ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+ {
+@@ -1246,6 +1300,12 @@ int spi_nor_scan(struct spi_nor *nor, co
+ write_sr(nor, ret);
+ }
+
++ if (EXT_ID(info) == SPINOR_S25FS_FAMILY_ID) {
++ ret = spansion_s25fs_disable_4kb_erase(nor);
++ if (ret)
++ return ret;
++ }
++
+ if (!mtd->name)
+ mtd->name = dev_name(dev);
+ mtd->priv = nor;
--- /dev/null
+From 23cd071c47c064d56921975d196dc22177069dea Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Wed, 24 Feb 2016 15:14:01 +0800
+Subject: [PATCH 104/113] mtd: fsl-quadspi: Add quad mode for flash n25q128
+
+Add some lut_tables to support quad mode for flash n25q128
+on the board ls1021a-twr and solve flash Spansion and Micron
+command conflict.
+In switch {}, The value of command SPINOR_OP_RD_EVCR and
+SPINOR_OP_SPANSION_RDAR is the same. They have to share
+the same seq_id: SEQID_RDAR_OR_RD_EVCR.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 47 ++++++++++++++++++++++++++++---------
+ 1 file changed, 36 insertions(+), 11 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -207,9 +207,9 @@
+ #define SEQID_RDCR 9
+ #define SEQID_EN4B 10
+ #define SEQID_BRWR 11
+-#define SEQID_RDAR 12
++#define SEQID_RDAR_OR_RD_EVCR 12
+ #define SEQID_WRAR 13
+-
++#define SEQID_WD_EVCR 14
+
+ #define QUADSPI_MIN_IOMAP SZ_4M
+
+@@ -393,6 +393,7 @@ static void fsl_qspi_init_lut(struct fsl
+ int rxfifo = q->devtype_data->rxfifo;
+ u32 lut_base;
+ int i;
++ const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
+
+ struct spi_nor *nor = &q->nor[0];
+ u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
+@@ -489,16 +490,26 @@ static void fsl_qspi_init_lut(struct fsl
+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
+ base + QUADSPI_LUT(lut_base));
+
++
+ /*
+- * Read any device register.
+- * Used for Spansion S25FS-S family flash only.
++ * Flash Micron and Spansion command confilict
++ * use the same value 0x65. But it indicates different meaning.
+ */
+- lut_base = SEQID_RDAR * 4;
+- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
+- LUT1(ADDR, PAD1, ADDR24BIT),
+- base + QUADSPI_LUT(lut_base));
+- qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
+- base + QUADSPI_LUT(lut_base + 1));
++ lut_base = SEQID_RDAR_OR_RD_EVCR * 4;
++ if (devtype_data->devtype == FSL_QUADSPI_LS2080A) {
++ /*
++ * Read any device register.
++ * Used for Spansion S25FS-S family flash only.
++ */
++ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
++ LUT1(ADDR, PAD1, ADDR24BIT),
++ base + QUADSPI_LUT(lut_base));
++ qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
++ base + QUADSPI_LUT(lut_base + 1));
++ } else {
++ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RD_EVCR),
++ base + QUADSPI_LUT(lut_base));
++ }
+
+ /*
+ * Write any device register.
+@@ -511,6 +522,11 @@ static void fsl_qspi_init_lut(struct fsl
+ qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
+ base + QUADSPI_LUT(lut_base + 1));
+
++ /* Write EVCR register */
++ lut_base = SEQID_WD_EVCR * 4;
++ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WD_EVCR),
++ base + QUADSPI_LUT(lut_base));
++
+ fsl_qspi_lock_lut(q);
+ }
+
+@@ -523,8 +539,15 @@ static int fsl_qspi_get_seqid(struct fsl
+ case SPINOR_OP_READ_FAST:
+ case SPINOR_OP_READ4_FAST:
+ return SEQID_READ;
++ /*
++ * Spansion & Micron use the same command value 0x65
++ * Spansion: SPINOR_OP_SPANSION_RDAR, read any register.
++ * Micron: SPINOR_OP_RD_EVCR,
++ * read enhanced volatile configuration register.
++ * case SPINOR_OP_RD_EVCR:
++ */
+ case SPINOR_OP_SPANSION_RDAR:
+- return SEQID_RDAR;
++ return SEQID_RDAR_OR_RD_EVCR;
+ case SPINOR_OP_SPANSION_WRAR:
+ return SEQID_WRAR;
+ case SPINOR_OP_WREN:
+@@ -550,6 +573,8 @@ static int fsl_qspi_get_seqid(struct fsl
+ return SEQID_EN4B;
+ case SPINOR_OP_BRWR:
+ return SEQID_BRWR;
++ case SPINOR_OP_WD_EVCR:
++ return SEQID_WD_EVCR;
+ default:
+ if (cmd == q->nor[0].erase_opcode)
+ return SEQID_SE;
--- /dev/null
+From 924f021c0344554a4b61746e5c4dcfc91d618ce2 Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Thu, 18 Feb 2016 16:41:53 +0800
+Subject: [PATCH 105/113] mtd: spi-nor: add DDR quad read support
+
+This patch adds the DDR quad read support by the following:
+
+ [1] add SPI_NOR_DDR_QUAD read mode.
+
+ [2] add DDR Quad read opcodes:
+ SPINOR_OP_READ_1_4_4_D / SPINOR_OP_READ4_1_4_4_D
+
+ [3] add set_ddr_quad_mode() to initialize for the DDR quad read.
+ Currently it only works for Spansion NOR.
+
+ [4] set dummy with 6 for Spansion family
+Test this patch for Spansion s25fl128s NOR flash.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 53 ++++++++++++++++++++++++++++++++++++-----
+ include/linux/mtd/spi-nor.h | 8 +++++--
+ 2 files changed, 53 insertions(+), 8 deletions(-)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -73,7 +73,8 @@ struct flash_info {
+ #define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
+ #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
+ #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
+-#define USE_FSR 0x80 /* use flag status register */
++#define SPI_NOR_DDR_QUAD_READ 0x80 /* Flash supports DDR Quad Read */
++#define USE_FSR 0x100 /* use flag status register */
+ };
+
+ #define JEDEC_MFR(info) ((info)->id[0])
+@@ -144,13 +145,17 @@ static int read_cr(struct spi_nor *nor)
+ * It can be used to support more commands with
+ * different dummy cycle requirements.
+ */
+-static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
++static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor,
++ const struct flash_info *info)
+ {
+ switch (nor->flash_read) {
+ case SPI_NOR_FAST:
+ case SPI_NOR_DUAL:
+ case SPI_NOR_QUAD:
+ return 8;
++ case SPI_NOR_DDR_QUAD:
++ if (JEDEC_MFR(info) == SNOR_MFR_SPANSION)
++ return 6;
+ case SPI_NOR_NORMAL:
+ return 0;
+ }
+@@ -797,7 +802,8 @@ static const struct flash_info spi_nor_i
+ { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
+ { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
+ { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
+- { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
++ { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ
++ | SPI_NOR_DDR_QUAD_READ) },
+ { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
+@@ -1186,6 +1192,23 @@ static int spansion_quad_enable(struct s
+ return 0;
+ }
+
++static int set_ddr_quad_mode(struct spi_nor *nor, const struct flash_info *info)
++{
++ int status;
++
++ switch (JEDEC_MFR(info)) {
++ case SNOR_MFR_SPANSION:
++ status = spansion_quad_enable(nor);
++ if (status) {
++ dev_err(nor->dev, "Spansion DDR quad-read not enabled\n");
++ return status;
++ }
++ return status;
++ default:
++ return -EINVAL;
++ }
++}
++
+ static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
+ {
+ int status;
+@@ -1375,8 +1398,15 @@ int spi_nor_scan(struct spi_nor *nor, co
+ if (info->flags & SPI_NOR_NO_FR)
+ nor->flash_read = SPI_NOR_NORMAL;
+
+- /* Quad/Dual-read mode takes precedence over fast/normal */
+- if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
++ /* DDR Quad/Quad/Dual-read mode takes precedence over fast/normal */
++ if (mode == SPI_NOR_DDR_QUAD && info->flags & SPI_NOR_DDR_QUAD_READ) {
++ ret = set_ddr_quad_mode(nor, info);
++ if (ret) {
++ dev_err(dev, "DDR quad mode not supported\n");
++ return ret;
++ }
++ nor->flash_read = SPI_NOR_DDR_QUAD;
++ } else if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
+ ret = set_quad_mode(nor, info);
+ if (ret) {
+ dev_err(dev, "quad mode not supported\n");
+@@ -1389,6 +1419,14 @@ int spi_nor_scan(struct spi_nor *nor, co
+
+ /* Default commands */
+ switch (nor->flash_read) {
++ case SPI_NOR_DDR_QUAD:
++ if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) { /* Spansion */
++ nor->read_opcode = SPINOR_OP_READ_1_4_4_D;
++ } else {
++ dev_err(dev, "DDR Quad Read is not supported.\n");
++ return -EINVAL;
++ }
++ break;
+ case SPI_NOR_QUAD:
+ nor->read_opcode = SPINOR_OP_READ_1_1_4;
+ break;
+@@ -1416,6 +1454,9 @@ int spi_nor_scan(struct spi_nor *nor, co
+ if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
+ /* Dedicated 4-byte command set */
+ switch (nor->flash_read) {
++ case SPI_NOR_DDR_QUAD:
++ nor->read_opcode = SPINOR_OP_READ4_1_4_4_D;
++ break;
+ case SPI_NOR_QUAD:
+ nor->read_opcode = SPINOR_OP_READ4_1_1_4;
+ break;
+@@ -1445,7 +1486,7 @@ int spi_nor_scan(struct spi_nor *nor, co
+ return -EINVAL;
+ }
+
+- nor->read_dummy = spi_nor_read_dummy_cycles(nor);
++ nor->read_dummy = spi_nor_read_dummy_cycles(nor, info);
+
+ dev_info(dev, "%s (%lld Kbytes)\n", info->name,
+ (long long)mtd->size >> 10);
+--- a/include/linux/mtd/spi-nor.h
++++ b/include/linux/mtd/spi-nor.h
+@@ -30,10 +30,11 @@
+
+ /*
+ * Note on opcode nomenclature: some opcodes have a format like
+- * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
++ * SPINOR_OP_FUNCTION{4,}_x_y_z{_D}. The numbers x, y,and z stand for the number
+ * of I/O lines used for the opcode, address, and data (respectively). The
+ * FUNCTION has an optional suffix of '4', to represent an opcode which
+- * requires a 4-byte (32-bit) address.
++ * requires a 4-byte (32-bit) address. The suffix of 'D' stands for the
++ * DDR mode.
+ */
+
+ /* Flash opcodes. */
+@@ -44,6 +45,7 @@
+ #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
+ #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
+ #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
++#define SPINOR_OP_READ_1_4_4_D 0xed /* Read data bytes (DDR Quad SPI) */
+ #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
+ #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
+ #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
+@@ -59,6 +61,7 @@
+ #define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
+ #define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
+ #define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
++#define SPINOR_OP_READ4_1_4_4_D 0xee /* Read data bytes (DDR Quad SPI) */
+ #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
+ #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
+
+@@ -107,6 +110,7 @@ enum read_mode {
+ SPI_NOR_FAST,
+ SPI_NOR_DUAL,
+ SPI_NOR_QUAD,
++ SPI_NOR_DDR_QUAD,
+ };
+
+ #define SPI_NOR_MAX_CMD_SIZE 8
--- /dev/null
+From 16eb35ceea5b43e6f64c1a869721ea86c0da5260 Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Thu, 25 Feb 2016 10:19:15 +0800
+Subject: [PATCH 106/113] mtd: fsl-quadspi: add DDR quad read for Spansion
+
+Add the DDR quad read support for the fsl-quadspi driver.
+And, add the Spansion s25fl128s NOR flash ddr quad mode
+support.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 57 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 57 insertions(+)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -296,6 +296,7 @@ struct fsl_qspi {
+ u32 nor_size;
+ u32 nor_num;
+ u32 clk_rate;
++ u32 ddr_smp;
+ unsigned int chip_base_addr; /* We may support two chips. */
+ bool has_second_chip;
+ bool big_endian;
+@@ -423,6 +424,19 @@ static void fsl_qspi_init_lut(struct fsl
+ qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
+ LUT1(FSL_READ, PAD4, rxfifo),
+ base + QUADSPI_LUT(lut_base + 1));
++ } else if (nor->flash_read == SPI_NOR_DDR_QUAD) {
++ /* read mode : 1-4-4, such as Spansion s25fl128s. */
++ qspi_writel(q, LUT0(CMD, PAD1, read_op)
++ | LUT1(ADDR_DDR, PAD4, addrlen),
++ base + QUADSPI_LUT(lut_base));
++
++ qspi_writel(q, LUT0(MODE_DDR, PAD4, 0xff)
++ | LUT1(DUMMY, PAD1, read_dm),
++ base + QUADSPI_LUT(lut_base + 1));
++
++ qspi_writel(q, LUT0(FSL_READ_DDR, PAD4, rxfifo)
++ | LUT1(JMP_ON_CS, PAD1, 0),
++ base + QUADSPI_LUT(lut_base + 2));
+ }
+
+ /* Write enable */
+@@ -534,6 +548,8 @@ static void fsl_qspi_init_lut(struct fsl
+ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
+ {
+ switch (cmd) {
++ case SPINOR_OP_READ_1_4_4_D:
++ case SPINOR_OP_READ4_1_4_4_D:
+ case SPINOR_OP_READ4_1_1_4:
+ case SPINOR_OP_READ_1_1_4:
+ case SPINOR_OP_READ_FAST:
+@@ -736,6 +752,32 @@ static void fsl_qspi_set_map_addr(struct
+ }
+
+ /*
++ * enable controller ddr quad mode to support different
++ * vender flashes ddr quad mode.
++ */
++static void set_ddr_quad_mode(struct fsl_qspi *q)
++{
++ u32 reg, reg2;
++
++ reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
++
++ /* Firstly, disable the module */
++ qspi_writel(q, reg | QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
++
++ /* Set the Sampling Register for DDR */
++ reg2 = qspi_readl(q, q->iobase + QUADSPI_SMPR);
++ reg2 &= ~QUADSPI_SMPR_DDRSMP_MASK;
++ reg2 |= (((q->ddr_smp) << QUADSPI_SMPR_DDRSMP_SHIFT) &
++ QUADSPI_SMPR_DDRSMP_MASK);
++ qspi_writel(q, reg2, q->iobase + QUADSPI_SMPR);
++
++ /* Enable the module again (enable the DDR too) */
++ reg |= QUADSPI_MCR_DDR_EN_MASK;
++ qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
++
++}
++
++/*
+ * There are two different ways to read out the data from the flash:
+ * the "IP Command Read" and the "AHB Command Read".
+ *
+@@ -775,6 +817,11 @@ static void fsl_qspi_init_abh_read(struc
+ seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
+ qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
+ q->iobase + QUADSPI_BFGENCR);
++
++ /* enable the DDR quad read */
++ if (q->nor->flash_read == SPI_NOR_DDR_QUAD)
++ set_ddr_quad_mode(q);
++
+ }
+
+ /* This function was used to prepare and enable QSPI clock */
+@@ -1108,6 +1155,12 @@ static int fsl_qspi_probe(struct platfor
+ goto clk_failed;
+ }
+
++ /* find ddrsmp value */
++ ret = of_property_read_u32(dev->of_node, "fsl,ddr-sampling-point",
++ &q->ddr_smp);
++ if (ret)
++ q->ddr_smp = 0;
++
+ /* find the irq */
+ ret = platform_get_irq(pdev, 0);
+ if (ret < 0) {
+@@ -1164,6 +1217,10 @@ static int fsl_qspi_probe(struct platfor
+
+ ret = of_property_read_bool(np, "m25p,fast-read");
+ mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD;
++ /* Can we enable the DDR Quad Read? */
++ ret = of_property_read_bool(np, "ddr-quad-read");
++ if (ret)
++ mode = SPI_NOR_DDR_QUAD;
+
+ ret = spi_nor_scan(nor, NULL, mode);
+ if (ret)
--- /dev/null
+From 50aac689d5be0a086f076cd4bc8b14ee0b9ab995 Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Tue, 8 Mar 2016 14:38:52 +0800
+Subject: [PATCH 107/113] mtd: fsl-quadspi: disable AHB buffer prefetch
+
+A-009282: QuadSPI: QuadSPI data pre-fetch can result in incorrect data
+Affects: QuadSPI
+Description: With AHB buffer prefetch enabled, the QuadSPI may return
+incorrect data on the AHB
+interface. The buffer pre-fetch is enabled if the fetch size as
+configured either in the LUT or in
+the BUFxCR register is greater than 8 bytes.
+Impact: Only 64 bit read allowed.
+Workaround: Keep the read data size to 64 bits (8 Bytes), which disables
+the prefetch on the AHB buffer,
+and prevents this issue from occurring.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 29 +++++++++++++++++++++++------
+ 1 file changed, 23 insertions(+), 6 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -794,19 +794,36 @@ static void fsl_qspi_init_abh_read(struc
+ {
+ void __iomem *base = q->iobase;
+ int seqid;
++ const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
+
+ /* AHB configuration for access buffer 0/1/2 .*/
+ qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
+ qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
+ qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
++
+ /*
+- * Set ADATSZ with the maximum AHB buffer size to improve the
+- * read performance.
++ * Errata: A-009282: QuadSPI data prefetch may result in incorrect data
++ * Workaround: Keep the read data size to 64 bits (8 bytes).
++ * This disables the prefetch on the AHB buffer and
++ * prevents this issue from occurring.
+ */
+- qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
+- ((q->devtype_data->ahb_buf_size / 8)
+- << QUADSPI_BUF3CR_ADATSZ_SHIFT),
+- base + QUADSPI_BUF3CR);
++ if (devtype_data->devtype == FSL_QUADSPI_LS2080A ||
++ devtype_data->devtype == FSL_QUADSPI_LS1021A) {
++
++ qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
++ (1 << QUADSPI_BUF3CR_ADATSZ_SHIFT),
++ base + QUADSPI_BUF3CR);
++
++ } else {
++ /*
++ * Set ADATSZ with the maximum AHB buffer size to improve the
++ * read performance.
++ */
++ qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
++ ((q->devtype_data->ahb_buf_size / 8)
++ << QUADSPI_BUF3CR_ADATSZ_SHIFT),
++ base + QUADSPI_BUF3CR);
++ }
+
+ /* We only use the buffer3 */
+ qspi_writel(q, 0, base + QUADSPI_BUF0IND);
--- /dev/null
+From d3a8ee41170ff9e5298ff354c77ff99439dfe2bf Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Thu, 10 Mar 2016 11:33:40 +0800
+Subject: [PATCH 108/113] mtd: fsl-quadspi: add multi flash chip R/W on
+ ls2080a
+
+There is a hardware feature that qspi_amba_base is added
+internally by SOC design on ls2080a. so memmap_phy need not
+be added in driver. If memmap_phy is added, the flash A1
+addr space is [0, memmap_phy] which far more than flash size.
+The AMBA memory will be divided into four parts and assign to
+every chipselect. Every channel will has two valid chipselects.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 14 ++++++++++----
+ 1 file changed, 10 insertions(+), 4 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -744,11 +744,17 @@ static void fsl_qspi_set_map_addr(struct
+ {
+ int nor_size = q->nor_size;
+ void __iomem *base = q->iobase;
++ u32 mem_base;
+
+- qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
+- qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
+- qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
+- qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
++ if (has_added_amba_base_internal(q))
++ mem_base = 0x0;
++ else
++ mem_base = q->memmap_phy;
++
++ qspi_writel(q, nor_size + mem_base, base + QUADSPI_SFA1AD);
++ qspi_writel(q, nor_size * 2 + mem_base, base + QUADSPI_SFA2AD);
++ qspi_writel(q, nor_size * 3 + mem_base, base + QUADSPI_SFB1AD);
++ qspi_writel(q, nor_size * 4 + mem_base, base + QUADSPI_SFB2AD);
+ }
+
+ /*
--- /dev/null
+From 70516f60de441829e7813c0b26567c8bda39c011 Mon Sep 17 00:00:00 2001
+From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Date: Sun, 24 Apr 2016 23:20:26 +0530
+Subject: [PATCH 109/113] drivers: mtd: spi-nor: Enable QSPI Flash in Kernel
+
+Enable read from QSPI flash, Write onto QSPI Flash and
+erase QSPI Flash in Fast mode in Kernel.
+
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -796,6 +796,7 @@ static const struct flash_info spi_nor_i
+ { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, 0)},
++ { "s25fs512s", INFO6(0x010220, 0x4d0081, 128 * 1024, 512, 0)},
+ { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
+ { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+@@ -962,9 +963,11 @@ static int spansion_s25fs_disable_4kb_er
+ ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
+ if (ret)
+ return ret;
++/*
+ if (!(cr3v & CR3V_4KB_ERASE_UNABLE))
+ return -EPERM;
+
++*/
+ return 0;
+ }
+
--- /dev/null
+From 034dd6241b55ab2256eecb845e941fa9b45da38e Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Thu, 28 Apr 2016 17:03:57 +0800
+Subject: [PATCH 110/113] mtd: spi-nor: fsl-quad: add flash S25FS extra
+ support
+
+[context adjustment]
+not apply changes of arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+
+There are some boards have the same QSPI controller but have
+different vendor flash, So, the controller can use the same
+compatible and share the driver, just for a different flash to do
+the appropriate adaptation. Based on this, we need add the vendor
+field in spi-nor, Because we will use the field to distribute
+corresponding LUT for different flash operations.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 47 ++++++++++++++++++++++++++++++-------
+ drivers/mtd/spi-nor/spi-nor.c | 5 ++--
+ include/linux/mtd/spi-nor.h | 1 +
+ 3 files changed, 42 insertions(+), 11 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -213,6 +213,9 @@
+
+ #define QUADSPI_MIN_IOMAP SZ_4M
+
++#define FLASH_VENDOR_SPANSION_FS "s25fs"
++#define SPANSION_S25FS_FAMILY (1 << 1)
++
+ enum fsl_qspi_devtype {
+ FSL_QUADSPI_VYBRID,
+ FSL_QUADSPI_IMX6SX,
+@@ -329,6 +332,18 @@ static inline int has_added_amba_base_in
+ return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL;
+ }
+
++static u32 fsl_get_nor_vendor(struct spi_nor *nor)
++{
++ u32 vendor_id;
++
++ if (nor->vendor) {
++ if (memcmp(nor->vendor, FLASH_VENDOR_SPANSION_FS,
++ sizeof(FLASH_VENDOR_SPANSION_FS) - 1))
++ vendor_id = SPANSION_S25FS_FAMILY;
++ }
++ return vendor_id;
++}
++
+ /*
+ * R/W functions for big- or little-endian registers:
+ * The qSPI controller's endian is independent of the CPU core's endian.
+@@ -394,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl
+ int rxfifo = q->devtype_data->rxfifo;
+ u32 lut_base;
+ int i;
+- const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
++ u32 vendor;
+
+ struct spi_nor *nor = &q->nor[0];
+ u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
+ u8 read_op = nor->read_opcode;
+ u8 read_dm = nor->read_dummy;
+
++ vendor = fsl_get_nor_vendor(nor);
++
+ fsl_qspi_unlock_lut(q);
+
+ /* Clear all the LUT table */
+@@ -418,12 +435,25 @@ static void fsl_qspi_init_lut(struct fsl
+ LUT1(FSL_READ, PAD1, rxfifo),
+ base + QUADSPI_LUT(lut_base + 1));
+ } else if (nor->flash_read == SPI_NOR_QUAD) {
+- qspi_writel(q, LUT0(CMD, PAD1, read_op) |
+- LUT1(ADDR, PAD1, addrlen),
+- base + QUADSPI_LUT(lut_base));
+- qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
+- LUT1(FSL_READ, PAD4, rxfifo),
+- base + QUADSPI_LUT(lut_base + 1));
++ if (q->nor_size == 0x4000000) {
++ read_op = 0xEC;
++ qspi_writel(q,
++ LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD4, addrlen),
++ base + QUADSPI_LUT(lut_base));
++ qspi_writel(q,
++ LUT0(MODE, PAD4, 0xff) | LUT1(DUMMY, PAD4, read_dm),
++ base + QUADSPI_LUT(lut_base + 1));
++ qspi_writel(q,
++ LUT0(FSL_READ, PAD4, rxfifo),
++ base + QUADSPI_LUT(lut_base + 2));
++ } else {
++ qspi_writel(q, LUT0(CMD, PAD1, read_op) |
++ LUT1(ADDR, PAD1, addrlen),
++ base + QUADSPI_LUT(lut_base));
++ qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
++ LUT1(FSL_READ, PAD4, rxfifo),
++ base + QUADSPI_LUT(lut_base + 1));
++ }
+ } else if (nor->flash_read == SPI_NOR_DDR_QUAD) {
+ /* read mode : 1-4-4, such as Spansion s25fl128s. */
+ qspi_writel(q, LUT0(CMD, PAD1, read_op)
+@@ -510,7 +540,8 @@ static void fsl_qspi_init_lut(struct fsl
+ * use the same value 0x65. But it indicates different meaning.
+ */
+ lut_base = SEQID_RDAR_OR_RD_EVCR * 4;
+- if (devtype_data->devtype == FSL_QUADSPI_LS2080A) {
++
++ if (vendor == SPANSION_S25FS_FAMILY) {
+ /*
+ * Read any device register.
+ * Used for Spansion S25FS-S family flash only.
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -796,7 +796,6 @@ static const struct flash_info spi_nor_i
+ { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, 0)},
+- { "s25fs512s", INFO6(0x010220, 0x4d0081, 128 * 1024, 512, 0)},
+ { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
+ { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+@@ -963,11 +962,9 @@ static int spansion_s25fs_disable_4kb_er
+ ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
+ if (ret)
+ return ret;
+-/*
+ if (!(cr3v & CR3V_4KB_ERASE_UNABLE))
+ return -EPERM;
+
+-*/
+ return 0;
+ }
+
+@@ -1334,6 +1331,8 @@ int spi_nor_scan(struct spi_nor *nor, co
+
+ if (!mtd->name)
+ mtd->name = dev_name(dev);
++ if (info->name)
++ nor->vendor = info->name;
+ mtd->priv = nor;
+ mtd->type = MTD_NORFLASH;
+ mtd->writesize = 1;
+--- a/include/linux/mtd/spi-nor.h
++++ b/include/linux/mtd/spi-nor.h
+@@ -172,6 +172,7 @@ struct spi_nor {
+ bool sst_write_second;
+ u32 flags;
+ u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
++ char *vendor;
+
+ int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
+ void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
--- /dev/null
+From 30d34abc80b0a602a1327bdfbddd42d250887049 Mon Sep 17 00:00:00 2001
+From: Yutang Jiang <yutang.jiang@nxp.com>
+Date: Fri, 9 Sep 2016 22:56:12 +0800
+Subject: [PATCH 111/113] mtd: spi-nor: disable 4kb sector erase for s25fl128
+
+As for s25fl128s flash, the sectors are organized either as a hybrid
+combination of 4-kB and 64-kB sectors, or as uniform 256-kbyte sectors.
+we should use the command 0xd8 to erase all bits, not the Parameter 4-kB
+Sector Erase (P4E) command 0x20.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+Integrated-by: Yutang Jiang <yutang.jiang@nxp.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -802,7 +802,7 @@ static const struct flash_info spi_nor_i
+ { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
+ { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
+ { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
+- { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ
++ { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ
+ | SPI_NOR_DDR_QUAD_READ) },
+ { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
--- /dev/null
+From f1b7824a42505669476f203e126fc26dd1006af2 Mon Sep 17 00:00:00 2001
+From: Yutang Jiang <yutang.jiang@nxp.com>
+Date: Fri, 9 Sep 2016 22:57:55 +0800
+Subject: [PATCH 112/113] driver: spi: fsl-quad: Hang memcpy: Unhandled fault:
+ alignment fault
+
+vmap/iomap based on whether the buffer is in memory region or reserved region.
+However, both map it as non-cacheable memory.
+For armv8 specifically, non-cacheable mapping requests use a memory type
+that has to be accessed aligned to the request size. memcpy() doesn't guarantee
+that. memcpy_toio() can guarantee 4-bytes alignment.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+Integrated-by: Yutang Jiang <yutang.jiang@nxp.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -1103,7 +1103,7 @@ static ssize_t fsl_qspi_read(struct spi_
+ len);
+
+ /* Read out the data directly from the AHB buffer.*/
+- memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
++ memcpy_toio(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
+ len);
+
+ return len;
--- /dev/null
+From 6f1195d231ab576809fe2f4cff44a6e48cff2457 Mon Sep 17 00:00:00 2001
+From: Yutang Jiang <yutang.jiang@nxp.com>
+Date: Fri, 2 Sep 2016 22:00:16 +0800
+Subject: [PATCH 113/113] mtd: spi-nor: fsl-quad: move mtd_device_register to
+ the last of probe
+
+After call mtd_device_register, the mtd devices should be workable immediately.
+If before finish all of init work call the mtd_device_register, it will not
+respond work request timely.
+
+For example, openwrt/lede have a AUTO split special flash partitions mechanism
+while mtd driver register. So, before call mtd_device_register, must let all of
+init work ready.
+
+Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 14 ++++++++++----
+ 1 file changed, 10 insertions(+), 4 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -1280,10 +1280,6 @@ static int fsl_qspi_probe(struct platfor
+ if (ret)
+ goto mutex_failed;
+
+- ret = mtd_device_register(mtd, NULL, 0);
+- if (ret)
+- goto mutex_failed;
+-
+ /* Set the correct NOR size now. */
+ if (q->nor_size == 0) {
+ q->nor_size = mtd->size;
+@@ -1313,6 +1309,16 @@ static int fsl_qspi_probe(struct platfor
+ goto last_init_failed;
+
+ fsl_qspi_clk_disable_unprep(q);
++
++ for (i = 0; i < q->nor_num; i++) {
++ /* skip the holes */
++ if (!q->has_second_chip)
++ i *= 2;
++
++ ret = mtd_device_register(&q->nor[i].mtd, NULL, 0);
++ if (ret)
++ goto last_init_failed;
++ }
+ return 0;
+
+ last_init_failed:
--- /dev/null
+From 035fe1e511e053c6650f37626deb5da76dcc1d92 Mon Sep 17 00:00:00 2001
+From: Ying Zhang <ying.zhang22455@nxp.com>
+Date: Thu, 29 Sep 2016 11:29:48 +0800
+Subject: [PATCH 119/124] armv8: aarch32: defconfig: Enable CAAM support
+
+This patch is to enable the driver module for Freescale's Cryptographics
+Accelerator and Assurance Module (CAAM) and related options.
+
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+---
+ arch/arm/configs/ls_aarch32_defconfig | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/configs/ls_aarch32_defconfig
++++ b/arch/arm/configs/ls_aarch32_defconfig
+@@ -200,8 +200,13 @@ CONFIG_MAGIC_SYSRQ=y
+ # CONFIG_FTRACE is not set
+ CONFIG_PID_IN_CONTEXTIDR=y
+ CONFIG_CRYPTO_LZO=y
+-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+-# CONFIG_CRYPTO_HW is not set
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_DEV_FSL_CAAM=y
++CONFIG_ARM_CRYPTO=y
++CONFIG_CRYPTO_SHA1_ARM_NEON=y
++CONFIG_CRYPTO_SHA256_ARM=y
++CONFIG_CRYPTO_SHA512_ARM_NEON=y
++CONFIG_CRYPTO_AES_ARM_BS=y
+ CONFIG_CRC_CCITT=m
+ CONFIG_CRC_T10DIF=y
+ CONFIG_CRC7=m
--- /dev/null
+From 027ca2530ce94dd7d9954e57631aa34987db392e Mon Sep 17 00:00:00 2001
+From: Ying Zhang <ying.zhang22455@nxp.com>
+Date: Thu, 29 Sep 2016 11:38:36 +0800
+Subject: [PATCH 120/124] armv8: aarch32: defconfig: Enable firmware loading
+
+As some modules require userspace firmware loading support, such as
+PPFE, add this feature in the defconfig for AArch32 on ARMv8.
+
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+---
+ arch/arm/configs/ls_aarch32_defconfig | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/arm/configs/ls_aarch32_defconfig
++++ b/arch/arm/configs/ls_aarch32_defconfig
+@@ -71,7 +71,6 @@ CONFIG_CAN=y
+ CONFIG_CAN_FLEXCAN=y
+ CONFIG_DEVTMPFS=y
+ CONFIG_DEVTMPFS_MOUNT=y
+-# CONFIG_FW_LOADER is not set
+ CONFIG_DMA_CMA=y
+ CONFIG_MTD=y
+ CONFIG_MTD_CMDLINE_PARTS=y
--- /dev/null
+From ff37b165bdb100450c7996c9fac0fad2e6ffe31d Mon Sep 17 00:00:00 2001
+From: Ying Zhang <ying.zhang22455@nxp.com>
+Date: Thu, 29 Sep 2016 11:40:37 +0800
+Subject: [PATCH 121/124] armv8: aarch32: defconfig: Enable support for AHCI
+ SATA
+
+This patch is to enable support for the Freescale QorIQ AHCI SoC's
+onboard AHCI SATA.
+
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+---
+ arch/arm/configs/ls_aarch32_defconfig | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/arm/configs/ls_aarch32_defconfig
++++ b/arch/arm/configs/ls_aarch32_defconfig
+@@ -92,7 +92,12 @@ CONFIG_MTD_SPI_NOR=y
+ CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+ CONFIG_SPI_FSL_QUADSPI=y
+ CONFIG_BLK_DEV_SD=y
++CONFIG_CHR_DEV_SG=y
+ CONFIG_ATA=y
++CONFIG_SATA_AHCI=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_QORIQ=y
++CONFIG_SATA_SIL24=y
+ CONFIG_BLK_DEV_LOOP=y
+ CONFIG_BLK_DEV_RAM=y
+ CONFIG_BLK_DEV_RAM_COUNT=8
--- /dev/null
+From 913db32774fe5c818112232823edfda1a706552f Mon Sep 17 00:00:00 2001
+From: Ying Zhang <ying.zhang22455@nxp.com>
+Date: Thu, 29 Sep 2016 11:42:40 +0800
+Subject: [PATCH 122/124] armv8: aarch32: defconfig: Enable USB and related
+ configuration options
+
+This patch is to enable USB and related configuration options for
+AArch32 on ARMv8.
+
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+---
+ arch/arm/configs/ls_aarch32_defconfig | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/arm/configs/ls_aarch32_defconfig
++++ b/arch/arm/configs/ls_aarch32_defconfig
+@@ -154,8 +154,14 @@ CONFIG_MFD_SYSCON=y
+ CONFIG_FB=y
+ CONFIG_USB=y
+ CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_HCD_PLATFORM=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_HCD_PLATFORM=y
++CONFIG_USB_STORAGE=y
+ CONFIG_USB_DWC3=y
+ CONFIG_USB_STORAGE=y
++CONFIG_USB_ULPI=y
+ CONFIG_MMC=y
+ CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_PLTFM=y
--- /dev/null
+From dbf356cd062d6313f90323a77d4cf7c820dae40f Mon Sep 17 00:00:00 2001
+From: Ying Zhang <ying.zhang22455@nxp.com>
+Date: Thu, 29 Sep 2016 13:51:32 +0800
+Subject: [PATCH 123/124] armv8: aarch32: defconfig: Enable KVM-related
+ configuration options
+
+This patch is to enable KVM-related configuration options for host and
+guest.
+
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+---
+ arch/arm/configs/ls_aarch32_defconfig | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/arch/arm/configs/ls_aarch32_defconfig
++++ b/arch/arm/configs/ls_aarch32_defconfig
+@@ -102,7 +102,11 @@ CONFIG_BLK_DEV_LOOP=y
+ CONFIG_BLK_DEV_RAM=y
+ CONFIG_BLK_DEV_RAM_COUNT=8
+ CONFIG_BLK_DEV_RAM_SIZE=262144
++CONFIG_VIRTIO_BLK=y
+ CONFIG_NETDEVICES=y
++CONFIG_TUN=y
++CONFIG_VIRTIO_NET=y
++CONFIG_VHOST_NET=y
+ CONFIG_NET_VENDOR_FREESCALE is not set
+ CONFIG_FSL_BMAN=y
+ CONFIG_FSL_QMAN=y
+@@ -130,6 +134,8 @@ CONFIG_SERIAL_8250=y
+ CONFIG_SERIAL_8250_CONSOLE=y
+ CONFIG_SERIAL_8250_EXTENDED=y
+ CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+ CONFIG_SERIAL_OF_PLATFORM=y
+ CONFIG_SERIAL_FSL_LPUART=y
+ CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+@@ -170,6 +176,7 @@ CONFIG_RTC_CLASS=y
+ CONFIG_RTC_DRV_DS3232=y
+ CONFIG_DMADEVICES=y
+ CONFIG_FSL_EDMA=y
++CONFIG_VIRTIO_PCI=y
+ CONFIG_STAGING=y
+ CONFIG_CLK_QORIQ=y
+ # CONFIG_IOMMU_SUPPORT is not set
+@@ -191,6 +198,7 @@ CONFIG_VFAT_FS=y
+ CONFIG_NTFS_FS=m
+ CONFIG_TMPFS=y
+ CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_HUGETLBFS=y
+ CONFIG_CONFIGFS_FS=y
+ CONFIG_JFFS2_FS=y
+ CONFIG_NFS_FS=y
+@@ -221,3 +229,5 @@ CONFIG_CRC_CCITT=m
+ CONFIG_CRC_T10DIF=y
+ CONFIG_CRC7=m
+ CONFIG_LIBCRC32C=m
++CONFIG_VIRTUALIZATION=y
++CONFIG_KVM=y
--- /dev/null
+From 6df7fdf7e0c76df7acc2d1a3a287bf094a94c4ff Mon Sep 17 00:00:00 2001
+From: Ying Zhang <ying.zhang22455@nxp.com>
+Date: Thu, 29 Sep 2016 13:55:44 +0800
+Subject: [PATCH 124/124] armv8: aarch32: defconfig: Enable FTM alarm support
+
+This patch is to enable FTM alarm support.
+
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+---
+ arch/arm/configs/ls_aarch32_defconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm/configs/ls_aarch32_defconfig
++++ b/arch/arm/configs/ls_aarch32_defconfig
+@@ -181,6 +181,8 @@ CONFIG_STAGING=y
+ CONFIG_CLK_QORIQ=y
+ # CONFIG_IOMMU_SUPPORT is not set
+ CONFIG_MEMORY=y
++CONFIG_LS_SOC_DRIVERS=y
++CONFIG_FTM_ALARM=y
+ CONFIG_PWM=y
+ CONFIG_PWM_FSL_FTM=y
+ # CONFIG_RESET_CONTROLLER is not set
--- /dev/null
+From 70e0080366e76dabf90b713f57fb9fc47aa35557 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 11 Aug 2016 10:36:05 +0800
+Subject: [PATCH 071/113] arm64: dts: add device tree for ls1012a SoC and
+ boards
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This patch is to add device tree for ls1012a SoC and RDB/FREEDOM boards.
+
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
+Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
+Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
+Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
+Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com>
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+[yangbolu: integrate]
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/Makefile | 2 +
+ arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 186 +++++++
+ arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 114 +++++
+ arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 526 ++++++++++++++++++++
+ 4 files changed, 828 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -2,6 +2,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
+
+ always := $(dtb-y)
+ subdir-y := $(dts-dirs)
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+@@ -0,0 +1,186 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
++ *
++ * Copyright 2016, Freescale Semiconductor Inc.
++
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Freescale Semiconductor nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++/dts-v1/;
++
++#include "fsl-ls1012a.dtsi"
++
++/ {
++ model = "LS1012A FREEDOM Board";
++ compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
++
++ aliases {
++ crypto = &crypto;
++ };
++
++ sys_mclk: clock-mclk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <25000000>;
++ };
++
++ regulators {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ reg_1p8v: regulator@0 {
++ compatible = "regulator-fixed";
++ reg = <0>;
++ regulator-name = "1P8V";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ };
++ };
++
++ sound {
++ compatible = "simple-audio-card";
++ simple-audio-card,format = "i2s";
++ simple-audio-card,widgets =
++ "Microphone", "Microphone Jack",
++ "Headphone", "Headphone Jack",
++ "Speaker", "Speaker Ext",
++ "Line", "Line In Jack";
++ simple-audio-card,routing =
++ "MIC_IN", "Microphone Jack",
++ "Microphone Jack", "Mic Bias",
++ "LINE_IN", "Line In Jack",
++ "Headphone Jack", "HP_OUT",
++ "Speaker Ext", "LINE_OUT";
++
++ simple-audio-card,cpu {
++ sound-dai = <&sai2>;
++ frame-master;
++ bitclock-master;
++ };
++
++ simple-audio-card,codec {
++ sound-dai = <&codec>;
++ frame-master;
++ bitclock-master;
++ system-clock-frequency = <25000000>;
++ };
++ };
++};
++
++&qspi {
++ num-cs = <2>;
++ bus-num = <0>;
++ status = "okay";
++ fsl,ddr-sampling-point = <4>;
++
++ qflash0: s25fs512s@0 {
++ compatible = "spansion,m25p80";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ spi-max-frequency = <20000000>;
++ m25p,fast-read;
++ reg = <0>;
++ };
++};
++&ftm0 {
++ status = "okay";
++};
++
++&i2c0 {
++ status = "okay";
++
++ codec: sgtl5000@a {
++ #sound-dai-cells = <0>;
++ compatible = "fsl,sgtl5000";
++ reg = <0xa>;
++ VDDA-supply = <®_1p8v>;
++ VDDIO-supply = <®_1p8v>;
++ clocks = <&sys_mclk 1>;
++ };
++};
++
++&duart0 {
++ status = "okay";
++};
++&pfe {
++ status = "okay";
++ ethernet@0 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = < 0x0 >; /* GEM_ID */
++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ local-mac-address = [ 00 1A 2B 3C 4D 5E ];
++ phy-mode = "sgmii";
++ fsl,pfe-gemac-if-name = "eth0";
++ fsl,pfe-phy-if-flags = <0x0>;
++ fsl,pfe-gemac-mode = <0x1B00>; /* GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G */
++
++ mdio@0 {
++ reg = <0x1>; /* enabled/disabled */
++ fsl,mdio-phy-mask = <0xFFFFFFF9>;
++ };
++ };
++ ethernet@1 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = < 0x1 >; /* GEM_ID */
++ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
++ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ local-mac-address = [ 00 AA BB CC DD EE ];
++ phy-mode = "sgmii";
++ fsl,pfe-gemac-if-name = "eth1";
++ fsl,pfe-phy-if-flags = <0x0>;
++ fsl,pfe-gemac-mode = <0x1B00>; /* GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G */
++ mdio@0 {
++ reg = <0x0>; /* enabled/disabled */
++ fsl,mdio-phy-mask = <0xFFFFFFF9>;
++ };
++
++ };
++
++};
++
++
++&esdhc0 {
++ status = "disabled";
++};
++
++&esdhc1 {
++ status = "disabled";
++};
++
++&sai2 {
++ status = "okay";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+@@ -0,0 +1,114 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
++ *
++ * Copyright 2016, Freescale Semiconductor Inc.
++
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Freescale Semiconductor nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++/dts-v1/;
++
++#include "fsl-ls1012a.dtsi"
++
++/ {
++ model = "LS1012A RDB Board";
++ compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
++
++ aliases {
++ crypto = &crypto;
++ };
++};
++
++&qspi {
++ num-cs = <2>;
++ bus-num = <0>;
++ status = "okay";
++ fsl,ddr-sampling-point = <4>;
++
++ qflash0: s25fs512s@0 {
++ compatible = "spansion,m25p80";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ spi-max-frequency = <20000000>;
++ m25p,fast-read;
++ reg = <0>;
++ };
++};
++&ftm0 {
++ status = "okay";
++};
++
++&i2c0 {
++ status = "okay";
++};
++
++&duart0 {
++ status = "okay";
++};
++&pfe {
++ status = "okay";
++ ethernet@0 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = < 0x0 >; /* GEM_ID */
++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ local-mac-address = [ 00 1A 2B 3C 4D 5E ];
++ phy-mode = "sgmii";
++ fsl,pfe-gemac-if-name = "eth0";
++ fsl,pfe-phy-if-flags = <0x0>;
++ fsl,pfe-gemac-mode = <0x1B00>; /* GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G */
++
++ mdio@0 {
++ reg = <0x1>; /* enabled/disabled */
++ fsl,mdio-phy-mask = <0xFFFFFFF9>;
++ };
++ };
++ ethernet@1 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = < 0x1 >; /* GEM_ID */
++ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
++ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ local-mac-address = [ 00 AA BB CC DD EE ];
++ phy-mode = "rgmii";
++ fsl,pfe-gemac-if-name = "eth2";
++ fsl,pfe-phy-if-flags = <0x0>;
++ fsl,pfe-gemac-mode = <0x1B00>; /* GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G */
++ mdio@0 {
++ reg = <0x0>; /* enabled/disabled */
++ fsl,mdio-phy-mask = <0xFFFFFFF9>;
++ };
++
++ };
++
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+@@ -0,0 +1,526 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
++ *
++ * Copyright 2016, Freescale Semiconductor
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This library is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This library is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include <dt-bindings/thermal/thermal.h>
++
++/ {
++ compatible = "fsl,ls1012a";
++ interrupt-parent = <&gic>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ /*
++ * We expect the enable-method for cpu's to be "psci", but this
++ * is dependent on the SoC FW, which will fill this in.
++ *
++ * Currently supported enable-method is psci v0.2
++ */
++ cpu0: cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a53";
++ reg = <0x0>;
++ clocks = <&clockgen 1 0>;
++ #cooling-cells = <2>;
++ };
++
++ };
++
++
++ sysclk: sysclk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <100000000>;
++ clock-output-names = "sysclk";
++ };
++
++ timer {
++ compatible = "arm,armv8-timer";
++ interrupts = <1 13 0x1>, /* Physical Secure PPI */
++ <1 14 0x1>, /* Physical Non-Secure PPI */
++ <1 11 0x1>, /* Virtual PPI */
++ <1 10 0x1>; /* Hypervisor PPI */
++ arm,reread-timer;
++ };
++
++ pmu {
++ compatible = "arm,armv8-pmuv3";
++ interrupts = <0 106 0x4>;
++ };
++
++ gic: interrupt-controller@1400000 {
++ compatible = "arm,gic-400";
++ #interrupt-cells = <3>;
++ interrupt-controller;
++ reg = <0x0 0x1401000 0 0x1000>, /* GICD */
++ <0x0 0x1402000 0 0x2000>, /* GICC */
++ <0x0 0x1404000 0 0x2000>, /* GICH */
++ <0x0 0x1406000 0 0x2000>; /* GICV */
++ interrupts = <1 9 0xf08>;
++ };
++
++ soc {
++ compatible = "simple-bus";
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ clockgen: clocking@1ee1000 {
++ compatible = "fsl,ls1012a-clockgen";
++ reg = <0x0 0x1ee1000 0x0 0x1000>;
++ #clock-cells = <2>;
++ clocks = <&sysclk>;
++ };
++
++ scfg: scfg@1570000 {
++ compatible = "fsl,ls1012a-scfg",
++ "fsl,ls1043a-scfg",
++ "syscon";
++ reg = <0x0 0x1570000 0x0 0x10000>;
++ big-endian;
++ };
++
++ crypto: crypto@1700000 {
++ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
++ "fsl,sec-v4.0";
++ fsl,sec-era = <8>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x0 0x00 0x1700000 0x100000>;
++ reg = <0x00 0x1700000 0x0 0x100000>;
++ interrupts = <0 75 0x4>;
++
++ sec_jr0: jr@10000 {
++ compatible = "fsl,sec-v5.4-job-ring",
++ "fsl,sec-v5.0-job-ring",
++ "fsl,sec-v4.0-job-ring";
++ reg = <0x10000 0x10000>;
++ interrupts = <0 71 0x4>;
++ };
++
++ sec_jr1: jr@20000 {
++ compatible = "fsl,sec-v5.4-job-ring",
++ "fsl,sec-v5.0-job-ring",
++ "fsl,sec-v4.0-job-ring";
++ reg = <0x20000 0x10000>;
++ interrupts = <0 72 0x4>;
++ };
++
++ sec_jr2: jr@30000 {
++ compatible = "fsl,sec-v5.4-job-ring",
++ "fsl,sec-v5.0-job-ring",
++ "fsl,sec-v4.0-job-ring";
++ reg = <0x30000 0x10000>;
++ interrupts = <0 73 0x4>;
++ };
++
++ sec_jr3: jr@40000 {
++ compatible = "fsl,sec-v5.4-job-ring",
++ "fsl,sec-v5.0-job-ring",
++ "fsl,sec-v4.0-job-ring";
++ reg = <0x40000 0x10000>;
++ interrupts = <0 74 0x4>;
++ };
++ };
++
++
++ dcfg: dcfg@1ee0000 {
++ compatible = "fsl,ls1012a-dcfg",
++ "fsl,ls1043a-dcfg",
++ "syscon";
++ reg = <0x0 0x1ee0000 0x0 0x10000>;
++ };
++
++ reset: reset@1EE00B0 {
++ compatible = "fsl,ls-reset";
++ reg = <0x0 0x1EE00B0 0x0 0x4>;
++ big-endian;
++ };
++
++ rcpm: rcpm@1ee2000 {
++ compatible = "fsl,ls1012a-rcpm",
++ "fsl,ls1043a-rcpm",
++ "fsl,qoriq-rcpm-2.1";
++ reg = <0x0 0x1ee2000 0x0 0x10000>;
++ };
++
++ ftm0: ftm0@29d0000 {
++ compatible = "fsl,ftm-alarm";
++ reg = <0x0 0x29d0000 0x0 0x10000>;
++ interrupts = <0 86 0x4>;
++ big-endian;
++ rcpm-wakeup = <&rcpm 0x00020000 0x0>;
++ status = "okay";
++ };
++
++ esdhc0: esdhc@1560000 {
++ compatible = "fsl,ls1012a-esdhc0", "fsl,esdhc";
++ reg = <0x0 0x1560000 0x0 0x10000>;
++ interrupts = <0 62 0x4>;
++ clock-frequency = <0>;
++ voltage-ranges = <1800 1800 3300 3300>;
++ sdhci,auto-cmd12;
++ big-endian;
++ bus-width = <4>;
++ };
++
++ esdhc1: esdhc@1580000 {
++ compatible = "fsl,ls1012a-esdhc1", "fsl,esdhc";
++ reg = <0x0 0x1580000 0x0 0x10000>;
++ interrupts = <0 65 0x4>;
++ clock-frequency = <0>;
++ voltage-ranges = <1800 1800 3300 3300>;
++ sdhci,auto-cmd12;
++ big-endian;
++ bus-width = <4>;
++ };
++
++ dspi0: dspi@2100000 {
++ compatible = "fsl,ls1012a-dspi",
++ "fsl,ls1043a-dspi",
++ "fsl,ls1021a-v1.0-dspi";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x2100000 0x0 0x10000>;
++ interrupts = <0 64 0x4>;
++ clock-names = "dspi";
++ clocks = <&clockgen 4 0>;
++ spi-num-chipselects = <5>;
++ big-endian;
++ status = "enabled";
++ };
++
++ qspi: quadspi@1550000 {
++ compatible = "fsl,ls1012a-qspi",
++ "fsl,ls1043a-qspi",
++ "fsl,ls1021a-qspi";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x1550000 0x0 0x10000>,
++ <0x0 0x40000000 0x0 0x4000000>;
++ reg-names = "QuadSPI", "QuadSPI-memory";
++ interrupts = <0 99 0x4>;
++ clock-names = "qspi_en", "qspi";
++ clocks = <&clockgen 4 0>, <&clockgen 4 0>;
++ big-endian;
++ amba-base = <0x42000000>;
++ };
++
++ tmu: tmu@1f00000 {
++ compatible = "fsl,qoriq-tmu", "fsl,ls1012a-tmu";
++ reg = <0x0 0x1f00000 0x0 0x10000>;
++ interrupts = <0 33 0x4>;
++ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
++ fsl,tmu-calibration = <0x00000000 0x00000026
++ 0x00000001 0x0000002d
++ 0x00000002 0x00000032
++ 0x00000003 0x00000039
++ 0x00000004 0x0000003f
++ 0x00000005 0x00000046
++ 0x00000006 0x0000004d
++ 0x00000007 0x00000054
++ 0x00000008 0x0000005a
++ 0x00000009 0x00000061
++ 0x0000000a 0x0000006a
++ 0x0000000b 0x00000071
++
++ 0x00010000 0x00000025
++ 0x00010001 0x0000002c
++ 0x00010002 0x00000035
++ 0x00010003 0x0000003d
++ 0x00010004 0x00000045
++ 0x00010005 0x0000004e
++ 0x00010006 0x00000057
++ 0x00010007 0x00000061
++ 0x00010008 0x0000006b
++ 0x00010009 0x00000076
++
++ 0x00020000 0x00000029
++ 0x00020001 0x00000033
++ 0x00020002 0x0000003d
++ 0x00020003 0x00000049
++ 0x00020004 0x00000056
++ 0x00020005 0x00000061
++ 0x00020006 0x0000006d
++
++ 0x00030000 0x00000021
++ 0x00030001 0x0000002a
++ 0x00030002 0x0000003c
++ 0x00030003 0x0000004e>;
++ big-endian;
++ #thermal-sensor-cells = <1>;
++ };
++
++ thermal-zones {
++ cpu_thermal: cpu-thermal {
++ polling-delay-passive = <1000>;
++ polling-delay = <5000>;
++
++ thermal-sensors = <&tmu 0>;
++
++ trips {
++ cpu_alert: cpu-alert {
++ temperature = <85000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++ cpu_crit: cpu-crit {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++ };
++
++ cooling-maps {
++ map0 {
++ trip = <&cpu_alert>;
++ cooling-device =
++ <&cpu0 THERMAL_NO_LIMIT
++ THERMAL_NO_LIMIT>;
++ };
++ };
++ };
++ };
++
++ i2c0: i2c@2180000 {
++ compatible = "fsl,vf610-i2c";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x2180000 0x0 0x10000>;
++ interrupts = <0 56 0x4>;
++ clock-names = "i2c";
++ clocks = <&clockgen 4 0>;
++ status = "disabled";
++ };
++
++ i2c1: i2c@2190000 {
++ compatible = "fsl,vf610-i2c";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x2190000 0x0 0x10000>;
++ interrupts = <0 57 0x4>;
++ clock-names = "i2c";
++ clocks = <&clockgen 4 0>;
++ status = "disabled";
++ };
++
++
++ duart0: serial@21c0500 {
++ compatible = "fsl,ns16550", "ns16550a";
++ reg = <0x00 0x21c0500 0x0 0x100>;
++ interrupts = <0 54 0x4>;
++ clocks = <&clockgen 4 0>;
++ };
++
++ duart1: serial@21c0600 {
++ compatible = "fsl,ns16550", "ns16550a";
++ reg = <0x00 0x21c0600 0x0 0x100>;
++ interrupts = <0 54 0x4>;
++ clocks = <&clockgen 4 0>;
++ };
++
++ gpio0: gpio@2300000 {
++ compatible = "fsl,qoriq-gpio";
++ reg = <0x0 0x2300000 0x0 0x10000>;
++ interrupts = <0 66 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio1: gpio@2310000 {
++ compatible = "fsl,qoriq-gpio";
++ reg = <0x0 0x2310000 0x0 0x10000>;
++ interrupts = <0 67 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ wdog0: wdog@2ad0000 {
++ compatible = "fsl,ls1012a-wdt",
++ "fsl,ls1043a-wdt",
++ "fsl,imx21-wdt";
++ reg = <0x0 0x2ad0000 0x0 0x10000>;
++ interrupts = <0 83 0x4>;
++ clocks = <&clockgen 4 0>;
++ clock-names = "wdog";
++ big-endian;
++ };
++
++ sai1: sai@2b50000 {
++ #sound-dai-cells = <0>;
++ compatible = "fsl,vf610-sai";
++ reg = <0x0 0x2b50000 0x0 0x10000>;
++ interrupts = <0 148 0x4>;
++ clocks = <&clockgen 4 3>, <&clockgen 4 3>,
++ <&clockgen 4 3>, <&clockgen 4 3>;
++ clock-names = "bus", "mclk1", "mclk2", "mclk3";
++ dma-names = "tx", "rx";
++ dmas = <&edma0 1 47>,
++ <&edma0 1 46>;
++ status = "disabled";
++ };
++
++ sai2: sai@2b60000 {
++ #sound-dai-cells = <0>;
++ compatible = "fsl,vf610-sai";
++ reg = <0x0 0x2b60000 0x0 0x10000>;
++ interrupts = <0 149 0x4>;
++ clocks = <&clockgen 4 3>, <&clockgen 4 3>,
++ <&clockgen 4 3>, <&clockgen 4 3>;
++ clock-names = "bus", "mclk1", "mclk2", "mclk3";
++ dma-names = "tx", "rx";
++ dmas = <&edma0 1 45>,
++ <&edma0 1 44>;
++ status = "disabled";
++ };
++
++ edma0: edma@2c00000 {
++ #dma-cells = <2>;
++ compatible = "fsl,vf610-edma";
++ reg = <0x0 0x2c00000 0x0 0x10000>,
++ <0x0 0x2c10000 0x0 0x10000>,
++ <0x0 0x2c20000 0x0 0x10000>;
++ interrupts = <0 103 0x4>,
++ <0 103 0x4>;
++ interrupt-names = "edma-tx", "edma-err";
++ dma-channels = <32>;
++ big-endian;
++ clock-names = "dmamux0", "dmamux1";
++ clocks = <&clockgen 4 3>,
++ <&clockgen 4 3>;
++ };
++
++ sata: sata@3200000 {
++ compatible = "fsl,ls1012a-ahci";
++ reg = <0x0 0x3200000 0x0 0x10000>;
++ interrupts = <0 69 0x4>;
++ clocks = <&clockgen 4 0>;
++ };
++
++ msi2: msi-controller2@1572000 {
++ compatible ="fsl,1s1012a-msi", "fsl,1s1021a-msi";
++ reg = <0x0 0x1572000 0x0 0x4>,
++ <0x0 0x1572004 0x0 0x4>;
++ reg-names = "msiir", "msir";
++ msi-controller;
++ interrupts = <0 126 0x4>;
++ };
++
++ usb@8600000 {
++ compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
++ reg = <0x0 0x8600000 0x0 0x1000>;
++ interrupts = <0 139 0x4>;
++ dr_mode = "host";
++ phy_type = "ulpi";
++ fsl,usb-erratum-a005697;
++ };
++
++ usb0: usb3@2f00000 {
++ compatible = "snps,dwc3";
++ reg = <0x0 0x2f00000 0x0 0x10000>;
++ interrupts = <0 60 0x4>;
++ dr_mode = "host";
++ configure-gfladj;
++ snps,dis_rxdet_inp3_quirk;
++ };
++
++ pcie@3400000 {
++ compatible = "fsl,ls1012a-pcie",
++ "fsl,ls1043a-pcie",
++ "snps,dw-pcie";
++ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
++ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
++ reg-names = "regs", "config";
++ interrupts = <0 118 0x4>, /* controller interrupt */
++ <0 117 0x4>; /* PME interrupt */
++ interrupt-names = "intr", "pme";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ num-lanes = <4>;
++ bus-range = <0x0 0xff>;
++ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
++ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++ msi-parent = <&msi2>;
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
++ <0000 0 0 2 &gic 0 111 0x4>,
++ <0000 0 0 3 &gic 0 112 0x4>,
++ <0000 0 0 4 &gic 0 113 0x4>;
++ };
++ };
++ reserved-memory {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ pfe_reserved: packetbuffer@83400000 {
++ reg = <0 0x83400000 0 0xc00000>;
++ };
++ };
++
++ pfe: pfe@04000000 {
++ compatible = "fsl,pfe";
++ ranges = <0x0 0x00 0x04000000 0xc00000
++ 0x1 0x00 0x83400000 0xc00000>;
++ reg = <0x0 0x90500000 0x0 0x10000>, /* APB 64K */
++ <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
++ <0x0 0x83400000 0x0 0xc00000>, /* PFE DDR 12M */
++ <0x0 0x10000000 0x0 0x2000>; /* OCRAM 8K */
++ fsl,pfe-num-interfaces = < 0x2 >;
++ interrupts = <0 172 0x4>;
++ #interrupt-names = "hifirq";
++ memory-region = <&pfe_reserved>;
++ fsl,pfe-scfg = <&scfg 0>;
++ };
++
++};
--- /dev/null
+From f6dcf8936845ea95eba432ee725cec761032fe2a Mon Sep 17 00:00:00 2001
+From: Ying Zhang <ying.zhang22455@nxp.com>
+Date: Thu, 29 Sep 2016 10:12:29 +0800
+Subject: [PATCH 117/124] armv8: aarch32: Run 32-bit Linux for LayerScape SoCs
+
+This patch adds AArch32 execution state support for LayerScape SoCs.
+
+Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com>
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+---
+ arch/arm/mach-imx/Makefile | 2 ++
+ arch/arm/mach-imx/mach-layerscape.c | 22 ++++++++++++++++++++++
+ 2 files changed, 24 insertions(+)
+ create mode 100644 arch/arm/mach-imx/mach-layerscape.c
+
+--- a/arch/arm/mach-imx/Makefile
++++ b/arch/arm/mach-imx/Makefile
+@@ -103,4 +103,6 @@ obj-$(CONFIG_SOC_LS1021A) += mach-ls1021
+
+ obj-$(CONFIG_ARCH_LAYERSCAPE) += mach-ls1043a.o
+
++obj-$(CONFIG_ARCH_LAYERSCAPE) += mach-layerscape.o
++
+ obj-y += devices/
+--- /dev/null
++++ b/arch/arm/mach-imx/mach-layerscape.c
+@@ -0,0 +1,22 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <asm/mach/arch.h>
++
++#include "common.h"
++
++static const char * const layerscape_dt_compat[] __initconst = {
++ "fsl,ls1043a",
++ "fsl,ls1012a",
++ NULL,
++};
++
++DT_MACHINE_START(LAYERSCAPE, "Freescale LAYERSCAPE")
++ .dt_compat = layerscape_dt_compat,
++MACHINE_END
--- /dev/null
+From 44914d3b7baff0f96c3584e4d46aa992e402ef4f Mon Sep 17 00:00:00 2001
+From: Ying Zhang <ying.zhang22455@nxp.com>
+Date: Thu, 29 Sep 2016 11:16:16 +0800
+Subject: [PATCH 118/124] armv8: aarch32: Add KVM support for AArch32 on ARMv8
+
+This patch is to add KVM support for AArch32 execution state on ARMv8.
+
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+---
+ arch/arm/include/asm/cputype.h | 2 ++
+ arch/arm/kvm/guest.c | 1 +
+ 2 files changed, 3 insertions(+)
+
+--- a/arch/arm/include/asm/cputype.h
++++ b/arch/arm/include/asm/cputype.h
+@@ -76,6 +76,8 @@
+ #define ARM_CPU_PART_CORTEX_A15 0x4100c0f0
+ #define ARM_CPU_PART_MASK 0xff00fff0
+
++#define ARM_CPU_PART_CORTEX_AARCH32_A53 0x4100d030
++
+ #define ARM_CPU_XSCALE_ARCH_MASK 0xe000
+ #define ARM_CPU_XSCALE_ARCH_V1 0x2000
+ #define ARM_CPU_XSCALE_ARCH_V2 0x4000
+--- a/arch/arm/kvm/guest.c
++++ b/arch/arm/kvm/guest.c
+@@ -247,6 +247,7 @@ int __attribute_const__ kvm_target_cpu(v
+ {
+ switch (read_cpuid_part()) {
+ case ARM_CPU_PART_CORTEX_A7:
++ case ARM_CPU_PART_CORTEX_AARCH32_A53:
+ return KVM_ARM_TARGET_CORTEX_A7;
+ case ARM_CPU_PART_CORTEX_A15:
+ return KVM_ARM_TARGET_CORTEX_A15;
--- /dev/null
+From 0157efe2fbe2fe56c34727d326cd74284c06cbd5 Mon Sep 17 00:00:00 2001
+From: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
+Date: Wed, 24 Aug 2016 10:51:21 +0800
+Subject: [PATCH 072/113] LS1012: Add PPFE driver in Linux
+
+commit 7584b690d4c8e4e435c2e6abcdb38d6595a0c302
+[context adjustment]
+[don't apply fsl-ls1012a-rdb.dts and fsl-ls1012a.dtsi]
+[Let PPFE driver can be selectd as a module]
+
+Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
+Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
+Integrated-by: Yutang Jiang <yutang.jiang@nxp.com>
+---
+ drivers/staging/Kconfig | 2 +
+ drivers/staging/Makefile | 1 +
+ drivers/staging/fsl_ppfe/Kconfig | 5 +
+ drivers/staging/fsl_ppfe/Makefile | 44 +
+ drivers/staging/fsl_ppfe/config.h | 8 +
+ drivers/staging/fsl_ppfe/control_link.lds | 32 +
+ drivers/staging/fsl_ppfe/include/pfe/cbus.h | 88 +
+ drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h | 55 +
+ .../staging/fsl_ppfe/include/pfe/cbus/class_csr.h | 242 ++
+ drivers/staging/fsl_ppfe/include/pfe/cbus/emac.h | 243 ++
+ .../staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h | 250 ++
+ drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h | 78 +
+ drivers/staging/fsl_ppfe/include/pfe/cbus/gpt.h | 29 +
+ drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h | 96 +
+ .../staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h | 51 +
+ .../staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h | 128 +
+ .../staging/fsl_ppfe/include/pfe/cbus/util_csr.h | 61 +
+ drivers/staging/fsl_ppfe/include/pfe/class.h | 133 +
+ drivers/staging/fsl_ppfe/include/pfe/class/ccu.h | 28 +
+ drivers/staging/fsl_ppfe/include/pfe/class/efet.h | 44 +
+ .../staging/fsl_ppfe/include/pfe/class/mac_hash.h | 55 +
+ drivers/staging/fsl_ppfe/include/pfe/class/perg.h | 39 +
+ .../staging/fsl_ppfe/include/pfe/class/vlan_hash.h | 46 +
+ drivers/staging/fsl_ppfe/include/pfe/gpt.h | 44 +
+ drivers/staging/fsl_ppfe/include/pfe/pe.h | 626 +++++
+ drivers/staging/fsl_ppfe/include/pfe/pfe.h | 444 +++
+ drivers/staging/fsl_ppfe/include/pfe/tmu.h | 68 +
+ .../staging/fsl_ppfe/include/pfe/tmu/phy_queue.h | 56 +
+ drivers/staging/fsl_ppfe/include/pfe/tmu/sched.h | 72 +
+ drivers/staging/fsl_ppfe/include/pfe/tmu/shaper.h | 37 +
+ drivers/staging/fsl_ppfe/include/pfe/uart.h | 31 +
+ drivers/staging/fsl_ppfe/include/pfe/util.h | 49 +
+ drivers/staging/fsl_ppfe/include/pfe/util/eape.h | 57 +
+ drivers/staging/fsl_ppfe/include/pfe/util/efet.h | 119 +
+ drivers/staging/fsl_ppfe/include/pfe/util/inq.h | 28 +
+ drivers/staging/fsl_ppfe/pfe_ctrl.c | 363 +++
+ drivers/staging/fsl_ppfe/pfe_ctrl.h | 111 +
+ drivers/staging/fsl_ppfe/pfe_ctrl_hal.c | 207 ++
+ drivers/staging/fsl_ppfe/pfe_ctrl_hal.h | 129 +
+ drivers/staging/fsl_ppfe/pfe_debugfs.c | 109 +
+ drivers/staging/fsl_ppfe/pfe_debugfs.h | 8 +
+ drivers/staging/fsl_ppfe/pfe_eth.c | 2956 ++++++++++++++++++++
+ drivers/staging/fsl_ppfe/pfe_eth.h | 384 +++
+ drivers/staging/fsl_ppfe/pfe_firmware.c | 322 +++
+ drivers/staging/fsl_ppfe/pfe_firmware.h | 41 +
+ drivers/staging/fsl_ppfe/pfe_hal.c | 2217 +++++++++++++++
+ drivers/staging/fsl_ppfe/pfe_hif.c | 939 +++++++
+ drivers/staging/fsl_ppfe/pfe_hif.h | 322 +++
+ drivers/staging/fsl_ppfe/pfe_hif_lib.c | 658 +++++
+ drivers/staging/fsl_ppfe/pfe_hif_lib.h | 219 ++
+ drivers/staging/fsl_ppfe/pfe_hw.c | 188 ++
+ drivers/staging/fsl_ppfe/pfe_hw.h | 32 +
+ drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c | 341 +++
+ drivers/staging/fsl_ppfe/pfe_mod.c | 140 +
+ drivers/staging/fsl_ppfe/pfe_mod.h | 163 ++
+ drivers/staging/fsl_ppfe/pfe_perfmon.c | 175 ++
+ drivers/staging/fsl_ppfe/pfe_perfmon.h | 41 +
+ drivers/staging/fsl_ppfe/pfe_platform.c | 358 +++
+ drivers/staging/fsl_ppfe/pfe_sysfs.c | 855 ++++++
+ drivers/staging/fsl_ppfe/pfe_sysfs.h | 34 +
+ drivers/staging/fsl_ppfe/platform.h | 25 +
+ include/linux/skbuff.h | 11 +
+ net/core/skbuff.c | 84 +
+ 63 files changed, 14821 insertions(+)
+ create mode 100644 drivers/staging/fsl_ppfe/Kconfig
+ create mode 100644 drivers/staging/fsl_ppfe/Makefile
+ create mode 100644 drivers/staging/fsl_ppfe/config.h
+ create mode 100644 drivers/staging/fsl_ppfe/control_link.lds
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/emac.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/gpt.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/class.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/class/ccu.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/class/efet.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/class/mac_hash.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/class/perg.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/class/vlan_hash.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/gpt.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/pe.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/pfe.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/tmu.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/tmu/phy_queue.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/tmu/sched.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/tmu/shaper.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/uart.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/util.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/util/eape.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/util/efet.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/util/inq.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl_hal.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl_hal.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hal.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_perfmon.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_perfmon.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_platform.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.h
+ create mode 100644 drivers/staging/fsl_ppfe/platform.h
+
+--- a/drivers/staging/Kconfig
++++ b/drivers/staging/Kconfig
+@@ -112,4 +112,6 @@ source "drivers/staging/wilc1000/Kconfig
+
+ source "drivers/staging/most/Kconfig"
+
++source "drivers/staging/fsl_ppfe/Kconfig"
++
+ endif # STAGING
+--- a/drivers/staging/Makefile
++++ b/drivers/staging/Makefile
+@@ -48,3 +48,4 @@ obj-$(CONFIG_FSL_MC_BUS) += fsl-mc/
+ obj-$(CONFIG_FSL_DPA) += fsl_qbman/
+ obj-$(CONFIG_WILC1000) += wilc1000/
+ obj-$(CONFIG_MOST) += most/
++obj-$(CONFIG_FSL_PPFE) += fsl_ppfe/
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/Kconfig
+@@ -0,0 +1,5 @@
++config FSL_PPFE
++ tristate "Freescale PPFE Driver"
++ default m
++ help
++ only compiled as module !
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/Makefile
+@@ -0,0 +1,44 @@
++#
++# Copyright (C) 2007 Freescale Semiconductor, Inc.
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++
++
++all: modules
++
++modules clean:
++ make CROSS_COMPILE=$(CROSS_COMPILE) ARCH=$(ARCH) -C $(KERNELDIR) M=`pwd` $@
++
++EXTRA_CFLAGS += -I$(src)/include -I$(src) -DCOMCERTO_2000 -DCONFIG_PLATFORM_LS1012A -DGEMAC_MTIP -DCONFIG_UTIL_DISABLED
++
++EXTRA_LDFLAGS += -T$(srctree)/$(src)/control_link.lds
++
++#only compiled as module !
++obj-$(CONFIG_FSL_PPFE) += pfe.o
++
++pfe-y += pfe_mod.o \
++ pfe_hw.o \
++ pfe_firmware.o \
++ pfe_ctrl.o \
++ pfe_ctrl_hal.o \
++ pfe_hif.o \
++ pfe_hif_lib.o\
++ pfe_eth.o \
++ pfe_perfmon.o \
++ pfe_sysfs.o \
++ pfe_debugfs.o \
++ pfe_ls1012a_platform.o \
++ pfe_hal.o \
++
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/config.h
+@@ -0,0 +1,8 @@
++#ifndef _CONFIG_H_
++#define _CONFIG_H_
++#define CFG_WIFI_OFFLOAD (1 << 1)
++#define CFG_ICC (1 << 11)
++#define CFG_RTP (1 << 14)
++#define CFG_ELLIPTIC (1 << 15)
++#define CFG_ALL (0 | CFG_WIFI_OFFLOAD | CFG_ICC | CFG_RTP | CFG_ELLIPTIC )
++#endif /* _CONFIG_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/control_link.lds
+@@ -0,0 +1,32 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++SECTIONS
++{
++ .class_dmem_sh : SUBALIGN(8) {
++ __class_dmem_sh = .;
++ *(SORT(.class_dmem_sh_*))
++ }
++
++ .tmu_dmem_sh : SUBALIGN(8) {
++ __tmu_dmem_sh = .;
++ *(SORT(.tmu_dmem_sh_*))
++ }
++
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus.h
+@@ -0,0 +1,88 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _CBUS_H_
++#define _CBUS_H_
++
++#define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000)
++#define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000)
++#define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000)
++#define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000)
++#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000)
++#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000)
++#define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000) /* FIXME not documented */
++#define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000) /* FIXME not documented */
++#define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000)
++#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000)
++#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000)
++#define LMEM_SIZE 0x10000
++#define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE)
++#define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000)
++#define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000)
++#if defined(CONFIG_PLATFORM_C2000)
++#define EMAC3_BASE_ADDR (CBUS_BASE_ADDR + 0x330000)
++#define EGPI3_BASE_ADDR (CBUS_BASE_ADDR + 0x340000)
++#endif
++#define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000)
++#define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000)
++#define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000)
++
++#define IS_LMEM(addr, len) (((unsigned long)(addr) >= (unsigned long)LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= (unsigned long)LMEM_END))
++
++/**
++* \defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR
++* XXX_MEM_ACCESS_ADDR register bit definitions.
++* @{
++*/
++#define PE_MEM_ACCESS_WRITE (1<<31) /**< Internal Memory Write. */
++#define PE_MEM_ACCESS_IMEM (1<<15)
++#define PE_MEM_ACCESS_DMEM (1<<16)
++#define PE_MEM_ACCESS_BYTE_ENABLE(offset,size) (((((1 << (size)) - 1) << (4 - (offset) - (size))) & 0xf) << 24) /**< Byte Enables of the Internal memory access. These are interpred in BE */
++// @}
++#if defined(CONFIG_PLATFORM_LS1012A)
++#include "cbus/emac_mtip.h"
++#else
++#include "cbus/emac.h"
++#endif //CONFIG_PLATFORM_LS1012A
++#include "cbus/gpi.h"
++#include "cbus/bmu.h"
++#include "cbus/hif.h"
++#include "cbus/tmu_csr.h"
++#include "cbus/class_csr.h"
++#include "cbus/hif_nocpy.h"
++#include "cbus/util_csr.h"
++#include "cbus/gpt.h"
++
++
++/* PFE cores states */
++#define CORE_DISABLE 0x00000000
++#define CORE_ENABLE 0x00000001
++#define CORE_SW_RESET 0x00000002
++
++/* LMEM defines */
++#define LMEM_HDR_SIZE 0x0010
++#define LMEM_BUF_SIZE_LN2 0x7
++#define LMEM_BUF_SIZE (1 << LMEM_BUF_SIZE_LN2)
++
++/* DDR defines */
++#define DDR_HDR_SIZE 0x0100
++#define DDR_BUF_SIZE_LN2 0xb
++#define DDR_BUF_SIZE (1 << DDR_BUF_SIZE_LN2)
++
++
++#endif /* _CBUS_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h
+@@ -0,0 +1,55 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _BMU_H_
++#define _BMU_H_
++
++#define BMU_VERSION 0x000
++#define BMU_CTRL 0x004
++#define BMU_UCAST_CONFIG 0x008
++#define BMU_UCAST_BASE_ADDR 0x00c
++#define BMU_BUF_SIZE 0x010
++#define BMU_BUF_CNT 0x014
++#define BMU_THRES 0x018
++#define BMU_INT_SRC 0x020
++#define BMU_INT_ENABLE 0x024
++#define BMU_ALLOC_CTRL 0x030
++#define BMU_FREE_CTRL 0x034
++#define BMU_FREE_ERR_ADDR 0x038
++#define BMU_CURR_BUF_CNT 0x03c
++#define BMU_MCAST_CNT 0x040
++#define BMU_MCAST_ALLOC_CTRL 0x044
++#define BMU_REM_BUF_CNT 0x048
++#define BMU_LOW_WATERMARK 0x050
++#define BMU_HIGH_WATERMARK 0x054
++#define BMU_INT_MEM_ACCESS 0x100
++
++typedef struct {
++ unsigned long baseaddr;
++ u32 count;
++ u32 size;
++} BMU_CFG;
++
++
++#define BMU1_BUF_SIZE LMEM_BUF_SIZE_LN2
++#define BMU2_BUF_SIZE DDR_BUF_SIZE_LN2
++
++#define BMU2_MCAST_ALLOC_CTRL BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL
++
++#endif /* _BMU_H_ */
++
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h
+@@ -0,0 +1,242 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _CLASS_CSR_H_
++#define _CLASS_CSR_H_
++
++/** @file class_csr.h.
++ * class_csr - block containing all the classifier control and status register. Mapped on CBUS and accessible from all PE's and ARM.
++ */
++
++
++#define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000)
++#define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004)
++#define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010)
++#define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014) /**< (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
++#define CLASS_HDR_SIZE_LMEM(off) ((off) & 0x3f) /**< LMEM header size for the Classifier block.\ Data in the LMEM is written from this offset. */
++#define CLASS_HDR_SIZE_DDR(off) (((off) & 0x1ff) << 16) /**< DDR header size for the Classifier block.\ Data in the DDR is written from this offset. */
++
++#define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020) /**< DMEM address of first [15:0] and second [31:16] buffers on QB side. */
++#define CLASS_PE0_QB_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x024) /**< DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
++
++#define CLASS_PE0_RO_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x060) /**< DMEM address of first [15:0] and second [31:16] buffers on RO side. */
++#define CLASS_PE0_RO_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x064) /**< DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
++
++/** @name Class PE memory access. Allows external PE's and HOST to read/write PMEM/DMEM memory ranges for each classifier PE.
++ */
++//@{
++#define CLASS_MEM_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x100) /**< {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]}, See \ref XXX_MEM_ACCESS_ADDR for details. */
++#define CLASS_MEM_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x104) /**< Internal Memory Access Write Data [31:0] */
++#define CLASS_MEM_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x108) /**< Internal Memory Access Read Data [31:0] */
++//@}
++#define CLASS_TM_INQ_ADDR (CLASS_CSR_BASE_ADDR + 0x114)
++#define CLASS_PE_STATUS (CLASS_CSR_BASE_ADDR + 0x118)
++
++#define CLASS_PHY1_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x11c)
++#define CLASS_PHY1_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x120)
++#define CLASS_PHY1_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x124)
++#define CLASS_PHY1_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x128)
++#define CLASS_PHY1_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x12c)
++#define CLASS_PHY1_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x130)
++#define CLASS_PHY1_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x134)
++#define CLASS_PHY1_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x138)
++#define CLASS_PHY1_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x13c)
++#define CLASS_PHY1_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x140)
++#define CLASS_PHY2_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x144)
++#define CLASS_PHY2_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x148)
++#define CLASS_PHY2_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x14c)
++#define CLASS_PHY2_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x150)
++#define CLASS_PHY2_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x154)
++#define CLASS_PHY2_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x158)
++#define CLASS_PHY2_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x15c)
++#define CLASS_PHY2_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x160)
++#define CLASS_PHY2_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x164)
++#define CLASS_PHY2_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x168)
++#define CLASS_PHY3_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x16c)
++#define CLASS_PHY3_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x170)
++#define CLASS_PHY3_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x174)
++#define CLASS_PHY3_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x178)
++#define CLASS_PHY3_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x17c)
++#define CLASS_PHY3_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x180)
++#define CLASS_PHY3_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x184)
++#define CLASS_PHY3_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x188)
++#define CLASS_PHY3_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x18c)
++#define CLASS_PHY3_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x190)
++#define CLASS_PHY1_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x194)
++#define CLASS_PHY1_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x198)
++#define CLASS_PHY1_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x19c)
++#define CLASS_PHY1_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a0)
++#define CLASS_PHY2_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a4)
++#define CLASS_PHY2_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a8)
++#define CLASS_PHY2_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1ac)
++#define CLASS_PHY2_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b0)
++#define CLASS_PHY3_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b4)
++#define CLASS_PHY3_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b8)
++#define CLASS_PHY3_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1bc)
++#define CLASS_PHY3_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c0)
++#define CLASS_PHY4_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c4)
++#define CLASS_PHY4_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c8)
++#define CLASS_PHY4_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1cc)
++#define CLASS_PHY4_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1d0)
++#define CLASS_PHY4_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d4)
++#define CLASS_PHY4_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d8)
++#define CLASS_PHY4_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1dc)
++#define CLASS_PHY4_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e0)
++#define CLASS_PHY4_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x1e4)
++#define CLASS_PHY4_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e8)
++#define CLASS_PHY4_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x1ec)
++#define CLASS_PHY4_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x1f0)
++#define CLASS_PHY4_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f4)
++#define CLASS_PHY4_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f8)
++
++#define CLASS_PE_SYS_CLK_RATIO (CLASS_CSR_BASE_ADDR + 0x200)
++#define CLASS_AFULL_THRES (CLASS_CSR_BASE_ADDR + 0x204)
++#define CLASS_GAP_BETWEEN_READS (CLASS_CSR_BASE_ADDR + 0x208)
++#define CLASS_MAX_BUF_CNT (CLASS_CSR_BASE_ADDR + 0x20c)
++#define CLASS_TSQ_FIFO_THRES (CLASS_CSR_BASE_ADDR + 0x210)
++#define CLASS_TSQ_MAX_CNT (CLASS_CSR_BASE_ADDR + 0x214)
++#define CLASS_IRAM_DATA_0 (CLASS_CSR_BASE_ADDR + 0x218)
++#define CLASS_IRAM_DATA_1 (CLASS_CSR_BASE_ADDR + 0x21c)
++#define CLASS_IRAM_DATA_2 (CLASS_CSR_BASE_ADDR + 0x220)
++#define CLASS_IRAM_DATA_3 (CLASS_CSR_BASE_ADDR + 0x224)
++
++#define CLASS_BUS_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x228)
++
++#define CLASS_BUS_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x22c)
++#define CLASS_BUS_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x230)
++
++#define CLASS_ROUTE_HASH_ENTRY_SIZE (CLASS_CSR_BASE_ADDR + 0x234) /**< (route_entry_size[9:0], route_hash_size[23:16] (this is actually ln2(size))) */
++#define CLASS_ROUTE_ENTRY_SIZE(size) ((size) & 0x1ff)
++#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
++
++#define CLASS_ROUTE_TABLE_BASE (CLASS_CSR_BASE_ADDR + 0x238)
++
++#define CLASS_ROUTE_MULTI (CLASS_CSR_BASE_ADDR + 0x23c)
++#define CLASS_SMEM_OFFSET (CLASS_CSR_BASE_ADDR + 0x240)
++#define CLASS_LMEM_BUF_SIZE (CLASS_CSR_BASE_ADDR + 0x244)
++#define CLASS_VLAN_ID (CLASS_CSR_BASE_ADDR + 0x248)
++#define CLASS_BMU1_BUF_FREE (CLASS_CSR_BASE_ADDR + 0x24c)
++#define CLASS_USE_TMU_INQ (CLASS_CSR_BASE_ADDR + 0x250)
++#define CLASS_VLAN_ID1 (CLASS_CSR_BASE_ADDR + 0x254)
++
++#define CLASS_BUS_ACCESS_BASE (CLASS_CSR_BASE_ADDR + 0x258)
++#define CLASS_BUS_ACCESS_BASE_MASK (0xFF000000) //bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE
++
++#define CLASS_HIF_PARSE (CLASS_CSR_BASE_ADDR + 0x25c)
++
++#define CLASS_HOST_PE0_GP (CLASS_CSR_BASE_ADDR + 0x260)
++#define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264)
++#define CLASS_HOST_PE1_GP (CLASS_CSR_BASE_ADDR + 0x268)
++#define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c)
++#define CLASS_HOST_PE2_GP (CLASS_CSR_BASE_ADDR + 0x270)
++#define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274)
++#define CLASS_HOST_PE3_GP (CLASS_CSR_BASE_ADDR + 0x278)
++#define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c)
++#define CLASS_HOST_PE4_GP (CLASS_CSR_BASE_ADDR + 0x280)
++#define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284)
++#define CLASS_HOST_PE5_GP (CLASS_CSR_BASE_ADDR + 0x288)
++#define CLASS_PE5_GP (CLASS_CSR_BASE_ADDR + 0x28c)
++
++#define CLASS_PE_INT_SRC (CLASS_CSR_BASE_ADDR + 0x290)
++#define CLASS_PE_INT_ENABLE (CLASS_CSR_BASE_ADDR + 0x294)
++
++#define CLASS_TPID0_TPID1 (CLASS_CSR_BASE_ADDR + 0x298)
++#define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c)
++
++#define CLASS_L4_CHKSUM_ADDR (CLASS_CSR_BASE_ADDR + 0x2a0)
++
++#define CLASS_PE0_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a4)
++#define CLASS_PE1_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a8)
++#define CLASS_PE2_DEBUG (CLASS_CSR_BASE_ADDR + 0x2ac)
++#define CLASS_PE3_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b0)
++#define CLASS_PE4_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b4)
++#define CLASS_PE5_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b8)
++
++#define CLASS_STATE (CLASS_CSR_BASE_ADDR + 0x2bc)
++
++/* CLASS defines */
++#define CLASS_PBUF_SIZE 0x100 /* Fixed by hardware */
++#define CLASS_PBUF_HEADER_OFFSET 0x80 /* Can be configured */
++
++#define CLASS_PBUF0_BASE_ADDR 0x000 /* Can be configured */
++#define CLASS_PBUF1_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE) /* Can be configured */
++#define CLASS_PBUF2_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE) /* Can be configured */
++#define CLASS_PBUF3_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE) /* Can be configured */
++
++#define CLASS_PBUF0_HEADER_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
++#define CLASS_PBUF1_HEADER_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
++#define CLASS_PBUF2_HEADER_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
++#define CLASS_PBUF3_HEADER_BASE_ADDR (CLASS_PBUF3_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
++
++#define CLASS_PE0_RO_DM_ADDR0_VAL ((CLASS_PBUF1_BASE_ADDR << 16) | CLASS_PBUF0_BASE_ADDR)
++#define CLASS_PE0_RO_DM_ADDR1_VAL ((CLASS_PBUF3_BASE_ADDR << 16) | CLASS_PBUF2_BASE_ADDR)
++
++#define CLASS_PE0_QB_DM_ADDR0_VAL ((CLASS_PBUF1_HEADER_BASE_ADDR << 16) | CLASS_PBUF0_HEADER_BASE_ADDR)
++#define CLASS_PE0_QB_DM_ADDR1_VAL ((CLASS_PBUF3_HEADER_BASE_ADDR << 16) | CLASS_PBUF2_HEADER_BASE_ADDR)
++
++#define CLASS_ROUTE_SIZE 128
++#define CLASS_MAX_ROUTE_SIZE 256
++#define CLASS_ROUTE_HASH_BITS 20
++#define CLASS_ROUTE_HASH_MASK ((1 << CLASS_ROUTE_HASH_BITS) - 1)
++
++#define CLASS_ROUTE0_BASE_ADDR 0x400 /* Can be configured */
++#define CLASS_ROUTE1_BASE_ADDR (CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE) /* Can be configured */
++#define CLASS_ROUTE2_BASE_ADDR (CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE) /* Can be configured */
++#define CLASS_ROUTE3_BASE_ADDR (CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE) /* Can be configured */
++
++#define CLASS_SA_SIZE 128
++#define CLASS_IPSEC_SA0_BASE_ADDR 0x600
++#define CLASS_IPSEC_SA1_BASE_ADDR (CLASS_IPSEC_SA0_BASE_ADDR + CLASS_SA_SIZE) /* not used */
++#define CLASS_IPSEC_SA2_BASE_ADDR (CLASS_IPSEC_SA1_BASE_ADDR + CLASS_SA_SIZE) /* not used */
++#define CLASS_IPSEC_SA3_BASE_ADDR (CLASS_IPSEC_SA2_BASE_ADDR + CLASS_SA_SIZE) /* not used */
++
++/* generic purpose free dmem buffer, last portion of 2K dmem pbuf */
++#define CLASS_GP_DMEM_BUF_SIZE (2048 - (CLASS_PBUF_SIZE*4) - (CLASS_ROUTE_SIZE*4) - (CLASS_SA_SIZE))
++#define CLASS_GP_DMEM_BUF ((void *)(CLASS_IPSEC_SA0_BASE_ADDR + CLASS_SA_SIZE))
++
++
++#define TWO_LEVEL_ROUTE (1 << 0)
++#define PHYNO_IN_HASH (1 << 1)
++#define HW_ROUTE_FETCH (1 << 3)
++#define HW_BRIDGE_FETCH (1 << 5)
++#define IP_ALIGNED (1 << 6)
++#define ARC_HIT_CHECK_EN (1 << 7)
++#define CLASS_TOE (1 << 11)
++#define HASH_NORMAL (0 << 12)
++#define HASH_CRC_PORT (1 << 12)
++#define HASH_CRC_IP (2 << 12)
++#define HASH_CRC_PORT_IP (3 << 12)
++#define QB2BUS_LE (1 << 15)
++
++#define TCP_CHKSUM_DROP (1 << 0)
++#define UDP_CHKSUM_DROP (1 << 1)
++#define IPV4_CHKSUM_DROP (1 << 9)
++
++/*CLASS_HIF_PARSE bits*/
++#define HIF_PKT_CLASS_EN (1 << 0)
++#define HIF_PKT_OFFSET(ofst) ((ofst&0xF) << 1)
++
++typedef struct {
++ u32 toe_mode;
++ unsigned long route_table_baseaddr;
++ u32 route_table_hash_bits;
++ u32 pe_sys_clk_ratio;
++ u32 resume;
++} CLASS_CFG;
++
++#endif /* _CLASS_CSR_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/emac.h
+@@ -0,0 +1,243 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _EMAC_H_
++#define _EMAC_H_
++
++#define EMAC_NETWORK_CONTROL 0x000
++#define EMAC_NETWORK_CONFIG 0x004
++#define EMAC_NETWORK_STATUS 0x008
++#define EMAC_DMA_CONFIG 0x010
++
++#define EMAC_PHY_MANAGEMENT 0x034
++
++#define EMAC_HASH_BOT 0x080
++#define EMAC_HASH_TOP 0x084
++
++#define EMAC_SPEC1_ADD_BOT 0x088
++#define EMAC_SPEC1_ADD_TOP 0x08c
++#define EMAC_SPEC2_ADD_BOT 0x090
++#define EMAC_SPEC2_ADD_TOP 0x094
++#define EMAC_SPEC3_ADD_BOT 0x098
++#define EMAC_SPEC3_ADD_TOP 0x09c
++#define EMAC_SPEC4_ADD_BOT 0x0a0
++#define EMAC_SPEC4_ADD_TOP 0x0a4
++#define EMAC_WOL 0x0b8
++
++#define EMAC_STACKED_VLAN_REG 0x0c0
++
++#define EMAC_SPEC1_ADD_MASK_BOT 0x0c8
++#define EMAC_SPEC1_ADD_MASK_TOP 0x0cc
++
++#define EMAC_RMON_BASE_OFST 0x100
++
++#define EMAC_SPEC5_ADD_BOT 0x300
++#define EMAC_SPEC5_ADD_TOP 0x304
++#define EMAC_SPEC6_ADD_BOT 0x308
++#define EMAC_SPEC6_ADD_TOP 0x30c
++#define EMAC_SPEC7_ADD_BOT 0x310
++#define EMAC_SPEC7_ADD_TOP 0x314
++#define EMAC_SPEC8_ADD_BOT 0x318
++#define EMAC_SPEC8_ADD_TOP 0x31c
++#define EMAC_SPEC9_ADD_BOT 0x320
++#define EMAC_SPEC9_ADD_TOP 0x324
++#define EMAC_SPEC10_ADD_BOT 0x328
++#define EMAC_SPEC10_ADD_TOP 0x32c
++#define EMAC_SPEC11_ADD_BOT 0x330
++#define EMAC_SPEC11_ADD_TOP 0x334
++#define EMAC_SPEC12_ADD_BOT 0x338
++#define EMAC_SPEC12_ADD_TOP 0x33c
++#define EMAC_SPEC13_ADD_BOT 0x340
++#define EMAC_SPEC13_ADD_TOP 0x344
++#define EMAC_SPEC14_ADD_BOT 0x348
++#define EMAC_SPEC14_ADD_TOP 0x34c
++#define EMAC_SPEC15_ADD_BOT 0x350
++#define EMAC_SPEC15_ADD_TOP 0x354
++#define EMAC_SPEC16_ADD_BOT 0x358
++#define EMAC_SPEC16_ADD_TOP 0x35c
++#define EMAC_SPEC17_ADD_BOT 0x360
++#define EMAC_SPEC17_ADD_TOP 0x364
++#define EMAC_SPEC18_ADD_BOT 0x368
++#define EMAC_SPEC18_ADD_TOP 0x36c
++#define EMAC_SPEC19_ADD_BOT 0x370
++#define EMAC_SPEC19_ADD_TOP 0x374
++#define EMAC_SPEC20_ADD_BOT 0x378
++#define EMAC_SPEC20_ADD_TOP 0x37c
++#define EMAC_SPEC21_ADD_BOT 0x380
++#define EMAC_SPEC21_ADD_TOP 0x384
++#define EMAC_SPEC22_ADD_BOT 0x388
++#define EMAC_SPEC22_ADD_TOP 0x38c
++#define EMAC_SPEC23_ADD_BOT 0x390
++#define EMAC_SPEC23_ADD_TOP 0x394
++#define EMAC_SPEC24_ADD_BOT 0x398
++#define EMAC_SPEC24_ADD_TOP 0x39c
++#define EMAC_SPEC25_ADD_BOT 0x3a0
++#define EMAC_SPEC25_ADD_TOP 0x3a4
++#define EMAC_SPEC26_ADD_BOT 0x3a8
++#define EMAC_SPEC26_ADD_TOP 0x3ac
++#define EMAC_SPEC27_ADD_BOT 0x3b0
++#define EMAC_SPEC27_ADD_TOP 0x3b4
++#define EMAC_SPEC28_ADD_BOT 0x3b8
++#define EMAC_SPEC28_ADD_TOP 0x3bc
++#define EMAC_SPEC29_ADD_BOT 0x3c0
++#define EMAC_SPEC29_ADD_TOP 0x3c4
++#define EMAC_SPEC30_ADD_BOT 0x3c8
++#define EMAC_SPEC30_ADD_TOP 0x3cc
++#define EMAC_SPEC31_ADD_BOT 0x3d0
++#define EMAC_SPEC31_ADD_TOP 0x3d4
++#define EMAC_SPEC32_ADD_BOT 0x3d8
++#define EMAC_SPEC32_ADD_TOP 0x3dc
++
++#define EMAC_SPEC_ADDR_MAX 32
++
++#define EMAC_CONTROL 0x7a0
++
++/* GEMAC definitions and settings */
++
++#define EMAC_PORT_0 0
++#define EMAC_PORT_1 1
++#define EMAC_PORT_2 2
++
++/* The possible operating speeds of the MAC, currently supporting 10, 100 and
++ * 1000Mb modes.
++ */
++typedef enum {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS} MAC_SPEED;
++
++#define GMII 1
++#define MII 2
++#define RMII 3
++#define RGMII 4
++#define SGMII 5
++
++#define DUP_HALF 0x00
++#define DUP_FULL 0x01
++
++/* EMAC_NETWORK_CONTROL bits definition */
++#define EMAC_LB_PHY (1 << 0)
++#define EMAC_LB_MAC (1 << 1)
++#define EMAC_RX_ENABLE (1 << 2)
++#define EMAC_TX_ENABLE (1 << 3)
++#define EMAC_MDIO_EN (1 << 4) /* Enable MDIO port */
++
++/* WoL (Wake on Lan bit definition) */
++#define EMAC_WOL_MAGIC (1 << 16)
++#define EMAC_WOL_ARP (1 << 17)
++#define EMAC_WOL_SPEC_ADDR (1 << 18)
++#define EMAC_WOL_MULTI (1 << 19)
++
++/* EMAC_NETWORK_CONFIG bits definition */
++#define EMAC_SPEED_100 (1 << 0)
++#define EMAC_HALF_DUP (0 << 1)
++#define EMAC_FULL_DUP (1 << 1)
++#define EMAC_DUPLEX_MASK (1 << 1)
++#define EMAC_ENABLE_JUMBO_FRAME (1 << 3)
++#define EMAC_ENABLE_COPY_ALL (1 << 4)
++#define EMAC_NO_BROADCAST (1 << 5)
++#define EMAC_ENABLE_MULTICAST (1 << 6)
++#define EMAC_ENABLE_UNICAST (1 << 7)
++#define EMAC_ENABLE_1536_RX (1 << 8)
++#define EMAC_SPEED_1000 (1 << 10)
++#define EMAC_PCS_ENABLE (1 << 11)
++#define EMAC_ENABLE_PAUSE_RX (1 << 13)
++#define EMAC_REMOVE_FCS (1 << 17)
++#define EMAC_ENABLE_CHKSUM_RX (1 << 24)
++#define EMAC_MDC_DIV_MASK (0x7 << 18) /* PCLK divisor for MDC */
++#define EMAC_DATA_BUS_WIDTH_SHIFT 21
++#define EMAC_DATA_BUS_WIDTH_MASK (0x3 << EMAC_DATA_BUS_WIDTH_SHIFT)
++#define EMAC_DATA_BUS_WIDTH_32 (0x00 << EMAC_DATA_BUS_WIDTH_SHIFT)
++#define EMAC_DATA_BUS_WIDTH_64 (0x01 << EMAC_DATA_BUS_WIDTH_SHIFT)
++#define EMAC_DATA_BUS_WIDTH_128 (0x10 << EMAC_DATA_BUS_WIDTH_SHIFT)
++#define EMAC_ENABLE_FCS_RX (1 << 26)
++#define EMAC_SGMII_MODE_ENABLE (1 << 27)
++
++#define EMAC_SPEED_MASK (EMAC_SPEED_100 | EMAC_SPEED_1000)
++
++/* EMAC_STACKED_VLAN_REG bits definition */
++#define EMAC_ENABLE_STACKED_VLAN (1 << 31)
++
++/* EMAC_CONTROL bits definition */
++#define EMAC_TWO_BYTES_IP_ALIGN (1 << 0) // two bytes IP alignement
++
++/* EMAC_NET_STATUS bits definition */
++#define EMAC_PHY_IDLE (1<<2) /* PHY management is idle */
++#define EMAC_MDIO_IN (1<<1) /* Status of mdio_in pin */
++#define EMAC_LINK_STATUS (1<<0) /* Status of link pin */
++
++/* EMAC_DMA_CONFIG Bit definitions */
++#define EMAC_ENABLE_CHKSUM_TX (1<<11)
++
++//RMII enable – bit 1 / RGMII enable – bit 2
++#define EMAC_RMII_MODE_ENABLE ((1 << 1) | (0 << 2))
++#define EMAC_RMII_MODE_DISABLE (0 << 1)
++#define EMAC_RGMII_MODE_ENABLE ((0 << 1) | (1 << 2))
++#define EMAC_RGMII_MODE_DISABLE (0 << 2)
++#define EMAC_MII_MODE_ENABLE (EMAC_RMII_MODE_DISABLE | EMAC_RGMII_MODE_DISABLE)
++#define EMAC_GMII_MODE_ENABLE (EMAC_RMII_MODE_DISABLE | EMAC_RGMII_MODE_DISABLE)
++#define EMAC_MODE_MASK (0x3 << 1)
++
++/* Default configuration */
++#define EMAC0_DEFAULT_DUPLEX_MODE FULLDUPLEX
++#define EMAC0_DEFAULT_EMAC_MODE RGMII
++#define EMAC0_DEFAULT_EMAC_SPEED SPEED_1000M
++
++#define EMAC1_DEFAULT_DUPLEX_MODE FULLDUPLEX
++#define EMAC1_DEFAULT_EMAC_MODE RGMII
++#define EMAC1_DEFAULT_EMAC_SPEED SPEED_1000M
++
++#define EMAC2_DEFAULT_DUPLEX_MODE FULLDUPLEX
++#define EMAC2_DEFAULT_EMAC_MODE RGMII
++#define EMAC2_DEFAULT_EMAC_SPEED SPEED_1000M
++
++/* EMAC Hash size */
++#define EMAC_HASH_REG_BITS 64
++
++/* The Address organisation for the MAC device. All addresses are split into
++ * two 32-bit register fields. The first one (bottom) is the lower 32-bits of
++ * the address and the other field are the high order bits - this may be 16-bits
++ * in the case of MAC addresses, or 32-bits for the hash address.
++ * In terms of memory storage, the first item (bottom) is assumed to be at a
++ * lower address location than 'top'. i.e. top should be at address location of
++ * 'bottom' + 4 bytes.
++ */
++typedef struct {
++ u32 bottom; /* Lower 32-bits of address. */
++ u32 top; /* Upper 32-bits of address. */
++} MAC_ADDR;
++
++
++/* The following is the organisation of the address filters section of the MAC
++ * registers. The Cadence MAC contains four possible specific address match
++ * addresses, if an incoming frame corresponds to any one of these four
++ * addresses then the frame will be copied to memory.
++ * It is not necessary for all four of the address match registers to be
++ * programmed, this is application dependant.
++ */
++typedef struct {
++ MAC_ADDR one; /* Specific address register 1. */
++ MAC_ADDR two; /* Specific address register 2. */
++ MAC_ADDR three; /* Specific address register 3. */
++ MAC_ADDR four; /* Specific address register 4. */
++} SPEC_ADDR;
++
++typedef struct {
++ u32 mode;
++ u32 speed;
++ u32 duplex;
++} GEMAC_CFG;
++
++#endif /* _EMAC_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h
+@@ -0,0 +1,250 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _EMAC_H_
++#define _EMAC_H_
++
++#define EMAC_IEVENT_REG 0x004
++#define EMAC_IMASK_REG 0x008
++#define EMAC_R_DES_ACTIVE_REG 0x010
++#define EMAC_X_DES_ACTIVE_REG 0x014
++#define EMAC_ECNTRL_REG 0x024
++#define EMAC_MII_DATA_REG 0x040
++#define EMAC_MII_CTRL_REG 0x044
++#define EMAC_MIB_CTRL_STS_REG 0x064
++#define EMAC_RCNTRL_REG 0x084
++#define EMAC_TCNTRL_REG 0x0C4
++#define EMAC_PHY_ADDR_LOW 0x0E4
++#define EMAC_PHY_ADDR_HIGH 0x0E8
++#define EMAC_GAUR 0x120
++#define EMAC_GALR 0x124
++#define EMAC_TFWR_STR_FWD 0x144
++#define EMAC_RX_SECTIOM_FULL 0x190
++#define EMAC_TX_SECTION_EMPTY 0x1A0
++#define EMAC_TRUNC_FL 0x1B0
++
++#define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */
++#define RMON_T_PACKETS 0x204 /* RMON TX packet count */
++#define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */
++#define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */
++#define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */
++#define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */
++#define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
++#define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */
++#define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
++#define RMON_T_COL 0x224 /* RMON TX collision count */
++#define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */
++#define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */
++#define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */
++#define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */
++#define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */
++#define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */
++#define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */
++#define RMON_T_OCTETS 0x244 /* RMON TX octets */
++#define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */
++#define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */
++#define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */
++#define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */
++#define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */
++#define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */
++#define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */
++#define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */
++#define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */
++#define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */
++#define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */
++#define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */
++#define RMON_R_PACKETS 0x284 /* RMON RX packet count */
++#define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */
++#define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */
++#define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */
++#define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */
++#define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
++#define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */
++#define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
++#define RMON_R_RESVD_O 0x2a4 /* Reserved */
++#define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */
++#define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */
++#define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */
++#define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */
++#define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */
++#define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */
++#define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */
++#define RMON_R_OCTETS 0x2c4 /* RMON RX octets */
++#define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */
++#define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */
++#define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */
++#define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */
++#define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */
++#define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */
++#define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */
++
++#define EMAC_SMAC_0_0 0x500 /*Supplemental MAC Address 0 (RW).*/
++#define EMAC_SMAC_0_1 0x504 /*Supplemental MAC Address 0 (RW).*/
++
++/* GEMAC definitions and settings */
++
++#define EMAC_PORT_0 0
++#define EMAC_PORT_1 1
++
++/* GEMAC Bit definitions */
++#define EMAC_IEVENT_HBERR 0x80000000
++#define EMAC_IEVENT_BABR 0x40000000
++#define EMAC_IEVENT_BABT 0x20000000
++#define EMAC_IEVENT_GRA 0x10000000
++#define EMAC_IEVENT_TXF 0x08000000
++#define EMAC_IEVENT_TXB 0x04000000
++#define EMAC_IEVENT_RXF 0x02000000
++#define EMAC_IEVENT_RXB 0x01000000
++#define EMAC_IEVENT_MII 0x00800000
++#define EMAC_IEVENT_EBERR 0x00400000
++#define EMAC_IEVENT_LC 0x00200000
++#define EMAC_IEVENT_RL 0x00100000
++#define EMAC_IEVENT_UN 0x00080000
++
++#define EMAC_IMASK_HBERR 0x80000000
++#define EMAC_IMASK_BABR 0x40000000
++#define EMAC_IMASKT_BABT 0x20000000
++#define EMAC_IMASK_GRA 0x10000000
++#define EMAC_IMASKT_TXF 0x08000000
++#define EMAC_IMASK_TXB 0x04000000
++#define EMAC_IMASKT_RXF 0x02000000
++#define EMAC_IMASK_RXB 0x01000000
++#define EMAC_IMASK_MII 0x00800000
++#define EMAC_IMASK_EBERR 0x00400000
++#define EMAC_IMASK_LC 0x00200000
++#define EMAC_IMASKT_RL 0x00100000
++#define EMAC_IMASK_UN 0x00080000
++
++#define EMAC_RCNTRL_MAX_FL_SHIFT 16
++#define EMAC_RCNTRL_LOOP 0x00000001
++#define EMAC_RCNTRL_DRT 0x00000002
++#define EMAC_RCNTRL_MII_MODE 0x00000004
++#define EMAC_RCNTRL_PROM 0x00000008
++#define EMAC_RCNTRL_BC_REJ 0x00000010
++#define EMAC_RCNTRL_FCE 0x00000020
++#define EMAC_RCNTRL_RGMII 0x00000040
++#define EMAC_RCNTRL_SGMII 0x00000080
++#define EMAC_RCNTRL_RMII 0x00000100
++#define EMAC_RCNTRL_RMII_10T 0x00000200
++#define EMAC_RCNTRL_CRC_FWD 0x00004000
++
++#define EMAC_TCNTRL_GTS 0x00000001
++#define EMAC_TCNTRL_HBC 0x00000002
++#define EMAC_TCNTRL_FDEN 0x00000004
++#define EMAC_TCNTRL_TFC_PAUSE 0x00000008
++#define EMAC_TCNTRL_RFC_PAUSE 0x00000010
++
++#define EMAC_ECNTRL_RESET 0x00000001 /* reset the EMAC */
++#define EMAC_ECNTRL_ETHER_EN 0x00000002 /* enable the EMAC */
++#define EMAC_ECNTRL_SPEED 0x00000020
++#define EMAC_ECNTRL_DBSWAP 0x00000100
++
++#define EMAC_X_WMRK_STRFWD 0x00000100
++
++#define EMAC_X_DES_ACTIVE_TDAR 0x01000000
++#define EMAC_R_DES_ACTIVE_RDAR 0x01000000
++
++
++
++/* The possible operating speeds of the MAC, currently supporting 10, 100 and
++ * 1000Mb modes.
++ */
++typedef enum {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS} MAC_SPEED;
++
++#define GMII 1
++#define MII 2
++#define RMII 3
++#define RGMII 4
++#define SGMII 5
++
++#define DUPLEX_HALF 0x00
++#define DUPLEX_FULL 0x01
++
++
++/* Default configuration */
++#define EMAC0_DEFAULT_DUPLEX_MODE FULLDUPLEX
++#define EMAC0_DEFAULT_EMAC_MODE RGMII
++#define EMAC0_DEFAULT_EMAC_SPEED SPEED_1000M
++
++#define EMAC1_DEFAULT_DUPLEX_MODE FULLDUPLEX
++#define EMAC1_DEFAULT_EMAC_MODE SGMII
++#define EMAC1_DEFAULT_EMAC_SPEED SPEED_1000M
++
++/* MII-related definitios */
++#define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
++#define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
++#define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
++#define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
++#define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
++#define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */
++#define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
++
++#define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
++#define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */
++#define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
++#define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */
++
++#define EMAC_MII_DATA_RA(v) ((v & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT)
++#define EMAC_MII_DATA_PA(v) ((v & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_PA_SHIFT)
++#define EMAC_MII_DATA(v) (v & 0xffff)
++
++#define EMAC_MII_SPEED_SHIFT 1
++#define EMAC_HOLDTIME_SHIFT 8
++#define EMAC_HOLDTIME_MASK 0x7
++#define EMAC_HOLDTIME(v) ((v & EMAC_HOLDTIME_MASK) << EMAC_HOLDTIME_SHIFT)
++
++/* The Address organisation for the MAC device. All addresses are split into
++ * two 32-bit register fields. The first one (bottom) is the lower 32-bits of
++ * the address and the other field are the high order bits - this may be 16-bits
++ * in the case of MAC addresses, or 32-bits for the hash address.
++ * In terms of memory storage, the first item (bottom) is assumed to be at a
++ * lower address location than 'top'. i.e. top should be at address location of
++ * 'bottom' + 4 bytes.
++ */
++typedef struct {
++ u32 bottom; /* Lower 32-bits of address. */
++ u32 top; /* Upper 32-bits of address. */
++} MAC_ADDR;
++
++
++/* The following is the organisation of the address filters section of the MAC
++ * registers. The Cadence MAC contains four possible specific address match
++ * addresses, if an incoming frame corresponds to any one of these four
++ * addresses then the frame will be copied to memory.
++ * It is not necessary for all four of the address match registers to be
++ * programmed, this is application dependant.
++ */
++typedef struct {
++ MAC_ADDR one; /* Specific address register 1. */
++ MAC_ADDR two; /* Specific address register 2. */
++ MAC_ADDR three; /* Specific address register 3. */
++ MAC_ADDR four; /* Specific address register 4. */
++} SPEC_ADDR;
++
++typedef struct {
++ u32 mode;
++ u32 speed;
++ u32 duplex;
++} GEMAC_CFG;
++
++/* EMAC Hash size */
++#define EMAC_HASH_REG_BITS 64
++
++#define EMAC_SPEC_ADDR_MAX 4
++
++#endif /* _EMAC_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h
+@@ -0,0 +1,78 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _GPI_H_
++#define _GPI_H_
++
++#define GPI_VERSION 0x00
++#define GPI_CTRL 0x04
++#define GPI_RX_CONFIG 0x08
++#define GPI_HDR_SIZE 0x0c
++#define GPI_BUF_SIZE 0x10
++#define GPI_LMEM_ALLOC_ADDR 0x14
++#define GPI_LMEM_FREE_ADDR 0x18
++#define GPI_DDR_ALLOC_ADDR 0x1c
++#define GPI_DDR_FREE_ADDR 0x20
++#define GPI_CLASS_ADDR 0x24
++#define GPI_DRX_FIFO 0x28
++#define GPI_TRX_FIFO 0x2c
++#define GPI_INQ_PKTPTR 0x30
++#define GPI_DDR_DATA_OFFSET 0x34
++#define GPI_LMEM_DATA_OFFSET 0x38
++#define GPI_TMLF_TX 0x4c
++#define GPI_DTX_ASEQ 0x50
++#define GPI_FIFO_STATUS 0x54
++#define GPI_FIFO_DEBUG 0x58
++#define GPI_TX_PAUSE_TIME 0x5c
++#define GPI_LMEM_SEC_BUF_DATA_OFFSET 0x60
++#define GPI_DDR_SEC_BUF_DATA_OFFSET 0x64
++#define GPI_TOE_CHKSUM_EN 0x68
++#define GPI_OVERRUN_DROPCNT 0x6c
++
++typedef struct {
++ u32 lmem_rtry_cnt;
++ u32 tmlf_txthres;
++ u32 aseq_len;
++} GPI_CFG;
++
++
++/* GPI commons defines */
++#define GPI_LMEM_BUF_EN 0x1
++#define GPI_DDR_BUF_EN 0x1
++
++/* EGPI 1 defines */
++#define EGPI1_LMEM_RTRY_CNT 0x40
++#define EGPI1_TMLF_TXTHRES 0xBC
++#define EGPI1_ASEQ_LEN 0x50
++
++/* EGPI 2 defines */
++#define EGPI2_LMEM_RTRY_CNT 0x40
++#define EGPI2_TMLF_TXTHRES 0xBC
++#define EGPI2_ASEQ_LEN 0x40
++
++/* EGPI 3 defines */
++#define EGPI3_LMEM_RTRY_CNT 0x40
++#define EGPI3_TMLF_TXTHRES 0xBC
++#define EGPI3_ASEQ_LEN 0x40
++
++/* HGPI defines */
++#define HGPI_LMEM_RTRY_CNT 0x40
++#define HGPI_TMLF_TXTHRES 0xBC
++#define HGPI_ASEQ_LEN 0x40
++
++#endif /* _GPI_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/gpt.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _CBUS_GPT_H_
++#define _CBUS_GPT_H_
++
++#define CBUS_GPT_VERSION (CBUS_GPT_BASE_ADDR + 0x00)
++#define CBUS_GPT_STATUS (CBUS_GPT_BASE_ADDR + 0x04)
++#define CBUS_GPT_CONFIG (CBUS_GPT_BASE_ADDR + 0x08)
++#define CBUS_GPT_COUNTER (CBUS_GPT_BASE_ADDR + 0x0c)
++#define CBUS_GPT_PERIOD (CBUS_GPT_BASE_ADDR + 0x10)
++#define CBUS_GPT_WIDTH (CBUS_GPT_BASE_ADDR + 0x14)
++
++#endif /* _CBUS_GPT_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h
+@@ -0,0 +1,96 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _HIF_H_
++#define _HIF_H_
++
++/** @file hif.h.
++ * hif - PFE hif block control and status register. Mapped on CBUS and accessible from all PE's and ARM.
++ */
++#define HIF_VERSION (HIF_BASE_ADDR + 0x00)
++#define HIF_TX_CTRL (HIF_BASE_ADDR + 0x04)
++#define HIF_TX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x08)
++#define HIF_TX_ALLOC (HIF_BASE_ADDR + 0x0c)
++#define HIF_TX_BDP_ADDR (HIF_BASE_ADDR + 0x10)
++#define HIF_TX_STATUS (HIF_BASE_ADDR + 0x14)
++#define HIF_RX_CTRL (HIF_BASE_ADDR + 0x20)
++#define HIF_RX_BDP_ADDR (HIF_BASE_ADDR + 0x24)
++#define HIF_RX_STATUS (HIF_BASE_ADDR + 0x30)
++#define HIF_INT_SRC (HIF_BASE_ADDR + 0x34)
++#define HIF_INT_ENABLE (HIF_BASE_ADDR + 0x38)
++#define HIF_POLL_CTRL (HIF_BASE_ADDR + 0x3c)
++#define HIF_RX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x40)
++#define HIF_RX_ALLOC (HIF_BASE_ADDR + 0x44)
++#define HIF_TX_DMA_STATUS (HIF_BASE_ADDR + 0x48)
++#define HIF_RX_DMA_STATUS (HIF_BASE_ADDR + 0x4c)
++#define HIF_INT_COAL (HIF_BASE_ADDR + 0x50)
++
++/*HIF_INT_SRC/ HIF_INT_ENABLE control bits */
++#define HIF_INT (1 << 0)
++#define HIF_RXBD_INT (1 << 1)
++#define HIF_RXPKT_INT (1 << 2)
++#define HIF_TXBD_INT (1 << 3)
++#define HIF_TXPKT_INT (1 << 4)
++
++/*HIF_TX_CTRL bits */
++#define HIF_CTRL_DMA_EN (1<<0)
++#define HIF_CTRL_BDP_POLL_CTRL_EN (1<<1)
++#define HIF_CTRL_BDP_CH_START_WSTB (1<<2)
++
++/*HIF_INT_ENABLE bits */
++#define HIF_INT_EN (1 << 0)
++#define HIF_RXBD_INT_EN (1 << 1)
++#define HIF_RXPKT_INT_EN (1 << 2)
++#define HIF_TXBD_INT_EN (1 << 3)
++#define HIF_TXPKT_INT_EN (1 << 4)
++
++/*HIF_POLL_CTRL bits*/
++#define HIF_RX_POLL_CTRL_CYCLE 0x0400
++#define HIF_TX_POLL_CTRL_CYCLE 0x0400
++
++/*HIF_INT_COAL bits*/
++#define HIF_INT_COAL_ENABLE (1 << 31)
++
++/*Buffer descriptor control bits */
++#define BD_CTRL_BUFLEN_MASK 0x3fff
++#define BD_BUF_LEN(x) (x & BD_CTRL_BUFLEN_MASK)
++#define BD_CTRL_CBD_INT_EN (1 << 16)
++#define BD_CTRL_PKT_INT_EN (1 << 17)
++#define BD_CTRL_LIFM (1 << 18)
++#define BD_CTRL_LAST_BD (1 << 19)
++#define BD_CTRL_DIR (1 << 20)
++#define BD_CTRL_LMEM_CPY (1 << 21) /*Valid only for HIF_NOCPY*/
++#define BD_CTRL_PKT_XFER (1 << 24)
++#define BD_CTRL_DESC_EN (1 << 31)
++#define BD_CTRL_PARSE_DISABLE (1 << 25)
++#define BD_CTRL_BRFETCH_DISABLE (1 << 26)
++#define BD_CTRL_RTFETCH_DISABLE (1 << 27)
++
++/*Buffer descriptor status bits*/
++#define BD_STATUS_CONN_ID(x) ((x) & 0xffff)
++#define BD_STATUS_DIR_PROC_ID (1 << 16)
++#define BD_STATUS_CONN_ID_EN (1 << 17))
++#define BD_STATUS_PE2PROC_ID(x) (((x) & 7) << 18)
++#define BD_STATUS_LE_DATA (1 << 21)
++#define BD_STATUS_CHKSUM_EN (1 << 22)
++
++/*HIF Buffer descriptor status bits */
++#define DIR_PROC_ID (1 << 16)
++#define PROC_ID(id) ((id) << 18)
++
++#endif /* _HIF_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h
+@@ -0,0 +1,51 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _HIF_NOCPY_H_
++#define _HIF_NOCPY_H_
++
++#define HIF_NOCPY_VERSION (HIF_NOCPY_BASE_ADDR + 0x00)
++#define HIF_NOCPY_TX_CTRL (HIF_NOCPY_BASE_ADDR + 0x04)
++#define HIF_NOCPY_TX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x08)
++#define HIF_NOCPY_TX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x0c)
++#define HIF_NOCPY_TX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x10)
++#define HIF_NOCPY_TX_STATUS (HIF_NOCPY_BASE_ADDR + 0x14)
++#define HIF_NOCPY_RX_CTRL (HIF_NOCPY_BASE_ADDR + 0x20)
++#define HIF_NOCPY_RX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x24)
++#define HIF_NOCPY_RX_STATUS (HIF_NOCPY_BASE_ADDR + 0x30)
++#define HIF_NOCPY_INT_SRC (HIF_NOCPY_BASE_ADDR + 0x34)
++#define HIF_NOCPY_INT_ENABLE (HIF_NOCPY_BASE_ADDR + 0x38)
++#define HIF_NOCPY_POLL_CTRL (HIF_NOCPY_BASE_ADDR + 0x3c)
++#define HIF_NOCPY_RX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x40)
++#define HIF_NOCPY_RX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x44)
++#define HIF_NOCPY_TX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x48)
++#define HIF_NOCPY_RX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x4c)
++#define HIF_NOCPY_RX_INQ0_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x50)
++#define HIF_NOCPY_RX_INQ1_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x54)
++#define HIF_NOCPY_TX_PORT_NO (HIF_NOCPY_BASE_ADDR + 0x60)
++#define HIF_NOCPY_LMEM_ALLOC_ADDR (HIF_NOCPY_BASE_ADDR + 0x64)
++#define HIF_NOCPY_CLASS_ADDR (HIF_NOCPY_BASE_ADDR + 0x68)
++#define HIF_NOCPY_TMU_PORT0_ADDR (HIF_NOCPY_BASE_ADDR + 0x70)
++#define HIF_NOCPY_TMU_PORT1_ADDR (HIF_NOCPY_BASE_ADDR + 0x74)
++#define HIF_NOCPY_TMU_PORT2_ADDR (HIF_NOCPY_BASE_ADDR + 0x7c)
++#define HIF_NOCPY_TMU_PORT3_ADDR (HIF_NOCPY_BASE_ADDR + 0x80)
++#define HIF_NOCPY_TMU_PORT4_ADDR (HIF_NOCPY_BASE_ADDR + 0x84)
++#define HIF_NOCPY_INT_COAL (HIF_NOCPY_BASE_ADDR + 0x90)
++
++
++#endif /* _HIF_NOCPY_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h
+@@ -0,0 +1,128 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _TMU_CSR_H_
++#define _TMU_CSR_H_
++
++#define TMU_VERSION (TMU_CSR_BASE_ADDR + 0x000)
++#define TMU_INQ_WATERMARK (TMU_CSR_BASE_ADDR + 0x004)
++#define TMU_PHY_INQ_PKTPTR (TMU_CSR_BASE_ADDR + 0x008)
++#define TMU_PHY_INQ_PKTINFO (TMU_CSR_BASE_ADDR + 0x00c)
++#define TMU_PHY_INQ_FIFO_CNT (TMU_CSR_BASE_ADDR + 0x010)
++#define TMU_SYS_GENERIC_CONTROL (TMU_CSR_BASE_ADDR + 0x014)
++#define TMU_SYS_GENERIC_STATUS (TMU_CSR_BASE_ADDR + 0x018)
++#define TMU_SYS_GEN_CON0 (TMU_CSR_BASE_ADDR + 0x01c)
++#define TMU_SYS_GEN_CON1 (TMU_CSR_BASE_ADDR + 0x020)
++#define TMU_SYS_GEN_CON2 (TMU_CSR_BASE_ADDR + 0x024)
++#define TMU_SYS_GEN_CON3 (TMU_CSR_BASE_ADDR + 0x028)
++#define TMU_SYS_GEN_CON4 (TMU_CSR_BASE_ADDR + 0x02c)
++#define TMU_TEQ_DISABLE_DROPCHK (TMU_CSR_BASE_ADDR + 0x030)
++#define TMU_TEQ_CTRL (TMU_CSR_BASE_ADDR + 0x034)
++#define TMU_TEQ_QCFG (TMU_CSR_BASE_ADDR + 0x038)
++#define TMU_TEQ_DROP_STAT (TMU_CSR_BASE_ADDR + 0x03c)
++#define TMU_TEQ_QAVG (TMU_CSR_BASE_ADDR + 0x040)
++#define TMU_TEQ_WREG_PROB (TMU_CSR_BASE_ADDR + 0x044)
++#define TMU_TEQ_TRANS_STAT (TMU_CSR_BASE_ADDR + 0x048)
++#define TMU_TEQ_HW_PROB_CFG0 (TMU_CSR_BASE_ADDR + 0x04c)
++#define TMU_TEQ_HW_PROB_CFG1 (TMU_CSR_BASE_ADDR + 0x050)
++#define TMU_TEQ_HW_PROB_CFG2 (TMU_CSR_BASE_ADDR + 0x054)
++#define TMU_TEQ_HW_PROB_CFG3 (TMU_CSR_BASE_ADDR + 0x058)
++#define TMU_TEQ_HW_PROB_CFG4 (TMU_CSR_BASE_ADDR + 0x05c)
++#define TMU_TEQ_HW_PROB_CFG5 (TMU_CSR_BASE_ADDR + 0x060)
++#define TMU_TEQ_HW_PROB_CFG6 (TMU_CSR_BASE_ADDR + 0x064)
++#define TMU_TEQ_HW_PROB_CFG7 (TMU_CSR_BASE_ADDR + 0x068)
++#define TMU_TEQ_HW_PROB_CFG8 (TMU_CSR_BASE_ADDR + 0x06c)
++#define TMU_TEQ_HW_PROB_CFG9 (TMU_CSR_BASE_ADDR + 0x070)
++#define TMU_TEQ_HW_PROB_CFG10 (TMU_CSR_BASE_ADDR + 0x074)
++#define TMU_TEQ_HW_PROB_CFG11 (TMU_CSR_BASE_ADDR + 0x078)
++#define TMU_TEQ_HW_PROB_CFG12 (TMU_CSR_BASE_ADDR + 0x07c)
++#define TMU_TEQ_HW_PROB_CFG13 (TMU_CSR_BASE_ADDR + 0x080)
++#define TMU_TEQ_HW_PROB_CFG14 (TMU_CSR_BASE_ADDR + 0x084)
++#define TMU_TEQ_HW_PROB_CFG15 (TMU_CSR_BASE_ADDR + 0x088)
++#define TMU_TEQ_HW_PROB_CFG16 (TMU_CSR_BASE_ADDR + 0x08c)
++#define TMU_TEQ_HW_PROB_CFG17 (TMU_CSR_BASE_ADDR + 0x090)
++#define TMU_TEQ_HW_PROB_CFG18 (TMU_CSR_BASE_ADDR + 0x094)
++#define TMU_TEQ_HW_PROB_CFG19 (TMU_CSR_BASE_ADDR + 0x098)
++#define TMU_TEQ_HW_PROB_CFG20 (TMU_CSR_BASE_ADDR + 0x09c)
++#define TMU_TEQ_HW_PROB_CFG21 (TMU_CSR_BASE_ADDR + 0x0a0)
++#define TMU_TEQ_HW_PROB_CFG22 (TMU_CSR_BASE_ADDR + 0x0a4)
++#define TMU_TEQ_HW_PROB_CFG23 (TMU_CSR_BASE_ADDR + 0x0a8)
++#define TMU_TEQ_HW_PROB_CFG24 (TMU_CSR_BASE_ADDR + 0x0ac)
++#define TMU_TEQ_HW_PROB_CFG25 (TMU_CSR_BASE_ADDR + 0x0b0)
++#define TMU_TDQ_IIFG_CFG (TMU_CSR_BASE_ADDR + 0x0b4)
++#define TMU_TDQ0_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x0b8) /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY0 */
++#define TMU_LLM_CTRL (TMU_CSR_BASE_ADDR + 0x0bc)
++#define TMU_LLM_BASE_ADDR (TMU_CSR_BASE_ADDR + 0x0c0)
++#define TMU_LLM_QUE_LEN (TMU_CSR_BASE_ADDR + 0x0c4)
++#define TMU_LLM_QUE_HEADPTR (TMU_CSR_BASE_ADDR + 0x0c8)
++#define TMU_LLM_QUE_TAILPTR (TMU_CSR_BASE_ADDR + 0x0cc)
++#define TMU_LLM_QUE_DROPCNT (TMU_CSR_BASE_ADDR + 0x0d0)
++#define TMU_INT_EN (TMU_CSR_BASE_ADDR + 0x0d4)
++#define TMU_INT_SRC (TMU_CSR_BASE_ADDR + 0x0d8)
++#define TMU_INQ_STAT (TMU_CSR_BASE_ADDR + 0x0dc)
++#define TMU_CTRL (TMU_CSR_BASE_ADDR + 0x0e0)
++
++#define TMU_MEM_ACCESS_ADDR (TMU_CSR_BASE_ADDR + 0x0e4) /**< [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory Write [27:24] Byte Enables of the Internal memory access [23:0] Address of the internal memory. This address is used to access both the PM and DM of all the PE's */
++#define TMU_MEM_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x0e8) /**< Internal Memory Access Write Data */
++#define TMU_MEM_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x0ec) /**< Internal Memory Access Read Data. The commands are blocked at the mem_access only */
++
++#define TMU_PHY0_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f0) /**< [31:0] PHY0 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
++#define TMU_PHY1_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f4) /**< [31:0] PHY1 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
++#define TMU_PHY2_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f8) /**< [31:0] PHY2 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
++#define TMU_PHY3_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0fc) /**< [31:0] PHY3 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
++#define TMU_BMU_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x100)
++#define TMU_TX_CTRL (TMU_CSR_BASE_ADDR + 0x104)
++
++#define TMU_BUS_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x108)
++#define TMU_BUS_ACCESS (TMU_CSR_BASE_ADDR + 0x10c)
++#define TMU_BUS_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x110)
++
++#define TMU_PE_SYS_CLK_RATIO (TMU_CSR_BASE_ADDR + 0x114)
++#define TMU_PE_STATUS (TMU_CSR_BASE_ADDR + 0x118)
++#define TMU_TEQ_MAX_THRESHOLD (TMU_CSR_BASE_ADDR + 0x11c)
++#define TMU_PHY4_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x134) /**< [31:0] PHY4 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
++#define TMU_TDQ1_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x138) /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY1 */
++#define TMU_TDQ2_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x13c) /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY2 */
++#define TMU_TDQ3_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x140) /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY3 */
++#define TMU_BMU_BUF_SIZE (TMU_CSR_BASE_ADDR + 0x144)
++#define TMU_PHY5_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x148) /**< [31:0] PHY5 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
++
++#define SW_RESET (1 << 0) /**< Global software reset */
++#define INQ_RESET (1 << 2)
++#define TEQ_RESET (1 << 3)
++#define TDQ_RESET (1 << 4)
++#define PE_RESET (1 << 5)
++#define MEM_INIT (1 << 6)
++#define MEM_INIT_DONE (1 << 7)
++#define LLM_INIT (1 << 8)
++#define LLM_INIT_DONE (1 << 9)
++#define ECC_MEM_INIT_DONE (1<<10)
++
++typedef struct {
++ u32 pe_sys_clk_ratio;
++ unsigned long llm_base_addr;
++ u32 llm_queue_len;
++} TMU_CFG;
++
++/* Not HW related for pfe_ctrl / pfe common defines */
++#define DEFAULT_MAX_QDEPTH 80
++#define DEFAULT_Q0_QDEPTH 511 //We keep one large queue for host tx qos
++#define DEFAULT_TMU3_QDEPTH 127
++
++
++#endif /* _TMU_CSR_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h
+@@ -0,0 +1,61 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _UTIL_CSR_H_
++#define _UTIL_CSR_H_
++
++#define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000)
++#define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004)
++#define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010)
++
++#define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014)
++
++#define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020)
++#define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024)
++#define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060)
++#define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064)
++
++#define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100)
++#define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104)
++#define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108)
++
++#define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114)
++#define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118)
++
++#define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200)
++#define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204)
++#define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208)
++#define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c)
++#define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210)
++#define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214)
++#define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218)
++#define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c)
++#define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220)
++#define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224)
++
++#define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228)
++#define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c)
++#define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230)
++
++#define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234)
++
++typedef struct {
++ u32 pe_sys_clk_ratio;
++} UTIL_CFG;
++
++#endif /* _UTIL_CSR_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/class.h
+@@ -0,0 +1,133 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _CLASS_H_
++#define _CLASS_H_
++
++#include "pe.h"
++
++#define CLASS_DMEM_BASE_ADDR 0x00000000
++#define CLASS_DMEM_SIZE 0x2000
++#define CLASS_DMEM_END (CLASS_DMEM_BASE_ADDR + CLASS_DMEM_SIZE)
++#define CLASS_PMEM_BASE_ADDR 0x00010000
++
++#define CBUS_BASE_ADDR 0xc0000000
++#define CLASS_APB_BASE_ADDR 0xc1000000
++#define CLASS_AHB1_BASE_ADDR 0xc2000000
++#define CLASS_AHB2_BASE_ADDR 0xc3000000
++
++#include "cbus.h"
++
++#define GPT_BASE_ADDR (CLASS_APB_BASE_ADDR + 0x00000)
++#define UART_BASE_ADDR (CLASS_APB_BASE_ADDR + 0x10000)
++#define PERG_BASE_ADDR (CLASS_APB_BASE_ADDR + 0x20000)
++#define EFET_BASE_ADDR (CLASS_APB_BASE_ADDR + 0x40000)
++
++#define MAC_HASH_BASE_ADDR (CLASS_AHB1_BASE_ADDR + 0x30000)
++#define VLAN_HASH_BASE_ADDR (CLASS_AHB1_BASE_ADDR + 0x50000)
++
++#define PE_LMEM_BASE_ADDR (CLASS_AHB2_BASE_ADDR + 0x10000)
++#define PE_LMEM_SIZE 0x8000
++#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
++#define CCU_BASE_ADDR (CLASS_AHB2_BASE_ADDR + 0x20000)
++
++#define IS_DMEM(addr, len) (((unsigned long)(addr) >= CLASS_DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= CLASS_DMEM_END))
++#define IS_PE_LMEM(addr, len) (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PE_LMEM_END))
++
++
++#include "gpt.h"
++#include "uart.h"
++#include "class/perg.h"
++#include "class/efet.h"
++#include "class/mac_hash.h"
++#include "class/vlan_hash.h"
++#include "class/ccu.h"
++
++
++#define CLASS_MAX_PBUFFERS 4
++
++#define PBUF_HWPARSE_OFFSET 0x10 /* Fixed by hardware */
++
++#define PAYLOAD_DMEM_MAX_SIZE (CLASS_PBUF_SIZE - CLASS_PBUF_HEADER_OFFSET - sizeof(class_rx_hdr_t))
++
++
++#define MIN_PKT_SIZE 56
++
++#define PARSE_ETH_TYPE (1 << 0)
++#define PARSE_VLAN_TYPE (1 << 1)
++#define PARSE_PPPOE_TYPE (1 << 2)
++#define PARSE_ARP_TYPE (1 << 3)
++#define PARSE_MCAST_TYPE (1 << 4)
++#define PARSE_IP_TYPE (1 << 5)
++#define PARSE_IPV6_TYPE (1 << 6)
++#define PARSE_IPV4_TYPE (1 << 7)
++
++#define PARSE_IPX_TYPE (1 << 9)
++
++#define PARSE_UDP_FLOW (1 << 11)
++#define PARSE_TCP_FLOW (1 << 12)
++#define PARSE_ICMP_FLOW (1 << 13)
++#define PARSE_IGMP_FLOW (1 << 14)
++#define PARSE_FRAG_FLOW (1 << 15)
++
++#define PARSE_HIF_PKT (1 << 23)
++#define PARSE_ARC_HIT (1 << 24)
++#define PARSE_PKT_OVERFLOW (1 << 25)
++
++#define PARSE_PROTO_MISMATCH (1 << 28)
++#define PARSE_L3_MISMATCH (1 << 29)
++#define PARSE_L2_MISMATCH (1 << 30)
++#define PARSE_INCOMPLETE (1 << 31)
++
++
++typedef struct _hwparse_t {
++ u16 sid;
++ u16 connid;
++ u8 toevec;
++ u8 pLayer2Hdr;
++ u8 pLayer3Hdr;
++ u8 pLayer4Hdr;
++ u16 vlanid;
++ u16 ifParseFlags;
++ u32 parseFlags;
++ u16 srcport;
++ u16 dstport;
++ u32 proto:8;
++ u32 port:4;
++ u32 hash:20;
++ u64 rte_res_valid:1;
++ u64 vlan_res_valid:1;
++ u64 dst_res_valid:1;
++ u64 src_res_valid:1;
++ u64 vlan_lookup:20;
++ u64 dst_lookup:20;
++ u64 src_lookup:20;
++} hwparse_t;
++
++
++typedef struct {
++ u8 num_cpy; /* no of copies to send out from RO block, for each there must be a corresponding tx pre-header */
++ u8 dma_len; /* len to be DMAed to DDR mem, including all tx pre-headers */
++ u16 src_addr; /* class dmem source address, pointing to first tx pre-header */
++ u32 dst_addr; /* DDR memory destination address of first tx pre-header, must be so packet data is continuous in DDR */
++ u32 res1; /* reserved for software usage - queue number? */
++ u16 res2; /* reserved for software usage */
++ u16 tsv; /* time stamp val */
++} class_tx_desc_t;
++
++#endif /* _CLASS_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/class/ccu.h
+@@ -0,0 +1,28 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _CCU_H_
++#define _CCU_H_
++
++#define CCU_ADDR (CCU_BASE_ADDR + 0x00)
++#define CCU_CNT (CCU_BASE_ADDR + 0x04)
++#define CCU_STATUS (CCU_BASE_ADDR + 0x08)
++#define CCU_VAL (CCU_BASE_ADDR + 0x0c)
++
++#endif /* _CCU_H_ */
++
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/class/efet.h
+@@ -0,0 +1,44 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _CLASS_EFET_H_
++#define _CLASS_EFET_H_
++
++//#define CLASS_EFET_ASYNC 1
++
++#define CLASS_EFET_ENTRY_ADDR (EFET_BASE_ADDR + 0x00)
++#define CLASS_EFET_ENTRY_SIZE (EFET_BASE_ADDR + 0x04)
++#define CLASS_EFET_ENTRY_DMEM_ADDR (EFET_BASE_ADDR + 0x08)
++#define CLASS_EFET_ENTRY_STATUS (EFET_BASE_ADDR + 0x0c)
++#define CLASS_EFET_ENTRY_ENDIAN (EFET_BASE_ADDR + 0x10)
++
++#define CBUS2DMEM 0
++#define DMEM2CBUS 1
++
++#define EFET2BUS_LE (1 << 0)
++#define PE2BUS_LE (1 << 1)
++
++#ifdef CLASS_EFET_ASYNC
++void class_efet_async(u32 cbus_addr, u32 dmem_addr, u32 len, u32 dir);
++#endif
++
++void class_efet_sync(u32 cbus_addr, u32 dmem_addr, u32 len, u32 dir);
++
++
++#endif /* _CLASS_EFET_H_ */
++
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/class/mac_hash.h
+@@ -0,0 +1,55 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _MAC_HASH_H_
++#define _MAC_HASH_H_
++
++#define MAC_HASH_REQ1_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x000)
++#define MAC_HASH_REQ2_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x020)
++#define MAC_HASH_REQ3_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x040)
++#define MAC_HASH_REQ4_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x060)
++#define MAC_HASH_REQ5_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x080)
++#define MAC_HASH_REQ6_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x0a0)
++#define MAC_HASH_REQ7_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x0c0)
++#define MAC_HASH_REQ8_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x0e0)
++
++#define MAC_HASH_REQ_CMD(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x000)
++#define MAC_HASH_REQ_MAC1_ADDR(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x004)
++#define MAC_HASH_REQ_MAC2_ADDR(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x008)
++#define MAC_HASH_REQ_MASK1_ADDR(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x00c)
++#define MAC_HASH_REQ_MASK2_ADDR(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x010)
++#define MAC_HASH_REQ_ENTRY(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x014)
++#define MAC_HASH_REQ_STATUS(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x018)
++#define MAC_HASH_REQ_ENTRY_MAYCH(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x01c)
++
++
++#define MAC_HASH_FREELIST_PTR_HEAD (MAC_HASH_BASE_ADDR + 0x100)
++#define MAC_HASH_FREELIST_PTR_TAIL (MAC_HASH_BASE_ADDR + 0x104)
++#define MAC_HASH_FREELIST_ENTRIES_ADDR (MAC_HASH_BASE_ADDR + 0x108)
++
++
++#define HASH_CMD_INIT 1
++#define HASH_CMD_ADD 2
++#define HASH_CMD_DELETE 3
++#define HASH_CMD_UPDATE 4
++#define HASH_CMD_SEARCH 5
++#define HASH_CMD_MEM_READ 6
++#define HASH_CMD_MEM_WRITE 7
++
++#endif /* _MAC_HASH_H_ */
++
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/class/perg.h
+@@ -0,0 +1,39 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _PERG_H_
++#define _PERG_H_
++
++#define PERG_QB_BUF_STATUS (PERG_BASE_ADDR + 0x00)
++#define PERG_RO_BUF_STATUS (PERG_BASE_ADDR + 0x04)
++#define PERG_CLR_QB_BUF_STATUS (PERG_BASE_ADDR + 0x08)
++#define PERG_SET_RO_BUF_STATUS (PERG_BASE_ADDR + 0x0c)
++#define PERG_CLR_RO_ERR_PKT (PERG_BASE_ADDR + 0x10)
++#define PERG_CLR_BMU2_ERR_PKT (PERG_BASE_ADDR + 0x14)
++
++#define PERG_ID (PERG_BASE_ADDR + 0x18)
++#define PERG_TIMER1 (PERG_BASE_ADDR + 0x1c)
++//FIXME #define PERG_TIMER2 (PERG_BASE_ADDR + 0x20)
++#define PERG_BMU1_CURRDEPTH (PERG_BASE_ADDR + 0x20)
++#define PERG_BMU2_CURRDEPTH (PERG_BASE_ADDR + 0x24)
++#define PERG_HOST_GP (PERG_BASE_ADDR + 0x2c)
++#define PERG_PE_GP (PERG_BASE_ADDR + 0x30)
++#define PERG_INT_ENABLE (PERG_BASE_ADDR + 0x34)
++#define PERG_INT_SRC (PERG_BASE_ADDR + 0x38)
++
++#endif /* _PERG_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/class/vlan_hash.h
+@@ -0,0 +1,46 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _VLAN_HASH_H_
++#define _VLAN_HASH_H_
++
++#define VLAN_HASH_REQ1_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x000)
++#define VLAN_HASH_REQ2_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x020)
++#define VLAN_HASH_REQ3_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x040)
++#define VLAN_HASH_REQ4_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x060)
++#define VLAN_HASH_REQ5_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x080)
++#define VLAN_HASH_REQ6_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x0a0)
++#define VLAN_HASH_REQ7_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x0c0)
++#define VLAN_HASH_REQ8_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x0e0)
++
++#define VLAN_HASH_REQ_CMD(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x000)
++#define VLAN_HASH_REQ_MAC1_ADDR(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x004)
++#define VLAN_HASH_REQ_MAC2_ADDR(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x008)
++#define VLAN_HASH_REQ_MASK1_ADDR(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x00c)
++#define VLAN_HASH_REQ_MASK2_ADDR(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x010)
++#define VLAN_HASH_REQ_ENTRY(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x014)
++#define VLAN_HASH_REQ_STATUS(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x018)
++#define VLAN_HASH_REQ_ENTRY_MAYCH(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x01c)
++
++
++#define VLAN_HASH_FREELIST_PTR_HEAD (VLAN_HASH_BASE_ADDR + 0x100)
++#define VLAN_HASH_FREELIST_PTR_TAIL (VLAN_HASH_BASE_ADDR + 0x104)
++#define VLAN_HASH_FREELIST_ENTRIES_ADDR (VLAN_HASH_BASE_ADDR + 0x108)
++
++#endif /* _VLAN_HASH_H_ */
++
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/gpt.h
+@@ -0,0 +1,44 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _GPT_H_
++#define _GPT_H_
++
++#define GPT_VERSION (GPT_BASE_ADDR + 0x00)
++#define GPT_STATUS (GPT_BASE_ADDR + 0x04)
++#define GPT_CONFIG (GPT_BASE_ADDR + 0x08)
++#define GPT_COUNTER (GPT_BASE_ADDR + 0x0c)
++#define GPT_PERIOD (GPT_BASE_ADDR + 0x10)
++#define GPT_WIDTH (GPT_BASE_ADDR + 0x14)
++
++/*** These bits are defined for GPT_STATUS register */
++#define GPT_STAT_IRQ (1<<0)
++#define GPT_STAT_OVERFLOW_ERR (1<<4)
++#define GPT_STAT_TMR_ENABLE (1<<8)
++#define GPT_STAT_TMR_DISABLE (1<<9)
++
++/*** These bits are defined for GPT_CONFIG register */
++#define GPT_CONFIG_PWM_MODE 0x1
++#define GPT_CONFIG_WCAP_MODE 0x2
++#define GPT_CONFIG_CAP_PULSE_OUT (1<<2)
++#define GPT_CONFIG_PERIOD_CNT (1<<3)
++#define GPT_CONFIG_INTR_ENABLE (1<<4)
++#define GPT_CONFIG_AUX_SEL (1<<5)
++
++
++#endif /* _GPT_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/pe.h
+@@ -0,0 +1,626 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _PE_H_
++#define _PE_H_
++
++#include "hal.h"
++
++#if defined(COMCERTO_2000_CLASS)
++#include "pfe/class.h"
++#elif defined(COMCERTO_2000_TMU)
++#include "pfe/tmu.h"
++#elif defined(COMCERTO_2000_UTIL)
++#include "pfe/util.h"
++#endif
++
++enum {
++ CLASS0_ID = 0,
++ CLASS1_ID,
++ CLASS2_ID,
++ CLASS3_ID,
++ CLASS4_ID,
++ CLASS5_ID,
++ TMU0_ID,
++ TMU1_ID,
++ TMU2_ID,
++ TMU3_ID,
++ UTIL_ID,
++ MAX_PE
++};
++#define PE_ID_ANY MAX_PE
++
++/* Hardware definition of physical ports */
++/* CLASS rx header phy number */
++enum CLASS_RX_PHY {
++ RX_PHY_0 = 0x0,
++ RX_PHY_1,
++ RX_PHY_2,
++ RX_PHY_HIF,
++ RX_PHY_HIF_NOCPY,
++ RX_PHY_CLASS = 1 << 14, /**< Control bit (in PHYNO field) used to inform CLASS PE that packet comes from Class. */
++ RX_PHY_UTIL = 1 << 15 /**< Control bit (in PHYNO field) used to inform CLASS PE that packet comes from UtilPE. */
++};
++
++#define RX_PHY_SW_INPUT_PORT_OFFSET 11 /**< Offset in PHYNO field where the original input port will be stored for packets coming directly from software (UtilPE or Class). */
++
++
++/* CLASS/TMU tx header phy number */
++enum TMU_TX_PHY {
++ TX_PHY_TMU0 = 0x0,
++ TX_PHY_TMU1,
++ TX_PHY_TMU2,
++ TX_PHY_TMU3
++};
++
++
++// NOTE: Any changes to the following drop counter definitions must also
++// be reflected in the pfe/pfe.h file and in pfe_ctrl/pfe_sysfs.c.
++
++#if defined(COMCERTO_2000_CLASS)
++
++#define CLASS_DROP_ICC 0
++#define CLASS_DROP_HOST_PKT_ERROR 1
++#define CLASS_DROP_RX_ERROR 2
++#define CLASS_DROP_IPSEC_OUT 3
++#define CLASS_DROP_IPSEC_IN 4
++#define CLASS_DROP_EXPT_IPSEC 5
++#define CLASS_DROP_REASSEMBLY 6
++#define CLASS_DROP_FRAGMENTER 7
++#define CLASS_DROP_NATT 8
++#define CLASS_DROP_SOCKET 9
++#define CLASS_DROP_MULTICAST 10
++#define CLASS_DROP_NATPT 11
++#define CLASS_DROP_TX_DISABLE 12
++
++#define CLASS_NUM_DROP_COUNTERS 13
++
++extern U32 drop_counter[CLASS_NUM_DROP_COUNTERS];
++#define DROP_PACKET(pmtd, counter) free_packet(pmtd, CLASS_DROP_##counter)
++#define DROP_BUFFER(addr, counter) free_buffer(addr, CLASS_DROP_##counter)
++
++#elif defined(COMCERTO_2000_UTIL)
++
++#define UTIL_DROP_IPSEC_OUT 0
++#define UTIL_DROP_IPSEC_IN 1
++#define UTIL_DROP_IPSEC_RATE_LIMIT 2
++#define UTIL_DROP_FRAGMENTER 3
++#define UTIL_DROP_SOCKET 4
++#define UTIL_DROP_TX_DISABLE 5
++#define UTIL_DROP_RX_ERROR 6
++#define UTIL_DROP_NO_MTD 7
++
++#define UTIL_NUM_DROP_COUNTERS 8
++
++extern U32 drop_counter[UTIL_NUM_DROP_COUNTERS];
++#define DROP_PACKET(pmtd, counter) free_packet(pmtd, UTIL_DROP_##counter)
++#define DROP_BUFFER(addr, counter) free_buffer(addr, UTIL_DROP_##counter)
++
++#endif
++
++
++
++#define DDR_BASE_ADDR 0x00020000
++#define DDR_END 0x86000000 /* This includes ACP and IRAM areas */
++#define IRAM_BASE_ADDR 0x83000000
++
++#define IS_DDR(addr, len) (((unsigned long)(addr) >= DDR_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= DDR_END))
++/* action bits of act_phyno is defined as follows */
++
++#define ACT_SRC_MAC_REPLACE (1 << (4 + 0))
++#define ACT_VLAN_ADD (1 << (4 + 1))
++#define ACT_TCPCHKSUM_REPLACE (1 << (4 + 2))
++#define ACT_VLAN_REPLACE (1 << (4 + 3))
++#define ACT_DONT_FREE_BUFFER (1 << (4 + 5))
++#define ACT_IPCHKSUM_REPLACE (1 << (4 + 6))
++
++typedef struct {
++ u8 start_data_off; /* packet data start offset, relative to start of this tx pre-header */
++ u8 start_buf_off; /* this tx pre-header start offset, relative to start of DDR buffer */
++ u16 pkt_length; /* total packet length */
++ u8 act_phyno; /* action / phy number */
++ u8 queueno; /* queueno */
++ u16 unused;
++} class_tx_hdr_t;
++
++typedef struct {
++ u8 start_data_off; /* packet data start offset, relative to start of this tx pre-header */
++ u8 start_buf_off; /* this tx pre-header start offset, relative to start of DDR buffer */
++ u16 pkt_length; /* total packet length */
++ u8 act_phyno; /* action / phy number */
++ u8 queueno; /* queueno */
++ u16 src_mac_msb; /* indicates src_mac 47:32 */
++ u32 src_mac_lsb; /* indicates src_mac 31:0 */
++ u32 vlanid; /* vlanid */
++} class_tx_hdr_mc_t;
++
++typedef struct {
++ u32 next_ptr; /* ptr to the start of the first DDR buffer */
++ u16 length; /* total packet length */
++ u16 phyno; /* input physical port number */
++ u32 status; /* gemac status bits bits[32:63]*/
++ u32 status2; /* gemac status bits bits[0:31] */
++} class_rx_hdr_t;
++/* class_rx_hdr status bits (status0 bits in hardware blocks)
++ * from hif_top/dma_dxr_dtx.v
++ * STATUS[9:0] is the encoding of bits in the LMEM buffer as seen by the QB block,
++ * NOT the encoding of bits as seen by the Class PEs in the DMEM rx header */
++#define STATUS_PARSE_DISABLE (1 << 0)
++#define STATUS_BRFETCH_DISABLE (1 << 1)
++#define STATUS_RTFETCH_DISABLE (1 << 2)
++#define STATUS_DIR_PROC_ID (1 << 3)
++#define STATUS_CONN_ID_EN (1 << 4))
++#define STATUS_PE2PROC_ID(x) (((x) & 7) << 5)
++#define STATUS_LE_DATA (1 << 8)
++#define STATUS_CHKSUM_EN (1 << 9)
++
++/* from gpi/gpi_rmlf.v */
++#define STATUS_CUMULATIVE_ERR (1 << 16)
++#define STATUS_LENGTH_ERR (1 << 17)
++#define STATUS_CRC_ERR (1 << 18)
++#define STATUS_TOO_SHORT_ERR (1 << 19)
++#define STATUS_TOO_LONG_ERR (1 << 20)
++#define STATUS_CODE_ERR (1 << 21)
++#define STATUS_MC_HASH_MATCH (1 << 22)
++#define STATUS_CUMULATIVE_ARC_HIT (1 << 23)
++#define STATUS_UNICAST_HASH_MATCH (1 << 24)
++#define STATUS_IP_CHECKSUM_CORRECT (1 << 25)
++#define STATUS_TCP_CHECKSUM_CORRECT (1 << 26)
++#define STATUS_UDP_CHECKSUM_CORRECT (1 << 27)
++#define STATUS_OVERFLOW_ERR (1 << 28)
++
++#define UTIL_MAGIC_NUM 0xffd8ffe000104a46
++#define UTIL_DDRC_WA
++
++/* The following structure is filled by class-pe when the packet
++ * has to be sent to util-pe, by filling the required information */
++typedef struct {
++ u32 mtd_flags : 16;
++ u32 packet_type : 8;
++ u32 input_port : 4;
++ u32 data_offset : 4;
++ u32 word[MTD_PRIV];
++#ifdef UTIL_DDRC_WA
++ u64 magic_num; // magic_number to verify the data validity in utilpe
++#endif
++} __attribute__((aligned(8))) util_rx_hdr_t; // Size must be a multiple of 64-bit to allow copies using EFET.
++
++#define UTIL_RX_IPS_IN_PKT EVENT_IPS_IN
++#define UTIL_RX_IPS_OUT_PKT EVENT_IPS_OUT
++#define UTIL_RX_RTP_PKT EVENT_RTP_RELAY
++#define UTIL_RX_RTP_QOS_PKT EVENT_RTP_QOS
++#define UTIL_RX_FRAG4_PKT EVENT_FRAG4
++#define UTIL_RX_FRAG6_PKT EVENT_FRAG6
++
++/** Structure passed from UtilPE to Class, stored at the end of the LMEM buffer. Defined and used by software only.
++ *
++ */
++
++typedef struct
++{
++ void *next;
++ u16 next_length;
++ u8 next_l3offset;
++ u8 next_l4offset;
++} frag_info;
++
++typedef struct {
++ u8 packet_type : 6;
++ u8 padding : 2;
++
++ u8 offset : 3;
++ u8 ddr_offset : 5;
++
++ u16 mtd_flags;
++ union {
++ u16 half[6];
++ u8 byte[12];
++
++ struct {
++ u16 sa_handle[2]; // SA_MAX_OP value should be used here instead of 2
++ u8 proto;
++ S8 sa_op;
++ u8 l2hdr_len;
++ u8 adj_dmem;
++ } ipsec;
++
++ struct {
++ u16 l4offset;
++ u16 socket_id;
++ BOOL update;
++ u8 reserved;
++ u32 payload_diff;
++ } relay;
++
++ struct {
++ u16 l3offset;
++ u16 l4offset;
++
++ frag_info frag;
++ } ipv6;
++
++ struct {
++ u16 l3offset;
++ } ipv4;
++
++ struct {
++ u32 ddr_addr;
++ u16 length;
++ u8 port;
++ u8 queue;
++ u8 action;
++ } tx;
++ };
++} lmem_trailer_t;
++
++/* The following values are defined for packet_type of lmem_trailer_t.
++ * These represent different types of packets sent from util to class
++ * for processing */
++enum {
++ UTIL_TX_IPS_IN = 0,
++ UTIL_TX_IPV4_RTP_PKT,
++ UTIL_TX_IPV6_RTP_PKT,
++ UTIL_TX_IPV4_PKT,
++ UTIL_TX_IPV6_PKT,
++ UTIL_TX_EXPT_PKT,
++#ifdef CFG_PCAP
++ UTIL_TX_PKT,
++#endif
++ UTIL_TX_MAX_PKT
++};
++
++
++#define UTIL_TX_TRAILER_SIZE sizeof(lmem_trailer_t)
++#define UTIL_TX_TRAILER(mtd) ((lmem_trailer_t *)ROUND_UP32((u32)(mtd)->rx_dmem_end))
++
++typedef struct {
++ u32 pkt_ptr;
++ u8 phyno;
++ u8 queueno;
++ u16 len;
++} tmu_tx_hdr_t;
++
++struct hif_pkt_hdr {
++ u8 client_id;
++ u8 qNo;
++ u16 client_ctrl_le_lsw;
++ u16 client_ctrl_le_msw;
++};
++
++
++#if defined(CFG_WIFI_OFFLOAD)
++#define MAX_WIFI_VAPS 3
++#define PFE_WIFI_PKT_HEADROOM 96 /*PFE inserts this headroom for WiFi tx packets only in lro mode */
++#else
++#define MAX_WIFI_VAPS 0
++#endif
++
++/* HIF header client id */
++enum HIF_CLIENT_ID {
++ CLIENT_ID_GEM0 = 0,
++ CLIENT_ID_GEM1,
++ CLIENT_ID_GEM2,
++ CLIENT_ID_WIFI0,
++ CLIENT_ID_WIFI_LAST = MAX_WIFI_VAPS + CLIENT_ID_GEM2,
++ CLIENT_ID_PCAP,
++ CLIENT_ID_UNKNOWN = 0xff,
++};
++
++
++#define IS_WIFI_CLIENT_ID(_clid) (((_clid) >= CLIENT_ID_WIFI0) && ((_clid) <= CLIENT_ID_WIFI_LAST))
++
++/* These match LE definition */
++#define HIF_CTRL_TX_TSO_NOCPY __cpu_to_le32(1 << 8)
++#define HIF_CTRL_TX_IPSEC_OUT __cpu_to_le32(1 << 7)
++#define HIF_CTRL_TX_WIFI_OWNMAC __cpu_to_le32(1 << 6)
++#define HIF_CTRL_TX_TSO_END __cpu_to_le32(1 << 5)
++#define HIF_CTRL_TX_TSO6 __cpu_to_le32(1 << 4)
++#define HIF_CTRL_TX_TSO __cpu_to_le32(1 << 3)
++#define HIF_CTRL_TX_CHECKSUM __cpu_to_le32(1 << 2)
++#define HIF_CTRL_TX_CSUM_VALIDATE __cpu_to_le32(1 << 1)
++#define HIF_CTRL_TX_WIFI_TXOFLD __cpu_to_le32(1 << 0)
++
++#define HIF_CTRL_RX_OFFSET_MASK __cpu_to_le32(0xf << 24)
++#define HIF_CTRL_RX_PE_ID_MASK __cpu_to_le32(0xf << 16)
++#define HIF_CTRL_RX_IPSEC_IN __cpu_to_le32(1 << 4)
++#define HIF_CTRL_RX_WIFI_EXPT __cpu_to_le32(1 << 3)
++#define HIF_CTRL_RX_CHECKSUMMED __cpu_to_le32(1 << 2)
++#define HIF_CTRL_RX_CONTINUED __cpu_to_le32(1 << 1)
++#define HIF_CTRL_RX_WIFI_HEADROOM __cpu_to_le32(1 << 0)
++
++#ifdef CFG_LRO
++struct hif_lro_hdr {
++ u16 data_offset;
++ u16 mss;
++};
++#endif
++
++struct hif_ipsec_hdr {
++ u16 sa_handle[2];
++};
++
++#define MAX_TSO_BUF_DESCS 5
++struct hif_tso_buf_desc {
++ u32 addr;
++ u32 ctrl;
++#define TSO_CTRL_LAST_BUFFER (1 << 31)
++};
++
++struct hif_tso_hdr {
++ u16 ip_off;
++ u16 ip_id;
++ u16 ip_len;
++ u16 tcp_off;
++ u32 tcp_seq;
++};
++
++struct hif_tso_hdr_nocpy {
++ u16 ip_off;
++ u16 ip_id;
++ u16 ip_len;
++ u16 tcp_off;
++ u32 tcp_seq;
++ struct hif_tso_buf_desc bdesc[MAX_TSO_BUF_DESCS];
++};
++
++struct hif_pcap_hdr {
++ u8 ifindex;
++ u8 unused;
++ u16 seqno;
++ u32 timestamp;
++};
++
++
++struct pe_sync_mailbox
++{
++ u32 stop;
++ u32 stopped;
++};
++
++struct pe_msg_mailbox
++{
++ u32 dst;
++ u32 src;
++ u32 len;
++ u32 request;
++};
++
++
++/** Basic busy loop delay function
++*
++* @param cycles Number of cycles to delay (actual cpu cycles should be close to 3 x cycles)
++*
++*/
++static inline void delay(u32 cycles)
++{
++ volatile int i;
++
++ for (i = 0; i < cycles; i++);
++}
++
++
++/** Read PE id
++*
++* @return PE id (0 - 5 for CLASS-PE's, 6 - 9 for TMU-PE's, 10 for UTIL-PE)
++*
++*/
++static inline u32 esi_get_mpid(void)
++{
++ u32 mpid;
++
++ asm ("rcsr %0, Configuration, MPID" : "=d" (mpid));
++
++ return mpid;
++}
++
++
++#define esi_get_csr(bank, csr) \
++({ \
++ u32 res; \
++ asm ("rcsr %0, " #bank ", " #csr : "=d" (res)); \
++ res; \
++})
++
++#define esi_get_isa0() esi_get_csr(Configuration, ISA0)
++#define esi_get_isa1() esi_get_csr(Configuration, ISA1)
++#define esi_get_isa2() esi_get_csr(Configuration, ISA2)
++#define esi_get_isa3() esi_get_csr(Configuration, ISA3)
++#define esi_get_epc() esi_get_csr(Thread, EPC)
++#define esi_get_ecas() esi_get_csr(Thread, ECAS)
++#define esi_get_eid() esi_get_csr(Thread, EID)
++#define esi_get_ed() esi_get_csr(Thread, ED)
++
++static inline void esi_pe_stop(U32 state)
++{
++ PESTATUS_SETSTATE(state);
++ while (1)
++ {
++ asm("stop");
++ }
++}
++
++
++/** Same 64bit alignment memory copy using efet.
++* Either the source or destination address must be in DMEM, the other address can be in LMEM or DDR.
++* Both the source and destination must have the same 64bit alignment, length should be more than four bytes
++* or dst/src must be 32bit aligned. Otherwise use efet_memcpy_any()
++* Uses efet synchronous interface to copy the data.
++*
++* @param dst Destination address to write to (must have the same 64bit alignment as src)
++* @param src Source address to read from (must have the same 64bit alignment as dst)
++* @param len Number of bytes to copy
++*
++*/
++void efet_memcpy(void *dst, void *src, unsigned int len);
++
++/** Same 64bit alignment memory copy using efet.
++* Either the source or destination address must be in DMEM, the other address can be in LMEM or DDR.
++* Both the source and destination must have the same 64bit alignment, there is no restriction on length.
++* For UTIL-PE revA0, this function will still fail to handle small/unaligned writes.
++* Uses efet synchronous interface to copy the data.
++*
++* @param dst Destination address to write to (must have the same 64bit alignment as src)
++* @param src Source address to read from (must have the same 64bit alignment as dst)
++* @param len Number of bytes to copy
++*
++*/
++void efet_memcpy_any(void *dst, void *src, unsigned int len);
++
++/** Same 64bit alignment memory copy using efet.
++* Either the source or destination address must be in DMEM, the other address can be in LMEM or DDR.
++* Both the source and destination must have the same 64bit alignment, length should be more than four bytes
++* or dst/src must be 32bit aligned.
++* Uses efet asynchronous interface to copy the data.
++*
++* @param dst Destination address to write to (must have the same 64bit alignment as src)
++* @param src Source address to read from (must have the same 64bit alignment as dst)
++* @param len Number of bytes to copy
++*
++*/
++void efet_memcpy_nowait(void *dst, void *src, unsigned int len);
++
++/** Unaligned memory copy using efet.
++* Either the source or destination address must be in DMEM, the other address can be in LMEM or DDR.
++* There is not restriction on source and destination, nor on length.
++*
++* @param dst Destination address to write to
++* @param src Source address to read from
++* @param len Number of bytes to copy
++* @param dmem_buf temp dmem buffer to use, must be 64bit aligned
++* @param dmem_len length of dmem buffer, must be 64bit aligned and at least 16 bytes
++*
++*/
++void efet_memcpy_unaligned(void *dst, void *src, unsigned int len, void *dmem_buf, unsigned int dmem_len);
++
++/** Aligned memory copy of 4 bytes to register address.
++* Register address must be 32 bit aligned.
++*
++* @param val value to be copied.
++* @param reg_addr Register address (must be 16bit aligned)
++*
++*/
++void __efet_writel(u32 val, void *addr);
++
++#ifdef REVA_WA
++#define efet_writel(val, addr) __efet_writel((u32)(val), (void *) (addr))
++#else
++#define efet_writel(val, addr) writel((u32)(val), (void *) (addr))
++#endif
++
++
++/** 32bit aligned memory copy.
++* Source and destination addresses must be 32bit aligned, there is no restriction on the length.
++*
++* @param dst Destination address (must be 32bit aligned)
++* @param src Source address (must be 32bit aligned)
++* @param len Number of bytes to copy
++*
++*/
++void memcpy_aligned32(void *dst, void *src, unsigned int len);
++
++/** Aligned memory copy.
++* Source and destination addresses must have the same alignment
++* relative to 32bit boundaries (but otherwsie may have any alignment),
++* there is no restriction on the length.
++*
++* @param dst Destination address
++* @param src Source address (must have same 32bit alignment as dst)
++* @param len Number of bytes to copy
++*
++*/
++void memcpy_aligned(void *dst, void *src, unsigned int len);
++
++/** Unaligned memory copy.
++* Implements unaligned memory copy. We first align the destination
++* to a 32bit boundary (using byte copies) then the src, and finally use a loop
++* of read, shift, write
++*
++* @param dst Destination address
++* @param src Source address (must have same 32bit alignment as dst)
++* @param len Number of bytes to copy
++*
++*/
++void memcpy_unaligned(void *dst, void *src, unsigned int len);
++
++/** Generic memory set.
++* Implements a generic memory set. Not very optimal (uses byte writes for the entire range)
++*
++*
++* @param dst Destination address
++* @param val Value to set memory to
++* @param len Number of bytes to set
++*
++*/
++void memset(void *dst, u8 val, unsigned int len);
++
++/** Generic memory copy.
++* Implements generic memory copy. If source and destination have the same
++* alignment memcpy_aligned() is used, otherwise memcpy_unaligned()
++*
++* @param dst Destination address
++* @param src Source address
++* @param len Number of bytes to copy
++*
++*/
++void memcpy(void *dst, void *src, unsigned int len);
++
++/** Generic memorymove.
++* Implements generic memorymove, where copies across overlapping
++* memory regions is supported.
++* Uses the dmem_buf passed as a parameter as a temporary buffer.
++* Includes two copies, forces one of the copies to be definitely aligned.
++* The "dmem_len" being passed should be atleast 3 bytes greater than "len"
++* The 3 bytes here are shift bytes used to ensure one aligned copy.
++*
++* @param dst Destination address
++* @param src Source address
++* @param len Number of bytes to copy
++* @param dmem_buf temp dmem buffer to use, must be 32bit aligned
++* @param dmem_len length of dmem buffer, must be 32bit aligned and at least 3 bytes greater
++* than @param len
++*
++*/
++
++void *memorymove(void * dst, void * src, unsigned int len, void *dmem_buf, unsigned int dmem_len);
++
++/** Aligned memory copy in DDR memory.
++ * Implements aligned memory copy between two DDR buffers using efet_memcpy64 and DMEM
++ * Both the source and destination must have the same 64bit alignment, there is no restriction on length.
++ * If start or end are not 64bit aligned, data in destination buffer before start/after end will be corrupted.
++ *
++ * @param dst DDR Destination address
++ * @param src DDR Source address
++ * @param len Number of bytes to copy
++ * @param dmem_buf temp dmem buffer to use, must be 64bit aligned
++ * @param dmem_len length of dmem buffer, must be 64bit aligned and at least 16 bytes
++ */
++void memcpy_ddr_to_ddr(void *dst, void *src, unsigned int len, void *dmem_buf, unsigned int dmem_len);
++
++/** Unaligned memory copy in DDR memory.
++ * Implements generic memory copy between two DDR buffers using efet_memcpy and DMEM
++ * There is no restriction on the source, destination and length alignments.
++ *
++ * @param dst DDR Destination address
++ * @param src DDR Source address
++ * @param len Number of bytes to copy
++ * @param dmem_buf temp dmem buffer to use, must be 64bit aligned
++ * @param dmem_len length of dmem buffer, must be 64bit aligned and at least 16 bytes
++ */
++void memcpy_ddr_to_ddr_unaligned(void *dst, void *src, unsigned int len, void *dmem_buf, unsigned int dmem_len);
++
++#endif /* _PE_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/pfe.h
+@@ -0,0 +1,444 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _PFE_H_
++#define _PFE_H_
++
++#define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
++#define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) /* Only valid for mem access register interface */
++#define CLASS_DMEM_SIZE 0x00002000
++#define CLASS_IMEM_SIZE 0x00008000
++
++#define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
++#define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20)) /* Only valid for mem access register interface */
++#define TMU_DMEM_SIZE 0x00000800
++#define TMU_IMEM_SIZE 0x00002000
++
++#define UTIL_DMEM_BASE_ADDR 0x00000000
++#define UTIL_DMEM_SIZE 0x00002000
++
++#define PE_LMEM_BASE_ADDR 0xc3010000
++#define PE_LMEM_SIZE 0x8000
++#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
++
++#define DMEM_BASE_ADDR 0x00000000
++#define DMEM_SIZE 0x2000 /**< TMU has less... */
++#define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE)
++
++#define PMEM_BASE_ADDR 0x00010000
++#define PMEM_SIZE 0x8000 /**< TMU has less... */
++#define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE)
++
++
++/* These check memory ranges from PE point of view/memory map */
++#define IS_DMEM(addr, len) (((unsigned long)(addr) >= DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= DMEM_END))
++#define IS_PMEM(addr, len) (((unsigned long)(addr) >= PMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PMEM_END))
++#define IS_PE_LMEM(addr, len) (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PE_LMEM_END))
++
++#define IS_PFE_LMEM(addr, len) (((unsigned long)(addr) >= CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) && (((unsigned long)(addr) + (len)) <= CBUS_VIRT_TO_PFE(LMEM_END)))
++#define __IS_PHYS_DDR(addr, len) (((unsigned long)(addr) >= DDR_PHYS_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= DDR_PHYS_END))
++#define IS_PHYS_DDR(addr, len) __IS_PHYS_DDR(DDR_PFE_TO_PHYS(addr), len)
++
++/* If using a run-time virtual address for the cbus base address use this code */
++extern void *cbus_base_addr;
++extern void *ddr_base_addr;
++extern unsigned long ddr_phys_base_addr;
++extern unsigned int ddr_size;
++
++#if defined(COMCERTO_2000_CONTROL)
++#include <linux/version.h>
++#if defined (CONFIG_PLATFORM_C2000)
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)
++/*This is copied from arch/arm/include/asm/system_info.h */
++extern unsigned int system_rev;
++#endif
++#endif
++#endif
++
++#define CBUS_BASE_ADDR cbus_base_addr
++#define DDR_PHYS_BASE_ADDR ddr_phys_base_addr
++#define DDR_BASE_ADDR ddr_base_addr
++#define DDR_SIZE ddr_size
++
++#define DDR_PHYS_END (DDR_PHYS_BASE_ADDR + DDR_SIZE)
++
++#if defined(CONFIG_PLATFORM_C2000)
++#define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /**< CBUS physical base address as seen by PE's. */
++#define DDR_PHYS_TO_PFE(p) (p)
++#define DDR_PFE_TO_PHYS(p) (p)
++#define CBUS_PHYS_TO_PFE(p) (p)
++#else
++#define LS1012A_PFE_RESET_WA /*PFE doesn't have global reset and re-init should takecare few things to make PFE functional after reset */
++#define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /**< CBUS physical base address as seen by PE's. */
++#define PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE 0xc0000000 /**< CBUS physical base address as seen by PE's. */
++#define DDR_PHYS_TO_PFE(p) (((unsigned long int) (p)) & 0x7FFFFFFF)
++#define DDR_PFE_TO_PHYS(p) (((unsigned long int) (p)) | 0x80000000)
++#define CBUS_PHYS_TO_PFE(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) + PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE) /*Translates to PFE address map */
++#endif
++
++#define DDR_PHYS_TO_VIRT(p) (((p) - DDR_PHYS_BASE_ADDR) + DDR_BASE_ADDR)
++#define DDR_VIRT_TO_PHYS(v) (((v) - DDR_BASE_ADDR) + DDR_PHYS_BASE_ADDR)
++#define DDR_VIRT_TO_PFE(p) (DDR_PHYS_TO_PFE(DDR_VIRT_TO_PHYS(p)))
++
++#define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) + PFE_CBUS_PHYS_BASE_ADDR)
++#define CBUS_PFE_TO_VIRT(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)
++
++/* The below part of the code is used in QOS control driver from host */
++#define TMU_APB_BASE_ADDR 0xc1000000 /** TMU base address seen by pe's */
++
++#define SHAPER0_BASE_ADDR (TMU_APB_BASE_ADDR + 0x020000)
++#define SHAPER1_BASE_ADDR (TMU_APB_BASE_ADDR + 0x030000)
++#define SHAPER2_BASE_ADDR (TMU_APB_BASE_ADDR + 0x040000)
++#define SHAPER3_BASE_ADDR (TMU_APB_BASE_ADDR + 0x050000)
++#define SHAPER4_BASE_ADDR (TMU_APB_BASE_ADDR + 0x060000)
++#define SHAPER5_BASE_ADDR (TMU_APB_BASE_ADDR + 0x070000)
++#define SHAPER6_BASE_ADDR (TMU_APB_BASE_ADDR + 0x080000)
++#define SHAPER7_BASE_ADDR (TMU_APB_BASE_ADDR + 0x090000)
++#define SHAPER8_BASE_ADDR (TMU_APB_BASE_ADDR + 0x0a0000)
++#define SHAPER9_BASE_ADDR (TMU_APB_BASE_ADDR + 0x0b0000)
++
++#define SCHED0_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1c0000)
++#define SCHED1_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1d0000)
++#define SCHED2_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1e0000)
++#define SCHED3_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1f0000)
++#define SCHED4_BASE_ADDR (TMU_APB_BASE_ADDR + 0x200000)
++#define SCHED5_BASE_ADDR (TMU_APB_BASE_ADDR + 0x210000)
++#define SCHED6_BASE_ADDR (TMU_APB_BASE_ADDR + 0x220000)
++#define SCHED7_BASE_ADDR (TMU_APB_BASE_ADDR + 0x230000)
++
++#define PHY_QUEUE_BASE_ADDR (TMU_APB_BASE_ADDR + 0x260000)
++#define QUEUE_RESULT0 (PHY_QUEUE_BASE_ADDR + 0x48) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY3), [6:0] winner input queue number */
++#define QUEUE_RESULT1 (PHY_QUEUE_BASE_ADDR + 0x4c) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY4), [6:0] winner input queue number */
++#define QUEUE_RESULT2 (PHY_QUEUE_BASE_ADDR + 0x50) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY5), [6:0] winner input queue number */
++
++#define QUEUE_RESULT0_REGOFFSET (QUEUE_RESULT0 - QUEUE_RESULT0)
++#define QUEUE_RESULT1_REGOFFSET (QUEUE_RESULT1 - QUEUE_RESULT0)
++#define QUEUE_RESULT2_REGOFFSET (QUEUE_RESULT2 - QUEUE_RESULT0)
++
++
++#include "cbus.h"
++
++enum {
++ CLASS0_ID = 0,
++ CLASS1_ID,
++ CLASS2_ID,
++ CLASS3_ID,
++#if !defined(CONFIG_PLATFORM_PCI)
++ CLASS4_ID,
++ CLASS5_ID,
++#endif
++#if !defined(CONFIG_TMU_DUMMY)
++ TMU0_ID,
++ TMU1_ID,
++ TMU2_ID,
++ TMU3_ID,
++#else
++ TMU0_ID,
++#endif
++#if !defined(CONFIG_UTIL_DISABLED)
++ UTIL_ID,
++#endif
++ MAX_PE
++};
++
++enum {
++ CLASS_TYPE = 0,
++ TMU_TYPE,
++ UTIL_TYPE
++};
++
++#if !defined(CONFIG_PLATFORM_PCI)
++#define CLASS_MASK ((1 << CLASS0_ID) | (1 << CLASS1_ID) | (1 << CLASS2_ID) | (1 << CLASS3_ID) | (1 << CLASS4_ID) | (1 << CLASS5_ID))
++#define CLASS_MAX_ID CLASS5_ID
++#else
++#define CLASS_MASK ((1 << CLASS0_ID) | (1 << CLASS1_ID) | (1 << CLASS2_ID) | (1 << CLASS3_ID))
++#define CLASS_MAX_ID CLASS3_ID
++#endif
++
++#if !defined(CONFIG_TMU_DUMMY)
++#if defined(CONFIG_PLATFORM_LS1012A)
++#define TMU_MASK ((1 << TMU0_ID) | (1 << TMU1_ID) | (1 << TMU3_ID))
++#else
++#define TMU_MASK ((1 << TMU0_ID) | (1 << TMU1_ID) | (1 << TMU2_ID) | (1 << TMU3_ID))
++#endif
++#define TMU_MAX_ID TMU3_ID
++#else
++#define TMU_MASK (1 << TMU0_ID)
++#define TMU_MAX_ID TMU0_ID
++#endif
++
++#if !defined(CONFIG_UTIL_DISABLED)
++#define UTIL_MASK (1 << UTIL_ID)
++#endif
++
++typedef struct tPE_STATUS
++{
++ u32 cpu_state;
++ u32 activity_counter;
++ u32 rx;
++ union {
++ u32 tx;
++ u32 tmu_qstatus;
++ };
++ u32 drop;
++#if defined(CFG_PE_DEBUG)
++ u32 debug_indicator;
++ u32 debug[16];
++#endif
++} __attribute__((aligned(16))) PE_STATUS;
++
++
++struct pe_sync_mailbox
++{
++ u32 stop;
++ u32 stopped;
++};
++
++struct pe_msg_mailbox
++{
++ u32 dst;
++ u32 src;
++ u32 len;
++ u32 request;
++};
++
++// Drop counter definitions
++
++#define CLASS_NUM_DROP_COUNTERS 13
++#define UTIL_NUM_DROP_COUNTERS 8
++
++
++/** PE information.
++ * Structure containing PE's specific information. It is used to create
++ * generic C functions common to all PE's.
++ * Before using the library functions this structure needs to be initialized with the different registers virtual addresses
++ * (according to the ARM MMU mmaping). The default initialization supports a virtual == physical mapping.
++ *
++ */
++struct pe_info
++{
++ u32 dmem_base_addr; /**< PE's dmem base address */
++ u32 pmem_base_addr; /**< PE's pmem base address */
++ u32 pmem_size; /**< PE's pmem size */
++
++ void *mem_access_wdata; /**< PE's _MEM_ACCESS_WDATA register address */
++ void *mem_access_addr; /**< PE's _MEM_ACCESS_ADDR register address */
++ void *mem_access_rdata; /**< PE's _MEM_ACCESS_RDATA register address */
++};
++
++
++void pe_lmem_read(u32 *dst, u32 len, u32 offset);
++void pe_lmem_write(u32 *src, u32 len, u32 offset);
++
++void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
++void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
++
++u32 pe_pmem_read(int id, u32 addr, u8 size);
++
++void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
++u32 pe_dmem_read(int id, u32 addr, u8 size);
++void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len);
++void class_pe_lmem_memset(u32 dst, int val, unsigned int len);
++void class_bus_write(u32 val, u32 addr, u8 size);
++u32 class_bus_read(u32 addr, u8 size);
++
++
++#define class_bus_readl(addr) class_bus_read(addr, 4)
++#define class_bus_readw(addr) class_bus_read(addr, 2)
++#define class_bus_readb(addr) class_bus_read(addr, 1)
++
++#define class_bus_writel(val, addr) class_bus_write(val, addr, 4)
++#define class_bus_writew(val, addr) class_bus_write(val, addr, 2)
++#define class_bus_writeb(val, addr) class_bus_write(val, addr, 1)
++
++#define pe_dmem_readl(id, addr) pe_dmem_read(id, addr, 4)
++#define pe_dmem_readw(id, addr) pe_dmem_read(id, addr, 2)
++#define pe_dmem_readb(id, addr) pe_dmem_read(id, addr, 1)
++
++#define pe_dmem_writel(id, val, addr) pe_dmem_write(id, val, addr, 4)
++#define pe_dmem_writew(id, val, addr) pe_dmem_write(id, val, addr, 2)
++#define pe_dmem_writeb(id, val, addr) pe_dmem_write(id, val, addr, 1)
++
++//int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr);
++int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr, struct device *dev);
++
++void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base, unsigned int ddr_size);
++void bmu_init(void *base, BMU_CFG *cfg);
++void bmu_reset(void *base);
++void bmu_enable(void *base);
++void bmu_disable(void *base);
++void bmu_set_config(void *base, BMU_CFG *cfg);
++
++/* An enumerated type for loopback values. This can be one of three values, no
++ * loopback -normal operation, local loopback with internal loopback module of
++ * MAC or PHY loopback which is through the external PHY.
++ */
++#ifndef __MAC_LOOP_ENUM__
++#define __MAC_LOOP_ENUM__
++typedef enum {LB_NONE, LB_EXT, LB_LOCAL} MAC_LOOP;
++#endif
++
++
++void gemac_init(void *base, void *config);
++void gemac_disable_rx_checksum_offload(void *base);
++void gemac_enable_rx_checksum_offload(void *base);
++void gemac_set_mdc_div(void *base, int mdc_div);
++void gemac_set_speed(void *base, MAC_SPEED gem_speed);
++void gemac_set_duplex(void *base, int duplex);
++void gemac_set_mode(void *base, int mode);
++void gemac_enable(void *base);
++void gemac_tx_disable(void *base);
++void gemac_disable(void *base);
++void gemac_reset(void *base);
++void gemac_set_address(void *base, SPEC_ADDR *addr);
++SPEC_ADDR gemac_get_address(void *base);
++void gemac_set_loop( void *base, MAC_LOOP gem_loop );
++void gemac_set_laddr1(void *base, MAC_ADDR *address);
++void gemac_set_laddr2(void *base, MAC_ADDR *address);
++void gemac_set_laddr3(void *base, MAC_ADDR *address);
++void gemac_set_laddr4(void *base, MAC_ADDR *address);
++void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index);
++void gemac_clear_laddr1(void *base);
++void gemac_clear_laddr2(void *base);
++void gemac_clear_laddr3(void *base);
++void gemac_clear_laddr4(void *base);
++void gemac_clear_laddrN(void *base, unsigned int entry_index);
++MAC_ADDR gemac_get_hash( void *base );
++void gemac_set_hash( void *base, MAC_ADDR *hash );
++MAC_ADDR gem_get_laddr1(void *base);
++MAC_ADDR gem_get_laddr2(void *base);
++MAC_ADDR gem_get_laddr3(void *base);
++MAC_ADDR gem_get_laddr4(void *base);
++MAC_ADDR gem_get_laddrN(void *base, unsigned int entry_index);
++void gemac_set_config(void *base, GEMAC_CFG *cfg);
++void gemac_allow_broadcast(void *base);
++void gemac_no_broadcast(void *base);
++void gemac_enable_unicast(void *base);
++void gemac_disable_unicast(void *base);
++void gemac_enable_multicast(void *base);
++void gemac_disable_multicast(void *base);
++void gemac_enable_fcs_rx(void *base);
++void gemac_disable_fcs_rx(void *base);
++void gemac_enable_1536_rx(void *base);
++void gemac_disable_1536_rx(void *base);
++void gemac_enable_rx_jmb(void *base);
++void gemac_disable_rx_jmb(void *base);
++void gemac_enable_stacked_vlan(void *base);
++void gemac_disable_stacked_vlan(void *base);
++void gemac_enable_pause_rx(void *base);
++void gemac_disable_pause_rx(void *base);
++void gemac_enable_copy_all(void *base);
++void gemac_disable_copy_all(void *base);
++void gemac_set_bus_width(void *base, int width);
++void gemac_set_wol(void *base, u32 wol_conf);
++
++void gpi_init(void *base, GPI_CFG *cfg);
++void gpi_reset(void *base);
++void gpi_enable(void *base);
++void gpi_disable(void *base);
++void gpi_set_config(void *base, GPI_CFG *cfg);
++
++void class_init(CLASS_CFG *cfg);
++void class_reset(void);
++void class_enable(void);
++void class_disable(void);
++void class_set_config(CLASS_CFG *cfg);
++
++void tmu_reset(void);
++void tmu_init(TMU_CFG *cfg);
++void tmu_enable(u32 pe_mask);
++void tmu_disable(u32 pe_mask);
++u32 tmu_qstatus(u32 if_id);
++u32 tmu_pkts_processed(u32 if_id);
++
++void util_init(UTIL_CFG *cfg);
++void util_reset(void);
++void util_enable(void);
++void util_disable(void);
++
++void hif_nocpy_init(void);
++void hif_nocpy_tx_enable(void);
++void hif_nocpy_tx_disable(void);
++void hif_nocpy_rx_enable(void);
++void hif_nocpy_rx_disable(void);
++
++void hif_init(void);
++void hif_tx_enable(void);
++void hif_tx_disable(void);
++void hif_rx_enable(void);
++void hif_rx_disable(void);
++
++
++/** Get Chip Revision level
++*
++*/
++
++static inline unsigned int CHIP_REVISION(void)
++{
++#if defined (CONFIG_PLATFORM_C2000)
++#if 1
++ return system_rev;
++ //return 0;
++#else
++ return (readl(COMCERTO_GPIO_DEVICE_ID_REG) >> 24) & 0xf;
++#endif
++
++#else
++ /*For LS1012A return always 1 */
++ return 1;
++#endif
++}
++
++/** Start HIF rx DMA
++*
++*/
++static inline void hif_rx_dma_start(void)
++{
++ /*TODO not sure poll_cntrl_en is required or not */
++ writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_RX_CTRL);
++}
++
++/** Start HIF tx DMA
++*
++*/
++static inline void hif_tx_dma_start(void)
++{
++ /*TODO not sure poll_cntrl_en is required or not */
++ writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_TX_CTRL);
++}
++
++/** Start HIF_NOCPY rx DMA
++*
++*/
++static inline void hif_nocpy_rx_dma_start(void)
++{
++ /*TODO not sure poll_cntrl_en is required or not */
++ writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_NOCPY_RX_CTRL);
++}
++
++/** Start HIF_NOCPY tx DMA
++*
++*/
++static inline void hif_nocpy_tx_dma_start(void)
++{
++ /*TODO not sure poll_cntrl_en is required or not */
++ writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_NOCPY_TX_CTRL);
++}
++
++#endif /* _PFE_H_ */
++
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/tmu.h
+@@ -0,0 +1,68 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _TMU_H_
++#define _TMU_H_
++
++#define TMU_DMEM_BASE_ADDR 0x00000000
++#define TMU_PMEM_BASE_ADDR 0x00010000
++
++#define CBUS_BASE_ADDR 0xc0000000
++#define TMU_APB_BASE_ADDR 0xc1000000
++
++#if defined (COMCERTO_2000_TMU) || defined (COMCERTO_2000_CONTROL)
++
++#include "cbus.h"
++
++#define GPT_BASE_ADDR (TMU_APB_BASE_ADDR + 0x00000)
++#define UART_BASE_ADDR (TMU_APB_BASE_ADDR + 0x10000)
++
++#define SHAPER0_BASE_ADDR (TMU_APB_BASE_ADDR + 0x020000)
++#define SHAPER1_BASE_ADDR (TMU_APB_BASE_ADDR + 0x030000)
++#define SHAPER2_BASE_ADDR (TMU_APB_BASE_ADDR + 0x040000)
++#define SHAPER3_BASE_ADDR (TMU_APB_BASE_ADDR + 0x050000)
++#define SHAPER4_BASE_ADDR (TMU_APB_BASE_ADDR + 0x060000)
++#define SHAPER5_BASE_ADDR (TMU_APB_BASE_ADDR + 0x070000)
++#define SHAPER6_BASE_ADDR (TMU_APB_BASE_ADDR + 0x080000)
++#define SHAPER7_BASE_ADDR (TMU_APB_BASE_ADDR + 0x090000)
++#define SHAPER8_BASE_ADDR (TMU_APB_BASE_ADDR + 0x0a0000)
++#define SHAPER9_BASE_ADDR (TMU_APB_BASE_ADDR + 0x0b0000)
++
++#define SCHED0_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1c0000)
++#define SCHED1_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1d0000)
++#define SCHED2_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1e0000)
++#define SCHED3_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1f0000)
++#define SCHED4_BASE_ADDR (TMU_APB_BASE_ADDR + 0x200000)
++#define SCHED5_BASE_ADDR (TMU_APB_BASE_ADDR + 0x210000)
++#define SCHED6_BASE_ADDR (TMU_APB_BASE_ADDR + 0x220000)
++#define SCHED7_BASE_ADDR (TMU_APB_BASE_ADDR + 0x230000)
++
++#define SHAPER_STATUS (TMU_APB_BASE_ADDR + 0x270000) /**< [9:0] bitmask of shapers that have positive credit */
++
++#include "gpt.h"
++#include "uart.h"
++#include "tmu/shaper.h"
++#include "tmu/sched.h"
++
++#endif
++
++#define PHY_QUEUE_BASE_ADDR (TMU_APB_BASE_ADDR + 0x260000)
++
++#include "tmu/phy_queue.h"
++
++#endif /* _TMU_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/tmu/phy_queue.h
+@@ -0,0 +1,56 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _PHY_QUEUE_H_
++#define _PHY_QUEUE_H_
++
++#define PHY_QUEUE_SHAPER_STATUS (PHY_QUEUE_BASE_ADDR + 0x00) /**< [28:19] same as SHAPER_STATUS, [18:3] same as QUEUE_STATUS, [2:0] must be zero before a new packet may be dequeued */
++#define QUEUE_STATUS (PHY_QUEUE_BASE_ADDR + 0x04) /**< [15:0] bit mask of input queues with pending packets */
++
++#define QUEUE0_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x08)
++#define QUEUE1_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x0c)
++#define QUEUE2_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x10)
++#define QUEUE3_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x14)
++#define QUEUE4_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x18)
++#define QUEUE5_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x1c)
++#define QUEUE6_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x20)
++#define QUEUE7_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x24)
++#define QUEUE8_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x28)
++#define QUEUE9_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x2c)
++#define QUEUE10_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x30)
++#define QUEUE11_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x34)
++#define QUEUE12_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x38)
++#define QUEUE13_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x3c)
++#define QUEUE14_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x40)
++#define QUEUE15_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x44)
++#define QUEUE_RESULT0 (PHY_QUEUE_BASE_ADDR + 0x48) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY3), [6:0] winner input queue number */
++#define QUEUE_RESULT1 (PHY_QUEUE_BASE_ADDR + 0x4c) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY4), [6:0] winner input queue number */
++#define QUEUE_RESULT2 (PHY_QUEUE_BASE_ADDR + 0x50) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY5), [6:0] winner input queue number */
++#define TMU_PE_GP_REG (PHY_QUEUE_BASE_ADDR + 0x54)
++#define QUEUE_GBL_PKTLEN (PHY_QUEUE_BASE_ADDR + 0x5c)
++#define QUEUE_GBL_PKTLEN_MASK (PHY_QUEUE_BASE_ADDR + 0x60)
++
++#define QUEUE_RESULT0_REGOFFSET (QUEUE_RESULT0 - QUEUE_RESULT0)
++#define QUEUE_RESULT1_REGOFFSET (QUEUE_RESULT1 - QUEUE_RESULT0)
++#define QUEUE_RESULT2_REGOFFSET (QUEUE_RESULT2 - QUEUE_RESULT0)
++
++#define TEQ_HTD (1 << 22)
++#define TEQ_HWRED (1 << 21)
++
++
++#endif /* _PHY_QUEUE_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/tmu/sched.h
+@@ -0,0 +1,72 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _SCHED_H_
++#define _SCHED_H_
++
++/* Offsets from SCHEDx_BASE_ADDR */
++#define SCHED_CTRL 0x00
++#define SCHED_SLOT_TIME 0x04
++#define SCHED_RES 0x08
++#define SCHED_QUEUE_ALLOC0 0x0c
++#define SCHED_QUEUE_ALLOC1 0x10
++#define SCHED_BW 0x14
++#define SCHED_GUR_DEF_CTR 0x18
++#define SCHED_AVL_CTR 0x1c
++#define SCHED_QU0_WGHT 0x20
++#define SCHED_QU1_WGHT 0x24
++#define SCHED_QU2_WGHT 0x28
++#define SCHED_QU3_WGHT 0x2c
++#define SCHED_QU4_WGHT 0x30
++#define SCHED_QU5_WGHT 0x34
++#define SCHED_QU6_WGHT 0x38
++#define SCHED_QU7_WGHT 0x3c
++#define SCHED_QUE0_DEFICIT_CNT 0x40
++#define SCHED_QUE1_DEFICIT_CNT 0x44
++#define SCHED_QUE2_DEFICIT_CNT 0x48
++#define SCHED_QUE3_DEFICIT_CNT 0x4c
++#define SCHED_QUE4_DEFICIT_CNT 0x50
++#define SCHED_QUE5_DEFICIT_CNT 0x54
++#define SCHED_QUE6_DEFICIT_CNT 0x58
++#define SCHED_QUE7_DEFICIT_CNT 0x5c
++#define SCHED_PKT_LEN 0x60
++
++#define SCHED_CTRL_ALGOTYPE(x) (((x) & 0xf) << 0)
++#define SCHED_CTRL_CALQUOTA(x) (((x) & 0x1) << 4)
++#define SCHED_CTRL_ACTIVE_Q(x) (((x) & 0xff) << 8)
++#define SCHED_CTRL_SHARE_BW(x) (((x) & 0xff) << 16)
++#define SCHED_CTRL_BARROW_BW(x) (((x) & 0xff) << 24)
++
++#define SCHED_QUEUE_ALLOC(x, b) (((x) & 0x1f) << (b))
++
++#define SCHED_QUEUE_ALLOC0_QUEUEA(x) (((x) & 0x1f) << 0)
++#define SCHED_QUEUE_ALLOC0_QUEUEB(x) (((x) & 0x1f) << 8)
++#define SCHED_QUEUE_ALLOC0_QUEUEC(x) (((x) & 0x1f) << 16)
++#define SCHED_QUEUE_ALLOC0_QUEUED(x) (((x) & 0x1f) << 24)
++
++#define SCHED_QUEUE_ALLOC0_RES0(x) (((x) & 0x7) << 5)
++#define SCHED_QUEUE_ALLOC0_RES1(x) (((x) & 0x7) << 13)
++#define SCHED_QUEUE_ALLOC0_RES2(x) (((x) & 0x7) << 21)
++#define SCHED_QUEUE_ALLOC0_RES3(x) (((x) & 0x7) << 29)
++
++#define SCHED_QUEUE_ALLOC1_QUEUEA(x) (((x) & 0x1f) << 0)
++#define SCHED_QUEUE_ALLOC1_QUEUEB(x) (((x) & 0x1f) << 8)
++#define SCHED_QUEUE_ALLOC1_QUEUEC(x) (((x) & 0x1f) << 16)
++#define SCHED_QUEUE_ALLOC1_QUEUED(x) (((x) & 0x1f) << 24)
++
++#endif /* _SCHED_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/tmu/shaper.h
+@@ -0,0 +1,37 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _SHAPER_H_
++#define _SHAPER_H_
++
++/* Offsets from SHAPPERx_BASE_ADDR */
++#define SHAPER_CTRL 0x00
++#define SHAPER_WEIGHT 0x04
++#define SHAPER_PKT_LEN 0x08
++
++#define SHAPER_CTRL_ENABLE(x) (((x) & 0x1) << 0)
++#define SHAPER_CTRL_QNO(x) (((x) & 0x3f) << 1)
++#define SHAPER_CTRL_CLKDIV(x) (((x) & 0xffff) << 16)
++
++#define SHAPER_WEIGHT_FRACWT(x) (((x) & 0xff) << 0)
++#define SHAPER_WEIGHT_INTWT(x) (((x) & 0x3) << 8)
++#define SHAPER_WEIGHT_MAXCREDIT(x) (((x) & 0x3fffff) << 10)
++
++#define PORT_SHAPER_MASK (1 << 0)
++
++#endif /* _SHAPER_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/uart.h
+@@ -0,0 +1,31 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _UART_H_
++#define _UART_H_
++
++#define UART_THR (UART_BASE_ADDR + 0x00)
++#define UART_IER (UART_BASE_ADDR + 0x04)
++#define UART_IIR (UART_BASE_ADDR + 0x08)
++#define UART_LCR (UART_BASE_ADDR + 0x0c)
++#define UART_MCR (UART_BASE_ADDR + 0x10)
++#define UART_LSR (UART_BASE_ADDR + 0x14)
++#define UART_MDR (UART_BASE_ADDR + 0x18)
++#define UART_SCRATCH (UART_BASE_ADDR + 0x1c)
++
++#endif /* _UART_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/util.h
+@@ -0,0 +1,49 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _UTIL_H_
++#define _UTIL_H_
++
++#define UTIL_DMEM_BASE_ADDR 0x00000000
++#define UTIL_DMEM_SIZE 0x00002000
++#define UTIL_DMEM_END (UTIL_DMEM_BASE_ADDR + UTIL_DMEM_SIZE)
++
++#define IS_DMEM(addr, len) (((unsigned long)(addr) >= UTIL_DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= UTIL_DMEM_END))
++
++#define CBUS_BASE_ADDR 0xc0000000
++#define UTIL_APB_BASE_ADDR 0xc1000000
++
++#include "cbus.h"
++
++#define GPT_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x00000)
++#define UART_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x10000)
++#define EAPE_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x20000)
++#define INQ_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x30000)
++#define EFET1_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x40000)
++#define EFET2_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x50000)
++#define EFET3_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x60000)
++
++
++#include "gpt.h"
++#include "uart.h"
++#include "util/eape.h"
++#include "util/inq.h"
++#include "util/efet.h"
++
++
++#endif /* _UTIL_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/util/eape.h
+@@ -0,0 +1,57 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _EAPE_H_
++#define _EAPE_H_
++
++#define EAPE_STATUS (EAPE_BASE_ADDR + 0x0)
++#define EAPE_INT_ENABLE (EAPE_BASE_ADDR + 0x4)
++#define EAPE_INT_SRC (EAPE_BASE_ADDR + 0x8)
++#define EAPE_HOST_INT_ENABLE (EAPE_BASE_ADDR + 0xc)
++
++/** The following bits represents to enable interrupts from host and to host
++* from / to utilpe */
++
++#define IRQ_EN_EFET_TO_UTIL 0x1
++#define IRQ_EN_QB_TO_UTIL 0x2
++#define IRQ_EN_INQ_TO_UTIL 0x4
++#define IRQ_EN_EAPE_TO_UTIL 0x8
++#define IRQ_EN_GPT_TMR_TO_UTIL 0x10
++#define IRQ_EN_UART_TO_UTIL 0x20
++#define IRQ_EN_SYSLP_TO_UTIL 0x40
++#define IRQ_EN_UPEGP_TO_UTIL 0x80
++
++/** Out interrupts */
++
++#define IRQ_EN_EFET_OUT 0x100
++#define IRQ_EN_QB_OUT 0x200
++#define IRQ_EN_INQ_OUT 0x400
++#define IRQ_EN_EAPE_OUT 0x800
++#define IRQ_EN_GPT_TMR_OUT 0x1000
++#define IRQ_EN_UART_OUT 0x2000
++#define IRQ_EN_SYSLP_OUT 0x4000
++#define IRQ_EN_UPEGP_OUT 0x8000
++
++/** The following bits are enabled in the status register
++ * which are mapped to IPSEC status register bits */
++#define EAPE_IN_STAT_AVAIL 0x1
++#define EAPE_OUT_STAT_AVAIL 0x2
++#define EAPE_IN_CMD_AVAIL 0x4
++#define EAPE_OUT_CMD_AVAIL 0x8
++
++#endif /* _EAPE_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/util/efet.h
+@@ -0,0 +1,119 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _UTIL_EFET_H_
++#define _UTIL_EFET_H_
++
++#define EFET_ENTRY_ADDR 0x00
++#define EFET_ENTRY_SIZE 0x04
++#define EFET_ENTRY_DMEM_ADDR 0x08
++#define EFET_ENTRY_STATUS 0x0c
++#define EFET_ENTRY_ENDIAN 0x10
++
++#define CBUS2DMEM 0
++#define DMEM2CBUS 1
++
++#define EFET2BUS_LE (1 << 0)
++
++#define EFET1 0
++#define EFET2 1
++#define EFET3 2
++#define MAX_UTIL_EFET_LEN 128
++
++extern const unsigned long util_efet_baseaddr[3];
++extern u32 util_efet_status;
++
++/* The barrier call is an empirical work-around for an unknown bug: for some unknown reason, it solves
++ * a UtilPE crash observed with LRO and packet steering. Other solutions also worked (e.g. barrier,
++ * nop calls in other positions). However, no common pattern could be extracted from those solutions
++ * to narrow down the source of the crash.
++ */
++
++#define __UTIL_EFET(i, cbus_addr, dmem_addr,len,dir) do { \
++ __writel((len & 0x3FF) | (dir << 16), util_efet_baseaddr[i] + EFET_ENTRY_SIZE); \
++ __writel(dmem_addr, util_efet_baseaddr[i] + EFET_ENTRY_DMEM_ADDR);\
++ __writel(cbus_addr, util_efet_baseaddr[i] + EFET_ENTRY_ADDR);\
++ nop();\
++ }while(0)
++
++#define UTIL_EFET(i, cbus_addr, dmem_addr,len,dir) do { \
++ __UTIL_EFET(i, cbus_addr, dmem_addr, len, dir); \
++ util_efet_status |= (1 << i); \
++ } while(0)
++
++
++/** Waits for the util efet to finish a transaction, blocking the caller
++* (without updating the status).
++* Can be called at any time.
++*
++* @param i Efet index
++*
++*
++*/
++static inline void __util_efet_wait(int i)
++{
++ while (!(readl(util_efet_baseaddr[i] + EFET_ENTRY_STATUS) & 0x1)) ;
++}
++
++/** Waits for the util efet to finish a transaction, blocking the caller.
++* Can be called at any time.
++*
++* @param i Efet index
++*
++*/
++static inline void util_efet_wait(int i)
++{
++ __util_efet_wait(i);
++
++ util_efet_status &= ~(1 << i);
++}
++
++/** Asynchronous interface to util efet read/write functions.
++* It will wait for the efet to finish previous transaction, but does not wait for the current transaction to finish.
++*
++* @param i Efet index
++* @param cbus_addr Cbus address (must be 64bits aligned)
++* @param dmem_addr DMEM address (must be 64bits aligned)
++* @param len Number of bytes to copy (must be 64bits aligned size)
++* @param dir Direction of the transaction (0 - cbus to dmem, 1 - dmem to cbus)
++*
++*/
++static inline void util_efet_async(int i, u32 cbus_addr, u32 dmem_addr, u32 len, u8 dir)
++{
++ if (util_efet_status & (1 << i))
++ util_efet_wait(i);
++
++ UTIL_EFET(i, cbus_addr, dmem_addr, len, dir);
++}
++
++
++static inline void util_efet_async0( u32 cbus_addr, u32 dmem_addr, u32 len, u8 dir)
++{
++ util_efet_async(0, cbus_addr, dmem_addr, len,dir);
++}
++
++/* EFET 2 is aways used for SYNC operations */
++static inline void util_efet_sync2(u32 cbus_addr, u32 dmem_addr, u32 len, u8 dir)
++{
++ __UTIL_EFET(2, cbus_addr, dmem_addr, len,dir);
++ __util_efet_wait(2);
++}
++
++void util_efet_sync0(u32 cbus_addr, u32 dmem_addr, u32 len, u8 dir);
++#endif /* _UTIL_EFET_H_ */
++
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/util/inq.h
+@@ -0,0 +1,28 @@
++/*
++ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ *
++*/
++#ifndef _INQ_H_
++#define _INQ_H_
++
++#define INQ_HOST_GP (INQ_BASE_ADDR + 0x00) /* FIXME what are these for ? */
++#define INQ_UPE_GP (INQ_BASE_ADDR + 0x04) /* FIXME what are these for ? */
++
++#define INQ_QB_PKTPTR (INQ_BASE_ADDR + 0x08)
++#define INQ_FIFO_CNT (INQ_BASE_ADDR + 0x0c)
++
++#endif /* _INQ_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_ctrl.c
+@@ -0,0 +1,363 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifdef __KERNEL__
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/module.h>
++#include <linux/list.h>
++#include <linux/kthread.h>
++#else
++#include "platform.h"
++#endif
++
++#include "pfe_mod.h"
++#include "pfe_ctrl.h"
++
++#include "pfe_ctrl_hal.h"
++
++static struct pe_sync_mailbox CLASS_DMEM_SH2(sync_mailbox);
++static struct pe_sync_mailbox TMU_DMEM_SH2(sync_mailbox);
++
++static struct pe_msg_mailbox CLASS_DMEM_SH2(msg_mailbox);
++static struct pe_msg_mailbox TMU_DMEM_SH2(msg_mailbox);
++
++#if !defined(CONFIG_PLATFORM_LS1012A)
++static u32 CLASS_DMEM_SH2(resume);
++static u32 TMU_DMEM_SH2(resume);
++#endif
++
++#if !defined(CONFIG_UTIL_DISABLED)
++static struct pe_sync_mailbox UTIL_DMEM_SH2(sync_mailbox);
++static struct pe_msg_mailbox UTIL_DMEM_SH2(msg_mailbox);
++static u32 UTIL_DMEM_SH2(resume);
++#endif
++
++static int pfe_ctrl_timer(void *data);
++
++static int initialized = 0;
++
++#define TIMEOUT_MS 1000
++
++int relax(unsigned long end)
++{
++#ifdef __KERNEL__
++ if (time_after(jiffies, end)) {
++ if (time_after(jiffies, end + (TIMEOUT_MS * HZ) / 1000)) {
++ return -1;
++ }
++
++ if (need_resched())
++ schedule();
++ }
++#else
++ udelay(1);
++#endif
++
++ return 0;
++}
++
++#if !defined(CONFIG_PLATFORM_LS1012A)
++void pfe_ctrl_suspend(struct pfe_ctrl *ctrl)
++{
++ int id;
++
++ kthread_stop(ctrl->timer_thread);
++
++ mutex_lock(&ctrl->mutex);
++
++ initialized = 0;
++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++)
++ pe_dmem_write(id, cpu_to_be32(0x1), (unsigned long)virt_to_class_dmem(&class_resume), 4);
++
++ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) {
++#if defined(CONFIG_PLATFORM_LS1012A)
++ if(id == TMU2_ID) continue;
++#endif
++ pe_dmem_write(id, cpu_to_be32(0x1), (unsigned long)virt_to_class_dmem(&tmu_resume), 4);
++ }
++
++#if !defined(CONFIG_UTIL_DISABLED)
++ pe_dmem_write(UTIL_ID, cpu_to_be32(0x1), (unsigned long)virt_to_class_dmem(&util_resume), 4);
++#endif
++
++ pe_sync_stop(&pfe->ctrl, 0xFF);
++
++ mutex_unlock(&ctrl->mutex);
++}
++
++void pfe_ctrl_resume(struct pfe_ctrl *ctrl)
++{
++ mutex_lock(&ctrl->mutex);
++ initialized = 1;
++ pe_start(&pfe->ctrl, 0xFF);
++ mutex_unlock(&ctrl->mutex);
++
++ ctrl->timer_thread = kthread_create(pfe_ctrl_timer, ctrl, "pfe_ctrl_timer");
++
++ wake_up_process(ctrl->timer_thread);
++}
++#endif
++
++/** PE sync stop.
++* Stops packet processing for a list of PE's (specified using a bitmask).
++* The caller must hold ctrl->mutex.
++*
++* @param ctrl Control context
++* @param pe_mask Mask of PE id's to stop
++*
++*/
++int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask)
++{
++ struct pe_sync_mailbox *mbox;
++ int pe_stopped = 0;
++ unsigned long end = jiffies + 2;
++ int i;
++
++#if defined(CONFIG_PLATFORM_LS1012A)
++ //TODO Util should be removed after IPSec is ported
++ pe_mask &= 0x2FF; //Exclude Util + TMU2
++#endif
++ for (i = 0; i < MAX_PE; i++)
++ if (pe_mask & (1 << i)) {
++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
++
++ pe_dmem_write(i, cpu_to_be32(0x1), (unsigned long)&mbox->stop, 4);
++ }
++
++ while (pe_stopped != pe_mask) {
++ for (i = 0; i < MAX_PE; i++)
++ if ((pe_mask & (1 << i)) && !(pe_stopped & (1 << i))) {
++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
++
++ if (pe_dmem_read(i, (unsigned long)&mbox->stopped, 4) & cpu_to_be32(0x1))
++ pe_stopped |= (1 << i);
++ }
++
++ if (relax(end) < 0)
++ goto err;
++ }
++
++ return 0;
++
++err:
++ printk(KERN_ERR "%s: timeout, %x %x\n", __func__, pe_mask, pe_stopped);
++
++ for (i = 0; i < MAX_PE; i++)
++ if (pe_mask & (1 << i)) {
++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
++
++ pe_dmem_write(i, cpu_to_be32(0x0), (unsigned long)&mbox->stop, 4);
++ }
++
++ return -EIO;
++}
++
++/** PE start.
++* Starts packet processing for a list of PE's (specified using a bitmask).
++* The caller must hold ctrl->mutex.
++*
++* @param ctrl Control context
++* @param pe_mask Mask of PE id's to start
++*
++*/
++void pe_start(struct pfe_ctrl *ctrl, int pe_mask)
++{
++ struct pe_sync_mailbox *mbox;
++ int i;
++
++#if defined(CONFIG_PLATFORM_LS1012A)
++ //TODO Util should be removed after IPSec is ported
++ pe_mask &= 0x2FF; //Exclude Util + TMU2
++#endif
++ for (i = 0; i < MAX_PE; i++)
++ if (pe_mask & (1 << i)) {
++
++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
++
++ pe_dmem_write(i, cpu_to_be32(0x0), (unsigned long)&mbox->stop, 4);
++ }
++}
++
++
++/** Sends a control request to a given PE (to copy data to/from internal memory from/to DDR).
++* The caller must hold ctrl->mutex.
++*
++* @param ctrl Control context
++* @param id PE id
++* @param dst Physical destination address of data
++* @param src Physical source address of data
++* @param len Data length
++*
++*/
++int pe_request(struct pfe_ctrl *ctrl, int id, unsigned short cmd_type, unsigned long dst, unsigned long src, int len)
++{
++ struct pe_msg_mailbox mbox = {
++ .dst = cpu_to_be32(dst),
++ .src = cpu_to_be32(src),
++ .len = cpu_to_be32(len),
++ .request = cpu_to_be32((cmd_type << 16) | 0x1),
++ };
++ struct pe_msg_mailbox *pmbox = (void *)ctrl->msg_mailbox_baseaddr[id];
++ unsigned long end = jiffies + 2;
++ u32 rc;
++
++ /* This works because .request is written last */
++ pe_dmem_memcpy_to32(id, (unsigned long)pmbox, &mbox, sizeof(mbox));
++
++ while ((rc = pe_dmem_read(id, (unsigned long)&pmbox->request, 4)) & cpu_to_be32(0xffff)) {
++ if (relax(end) < 0)
++ goto err;
++ }
++
++ rc = be32_to_cpu(rc);
++
++ return rc >> 16;
++
++err:
++ printk(KERN_ERR "%s: timeout, %x\n", __func__, be32_to_cpu(rc));
++ pe_dmem_write(id, cpu_to_be32(0), (unsigned long)&pmbox->request, 4);
++ return -EIO;
++}
++
++
++/** Control code timer thread.
++*
++* A kernel thread is used so that the timer code can be run under the control path mutex.
++* The thread wakes up regularly and checks if any timer in the timer list as expired.
++* The timers are re-started automatically.
++* The code tries to keep the number of times a timer runs per unit time constant on average,
++* if the thread scheduling is delayed, it's possible for a particular timer to be scheduled in
++* quick succession to make up for the lost time.
++*
++* @param data Pointer to the control context structure
++*
++* @return 0 on sucess, a negative value on error
++*
++*/
++static int pfe_ctrl_timer(void *data)
++{
++ struct pfe_ctrl *ctrl = data;
++ TIMER_ENTRY *timer, *next;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ while (1)
++ {
++ schedule_timeout_uninterruptible(ctrl->timer_period);
++
++ mutex_lock(&ctrl->mutex);
++
++ list_for_each_entry_safe(timer, next, &ctrl->timer_list, list)
++ {
++ if (time_after(jiffies, timer->timeout))
++ {
++ timer->timeout += timer->period;
++
++ timer->handler();
++ }
++ }
++
++ mutex_unlock(&ctrl->mutex);
++
++ if (kthread_should_stop())
++ break;
++ }
++
++ printk(KERN_INFO "%s exiting\n", __func__);
++
++ return 0;
++}
++
++
++int pfe_ctrl_init(struct pfe *pfe)
++{
++ struct pfe_ctrl *ctrl = &pfe->ctrl;
++ int id;
++ int rc;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ mutex_init(&ctrl->mutex);
++ spin_lock_init(&ctrl->lock);
++
++ ctrl->timer_period = HZ / TIMER_TICKS_PER_SEC;
++
++ INIT_LIST_HEAD(&ctrl->timer_list);
++
++ /*INIT_WORK(&ctrl->work, comcerto_fpp_workqueue);*/
++
++ INIT_LIST_HEAD(&ctrl->msg_list);
++
++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
++ ctrl->sync_mailbox_baseaddr[id] = virt_to_class_dmem(&class_sync_mailbox);
++ ctrl->msg_mailbox_baseaddr[id] = virt_to_class_dmem(&class_msg_mailbox);
++ }
++
++ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) {
++#if defined(CONFIG_PLATFORM_LS1012A)
++ if(id == TMU2_ID) continue;
++#endif
++ ctrl->sync_mailbox_baseaddr[id] = virt_to_tmu_dmem(&tmu_sync_mailbox);
++ ctrl->msg_mailbox_baseaddr[id] = virt_to_tmu_dmem(&tmu_msg_mailbox);
++ }
++
++#if !defined(CONFIG_UTIL_DISABLED)
++ ctrl->sync_mailbox_baseaddr[UTIL_ID] = virt_to_util_dmem(&util_sync_mailbox);
++ ctrl->msg_mailbox_baseaddr[UTIL_ID] = virt_to_util_dmem(&util_msg_mailbox);
++#endif
++
++ ctrl->hash_array_baseaddr = pfe->ddr_baseaddr + ROUTE_TABLE_BASEADDR;
++ ctrl->hash_array_phys_baseaddr = pfe->ddr_phys_baseaddr + ROUTE_TABLE_BASEADDR;
++ ctrl->ipsec_lmem_phys_baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR + IPSEC_LMEM_BASEADDR);
++ ctrl->ipsec_lmem_baseaddr = (LMEM_BASE_ADDR + IPSEC_LMEM_BASEADDR);
++
++ ctrl->timer_thread = kthread_create(pfe_ctrl_timer, ctrl, "pfe_ctrl_timer");
++ if (IS_ERR(ctrl->timer_thread))
++ {
++ printk (KERN_ERR "%s: kthread_create() failed\n", __func__);
++ rc = PTR_ERR(ctrl->timer_thread);
++ goto err0;
++ }
++
++ ctrl->dev = pfe->dev;
++
++ wake_up_process(ctrl->timer_thread);
++
++ printk(KERN_INFO "%s finished\n", __func__);
++
++ initialized = 1;
++
++ return 0;
++
++err0:
++ return rc;
++}
++
++
++void pfe_ctrl_exit(struct pfe *pfe)
++{
++ struct pfe_ctrl *ctrl = &pfe->ctrl;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ initialized = 0;
++
++ kthread_stop(ctrl->timer_thread);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_ctrl.h
+@@ -0,0 +1,111 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _PFE_CTRL_H_
++#define _PFE_CTRL_H_
++
++#include <linux/dmapool.h>
++
++#include "pfe_mod.h"
++#include "pfe/pfe.h"
++
++#define DMA_BUF_SIZE_128 0x80 /* enough for 1 conntracks */
++#define DMA_BUF_SIZE_256 0x100 /* enough for 2 conntracks, 1 bridge entry or 1 multicast entry */
++#define DMA_BUF_SIZE_512 0x200 /* 512bytes dma allocated buffers used by rtp relay feature */
++#define DMA_BUF_MIN_ALIGNMENT 8
++#define DMA_BUF_BOUNDARY (4 * 1024) /* bursts can not cross 4k boundary */
++
++#define CMD_TX_ENABLE 0x0501
++#define CMD_TX_DISABLE 0x0502
++
++#define CMD_RX_LRO 0x0011
++#define CMD_PKTCAP_ENABLE 0x0d01
++#define CMD_QM_EXPT_RATE 0x020c
++
++#define EXPT_TYPE_PCAP 0x3
++
++struct pfe_ctrl {
++ struct mutex mutex;
++ spinlock_t lock;
++
++ void *dma_pool;
++ void *dma_pool_512;
++ void *dma_pool_128;
++
++ struct device *dev;
++
++ void *hash_array_baseaddr; /** Virtual base address of the conntrack hash array */
++ unsigned long hash_array_phys_baseaddr; /** Physical base address of the conntrack hash array */
++
++ struct task_struct *timer_thread;
++ struct list_head timer_list;
++ unsigned long timer_period;
++
++ int (*event_cb)(u16, u16, u16*);
++
++ unsigned long sync_mailbox_baseaddr[MAX_PE]; /* Sync mailbox PFE internal address, initialized when parsing elf images */
++ unsigned long msg_mailbox_baseaddr[MAX_PE]; /* Msg mailbox PFE internal address, initialized when parsing elf images */
++
++ unsigned long class_dmem_sh;
++ unsigned long class_pe_lmem_sh;
++ unsigned long tmu_dmem_sh;
++ unsigned long util_dmem_sh;
++ unsigned long util_ddr_sh;
++ struct clk *clk_axi;
++ unsigned int sys_clk; // AXI clock value, in KHz
++ void *ipsec_lmem_baseaddr;
++ unsigned long ipsec_lmem_phys_baseaddr;
++
++ /* used for asynchronous message transfer to PFE */
++ struct list_head msg_list;
++ struct work_struct work;
++};
++
++int pfe_ctrl_init(struct pfe *pfe);
++void pfe_ctrl_exit(struct pfe *pfe);
++
++int pe_send_cmd(unsigned short cmd_type, unsigned short action, unsigned long param1, unsigned long param2);
++int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask);
++void pe_start(struct pfe_ctrl *ctrl, int pe_mask);
++int pe_request(struct pfe_ctrl *ctrl, int id,unsigned short cmd_type, unsigned long dst, unsigned long src, int len);
++int pe_read(struct pfe_ctrl *ctrl, int id, u32 *dst, unsigned long src, int len, int clear_flag);
++int tmu_pe_request(struct pfe_ctrl *ctrl, int id, unsigned int tmu_cmd_bitmask);
++
++int pfe_ctrl_set_eth_state(int id, unsigned int state, unsigned char *mac_addr);
++int pfe_ctrl_set_lro(char enable);
++#ifdef CFG_PCAP
++int pfe_ctrl_set_pcap(char enable);
++int pfe_ctrl_set_pcap_ratelimit(u32 pkts_per_msec);
++#endif
++void pfe_ctrl_suspend(struct pfe_ctrl *ctrl);
++void pfe_ctrl_resume(struct pfe_ctrl *ctrl);
++int relax(unsigned long end);
++
++/* used for asynchronous message transfer to PFE */
++#define FPP_MAX_MSG_LENGTH 256 /* expressed in U8 -> 256 bytes*/
++struct fpp_msg {
++ struct list_head list;
++ void (*callback)(unsigned long, int, u16, u16 *);
++ unsigned long data;
++ u16 fcode;
++ u16 length;
++ u16 *payload;
++};
++
++#endif /* _PFE_CTRL_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_ctrl_hal.c
+@@ -0,0 +1,207 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++/* OS abstraction functions used by PFE control code */
++
++#include <linux/slab.h>
++
++#include "pfe_ctrl_hal.h"
++
++#include "pfe_mod.h"
++
++extern char *__class_dmem_sh;
++extern char *__tmu_dmem_sh;
++#if !defined(CONFIG_UTIL_DISABLED)
++extern char *__util_dmem_sh;
++extern char *__util_ddr_sh;
++#endif
++
++HostMessage msg_buf;
++static int msg_buf_used = 0;
++unsigned long virt_to_class_dmem(void *p)
++{
++ struct pfe_ctrl *ctrl = &pfe->ctrl;
++
++ if (p)
++ return (unsigned long)p - (unsigned long)&__class_dmem_sh + ctrl->class_dmem_sh;
++ else
++ return 0;
++}
++unsigned long virt_to_tmu_dmem(void *p)
++{
++ struct pfe_ctrl *ctrl = &pfe->ctrl;
++
++ if (p)
++ return (unsigned long)p - (unsigned long)&__tmu_dmem_sh + ctrl->tmu_dmem_sh;
++ else
++ return 0;
++}
++
++
++#if !defined(CONFIG_UTIL_DISABLED)
++unsigned long virt_to_util_dmem(void *p)
++{
++ struct pfe_ctrl *ctrl = &pfe->ctrl;
++
++ if (p)
++ return (unsigned long)p - (unsigned long)&__util_dmem_sh + ctrl->util_dmem_sh;
++ else
++ return 0;
++}
++
++/** Returns the DDR physical address of a Util PE shared DDR variable.
++ *
++ * @param p pointer (kernel space, virtual) to be converted to a physical address.
++ */
++unsigned long virt_to_util_ddr(void *p)
++{
++ struct pfe_ctrl *ctrl = &pfe->ctrl;
++
++ if (p)
++ return (unsigned long)p - (unsigned long)&__util_ddr_sh + ctrl->util_ddr_sh;
++ else
++ return 0;
++}
++/** Returns the virtual address of a Util PE shared DDR variable.
++ *
++ * @param p pointer (kernel space, virtual) to be converted to a pointer (usable in kernel space)
++ * pointing to the actual data.
++ */
++
++void * virt_to_util_virt(void *p)
++{
++ if (p)
++ return DDR_PHYS_TO_VIRT(virt_to_util_ddr(p));
++ else
++ return NULL;
++}
++#endif
++unsigned long virt_to_phys_iram(void *p)
++{
++ if (p)
++ return (p - pfe->iram_baseaddr) + pfe->iram_phys_baseaddr;
++ else
++ return 0;
++}
++
++unsigned long virt_to_phys_ipsec_lmem(void *p)
++{
++ struct pfe_ctrl *ctrl = &pfe->ctrl;
++
++ if (p)
++ return (p - ctrl->ipsec_lmem_baseaddr) + ctrl->ipsec_lmem_phys_baseaddr;
++ else
++ return 0;
++}
++
++unsigned long virt_to_phys_ipsec_axi(void *p)
++{
++ if (p)
++ return (p - pfe->ipsec_baseaddr) + pfe->ipsec_phys_baseaddr;
++ else
++ return 0;
++}
++
++
++HostMessage *msg_alloc(void)
++{
++ if (msg_buf_used)
++ {
++ printk(KERN_ERR "%s: failed\n", __func__);
++ return NULL;
++ }
++
++ msg_buf_used = 1;
++
++ return &msg_buf;
++}
++
++void msg_free(HostMessage *msg)
++{
++ if (!msg_buf_used)
++ printk(KERN_ERR "%s: freing already free msg buffer\n", __func__);
++
++ msg_buf_used = 0;
++}
++
++int msg_send(HostMessage *msg)
++{
++ struct pfe_ctrl *ctrl = &pfe->ctrl;
++ int rc = -1;
++
++ if (!ctrl->event_cb)
++ goto out;
++
++ if (ctrl->event_cb(msg->code, msg->length, msg->data) < 0)
++ goto out;
++
++ rc = 0;
++
++out:
++ msg_free(msg);
++
++ return rc;
++}
++
++
++void timer_init(TIMER_ENTRY *timer, TIMER_HANDLER handler)
++{
++ timer->handler = handler;
++ timer->running = 0;
++}
++
++
++void timer_add(TIMER_ENTRY *timer, u16 granularity)
++{
++ struct pfe_ctrl *ctrl = &pfe->ctrl;
++
++
++ timer->period = granularity;
++ timer->timeout = jiffies + timer->period;
++
++ if (!timer->running)
++ {
++ list_add(&timer->list, &ctrl->timer_list);
++ timer->running = 1;
++ }
++}
++
++
++void timer_del(TIMER_ENTRY *timer)
++{
++
++ if (timer->running)
++ {
++ list_del(&timer->list);
++ timer->running = 0;
++ }
++}
++
++
++void *Heap_Alloc(int size)
++{
++ /* FIXME we may want to use dma API's and use non cacheable memory */
++ return pfe_kmalloc(size, GFP_KERNEL);
++}
++
++
++void Heap_Free(void *p)
++{
++ pfe_kfree(p);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_ctrl_hal.h
+@@ -0,0 +1,129 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _PFE_CTRL_HAL_H_
++#define _PFE_CTRL_HAL_H_
++
++#include <linux/timer.h>
++#include <linux/jiffies.h>
++#include <linux/string.h>
++#include <linux/elf.h>
++#include <linux/slab.h>
++#include <asm/byteorder.h>
++#include <asm/io.h>
++
++#include "pfe_mod.h"
++
++#define CLASS_DMEM_SH(var) __attribute__((section(".class_dmem_sh_" #var))) var
++#define CLASS_PE_LMEM_SH(var) __attribute__((section(".class_pe_lmem_sh_" #var))) var
++#define TMU_DMEM_SH(var) __attribute__((section(".tmu_dmem_sh_" #var))) var
++#define UTIL_DMEM_SH(var) __attribute__((section(".util_dmem_sh_" #var))) var
++#define UTIL_DDR_SH(var) __attribute__((section(".util_ddr_sh_" #var))) var
++
++#define CLASS_DMEM_SH2(var) __attribute__((section(".class_dmem_sh_" #var))) class_##var
++#define CLASS_PE_LMEM_SH2(var) __attribute__((section(".class_pe_lmem_sh_" #var))) class_##var
++#define TMU_DMEM_SH2(var) __attribute__((section(".tmu_dmem_sh_" #var))) tmu_##var
++#define UTIL_DMEM_SH2(var) __attribute__((section(".util_dmem_sh_" #var))) util_##var
++
++/** Translate the name of a shared variable to its PFE counterpart.
++ * Those macros may be used to determine the address of a shared variable,
++ * and will work even if the variable is accessed through a macro, as is the case
++ * with most fields of gFppGlobals.
++ */
++#define CONCAT(str, var) str##var
++#define CLASS_VARNAME2(var) CONCAT(class_, var)
++#define UTIL_VARNAME2(var) CONCAT(util_, var)
++#define TMU_VARNAME2(var) CONCAT(tmu_, var)
++
++typedef struct tHostMessage {
++ u16 length;
++ u16 code;
++ u16 data[128];
++} HostMessage;
++
++HostMessage *msg_alloc(void);
++void msg_free(HostMessage *msg);
++int msg_send(HostMessage *msg);
++
++
++unsigned long virt_to_class(void *p);
++unsigned long virt_to_class_dmem(void *p);
++unsigned long virt_to_class_pe_lmem(void *p);
++unsigned long virt_to_tmu_dmem(void *p);
++unsigned long virt_to_util_dmem(void *p);
++unsigned long virt_to_util_ddr(void *p);
++void * virt_to_util_virt(void *p);
++unsigned long virt_to_phys_iram(void *p);
++unsigned long virt_to_phys_ipsec_lmem(void *p);
++unsigned long virt_to_phys_ipsec_axi(void *p);
++
++
++#define TIMER_TICKS_PER_SEC 100
++
++#if TIMER_TICKS_PER_SEC > HZ
++#error TIMER_TICKS_PER_SEC is too high
++#endif
++
++
++typedef void (* TIMER_HANDLER)(void);
++
++typedef struct {
++ struct list_head list;
++ unsigned long timeout;
++ unsigned long period;
++ TIMER_HANDLER handler;
++ char running;
++} TIMER_ENTRY;
++
++
++/** Initializes a timer structure.
++* Must be called once for each TIMER_ENTRY structure.
++* The caller must be holding the ctrl->mutex.
++*
++* @param timer pointer to the timer to be initialized
++* @param handler timer handler function pointer
++*
++*/
++void timer_init(TIMER_ENTRY *timer, TIMER_HANDLER handler);
++
++/** Adds a timer to the running timer list.
++* It's safe to call even if the timer was already running. In this case we just update the granularity.
++* The caller must be holding the ctrl->mutex.
++*
++* @param timer pointer to the timer to be added
++* @param granularity granularity of the timer (in timer tick units)
++*
++*/
++void timer_add(TIMER_ENTRY *timer, u16 granularity);
++
++/** Deletes a timer from the running timer list.
++* It's safe to call even if the timer is no longer running.
++* The caller must be holding the ctrl->mutex.
++*
++* @param timer pointer to the timer to be removed
++*/
++void timer_del(TIMER_ENTRY *timer);
++
++void *Heap_Alloc(int size);
++
++#define Heap_Alloc_ARAM(s) Heap_Alloc(s)
++#define __Heap_Alloc(h, s) Heap_Alloc(s)
++void Heap_Free(void *p);
++
++#endif /* _PFE_CTRL_HAL_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_debugfs.c
+@@ -0,0 +1,109 @@
++/*
++ * (C) Copyright 2013
++ * Author : Freescale Technologes
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ * */
++
++#include <linux/module.h>
++#include <linux/debugfs.h>
++#include <linux/platform_device.h>
++
++#include "pfe_mod.h"
++
++static int dmem_show(struct seq_file *s, void *unused)
++{
++ u32 dmem_addr, val;
++ int id = (long int)s->private;
++ int i;
++
++ for (dmem_addr = 0; dmem_addr < CLASS_DMEM_SIZE; dmem_addr += 8 * 4) {
++ seq_printf(s, "%04x:", dmem_addr);
++
++ for (i = 0; i < 8; i++) {
++ val = pe_dmem_read(id, dmem_addr + i * 4, 4);
++ seq_printf(s, " %02x %02x %02x %02x", val & 0xff, (val >> 8) & 0xff, (val >> 16) & 0xff, (val >> 24) & 0xff);
++ }
++
++ seq_printf(s, "\n");
++ }
++
++ return 0;
++}
++
++static int dmem_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, dmem_show, inode->i_private);
++}
++
++static const struct file_operations dmem_fops = {
++ .open = dmem_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++int pfe_debugfs_init(struct pfe *pfe)
++{
++ struct dentry *d;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ pfe->dentry = debugfs_create_dir("pfe", NULL);
++ if (IS_ERR_OR_NULL(pfe->dentry))
++ goto err_dir;
++
++ d = debugfs_create_file("pe0_dmem", S_IRUGO, pfe->dentry, (void *)0, &dmem_fops);
++ if (IS_ERR_OR_NULL(d))
++ goto err_pe;
++
++ d = debugfs_create_file("pe1_dmem", S_IRUGO, pfe->dentry, (void *)1, &dmem_fops);
++ if (IS_ERR_OR_NULL(d))
++ goto err_pe;
++
++ d = debugfs_create_file("pe2_dmem", S_IRUGO, pfe->dentry, (void *)2, &dmem_fops);
++ if (IS_ERR_OR_NULL(d))
++ goto err_pe;
++
++ d = debugfs_create_file("pe3_dmem", S_IRUGO, pfe->dentry, (void *)3, &dmem_fops);
++ if (IS_ERR_OR_NULL(d))
++ goto err_pe;
++
++ d = debugfs_create_file("pe4_dmem", S_IRUGO, pfe->dentry, (void *)4, &dmem_fops);
++ if (IS_ERR_OR_NULL(d))
++ goto err_pe;
++
++ d = debugfs_create_file("pe5_dmem", S_IRUGO, pfe->dentry, (void *)5, &dmem_fops);
++ if (IS_ERR_OR_NULL(d))
++ goto err_pe;
++
++ return 0;
++
++err_pe:
++ debugfs_remove_recursive(pfe->dentry);
++
++err_dir:
++ return -1;
++}
++
++void pfe_debugfs_exit(struct pfe *pfe)
++{
++ debugfs_remove_recursive(pfe->dentry);
++}
++
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_debugfs.h
+@@ -0,0 +1,8 @@
++#ifndef _PFE_DEBUGFS_H_
++#define _PFE_DEBUGFS_H_
++
++int pfe_debugfs_init(struct pfe *pfe);
++void pfe_debugfs_exit(struct pfe *pfe);
++#endif /* _PFE_DEBUGFS_H_ */
++
++
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_eth.c
+@@ -0,0 +1,2956 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++/** @pfe_eth.c.
++ * Ethernet driver for to handle exception path for PFE.
++ * - uses HIF functions to send/receive packets.
++ * - uses ctrl function to start/stop interfaces.
++ * - uses direct register accesses to control phy operation.
++ */
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool.h>
++#include <linux/mii.h>
++#include <linux/phy.h>
++#include <linux/timer.h>
++#include <linux/hrtimer.h>
++#include <linux/platform_device.h>
++
++#include <net/ip.h>
++#include <net/sock.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/delay.h>
++#include <linux/regmap.h>
++#include <linux/i2c.h>
++
++#if defined(CONFIG_NF_CONNTRACK_MARK)
++#include <net/netfilter/nf_conntrack.h>
++#endif
++
++#include "pfe_mod.h"
++#include "pfe_eth.h"
++
++const char comcerto_eth_driver_version[]="1.0";
++static void *cbus_emac_base[3];
++static void *cbus_gpi_base[3];
++
++/* Forward Declaration */
++static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv);
++static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv, int force);
++static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int txQ_num, int from_tx, int n_desc);
++
++#if defined(CONFIG_PLATFORM_C2000)
++static void pfe_eth_set_device_wakeup(struct pfe *pfe);
++
++
++
++unsigned int gemac_regs[] = {
++ 0x0000, /* Network control */
++ 0x0004, /* Network configuration */
++ 0x0008, /* Network status */
++ 0x0010, /* DMA configuration */
++ 0x0014, /* Transmit status */
++ 0x0020, /* Receive status */
++ 0x0024, /* Interrupt status */
++ 0x0030, /* Interrupt mask */
++ 0x0038, /* Received pause quantum */
++ 0x003c, /* Transmit pause quantum */
++ 0x0080, /* Hash register bottom [31:0] */
++ 0x0084, /* Hash register bottom [63:32] */
++ 0x0088, /* Specific address 1 bottom [31:0] */
++ 0x008c, /* Specific address 1 top [47:32] */
++ 0x0090, /* Specific address 2 bottom [31:0] */
++ 0x0094, /* Specific address 2 top [47:32] */
++ 0x0098, /* Specific address 3 bottom [31:0] */
++ 0x009c, /* Specific address 3 top [47:32] */
++ 0x00a0, /* Specific address 4 bottom [31:0] */
++ 0x00a4, /* Specific address 4 top [47:32] */
++ 0x00a8, /* Type ID Match 1 */
++ 0x00ac, /* Type ID Match 2 */
++ 0x00b0, /* Type ID Match 3 */
++ 0x00b4, /* Type ID Match 4 */
++ 0x00b8, /* Wake Up ON LAN */
++ 0x00bc, /* IPG stretch register */
++ 0x00c0, /* Stacked VLAN Register */
++ 0x00fc, /* Module ID */
++ 0x07a0 /* EMAC Control register */
++};
++#else
++unsigned int gemac_regs[] = {
++ 0x0004, /*Interrupt event */
++ 0x0008, /*Interrupt mask */
++ 0x0024, /*Ethernet control */
++ 0x0064, /*MIB Control/Status */
++ 0x0084, /*Receive control/status */
++ 0x00C4, /*Transmit control */
++ 0x00E4, /*Physical address low */
++ 0x00E8, /*Physical address high */
++ 0x0144, /*Transmit FIFO Watermark and Store and Forward Control*/
++ 0x0190, /* Receive FIFO Section Full Threshold */
++ 0x01A0, /* Transmit FIFO Section Empty Threshold */
++ 0x01B0, /* Frame Truncation Length */
++};
++#endif
++/********************************************************************/
++/* SYSFS INTERFACE */
++/********************************************************************/
++
++
++
++#ifdef PFE_ETH_NAPI_STATS
++/*
++ * pfe_eth_show_napi_stats
++ */
++static ssize_t pfe_eth_show_napi_stats(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++ ssize_t len = 0;
++
++ len += sprintf(buf + len, "sched: %u\n", priv->napi_counters[NAPI_SCHED_COUNT]);
++ len += sprintf(buf + len, "poll: %u\n", priv->napi_counters[NAPI_POLL_COUNT]);
++ len += sprintf(buf + len, "packet: %u\n", priv->napi_counters[NAPI_PACKET_COUNT]);
++ len += sprintf(buf + len, "budget: %u\n", priv->napi_counters[NAPI_FULL_BUDGET_COUNT]);
++ len += sprintf(buf + len, "desc: %u\n", priv->napi_counters[NAPI_DESC_COUNT]);
++
++ return len;
++}
++
++/*
++ * pfe_eth_set_napi_stats
++ */
++static ssize_t pfe_eth_set_napi_stats(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++
++ memset(priv->napi_counters, 0, sizeof(priv->napi_counters));
++
++ return count;
++}
++#endif
++#ifdef PFE_ETH_TX_STATS
++/** pfe_eth_show_tx_stats
++ *
++ */
++static ssize_t pfe_eth_show_tx_stats(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++ ssize_t len = 0;
++ int i;
++
++ len += sprintf(buf + len, "TX queues stats:\n");
++
++ for (i = 0; i < emac_txq_cnt; i++) {
++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->dev, i);
++
++ len += sprintf(buf + len, "\n");
++ __netif_tx_lock_bh(tx_queue);
++
++ hif_tx_lock(&pfe->hif);
++ len += sprintf(buf + len, "Queue %2d : credits = %10d\n", i, hif_lib_tx_credit_avail(pfe, priv->id, i));
++ len += sprintf(buf + len, " tx packets = %10d\n", pfe->tmu_credit.tx_packets[priv->id][i]);
++ hif_tx_unlock(&pfe->hif);
++
++ /* Don't output additionnal stats if queue never used */
++ if (!pfe->tmu_credit.tx_packets[priv->id][i])
++ goto skip;
++
++ len += sprintf(buf + len, " clean_fail = %10d\n", priv->clean_fail[i]);
++ len += sprintf(buf + len, " stop_queue = %10d\n", priv->stop_queue_total[i]);
++ len += sprintf(buf + len, " stop_queue_hif = %10d\n", priv->stop_queue_hif[i]);
++ len += sprintf(buf + len, " stop_queue_hif_client = %10d\n", priv->stop_queue_hif_client[i]);
++ len += sprintf(buf + len, " stop_queue_credit = %10d\n", priv->stop_queue_credit[i]);
++skip:
++ __netif_tx_unlock_bh(tx_queue);
++ }
++ return len;
++}
++
++/** pfe_eth_set_tx_stats
++ *
++ */
++static ssize_t pfe_eth_set_tx_stats(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++ int i;
++
++ for (i = 0; i < emac_txq_cnt; i++) {
++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->dev, i);
++
++ __netif_tx_lock_bh(tx_queue);
++ priv->clean_fail[i] = 0;
++ priv->stop_queue_total[i] = 0;
++ priv->stop_queue_hif[i] = 0;
++ priv->stop_queue_hif_client[i]= 0;
++ priv->stop_queue_credit[i] = 0;
++ __netif_tx_unlock_bh(tx_queue);
++ }
++
++ return count;
++}
++#endif
++/** pfe_eth_show_txavail
++ *
++ */
++static ssize_t pfe_eth_show_txavail(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++ ssize_t len = 0;
++ int i;
++
++ for (i = 0; i < emac_txq_cnt; i++) {
++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->dev, i);
++
++ __netif_tx_lock_bh(tx_queue);
++
++ len += sprintf(buf + len, "%d", hif_lib_tx_avail(&priv->client, i));
++
++ __netif_tx_unlock_bh(tx_queue);
++
++ if (i == (emac_txq_cnt - 1))
++ len += sprintf(buf + len, "\n");
++ else
++ len += sprintf(buf + len, " ");
++ }
++
++ return len;
++}
++
++
++/** pfe_eth_show_default_priority
++ *
++ */
++static ssize_t pfe_eth_show_default_priority(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++ unsigned long flags;
++ int rc;
++
++ spin_lock_irqsave(&priv->lock, flags);
++ rc = sprintf(buf, "%d\n", priv->default_priority);
++ spin_unlock_irqrestore(&priv->lock, flags);
++
++ return rc;
++}
++
++/** pfe_eth_set_default_priority
++ *
++ */
++
++static ssize_t pfe_eth_set_default_priority(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++ unsigned long flags;
++
++ spin_lock_irqsave(&priv->lock, flags);
++ priv->default_priority = simple_strtoul(buf, NULL, 0);
++ spin_unlock_irqrestore(&priv->lock, flags);
++
++ return count;
++}
++
++static DEVICE_ATTR(txavail, 0444, pfe_eth_show_txavail, NULL);
++static DEVICE_ATTR(default_priority, 0644, pfe_eth_show_default_priority, pfe_eth_set_default_priority);
++
++#ifdef PFE_ETH_NAPI_STATS
++static DEVICE_ATTR(napi_stats, 0644, pfe_eth_show_napi_stats, pfe_eth_set_napi_stats);
++#endif
++
++#ifdef PFE_ETH_TX_STATS
++static DEVICE_ATTR(tx_stats, 0644, pfe_eth_show_tx_stats, pfe_eth_set_tx_stats);
++#endif
++
++
++/** pfe_eth_sysfs_init
++ *
++ */
++static int pfe_eth_sysfs_init(struct net_device *dev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ int err;
++
++ /* Initialize the default values */
++ /* By default, packets without conntrack will use this default high priority queue */
++ priv->default_priority = 15;
++
++ /* Create our sysfs files */
++ err = device_create_file(&dev->dev, &dev_attr_default_priority);
++ if (err) {
++ netdev_err(dev, "failed to create default_priority sysfs files\n");
++ goto err_priority;
++ }
++
++ err = device_create_file(&dev->dev, &dev_attr_txavail);
++ if (err) {
++ netdev_err(dev, "failed to create default_priority sysfs files\n");
++ goto err_txavail;
++ }
++
++#ifdef PFE_ETH_NAPI_STATS
++ err = device_create_file(&dev->dev, &dev_attr_napi_stats);
++ if (err) {
++ netdev_err(dev, "failed to create napi stats sysfs files\n");
++ goto err_napi;
++ }
++#endif
++
++#ifdef PFE_ETH_TX_STATS
++ err = device_create_file(&dev->dev, &dev_attr_tx_stats);
++ if (err) {
++ netdev_err(dev, "failed to create tx stats sysfs files\n");
++ goto err_tx;
++ }
++#endif
++
++ return 0;
++
++#ifdef PFE_ETH_TX_STATS
++err_tx:
++#endif
++#ifdef PFE_ETH_NAPI_STATS
++ device_remove_file(&dev->dev, &dev_attr_napi_stats);
++
++err_napi:
++#endif
++ device_remove_file(&dev->dev, &dev_attr_txavail);
++
++err_txavail:
++ device_remove_file(&dev->dev, &dev_attr_default_priority);
++
++err_priority:
++ return -1;
++}
++
++/** pfe_eth_sysfs_exit
++ *
++ */
++void pfe_eth_sysfs_exit(struct net_device *dev)
++{
++#ifdef PFE_ETH_TX_STATS
++ device_remove_file(&dev->dev, &dev_attr_tx_stats);
++#endif
++
++#ifdef PFE_ETH_NAPI_STATS
++ device_remove_file(&dev->dev, &dev_attr_napi_stats);
++#endif
++ device_remove_file(&dev->dev, &dev_attr_txavail);
++ device_remove_file(&dev->dev, &dev_attr_default_priority);
++}
++
++/*************************************************************************/
++/* ETHTOOL INTERCAE */
++/*************************************************************************/
++
++#if defined(CONFIG_PLATFORM_C2000)
++static char stat_gstrings[][ETH_GSTRING_LEN] = {
++ "tx- octets",
++ "tx- packets",
++ "tx- broadcast",
++ "tx- multicast",
++ "tx- pause",
++ "tx- 64 bytes packets",
++ "tx- 64 - 127 bytes packets",
++ "tx- 128 - 255 bytes packets",
++ "tx- 256 - 511 bytes packets",
++ "tx- 512 - 1023 bytes packets",
++ "tx- 1024 - 1518 bytes packets",
++ "tx- > 1518 bytes packets",
++ "tx- underruns - errors",
++ "tx- single collision",
++ "tx- multi collision",
++ "tx- exces. collision - errors",
++ "tx- late collision - errors",
++ "tx- deferred",
++ "tx- carrier sense - errors",
++ "rx- octets",
++ "rx- packets",
++ "rx- broadcast",
++ "rx- multicast",
++ "rx- pause",
++ "rx- 64 bytes packets",
++ "rx- 64 - 127 bytes packets",
++ "rx- 128 - 255 bytes packets",
++ "rx- 256 - 511 bytes packets",
++ "rx- 512 - 1023 bytes packets",
++ "rx- 1024 - 1518 bytes packets",
++ "rx- > 1518 bytes packets",
++ "rx- undersize -errors",
++ "rx- oversize - errors ",
++ "rx- jabbers - errors",
++ "rx- fcs - errors",
++ "rx- length - errors",
++ "rx- symbol - errors",
++ "rx- align - errors",
++ "rx- ressource - errors",
++ "rx- overrun - errors",
++ "rx- IP cksum - errors",
++ "rx- TCP cksum - errors",
++ "rx- UDP cksum - errors"
++};
++
++
++/**
++ * pfe_eth_gstrings - Fill in a buffer with the strings which correspond to
++ * the stats.
++ *
++ */
++static void pfe_eth_gstrings(struct net_device *dev, u32 stringset, u8 * buf)
++{
++ switch (stringset) {
++ case ETH_SS_STATS:
++ memcpy(buf, stat_gstrings, (EMAC_RMON_LEN - 2) * ETH_GSTRING_LEN);
++ break;
++
++ default:
++ WARN_ON(1);
++ break;
++ }
++}
++
++/**
++ * pfe_eth_fill_stats - Fill in an array of 64-bit statistics from
++ * various sources. This array will be appended
++ * to the end of the ethtool_stats* structure, and
++ * returned to user space
++ */
++static void pfe_eth_fill_stats(struct net_device *dev, struct ethtool_stats *dummy, u64 * buf)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ int i;
++ for (i=0;i<EMAC_RMON_LEN;i++, buf++) {
++ *buf = readl(priv->EMAC_baseaddr + EMAC_RMON_BASE_OFST + (i << 2));
++ if ( ( i == EMAC_RMON_TXBYTES_POS ) || ( i == EMAC_RMON_RXBYTES_POS ) ){
++ i++;
++ *buf |= (u64)readl(priv->EMAC_baseaddr + EMAC_RMON_BASE_OFST + (i << 2)) << 32;
++ }
++ }
++
++}
++
++/**
++ * pfe_eth_stats_count - Returns the number of stats (and their corresponding strings)
++ *
++ */
++static int pfe_eth_stats_count(struct net_device *dev, int sset)
++{
++ switch (sset) {
++ case ETH_SS_STATS:
++ return EMAC_RMON_LEN - 2;
++ default:
++ return -EOPNOTSUPP;
++ }
++}
++
++#if defined(CONFIG_PLATFORM_C2000)
++/**
++ * pfe_eth_set_wol - Set the magic packet option, in WoL register.
++ *
++ */
++static int pfe_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++
++ if (wol->wolopts & ~(WAKE_MAGIC | WAKE_ARP | WAKE_MCAST | WAKE_UCAST))
++ return -EOPNOTSUPP;
++
++ priv->wol = 0;
++
++ if (wol->wolopts & WAKE_MAGIC)
++ priv->wol |= EMAC_WOL_MAGIC;
++ if (wol->wolopts & WAKE_ARP)
++ priv->wol |= EMAC_WOL_ARP;
++ if (wol->wolopts & WAKE_MCAST)
++ priv->wol |= EMAC_WOL_MULTI;
++ if (wol->wolopts & WAKE_UCAST)
++ priv->wol |= EMAC_WOL_SPEC_ADDR;
++
++ pfe_eth_set_device_wakeup(priv->pfe);
++
++ return 0;
++}
++
++/**
++ *
++ * pfe_eth_get_wol - Get the WoL options.
++ *
++ */
++static void pfe_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++
++ wol->supported = (WAKE_MAGIC | WAKE_ARP | WAKE_MCAST | WAKE_UCAST);
++ wol->wolopts = 0;
++
++ if(priv->wol & EMAC_WOL_MAGIC)
++ wol->wolopts |= WAKE_MAGIC;
++ if(priv->wol & EMAC_WOL_ARP)
++ wol->wolopts |= WAKE_ARP;
++ if(priv->wol & EMAC_WOL_MULTI)
++ wol->wolopts |= WAKE_UCAST;
++ if(priv->wol & EMAC_WOL_SPEC_ADDR)
++ wol->wolopts |= WAKE_UCAST;
++
++ memset(&wol->sopass, 0, sizeof(wol->sopass));
++}
++#endif
++/**
++ * pfe_eth_gemac_reglen - Return the length of the register structure.
++ *
++ */
++static int pfe_eth_gemac_reglen(struct net_device *dev)
++{
++ return (sizeof (gemac_regs)/ sizeof(u32)) + (( MAX_UC_SPEC_ADDR_REG - 3 ) * 2);
++}
++
++/**
++ * pfe_eth_gemac_get_regs - Return the gemac register structure.
++ *
++ */
++static void pfe_eth_gemac_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
++{
++ int i,j;
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ u32 *buf = (u32 *) regbuf;
++
++ for (i = 0; i < sizeof (gemac_regs) / sizeof (u32); i++)
++ buf[i] = readl( priv->EMAC_baseaddr + gemac_regs[i] );
++
++ for (j = 0; j < (( MAX_UC_SPEC_ADDR_REG - 3 ) * 2); j++,i++)
++ buf[i] = readl( priv->EMAC_baseaddr + EMAC_SPEC5_ADD_BOT + (j<<2) );
++
++}
++
++
++#else //if defined(CONFIG_PLATFORM_C2000)
++/*MTIP GEMAC */
++static const struct fec_stat {
++ char name[ETH_GSTRING_LEN];
++ u16 offset;
++} fec_stats[] = {
++ /* RMON TX */
++ { "tx_dropped", RMON_T_DROP },
++ { "tx_packets", RMON_T_PACKETS },
++ { "tx_broadcast", RMON_T_BC_PKT },
++ { "tx_multicast", RMON_T_MC_PKT },
++ { "tx_crc_errors", RMON_T_CRC_ALIGN },
++ { "tx_undersize", RMON_T_UNDERSIZE },
++ { "tx_oversize", RMON_T_OVERSIZE },
++ { "tx_fragment", RMON_T_FRAG },
++ { "tx_jabber", RMON_T_JAB },
++ { "tx_collision", RMON_T_COL },
++ { "tx_64byte", RMON_T_P64 },
++ { "tx_65to127byte", RMON_T_P65TO127 },
++ { "tx_128to255byte", RMON_T_P128TO255 },
++ { "tx_256to511byte", RMON_T_P256TO511 },
++ { "tx_512to1023byte", RMON_T_P512TO1023 },
++ { "tx_1024to2047byte", RMON_T_P1024TO2047 },
++ { "tx_GTE2048byte", RMON_T_P_GTE2048 },
++ { "tx_octets", RMON_T_OCTETS },
++
++ /* IEEE TX */
++ { "IEEE_tx_drop", IEEE_T_DROP },
++ { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
++ { "IEEE_tx_1col", IEEE_T_1COL },
++ { "IEEE_tx_mcol", IEEE_T_MCOL },
++ { "IEEE_tx_def", IEEE_T_DEF },
++ { "IEEE_tx_lcol", IEEE_T_LCOL },
++ { "IEEE_tx_excol", IEEE_T_EXCOL },
++ { "IEEE_tx_macerr", IEEE_T_MACERR },
++ { "IEEE_tx_cserr", IEEE_T_CSERR },
++ { "IEEE_tx_sqe", IEEE_T_SQE },
++ { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
++ { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
++
++ /* RMON RX */
++ { "rx_packets", RMON_R_PACKETS },
++ { "rx_broadcast", RMON_R_BC_PKT },
++ { "rx_multicast", RMON_R_MC_PKT },
++ { "rx_crc_errors", RMON_R_CRC_ALIGN },
++ { "rx_undersize", RMON_R_UNDERSIZE },
++ { "rx_oversize", RMON_R_OVERSIZE },
++ { "rx_fragment", RMON_R_FRAG },
++ { "rx_jabber", RMON_R_JAB },
++ { "rx_64byte", RMON_R_P64 },
++ { "rx_65to127byte", RMON_R_P65TO127 },
++ { "rx_128to255byte", RMON_R_P128TO255 },
++ { "rx_256to511byte", RMON_R_P256TO511 },
++ { "rx_512to1023byte", RMON_R_P512TO1023 },
++ { "rx_1024to2047byte", RMON_R_P1024TO2047 },
++ { "rx_GTE2048byte", RMON_R_P_GTE2048 },
++ { "rx_octets", RMON_R_OCTETS },
++
++ /* IEEE RX */
++ { "IEEE_rx_drop", IEEE_R_DROP },
++ { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
++ { "IEEE_rx_crc", IEEE_R_CRC },
++ { "IEEE_rx_align", IEEE_R_ALIGN },
++ { "IEEE_rx_macerr", IEEE_R_MACERR },
++ { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
++ { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
++};
++
++static void pfe_eth_fill_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
++ data[i] = readl(priv->EMAC_baseaddr + fec_stats[i].offset);
++}
++
++static void pfe_eth_gstrings(struct net_device *netdev,
++ u32 stringset, u8 *data)
++{
++ int i;
++ switch (stringset) {
++ case ETH_SS_STATS:
++ for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
++ memcpy(data + i * ETH_GSTRING_LEN,
++ fec_stats[i].name, ETH_GSTRING_LEN);
++ break;
++ }
++}
++
++static int pfe_eth_stats_count(struct net_device *dev, int sset)
++{
++ switch (sset) {
++ case ETH_SS_STATS:
++ return ARRAY_SIZE(fec_stats);
++ default:
++ return -EOPNOTSUPP;
++ }
++}
++
++/**
++ * pfe_eth_gemac_reglen - Return the length of the register structure.
++ *
++ */
++static int pfe_eth_gemac_reglen(struct net_device *dev)
++{
++ printk("%s() \n", __func__);
++ return (sizeof (gemac_regs)/ sizeof(u32)) ;
++}
++
++/**
++ * pfe_eth_gemac_get_regs - Return the gemac register structure.
++ *
++ */
++static void pfe_eth_gemac_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
++{
++ int i;
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ u32 *buf = (u32 *) regbuf;
++
++ printk("%s() \n", __func__);
++ for (i = 0; i < sizeof (gemac_regs) / sizeof (u32); i++)
++ buf[i] = readl( priv->EMAC_baseaddr + gemac_regs[i] );
++
++}
++
++
++#endif
++
++/**
++ * pfe_eth_get_drvinfo - Fills in the drvinfo structure with some basic info
++ *
++ */
++static void pfe_eth_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
++{
++ strncpy(drvinfo->driver, DRV_NAME, COMCERTO_INFOSTR_LEN);
++ strncpy(drvinfo->version, comcerto_eth_driver_version, COMCERTO_INFOSTR_LEN);
++ strncpy(drvinfo->fw_version, "N/A", COMCERTO_INFOSTR_LEN);
++ strncpy(drvinfo->bus_info, "N/A", COMCERTO_INFOSTR_LEN);
++ drvinfo->testinfo_len = 0;
++ drvinfo->regdump_len = 0;
++ drvinfo->eedump_len = 0;
++}
++
++/**
++ * pfe_eth_set_settings - Used to send commands to PHY.
++ *
++ */
++
++static int pfe_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ struct phy_device *phydev = priv->phydev;
++
++ if (NULL == phydev)
++ return -ENODEV;
++
++ return phy_ethtool_sset(phydev, cmd);
++}
++
++
++/**
++ * pfe_eth_getsettings - Return the current settings in the ethtool_cmd structure.
++ *
++ */
++static int pfe_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ struct phy_device *phydev = priv->phydev;
++
++ if (NULL == phydev)
++ return -ENODEV;
++
++ return phy_ethtool_gset(phydev, cmd);
++}
++
++
++/**
++ * pfe_eth_get_msglevel - Gets the debug message mask.
++ *
++ */
++static uint32_t pfe_eth_get_msglevel(struct net_device *dev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++
++ return priv->msg_enable;
++}
++
++/**
++ * pfe_eth_set_msglevel - Sets the debug message mask.
++ *
++ */
++static void pfe_eth_set_msglevel(struct net_device *dev, uint32_t data)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++
++ priv->msg_enable = data;
++}
++
++#define HIF_RX_COAL_MAX_CLKS (~(1<<31))
++#define HIF_RX_COAL_CLKS_PER_USEC (pfe->ctrl.sys_clk/1000)
++#define HIF_RX_COAL_MAX_USECS (HIF_RX_COAL_MAX_CLKS/HIF_RX_COAL_CLKS_PER_USEC)
++
++/**
++ * pfe_eth_set_coalesce - Sets rx interrupt coalescing timer.
++ *
++ */
++static int pfe_eth_set_coalesce(struct net_device *dev,
++ struct ethtool_coalesce *ec)
++{
++ if (ec->rx_coalesce_usecs > HIF_RX_COAL_MAX_USECS)
++ return -EINVAL;
++
++ if (!ec->rx_coalesce_usecs) {
++ writel(0, HIF_INT_COAL);
++ return 0;
++ }
++
++ writel((ec->rx_coalesce_usecs * HIF_RX_COAL_CLKS_PER_USEC) | HIF_INT_COAL_ENABLE, HIF_INT_COAL);
++
++ return 0;
++}
++
++/**
++ * pfe_eth_get_coalesce - Gets rx interrupt coalescing timer value.
++ *
++ */
++static int pfe_eth_get_coalesce(struct net_device *dev,
++ struct ethtool_coalesce *ec)
++{
++ int reg_val = readl(HIF_INT_COAL);
++
++ if (reg_val & HIF_INT_COAL_ENABLE)
++ ec->rx_coalesce_usecs = (reg_val & HIF_RX_COAL_MAX_CLKS) / HIF_RX_COAL_CLKS_PER_USEC;
++ else
++ ec->rx_coalesce_usecs = 0;
++
++ return 0;
++}
++
++#if defined(CONFIG_PLATFORM_C2000)
++/**
++ * pfe_eth_pause_rx_enabled - Tests if pause rx is enabled on GEM
++ *
++ */
++static int pfe_eth_pause_rx_enabled(struct pfe_eth_priv_s *priv)
++{
++ return (readl(priv->EMAC_baseaddr + EMAC_NETWORK_CONFIG) & EMAC_ENABLE_PAUSE_RX) != 0;
++}
++
++/**
++ * pfe_eth_set_pauseparam - Sets pause parameters
++ *
++ */
++static int pfe_eth_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++
++ if (epause->rx_pause)
++ {
++ gemac_enable_pause_rx(priv->EMAC_baseaddr);
++ if (priv->phydev)
++ priv->phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
++ }
++ else
++ {
++ gemac_disable_pause_rx(priv->EMAC_baseaddr);
++ if (priv->phydev)
++ priv->phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
++ }
++
++ return 0;
++}
++
++/**
++ * pfe_eth_get_pauseparam - Gets pause parameters
++ *
++ */
++static void pfe_eth_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++
++ epause->autoneg = 0;
++ epause->tx_pause = 0;
++ epause->rx_pause = pfe_eth_pause_rx_enabled(priv);
++}
++
++/** pfe_eth_get_hash
++ */
++static int pfe_eth_get_hash(u8 * addr)
++{
++ u8 temp1,temp2,temp3,temp4,temp5,temp6,temp7,temp8;
++ temp1 = addr[0] & 0x3F ;
++ temp2 = ((addr[0] & 0xC0) >> 6)| ((addr[1] & 0x0F) << 2);
++ temp3 = ((addr[1] & 0xF0) >> 4) | ((addr[2] & 0x03) << 4);
++ temp4 = (addr[2] & 0xFC) >> 2;
++ temp5 = addr[3] & 0x3F;
++ temp6 = ((addr[3] & 0xC0) >> 6) | ((addr[4] & 0x0F) << 2);
++ temp7 = ((addr[4] & 0xF0) >>4 ) | ((addr[5] & 0x03) << 4);
++ temp8 = ((addr[5] &0xFC) >> 2);
++ return (temp1 ^ temp2 ^ temp3 ^ temp4 ^ temp5 ^ temp6 ^ temp7 ^ temp8);
++}
++
++#else
++ /*TODO Add pause frame support for LS1012A */
++
++/** pfe_eth_get_hash
++ */
++#define HASH_BITS 6 /* #bits in hash */
++#define CRC32_POLY 0xEDB88320
++
++static int pfe_eth_get_hash(u8 * addr)
++{
++ unsigned int i, bit, data, crc, hash;
++
++ /* calculate crc32 value of mac address */
++ crc = 0xffffffff;
++
++ for (i = 0; i < 6; i++) {
++ data = addr[i];
++ for (bit = 0; bit < 8; bit++, data >>= 1) {
++ crc = (crc >> 1) ^
++ (((crc ^ data) & 1) ? CRC32_POLY : 0);
++ }
++ }
++
++ /* only upper 6 bits (HASH_BITS) are used
++ * which point to specific bit in he hash registers
++ */
++ hash = (crc >> (32 - HASH_BITS)) & 0x3f;
++
++ return hash;
++}
++
++#endif
++
++struct ethtool_ops pfe_ethtool_ops = {
++ .get_settings = pfe_eth_get_settings,
++ .set_settings = pfe_eth_set_settings,
++ .get_drvinfo = pfe_eth_get_drvinfo,
++ .get_regs_len = pfe_eth_gemac_reglen,
++ .get_regs = pfe_eth_gemac_get_regs,
++ .get_link = ethtool_op_get_link,
++#if defined(CONFIG_PLATFORM_C2000)
++ .get_wol = pfe_eth_get_wol,
++ .set_wol = pfe_eth_set_wol,
++ .set_pauseparam = pfe_eth_set_pauseparam,
++ .get_pauseparam = pfe_eth_get_pauseparam,
++#endif
++ .get_strings = pfe_eth_gstrings,
++ .get_sset_count = pfe_eth_stats_count,
++ .get_ethtool_stats = pfe_eth_fill_stats,
++ .get_msglevel = pfe_eth_get_msglevel,
++ .set_msglevel = pfe_eth_set_msglevel,
++ .set_coalesce = pfe_eth_set_coalesce,
++ .get_coalesce = pfe_eth_get_coalesce,
++};
++
++
++
++#if defined(CONFIG_PLATFORM_C2000)
++/** pfe_eth_mdio_reset
++ */
++int pfe_eth_mdio_reset(struct mii_bus *bus)
++{
++ struct pfe_eth_priv_s *priv = (struct pfe_eth_priv_s *)bus->priv;
++
++ netif_info(priv, hw, priv->dev, "%s\n", __func__);
++
++#if !defined(CONFIG_PLATFORM_EMULATION)
++ mutex_lock(&bus->mdio_lock);
++
++ /* Setup the MII Mgmt clock speed */
++ if (priv->mii_bus)
++ gemac_set_mdc_div(priv->EMAC_baseaddr, priv->mdc_div);
++
++ /* Reset the management interface */
++ __raw_writel(__raw_readl(priv->EMAC_baseaddr + EMAC_NETWORK_CONTROL) | EMAC_MDIO_EN,
++ priv->EMAC_baseaddr + EMAC_NETWORK_CONTROL);
++
++ /* Wait until the bus is free */
++ while(!(__raw_readl(priv->EMAC_baseaddr + EMAC_NETWORK_STATUS) & EMAC_PHY_IDLE));
++
++ mutex_unlock(&bus->mdio_lock);
++#endif
++
++ return 0;
++}
++
++
++/** pfe_eth_gemac_phy_timeout
++ *
++ */
++static int pfe_eth_gemac_phy_timeout(struct pfe_eth_priv_s *priv, int timeout)
++{
++ while(!(__raw_readl(priv->EMAC_baseaddr + EMAC_NETWORK_STATUS) & EMAC_PHY_IDLE)) {
++
++ if (timeout-- <= 0) {
++ return -1;
++ }
++
++ udelay(10);
++ }
++
++ return 0;
++}
++
++
++/** pfe_eth_mdio_write
++ */
++static int pfe_eth_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
++{
++ struct pfe_eth_priv_s *priv = (struct pfe_eth_priv_s *)bus->priv;
++ u32 write_data;
++
++#if !defined(CONFIG_PLATFORM_EMULATION)
++
++ netif_info(priv, hw, priv->dev, "%s: phy %d\n", __func__, mii_id);
++
++// netif_info(priv, hw, priv->dev, "%s %d %d %x\n", bus->id, mii_id, regnum, value);
++
++ write_data = 0x50020000;
++ write_data |= ((mii_id << 23) | (regnum << 18) | value);
++ __raw_writel(write_data, priv->EMAC_baseaddr + EMAC_PHY_MANAGEMENT);
++
++ if (pfe_eth_gemac_phy_timeout(priv, EMAC_MDIO_TIMEOUT)){
++ netdev_err(priv->dev, "%s: phy MDIO write timeout\n", __func__);
++ return -1;
++ }
++
++#endif
++
++ return 0;
++}
++
++
++/** pfe_eth_mdio_read
++ */
++static int pfe_eth_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
++{
++ struct pfe_eth_priv_s *priv = (struct pfe_eth_priv_s *)bus->priv;
++ u16 value = 0;
++ u32 write_data;
++
++#if !defined(CONFIG_PLATFORM_EMULATION)
++ netif_info(priv, hw, priv->dev, "%s: phy %d\n", __func__, mii_id);
++
++ write_data = 0x60020000;
++ write_data |= ((mii_id << 23) | (regnum << 18));
++
++ __raw_writel(write_data, priv->EMAC_baseaddr + EMAC_PHY_MANAGEMENT);
++
++ if (pfe_eth_gemac_phy_timeout( priv, EMAC_MDIO_TIMEOUT)) {
++ netdev_err(priv->dev, "%s: phy MDIO read timeout\n", __func__);
++ return -1;
++ }
++
++ value = __raw_readl(priv->EMAC_baseaddr + EMAC_PHY_MANAGEMENT) & 0xFFFF;
++#endif
++
++// netif_info(priv, hw, priv->dev, "%s %d %d %x\n", bus->id, mii_id, regnum, value);
++
++ return value;
++}
++
++#else
++/** pfe_eth_mdio_reset
++ */
++int pfe_eth_mdio_reset(struct mii_bus *bus)
++{
++ struct pfe_eth_priv_s *priv = (struct pfe_eth_priv_s *)bus->priv;
++ u32 phy_speed, pclk = 250000000; /*TODO this needs to be checked read from the correct source*/
++
++ netif_info(priv, hw, priv->dev, "%s\n", __func__);
++
++ mutex_lock(&bus->mdio_lock);
++
++ /*
++ * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
++ *
++ * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
++ * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'.
++ */
++ phy_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT);
++ phy_speed |= EMAC_HOLDTIME(0x5);
++ __raw_writel(phy_speed, priv->PHY_baseaddr + EMAC_MII_CTRL_REG);
++
++ mutex_unlock(&bus->mdio_lock);
++
++ return 0;
++}
++
++/** pfe_eth_gemac_phy_timeout
++ *
++ */
++static int pfe_eth_gemac_phy_timeout(struct pfe_eth_priv_s *priv, int timeout)
++{
++ while(!(__raw_readl(priv->PHY_baseaddr + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
++
++ if (timeout-- <= 0) {
++ return -1;
++ }
++
++ udelay(10);
++ }
++ __raw_writel(EMAC_IEVENT_MII, priv->PHY_baseaddr + EMAC_IEVENT_REG);
++
++ return 0;
++}
++
++static int pfe_eth_mdio_mux(u8 muxval)
++{
++ struct i2c_adapter *a;
++ struct i2c_msg msg;
++ unsigned char buf[2];
++ int ret;
++
++ a = i2c_get_adapter(0);
++ if (!a)
++ return -ENODEV;
++
++ /* set bit 1 (the second bit) of chip at 0x09, register 0x13 */
++ buf[0] = 0x54; //reg number
++ buf[1] = (muxval << 6)| 0x3; //data
++ msg.addr = 0x66;
++ msg.buf = buf;
++ msg.len = 2;
++ msg.flags = 0;
++ ret = i2c_transfer(a, &msg, 1);
++ i2c_put_adapter(a);
++ if (ret != 1)
++ return -ENODEV;
++ return 0;
++
++
++}
++
++static int pfe_eth_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
++{
++ struct pfe_eth_priv_s *priv = (struct pfe_eth_priv_s *)bus->priv;
++
++ /*FIXME Dirty hack to configure mux */
++ if(priv->mdio_muxval) {
++ if(mii_id == 0x1)
++ pfe_eth_mdio_mux(0x1);
++ else
++ pfe_eth_mdio_mux(0x2);
++ }
++
++ /* start a write op */
++ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR |
++ EMAC_MII_DATA_PA(mii_id) | EMAC_MII_DATA_RA(regnum) |
++ EMAC_MII_DATA_TA | EMAC_MII_DATA(value),
++ priv->PHY_baseaddr + EMAC_MII_DATA_REG);
++
++ if (pfe_eth_gemac_phy_timeout(priv, EMAC_MDIO_TIMEOUT)){
++ netdev_err(priv->dev, "%s: phy MDIO write timeout\n", __func__);
++ return -1;
++ }
++ netif_info(priv, hw, priv->dev, "%s: phy %x reg %x val %x\n", __func__, mii_id, regnum, value);
++
++ return 0;
++
++
++}
++static int pfe_eth_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
++{
++ struct pfe_eth_priv_s *priv = (struct pfe_eth_priv_s *)bus->priv;
++ u16 value = 0;
++
++ /*FIXME Dirty hack to configure mux */
++ if(priv->mdio_muxval){
++ if(mii_id == 0x1)
++ pfe_eth_mdio_mux(0x1);
++ else
++ pfe_eth_mdio_mux(0x2);
++ }
++
++ /* start a read op */
++ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD |
++ EMAC_MII_DATA_PA(mii_id) | EMAC_MII_DATA_RA(regnum) |
++ EMAC_MII_DATA_TA, priv->PHY_baseaddr + EMAC_MII_DATA_REG);
++
++ if (pfe_eth_gemac_phy_timeout( priv, EMAC_MDIO_TIMEOUT)) {
++ netdev_err(priv->dev, "%s: phy MDIO read timeout\n", __func__);
++ return -1;
++ }
++
++ value = EMAC_MII_DATA(__raw_readl(priv->PHY_baseaddr + EMAC_MII_DATA_REG));
++ netif_info(priv, hw, priv->dev, "%s: phy %x reg %x val %x\n", __func__, mii_id, regnum, value);
++ return value;
++}
++#endif
++static int pfe_eth_mdio_init(struct pfe_eth_priv_s *priv, struct comcerto_mdio_platform_data *minfo)
++{
++ struct mii_bus *bus;
++ int rc;
++
++ netif_info(priv, drv, priv->dev, "%s\n", __func__);
++ printk( "%s\n", __func__);
++
++#if !defined(CONFIG_PLATFORM_EMULATION)
++ bus = mdiobus_alloc();
++ if (!bus) {
++ netdev_err(priv->dev, "mdiobus_alloc() failed\n");
++ rc = -ENOMEM;
++ goto err0;
++ }
++
++ bus->name = "Comcerto MDIO Bus";
++ bus->read = &pfe_eth_mdio_read;
++ bus->write = &pfe_eth_mdio_write;
++ bus->reset = &pfe_eth_mdio_reset;
++ snprintf(bus->id, MII_BUS_ID_SIZE, "comcerto-%x", priv->id);
++ bus->priv = priv;
++
++ bus->phy_mask = minfo->phy_mask;
++ priv->mdc_div = minfo->mdc_div;
++
++ if (!priv->mdc_div)
++ priv->mdc_div = 64;
++
++ bus->irq = minfo->irq;
++
++ bus->parent = priv->pfe->dev;
++
++ netif_info(priv, drv, priv->dev, "%s: mdc_div: %d, phy_mask: %x \n", __func__, priv->mdc_div, bus->phy_mask);
++ rc = mdiobus_register(bus);
++ if (rc) {
++ netdev_err(priv->dev, "mdiobus_register(%s) failed\n", bus->name);
++ goto err1;
++ }
++
++ priv->mii_bus = bus;
++ pfe_eth_mdio_reset(bus);
++
++ return 0;
++
++err1:
++ mdiobus_free(bus);
++err0:
++ return rc;
++#else
++ return 0;
++#endif
++
++}
++
++/** pfe_eth_mdio_exit
++ */
++static void pfe_eth_mdio_exit(struct mii_bus *bus)
++{
++ if (!bus)
++ return;
++
++ netif_info((struct pfe_eth_priv_s *)bus->priv, drv, ((struct pfe_eth_priv_s *)(bus->priv))->dev, "%s\n", __func__);
++
++ mdiobus_unregister(bus);
++ mdiobus_free(bus);
++}
++
++#if defined(CONFIG_PLATFORM_C2000)
++/** pfe_get_interface
++ */
++static phy_interface_t pfe_get_interface(struct net_device *dev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ u32 mii_mode = priv->einfo->mii_config;
++
++ netif_info(priv, drv, dev, "%s\n", __func__);
++
++ if (priv->einfo->gemac_mode & (GEMAC_SW_CONF)) {
++ switch (mii_mode) {
++ case CONFIG_COMCERTO_USE_GMII:
++ return PHY_INTERFACE_MODE_GMII;
++ break;
++ case CONFIG_COMCERTO_USE_RGMII:
++ return PHY_INTERFACE_MODE_RGMII;
++ break;
++ case CONFIG_COMCERTO_USE_RMII:
++ return PHY_INTERFACE_MODE_RMII;
++ break;
++ case CONFIG_COMCERTO_USE_SGMII:
++ return PHY_INTERFACE_MODE_SGMII;
++ break;
++
++ default :
++ case CONFIG_COMCERTO_USE_MII:
++ return PHY_INTERFACE_MODE_MII;
++ break;
++
++ }
++ } else {
++ // Bootstrap config read from controller
++ BUG();
++ return 0;
++ }
++}
++#endif
++
++/** pfe_get_phydev_speed
++ */
++static int pfe_get_phydev_speed(struct phy_device *phydev)
++{
++ switch (phydev->speed) {
++ case 10:
++ return SPEED_10M;
++ case 100:
++ return SPEED_100M;
++ case 1000:
++ default:
++ return SPEED_1000M;
++ }
++
++}
++
++/** pfe_set_rgmii_speed
++ */
++#define RGMIIPCR 0x434
++/* RGMIIPCR bit definitions*/
++#define SCFG_RGMIIPCR_EN_AUTO (0x00000008)
++#define SCFG_RGMIIPCR_SETSP_1000M (0x00000004)
++#define SCFG_RGMIIPCR_SETSP_100M (0x00000000)
++#define SCFG_RGMIIPCR_SETSP_10M (0x00000002)
++#define SCFG_RGMIIPCR_SETFD (0x00000001)
++
++static void pfe_set_rgmii_speed(struct phy_device *phydev)
++{
++ u32 rgmii_pcr;
++
++ regmap_read(pfe->scfg, RGMIIPCR, &rgmii_pcr);
++ rgmii_pcr &= ~(SCFG_RGMIIPCR_SETSP_1000M|SCFG_RGMIIPCR_SETSP_10M);
++
++ switch (phydev->speed) {
++ case 10:
++ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M;
++ break;
++ case 1000:
++ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M;
++ break;
++ case 100:
++ default:
++ /* Default is 100M */
++ break;
++ }
++ regmap_write(pfe->scfg, RGMIIPCR, rgmii_pcr);
++
++
++}
++/** pfe_get_phydev_duplex
++ */
++static int pfe_get_phydev_duplex(struct phy_device *phydev)
++{
++ //return ( phydev->duplex == DUPLEX_HALF ) ? DUP_HALF:DUP_FULL ;
++ return DUPLEX_FULL;
++}
++
++/** pfe_eth_adjust_link
++ */
++static void pfe_eth_adjust_link(struct net_device *dev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ unsigned long flags;
++ struct phy_device *phydev = priv->phydev;
++ int new_state = 0;
++
++ netif_info(priv, drv, dev, "%s\n", __func__);
++
++ spin_lock_irqsave(&priv->lock, flags);
++ if (phydev->link) {
++ /* Now we make sure that we can be in full duplex mode.
++ * If not, we operate in half-duplex mode. */
++ if (phydev->duplex != priv->oldduplex) {
++ new_state = 1;
++ gemac_set_duplex(priv->EMAC_baseaddr, pfe_get_phydev_duplex(phydev));
++ priv->oldduplex = phydev->duplex;
++ }
++
++ if (phydev->speed != priv->oldspeed) {
++ new_state = 1;
++ gemac_set_speed(priv->EMAC_baseaddr, pfe_get_phydev_speed(phydev));
++ if(priv->einfo->mii_config == PHY_INTERFACE_MODE_RGMII)
++ pfe_set_rgmii_speed(phydev);
++ priv->oldspeed = phydev->speed;
++ }
++
++ if (!priv->oldlink) {
++ new_state = 1;
++ priv->oldlink = 1;
++ }
++
++ } else if (priv->oldlink) {
++ new_state = 1;
++ priv->oldlink = 0;
++ priv->oldspeed = 0;
++ priv->oldduplex = -1;
++ }
++
++ if (new_state && netif_msg_link(priv))
++ phy_print_status(phydev);
++
++ spin_unlock_irqrestore(&priv->lock, flags);
++}
++
++
++/** pfe_phy_exit
++ */
++static void pfe_phy_exit(struct net_device *dev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++
++ netif_info(priv, drv, dev, "%s\n", __func__);
++
++ phy_disconnect(priv->phydev);
++ priv->phydev = NULL;
++}
++
++/** pfe_eth_stop
++ */
++static void pfe_eth_stop( struct net_device *dev , int wake)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++
++ netif_info(priv, drv, dev, "%s\n", __func__);
++
++ if (wake)
++ gemac_tx_disable(priv->EMAC_baseaddr);
++ else {
++ gemac_disable(priv->EMAC_baseaddr);
++ gpi_disable(priv->GPI_baseaddr);
++
++ if (priv->phydev)
++ phy_stop(priv->phydev);
++ }
++}
++
++/** pfe_eth_start
++ */
++static int pfe_eth_start( struct pfe_eth_priv_s *priv )
++{
++ netif_info(priv, drv, priv->dev, "%s\n", __func__);
++
++ if (priv->phydev)
++ phy_start(priv->phydev);
++
++ gpi_enable(priv->GPI_baseaddr);
++ gemac_enable(priv->EMAC_baseaddr);
++
++ return 0;
++}
++
++/*Configure on chip serdes through mdio
++ * Is there any better way to do this? */
++static void ls1012a_configure_serdes(struct net_device *dev)
++{
++ struct pfe_eth_priv_s *priv = pfe->eth.eth_priv[0]; // FIXME This will not work for EMAC2 as SGMII
++ /*int value,sgmii_2500=0; */
++ struct mii_bus *bus = priv->mii_bus;
++
++ netif_info(priv, drv, dev, "%s\n", __func__);
++ /* PCS configuration done with corresponding GEMAC */
++
++ pfe_eth_mdio_read(bus, 0, 0);
++ pfe_eth_mdio_read(bus, 0, 1);
++#if 1
++ /*These settings taken from validtion team */
++ pfe_eth_mdio_write(bus, 0, 0x0, 0x8000);
++ pfe_eth_mdio_write(bus, 0, 0x14, 0xb);
++ pfe_eth_mdio_write(bus, 0, 0x4, 0x1a1);
++ pfe_eth_mdio_write(bus, 0, 0x12, 0x400);
++ pfe_eth_mdio_write(bus, 0, 0x13, 0x0);
++ pfe_eth_mdio_write(bus, 0, 0x0, 0x1140);
++ return;
++#else
++ /*Reset serdes */
++ pfe_eth_mdio_write(bus, 0, 0x0, 0x8000);
++
++ /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
++ value = PHY_SGMII_IF_MODE_SGMII;
++ if (!sgmii_2500)
++ value |= PHY_SGMII_IF_MODE_AN;
++
++ pfe_eth_mdio_write(bus, 0, 0x14, value);
++
++ /* Dev ability according to SGMII specification */
++ value = PHY_SGMII_DEV_ABILITY_SGMII;
++ pfe_eth_mdio_write(bus, 0, 0x4, value);
++
++ //These values taken from validation team
++ pfe_eth_mdio_write(bus, 0, 0x13, 0x0);
++ pfe_eth_mdio_write(bus, 0, 0x12, 0x400);
++
++ /* Restart AN */
++ value = PHY_SGMII_CR_DEF_VAL;
++ if (!sgmii_2500)
++ value |= PHY_SGMII_CR_RESET_AN;
++ pfe_eth_mdio_write(bus, 0, 0, value);
++
++#endif
++}
++
++/** pfe_phy_init
++ *
++ */
++static int pfe_phy_init(struct net_device *dev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ struct phy_device *phydev;
++ char phy_id[MII_BUS_ID_SIZE + 3];
++ char bus_id[MII_BUS_ID_SIZE];
++ phy_interface_t interface;
++
++ priv->oldlink = 0;
++ priv->oldspeed = 0;
++ priv->oldduplex = -1;
++
++ snprintf(bus_id, MII_BUS_ID_SIZE, "comcerto-%d", 0);
++ snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, priv->einfo->phy_id);
++
++ netif_info(priv, drv, dev, "%s: %s\n", __func__, phy_id);
++#if defined(CONFIG_PLATFORM_C2000)
++ interface = pfe_get_interface(dev);
++#else
++ interface = priv->einfo->mii_config;
++ if(interface == PHY_INTERFACE_MODE_SGMII) {
++ /*Configure SGMII PCS */
++ if(pfe->scfg) {
++ /*Config MDIO from serdes */
++ regmap_write(pfe->scfg, 0x484, 0x00000000);
++ }
++ ls1012a_configure_serdes(dev);
++ }
++
++ if(pfe->scfg) {
++ /*Config MDIO from PAD */
++ regmap_write(pfe->scfg, 0x484, 0x80000000);
++ }
++#endif
++
++
++ priv->oldlink = 0;
++ priv->oldspeed = 0;
++ priv->oldduplex = -1;
++
++ printk("%s interface %x \n", __func__, interface);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0)
++ phydev = phy_connect(dev, phy_id, &pfe_eth_adjust_link, interface);
++#else
++ phydev = phy_connect(dev, phy_id, &pfe_eth_adjust_link, 0, interface);
++#endif
++
++ if (IS_ERR(phydev)) {
++ netdev_err(dev, "phy_connect() failed\n");
++ return PTR_ERR(phydev);
++ }
++
++ priv->phydev = phydev;
++ phydev->irq = PHY_POLL;
++
++#if defined(CONFIG_PLATFORM_C2000)
++ /* Pause frame support */
++ phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
++ if (pfe_eth_pause_rx_enabled(priv))
++ phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
++ else
++ phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
++#else
++ /*TODO Add pause frame support for LS1012A */
++#endif
++
++ return 0;
++}
++
++/** pfe_gemac_init
++ */
++static int pfe_gemac_init(struct pfe_eth_priv_s *priv)
++{
++ GEMAC_CFG cfg;
++
++ netif_info(priv, ifup, priv->dev, "%s\n", __func__);
++
++ /* software config */
++ /* MII interface mode selection */
++ switch (priv->einfo->mii_config) {
++ case CONFIG_COMCERTO_USE_GMII:
++ cfg.mode = GMII;
++ break;
++
++ case CONFIG_COMCERTO_USE_MII:
++ cfg.mode = MII;
++ break;
++
++ case CONFIG_COMCERTO_USE_RGMII:
++ cfg.mode = RGMII;
++ break;
++
++ case CONFIG_COMCERTO_USE_RMII:
++ cfg.mode = RMII;
++ break;
++
++ case CONFIG_COMCERTO_USE_SGMII:
++ cfg.mode = SGMII;
++ break;
++
++ default:
++ cfg.mode = RGMII;
++ }
++
++ /* Speed selection */
++ switch (priv->einfo->gemac_mode & GEMAC_SW_SPEED_1G ) {
++ case GEMAC_SW_SPEED_1G:
++ cfg.speed = SPEED_1000M;
++ break;
++
++ case GEMAC_SW_SPEED_100M:
++ cfg.speed = SPEED_100M;
++ break;
++
++ case GEMAC_SW_SPEED_10M:
++ cfg.speed = SPEED_10M;
++ break;
++
++ default:
++ cfg.speed = SPEED_1000M;
++ }
++
++ /* Duplex selection */
++ cfg.duplex = ( priv->einfo->gemac_mode & GEMAC_SW_FULL_DUPLEX ) ? DUPLEX_FULL : DUPLEX_HALF;
++
++ gemac_set_config( priv->EMAC_baseaddr, &cfg);
++ gemac_allow_broadcast( priv->EMAC_baseaddr );
++ gemac_disable_unicast( priv->EMAC_baseaddr );
++ gemac_disable_multicast( priv->EMAC_baseaddr );
++ gemac_disable_fcs_rx( priv->EMAC_baseaddr );
++ gemac_enable_1536_rx( priv->EMAC_baseaddr );
++ gemac_enable_rx_jmb( priv->EMAC_baseaddr );
++ gemac_enable_stacked_vlan( priv->EMAC_baseaddr );
++ gemac_enable_pause_rx( priv->EMAC_baseaddr );
++ gemac_set_bus_width(priv->EMAC_baseaddr, 64);
++ /*TODO just for testing remove it later */
++ gemac_enable_copy_all(priv->EMAC_baseaddr);
++
++ /*GEM will perform checksum verifications*/
++ if (priv->dev->features & NETIF_F_RXCSUM)
++ gemac_enable_rx_checksum_offload(priv->EMAC_baseaddr);
++ else
++ gemac_disable_rx_checksum_offload(priv->EMAC_baseaddr);
++
++ return 0;
++}
++
++/** pfe_eth_event_handler
++ */
++static int pfe_eth_event_handler(void *data, int event, int qno)
++{
++ struct pfe_eth_priv_s *priv = data;
++
++ switch (event) {
++ case EVENT_RX_PKT_IND:
++
++ if (qno == 0) {
++ if (napi_schedule_prep(&priv->high_napi)) {
++ netif_info(priv, intr, priv->dev, "%s: schedule high prio poll\n", __func__);
++
++#ifdef PFE_ETH_NAPI_STATS
++ priv->napi_counters[NAPI_SCHED_COUNT]++;
++#endif
++
++ __napi_schedule(&priv->high_napi);
++ }
++ }
++ else if (qno == 1) {
++ if (napi_schedule_prep(&priv->low_napi)) {
++ netif_info(priv, intr, priv->dev, "%s: schedule low prio poll\n", __func__);
++
++#ifdef PFE_ETH_NAPI_STATS
++ priv->napi_counters[NAPI_SCHED_COUNT]++;
++#endif
++ __napi_schedule(&priv->low_napi);
++ }
++ }
++ else if (qno == 2) {
++ if (napi_schedule_prep(&priv->lro_napi)) {
++ netif_info(priv, intr, priv->dev, "%s: schedule lro prio poll\n", __func__);
++
++#ifdef PFE_ETH_NAPI_STATS
++ priv->napi_counters[NAPI_SCHED_COUNT]++;
++#endif
++ __napi_schedule(&priv->lro_napi);
++ }
++ }
++
++ break;
++
++ case EVENT_TXDONE_IND:
++ case EVENT_HIGH_RX_WM:
++ default:
++ break;
++ }
++
++ return 0;
++}
++
++/** pfe_eth_open
++ */
++static int pfe_eth_open(struct net_device *dev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ struct hif_client_s *client;
++ int rc;
++
++ netif_info(priv, ifup, dev, "%s\n", __func__);
++
++ /* Register client driver with HIF */
++ client = &priv->client;
++ memset(client, 0, sizeof(*client));
++ client->id = PFE_CL_GEM0 + priv->id;
++ client->tx_qn = emac_txq_cnt;
++ client->rx_qn = EMAC_RXQ_CNT;
++ client->priv = priv;
++ client->pfe = priv->pfe;
++ client->event_handler = pfe_eth_event_handler;
++
++ /* FIXME : For now hif lib sets all tx and rx queues to same size */
++ client->tx_qsize = EMAC_TXQ_DEPTH;
++ client->rx_qsize = EMAC_RXQ_DEPTH;
++
++ if ((rc = hif_lib_client_register(client))) {
++ netdev_err(dev, "%s: hif_lib_client_register(%d) failed\n", __func__, client->id);
++ goto err0;
++ }
++
++ netif_info(priv, drv, dev, "%s: registered client: %p\n", __func__, client);
++
++#if defined(CONFIG_PLATFORM_C2000)
++ /* Enable gemac tx clock */
++ clk_enable(priv->gemtx_clk);
++#endif
++
++ pfe_gemac_init(priv);
++
++ if (!is_valid_ether_addr(dev->dev_addr)) {
++ netdev_err(dev, "%s: invalid MAC address\n", __func__);
++ rc = -EADDRNOTAVAIL;
++ goto err1;
++ }
++
++ gemac_set_laddrN( priv->EMAC_baseaddr, ( MAC_ADDR *)dev->dev_addr, 1 );
++
++ napi_enable(&priv->high_napi);
++ napi_enable(&priv->low_napi);
++ napi_enable(&priv->lro_napi);
++
++ rc = pfe_eth_start(priv);
++
++ netif_tx_wake_all_queues(dev);
++
++ //pfe_ctrl_set_eth_state(priv->id, 1, dev->dev_addr);
++
++ priv->tx_timer.expires = jiffies + ( COMCERTO_TX_RECOVERY_TIMEOUT_MS * HZ )/1000;
++ add_timer(&priv->tx_timer);
++
++ return rc;
++
++err1:
++ hif_lib_client_unregister(&priv->client);
++#if defined(CONFIG_PLATFORM_C2000)
++ clk_disable(priv->gemtx_clk);
++#endif
++
++err0:
++ return rc;
++}
++/*
++ * pfe_eth_shutdown
++ */
++int pfe_eth_shutdown( struct net_device *dev, int wake)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ int i, qstatus;
++ unsigned long next_poll = jiffies + 1, end = jiffies + (TX_POLL_TIMEOUT_MS * HZ) / 1000;
++ int tx_pkts, prv_tx_pkts;
++
++ netif_info(priv, ifdown, dev, "%s\n", __func__);
++
++ del_timer_sync(&priv->tx_timer);
++
++ for(i = 0; i < emac_txq_cnt; i++)
++ hrtimer_cancel(&priv->fast_tx_timeout[i].timer);
++
++ netif_tx_stop_all_queues(dev);
++
++ do {
++ tx_pkts = 0;
++ pfe_eth_flush_tx(priv, 1);
++
++ for (i = 0; i < emac_txq_cnt; i++)
++ tx_pkts += hif_lib_tx_pending(&priv->client, i);
++
++ if (tx_pkts) {
++ /*Don't wait forever, break if we cross max timeout */
++ if (time_after(jiffies, end)) {
++ printk(KERN_ERR "(%s)Tx is not complete after %dmsec\n", dev->name, TX_POLL_TIMEOUT_MS);
++ break;
++ }
++
++ printk("%s : (%s) Waiting for tx packets to free. Pending tx pkts = %d.\n", __func__, dev->name, tx_pkts);
++ if (need_resched())
++ schedule();
++ }
++
++ } while(tx_pkts);
++
++ end = jiffies + (TX_POLL_TIMEOUT_MS * HZ) / 1000;
++ /*Disable transmit in PFE before disabling GEMAC */
++ //pfe_ctrl_set_eth_state(priv->id, 0, NULL);
++
++ prv_tx_pkts = tmu_pkts_processed(priv->id);
++ /*Wait till TMU transmits all pending packets
++ * poll tmu_qstatus and pkts processed by TMU for every 10ms
++ * Consider TMU is busy, If we see TMU qeueu pending or any packets processed by TMU
++ */
++ while(1) {
++
++ if (time_after(jiffies, next_poll)) {
++
++ tx_pkts = tmu_pkts_processed(priv->id);
++ qstatus = tmu_qstatus(priv->id) & 0x7ffff;
++
++ if(!qstatus && (tx_pkts == prv_tx_pkts)) {
++ break;
++ }
++ /*Don't wait forever, break if we cross max timeout(TX_POLL_TIMEOUT_MS) */
++ if (time_after(jiffies, end)) {
++ printk(KERN_ERR "TMU%d is busy after %dmsec\n", priv->id, TX_POLL_TIMEOUT_MS);
++ break;
++ }
++ prv_tx_pkts = tx_pkts;
++ next_poll++;
++ }
++ if (need_resched())
++ schedule();
++
++
++ }
++ /* Wait for some more time to complete transmitting packet if any */
++ next_poll = jiffies + 1;
++ while(1) {
++ if (time_after(jiffies, next_poll))
++ break;
++ if (need_resched())
++ schedule();
++ }
++
++ pfe_eth_stop(dev, wake);
++
++ napi_disable(&priv->lro_napi);
++ napi_disable(&priv->low_napi);
++ napi_disable(&priv->high_napi);
++
++#if defined(CONFIG_PLATFORM_C2000)
++ /* Disable gemac tx clock */
++ clk_disable(priv->gemtx_clk);
++#endif
++
++ hif_lib_client_unregister(&priv->client);
++
++ return 0;
++}
++
++/* pfe_eth_close
++ *
++ */
++static int pfe_eth_close( struct net_device *dev )
++{
++ pfe_eth_shutdown(dev, 0);
++
++ return 0;
++}
++
++/* pfe_eth_suspend
++ *
++ * return value : 1 if netdevice is configured to wakeup system
++ * 0 otherwise
++ */
++int pfe_eth_suspend(struct net_device *dev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ int retval = 0;
++
++ if (priv->wol) {
++ gemac_set_wol(priv->EMAC_baseaddr, priv->wol);
++ retval = 1;
++ }
++ pfe_eth_shutdown(dev, priv->wol);
++
++ return retval;
++}
++
++/** pfe_eth_resume
++ *
++ */
++int pfe_eth_resume(struct net_device *dev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++
++ if (priv->wol)
++ gemac_set_wol(priv->EMAC_baseaddr, 0);
++
++ return pfe_eth_open(dev);
++}
++
++#if defined(CONFIG_PLATFORM_C2000)
++/** pfe_eth_set_device_wakeup
++ *
++ * Called when a netdevice changes its wol status.
++ * Scans state of all interfaces and updae PFE device
++ * wakeable state
++ */
++static void pfe_eth_set_device_wakeup(struct pfe *pfe)
++{
++ int i;
++ int wake = 0;
++
++ for(i = 0; i < NUM_GEMAC_SUPPORT; i++)
++ wake |= pfe->eth.eth_priv[i]->wol;
++
++ device_set_wakeup_enable(pfe->dev, wake);
++ //TODO Find correct IRQ mapping.
++ //TODO interface with PMU
++ //int irq_set_irq_wake(unsigned int irq, unsigned int on)
++}
++#endif
++/** pfe_eth_get_queuenum
++ *
++ */
++static int pfe_eth_get_queuenum( struct pfe_eth_priv_s *priv, struct sk_buff *skb )
++{
++ int queuenum = 0;
++ unsigned long flags;
++
++ /* Get the Fast Path queue number */
++ /* Use conntrack mark (if conntrack exists), then packet mark (if any), then fallback to default */
++#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK)
++ if (skb->nfct) {
++ enum ip_conntrack_info cinfo;
++ struct nf_conn *ct;
++ ct = nf_ct_get(skb, &cinfo);
++
++ if (ct) {
++ u_int32_t connmark;
++ connmark = ct->mark;
++
++ if ((connmark & 0x80000000) && priv->id != 0)
++ connmark >>= 16;
++
++ queuenum = connmark & EMAC_QUEUENUM_MASK;
++ }
++ }
++ else /* continued after #endif ... */
++#endif
++ if (skb->mark)
++ queuenum = skb->mark & EMAC_QUEUENUM_MASK;
++ else {
++ spin_lock_irqsave(&priv->lock, flags);
++ queuenum = priv->default_priority & EMAC_QUEUENUM_MASK;
++ spin_unlock_irqrestore(&priv->lock, flags);
++ }
++
++ return queuenum;
++}
++
++
++
++/** pfe_eth_might_stop_tx
++ *
++ */
++static int pfe_eth_might_stop_tx(struct pfe_eth_priv_s *priv, int queuenum, struct netdev_queue *tx_queue, unsigned int n_desc, unsigned int n_segs)
++{
++ int tried = 0;
++ ktime_t kt;
++
++try_again:
++ if (unlikely((__hif_tx_avail(&pfe->hif) < n_desc)
++ || (hif_lib_tx_avail(&priv->client, queuenum) < n_desc)
++ || (hif_lib_tx_credit_avail(pfe, priv->id, queuenum) < n_segs))) {
++
++ if (!tried) {
++ hif_tx_unlock(&pfe->hif);
++ pfe_eth_flush_txQ(priv, queuenum, 1, n_desc);
++ hif_lib_update_credit(&priv->client, queuenum);
++ tried = 1;
++ hif_tx_lock(&pfe->hif);
++ goto try_again;
++ }
++#ifdef PFE_ETH_TX_STATS
++ if (__hif_tx_avail(&pfe->hif) < n_desc)
++ priv->stop_queue_hif[queuenum]++;
++ else if (hif_lib_tx_avail(&priv->client, queuenum) < n_desc) {
++ priv->stop_queue_hif_client[queuenum]++;
++ }
++ else if (hif_lib_tx_credit_avail(pfe, priv->id, queuenum) < n_segs) {
++ priv->stop_queue_credit[queuenum]++;
++ }
++ priv->stop_queue_total[queuenum]++;
++#endif
++ netif_tx_stop_queue(tx_queue);
++
++ kt = ktime_set(0, COMCERTO_TX_FAST_RECOVERY_TIMEOUT_MS * NSEC_PER_MSEC);
++ hrtimer_start(&priv->fast_tx_timeout[queuenum].timer, kt, HRTIMER_MODE_REL);
++ return -1;
++ }
++ else {
++ return 0;
++ }
++}
++
++#define SA_MAX_OP 2
++/** pfe_hif_send_packet
++ *
++ * At this level if TX fails we drop the packet
++ */
++static void pfe_hif_send_packet( struct sk_buff *skb, struct pfe_eth_priv_s *priv, int queuenum)
++{
++ struct skb_shared_info *sh = skb_shinfo(skb);
++ unsigned int nr_frags;
++ u32 ctrl = 0;
++
++ netif_info(priv, tx_queued, priv->dev, "%s\n", __func__);
++
++ if (skb_is_gso(skb)) {
++ priv->stats.tx_dropped++;
++ return;
++ }
++
++ if (skb->ip_summed == CHECKSUM_PARTIAL) {
++ if (skb->len > 1522) {
++ skb->ip_summed = 0;
++ ctrl = 0;
++
++ if (pfe_compute_csum(skb)){
++ kfree_skb(skb);
++ return;
++ }
++ }
++ else
++ ctrl = HIF_CTRL_TX_CHECKSUM;
++ }
++
++ nr_frags = sh->nr_frags;
++
++ if (nr_frags) {
++ skb_frag_t *f;
++ int i;
++
++ __hif_lib_xmit_pkt(&priv->client, queuenum, skb->data, skb_headlen(skb), ctrl, HIF_FIRST_BUFFER, skb);
++
++ for (i = 0; i < nr_frags - 1; i++) {
++ f = &sh->frags[i];
++ __hif_lib_xmit_pkt(&priv->client, queuenum, skb_frag_address(f), skb_frag_size(f), 0x0, 0x0, skb);
++ }
++
++ f = &sh->frags[i];
++
++ __hif_lib_xmit_pkt(&priv->client, queuenum, skb_frag_address(f), skb_frag_size(f), 0x0, HIF_LAST_BUFFER|HIF_DATA_VALID, skb);
++
++ netif_info(priv, tx_queued, priv->dev, "%s: pkt sent successfully skb:%p nr_frags:%d len:%d\n", __func__, skb, nr_frags, skb->len);
++ }
++ else {
++ __hif_lib_xmit_pkt(&priv->client, queuenum, skb->data, skb->len, ctrl, HIF_FIRST_BUFFER | HIF_LAST_BUFFER | HIF_DATA_VALID, skb);
++ netif_info(priv, tx_queued, priv->dev, "%s: pkt sent successfully skb:%p len:%d\n", __func__, skb, skb->len);
++ }
++ hif_tx_dma_start();
++ priv->stats.tx_packets++;
++ priv->stats.tx_bytes += skb->len;
++ hif_lib_tx_credit_use(pfe, priv->id, queuenum, 1);
++}
++
++/** pfe_eth_flush_txQ
++ */
++static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int txQ_num, int from_tx, int n_desc)
++{
++ struct sk_buff *skb;
++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->dev, txQ_num);
++ int count = max(TX_FREE_MAX_COUNT, n_desc);
++ unsigned int flags;
++
++ netif_info(priv, tx_done, priv->dev, "%s\n", __func__);
++
++ if (!from_tx)
++ __netif_tx_lock_bh(tx_queue);
++
++ /* Clean HIF and client queue */
++ while (count && (skb = hif_lib_tx_get_next_complete(&priv->client, txQ_num, &flags, count))) {
++
++ /* FIXME : Invalid data can be skipped in hif_lib itself */
++ if (flags & HIF_DATA_VALID) {
++ dev_kfree_skb_any(skb);
++
++ }
++ // When called from the timer, flush all descriptors
++ if (from_tx)
++ count--;
++ }
++
++ if (!from_tx)
++ __netif_tx_unlock_bh(tx_queue);
++}
++
++/** pfe_eth_flush_tx
++ */
++static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv, int force)
++{
++ int ii;
++
++ netif_info(priv, tx_done, priv->dev, "%s\n", __func__);
++
++ for (ii = 0; ii < emac_txq_cnt; ii++) {
++ if (force || (time_after(jiffies, priv->client.tx_q[ii].jiffies_last_packet + (COMCERTO_TX_RECOVERY_TIMEOUT_MS * HZ)/1000))) {
++ pfe_eth_flush_txQ(priv, ii, 0, 0); //We will release everything we can based on from_tx param, so the count param can be set to any value
++ hif_lib_update_credit(&priv->client, ii);
++ }
++ }
++}
++
++void pfe_tx_get_req_desc(struct sk_buff *skb, unsigned int *n_desc, unsigned int *n_segs)
++{
++ struct skb_shared_info *sh = skb_shinfo(skb);
++
++ // Scattered data
++ if (sh->nr_frags) {
++ *n_desc = sh->nr_frags + 1;
++ *n_segs = 1;
++ }
++ // Regular case
++ else {
++ *n_desc = 1;
++ *n_segs = 1;
++ }
++ return;
++}
++
++/** pfe_eth_send_packet
++ */
++static int pfe_eth_send_packet(struct sk_buff *skb, struct net_device *dev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ int txQ_num = skb_get_queue_mapping(skb);
++ int n_desc, n_segs, count;
++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->dev, txQ_num);
++
++ netif_info(priv, tx_queued, dev, "%s\n", __func__);
++
++ if ((!skb_is_gso(skb)) && (skb_headroom(skb) < (PFE_PKT_HEADER_SZ + sizeof(unsigned long)))) {
++
++ netif_warn(priv, tx_err, priv->dev, "%s: copying skb\n", __func__);
++
++ if (pskb_expand_head(skb, (PFE_PKT_HEADER_SZ + sizeof(unsigned long)), 0, GFP_ATOMIC)) {
++ /* No need to re-transmit, no way to recover*/
++ kfree_skb(skb);
++ priv->stats.tx_dropped++;
++ return NETDEV_TX_OK;
++ }
++ }
++
++ pfe_tx_get_req_desc(skb, &n_desc, &n_segs);
++
++ hif_tx_lock(&pfe->hif);
++ if(unlikely(pfe_eth_might_stop_tx(priv, txQ_num, tx_queue, n_desc, n_segs))) {
++#ifdef PFE_ETH_TX_STATS
++ if(priv->was_stopped[txQ_num]) {
++ priv->clean_fail[txQ_num]++;
++ priv->was_stopped[txQ_num] = 0;
++ }
++#endif
++ hif_tx_unlock(&pfe->hif);
++ return NETDEV_TX_BUSY;
++ }
++
++ pfe_hif_send_packet(skb, priv, txQ_num);
++
++ hif_tx_unlock(&pfe->hif);
++
++ dev->trans_start = jiffies;
++
++ // Recycle buffers if a socket's send buffer becomes half full or if the HIF client queue starts filling up
++ if (((count = (hif_lib_tx_pending(&priv->client, txQ_num) - HIF_CL_TX_FLUSH_MARK)) > 0)
++ || (skb->sk && ((sk_wmem_alloc_get(skb->sk) << 1) > skb->sk->sk_sndbuf)))
++ pfe_eth_flush_txQ(priv, txQ_num, 1, count);
++
++#ifdef PFE_ETH_TX_STATS
++ priv->was_stopped[txQ_num] = 0;
++#endif
++
++ return NETDEV_TX_OK;
++}
++
++/** pfe_eth_select_queue
++ *
++ */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
++static u16 pfe_eth_select_queue( struct net_device *dev, struct sk_buff *skb,
++ void *accel_priv, select_queue_fallback_t fallback)
++#else
++static u16 pfe_eth_select_queue( struct net_device *dev, struct sk_buff *skb )
++#endif
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++
++ return pfe_eth_get_queuenum(priv, skb);
++}
++
++
++/** pfe_eth_get_stats
++ */
++static struct net_device_stats *pfe_eth_get_stats(struct net_device *dev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++
++ netif_info(priv, drv, dev, "%s\n", __func__);
++
++ return &priv->stats;
++}
++
++
++/** pfe_eth_change_mtu
++ */
++static int pfe_eth_change_mtu(struct net_device *dev, int new_mtu)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ int oldsize = dev->mtu ;
++ int frame_size = new_mtu + ETH_HLEN +4;
++
++ netif_info(priv, drv, dev, "%s\n", __func__);
++
++ if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
++ netif_err(priv, drv, dev, "Invalid MTU setting\n");
++ return -EINVAL;
++ }
++
++ if ((new_mtu > 1500) && (dev->features & NETIF_F_TSO))
++ {
++ priv->usr_features = dev->features;
++ if (dev->features & NETIF_F_TSO)
++ {
++ netdev_err(dev, "MTU cannot be set to more than 1500 while TSO is enabled. disabling TSO.\n");
++ dev->features &= ~(NETIF_F_TSO);
++ }
++ }
++ else if ((dev->mtu > 1500) && (new_mtu <= 1500))
++ {
++ if (priv->usr_features & NETIF_F_TSO)
++ {
++ priv->usr_features &= ~(NETIF_F_TSO);
++ dev->features |= NETIF_F_TSO;
++ netdev_err(dev, "MTU is <= 1500, Enabling TSO feature.\n");
++ }
++ }
++
++ /* Only stop and start the controller if it isn't already
++ * stopped, and we changed something */
++ if ((oldsize != new_mtu) && (dev->flags & IFF_UP)){
++ netdev_err(dev, "Can not change MTU - fast_path must be disabled and ifconfig down must be issued first\n");
++
++ return -EINVAL;
++ }
++
++ dev->mtu = new_mtu;
++
++ return 0;
++}
++
++/** pfe_eth_set_mac_address
++ */
++static int pfe_eth_set_mac_address(struct net_device *dev, void *addr)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ struct sockaddr *sa = addr;
++
++ netif_info(priv, drv, dev, "%s\n", __func__);
++
++ if (!is_valid_ether_addr(sa->sa_data))
++ return -EADDRNOTAVAIL;
++
++ memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
++
++ gemac_set_laddrN(priv->EMAC_baseaddr, (MAC_ADDR *)dev->dev_addr, 1);
++
++ return 0;
++
++}
++
++/** pfe_eth_enet_addr_byte_mac
++ */
++int pfe_eth_enet_addr_byte_mac(u8 * enet_byte_addr, MAC_ADDR *enet_addr)
++{
++ if ((enet_byte_addr == NULL) || (enet_addr == NULL))
++ {
++ return -1;
++ }
++ else
++ {
++ enet_addr->bottom = enet_byte_addr[0] |
++ (enet_byte_addr[1] << 8) |
++ (enet_byte_addr[2] << 16) |
++ (enet_byte_addr[3] << 24);
++ enet_addr->top = enet_byte_addr[4] |
++ (enet_byte_addr[5] << 8);
++ return 0;
++ }
++}
++
++
++
++/** pfe_eth_set_multi
++ */
++static void pfe_eth_set_multi(struct net_device *dev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ MAC_ADDR hash_addr; /* hash register structure */
++ MAC_ADDR spec_addr; /* specific mac address register structure */
++ int result; /* index into hash register to set.. */
++ int uc_count = 0;
++ struct netdev_hw_addr *ha;
++
++ if (dev->flags & IFF_PROMISC) {
++ netif_info(priv, drv, dev, "entering promiscuous mode\n");
++
++ priv->promisc = 1;
++ gemac_enable_copy_all(priv->EMAC_baseaddr);
++ } else {
++ priv->promisc = 0;
++ gemac_disable_copy_all(priv->EMAC_baseaddr);
++ }
++
++ /* Enable broadcast frame reception if required. */
++ if (dev->flags & IFF_BROADCAST) {
++ gemac_allow_broadcast(priv->EMAC_baseaddr);
++ } else {
++ netif_info(priv, drv, dev, "disabling broadcast frame reception\n");
++
++ gemac_no_broadcast(priv->EMAC_baseaddr);
++ }
++
++ if (dev->flags & IFF_ALLMULTI) {
++ /* Set the hash to rx all multicast frames */
++ hash_addr.bottom = 0xFFFFFFFF;
++ hash_addr.top = 0xFFFFFFFF;
++ gemac_set_hash(priv->EMAC_baseaddr, &hash_addr);
++ gemac_enable_multicast(priv->EMAC_baseaddr);
++ netdev_for_each_uc_addr(ha, dev) {
++ if(uc_count >= MAX_UC_SPEC_ADDR_REG) break;
++ pfe_eth_enet_addr_byte_mac(ha->addr, &spec_addr);
++ gemac_set_laddrN(priv->EMAC_baseaddr, &spec_addr, uc_count + 2);
++ uc_count++;
++ }
++ } else if ((netdev_mc_count(dev) > 0) || (netdev_uc_count(dev))) {
++ u8 *addr;
++
++ hash_addr.bottom = 0;
++ hash_addr.top = 0;
++
++ netdev_for_each_mc_addr(ha, dev) {
++ addr = ha->addr;
++
++ netif_info(priv, drv, dev, "adding multicast address %X:%X:%X:%X:%X:%X to gem filter\n",
++ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
++
++ result = pfe_eth_get_hash(addr);
++
++ if (result >= EMAC_HASH_REG_BITS) {
++ break;
++ } else {
++ if (result < 32) {
++ hash_addr.bottom |= (1 << result);
++ } else {
++ hash_addr.top |= (1 << (result - 32));
++ }
++ }
++
++ }
++
++ uc_count = -1;
++ netdev_for_each_uc_addr(ha, dev) {
++ addr = ha->addr;
++
++ if(++uc_count < MAX_UC_SPEC_ADDR_REG)
++ {
++ netdev_info(dev, "adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem filter\n",
++ addr[0], addr[1], addr[2],
++ addr[3], addr[4], addr[5]);
++
++ pfe_eth_enet_addr_byte_mac(addr, &spec_addr);
++ gemac_set_laddrN(priv->EMAC_baseaddr, &spec_addr, uc_count + 2);
++ }
++ else
++ {
++ netif_info(priv, drv, dev, "adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem hash\n",
++ addr[0], addr[1], addr[2],
++ addr[3], addr[4], addr[5]);
++
++ result = pfe_eth_get_hash(addr);
++ if (result >= EMAC_HASH_REG_BITS) {
++ break;
++ } else {
++ if (result < 32)
++ hash_addr.bottom |= (1 << result);
++ else
++ hash_addr.top |= (1 << (result - 32));
++ }
++
++
++ }
++ }
++
++ gemac_set_hash(priv->EMAC_baseaddr, &hash_addr);
++ if(netdev_mc_count(dev))
++ gemac_enable_multicast(priv->EMAC_baseaddr);
++ else
++ gemac_disable_multicast(priv->EMAC_baseaddr);
++ }
++
++ if(netdev_uc_count(dev) >= MAX_UC_SPEC_ADDR_REG)
++ gemac_enable_unicast(priv->EMAC_baseaddr);
++ else
++ {
++ /* Check if there are any specific address HW registers that need
++ * to be flushed
++ * */
++ for(uc_count = netdev_uc_count(dev); uc_count < MAX_UC_SPEC_ADDR_REG; uc_count++)
++ gemac_clear_laddrN(priv->EMAC_baseaddr, uc_count + 2);
++
++ gemac_disable_unicast(priv->EMAC_baseaddr);
++ }
++
++ if (dev->flags & IFF_LOOPBACK) {
++ gemac_set_loop(priv->EMAC_baseaddr, LB_LOCAL);
++ }
++
++ return;
++}
++
++/** pfe_eth_set_features
++ */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)
++static int pfe_eth_set_features(struct net_device *dev, netdev_features_t features)
++#else
++static int pfe_eth_set_features(struct net_device *dev, u32 features)
++#endif
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++ int rc = 0;
++
++ if (features & NETIF_F_RXCSUM)
++ gemac_enable_rx_checksum_offload(priv->EMAC_baseaddr);
++ else
++ gemac_disable_rx_checksum_offload(priv->EMAC_baseaddr);
++ return rc;
++}
++
++/** pfe_eth_fix_features
++ */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)
++static netdev_features_t pfe_eth_fix_features(struct net_device *dev, netdev_features_t features)
++#else
++static unsigned int pfe_eth_fix_features(struct net_device *dev,u32 features)
++#endif
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(dev);
++
++ if (dev->mtu > 1500)
++ {
++ if (features & (NETIF_F_TSO))
++ {
++ priv->usr_features |= NETIF_F_TSO;
++ features &= ~(NETIF_F_TSO);
++ netdev_err(dev, "TSO cannot be enabled when the MTU is larger than 1500. Please set the MTU to 1500 or lower first.\n");
++ }
++ }
++
++ return features;
++}
++
++/** pfe_eth_tx_timeout
++ */
++void pfe_eth_tx_timeout(unsigned long data )
++{
++ struct pfe_eth_priv_s *priv = (struct pfe_eth_priv_s *)data;
++
++ netif_info(priv, timer, priv->dev, "%s\n", __func__);
++
++ pfe_eth_flush_tx(priv, 0);
++
++ priv->tx_timer.expires = jiffies + ( COMCERTO_TX_RECOVERY_TIMEOUT_MS * HZ )/1000;
++ add_timer(&priv->tx_timer);
++}
++
++/** pfe_eth_fast_tx_timeout
++ */
++static enum hrtimer_restart pfe_eth_fast_tx_timeout(struct hrtimer *timer)
++{
++ struct pfe_eth_fast_timer *fast_tx_timeout = container_of(timer, struct pfe_eth_fast_timer, timer);
++ struct pfe_eth_priv_s *priv = container_of(fast_tx_timeout->base, struct pfe_eth_priv_s, fast_tx_timeout);
++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->dev, fast_tx_timeout->queuenum);
++
++ if(netif_tx_queue_stopped(tx_queue)) {
++#ifdef PFE_ETH_TX_STATS
++ priv->was_stopped[fast_tx_timeout->queuenum] = 1;
++#endif
++ netif_tx_wake_queue(tx_queue);
++ }
++
++ return HRTIMER_NORESTART;
++}
++
++/** pfe_eth_fast_tx_timeout_init
++ */
++static void pfe_eth_fast_tx_timeout_init(struct pfe_eth_priv_s *priv)
++{
++ int i;
++ for (i = 0; i < emac_txq_cnt; i++) {
++ priv->fast_tx_timeout[i].queuenum = i;
++ hrtimer_init(&priv->fast_tx_timeout[i].timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
++ priv->fast_tx_timeout[i].timer.function = pfe_eth_fast_tx_timeout;
++ priv->fast_tx_timeout[i].base = priv->fast_tx_timeout;
++ }
++}
++
++static struct sk_buff *pfe_eth_rx_skb(struct net_device *dev, struct pfe_eth_priv_s *priv, unsigned int qno)
++{
++ void *buf_addr;
++ unsigned int rx_ctrl;
++ unsigned int desc_ctrl = 0;
++ struct hif_ipsec_hdr *ipsec_hdr = NULL;
++ struct sk_buff *skb;
++ struct sk_buff *skb_frag, *skb_frag_last = NULL;
++ int length = 0, offset;
++
++ skb = priv->skb_inflight[qno];
++
++ if (skb && (skb_frag_last = skb_shinfo(skb)->frag_list)) {
++ while (skb_frag_last->next)
++ skb_frag_last = skb_frag_last->next;
++ }
++
++ while (!(desc_ctrl & CL_DESC_LAST)) {
++
++ buf_addr = hif_lib_receive_pkt(&priv->client, qno, &length, &offset, &rx_ctrl, &desc_ctrl, (void **)&ipsec_hdr);
++ if (!buf_addr)
++ goto incomplete;
++
++#ifdef PFE_ETH_NAPI_STATS
++ priv->napi_counters[NAPI_DESC_COUNT]++;
++#endif
++
++ /* First frag */
++ if (desc_ctrl & CL_DESC_FIRST) {
++#if defined(CONFIG_PLATFORM_EMULATION) || defined(CONFIG_PLATFORM_PCI)
++ skb = dev_alloc_skb(PFE_BUF_SIZE);
++ if (unlikely(!skb)) {
++ goto pkt_drop;
++ }
++
++ skb_copy_to_linear_data(skb, buf_addr, length + offset);
++ kfree(buf_addr);
++#else
++#if defined(CONFIG_COMCERTO_ZONE_DMA_NCNB)
++ skb = alloc_skb(length + offset + 32, GFP_ATOMIC);
++#else
++ skb = alloc_skb_header(PFE_BUF_SIZE, buf_addr, GFP_ATOMIC);
++#endif
++ if (unlikely(!skb)) {
++ goto pkt_drop;
++ }
++#endif
++ skb_reserve(skb, offset);
++#if defined(CONFIG_COMCERTO_ZONE_DMA_NCNB)
++ __memcpy(skb->data, buf_addr + offset, length);
++ if (ipsec_hdr) {
++ sah_local = *(unsigned int *)&ipsec_hdr->sa_handle[0];
++ }
++ kfree(buf_addr);
++#endif
++ skb_put(skb, length);
++ skb->dev = dev;
++
++ if ((dev->features & NETIF_F_RXCSUM) && (rx_ctrl & HIF_CTRL_RX_CHECKSUMMED))
++ skb->ip_summed = CHECKSUM_UNNECESSARY;
++ else
++ skb_checksum_none_assert(skb);
++
++ } else {
++
++ /* Next frags */
++ if (unlikely(!skb)) {
++ printk(KERN_ERR "%s: NULL skb_inflight\n", __func__);
++ goto pkt_drop;
++ }
++
++#if defined(CONFIG_COMCERTO_ZONE_DMA_NCNB)
++ skb_frag = alloc_skb(length + offset + 32, GFP_ATOMIC);
++#else
++ skb_frag = alloc_skb_header(PFE_BUF_SIZE, buf_addr, GFP_ATOMIC);
++#endif
++ if (unlikely(!skb_frag)) {
++ kfree(buf_addr);
++ goto pkt_drop;
++ }
++
++ skb_reserve(skb_frag, offset);
++#if defined(CONFIG_COMCERTO_ZONE_DMA_NCNB)
++ __memcpy(skb_frag->data, buf_addr + offset, length);
++ kfree(buf_addr);
++#endif
++ skb_put(skb_frag, length);
++
++ skb_frag->dev = dev;
++
++ if (skb_shinfo(skb)->frag_list)
++ skb_frag_last->next = skb_frag;
++ else
++ skb_shinfo(skb)->frag_list = skb_frag;
++
++ skb->truesize += skb_frag->truesize;
++ skb->data_len += length;
++ skb->len += length;
++ skb_frag_last = skb_frag;
++ }
++ }
++
++ priv->skb_inflight[qno] = NULL;
++ return skb;
++
++incomplete:
++ priv->skb_inflight[qno] = skb;
++ return NULL;
++
++pkt_drop:
++ priv->skb_inflight[qno] = NULL;
++
++ if (skb) {
++ kfree_skb(skb);
++ } else {
++ kfree(buf_addr);
++ }
++
++ priv->stats.rx_errors++;
++
++ return NULL;
++}
++
++
++/** pfe_eth_poll
++ */
++static int pfe_eth_poll(struct pfe_eth_priv_s *priv, struct napi_struct *napi, unsigned int qno, int budget)
++{
++ struct net_device *dev = priv->dev;
++ struct sk_buff *skb;
++ int work_done = 0;
++ unsigned int len;
++
++ netif_info(priv, intr, priv->dev, "%s\n", __func__);
++
++#ifdef PFE_ETH_NAPI_STATS
++ priv->napi_counters[NAPI_POLL_COUNT]++;
++#endif
++
++ do {
++ skb = pfe_eth_rx_skb(dev, priv, qno);
++
++ if (!skb)
++ break;
++
++ len = skb->len;
++
++ /* Packet will be processed */
++ skb->protocol = eth_type_trans(skb, dev);
++
++ netif_receive_skb(skb);
++
++ priv->stats.rx_packets++;
++ priv->stats.rx_bytes += len;
++
++ dev->last_rx = jiffies;
++
++ work_done++;
++
++#ifdef PFE_ETH_NAPI_STATS
++ priv->napi_counters[NAPI_PACKET_COUNT]++;
++#endif
++
++ } while (work_done < budget);
++
++ /* If no Rx receive nor cleanup work was done, exit polling mode.
++ * No more netif_running(dev) check is required here , as this is checked in
++ * net/core/dev.c ( 2.6.33.5 kernel specific).
++ */
++ if (work_done < budget) {
++ napi_complete(napi);
++
++ hif_lib_event_handler_start(&priv->client, EVENT_RX_PKT_IND, qno);
++ }
++#ifdef PFE_ETH_NAPI_STATS
++ else
++ priv->napi_counters[NAPI_FULL_BUDGET_COUNT]++;
++#endif
++
++ return work_done;
++}
++
++/** pfe_eth_lro_poll
++ */
++static int pfe_eth_lro_poll(struct napi_struct *napi, int budget)
++{
++ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s, lro_napi);
++
++ netif_info(priv, intr, priv->dev, "%s\n", __func__);
++
++ return pfe_eth_poll(priv, napi, 2, budget);
++}
++
++
++/** pfe_eth_low_poll
++ */
++static int pfe_eth_low_poll(struct napi_struct *napi, int budget)
++{
++ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s, low_napi);
++
++ netif_info(priv, intr, priv->dev, "%s\n", __func__);
++
++ return pfe_eth_poll(priv, napi, 1, budget);
++}
++
++/** pfe_eth_high_poll
++ */
++static int pfe_eth_high_poll(struct napi_struct *napi, int budget )
++{
++ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s, high_napi);
++
++ netif_info(priv, intr, priv->dev, "%s\n", __func__);
++
++ return pfe_eth_poll(priv, napi, 0, budget);
++}
++
++static const struct net_device_ops pfe_netdev_ops = {
++ .ndo_open = pfe_eth_open,
++ .ndo_stop = pfe_eth_close,
++ .ndo_start_xmit = pfe_eth_send_packet,
++ .ndo_select_queue = pfe_eth_select_queue,
++ .ndo_get_stats = pfe_eth_get_stats,
++ .ndo_change_mtu = pfe_eth_change_mtu,
++ .ndo_set_mac_address = pfe_eth_set_mac_address,
++ .ndo_set_rx_mode = pfe_eth_set_multi,
++ .ndo_set_features = pfe_eth_set_features,
++ .ndo_fix_features = pfe_eth_fix_features,
++ .ndo_validate_addr = eth_validate_addr,
++};
++
++
++/** pfe_eth_init_one
++ */
++
++static int pfe_eth_init_one( struct pfe *pfe, int id )
++{
++ struct net_device *dev = NULL;
++ struct pfe_eth_priv_s *priv = NULL;
++ struct comcerto_eth_platform_data *einfo;
++ struct comcerto_mdio_platform_data *minfo;
++ struct comcerto_pfe_platform_data *pfe_info;
++ int err;
++
++ /* Extract pltform data */
++#if defined(CONFIG_PLATFORM_EMULATION) || defined(CONFIG_PLATFORM_PCI)
++ pfe_info = (struct comcerto_pfe_platform_data *) &comcerto_pfe_pdata;
++#else
++ pfe_info = (struct comcerto_pfe_platform_data *) pfe->dev->platform_data;
++#endif
++ if (!pfe_info) {
++ printk(KERN_ERR "%s: pfe missing additional platform data\n", __func__);
++ err = -ENODEV;
++ goto err0;
++ }
++
++ einfo = (struct comcerto_eth_platform_data *) pfe_info->comcerto_eth_pdata;
++
++ /* einfo never be NULL, but no harm in having this check */
++ if (!einfo) {
++ printk(KERN_ERR "%s: pfe missing additional gemacs platform data\n", __func__);
++ err = -ENODEV;
++ goto err0;
++ }
++
++ minfo = (struct comcerto_mdio_platform_data *) pfe_info->comcerto_mdio_pdata;
++
++ /* einfo never be NULL, but no harm in having this check */
++ if (!minfo) {
++ printk(KERN_ERR "%s: pfe missing additional mdios platform data\n", __func__);
++ err = -ENODEV;
++ goto err0;
++ }
++
++ /*
++ * FIXME: Need to check some flag in "einfo" to know whether
++ * GEMAC is enabled Or not.
++ */
++
++ /* Create an ethernet device instance */
++ dev = alloc_etherdev_mq(sizeof (*priv), emac_txq_cnt);
++
++ if (!dev) {
++ printk(KERN_ERR "%s: gemac %d device allocation failed\n", __func__, einfo[id].gem_id);
++ err = -ENOMEM;
++ goto err0;
++ }
++
++ priv = netdev_priv(dev);
++ priv->dev = dev;
++ priv->id = einfo[id].gem_id;
++ priv->pfe = pfe;
++
++#if defined(CONFIG_PLATFORM_C2000)
++ /* get gemac tx clock */
++ priv->gemtx_clk = clk_get(NULL, "gemtx");
++
++ if (IS_ERR(priv->gemtx_clk)) {
++ printk(KERN_ERR "%s: Unable to get the clock for gemac %d\n", __func__, priv->id);
++ err = -ENODEV;
++ goto err1;
++ }
++#endif
++
++ pfe->eth.eth_priv[id] = priv;
++
++ /* Set the info in the priv to the current info */
++ priv->einfo = &einfo[id];
++ priv->EMAC_baseaddr = cbus_emac_base[id];
++ priv->PHY_baseaddr = cbus_emac_base[0];
++ priv->mdio_muxval = einfo[id].mdio_muxval;
++ priv->GPI_baseaddr = cbus_gpi_base[id];
++
++ /* FIXME : For now TMU queue numbers hardcoded, later should be taken from pfe.h */
++#define HIF_GEMAC_TMUQ_BASE 6
++ priv->low_tmuQ = HIF_GEMAC_TMUQ_BASE + (id * 2);
++ priv->high_tmuQ = priv->low_tmuQ + 1;
++
++ spin_lock_init(&priv->lock);
++ priv->tx_timer.data = (unsigned long)priv;
++ priv->tx_timer.function = pfe_eth_tx_timeout;
++ priv->tx_timer.expires = jiffies + ( COMCERTO_TX_RECOVERY_TIMEOUT_MS * HZ )/1000;
++ init_timer(&priv->tx_timer);
++
++ pfe_eth_fast_tx_timeout_init(priv);
++
++ /* Copy the station address into the dev structure, */
++ memcpy(dev->dev_addr, einfo[id].mac_addr, ETH_ALEN);
++
++ /* Initialize mdio */
++ if (minfo[id].enabled) {
++ if ((err = pfe_eth_mdio_init(priv, &minfo[id]))) {
++ netdev_err(dev, "%s: pfe_eth_mdio_init() failed\n", __func__);
++ goto err2;
++ }
++ }
++
++ dev->mtu = 1500;
++
++ /* supported features */
++ dev->hw_features = NETIF_F_SG;
++ /* Enable after checksum offload is validated
++ dev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
++ NETIF_F_SG; */
++
++ /* enabled by default */
++ dev->features = dev->hw_features;
++
++ priv->usr_features = dev->features;
++
++ dev->netdev_ops = &pfe_netdev_ops;
++
++ dev->ethtool_ops = &pfe_ethtool_ops;
++
++ /* Enable basic messages by default */
++ priv->msg_enable = NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK | NETIF_MSG_PROBE;
++
++ netif_napi_add(dev, &priv->low_napi, pfe_eth_low_poll, HIF_RX_POLL_WEIGHT - 16);
++ netif_napi_add(dev, &priv->high_napi, pfe_eth_high_poll, HIF_RX_POLL_WEIGHT - 16);
++ netif_napi_add(dev, &priv->lro_napi, pfe_eth_lro_poll, HIF_RX_POLL_WEIGHT - 16);
++
++ err = register_netdev(dev);
++
++ if (err) {
++ netdev_err(dev, "register_netdev() failed\n");
++ goto err3;
++ }
++
++ if (!(priv->einfo->phy_flags & GEMAC_NO_PHY)) {
++ err = pfe_phy_init(dev);
++ if (err) {
++ netdev_err(dev, "%s: pfe_phy_init() failed\n", __func__);
++ goto err4;
++ }
++ }
++
++
++ /* Create all the sysfs files */
++ if(pfe_eth_sysfs_init(dev))
++ goto err4;
++
++ netif_info(priv, probe, dev, "%s: created interface, baseaddr: %p\n", __func__, priv->EMAC_baseaddr);
++
++ return 0;
++err4:
++ unregister_netdev(dev);
++err3:
++ pfe_eth_mdio_exit(priv->mii_bus);
++err2:
++#if defined(CONFIG_PLATFORM_C2000)
++ clk_put(priv->gemtx_clk);
++err1:
++#endif
++ free_netdev(priv->dev);
++
++err0:
++ return err;
++}
++
++/** pfe_eth_init
++ */
++int pfe_eth_init(struct pfe *pfe)
++{
++ int ii = 0;
++ int err;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ cbus_emac_base[0] = EMAC1_BASE_ADDR;
++ cbus_emac_base[1] = EMAC2_BASE_ADDR;
++
++ cbus_gpi_base[0] = EGPI1_BASE_ADDR;
++ cbus_gpi_base[1] = EGPI2_BASE_ADDR;
++
++#if !defined(CONFIG_PLATFORM_LS1012A)
++ cbus_emac_base[2] = EMAC3_BASE_ADDR;
++ cbus_gpi_base[2] = EGPI3_BASE_ADDR;
++#endif
++
++ for (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) {
++ if ((err = pfe_eth_init_one(pfe, ii)))
++ goto err0;
++ }
++
++ return 0;
++
++err0:
++ while(ii--){
++ pfe_eth_exit_one( pfe->eth.eth_priv[ii] );
++ }
++
++ /* Register three network devices in the kernel */
++ return err;
++}
++
++/** pfe_eth_exit_one
++ */
++static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv)
++{
++ netif_info(priv, probe, priv->dev, "%s\n", __func__);
++
++ pfe_eth_sysfs_exit(priv->dev);
++
++#if defined(CONFIG_PLATFORM_C2000)
++ clk_put(priv->gemtx_clk);
++#endif
++
++ unregister_netdev(priv->dev);
++
++ pfe_eth_mdio_exit(priv->mii_bus);
++
++ if (!(priv->einfo->phy_flags & GEMAC_NO_PHY))
++ pfe_phy_exit(priv->dev);
++
++ free_netdev(priv->dev);
++}
++
++/** pfe_eth_exit
++ */
++void pfe_eth_exit(struct pfe *pfe)
++{
++ int ii;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ for(ii = 0; ii < NUM_GEMAC_SUPPORT; ii++ ) {
++ /*
++ * FIXME: Need to check some flag in "einfo" to know whether
++ * GEMAC is enabled Or not.
++ */
++
++ pfe_eth_exit_one(pfe->eth.eth_priv[ii]);
++ }
++}
++
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_eth.h
+@@ -0,0 +1,384 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _PFE_ETH_H_
++#define _PFE_ETH_H_
++#include <linux/kernel.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool.h>
++#include <linux/mii.h>
++#include <linux/phy.h>
++#include <linux/clk.h>
++#include <linux/interrupt.h>
++#include <linux/time.h>
++
++#define PFE_ETH_NAPI_STATS
++#define PFE_ETH_TX_STATS
++
++#define PFE_ETH_FRAGS_MAX (65536/HIF_RX_PKT_MIN_SIZE)
++#define LRO_LEN_COUNT_MAX 32
++#define LRO_NB_COUNT_MAX 32
++
++#if defined(CONFIG_PLATFORM_PCI) || defined(CONFIG_PLATFORM_EMULATION) || defined(CONFIG_PLATFORM_LS1012A)
++
++#define CONFIG_COMCERTO_GEMAC 1
++
++#define CONFIG_COMCERTO_USE_MII 1
++#define CONFIG_COMCERTO_USE_RMII 2
++#define CONFIG_COMCERTO_USE_GMII 4
++#define CONFIG_COMCERTO_USE_RGMII 8
++#define CONFIG_COMCERTO_USE_SGMII 16
++
++#define GEMAC_SW_CONF (1 << 8) | (1 << 11) // GEMAC configured by SW
++#define GEMAC_PHY_CONF 0 // GEMAC configured by phy lines (not for MII/GMII)
++#define GEMAC_SW_FULL_DUPLEX (1 << 9)
++#define GEMAC_SW_SPEED_10M (0 << 12)
++#define GEMAC_SW_SPEED_100M (1 << 12)
++#define GEMAC_SW_SPEED_1G (2 << 12)
++
++#define GEMAC_NO_PHY (1 << 0) // set if no phy connected to MAC (ex ethernet switch). In this case use MAC fixed configuration
++#define GEMAC_PHY_RGMII_ADD_DELAY (1 << 1)
++
++/* gemac to interface name assignment */
++#define GEMAC0_ITF_NAME "eth5"
++#define GEMAC1_ITF_NAME "eth6"
++#define GEMAC2_ITF_NAME "eth7"
++
++#define GEMAC0_MAC { 0x00, 0xED, 0xCD, 0xEF, 0xAA, 0xCC }
++#define GEMAC1_MAC { 0x00, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E }
++
++struct comcerto_eth_platform_data {
++ /* device specific information */
++ u32 device_flags;
++ char name[16];
++
++
++ /* board specific information */
++ u32 mii_config;
++ u32 gemac_mode;
++ u32 phy_flags;
++ u32 gem_id;
++ u32 bus_id;
++ u32 phy_id;
++ u32 mdio_muxval;
++ u8 mac_addr[ETH_ALEN];
++};
++
++struct comcerto_mdio_platform_data {
++ int enabled;
++ int irq[32];
++ u32 phy_mask;
++ int mdc_div;
++};
++
++struct comcerto_pfe_platform_data
++{
++ struct comcerto_eth_platform_data comcerto_eth_pdata[3];
++ struct comcerto_mdio_platform_data comcerto_mdio_pdata[3];
++};
++#if !defined(CONFIG_PLATFORM_LS1012A)
++static struct comcerto_pfe_platform_data comcerto_pfe_pdata = {
++ .comcerto_eth_pdata[0] = {
++ .name = GEMAC0_ITF_NAME,
++ .device_flags = CONFIG_COMCERTO_GEMAC,
++ .mii_config = CONFIG_COMCERTO_USE_MII,
++ .gemac_mode = GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_100M,
++#if defined(CONFIG_PLATFORM_EMULATION) || defined(CONFIG_PLATFORM_PCI)
++ .phy_flags = GEMAC_NO_PHY,
++#else
++ .phy_flags = GEMAC_PHY_RGMII_ADD_DELAY,
++#endif
++ .bus_id = 0,
++ .phy_id = 0,
++ .gem_id = 0,
++ .mac_addr = (u8[])GEMAC0_MAC,
++ },
++
++ .comcerto_eth_pdata[1] = {
++ .name = GEMAC1_ITF_NAME,
++ .device_flags = CONFIG_COMCERTO_GEMAC,
++ .mii_config = CONFIG_COMCERTO_USE_RGMII,
++ .gemac_mode = GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G,
++ .phy_flags = GEMAC_NO_PHY,
++ .gem_id = 1,
++ .mac_addr = (u8[])GEMAC1_MAC,
++ },
++
++ .comcerto_eth_pdata[2] = {
++ .name = GEMAC2_ITF_NAME,
++ },
++
++ .comcerto_mdio_pdata[0] = {
++ .enabled = 1,
++ .phy_mask = 0xFFFFFFFE,
++ .mdc_div = 96,
++ .irq = {
++ [0] = PHY_POLL,
++ },
++ },
++};
++#endif
++#endif
++
++#if defined(CONFIG_PLATFORM_LS1012A)
++#define NUM_GEMAC_SUPPORT 2
++#define DRV_NAME "ls1012a-geth"
++#else
++#define NUM_GEMAC_SUPPORT 3
++#define DRV_NAME "c2000-geth"
++#endif
++#define COMCERTO_INFOSTR_LEN 32
++#define COMCERTO_TX_RECOVERY_TIMEOUT_MS 500
++#define COMCERTO_TX_FAST_RECOVERY_TIMEOUT_MS 3
++#define TX_POLL_TIMEOUT_MS 1000
++
++#define EMAC_TXQ_CNT 16
++#define EMAC_TXQ_DEPTH (HIF_TX_DESC_NT)
++
++#define JUMBO_FRAME_SIZE 10258
++/**
++ * Client Tx queue threshold, for txQ flush condition.
++ * It must be smaller than the queue size (in case we ever change it in the future).
++ */
++#define HIF_CL_TX_FLUSH_MARK 32
++
++/**
++ * Max number of TX resources (HIF descriptors or skbs) that will be released
++ * in a single go during batch recycling.
++ * Should be lower than the flush mark so the SW can provide the HW with a
++ * continuous stream of packets instead of bursts.
++ */
++#define TX_FREE_MAX_COUNT 16
++#define EMAC_RXQ_CNT 3
++#define EMAC_RXQ_DEPTH HIF_RX_DESC_NT /* make sure clients can receive a full burst of packets */
++#define EMAC_RMON_TXBYTES_POS 0x00
++#define EMAC_RMON_RXBYTES_POS 0x14
++
++#define EMAC_QUEUENUM_MASK (emac_txq_cnt - 1)
++#define EMAC_MDIO_TIMEOUT 1000
++#define MAX_UC_SPEC_ADDR_REG 31
++
++
++/* The set of statistics registers implemented in the Cadence MAC.
++ * The statistics registers implemented are a subset of all the statistics
++ * available, but contains all the compulsory ones.
++ * For full descriptions on the registers, refer to the Cadence MAC programmers
++ * guide or the IEEE 802.3 specifications.
++ */
++struct gemac_stats{
++ u32 octets_tx_bot; /* Lower 32-bits for number of octets tx'd */
++ u32 octets_tx_top; /* Upper 16-bits for number of octets tx'd */
++ u32 frames_tx; /* Number of frames transmitted OK */
++ u32 broadcast_tx; /* Number of broadcast frames transmitted */
++ u32 multicast_tx; /* Number of multicast frames transmitted */
++ u32 pause_tx; /* Number of pause frames transmitted. */
++ u32 frame64_tx; /* Number of 64byte frames transmitted */
++ u32 frame65_127_tx; /* Number of 65-127 byte frames transmitted */
++ u32 frame128_255_tx; /* Number of 128-255 byte frames transmitted */
++ u32 frame256_511_tx; /* Number of 256-511 byte frames transmitted */
++ u32 frame512_1023_tx; /* Number of 512-1023 byte frames transmitted */
++ u32 frame1024_1518_tx; /* Number of 1024-1518 byte frames transmitted*/
++ u32 frame1519_tx; /* Number of frames greater than 1518 bytes tx*/
++ u32 tx_urun; /* Transmit underrun errors due to DMA */
++ u32 single_col; /* Number of single collision frames */
++ u32 multi_col; /* Number of multi collision frames */
++ u32 excess_col; /* Number of excessive collision frames. */
++ u32 late_col; /* Collisions occuring after slot time */
++ u32 def_tx; /* Frames deferred due to crs */
++ u32 crs_errors; /* Errors caused by crs not being asserted. */
++ u32 octets_rx_bot; /* Lower 32-bits for number of octets rx'd */
++ u32 octets_rx_top; /* Upper 16-bits for number of octets rx'd */
++ u32 frames_rx; /* Number of frames received OK */
++ u32 broadcast_rx; /* Number of broadcast frames received */
++ u32 multicast_rx; /* Number of multicast frames received */
++ u32 pause_rx; /* Number of pause frames received. */
++ u32 frame64_rx; /* Number of 64byte frames received */
++ u32 frame65_127_rx; /* Number of 65-127 byte frames received */
++ u32 frame128_255_rx; /* Number of 128-255 byte frames received */
++ u32 frame256_511_rx; /* Number of 256-511 byte frames received */
++ u32 frame512_1023_rx; /* Number of 512-1023 byte frames received */
++ u32 frame1024_1518_rx; /* Number of 1024-1518 byte frames received*/
++ u32 frame1519_rx; /* Number of frames greater than 1518 bytes rx*/
++ u32 usize_frames; /* Frames received less than min of 64 bytes */
++ u32 excess_length; /* Number of excessive length frames rx */
++ u32 jabbers; /* Excessive length + crc or align errors. */
++ u32 fcs_errors; /* Number of frames received with crc errors */
++ u32 length_check_errors;/* Number of frames with incorrect length */
++ u32 rx_symbol_errors; /* Number of times rx_er asserted during rx */
++ u32 align_errors; /* Frames received without integer no. bytes */
++ u32 rx_res_errors; /* Number of times buffers ran out during rx */
++ u32 rx_orun; /* Receive overrun errors due to DMA */
++ u32 ip_cksum; /* IP header checksum errors */
++ u32 tcp_cksum; /* TCP checksum errors */
++ u32 udp_cksum; /* UDP checksum errors */
++};
++
++#define EMAC_REG_SPACE sizeof(struct gemac_reg)
++#define EMAC_RMON_LEN (sizeof(struct gemac_stats)/sizeof(u32))
++
++
++struct pfe_eth_fast_timer {
++ int queuenum;
++ struct hrtimer timer;
++ void * base;
++};
++
++typedef struct pfe_eth_priv_s
++{
++ struct pfe *pfe;
++ struct hif_client_s client;
++ struct napi_struct lro_napi;
++ struct napi_struct low_napi;
++ struct napi_struct high_napi;
++ int low_tmuQ;
++ int high_tmuQ;
++ struct net_device_stats stats;
++ struct net_device *dev;
++ int id;
++ int promisc;
++ unsigned int msg_enable;
++ unsigned int usr_features;
++
++ spinlock_t lock;
++ unsigned int event_status;
++ int irq;
++ void* EMAC_baseaddr;
++ void* PHY_baseaddr; /* This points to the EMAC base from where we access PHY */
++ void* GPI_baseaddr;
++ int mdio_muxval;
++ /* PHY stuff */
++ struct phy_device *phydev;
++ int oldspeed;
++ int oldduplex;
++ int oldlink;
++ /* mdio info */
++ int mdc_div;
++ struct mii_bus *mii_bus;
++ struct clk *gemtx_clk;
++ int wol;
++
++ int default_priority;
++ struct timer_list tx_timer;
++ struct pfe_eth_fast_timer fast_tx_timeout[EMAC_TXQ_CNT];
++
++ struct comcerto_eth_platform_data *einfo;
++ struct sk_buff *skb_inflight[EMAC_RXQ_CNT + 6];
++
++#ifdef PFE_ETH_LRO_STATS
++ unsigned int lro_len_counters[LRO_LEN_COUNT_MAX];
++ unsigned int lro_nb_counters[LRO_NB_COUNT_MAX]; //TODO change to exact max number when RX scatter done
++#endif
++
++
++#ifdef PFE_ETH_TX_STATS
++ unsigned int stop_queue_total[EMAC_TXQ_CNT];
++ unsigned int stop_queue_hif[EMAC_TXQ_CNT];
++ unsigned int stop_queue_hif_client[EMAC_TXQ_CNT];
++ unsigned int stop_queue_credit[EMAC_TXQ_CNT];
++ unsigned int clean_fail[EMAC_TXQ_CNT];
++ unsigned int was_stopped[EMAC_TXQ_CNT];
++#endif
++
++#ifdef PFE_ETH_NAPI_STATS
++ unsigned int napi_counters[NAPI_MAX_COUNT];
++#endif
++ unsigned int frags_inflight[EMAC_RXQ_CNT + 6];
++
++}pfe_eth_priv_t;
++
++struct pfe_eth {
++ struct pfe_eth_priv_s *eth_priv[3];
++};
++
++int pfe_eth_init(struct pfe *pfe);
++void pfe_eth_exit(struct pfe *pfe);
++int pfe_eth_suspend(struct net_device *dev);
++int pfe_eth_resume(struct net_device *dev);
++int pfe_eth_mdio_reset(struct mii_bus *bus);
++
++/** pfe_compute_csum
++ *
++ */
++static int inline pfe_compute_csum(struct sk_buff *skb)
++{
++ struct skb_shared_info *sh;
++ unsigned int nr_frags;
++ skb_frag_t *f;
++ u32 csum = 0;
++ int i;
++ int len;
++
++ /* Make sure that no intermediate buffers/fragments are odd byte aligned */
++ if (skb_is_nonlinear(skb)) {
++ int linearize = 0;
++
++ sh = skb_shinfo(skb);
++ nr_frags = sh->nr_frags;
++ len = skb_headlen(skb) - skb_transport_offset(skb);
++
++ if (len & 0x1) {
++ linearize = 1;
++ //printk("#1 Odd length %d\n", len);
++ }
++ else {
++ for (i = 0; i < nr_frags - 1; i++) {
++ f = &sh->frags[i];
++ len = skb_frag_size(f);
++
++ if (len & 0x1) {
++ linearize = 1;
++ //printk("#2 %d Odd length %d\n", i, len);
++ break;
++ }
++ }
++ }
++
++ if (linearize)
++ if (skb_linearize(skb))
++ return -1;
++ }
++
++ /* Compute checksum */
++ if (!skb_is_nonlinear(skb)) {
++ *(u16*)(skb_transport_header(skb) + skb->csum_offset) = csum_fold(csum_partial(skb_transport_header(skb), skb->len - skb_transport_offset(skb), 0));
++ }
++ else {
++ sh = skb_shinfo(skb);
++ nr_frags = sh->nr_frags;
++
++ if (nr_frags) {
++ csum = csum_partial(skb_transport_header(skb), skb_headlen(skb) - skb_transport_offset(skb), 0);
++
++ for (i = 0; i < nr_frags - 1; i++) {
++ f = &sh->frags[i];
++ csum = csum_partial(skb_frag_address(f), skb_frag_size(f), csum);
++ }
++
++ f = &sh->frags[i];
++ *(u16*)(skb_transport_header(skb) + skb->csum_offset) = csum_fold(csum_partial(skb_frag_address(f), skb_frag_size(f), csum));
++ }
++ }
++
++ return 0;
++}
++
++
++
++#endif /* _PFE_ETH_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_firmware.c
+@@ -0,0 +1,322 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++/** @file
++ * Contains all the functions to handle parsing and loading of PE firmware files.
++ */
++#include <linux/firmware.h>
++
++#include "pfe_mod.h"
++#include "pfe_firmware.h"
++#include "pfe/pfe.h"
++
++static Elf32_Shdr * get_elf_section_header(const struct firmware *fw, const char *section)
++{
++ Elf32_Ehdr *elf_hdr = (Elf32_Ehdr *)fw->data;
++ Elf32_Shdr *shdr, *shdr_shstr;
++ Elf32_Off e_shoff = be32_to_cpu(elf_hdr->e_shoff);
++ Elf32_Half e_shentsize = be16_to_cpu(elf_hdr->e_shentsize);
++ Elf32_Half e_shnum = be16_to_cpu(elf_hdr->e_shnum);
++ Elf32_Half e_shstrndx = be16_to_cpu(elf_hdr->e_shstrndx);
++ Elf32_Off shstr_offset;
++ Elf32_Word sh_name;
++ const char *name;
++ int i;
++
++ /* Section header strings */
++ shdr_shstr = (Elf32_Shdr *)(fw->data + e_shoff + e_shstrndx * e_shentsize);
++ shstr_offset = be32_to_cpu(shdr_shstr->sh_offset);
++
++ for (i = 0; i < e_shnum; i++) {
++ shdr = (Elf32_Shdr *)(fw->data + e_shoff + i * e_shentsize);
++
++ sh_name = be32_to_cpu(shdr->sh_name);
++
++ name = (const char *)(fw->data + shstr_offset + sh_name);
++
++ if (!strcmp(name, section))
++ return shdr;
++ }
++
++ printk(KERN_ERR "%s: didn't find section %s\n", __func__, section);
++
++ return NULL;
++}
++
++static unsigned long get_elf_section(const struct firmware *fw, const char *section)
++{
++ Elf32_Shdr *shdr = get_elf_section_header(fw, section);
++
++ if (shdr)
++ return be32_to_cpu(shdr->sh_addr);
++ else
++ return -1;
++}
++
++#if defined(CFG_DIAGS)
++static int pfe_get_diags_info(const struct firmware *fw, struct pfe_diags_info *diags_info)
++{
++ Elf32_Shdr *shdr;
++ unsigned long offset, size;
++
++ shdr = get_elf_section_header(fw, ".pfe_diags_str");
++ if (shdr)
++ {
++ offset = be32_to_cpu(shdr->sh_offset);
++ size = be32_to_cpu(shdr->sh_size);
++ diags_info->diags_str_base = be32_to_cpu(shdr->sh_addr);
++ diags_info->diags_str_size = size;
++ diags_info->diags_str_array = pfe_kmalloc(size, GFP_KERNEL);
++ memcpy(diags_info->diags_str_array, fw->data+offset, size);
++
++ return 0;
++ } else
++ {
++ return -1;
++ }
++}
++#endif
++
++static void pfe_check_version_info(const struct firmware *fw)
++{
++ static char *version = NULL;
++
++ Elf32_Shdr *shdr = get_elf_section_header(fw, ".version");
++
++ if (shdr)
++ {
++ if(!version)
++ {
++ /* this is the first fw we load, use its version string as reference (whatever it is) */
++ version = (char *)(fw->data + be32_to_cpu(shdr->sh_offset));
++
++ printk(KERN_INFO "PFE binary version: %s\n", version);
++ }
++ else
++ {
++ /* already have loaded at least one firmware, check sequence can start now */
++ if(strcmp(version, (char *)(fw->data + be32_to_cpu(shdr->sh_offset))))
++ {
++ printk(KERN_INFO "WARNING: PFE firmware binaries from incompatible version\n");
++ }
++ }
++ }
++ else
++ {
++ /* version cannot be verified, a potential issue that should be reported */
++ printk(KERN_INFO "WARNING: PFE firmware binaries from incompatible version\n");
++ }
++}
++
++/** PFE elf firmware loader.
++* Loads an elf firmware image into a list of PE's (specified using a bitmask)
++*
++* @param pe_mask Mask of PE id's to load firmware to
++* @param fw Pointer to the firmware image
++*
++* @return 0 on sucess, a negative value on error
++*
++*/
++int pfe_load_elf(int pe_mask, const struct firmware *fw, struct pfe *pfe)
++{
++ Elf32_Ehdr *elf_hdr = (Elf32_Ehdr *)fw->data;
++ Elf32_Half sections = be16_to_cpu(elf_hdr->e_shnum);
++ Elf32_Shdr *shdr = (Elf32_Shdr *) (fw->data + be32_to_cpu(elf_hdr->e_shoff));
++ int id, section;
++ int rc;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ /* Some sanity checks */
++ if (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG))
++ {
++ printk(KERN_ERR "%s: incorrect elf magic number\n", __func__);
++ return -EINVAL;
++ }
++
++ if (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32)
++ {
++ printk(KERN_ERR "%s: incorrect elf class(%x)\n", __func__, elf_hdr->e_ident[EI_CLASS]);
++ return -EINVAL;
++ }
++
++ if (elf_hdr->e_ident[EI_DATA] != ELFDATA2MSB)
++ {
++ printk(KERN_ERR "%s: incorrect elf data(%x)\n", __func__, elf_hdr->e_ident[EI_DATA]);
++ return -EINVAL;
++ }
++
++ if (be16_to_cpu(elf_hdr->e_type) != ET_EXEC)
++ {
++ printk(KERN_ERR "%s: incorrect elf file type(%x)\n", __func__, be16_to_cpu(elf_hdr->e_type));
++ return -EINVAL;
++ }
++
++ for (section = 0; section < sections; section++, shdr++)
++ {
++ if (!(be32_to_cpu(shdr->sh_flags) & (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR)))
++ continue;
++
++ for (id = 0; id < MAX_PE; id++)
++ if (pe_mask & (1 << id))
++ {
++ rc = pe_load_elf_section(id, fw->data, shdr, pfe->dev);
++ if (rc < 0)
++ goto err;
++ }
++ }
++
++ pfe_check_version_info(fw);
++
++ return 0;
++
++err:
++ return rc;
++}
++
++
++/** PFE firmware initialization.
++* Loads different firmware files from filesystem.
++* Initializes PE IMEM/DMEM and UTIL-PE DDR
++* Initializes control path symbol addresses (by looking them up in the elf firmware files
++* Takes PE's out of reset
++*
++* @return 0 on sucess, a negative value on error
++*
++*/
++int pfe_firmware_init(struct pfe *pfe)
++{
++ const struct firmware *class_fw, *tmu_fw;
++ int rc = 0;
++#if !defined(CONFIG_UTIL_DISABLED)
++ const char* util_fw_name;
++ const struct firmware *util_fw;
++#endif
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ if (request_firmware(&class_fw, CLASS_FIRMWARE_FILENAME, pfe->dev)) {
++ printk(KERN_ERR "%s: request firmware %s failed\n", __func__, CLASS_FIRMWARE_FILENAME);
++ rc = -ETIMEDOUT;
++ goto err0;
++ }
++
++ if (request_firmware(&tmu_fw, TMU_FIRMWARE_FILENAME, pfe->dev)) {
++ printk(KERN_ERR "%s: request firmware %s failed\n", __func__, TMU_FIRMWARE_FILENAME);
++ rc = -ETIMEDOUT;
++ goto err1;
++ }
++#if !defined(CONFIG_UTIL_DISABLED)
++#if defined(CONFIG_PLATFORM_C2000)
++ util_fw_name = (system_rev == 0) ? UTIL_REVA0_FIRMWARE_FILENAME : UTIL_FIRMWARE_FILENAME;
++#else
++ util_fw_name = UTIL_FIRMWARE_FILENAME;
++#endif
++
++ if (request_firmware(&util_fw, util_fw_name, pfe->dev)) {
++ printk(KERN_ERR "%s: request firmware %s failed\n", __func__, util_fw_name);
++ rc = -ETIMEDOUT;
++ goto err2;
++ }
++#endif
++ rc = pfe_load_elf(CLASS_MASK, class_fw, pfe);
++ if (rc < 0) {
++ printk(KERN_ERR "%s: class firmware load failed\n", __func__);
++ goto err3;
++ }
++
++ pfe->ctrl.class_dmem_sh = get_elf_section(class_fw, ".dmem_sh");
++ pfe->ctrl.class_pe_lmem_sh = get_elf_section(class_fw, ".pe_lmem_sh");
++
++#if defined(CFG_DIAGS)
++ rc = pfe_get_diags_info(class_fw, &pfe->diags.class_diags_info);
++ if (rc < 0) {
++ printk (KERN_WARNING "PFE diags won't be available for class PEs\n");
++ rc = 0;
++ }
++#endif
++
++ printk(KERN_INFO "%s: class firmware loaded %#lx %#lx\n", __func__, pfe->ctrl.class_dmem_sh, pfe->ctrl.class_pe_lmem_sh);
++
++ rc = pfe_load_elf(TMU_MASK, tmu_fw, pfe);
++ if (rc < 0) {
++ printk(KERN_ERR "%s: tmu firmware load failed\n", __func__);
++ goto err3;
++ }
++
++ pfe->ctrl.tmu_dmem_sh = get_elf_section(tmu_fw, ".dmem_sh");
++
++ printk(KERN_INFO "%s: tmu firmware loaded %#lx\n", __func__, pfe->ctrl.tmu_dmem_sh);
++
++#if !defined(CONFIG_UTIL_DISABLED)
++ rc = pfe_load_elf(UTIL_MASK, util_fw, pfe);
++ if (rc < 0) {
++ printk(KERN_ERR "%s: util firmware load failed\n", __func__);
++ goto err3;
++ }
++
++ pfe->ctrl.util_dmem_sh = get_elf_section(util_fw, ".dmem_sh");
++ pfe->ctrl.util_ddr_sh = get_elf_section(util_fw, ".ddr_sh");
++
++#if defined(CFG_DIAGS)
++ rc = pfe_get_diags_info(util_fw, &pfe->diags.util_diags_info);
++ if (rc < 0) {
++ printk(KERN_WARNING "PFE diags won't be available for util PE\n");
++ rc = 0;
++ }
++#endif
++
++ printk(KERN_INFO "%s: util firmware loaded %#lx\n", __func__, pfe->ctrl.util_dmem_sh);
++
++ util_enable();
++#endif
++
++ tmu_enable(0xf);
++ class_enable();
++
++err3:
++#if !defined(CONFIG_UTIL_DISABLED)
++ release_firmware(util_fw);
++
++err2:
++#endif
++ release_firmware(tmu_fw);
++
++err1:
++ release_firmware(class_fw);
++
++err0:
++ return rc;
++}
++
++/** PFE firmware cleanup
++* Puts PE's in reset
++*
++*
++*/
++void pfe_firmware_exit(struct pfe *pfe)
++{
++ printk(KERN_INFO "%s\n", __func__);
++
++ class_disable();
++ tmu_disable(0xf);
++#if !defined(CONFIG_UTIL_DISABLED)
++ util_disable();
++#endif
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_firmware.h
+@@ -0,0 +1,41 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _PFE_FIRMWARE_H_
++#define _PFE_FIRMWARE_H_
++
++#if defined(CONFIG_PLATFORM_C2000)
++#define CLASS_FIRMWARE_FILENAME "class_c2000.elf"
++#define TMU_FIRMWARE_FILENAME "tmu_c2000.elf"
++#define UTIL_FIRMWARE_FILENAME "util_c2000.elf"
++#define UTIL_REVA0_FIRMWARE_FILENAME "util_c2000_revA0.elf"
++#else
++#define CLASS_FIRMWARE_FILENAME "ppfe_class_ls1012a.elf"
++#define TMU_FIRMWARE_FILENAME "ppfe_tmu_ls1012a.elf"
++#endif
++
++#define PFE_FW_CHECK_PASS 0
++#define PFE_FW_CHECK_FAIL 1
++#define NUM_PFE_FW 3
++
++int pfe_firmware_init(struct pfe *pfe);
++void pfe_firmware_exit(struct pfe *pfe);
++
++#endif /* _PFE_FIRMWARE_H_ */
++
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hal.c
+@@ -0,0 +1,2217 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++
++#include "pfe_ctrl_hal.h"
++#include "pfe/pfe.h"
++
++void *cbus_base_addr;
++void *ddr_base_addr;
++unsigned long ddr_phys_base_addr;
++unsigned int ddr_size;
++
++static struct pe_info pe[MAX_PE];
++
++/** Initializes the PFE library.
++* Must be called before using any of the library functions.
++*
++* @param[in] cbus_base CBUS virtual base address (as mapped in the host CPU address space)
++* @param[in] ddr_base PFE DDR range virtual base address (as mapped in the host CPU address space)
++* @param[in] ddr_phys_base PFE DDR range physical base address (as mapped in platform)
++* @param[in] size PFE DDR range size (as defined by the host software)
++*/
++void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base, unsigned int size)
++{
++ cbus_base_addr = cbus_base;
++ ddr_base_addr = ddr_base;
++ ddr_phys_base_addr = ddr_phys_base;
++ ddr_size = size;
++
++ pe[CLASS0_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(0);
++ pe[CLASS0_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(0);
++ pe[CLASS0_ID].pmem_size = CLASS_IMEM_SIZE;
++ pe[CLASS0_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS0_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS0_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++ pe[CLASS1_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(1);
++ pe[CLASS1_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(1);
++ pe[CLASS1_ID].pmem_size = CLASS_IMEM_SIZE;
++ pe[CLASS1_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS1_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS1_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++ pe[CLASS2_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(2);
++ pe[CLASS2_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(2);
++ pe[CLASS2_ID].pmem_size = CLASS_IMEM_SIZE;
++ pe[CLASS2_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS2_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS2_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++ pe[CLASS3_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(3);
++ pe[CLASS3_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(3);
++ pe[CLASS3_ID].pmem_size = CLASS_IMEM_SIZE;
++ pe[CLASS3_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS3_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS3_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++#if !defined(CONFIG_PLATFORM_PCI)
++ pe[CLASS4_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(4);
++ pe[CLASS4_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(4);
++ pe[CLASS4_ID].pmem_size = CLASS_IMEM_SIZE;
++ pe[CLASS4_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS4_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS4_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++ pe[CLASS5_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(5);
++ pe[CLASS5_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(5);
++ pe[CLASS5_ID].pmem_size = CLASS_IMEM_SIZE;
++ pe[CLASS5_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS5_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS5_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++#endif
++ pe[TMU0_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(0);
++ pe[TMU0_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(0);
++ pe[TMU0_ID].pmem_size = TMU_IMEM_SIZE;
++ pe[TMU0_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
++ pe[TMU0_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
++ pe[TMU0_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
++
++#if !defined(CONFIG_TMU_DUMMY)
++ pe[TMU1_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(1);
++ pe[TMU1_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(1);
++ pe[TMU1_ID].pmem_size = TMU_IMEM_SIZE;
++ pe[TMU1_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
++ pe[TMU1_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
++ pe[TMU1_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
++
++#if !defined(CONFIG_PLATFORM_LS1012A)
++ pe[TMU2_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(2);
++ pe[TMU2_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(2);
++ pe[TMU2_ID].pmem_size = TMU_IMEM_SIZE;
++ pe[TMU2_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
++ pe[TMU2_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
++ pe[TMU2_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
++#endif
++
++ pe[TMU3_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(3);
++ pe[TMU3_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(3);
++ pe[TMU3_ID].pmem_size = TMU_IMEM_SIZE;
++ pe[TMU3_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
++ pe[TMU3_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
++ pe[TMU3_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
++#endif
++
++#if !defined(CONFIG_UTIL_DISABLED)
++ pe[UTIL_ID].dmem_base_addr = UTIL_DMEM_BASE_ADDR;
++ pe[UTIL_ID].mem_access_wdata = UTIL_MEM_ACCESS_WDATA;
++ pe[UTIL_ID].mem_access_addr = UTIL_MEM_ACCESS_ADDR;
++ pe[UTIL_ID].mem_access_rdata = UTIL_MEM_ACCESS_RDATA;
++#endif
++}
++
++
++/** Writes a buffer to PE internal memory from the host
++ * through indirect access registers.
++ *
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] src Buffer source address
++ * @param[in] mem_access_addr DMEM destination address (must be 32bit aligned)
++ * @param[in] len Number of bytes to copy
++ */
++void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned int len)
++{
++ u32 offset = 0, val, addr;
++ unsigned int len32 = len >> 2;
++ int i;
++
++ addr = mem_access_addr | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(0, 4);
++
++ for (i = 0; i < len32; i++, offset += 4, src += 4) {
++ val = *(u32 *)src;
++ writel(cpu_to_be32(val), pe[id].mem_access_wdata);
++ writel(addr + offset, pe[id].mem_access_addr);
++ }
++
++ if ((len = (len & 0x3))) {
++ val = 0;
++
++ addr = (mem_access_addr | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset;
++
++ for (i = 0; i < len; i++, src++)
++ val |= (*(u8 *)src) << (8 * i);
++
++ writel(cpu_to_be32(val), pe[id].mem_access_wdata);
++ writel(addr, pe[id].mem_access_addr);
++ }
++}
++
++/** Writes a buffer to PE internal data memory (DMEM) from the host
++ * through indirect access registers.
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] src Buffer source address
++ * @param[in] dst DMEM destination address (must be 32bit aligned)
++ * @param[in] len Number of bytes to copy
++ */
++void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
++{
++ pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst | PE_MEM_ACCESS_DMEM, src, len);
++}
++
++
++/** Writes a buffer to PE internal program memory (PMEM) from the host
++ * through indirect access registers.
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
++ * @param[in] src Buffer source address
++ * @param[in] dst PMEM destination address (must be 32bit aligned)
++ * @param[in] len Number of bytes to copy
++ */
++void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
++{
++ pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size - 1)) | PE_MEM_ACCESS_IMEM, src, len);
++}
++
++
++/** Reads PE internal program memory (IMEM) from the host
++ * through indirect access registers.
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
++ * @param[in] addr PMEM read address (must be aligned on size)
++ * @param[in] size Number of bytes to read (maximum 4, must not cross 32bit boundaries)
++ * @return the data read (in PE endianess, i.e BE).
++ */
++u32 pe_pmem_read(int id, u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++ u32 mask = 0xffffffff >> ((4 - size) << 3);
++ u32 val;
++
++ addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1)) | PE_MEM_ACCESS_IMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++ writel(addr, pe[id].mem_access_addr);
++ val = be32_to_cpu(readl(pe[id].mem_access_rdata));
++
++ return (val >> (offset << 3)) & mask;
++}
++
++
++/** Writes PE internal data memory (DMEM) from the host
++ * through indirect access registers.
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] addr DMEM write address (must be aligned on size)
++ * @param[in] val Value to write (in PE endianess, i.e BE)
++ * @param[in] size Number of bytes to write (maximum 4, must not cross 32bit boundaries)
++ */
++void pe_dmem_write(int id, u32 val, u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++
++ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++ /* Indirect access interface is byte swapping data being written */
++ writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata);
++ writel(addr, pe[id].mem_access_addr);
++}
++
++
++/** Reads PE internal data memory (DMEM) from the host
++ * through indirect access registers.
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] addr DMEM read address (must be aligned on size)
++ * @param[in] size Number of bytes to read (maximum 4, must not cross 32bit boundaries)
++ * @return the data read (in PE endianess, i.e BE).
++ */
++u32 pe_dmem_read(int id, u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++ u32 mask = 0xffffffff >> ((4 - size) << 3);
++ u32 val;
++
++ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++ writel(addr, pe[id].mem_access_addr);
++
++ /* Indirect access interface is byte swapping data being read */
++ val = be32_to_cpu(readl(pe[id].mem_access_rdata));
++
++ return (val >> (offset << 3)) & mask;
++}
++
++
++/** This function is used to write to CLASS internal bus peripherals (ccu, pe-lem) from the host
++* through indirect access registers.
++* @param[in] val value to write
++* @param[in] addr Address to write to (must be aligned on size)
++* @param[in] size Number of bytes to write (1, 2 or 4)
++*
++*/
++void class_bus_write(u32 val, u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++
++ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
++
++ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE | (size << 24);
++
++ writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA);
++ writel(addr, CLASS_BUS_ACCESS_ADDR);
++}
++
++
++/** Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host
++* through indirect access registers.
++* @param[in] addr Address to read from (must be aligned on size)
++* @param[in] size Number of bytes to read (1, 2 or 4)
++* @return the read data
++*
++*/
++u32 class_bus_read(u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++ u32 mask = 0xffffffff >> ((4 - size) << 3);
++ u32 val;
++
++ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
++
++ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24);
++
++ writel(addr, CLASS_BUS_ACCESS_ADDR);
++ val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA));
++
++ return (val >> (offset << 3)) & mask;
++}
++
++
++/** Writes data to the cluster memory (PE_LMEM)
++* @param[in] dst PE LMEM destination address (must be 32bit aligned)
++* @param[in] src Buffer source address
++* @param[in] len Number of bytes to copy
++*/
++void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len)
++{
++ u32 len32 = len >> 2;
++ int i;
++
++ for (i = 0; i < len32; i++, src += 4, dst += 4)
++ class_bus_write(*(u32 *)src, dst, 4);
++
++ if (len & 0x2)
++ {
++ class_bus_write(*(u16 *)src, dst, 2);
++ src += 2;
++ dst += 2;
++ }
++
++ if (len & 0x1)
++ {
++ class_bus_write(*(u8 *)src, dst, 1);
++ src++;
++ dst++;
++ }
++}
++
++/** Writes value to the cluster memory (PE_LMEM)
++* @param[in] dst PE LMEM destination address (must be 32bit aligned)
++* @param[in] val Value to write
++* @param[in] len Number of bytes to write
++*/
++void class_pe_lmem_memset(u32 dst, int val, unsigned int len)
++{
++ u32 len32 = len >> 2;
++ int i;
++
++ val = val | (val << 8) | (val << 16) | (val << 24);
++
++ for (i = 0; i < len32; i++, dst += 4)
++ class_bus_write(val, dst, 4);
++
++ if (len & 0x2)
++ {
++ class_bus_write(val, dst, 2);
++ dst += 2;
++ }
++
++ if (len & 0x1)
++ {
++ class_bus_write(val, dst, 1);
++ dst++;
++ }
++}
++
++#if !defined(CONFIG_UTIL_DISABLED)
++
++/** Writes UTIL program memory (DDR) from the host.
++ *
++ * @param[in] addr Address to write (virtual, must be aligned on size)
++ * @param[in] val Value to write (in PE endianess, i.e BE)
++ * @param[in] size Number of bytes to write (2 or 4)
++ */
++static void util_pmem_write(u32 val, void *addr, u8 size)
++{
++ void *addr64 = (void *)((unsigned long)addr & ~0x7);
++ unsigned long off = 8 - ((unsigned long)addr & 0x7) - size;
++
++ //IMEM should be loaded as a 64bit swapped value in a 64bit aligned location
++ if (size == 4)
++ writel(be32_to_cpu(val), addr64 + off);
++ else
++ writew(be16_to_cpu((u16)val), addr64 + off);
++}
++
++
++/** Writes a buffer to UTIL program memory (DDR) from the host.
++ *
++ * @param[in] dst Address to write (virtual, must be at least 16bit aligned)
++ * @param[in] src Buffer to write (in PE endianess, i.e BE, must have same alignment as dst)
++ * @param[in] len Number of bytes to write (must be at least 16bit aligned)
++ */
++static void util_pmem_memcpy(void *dst, const void *src, unsigned int len)
++{
++ unsigned int len32;
++ int i;
++
++ if ((unsigned long)src & 0x2) {
++ util_pmem_write(*(u16 *)src, dst, 2);
++ src += 2;
++ dst += 2;
++ len -= 2;
++ }
++
++ len32 = len >> 2;
++
++ for (i = 0; i < len32; i++, dst += 4, src += 4)
++ util_pmem_write(*(u32 *)src, dst, 4);
++
++ if (len & 0x2)
++ util_pmem_write(*(u16 *)src, dst, len & 0x2);
++}
++#endif
++
++/** Loads an elf section into pmem
++ * Code needs to be at least 16bit aligned and only PROGBITS sections are supported
++ *
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
++ * @param[in] data pointer to the elf firmware
++ * @param[in] shdr pointer to the elf section header
++ *
++ */
++static int pe_load_pmem_section(int id, const void *data, Elf32_Shdr *shdr)
++{
++ u32 offset = be32_to_cpu(shdr->sh_offset);
++ u32 addr = be32_to_cpu(shdr->sh_addr);
++ u32 size = be32_to_cpu(shdr->sh_size);
++ u32 type = be32_to_cpu(shdr->sh_type);
++
++#if !defined(CONFIG_UTIL_DISABLED)
++ if (id == UTIL_ID)
++ {
++ printk(KERN_ERR "%s: unsuported pmem section for UTIL\n", __func__);
++ return -EINVAL;
++ }
++#endif
++
++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
++ {
++ printk(KERN_ERR "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
++ __func__, addr, (unsigned long) data + offset);
++
++ return -EINVAL;
++ }
++
++ if (addr & 0x1)
++ {
++ printk(KERN_ERR "%s: load address(%x) is not 16bit aligned\n", __func__, addr);
++ return -EINVAL;
++ }
++
++ if (size & 0x1)
++ {
++ printk(KERN_ERR "%s: load size(%x) is not 16bit aligned\n", __func__, size);
++ return -EINVAL;
++ }
++
++ switch (type)
++ {
++ case SHT_PROGBITS:
++ pe_pmem_memcpy_to32(id, addr, data + offset, size);
++
++ break;
++
++ default:
++ printk(KERN_ERR "%s: unsuported section type(%x)\n", __func__, type);
++ return -EINVAL;
++ break;
++ }
++
++ return 0;
++}
++
++
++/** Loads an elf section into dmem
++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0
++ *
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] data pointer to the elf firmware
++ * @param[in] shdr pointer to the elf section header
++ *
++ */
++static int pe_load_dmem_section(int id, const void *data, Elf32_Shdr *shdr)
++{
++ u32 offset = be32_to_cpu(shdr->sh_offset);
++ u32 addr = be32_to_cpu(shdr->sh_addr);
++ u32 size = be32_to_cpu(shdr->sh_size);
++ u32 type = be32_to_cpu(shdr->sh_type);
++ u32 size32 = size >> 2;
++ int i;
++
++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
++ {
++ printk(KERN_ERR "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
++ __func__, addr, (unsigned long)data + offset);
++
++ return -EINVAL;
++ }
++
++ if (addr & 0x3)
++ {
++ printk(KERN_ERR "%s: load address(%x) is not 32bit aligned\n", __func__, addr);
++ return -EINVAL;
++ }
++
++ switch (type)
++ {
++ case SHT_PROGBITS:
++ pe_dmem_memcpy_to32(id, addr, data + offset, size);
++ break;
++
++ case SHT_NOBITS:
++ for (i = 0; i < size32; i++, addr += 4)
++ pe_dmem_write(id, 0, addr, 4);
++
++ if (size & 0x3)
++ pe_dmem_write(id, 0, addr, size & 0x3);
++
++ break;
++
++ default:
++ printk(KERN_ERR "%s: unsuported section type(%x)\n", __func__, type);
++ return -EINVAL;
++ break;
++ }
++
++ return 0;
++}
++
++
++/** Loads an elf section into DDR
++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0
++ *
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] data pointer to the elf firmware
++ * @param[in] shdr pointer to the elf section header
++ *
++ */
++static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr, struct device *dev)
++{
++ u32 offset = be32_to_cpu(shdr->sh_offset);
++ u32 addr = be32_to_cpu(shdr->sh_addr);
++ u32 size = be32_to_cpu(shdr->sh_size);
++ u32 type = be32_to_cpu(shdr->sh_type);
++ u32 flags = be32_to_cpu(shdr->sh_flags);
++
++ switch (type)
++ {
++ case SHT_PROGBITS:
++ if (flags & SHF_EXECINSTR)
++ {
++ if (id <= CLASS_MAX_ID)
++ {
++ /* DO the loading only once in DDR */
++ if (id == CLASS0_ID)
++ {
++ printk(KERN_ERR "%s: load address(%x) and elf file address(%lx) rcvd\n", __func__, addr, (unsigned long)data + offset);
++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
++ {
++ printk(KERN_ERR "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
++ __func__, addr, (unsigned long)data + offset);
++
++ return -EINVAL;
++ }
++
++ if (addr & 0x1)
++ {
++ printk(KERN_ERR "%s: load address(%x) is not 16bit aligned\n", __func__, addr);
++ return -EINVAL;
++ }
++
++ if (size & 0x1)
++ {
++ printk(KERN_ERR "%s: load length(%x) is not 16bit aligned\n", __func__, size);
++ return -EINVAL;
++ }
++ memcpy(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), data + offset, size);
++ }
++ }
++#if !defined(CONFIG_UTIL_DISABLED)
++ else if (id == UTIL_ID)
++ {
++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
++ {
++ printk(KERN_ERR "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
++ __func__, addr, (unsigned long)data + offset);
++
++ return -EINVAL;
++ }
++
++ if (addr & 0x1)
++ {
++ printk(KERN_ERR "%s: load address(%x) is not 16bit aligned\n", __func__, addr);
++ return -EINVAL;
++ }
++
++ if (size & 0x1)
++ {
++ printk(KERN_ERR "%s: load length(%x) is not 16bit aligned\n", __func__, size);
++ return -EINVAL;
++ }
++
++ util_pmem_memcpy(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), data + offset, size);
++ }
++#endif
++ else
++ {
++ printk(KERN_ERR "%s: unsuported ddr section type(%x) for PE(%d)\n", __func__, type, id);
++ return -EINVAL;
++ }
++
++ }
++ else
++ {
++ memcpy(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), data + offset, size);
++ }
++
++ break;
++
++ case SHT_NOBITS:
++ memset(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), 0, size);
++
++ break;
++
++ default:
++ printk(KERN_ERR "%s: unsuported section type(%x)\n", __func__, type);
++ return -EINVAL;
++ break;
++ }
++
++ return 0;
++}
++
++
++/** Loads an elf section into pe lmem
++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0
++ *
++ * @param[in] id PE identification (CLASS0_ID,..., CLASS5_ID)
++ * @param[in] data pointer to the elf firmware
++ * @param[in] shdr pointer to the elf section header
++ *
++ */
++static int pe_load_pe_lmem_section(int id, const void *data, Elf32_Shdr *shdr)
++{
++ u32 offset = be32_to_cpu(shdr->sh_offset);
++ u32 addr = be32_to_cpu(shdr->sh_addr);
++ u32 size = be32_to_cpu(shdr->sh_size);
++ u32 type = be32_to_cpu(shdr->sh_type);
++
++ if (id > CLASS_MAX_ID)
++ {
++ printk(KERN_ERR "%s: unsuported pe-lmem section type(%x) for PE(%d)\n", __func__, type, id);
++ return -EINVAL;
++ }
++
++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
++ {
++ printk(KERN_ERR "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
++ __func__, addr, (unsigned long)data + offset);
++
++ return -EINVAL;
++ }
++
++ if (addr & 0x3)
++ {
++ printk(KERN_ERR "%s: load address(%x) is not 32bit aligned\n", __func__, addr);
++ return -EINVAL;
++ }
++
++ switch (type)
++ {
++ case SHT_PROGBITS:
++ class_pe_lmem_memcpy_to32(addr, data + offset, size);
++ break;
++
++ case SHT_NOBITS:
++ class_pe_lmem_memset(addr, 0, size);
++ break;
++
++ default:
++ printk(KERN_ERR "%s: unsuported section type(%x)\n", __func__, type);
++ return -EINVAL;
++ break;
++ }
++
++ return 0;
++}
++
++
++/** Loads an elf section into a PE
++ * For now only supports loading a section to dmem (all PE's), pmem (class and tmu PE's),
++ * DDDR (util PE code)
++ *
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
++ * @param[in] data pointer to the elf firmware
++ * @param[in] shdr pointer to the elf section header
++ *
++ */
++int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr, struct device *dev)
++{
++ u32 addr = be32_to_cpu(shdr->sh_addr);
++ u32 size = be32_to_cpu(shdr->sh_size);
++
++ if (IS_DMEM(addr, size))
++ return pe_load_dmem_section(id, data, shdr);
++ else if (IS_PMEM(addr, size))
++ return pe_load_pmem_section(id, data, shdr);
++ else if (IS_PFE_LMEM(addr, size))
++ return 0; /* FIXME */
++ else if (IS_PHYS_DDR(addr, size))
++ return pe_load_ddr_section(id, data, shdr, dev);
++ else if (IS_PE_LMEM(addr, size))
++ return pe_load_pe_lmem_section(id, data, shdr);
++ else {
++ printk(KERN_ERR "%s: unsuported memory range(%x)\n", __func__, addr);
++// return -EINVAL;
++ }
++
++ return 0;
++}
++
++
++/**************************** BMU ***************************/
++
++/** Initializes a BMU block.
++* @param[in] base BMU block base address
++* @param[in] cfg BMU configuration
++*/
++void bmu_init(void *base, BMU_CFG *cfg)
++{
++ bmu_disable(base);
++
++ bmu_set_config(base, cfg);
++
++ bmu_reset(base);
++}
++
++/** Resets a BMU block.
++* @param[in] base BMU block base address
++*/
++void bmu_reset(void *base)
++{
++ writel(CORE_SW_RESET, base + BMU_CTRL);
++
++ /* Wait for self clear */
++ while (readl(base + BMU_CTRL) & CORE_SW_RESET) ;
++}
++
++/** Enabled a BMU block.
++* @param[in] base BMU block base address
++*/
++void bmu_enable(void *base)
++{
++ writel (CORE_ENABLE, base + BMU_CTRL);
++}
++
++/** Disables a BMU block.
++* @param[in] base BMU block base address
++*/
++void bmu_disable(void *base)
++{
++ writel (CORE_DISABLE, base + BMU_CTRL);
++}
++
++/** Sets the configuration of a BMU block.
++* @param[in] base BMU block base address
++* @param[in] cfg BMU configuration
++*/
++void bmu_set_config(void *base, BMU_CFG *cfg)
++{
++ writel (cfg->baseaddr, base + BMU_UCAST_BASE_ADDR);
++ writel (cfg->count & 0xffff, base + BMU_UCAST_CONFIG);
++ writel (cfg->size & 0xffff, base + BMU_BUF_SIZE);
++// writel (BMU1_THRES_CNT, base + BMU_THRES);
++
++ /* Interrupts are never used */
++// writel (0x0, base + BMU_INT_SRC);
++ writel (0x0, base + BMU_INT_ENABLE);
++}
++#if defined(CONFIG_PLATFORM_C2000)
++/**************************** GEMAC ***************************/
++
++/** Enable Rx Checksum Engine. With this enabled, Frame with bad IP,
++ * TCP or UDP checksums are discarded
++ *
++ * @param[in] base GEMAC base address.
++ */
++void gemac_enable_rx_checksum_offload(void *base)
++{
++ writel(readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_CHKSUM_RX, base + EMAC_NETWORK_CONFIG);
++ writel(readl(CLASS_L4_CHKSUM_ADDR) | IPV4_CHKSUM_DROP, CLASS_L4_CHKSUM_ADDR);
++}
++
++/** Disable Rx Checksum Engine.
++ *
++ * @param[in] base GEMAC base address.
++ */
++void gemac_disable_rx_checksum_offload(void *base)
++{
++ writel(readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_CHKSUM_RX, base + EMAC_NETWORK_CONFIG);
++ writel(readl(CLASS_L4_CHKSUM_ADDR) & ~IPV4_CHKSUM_DROP, CLASS_L4_CHKSUM_ADDR);
++}
++
++/** Setup the MII Mgmt clock speed.
++ * @param[in] base GEMAC base address (GEMAC0, GEMAC1, GEMAC2)
++ * @param[in] mdc_div MII clock dividor
++ */
++void gemac_set_mdc_div(void *base, int mdc_div)
++{
++ u32 val = readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_MDC_DIV_MASK;
++ u32 div;
++
++ switch (mdc_div) {
++ case 8:
++ div = 0;
++ break;
++
++ case 16:
++ div = 1;
++ break;
++
++ case 32:
++ div = 2;
++ break;
++
++ case 48:
++ div = 3;
++ break;
++
++ default:
++ case 64:
++ div = 4;
++ break;
++
++ case 96:
++ div = 5;
++ break;
++
++ case 128:
++ div = 6;
++ break;
++
++ case 224:
++ div = 7;
++ break;
++ }
++
++ val |= div << 18;
++
++ writel(val, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC set speed.
++* @param[in] base GEMAC base address
++* @param[in] speed GEMAC speed (10, 100 or 1000 Mbps)
++*/
++void gemac_set_speed(void *base, MAC_SPEED gem_speed)
++{
++ u32 val = readl(base + EMAC_NETWORK_CONFIG);
++
++ val = val & ~EMAC_SPEED_MASK;
++
++ switch (gem_speed)
++ {
++ case SPEED_10M:
++ val &= (~EMAC_PCS_ENABLE);
++ break;
++
++ case SPEED_100M:
++ val = val | EMAC_SPEED_100;
++ val &= (~EMAC_PCS_ENABLE);
++ break;
++
++ case SPEED_1000M:
++ val = val | EMAC_SPEED_1000;
++ val &= (~EMAC_PCS_ENABLE);
++ break;
++
++ case SPEED_1000M_PCS:
++ val = val | EMAC_SPEED_1000;
++ val |= EMAC_PCS_ENABLE;
++ break;
++
++ default:
++ val = val | EMAC_SPEED_100;
++ val &= (~EMAC_PCS_ENABLE);
++ break;
++ }
++
++ writel (val, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC set duplex.
++* @param[in] base GEMAC base address
++* @param[in] duplex GEMAC duplex mode (Full, Half)
++*/
++void gemac_set_duplex(void *base, int duplex)
++{
++ u32 val = readl(base + EMAC_NETWORK_CONFIG);
++
++ if (duplex == DUPLEX_HALF)
++ val = (val & ~EMAC_DUPLEX_MASK) | EMAC_HALF_DUP;
++ else
++ val = (val & ~EMAC_DUPLEX_MASK) | EMAC_FULL_DUP;
++
++ writel (val, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC set mode.
++* @param[in] base GEMAC base address
++* @param[in] mode GEMAC operation mode (MII, RMII, RGMII, SGMII)
++*/
++
++#if defined(CONFIG_IP_ALIGNED)
++#define IP_ALIGNED_BITVAL EMAC_TWO_BYTES_IP_ALIGN
++#else
++#define IP_ALIGNED_BITVAL 0
++#endif
++
++void gemac_set_mode(void *base, int mode)
++{
++ switch (mode)
++ {
++ case GMII:
++ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_GMII_MODE_ENABLE | IP_ALIGNED_BITVAL, base + EMAC_CONTROL);
++ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
++ break;
++
++ case RGMII:
++ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_RGMII_MODE_ENABLE | IP_ALIGNED_BITVAL, base + EMAC_CONTROL);
++ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
++ break;
++
++ case RMII:
++ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_RMII_MODE_ENABLE | IP_ALIGNED_BITVAL, base + EMAC_CONTROL);
++ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
++ break;
++
++ case MII:
++ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_MII_MODE_ENABLE | IP_ALIGNED_BITVAL, base + EMAC_CONTROL);
++ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
++ break;
++
++ case SGMII:
++ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | (EMAC_RMII_MODE_DISABLE | EMAC_RGMII_MODE_DISABLE) | IP_ALIGNED_BITVAL, base + EMAC_CONTROL);
++ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_SGMII_MODE_ENABLE, base + EMAC_NETWORK_CONFIG);
++ break;
++
++ default:
++ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_MII_MODE_ENABLE | IP_ALIGNED_BITVAL, base + EMAC_CONTROL);
++ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
++ break;
++ }
++}
++/** GEMAC Enable MDIO: Activate the Management interface. This is required to program the PHY
++ * @param[in] base GEMAC base address
++ */
++void gemac_enable_mdio(void *base)
++{
++ u32 data;
++
++ data = readl(base + EMAC_NETWORK_CONTROL);
++ data |= EMAC_MDIO_EN;
++ writel(data, base + EMAC_NETWORK_CONTROL);
++}
++
++/** GEMAC Disable MDIO: Disable the Management interface.
++ * @param[in] base GEMAC base address
++ */
++void gemac_disable_mdio(void *base)
++{
++ u32 data;
++
++ data = readl(base + EMAC_NETWORK_CONTROL);
++ data &= ~EMAC_MDIO_EN;
++ writel(data, base + EMAC_NETWORK_CONTROL);
++}
++
++
++/** GEMAC reset function.
++* @param[in] base GEMAC base address
++*/
++void gemac_reset(void *base)
++{
++}
++
++/** GEMAC enable function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONTROL) | EMAC_TX_ENABLE | EMAC_RX_ENABLE, base + EMAC_NETWORK_CONTROL);
++}
++
++/** GEMAC disable function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONTROL) & ~(EMAC_TX_ENABLE | EMAC_RX_ENABLE), base + EMAC_NETWORK_CONTROL);
++}
++
++/** GEMAC TX disable function.
++* @param[in] base GEMAC base address
++*/
++void gemac_tx_disable(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONTROL) & ~(EMAC_TX_ENABLE), base + EMAC_NETWORK_CONTROL);
++}
++
++/** GEMAC set mac address configuration.
++* @param[in] base GEMAC base address
++* @param[in] addr MAC address to be configured
++*/
++void gemac_set_address(void *base, SPEC_ADDR *addr)
++{
++ writel(addr->one.bottom, base + EMAC_SPEC1_ADD_BOT);
++ writel(addr->one.top, base + EMAC_SPEC1_ADD_TOP);
++ writel(addr->two.bottom, base + EMAC_SPEC2_ADD_BOT);
++ writel(addr->two.top, base + EMAC_SPEC2_ADD_TOP);
++ writel(addr->three.bottom, base + EMAC_SPEC3_ADD_BOT);
++ writel(addr->three.top, base + EMAC_SPEC3_ADD_TOP);
++ writel(addr->four.bottom, base + EMAC_SPEC4_ADD_BOT);
++ writel(addr->four.top, base + EMAC_SPEC4_ADD_TOP);
++}
++
++/** GEMAC get mac address configuration.
++* @param[in] base GEMAC base address
++*
++* @return MAC addresses configured
++*/
++SPEC_ADDR gemac_get_address(void *base)
++{
++ SPEC_ADDR addr;
++
++ addr.one.bottom = readl(base + EMAC_SPEC1_ADD_BOT);
++ addr.one.top = readl(base + EMAC_SPEC1_ADD_TOP);
++ addr.two.bottom = readl(base + EMAC_SPEC2_ADD_BOT);
++ addr.two.top = readl(base + EMAC_SPEC2_ADD_TOP);
++ addr.three.bottom = readl(base + EMAC_SPEC3_ADD_BOT);
++ addr.three.top = readl(base + EMAC_SPEC3_ADD_TOP);
++ addr.four.bottom = readl(base + EMAC_SPEC4_ADD_BOT);
++ addr.four.top = readl(base + EMAC_SPEC4_ADD_TOP);
++
++ return addr;
++}
++
++/** Sets the hash register of the MAC.
++ * This register is used for matching unicast and multicast frames.
++ *
++ * @param[in] base GEMAC base address.
++ * @param[in] hash 64-bit hash to be configured.
++ */
++void gemac_set_hash( void *base, MAC_ADDR *hash )
++{
++ writel(hash->bottom, base + EMAC_HASH_BOT);
++ writel(hash->top, base + EMAC_HASH_TOP);
++}
++
++/** Get the current value hash register of the MAC.
++ * This register is used for matching unicast and multicast frames.
++ *
++ * @param[in] base GEMAC base address
++
++ * @returns 64-bit hash.
++ */
++MAC_ADDR gemac_get_hash( void *base )
++{
++ MAC_ADDR hash;
++
++ hash.bottom = readl(base + EMAC_HASH_BOT);
++ hash.top = readl(base + EMAC_HASH_TOP);
++
++ return hash;
++}
++
++/** GEMAC set specific local addresses of the MAC.
++* Rather than setting up all four specific addresses, this function sets them up individually.
++*
++* @param[in] base GEMAC base address
++* @param[in] addr MAC address to be configured
++*/
++void gemac_set_laddr1(void *base, MAC_ADDR *address)
++{
++ writel(address->bottom, base + EMAC_SPEC1_ADD_BOT);
++ writel(address->top, base + EMAC_SPEC1_ADD_TOP);
++}
++
++
++void gemac_set_laddr2(void *base, MAC_ADDR *address)
++{
++ writel(address->bottom, base + EMAC_SPEC2_ADD_BOT);
++ writel(address->top, base + EMAC_SPEC2_ADD_TOP);
++}
++
++
++void gemac_set_laddr3(void *base, MAC_ADDR *address)
++{
++ writel(address->bottom, base + EMAC_SPEC3_ADD_BOT);
++ writel(address->top, base + EMAC_SPEC3_ADD_TOP);
++}
++
++
++void gemac_set_laddr4(void *base, MAC_ADDR *address)
++{
++ writel(address->bottom, base + EMAC_SPEC4_ADD_BOT);
++ writel(address->top, base + EMAC_SPEC4_ADD_TOP);
++}
++
++void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index)
++{
++ if( (entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX) )
++ return;
++
++ entry_index = entry_index - 1;
++
++ if (entry_index < 4)
++ {
++ writel(address->bottom, base + (entry_index * 8) + EMAC_SPEC1_ADD_BOT);
++ writel(address->top, base + (entry_index * 8) + EMAC_SPEC1_ADD_TOP);
++ }
++ else
++ {
++ writel(address->bottom, base + ((entry_index - 4) * 8) + EMAC_SPEC5_ADD_BOT);
++ writel(address->top, base + ((entry_index - 4) * 8) + EMAC_SPEC5_ADD_TOP);
++ }
++}
++
++/** Get specific local addresses of the MAC.
++* This allows returning of a single specific address stored in the MAC.
++* @param[in] base GEMAC base address
++*
++* @return Specific MAC address 1
++*
++*/
++MAC_ADDR gem_get_laddr1(void *base)
++{
++ MAC_ADDR addr;
++ addr.bottom = readl(base + EMAC_SPEC1_ADD_BOT);
++ addr.top = readl(base + EMAC_SPEC1_ADD_TOP);
++ return addr;
++}
++
++
++MAC_ADDR gem_get_laddr2(void *base)
++{
++ MAC_ADDR addr;
++ addr.bottom = readl(base + EMAC_SPEC2_ADD_BOT);
++ addr.top = readl(base + EMAC_SPEC2_ADD_TOP);
++ return addr;
++}
++
++
++MAC_ADDR gem_get_laddr3(void *base)
++{
++ MAC_ADDR addr;
++ addr.bottom = readl(base + EMAC_SPEC3_ADD_BOT);
++ addr.top = readl(base + EMAC_SPEC3_ADD_TOP);
++ return addr;
++}
++
++
++MAC_ADDR gem_get_laddr4(void *base)
++{
++ MAC_ADDR addr;
++ addr.bottom = readl(base + EMAC_SPEC4_ADD_BOT);
++ addr.top = readl(base + EMAC_SPEC4_ADD_TOP);
++ return addr;
++}
++
++MAC_ADDR gem_get_laddrN(void *base, unsigned int entry_index)
++{
++ MAC_ADDR addr = {0xffffffff, 0xffffffff};
++
++ if( (entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX) )
++ return addr;
++
++ entry_index = entry_index - 1;
++
++ if (entry_index < 4)
++ {
++ addr.bottom = readl(base + (entry_index * 8) + EMAC_SPEC1_ADD_BOT);
++ addr.top = readl(base + (entry_index * 8) + EMAC_SPEC1_ADD_TOP);
++ }
++ else
++ {
++ addr.bottom = readl(base + ((entry_index - 4) * 8) + EMAC_SPEC5_ADD_BOT);
++ addr.top = readl(base + ((entry_index - 4) * 8) + EMAC_SPEC5_ADD_TOP);
++ }
++
++ return addr;
++}
++
++/** Clear specific local addresses of the MAC.
++ * @param[in] base GEMAC base address
++ */
++
++void gemac_clear_laddr1(void *base)
++{
++ writel(0, base + EMAC_SPEC1_ADD_BOT);
++}
++
++void gemac_clear_laddr2(void *base)
++{
++ writel(0, base + EMAC_SPEC2_ADD_BOT);
++}
++
++void gemac_clear_laddr3(void *base)
++{
++ writel(0, base + EMAC_SPEC3_ADD_BOT);
++}
++
++void gemac_clear_laddr4(void *base)
++{
++ writel(0, base + EMAC_SPEC4_ADD_BOT);
++}
++
++void gemac_clear_laddrN(void *base, unsigned int entry_index)
++{
++ if( (entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX) )
++ return;
++
++ entry_index = entry_index - 1;
++
++ if ( entry_index < 4 )
++ writel(0, base + (entry_index * 8) + EMAC_SPEC1_ADD_BOT);
++ else
++ writel(0, base + ((entry_index - 4) * 8) + EMAC_SPEC5_ADD_BOT);
++}
++
++/** Set the loopback mode of the MAC. This can be either no loopback for normal
++ * operation, local loopback through MAC internal loopback module or PHY
++ * loopback for external loopback through a PHY. This asserts the external loop
++ * pin.
++ *
++ * @param[in] base GEMAC base address.
++ * @param[in] gem_loop Loopback mode to be enabled. LB_LOCAL - MAC Loopback,
++ * LB_EXT - PHY Loopback.
++ */
++void gemac_set_loop( void *base, MAC_LOOP gem_loop )
++{
++ switch (gem_loop) {
++ case LB_LOCAL:
++ writel(readl(base + EMAC_NETWORK_CONTROL) & (~EMAC_LB_PHY),
++ base + EMAC_NETWORK_CONTROL);
++ writel(readl(base + EMAC_NETWORK_CONTROL) | (EMAC_LB_MAC),
++ base + EMAC_NETWORK_CONTROL);
++ break;
++ case LB_EXT:
++ writel(readl(base + EMAC_NETWORK_CONTROL) & (~EMAC_LB_MAC),
++ base + EMAC_NETWORK_CONTROL);
++ writel(readl(base + EMAC_NETWORK_CONTROL) | (EMAC_LB_PHY),
++ base + EMAC_NETWORK_CONTROL);
++ break;
++ default:
++ writel(readl(base + EMAC_NETWORK_CONTROL) & (~(EMAC_LB_MAC | EMAC_LB_PHY)),
++ base + EMAC_NETWORK_CONTROL);
++ }
++}
++
++/** GEMAC allow frames
++ * @param[in] base GEMAC base address
++ */
++void gemac_enable_copy_all(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_COPY_ALL, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC do not allow frames
++ * @param[in] base GEMAC base address
++*/
++void gemac_disable_copy_all(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_COPY_ALL, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC allow broadcast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_allow_broadcast(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_NO_BROADCAST, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC no broadcast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_no_broadcast(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_NO_BROADCAST, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC enable unicast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_unicast(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_UNICAST, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC disable unicast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_unicast(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_UNICAST, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC enable multicast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_multicast(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_MULTICAST, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC disable multicast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_multicast(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_MULTICAST, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC enable fcs rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_fcs_rx(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_FCS_RX, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC disable fcs rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_fcs_rx(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_FCS_RX, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC enable 1536 rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_1536_rx(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_1536_RX, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC disable 1536 rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_1536_rx(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_1536_RX, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC enable jumbo function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_rx_jmb(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_JUMBO_FRAME, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC disable jumbo function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_rx_jmb(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_JUMBO_FRAME, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC enable stacked vlan function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_stacked_vlan(void *base)
++{
++ writel (readl(base + EMAC_STACKED_VLAN_REG) | EMAC_ENABLE_STACKED_VLAN, base + EMAC_STACKED_VLAN_REG);
++}
++
++/** GEMAC enable stacked vlan function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_stacked_vlan(void *base)
++{
++ writel (readl(base + EMAC_STACKED_VLAN_REG) & ~EMAC_ENABLE_STACKED_VLAN, base + EMAC_STACKED_VLAN_REG);
++}
++
++/** GEMAC enable pause rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_pause_rx(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_PAUSE_RX, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC disable pause rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_pause_rx(void *base)
++{
++ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_PAUSE_RX, base + EMAC_NETWORK_CONFIG);
++}
++
++/** GEMAC wol configuration
++* @param[in] base GEMAC base address
++* @param[in] wol_conf WoL register configuration
++*/
++void gemac_set_wol(void *base, u32 wol_conf)
++{
++ writel(wol_conf, base + EMAC_WOL);
++}
++
++/** Sets Gemac bus width to 64bit
++ * @param[in] base GEMAC base address
++ * @param[in] width gemac bus width to be set possible values are 32/64/128
++ * */
++void gemac_set_bus_width(void *base, int width)
++{
++ u32 val = readl(base + EMAC_NETWORK_CONFIG);
++ switch(width)
++ {
++ case 32:
++ val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_32;
++ case 128:
++ val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_128;
++ case 64:
++ default:
++ val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_64;
++
++ }
++ writel (val, base + EMAC_NETWORK_CONFIG);
++}
++
++/** Sets Gemac configuration.
++* @param[in] base GEMAC base address
++* @param[in] cfg GEMAC configuration
++*/
++void gemac_set_config(void *base, GEMAC_CFG *cfg)
++{
++ gemac_set_mode(base, cfg->mode);
++
++ gemac_set_speed(base, cfg->speed);
++
++ gemac_set_duplex(base,cfg->duplex);
++}
++#elif defined(CONFIG_PLATFORM_LS1012A)
++/**************************** MTIP GEMAC ***************************/
++
++/** Enable Rx Checksum Engine. With this enabled, Frame with bad IP,
++ * TCP or UDP checksums are discarded
++ *
++ * @param[in] base GEMAC base address.
++ */
++void gemac_enable_rx_checksum_offload(void *base)
++{
++ /*Do not find configuration to do this */
++}
++
++/** Disable Rx Checksum Engine.
++ *
++ * @param[in] base GEMAC base address.
++ */
++void gemac_disable_rx_checksum_offload(void *base)
++{
++ /*Do not find configuration to do this */
++}
++
++/** GEMAC set speed.
++* @param[in] base GEMAC base address
++* @param[in] speed GEMAC speed (10, 100 or 1000 Mbps)
++*/
++void gemac_set_speed(void *base, MAC_SPEED gem_speed)
++{
++ u32 ecr = readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
++ u32 rcr = readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
++
++ switch (gem_speed)
++ {
++ case SPEED_10M:
++ rcr |= EMAC_RCNTRL_RMII_10T;
++ break;
++
++
++ case SPEED_1000M:
++ ecr |= EMAC_ECNTRL_SPEED;
++ break;
++
++ case SPEED_100M:
++ default:
++ /*It is in 100M mode */
++ break;
++ }
++ writel(ecr, (base + EMAC_ECNTRL_REG));
++ writel(rcr, (base + EMAC_RCNTRL_REG));
++}
++
++/** GEMAC set duplex.
++* @param[in] base GEMAC base address
++* @param[in] duplex GEMAC duplex mode (Full, Half)
++*/
++void gemac_set_duplex(void *base, int duplex)
++{
++
++ if (duplex == DUPLEX_HALF) {
++ printk("%s() TODO\n", __func__);
++ writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_FDEN, base + EMAC_TCNTRL_REG);
++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_DRT, (base + EMAC_RCNTRL_REG));
++ }else{
++ writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN, base + EMAC_TCNTRL_REG);
++ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_DRT, (base + EMAC_RCNTRL_REG));
++ }
++}
++
++/** GEMAC set mode.
++* @param[in] base GEMAC base address
++* @param[in] mode GEMAC operation mode (MII, RMII, RGMII, SGMII)
++*/
++void gemac_set_mode(void *base, int mode)
++{
++ u32 val = readl(base + EMAC_RCNTRL_REG);
++
++ /*Remove loopbank*/
++ val &= ~EMAC_RCNTRL_LOOP;
++
++ /*Enable flow control and MII mode*/
++ val |= (EMAC_RCNTRL_FCE | EMAC_RCNTRL_MII_MODE);
++
++ writel(val, base + EMAC_RCNTRL_REG);
++}
++
++/** GEMAC enable function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable(void *base)
++{
++ writel(readl(base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, base + EMAC_ECNTRL_REG);
++}
++
++/** GEMAC disable function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable(void *base)
++{
++ writel(readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, base + EMAC_ECNTRL_REG);
++}
++
++/** GEMAC TX disable function.
++* @param[in] base GEMAC base address
++*/
++void gemac_tx_disable(void *base)
++{
++ writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_GTS, base + EMAC_TCNTRL_REG);
++}
++
++/** Sets the hash register of the MAC.
++ * This register is used for matching unicast and multicast frames.
++ *
++ * @param[in] base GEMAC base address.
++ * @param[in] hash 64-bit hash to be configured.
++ */
++void gemac_set_hash( void *base, MAC_ADDR *hash )
++{
++ writel(hash->bottom, base + EMAC_GALR);
++ writel(hash->top, base + EMAC_GAUR);
++}
++
++void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index)
++{
++ if( (entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX) )
++ return;
++
++ entry_index = entry_index - 1;
++ if (entry_index < 1) {
++ writel(htonl(address->bottom), base + EMAC_PHY_ADDR_LOW);
++ writel((htonl(address->top) | 0x8808), base + EMAC_PHY_ADDR_HIGH);
++ }
++ else
++ {
++ /* TODO for other entry_index */
++ /*printk("%s for entry_index %d \n",__func__, entry_index); */
++ writel(htonl(address->bottom), base + ((entry_index - 1) * 8) + EMAC_SMAC_0_0);
++ writel((htonl(address->top) | 0x8808), base + ((entry_index - 1) * 8) + EMAC_SMAC_0_1);
++ }
++
++}
++
++void gemac_clear_laddrN(void *base, unsigned int entry_index)
++{
++ if( (entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX) )
++ return;
++
++ entry_index = entry_index - 1;
++ if (entry_index < 1) {
++ writel(0, base + EMAC_PHY_ADDR_LOW);
++ writel(0, base + EMAC_PHY_ADDR_HIGH);
++ }
++ else
++ {
++ writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_0);
++ writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_1);
++ }
++
++
++}
++
++/** Set the loopback mode of the MAC. This can be either no loopback for normal
++ * operation, local loopback through MAC internal loopback module or PHY
++ * loopback for external loopback through a PHY. This asserts the external loop
++ * pin.
++ *
++ * @param[in] base GEMAC base address.
++ * @param[in] gem_loop Loopback mode to be enabled. LB_LOCAL - MAC Loopback,
++ * LB_EXT - PHY Loopback.
++ */
++void gemac_set_loop( void *base, MAC_LOOP gem_loop )
++{
++ printk("%s()\n", __func__);
++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_LOOP, (base + EMAC_RCNTRL_REG));
++}
++
++
++/** GEMAC allow frames
++ * @param[in] base GEMAC base address
++ */
++void gemac_enable_copy_all(void *base)
++{
++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_PROM, (base + EMAC_RCNTRL_REG));
++}
++
++/** GEMAC do not allow frames
++ * @param[in] base GEMAC base address
++*/
++void gemac_disable_copy_all(void *base)
++{
++ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_PROM, (base + EMAC_RCNTRL_REG));
++}
++
++/** GEMAC allow broadcast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_allow_broadcast(void *base)
++{
++ writel (readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_BC_REJ, base + EMAC_RCNTRL_REG);
++}
++
++/** GEMAC no broadcast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_no_broadcast(void *base)
++{
++ writel (readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_BC_REJ, base + EMAC_RCNTRL_REG);
++}
++
++/** GEMAC enable unicast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_unicast(void *base)
++{
++ return;
++}
++
++/** GEMAC disable unicast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_unicast(void *base)
++{
++ return;
++}
++
++/** GEMAC enable multicast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_multicast(void *base)
++{
++ return;
++}
++
++/** GEMAC disable multicast function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_multicast(void *base)
++{
++ /* TODO how to disable multicast? */
++ return;
++}
++
++/** GEMAC enable fcs rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_fcs_rx(void *base)
++{
++ /*Do not find configuration to do this */
++}
++
++/** GEMAC disable fcs rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_fcs_rx(void *base)
++{
++ /*Do not find configuration to do this */
++}
++
++
++/** GEMAC enable 1536 rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_1536_rx(void *base)
++{
++ /* Set 1536 as Maximum frame length */
++ writel (readl(base + EMAC_RCNTRL_REG) | (1536 << 16), base + EMAC_RCNTRL_REG);
++}
++
++/** GEMAC enable jumbo function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_rx_jmb(void *base)
++{
++ /*TODO what is the jumbo size supported by MTIP */
++ writel (readl(base + EMAC_RCNTRL_REG) | (JUMBO_FRAME_SIZE << 16), base + EMAC_RCNTRL_REG);
++}
++
++/** GEMAC enable stacked vlan function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_stacked_vlan(void *base)
++{
++ /* MTIP doesn't support stacked vlan */
++ return;
++}
++
++/** GEMAC enable pause rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_enable_pause_rx(void *base)
++{
++ writel (readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_FCE, base + EMAC_RCNTRL_REG);
++}
++
++/** GEMAC disable pause rx function.
++* @param[in] base GEMAC base address
++*/
++void gemac_disable_pause_rx(void *base)
++{
++ writel (readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_FCE, base + EMAC_RCNTRL_REG);
++}
++
++/** GEMAC wol configuration
++* @param[in] base GEMAC base address
++* @param[in] wol_conf WoL register configuration
++*/
++void gemac_set_wol(void *base, u32 wol_conf)
++{
++ printk("%s() TODO\n", __func__);
++}
++
++/** Sets Gemac bus width to 64bit
++ * @param[in] base GEMAC base address
++ * @param[in] width gemac bus width to be set possible values are 32/64/128
++ * */
++void gemac_set_bus_width(void *base, int width)
++{
++}
++
++/** Sets Gemac configuration.
++* @param[in] base GEMAC base address
++* @param[in] cfg GEMAC configuration
++*/
++void gemac_set_config(void *base, GEMAC_CFG *cfg)
++{
++
++ /*GEMAC config taken from VLSI */
++ writel(0x00000004, base + EMAC_TFWR_STR_FWD);
++ writel(0x00000005, base + EMAC_RX_SECTIOM_FULL);
++ writel(0x00003fff, base + EMAC_TRUNC_FL);
++ writel(0x00000030, base + EMAC_TX_SECTION_EMPTY);
++ writel(0x00000000, base + EMAC_MIB_CTRL_STS_REG);
++
++ gemac_set_mode(base, cfg->mode);
++
++ gemac_set_speed(base, cfg->speed);
++
++ gemac_set_duplex(base,cfg->duplex);
++}
++
++
++#endif //CONFIG_PLATFORM_LS1012A)
++
++
++
++/**************************** GPI ***************************/
++
++/** Initializes a GPI block.
++* @param[in] base GPI base address
++* @param[in] cfg GPI configuration
++*/
++void gpi_init(void *base, GPI_CFG *cfg)
++{
++ gpi_reset(base);
++
++ gpi_disable(base);
++
++ gpi_set_config(base, cfg);
++}
++
++/** Resets a GPI block.
++* @param[in] base GPI base address
++*/
++void gpi_reset(void *base)
++{
++ writel (CORE_SW_RESET, base + GPI_CTRL);
++}
++
++/** Enables a GPI block.
++* @param[in] base GPI base address
++*/
++void gpi_enable(void *base)
++{
++ writel (CORE_ENABLE, base + GPI_CTRL);
++}
++
++/** Disables a GPI block.
++* @param[in] base GPI base address
++*/
++void gpi_disable(void *base)
++{
++ writel (CORE_DISABLE, base + GPI_CTRL);
++}
++
++
++/** Sets the configuration of a GPI block.
++* @param[in] base GPI base address
++* @param[in] cfg GPI configuration
++*/
++void gpi_set_config(void *base, GPI_CFG *cfg)
++{
++ writel (CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), base + GPI_LMEM_ALLOC_ADDR);
++ writel (CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL), base + GPI_LMEM_FREE_ADDR);
++ writel (CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL), base + GPI_DDR_ALLOC_ADDR);
++ writel (CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), base + GPI_DDR_FREE_ADDR);
++ writel (CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR);
++ writel (DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET);
++ writel (LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET);
++ writel (0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET);
++ writel (0, base + GPI_DDR_SEC_BUF_DATA_OFFSET);
++ writel ((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, base + GPI_HDR_SIZE);
++ writel ((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE, base + GPI_BUF_SIZE);
++
++ writel (((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) | GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG);
++ writel (cfg->tmlf_txthres, base + GPI_TMLF_TX);
++ writel (cfg->aseq_len, base + GPI_DTX_ASEQ);
++ writel (1, base + GPI_TOE_CHKSUM_EN);
++}
++
++/**************************** CLASSIFIER ***************************/
++
++/** Initializes CLASSIFIER block.
++* @param[in] cfg CLASSIFIER configuration
++*/
++void class_init(CLASS_CFG *cfg)
++{
++ class_reset();
++
++ class_disable();
++
++ class_set_config(cfg);
++}
++
++/** Resets CLASSIFIER block.
++*
++*/
++void class_reset(void)
++{
++ writel(CORE_SW_RESET, CLASS_TX_CTRL);
++}
++
++/** Enables all CLASS-PE's cores.
++*
++*/
++void class_enable(void)
++{
++ writel(CORE_ENABLE, CLASS_TX_CTRL);
++}
++
++/** Disables all CLASS-PE's cores.
++*
++*/
++void class_disable(void)
++{
++ writel(CORE_DISABLE, CLASS_TX_CTRL);
++}
++
++/** Sets the configuration of the CLASSIFIER block.
++* @param[in] cfg CLASSIFIER configuration
++*/
++void class_set_config(CLASS_CFG *cfg)
++{
++ u32 val;
++
++ /* Initialize route table */
++ if (!cfg->resume)
++ memset(DDR_PHYS_TO_VIRT(cfg->route_table_baseaddr), 0, (1 << cfg->route_table_hash_bits) * CLASS_ROUTE_SIZE);
++
++#if !defined(LS1012A_PFE_RESET_WA)
++ writel(cfg->pe_sys_clk_ratio, CLASS_PE_SYS_CLK_RATIO);
++#endif
++
++ writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, CLASS_HDR_SIZE);
++ writel(LMEM_BUF_SIZE, CLASS_LMEM_BUF_SIZE);
++ writel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) | CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits), CLASS_ROUTE_HASH_ENTRY_SIZE);
++ writel(HIF_PKT_CLASS_EN| HIF_PKT_OFFSET(sizeof(struct hif_hdr)), CLASS_HIF_PARSE);
++
++ val = HASH_CRC_PORT_IP | QB2BUS_LE;
++
++#if defined(CONFIG_IP_ALIGNED)
++ val |= IP_ALIGNED;
++#endif
++
++ /* Class PE packet steering will only work if TOE mode, bridge fetch or
++ * route fetch are enabled (see class/qb_fet.v). Route fetch would trigger
++ * additional memory copies (likely from DDR because of hash table size, which
++ * cannot be reduced because PE software still relies on hash value computed
++ * in HW), so when not in TOE mode we simply enable HW bridge fetch even
++ * though we don't use it.
++ */
++ if (cfg->toe_mode)
++ val |= CLASS_TOE;
++ else
++ val |= HW_BRIDGE_FETCH;
++
++ writel(val, CLASS_ROUTE_MULTI);
++
++ writel(DDR_PHYS_TO_PFE(cfg->route_table_baseaddr), CLASS_ROUTE_TABLE_BASE);
++ writel(CLASS_PE0_RO_DM_ADDR0_VAL, CLASS_PE0_RO_DM_ADDR0);
++ writel(CLASS_PE0_RO_DM_ADDR1_VAL, CLASS_PE0_RO_DM_ADDR1);
++ writel(CLASS_PE0_QB_DM_ADDR0_VAL, CLASS_PE0_QB_DM_ADDR0);
++ writel(CLASS_PE0_QB_DM_ADDR1_VAL, CLASS_PE0_QB_DM_ADDR1);
++ writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR), CLASS_TM_INQ_ADDR);
++
++ writel(23, CLASS_AFULL_THRES);
++ writel(23, CLASS_TSQ_FIFO_THRES);
++
++ writel(24, CLASS_MAX_BUF_CNT);
++ writel(24, CLASS_TSQ_MAX_CNT);
++}
++
++/**************************** TMU ***************************/
++
++void tmu_reset(void)
++{
++ writel(SW_RESET, TMU_CTRL);
++}
++
++/** Initializes TMU block.
++* @param[in] cfg TMU configuration
++*/
++void tmu_init(TMU_CFG *cfg)
++{
++ int q, phyno;
++
++ tmu_disable(0xF);
++ mdelay(10);
++
++#if !defined(LS1012A_PFE_RESET_WA)
++ /* keep in soft reset */
++ writel(SW_RESET, TMU_CTRL);
++#endif
++ writel(0x3, TMU_SYS_GENERIC_CONTROL);
++ writel(750, TMU_INQ_WATERMARK);
++ writel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR + GPI_INQ_PKTPTR), TMU_PHY0_INQ_ADDR);
++ writel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR + GPI_INQ_PKTPTR), TMU_PHY1_INQ_ADDR);
++#if !defined(CONFIG_PLATFORM_LS1012A)
++ writel(CBUS_VIRT_TO_PFE(EGPI3_BASE_ADDR + GPI_INQ_PKTPTR), TMU_PHY2_INQ_ADDR);
++#endif
++ writel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR + GPI_INQ_PKTPTR), TMU_PHY3_INQ_ADDR);
++ writel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR), TMU_PHY4_INQ_ADDR);
++ writel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR), TMU_PHY5_INQ_ADDR);
++ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), TMU_BMU_INQ_ADDR);
++
++ writel(0x3FF, TMU_TDQ0_SCH_CTRL); // enabling all 10 schedulers [9:0] of each TDQ
++ writel(0x3FF, TMU_TDQ1_SCH_CTRL);
++#if !defined(CONFIG_PLATFORM_LS1012A)
++ writel(0x3FF, TMU_TDQ2_SCH_CTRL);
++#endif
++ writel(0x3FF, TMU_TDQ3_SCH_CTRL);
++
++#if !defined(LS1012A_PFE_RESET_WA)
++ writel(cfg->pe_sys_clk_ratio, TMU_PE_SYS_CLK_RATIO);
++#endif
++
++#if !defined(LS1012A_PFE_RESET_WA)
++ writel(DDR_PHYS_TO_PFE(cfg->llm_base_addr), TMU_LLM_BASE_ADDR); // Extra packet pointers will be stored from this address onwards
++
++ writel(cfg->llm_queue_len, TMU_LLM_QUE_LEN);
++ writel(5, TMU_TDQ_IIFG_CFG);
++ writel(DDR_BUF_SIZE, TMU_BMU_BUF_SIZE);
++
++ writel(0x0, TMU_CTRL);
++
++ /* MEM init */
++ printk(KERN_INFO "%s: mem init\n", __func__);
++ writel(MEM_INIT, TMU_CTRL);
++
++ while(!(readl(TMU_CTRL) & MEM_INIT_DONE)) ;
++
++ /* LLM init */
++ printk(KERN_INFO "%s: lmem init\n", __func__);
++ writel(LLM_INIT, TMU_CTRL);
++
++ while(!(readl(TMU_CTRL) & LLM_INIT_DONE)) ;
++#endif
++ // set up each queue for tail drop
++ for (phyno = 0; phyno < 4; phyno++)
++ {
++#if defined(CONFIG_PLATFORM_LS1012A)
++ if(phyno == 2) continue;
++#endif
++ for (q = 0; q < 16; q++)
++ {
++ u32 qdepth;
++ writel((phyno << 8) | q, TMU_TEQ_CTRL);
++ writel(1 << 22, TMU_TEQ_QCFG); //Enable tail drop
++
++ if (phyno == 3)
++ qdepth = DEFAULT_TMU3_QDEPTH;
++ else
++ qdepth = (q == 0) ? DEFAULT_Q0_QDEPTH : DEFAULT_MAX_QDEPTH;
++
++ // LOG: 68855
++ // The following is a workaround for the reordered packet and BMU2 buffer leakage issue.
++ if (CHIP_REVISION() == 0)
++ qdepth = 31;
++
++ writel(qdepth << 18, TMU_TEQ_HW_PROB_CFG2);
++ writel(qdepth >> 14, TMU_TEQ_HW_PROB_CFG3);
++ }
++ }
++
++#ifdef CFG_LRO
++ /* Set TMU-3 queue 5 (LRO) in no-drop mode */
++ writel((3 << 8) | TMU_QUEUE_LRO, TMU_TEQ_CTRL);
++ writel(0, TMU_TEQ_QCFG);
++#endif
++
++ writel(0x05, TMU_TEQ_DISABLE_DROPCHK);
++
++ writel(0x0, TMU_CTRL);
++}
++
++/** Enables TMU-PE cores.
++* @param[in] pe_mask TMU PE mask
++*/
++void tmu_enable(u32 pe_mask)
++{
++ writel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL);
++}
++
++/** Disables TMU cores.
++* @param[in] pe_mask TMU PE mask
++*/
++void tmu_disable(u32 pe_mask)
++{
++ writel(readl(TMU_TX_CTRL) & ~(pe_mask & 0xF), TMU_TX_CTRL);
++}
++/** This will return the tmu queue status
++ * @param[in] if_id gem interface id or TMU index
++ * @return returns the bit mask of busy queues, zero means all queues are empty
++ */
++u32 tmu_qstatus(u32 if_id)
++{
++ return cpu_to_be32(pe_dmem_read(TMU0_ID+if_id, PESTATUS_ADDR_TMU + offsetof(PE_STATUS, tmu_qstatus), 4));
++}
++
++u32 tmu_pkts_processed(u32 if_id)
++{
++ return cpu_to_be32(pe_dmem_read(TMU0_ID+if_id, PESTATUS_ADDR_TMU + offsetof(PE_STATUS, rx), 4));
++}
++/**************************** UTIL ***************************/
++
++/** Resets UTIL block.
++*/
++void util_reset(void)
++{
++ writel(CORE_SW_RESET, UTIL_TX_CTRL);
++}
++
++/** Initializes UTIL block.
++* @param[in] cfg UTIL configuration
++*/
++void util_init(UTIL_CFG *cfg)
++{
++ writel(cfg->pe_sys_clk_ratio, UTIL_PE_SYS_CLK_RATIO);
++}
++
++/** Enables UTIL-PE core.
++*
++*/
++void util_enable(void)
++{
++ writel(CORE_ENABLE, UTIL_TX_CTRL);
++}
++
++/** Disables UTIL-PE core.
++*
++*/
++void util_disable(void)
++{
++ writel(CORE_DISABLE, UTIL_TX_CTRL);
++}
++
++/**************************** HIF ***************************/
++
++/** Initializes HIF no copy block.
++*
++*/
++void hif_nocpy_init(void)
++{
++ writel(4, HIF_NOCPY_TX_PORT_NO);
++ writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), HIF_NOCPY_LMEM_ALLOC_ADDR);
++ writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), HIF_NOCPY_CLASS_ADDR);
++ writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR), HIF_NOCPY_TMU_PORT0_ADDR);
++ writel(HIF_RX_POLL_CTRL_CYCLE<<16|HIF_TX_POLL_CTRL_CYCLE, HIF_NOCPY_POLL_CTRL);
++}
++
++/** Enable hif_nocpy tx DMA and interrupt
++*
++*/
++void hif_nocpy_tx_enable(void)
++{
++ /*TODO not sure poll_cntrl_en is required or not */
++ writel( HIF_CTRL_DMA_EN, HIF_NOCPY_TX_CTRL);
++ //writel((readl(HIF_NOCPY_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN), HIF_NOCPY_INT_ENABLE);
++}
++
++/** Disable hif_nocpy tx DMA and interrupt
++*
++*/
++void hif_nocpy_tx_disable(void)
++{
++ u32 hif_int;
++
++ writel(0, HIF_NOCPY_TX_CTRL);
++
++ hif_int = readl(HIF_NOCPY_INT_ENABLE);
++ hif_int &= HIF_TXPKT_INT_EN;
++ writel(hif_int, HIF_NOCPY_INT_ENABLE);
++}
++
++/** Enable hif rx DMA and interrupt
++*
++*/
++void hif_nocpy_rx_enable(void)
++{
++ hif_nocpy_rx_dma_start();
++ writel((readl(HIF_NOCPY_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN), HIF_NOCPY_INT_ENABLE);
++}
++
++/** Disable hif_nocpy rx DMA and interrupt
++*
++*/
++void hif_nocpy_rx_disable(void)
++{
++ u32 hif_int;
++
++ writel(0, HIF_NOCPY_RX_CTRL);
++
++ hif_int = readl(HIF_NOCPY_INT_ENABLE);
++ hif_int &= HIF_RXPKT_INT_EN;
++ writel(hif_int, HIF_NOCPY_INT_ENABLE);
++
++}
++/** Initializes HIF copy block.
++*
++*/
++void hif_init(void)
++{
++ /*Initialize HIF registers*/
++ writel((HIF_RX_POLL_CTRL_CYCLE << 16) | HIF_TX_POLL_CTRL_CYCLE, HIF_POLL_CTRL);
++}
++
++/** Enable hif tx DMA and interrupt
++*
++*/
++void hif_tx_enable(void)
++{
++ /*TODO not sure poll_cntrl_en is required or not */
++ writel(HIF_CTRL_DMA_EN, HIF_TX_CTRL);
++ writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN), HIF_INT_ENABLE);
++}
++
++/** Disable hif tx DMA and interrupt
++*
++*/
++void hif_tx_disable(void)
++{
++ u32 hif_int;
++
++ writel(0, HIF_TX_CTRL);
++
++ hif_int = readl(HIF_INT_ENABLE);
++ hif_int &= HIF_TXPKT_INT_EN;
++ writel(hif_int, HIF_INT_ENABLE);
++}
++
++/** Enable hif rx DMA and interrupt
++*
++*/
++void hif_rx_enable(void)
++{
++ hif_rx_dma_start();
++ writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN), HIF_INT_ENABLE);
++}
++
++/** Disable hif rx DMA and interrupt
++*
++*/
++void hif_rx_disable(void)
++{
++ u32 hif_int;
++
++ writel(0, HIF_RX_CTRL);
++
++ hif_int = readl(HIF_INT_ENABLE);
++ hif_int &= HIF_RXPKT_INT_EN;
++ writel(hif_int, HIF_INT_ENABLE);
++
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hif.c
+@@ -0,0 +1,939 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifdef __KERNEL__
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/sched.h>
++#include <linux/module.h>
++#include <linux/list.h>
++#include <linux/kthread.h>
++#include <linux/slab.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#else
++#include "platform.h"
++#endif
++
++
++#include "pfe_mod.h"
++#if 0
++#define DMA_MAP_SINGLE(dev, vaddr, size, direction) dma_map_single(dev, vaddr, size, direction)
++#define DMA_UNMAP_SINGLE(dev, vaddr, size, direction) dma_unmap_single(dev, vaddr, size, direction)
++void ct_flush(void *addr, u32 size)
++{
++ dma_map_single(pfe->dev, addr, size, DMA_TO_DEVICE);
++}
++#else
++#define DMA_UNMAP_SINGLE(dev, vaddr, size, direction)
++#define DMA_MAP_SINGLE(dev, vaddr, size, direction) virt_to_phys(vaddr)
++#define ct_flush(addr, sz)
++#endif
++
++#define HIF_INT_MASK (HIF_INT | HIF_RXPKT_INT)
++
++#define inc_cl_idx(idxname) idxname = (idxname+1) & (queue->size-1)
++#define inc_hif_rxidx(idxname) idxname = (idxname+1) & (hif->RxRingSize-1)
++#define inc_hif_txidx(idxname) idxname = (idxname+1) & (hif->TxRingSize-1)
++
++unsigned char napi_first_batch = 0;
++
++static int pfe_hif_alloc_descr(struct pfe_hif *hif)
++{
++#if !defined(CONFIG_PLATFORM_PCI)
++ void *addr;
++ dma_addr_t dma_addr;
++ int err = 0;
++
++ printk(KERN_INFO "%s\n", __func__);
++ addr = dma_alloc_coherent(pfe->dev,
++ HIF_RX_DESC_NT * sizeof(struct hif_desc) + HIF_TX_DESC_NT * sizeof(struct hif_desc),
++ &dma_addr, GFP_KERNEL);
++
++ if (!addr) {
++ printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n", __func__);
++ err = -ENOMEM;
++ goto err0;
++ }
++
++ hif->descr_baseaddr_p = dma_addr;
++ hif->descr_baseaddr_v = addr;
++#else
++ hif->descr_baseaddr_p = pfe->ddr_phys_baseaddr + HIF_DESC_BASEADDR;
++ hif->descr_baseaddr_v = pfe->ddr_baseaddr + HIF_DESC_BASEADDR;
++#endif
++ hif->RxRingSize = HIF_RX_DESC_NT;
++ hif->TxRingSize = HIF_TX_DESC_NT;
++
++ return 0;
++
++err0:
++ return err;
++}
++
++static void pfe_hif_free_descr(struct pfe_hif *hif)
++{
++ printk(KERN_INFO "%s\n", __func__);
++#if !defined(CONFIG_PLATFORM_PCI)
++ dma_free_coherent(pfe->dev,
++ hif->RxRingSize * sizeof(struct hif_desc) + hif->TxRingSize * sizeof(struct hif_desc),
++ hif->descr_baseaddr_v, hif->descr_baseaddr_p);
++#endif
++}
++void pfe_hif_desc_dump(struct pfe_hif *hif)
++{
++ struct hif_desc *desc;
++ unsigned long desc_p;
++ int ii=0;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ desc = hif->RxBase;
++ desc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v + hif->descr_baseaddr_p);
++
++ printk("HIF Rx desc base %p physical %x\n", desc, (u32)desc_p);
++ for (ii = 0; ii < hif->RxRingSize; ii++) {
++ printk(KERN_INFO "status: %08x, ctrl: %08x, data: %08x, next: %x\n",
++ desc->status, desc->ctrl, desc->data, desc->next);
++ desc++;
++ }
++
++ desc = hif->TxBase;
++ desc_p = ((u64)desc - (u64)hif->descr_baseaddr_v + hif->descr_baseaddr_p);
++
++ printk("HIF Tx desc base %p physical %x\n", desc, (u32)desc_p);
++ for (ii = 0; ii < hif->TxRingSize; ii++) {
++ printk(KERN_INFO "status: %08x, ctrl: %08x, data: %08x, next: %x\n",
++ desc->status, desc->ctrl, desc->data, desc->next);
++ desc++;
++ }
++
++}
++
++/* pfe_hif_release_buffers
++ *
++ */
++static void pfe_hif_release_buffers(struct pfe_hif *hif)
++{
++ struct hif_desc *desc;
++ int i = 0;
++
++ hif->RxBase = hif->descr_baseaddr_v;
++
++ printk(KERN_INFO "%s\n", __func__);
++ /*Free Rx buffers */
++#if !defined(CONFIG_PLATFORM_PCI)
++ desc = hif->RxBase;
++ for (i = 0; i < hif->RxRingSize; i++) {
++ if (desc->data) {
++ if ((i < hif->shm->rx_buf_pool_cnt) && (hif->shm->rx_buf_pool[i] == NULL)) {
++ //dma_unmap_single(hif->dev, desc->data, hif->rx_buf_len[i], DMA_FROM_DEVICE);
++ DMA_UNMAP_SINGLE(hif->dev, desc->data, hif->rx_buf_len[i], DMA_FROM_DEVICE);
++ hif->shm->rx_buf_pool[i] = hif->rx_buf_addr[i];
++ }
++ else {
++ /*TODO This should not happen*/
++ printk(KERN_ERR "%s: buffer pool already full\n", __func__);
++ }
++ }
++
++ desc->data = 0;
++ desc->status = 0;
++ desc->ctrl = 0;
++ desc++;
++ }
++#endif
++}
++
++
++/*
++ * pfe_hif_init_buffers
++ * This function initializes the HIF Rx/Tx ring descriptors and
++ * initialize Rx queue with buffers.
++ */
++static int pfe_hif_init_buffers(struct pfe_hif *hif)
++{
++ struct hif_desc *desc, *first_desc_p;
++ u32 data;
++ int i = 0;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ /* Check enough Rx buffers available in the shared memory */
++ if (hif->shm->rx_buf_pool_cnt < hif->RxRingSize)
++ return -ENOMEM;
++
++ hif->RxBase = hif->descr_baseaddr_v;
++ memset(hif->RxBase, 0, hif->RxRingSize * sizeof(struct hif_desc));
++
++ /*Initialize Rx descriptors */
++ desc = hif->RxBase;
++ first_desc_p = (struct hif_desc *)hif->descr_baseaddr_p;
++
++ for (i = 0; i < hif->RxRingSize; i++) {
++ /* Initialize Rx buffers from the shared memory */
++
++#if defined(CONFIG_PLATFORM_PCI)
++ data = pfe->ddr_phys_baseaddr + HIF_RX_PKT_DDR_BASEADDR + i * DDR_BUF_SIZE;
++#else
++ data = (u32)DMA_MAP_SINGLE(hif->dev, hif->shm->rx_buf_pool[i], pfe_pkt_size, DMA_FROM_DEVICE);
++ hif->rx_buf_addr[i] = hif->shm->rx_buf_pool[i];
++ hif->rx_buf_len[i] = pfe_pkt_size;
++ // printk("#%d %p %p %d\n", i, data, hif->rx_buf_addr[i], hif->rx_buf_len[i]);
++ hif->shm->rx_buf_pool[i] = NULL;
++#endif
++ if (likely(dma_mapping_error(hif->dev, data) == 0)) {
++ desc->data = DDR_PHYS_TO_PFE(data);
++ } else {
++ printk(KERN_ERR "%s : low on mem\n", __func__);
++
++ goto err;
++ }
++
++ desc->status = 0;
++ wmb();
++ desc->ctrl = BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM | BD_CTRL_DIR |
++ BD_CTRL_DESC_EN | BD_BUF_LEN(pfe_pkt_size);
++ /* Chain descriptors */
++ desc->next = (u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1);
++ desc++;
++ }
++
++ /* Overwrite last descriptor to chain it to first one*/
++ desc--;
++ desc->next = (u32)DDR_PHYS_TO_PFE(first_desc_p);
++
++ hif->RxtocleanIndex = 0;
++
++ /*Initialize Rx buffer descriptor ring base address */
++ writel(DDR_PHYS_TO_PFE(hif->descr_baseaddr_p), HIF_RX_BDP_ADDR);
++
++ hif->TxBase = hif->RxBase + hif->RxRingSize;
++ first_desc_p = (struct hif_desc *)hif->descr_baseaddr_p + hif->RxRingSize;
++ memset(hif->TxBase, 0, hif->TxRingSize * sizeof(struct hif_desc));
++
++ /*Initialize tx descriptors */
++ desc = hif->TxBase;
++
++ for (i = 0; i < hif->TxRingSize; i++) {
++ /* Chain descriptors */
++ desc->next = (u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1);
++#if defined(CONFIG_PLATFORM_PCI)
++ desc->data = pfe->ddr_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR + i * DDR_BUF_SIZE;
++#endif
++ desc->ctrl = 0;
++ desc++;
++ }
++
++ /* Overwrite last descriptor to chain it to first one */
++ desc--;
++ desc->next = (u32)DDR_PHYS_TO_PFE(first_desc_p);
++ hif->TxAvail = hif->TxRingSize;
++ hif->Txtosend = 0;
++ hif->Txtoclean = 0;
++ hif->Txtoflush = 0;
++
++ /*Initialize Tx buffer descriptor ring base address */
++ writel((u32)DDR_PHYS_TO_PFE(first_desc_p), HIF_TX_BDP_ADDR);
++
++ return 0;
++
++err:
++ pfe_hif_release_buffers(hif);
++ return -ENOMEM;
++}
++
++/* pfe_hif_client_register
++ *
++ * This function used to register a client driver with the HIF driver.
++ *
++ * Return value:
++ * 0 - on Successful registration
++ */
++static int pfe_hif_client_register(struct pfe_hif *hif, u32 client_id, struct hif_client_shm *client_shm)
++{
++ struct hif_client *client = &hif->client[client_id];
++ u32 i, cnt;
++ struct rx_queue_desc *rx_qbase;
++ struct tx_queue_desc *tx_qbase;
++ struct hif_rx_queue *rx_queue;
++ struct hif_tx_queue *tx_queue;
++ int err = 0;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ spin_lock_bh(&hif->tx_lock);
++
++ if (test_bit(client_id, &hif->shm->gClient_status[0])) {
++ printk(KERN_ERR "%s: client %d already registered\n", __func__, client_id);
++ err = -1;
++ goto unlock;
++ }
++
++ memset(client, 0, sizeof(struct hif_client));
++
++ /*Initialize client Rx queues baseaddr, size */
++
++ cnt = CLIENT_CTRL_RX_Q_CNT(client_shm->ctrl);
++ /*Check if client is requesting for more queues than supported */
++ if (cnt > HIF_CLIENT_QUEUES_MAX)
++ cnt = HIF_CLIENT_QUEUES_MAX;
++
++ client->rx_qn = cnt;
++ rx_qbase = (struct rx_queue_desc *)client_shm->rx_qbase;
++ for (i = 0; i < cnt; i++)
++ {
++ rx_queue = &client->rx_q[i];
++ rx_queue->base = rx_qbase + i * client_shm->rx_qsize;
++ rx_queue->size = client_shm->rx_qsize;
++ rx_queue->write_idx = 0;
++ }
++
++ /*Initialize client Tx queues baseaddr, size */
++ cnt = CLIENT_CTRL_TX_Q_CNT(client_shm->ctrl);
++
++ /*Check if client is requesting for more queues than supported */
++ if (cnt > HIF_CLIENT_QUEUES_MAX)
++ cnt = HIF_CLIENT_QUEUES_MAX;
++
++ client->tx_qn = cnt;
++ tx_qbase = (struct tx_queue_desc *)client_shm->tx_qbase;
++ for (i = 0; i < cnt; i++)
++ {
++ tx_queue = &client->tx_q[i];
++ tx_queue->base = tx_qbase + i * client_shm->tx_qsize;
++ tx_queue->size = client_shm->tx_qsize;
++ tx_queue->ack_idx = 0;
++ }
++
++ set_bit(client_id, &hif->shm->gClient_status[0]);
++
++unlock:
++ spin_unlock_bh(&hif->tx_lock);
++
++ return err;
++}
++
++
++/* pfe_hif_client_unregister
++ *
++ * This function used to unregister a client from the HIF driver.
++ *
++ */
++static void pfe_hif_client_unregister(struct pfe_hif *hif, u32 client_id)
++{
++ printk(KERN_INFO "%s\n", __func__);
++
++ /* Mark client as no longer available (which prevents further packet receive for this client) */
++ spin_lock_bh(&hif->tx_lock);
++
++ if (!test_bit(client_id, &hif->shm->gClient_status[0])) {
++ printk(KERN_ERR "%s: client %d not registered\n", __func__, client_id);
++
++ spin_unlock_bh(&hif->tx_lock);
++ return;
++ }
++
++ clear_bit(client_id, &hif->shm->gClient_status[0]);
++
++ spin_unlock_bh(&hif->tx_lock);
++}
++
++/* client_put_rxpacket-
++ * This functions puts the Rx pkt in the given client Rx queue.
++ * It actually swap the Rx pkt in the client Rx descriptor buffer
++ * and returns the free buffer from it.
++ *
++ * If the funtion returns NULL means client Rx queue is full and
++ * packet couldn't send to client queue.
++ */
++static void *client_put_rxpacket(struct hif_rx_queue *queue, void *pkt, u32 len, u32 flags, u32 client_ctrl, u32 *rem_len)
++{
++ void *free_pkt = NULL;
++ struct rx_queue_desc *desc = queue->base + queue->write_idx;
++
++ if (desc->ctrl & CL_DESC_OWN) {
++#if defined(CONFIG_PLATFORM_PCI)
++ memcpy(desc->data, pkt, len);
++ free_pkt = PFE_HOST_TO_PCI(pkt);
++ smp_wmb();
++ desc->ctrl = CL_DESC_BUF_LEN(len) | flags;
++ inc_cl_idx(queue->write_idx);
++#else
++ //TODO: move allocations after Rx loop to improve instruction cache locality
++ if (page_mode) {
++ int rem_page_size = PAGE_SIZE - PRESENT_OFST_IN_PAGE(pkt);
++ int cur_pkt_size = ROUND_MIN_RX_SIZE(len + pfe_pkt_headroom);
++ *rem_len = (rem_page_size - cur_pkt_size);
++ //printk("%p rem_len %d cur_len %d buf_len %d\n", pkt, rem_page_size, cur_pkt_size, *rem_len);
++ if (*rem_len)
++ {
++ free_pkt = pkt + cur_pkt_size;
++ get_page(virt_to_page(free_pkt));
++ } else {
++ free_pkt = (void *)__get_free_page(GFP_ATOMIC | GFP_DMA_PFE);
++ *rem_len = pfe_pkt_size;
++ }
++ } else {
++ free_pkt = kmalloc(PFE_BUF_SIZE, GFP_ATOMIC | GFP_DMA_PFE);
++ *rem_len = PFE_BUF_SIZE - pfe_pkt_headroom;
++ }
++
++ if (free_pkt) {
++ desc->data = pkt;
++ desc->client_ctrl = client_ctrl;
++ smp_wmb();
++ desc->ctrl = CL_DESC_BUF_LEN(len) | flags;
++ inc_cl_idx(queue->write_idx);
++ free_pkt += pfe_pkt_headroom;
++ }
++#endif
++ }
++
++ return free_pkt;
++}
++
++
++/* pfe_hif_rx_process-
++ * This function does pfe hif rx queue processing.
++ * Dequeue packet from Rx queue and send it to corresponding client queue
++ */
++static int pfe_hif_rx_process(struct pfe_hif *hif, int budget)
++{
++ struct hif_desc *desc;
++ struct hif_hdr *pkt_hdr;
++ struct __hif_hdr hif_hdr;
++ void *free_buf;
++ int rtc, len, rx_processed = 0;
++ struct __hif_desc local_desc;
++ int flags;
++ unsigned int desc_p;
++ unsigned int buf_size = 0;
++
++ spin_lock_bh(&hif->lock);
++
++ rtc = hif->RxtocleanIndex;
++
++ while (rx_processed < budget)
++ {
++ /*TODO may need to implement rx process budget */
++ desc = hif->RxBase + rtc;
++
++ __memcpy12(&local_desc, desc);
++
++ /* ACK pending Rx interrupt */
++ if (local_desc.ctrl & BD_CTRL_DESC_EN) {
++ writel(HIF_INT_MASK, HIF_INT_SRC);
++
++ if(rx_processed == 0)
++ {
++ if(napi_first_batch == 1)
++ {
++ desc_p = hif->descr_baseaddr_p + ((unsigned long int)(desc) - (unsigned long int)hif->descr_baseaddr_v);
++#if defined(CONFIG_PLATFORM_C2000)
++ outer_inv_range(desc_p, (desc_p + 16));
++#endif
++ napi_first_batch = 0;
++ }
++ }
++
++ __memcpy12(&local_desc, desc);
++
++ if (local_desc.ctrl & BD_CTRL_DESC_EN)
++ break;
++ }
++
++ napi_first_batch = 0;
++
++#ifdef HIF_NAPI_STATS
++ hif->napi_counters[NAPI_DESC_COUNT]++;
++#endif
++ len = BD_BUF_LEN(local_desc.ctrl);
++#if defined(CONFIG_PLATFORM_PCI)
++ pkt_hdr = &hif_hdr;
++ memcpy(pkt_hdr, (void *)PFE_PCI_TO_HOST(local_desc.data), sizeof(struct hif_hdr));
++#else
++ //dma_unmap_single(hif->dev, DDR_PFE_TO_PHYS(local_desc.data), hif->rx_buf_len[rtc], DMA_FROM_DEVICE);
++ DMA_UNMAP_SINGLE(hif->dev, DDR_PFE_TO_PHYS(local_desc.data), hif->rx_buf_len[rtc], DMA_FROM_DEVICE);
++
++ pkt_hdr = (struct hif_hdr *)hif->rx_buf_addr[rtc];
++
++ /* Track last HIF header received */
++ if (!hif->started) {
++ hif->started = 1;
++
++ __memcpy8(&hif_hdr, pkt_hdr);
++
++ hif->qno = hif_hdr.hdr.qNo;
++ hif->client_id = hif_hdr.hdr.client_id;
++ hif->client_ctrl = (hif_hdr.hdr.client_ctrl1 << 16) | hif_hdr.hdr.client_ctrl;
++ flags = CL_DESC_FIRST;
++
++// printk(KERN_INFO "start of packet: id %d, q %d, len %d, flags %x %x\n", hif->client_id, hif->qno, len, local_desc.ctrl, hif->client_ctrl);
++ }
++ else {
++// printk(KERN_INFO "continuation: id %d, q %d, len %d, flags %x\n", hif->client_id, hif->qno, len, local_desc.ctrl);
++ flags = 0;
++ }
++
++ if (local_desc.ctrl & BD_CTRL_LIFM)
++ flags |= CL_DESC_LAST;
++#endif
++ /* Check for valid client id and still registered */
++ if ((hif->client_id >= HIF_CLIENTS_MAX) || !(test_bit(hif->client_id, &hif->shm->gClient_status[0]))) {
++ if (printk_ratelimit())
++ printk(KERN_ERR "%s: packet with invalid client id %d qNo %d\n", __func__, hif->client_id, hif->qno);
++
++#if defined(CONFIG_PLATFORM_PCI)
++ free_buf = local_desc.data;
++#else
++ free_buf = pkt_hdr;
++#endif
++ goto pkt_drop;
++ }
++
++ /* Check to valid queue number */
++ if (hif->client[hif->client_id].rx_qn <= hif->qno) {
++ printk(KERN_INFO "%s: packet with invalid queue: %d\n", __func__, hif->qno);
++ hif->qno = 0;
++ }
++
++#if defined(CONFIG_PLATFORM_PCI)
++ free_buf = client_put_rxpacket(&hif->client[hif->client_id].rx_q[hif->qno],
++ (void *)PFE_PCI_TO_HOST(desc->data), len, flags, hif->client_ctrl, &buf_zize);
++#else
++ free_buf = client_put_rxpacket(&hif->client[hif->client_id].rx_q[hif->qno],
++ (void *)pkt_hdr, len, flags, hif->client_ctrl, &buf_size);
++#endif
++
++ hif_lib_indicate_client(hif->client_id, EVENT_RX_PKT_IND, hif->qno);
++
++ if (unlikely(!free_buf)) {
++#ifdef HIF_NAPI_STATS
++ hif->napi_counters[NAPI_CLIENT_FULL_COUNT]++;
++#endif
++ /* If we want to keep in polling mode to retry later, we need to tell napi that we consumed
++ the full budget or we will hit a livelock scenario. The core code keeps this napi instance
++ at the head of the list and none of the other instances get to run */
++ rx_processed = budget;
++
++ if (flags & CL_DESC_FIRST)
++ hif->started = 0;
++
++ break;
++ }
++
++ pkt_drop:
++#if defined(CONFIG_PLATFORM_PCI)
++ desc->data = (u32)free_buf;
++#else
++ /*Fill free buffer in the descriptor */
++ hif->rx_buf_addr[rtc] = free_buf;
++ hif->rx_buf_len[rtc] = min(pfe_pkt_size, buf_size);
++ desc->data = DDR_PHYS_TO_PFE((u32)DMA_MAP_SINGLE(hif->dev, free_buf, hif->rx_buf_len[rtc], DMA_FROM_DEVICE));
++ //printk("#%p %p %d\n", desc->data, hif->rx_buf_addr[rtc], hif->rx_buf_len[rtc]);
++#endif
++ wmb();
++ desc->ctrl = BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM | BD_CTRL_DIR |
++ BD_CTRL_DESC_EN | BD_BUF_LEN(hif->rx_buf_len[rtc]);
++
++ inc_hif_rxidx(rtc);
++
++ if (local_desc.ctrl & BD_CTRL_LIFM) {
++ if (!(hif->client_ctrl & HIF_CTRL_RX_CONTINUED)) {
++ rx_processed++;
++
++#ifdef HIF_NAPI_STATS
++ hif->napi_counters[NAPI_PACKET_COUNT]++;
++#endif
++ }
++ hif->started = 0;
++ }
++ }
++
++ hif->RxtocleanIndex = rtc;
++ spin_unlock_bh(&hif->lock);
++
++ /* we made some progress, re-start rx dma in case it stopped */
++ hif_rx_dma_start();
++
++ return rx_processed;
++}
++
++
++/* client_ack_txpacket-
++ * This function ack the Tx packet in the give client Tx queue by resetting
++ * ownership bit in the descriptor.
++ */
++static int client_ack_txpacket(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no)
++{
++ struct hif_tx_queue *queue = &hif->client[client_id].tx_q[q_no];
++ struct tx_queue_desc *desc = queue->base + queue->ack_idx;
++
++ if (desc->ctrl & CL_DESC_OWN) {
++ /*TODO Do we need to match the pkt address also? */
++ desc->ctrl &= ~CL_DESC_OWN;
++ inc_cl_idx(queue->ack_idx);
++
++ return 0;
++ }
++ else {
++ /*This should not happen */
++ printk(KERN_ERR "%s: %d %d %d %d %d %p %d\n", __func__, hif->Txtosend, hif->Txtoclean, hif->TxAvail, client_id, q_no, queue, queue->ack_idx);
++ BUG();
++ return 1;
++ }
++}
++
++void __hif_tx_done_process(struct pfe_hif *hif, int count)
++{
++ struct hif_desc *desc;
++ struct hif_desc_sw *desc_sw;
++ int ttc, tx_avl;
++
++ ttc = hif->Txtoclean;
++ tx_avl = hif->TxAvail;
++
++ while ((tx_avl < hif->TxRingSize) && count--) {
++ desc = hif->TxBase + ttc;
++
++ if (desc->ctrl & BD_CTRL_DESC_EN)
++ break;
++
++ desc_sw = &hif->tx_sw_queue[ttc];
++
++ if (desc_sw->data) {
++#if !defined(CONFIG_PLATFORM_PCI)
++ //dmap_unmap_single(hif->dev, desc_sw->data, desc_sw->len, DMA_TO_DEVICE);
++ DMA_UNMAP_SINGLE(hif->dev, desc_sw->data, desc_sw->len, DMA_TO_DEVICE);
++#endif
++ }
++ client_ack_txpacket(hif, desc_sw->client_id, desc_sw->q_no);
++
++ inc_hif_txidx(ttc);
++ tx_avl++;
++ }
++
++ hif->Txtoclean = ttc;
++ hif->TxAvail = tx_avl;
++}
++
++
++/* __hif_xmit_pkt -
++ * This function puts one packet in the HIF Tx queue
++ */
++void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no, void *data, u32 len, unsigned int flags)
++{
++ struct hif_desc *desc;
++ struct hif_desc_sw *desc_sw;
++
++#if defined(CONFIG_PLATFORM_EMULATION)
++ {
++ struct hif_queue *queue = &hif->client[client_id].rx_q[0];
++ struct queue_desc *qdesc = queue->base + queue->write_idx;
++ void *buf;
++
++ printk("%s: packet loop backed client_id:%d qno:%d data : %p len:%d\n", __func__, client_id, q_no, data, len);
++#if 1
++ if (qdesc->ctrl & CL_DESC_OWN) {
++ buf = (void *)qdesc->data;
++ memcpy(buf, data, len);
++ wmb();
++ qdesc->ctrl = CL_DESC_BUF_LEN(len);
++ inc_cl_idx(queue->write_idx);
++ printk("%s: packet loop backed..\n", __func__);
++ hif_lib_indicate_client(client_id, EVENT_RX_PKT_IND, q_no);
++ client_ack_txpacket(&hif->client[client_id].tx_q[q_no]);
++ }
++#endif
++ }
++
++#else
++ desc = hif->TxBase + hif->Txtosend;
++ desc_sw = &hif->tx_sw_queue[hif->Txtosend];
++
++ desc_sw->len = len;
++ desc_sw->client_id = client_id;
++ desc_sw->q_no = q_no;
++ desc_sw->flags = flags;
++
++#if !defined(CONFIG_PLATFORM_PCI)
++ if (flags & HIF_DONT_DMA_MAP) {
++ desc_sw->data = 0;
++ desc->data = (u32)DDR_PHYS_TO_PFE(data);
++ } else {
++ desc_sw->data = DMA_MAP_SINGLE(hif->dev, data, len, DMA_TO_DEVICE);
++ desc->data = (u32)DDR_PHYS_TO_PFE(desc_sw->data);
++ }
++#else
++#define ALIGN32(x) ((x) & ~0x3)
++ memcpy(PFE_PCI_TO_HOST(desc->data), data, ALIGN32(len+0x3));
++#endif
++
++ inc_hif_txidx(hif->Txtosend);
++ hif->TxAvail--;
++
++ /* For TSO we skip actual TX until the last descriptor */
++ /* This reduce the number of required wmb() */
++ if ((flags & HIF_TSO) && (!((flags & HIF_DATA_VALID) && (flags & HIF_LAST_BUFFER))))
++ goto skip_tx;
++
++ wmb();
++
++ do {
++ desc_sw = &hif->tx_sw_queue[hif->Txtoflush];
++ desc = hif->TxBase + hif->Txtoflush;
++
++ if (desc_sw->flags & HIF_LAST_BUFFER) {
++ if ((desc_sw->client_id < PFE_CL_VWD0) || (desc_sw->client_id > (PFE_CL_VWD0 + MAX_VAP_SUPPORT)))
++ desc->ctrl = BD_CTRL_LIFM | BD_CTRL_BRFETCH_DISABLE |
++ BD_CTRL_RTFETCH_DISABLE | BD_CTRL_PARSE_DISABLE |
++ BD_CTRL_DESC_EN | BD_BUF_LEN(desc_sw->len);
++ else {
++
++ desc->ctrl = BD_CTRL_LIFM | BD_CTRL_DESC_EN | BD_BUF_LEN(desc_sw->len);
++ }
++ }
++ else
++ desc->ctrl = BD_CTRL_DESC_EN | BD_BUF_LEN(desc_sw->len);
++
++ inc_hif_txidx(hif->Txtoflush);
++ }
++ while (hif->Txtoflush != hif->Txtosend);
++
++skip_tx:
++ return;
++
++#endif
++}
++
++
++int hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no, void *data, unsigned int len)
++{
++ int rc = 0;
++
++ spin_lock_bh(&hif->tx_lock);
++
++ if (!hif->TxAvail)
++ rc = 1;
++ else {
++ __hif_xmit_pkt(hif, client_id, q_no, data, len, HIF_FIRST_BUFFER | HIF_LAST_BUFFER);
++ hif_tx_dma_start();
++ }
++ if (hif->TxAvail < (hif->TxRingSize >> 1))
++ __hif_tx_done_process(hif, TX_FREE_MAX_COUNT);
++
++ spin_unlock_bh(&hif->tx_lock);
++
++ return rc;
++}
++
++/* hif_isr-
++ * This ISR routine processes Rx/Tx done interrupts from the HIF hardware block
++ */
++static irqreturn_t hif_isr(int irq, void *dev_id)
++{
++ struct pfe_hif *hif = (struct pfe_hif *) dev_id;
++ int int_status;
++
++ /*Read hif interrupt source register */
++ int_status = readl_relaxed(HIF_INT_SRC);
++
++ if ((int_status & HIF_INT) == 0)
++ return(IRQ_NONE);
++
++ int_status &= ~(HIF_INT);
++
++ if (int_status & HIF_RXPKT_INT) {
++ int_status &= ~(HIF_RXPKT_INT);
++
++ /* Disable interrupts */
++ writel_relaxed(0, HIF_INT_ENABLE);
++
++ napi_first_batch = 1;
++
++ if (napi_schedule_prep(&hif->napi))
++ {
++#ifdef HIF_NAPI_STATS
++ hif->napi_counters[NAPI_SCHED_COUNT]++;
++#endif
++ __napi_schedule(&hif->napi);
++ }
++ }
++
++ if (int_status) {
++ printk(KERN_INFO "%s : Invalid interrupt : %d\n", __func__, int_status);
++ writel(int_status, HIF_INT_SRC);
++ }
++
++ return IRQ_HANDLED;
++}
++
++
++void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int data2)
++{
++ unsigned int client_id = data1;
++
++ if (client_id >= HIF_CLIENTS_MAX)
++ {
++ printk(KERN_ERR "%s: client id %d out of bounds\n", __func__, client_id);
++ return;
++ }
++
++ switch (req) {
++ case REQUEST_CL_REGISTER:
++ /* Request for register a client */
++ printk(KERN_INFO "%s: register client_id %d\n", __func__, client_id);
++ pfe_hif_client_register(hif, client_id, (struct hif_client_shm *)&hif->shm->client[client_id]);
++ break;
++
++ case REQUEST_CL_UNREGISTER:
++ printk(KERN_INFO "%s: unregister client_id %d\n", __func__, client_id);
++
++ /* Request for unregister a client */
++ pfe_hif_client_unregister(hif, client_id);
++
++ break;
++
++ default:
++ printk(KERN_ERR "%s: unsupported request %d\n", __func__, req);
++ break;
++ }
++
++ /*TODO check for TMU queue resume request */
++
++ /*Process client Tx queues
++ * Currently we don't have checking for tx pending*/
++}
++
++/** pfe_hif_rx_poll
++ * This function is NAPI poll function to process HIF Rx queue.
++ */
++static int pfe_hif_rx_poll(struct napi_struct *napi, int budget)
++{
++ struct pfe_hif *hif = container_of(napi, struct pfe_hif, napi);
++ int work_done;
++
++#ifdef HIF_NAPI_STATS
++ hif->napi_counters[NAPI_POLL_COUNT]++;
++#endif
++
++ work_done = pfe_hif_rx_process(hif, budget);
++
++ if (work_done < budget)
++ {
++ napi_complete(napi);
++ writel_relaxed(HIF_INT_MASK, HIF_INT_ENABLE);
++ }
++#ifdef HIF_NAPI_STATS
++ else
++ hif->napi_counters[NAPI_FULL_BUDGET_COUNT]++;
++#endif
++
++ return work_done;
++}
++
++/* pfe_hif_init
++ * This function initializes the baseaddresses and irq, etc.
++ */
++int pfe_hif_init(struct pfe *pfe)
++{
++ struct pfe_hif *hif = &pfe->hif;
++ int err;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ hif->dev = pfe->dev;
++ hif->irq = pfe->hif_irq;
++
++ if ((err = pfe_hif_alloc_descr(hif))) {
++ goto err0;
++ }
++
++ if (pfe_hif_init_buffers(hif)) {
++ printk(KERN_ERR "%s: Could not initialize buffer descriptors\n", __func__);
++ err = -ENOMEM;
++ goto err1;
++ }
++
++ /* Initilize NAPI for Rx processing */
++ init_dummy_netdev(&hif->dummy_dev);
++ netif_napi_add(&hif->dummy_dev, &hif->napi, pfe_hif_rx_poll, HIF_RX_POLL_WEIGHT);
++ napi_enable(&hif->napi);
++
++ spin_lock_init(&hif->tx_lock);
++ spin_lock_init(&hif->lock);
++
++ hif_init();
++ hif_rx_enable();
++ hif_tx_enable();
++
++ /* Disable tx done interrupt */
++ writel(HIF_INT_MASK, HIF_INT_ENABLE);
++
++ gpi_enable(HGPI_BASE_ADDR);
++
++#ifdef __KERNEL__
++ err = request_irq(hif->irq, hif_isr, 0, "pfe_hif", hif);
++ if (err) {
++ printk(KERN_ERR "%s: failed to get the hif IRQ = %d\n", __func__, hif->irq);
++ goto err1;
++ }
++#else
++ /*TODO register interrupts */
++#endif
++
++ return 0;
++err1:
++ pfe_hif_free_descr(hif);
++err0:
++ return err;
++}
++
++/* pfe_hif_exit-
++ */
++void pfe_hif_exit(struct pfe *pfe)
++{
++ struct pfe_hif *hif = &pfe->hif;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ spin_lock_bh(&hif->lock);
++ hif->shm->gClient_status[0] = 0;
++ hif->shm->gClient_status[1] = 0; /* Make sure all clients are disabled */
++
++ spin_unlock_bh(&hif->lock);
++
++ /*Disable Rx/Tx */
++ gpi_disable(HGPI_BASE_ADDR);
++ hif_rx_disable();
++ hif_tx_disable();
++
++ napi_disable(&hif->napi);
++ netif_napi_del(&hif->napi);
++
++#ifdef __KERNEL__
++ free_irq(hif->irq, hif);
++#endif
++ pfe_hif_release_buffers(hif);
++ pfe_hif_free_descr(hif);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hif.h
+@@ -0,0 +1,322 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _PFE_HIF_H_
++#define _PFE_HIF_H_
++
++#include <linux/netdevice.h>
++
++#define HIF_NAPI_STATS
++
++#define HIF_CLIENT_QUEUES_MAX 16
++#define HIF_RX_POLL_WEIGHT 64
++
++#define HIF_RX_PKT_MIN_SIZE 0x800 /* 2KB */
++#define HIF_RX_PKT_MIN_SIZE_MASK ~(HIF_RX_PKT_MIN_SIZE - 1)
++#define ROUND_MIN_RX_SIZE(_sz) ((_sz + (HIF_RX_PKT_MIN_SIZE - 1)) & HIF_RX_PKT_MIN_SIZE_MASK)
++#define PRESENT_OFST_IN_PAGE(_buf) (((unsigned long int)_buf & (PAGE_SIZE - 1)) & HIF_RX_PKT_MIN_SIZE_MASK)
++
++enum {
++ NAPI_SCHED_COUNT = 0,
++ NAPI_POLL_COUNT,
++ NAPI_PACKET_COUNT,
++ NAPI_DESC_COUNT,
++ NAPI_FULL_BUDGET_COUNT,
++ NAPI_CLIENT_FULL_COUNT,
++ NAPI_MAX_COUNT
++};
++
++
++/* XXX HIF_TX_DESC_NT value should be always greter than 4,
++ * Otherwise HIF_TX_POLL_MARK will become zero.
++ */
++#if defined(CONFIG_PLATFORM_PCI)
++#define HIF_RX_DESC_NT 4
++#define HIF_TX_DESC_NT 4
++#else
++#if defined(CONFIG_COMCERTO_64K_PAGES)
++#define HIF_RX_DESC_NT 64
++#else
++#define HIF_RX_DESC_NT 256
++#endif
++#define HIF_TX_DESC_NT 2048
++#endif
++
++#define HIF_FIRST_BUFFER (1 << 0)
++#define HIF_LAST_BUFFER (1 << 1)
++#define HIF_DONT_DMA_MAP (1 << 2) //TODO merge it with TSO
++#define HIF_DATA_VALID (1 << 3)
++#define HIF_TSO (1 << 4)
++
++#define MAX_VAP_SUPPORT 3
++#define MAX_WIFI_VAPS MAX_VAP_SUPPORT
++
++enum {
++ PFE_CL_GEM0 = 0,
++ PFE_CL_GEM1,
++ PFE_CL_GEM2,
++ PFE_CL_VWD0,
++ PFE_CL_VWD_LAST = PFE_CL_VWD0 + MAX_VAP_SUPPORT,
++ PFE_CL_PCAP0,
++ HIF_CLIENTS_MAX
++};
++
++/*structure to store client queue info */
++struct hif_rx_queue {
++ struct rx_queue_desc *base;
++ u32 size;
++ u32 write_idx;
++};
++
++struct hif_tx_queue {
++ struct tx_queue_desc *base;
++ u32 size;
++ u32 ack_idx;
++};
++
++/*Structure to store the client info */
++struct hif_client {
++ int rx_qn;
++ struct hif_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX];
++ int tx_qn;
++ struct hif_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX];
++};
++
++/*HIF hardware buffer descriptor */
++struct hif_desc {
++ volatile u32 ctrl;
++ volatile u32 status;
++ volatile u32 data;
++ volatile u32 next;
++};
++
++struct __hif_desc {
++ u32 ctrl;
++ u32 status;
++ u32 data;
++};
++
++struct hif_desc_sw {
++ dma_addr_t data;
++ u16 len;
++ u8 client_id;
++ u8 q_no;
++ u16 flags;
++};
++
++struct hif_hdr {
++ u8 client_id;
++ u8 qNo;
++ u16 client_ctrl;
++ u16 client_ctrl1;
++};
++
++struct __hif_hdr {
++ union {
++ struct hif_hdr hdr;
++ u32 word[2];
++ };
++};
++
++struct hif_lro_hdr {
++ u16 data_offset;
++ u16 mss;
++};
++
++struct hif_ipsec_hdr {
++ u16 sa_handle[2];
++}__attribute__((packed));
++
++#define MAX_TSO_BUF_DESCS 5
++struct hif_tso_buf_desc {
++ u32 addr;
++ u32 ctrl;
++#define TSO_CTRL_LAST_BUFFER (1 << 31)
++};
++
++struct hif_tso_hdr {
++ struct hif_hdr pkt_hdr;
++ u16 ip_off;
++ u16 ip_id;
++ u16 ip_len;
++ u16 tcp_off;
++ u32 tcp_seq;
++} __attribute__((packed));
++
++struct hif_tso_hdr_nocpy {
++ struct hif_tso_hdr tso_hdr;
++ struct hif_tso_buf_desc bdesc[MAX_TSO_BUF_DESCS];
++} __attribute__((packed));
++
++struct hif_pcap_hdr {
++ u8 ifindex;
++ u8 unused;
++ u16 seqno;
++ u32 timestamp;
++}__attribute__((packed));
++
++/* HIF_CTRL_TX... defines */
++#define HIF_CTRL_TX_TSO_NOCPY (1 << 8)
++#define HIF_CTRL_TX_IPSEC_OUT (1 << 7)
++#define HIF_CTRL_TX_OWN_MAC (1 << 6)
++#define HIF_CTRL_TX_TSO_END (1 << 5)
++#define HIF_CTRL_TX_TSO6 (1 << 4)
++#define HIF_CTRL_TX_TSO (1 << 3)
++#define HIF_CTRL_TX_CHECKSUM (1 << 2)
++#define HIF_CTRL_TX_CSUM_VALIDATE (1 << 1)
++#define HIF_CTRL_TX_WIFI (1 << 0)
++
++/* HIF_CTRL_RX... defines */
++#define HIF_CTRL_RX_OFFSET_OFST (24)
++#define HIF_CTRL_RX_PE_ID_OFST (16)
++#define HIF_CTRL_RX_IPSEC_IN (1 << 4)
++#define HIF_CTRL_RX_WIFI_EXPT (1 << 3)
++#define HIF_CTRL_RX_CHECKSUMMED (1 << 2)
++#define HIF_CTRL_RX_CONTINUED (1 << 1)
++#define HIF_CTRL_RX_WIFI_HEADROOM (1 << 0)
++
++#define HIF_CTRL_VAPID_OFST (8)
++
++struct pfe_hif {
++ /* To store registered clients in hif layer */
++ struct hif_client client[HIF_CLIENTS_MAX];
++ struct hif_shm *shm;
++ int irq;
++
++ void *descr_baseaddr_v;
++ unsigned long descr_baseaddr_p;
++
++ struct hif_desc *RxBase;
++ u32 RxRingSize;
++ u32 RxtocleanIndex;
++ void *rx_buf_addr[HIF_RX_DESC_NT];
++ int rx_buf_len[HIF_RX_DESC_NT];
++ unsigned int qno;
++ unsigned int client_id;
++ unsigned int client_ctrl;
++ unsigned int started;
++
++ struct hif_desc *TxBase;
++ u32 TxRingSize;
++ u32 Txtosend;
++ u32 Txtoclean;
++ u32 TxAvail;
++ u32 Txtoflush;
++ struct hif_desc_sw tx_sw_queue[HIF_TX_DESC_NT];
++ struct hif_tso_hdr_nocpy *tso_hdr_v;
++ dma_addr_t tso_hdr_p;
++
++ spinlock_t tx_lock;
++ spinlock_t lock;
++ struct net_device dummy_dev;
++ struct napi_struct napi;
++ struct device *dev;
++
++#ifdef CONFIG_HOTPLUG_CPU
++ struct notifier_block cpu_notify;
++#endif
++
++#ifdef HIF_NAPI_STATS
++ unsigned int napi_counters[NAPI_MAX_COUNT];
++#endif
++};
++
++void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no, void *data, u32 len, unsigned int flags);
++int hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no, void *data, unsigned int len);
++void __hif_tx_done_process(struct pfe_hif *hif, int count);
++void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int data2);
++int pfe_hif_init(struct pfe *pfe);
++void pfe_hif_exit(struct pfe *pfe);
++
++static inline void hif_tx_done_process(struct pfe_hif *hif, int count)
++{
++ spin_lock_bh(&hif->tx_lock);
++ __hif_tx_done_process(hif, count);
++ spin_unlock_bh(&hif->tx_lock);
++}
++
++static inline void hif_tx_lock(struct pfe_hif *hif)
++{
++ spin_lock_bh(&hif->tx_lock);
++}
++
++static inline void hif_tx_unlock(struct pfe_hif *hif)
++{
++ spin_unlock_bh(&hif->tx_lock);
++}
++
++static inline int __hif_tx_avail(struct pfe_hif *hif)
++{
++ return hif->TxAvail;
++}
++
++#if defined(CONFIG_PLATFORM_C2000)
++static inline void __memcpy8(void *dst, void *src)
++{
++ asm volatile ( "ldm %1, {r9, r10}\n\t"
++ "stm %0, {r9, r10}\n\t"
++ :
++ : "r" (dst), "r" (src)
++ : "r9", "r10", "memory"
++ );
++}
++
++static inline void __memcpy12(void *dst, void *src)
++{
++ asm volatile ( "ldm %1, {r8, r9, r10}\n\t"
++ "stm %0, {r8, r9, r10}\n\t"
++ :
++ : "r" (dst), "r" (src)
++ : "r8", "r9", "r10", "memory"
++ );
++}
++
++static inline void __memcpy16(void *dst, void *src)
++{
++ asm volatile ( "ldm %1, {r7, r8, r9, r10}\n\t"
++ "stm %0, {r7, r8, r9, r10}\n\t"
++ :
++ : "r"(dst), "r"(src)
++ : "r7", "r8", "r9", "r10", "memory"
++ );
++}
++
++#define HIF_MEMCPY_BURSTSIZE 32 /*__memcpy copy 32byte in a burst*/
++static inline void __memcpy(void *dst, void *src, unsigned int len)
++{
++ void *end = src + len;
++
++ dst = (void *)((unsigned long)dst & ~0x3);
++ src = (void *)((unsigned long)src & ~0x3);
++
++ while (src < end) {
++ asm volatile ( "ldm %1!, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t"
++ "stm %0!, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t"
++ : "+r"(dst), "+r"(src)
++ :
++ : "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "memory"
++ );
++ }
++}
++#else
++#define __memcpy8(dst, src) memcpy(dst, src, 8)
++#define __memcpy12(dst, src) memcpy(dst, src, 12)
++#define __memcpy(dst, src, len) memcpy(dst, src, len)
++#endif
++#endif /* _PFE_HIF_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.c
+@@ -0,0 +1,658 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/version.h>
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
++#include <asm/system.h>
++#endif
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/workqueue.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/sched.h>
++#include <linux/skbuff.h>
++#include <linux/moduleparam.h>
++#include <linux/cpu.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++//#include <asm/system_info.h>
++#endif
++
++#include "pfe_mod.h"
++#include "pfe_hif.h"
++#include "pfe_hif_lib.h"
++#include "pfe_ctrl_hal.h"
++
++
++unsigned int lro_mode = 0;
++unsigned int page_mode = 0;
++unsigned int tx_qos = 0;
++unsigned int pfe_pkt_size;
++unsigned int pfe_pkt_headroom;
++unsigned int emac_txq_cnt;
++
++/** @pfe_hal_lib.c.
++ * Common functions used by HIF client drivers
++ */
++
++/*HIF shared memory Global variable */
++struct hif_shm ghif_shm;
++
++/* TMU tx transmitted packets counter, 1 per TMU */
++unsigned int TMU_DMEM_SH(tx_trans)[EMAC_TXQ_CNT];
++
++/* Cleanup the HIF shared memory, release HIF rx_buffer_pool.
++ * This function should be called after pfe_hif_exit
++ *
++ * @param[in] hif_shm Shared memory address location in DDR
++ */
++static void pfe_hif_shm_clean(struct hif_shm *hif_shm)
++{
++ int i;
++ void *pkt;
++
++ for (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) {
++ pkt = hif_shm->rx_buf_pool[i];
++ if (pkt) {
++ hif_shm->rx_buf_pool[i] = NULL;
++ pkt -= pfe_pkt_headroom;
++
++ if (page_mode) {
++ put_page(virt_to_page(pkt));
++ } else
++ kfree(pkt);
++ }
++ }
++}
++
++/* Initialize shared memory used between HIF driver and clients,
++ * allocate rx_buffer_pool required for HIF Rx descriptors.
++ * This function should be called before initializing HIF driver.
++ *
++ * @param[in] hif_shm Shared memory address location in DDR
++ * @rerurn 0 - on succes, <0 on fail to initialize
++ */
++static int pfe_hif_shm_init(struct hif_shm *hif_shm)
++{
++ int i;
++ void *pkt;
++
++ memset(hif_shm, 0, sizeof(struct hif_shm));
++ hif_shm->rx_buf_pool_cnt = HIF_RX_DESC_NT;
++
++ for (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) {
++ if (page_mode) {
++ pkt = (void *)__get_free_page(GFP_KERNEL | GFP_DMA_PFE);
++ } else
++ pkt = kmalloc(PFE_BUF_SIZE, GFP_KERNEL | GFP_DMA_PFE);
++
++ if (pkt)
++ hif_shm->rx_buf_pool[i] = pkt + pfe_pkt_headroom;
++ else
++ goto err0;
++ }
++
++ return 0;
++
++err0:
++ printk(KERN_ERR "%s Low memory\n", __func__);
++ pfe_hif_shm_clean(hif_shm);
++ return -ENOMEM;
++}
++
++/*This function sends indication to HIF driver
++ *
++ * @param[in] hif hif context
++ **/
++static void hif_lib_indicate_hif(struct pfe_hif *hif, int req, int data1, int data2)
++{
++ //TODO : If we separate HIF and HIF LIB, then send req and data through shared memory.
++
++ hif_process_client_req(hif, req, data1, data2);
++}
++
++void hif_lib_indicate_client(int client_id, int event_type, int qno)
++{
++ struct hif_client_s *client = pfe->hif_client[client_id];
++
++ /*
++ * TODO : Right now, all events are queue number based. So we are masking events per queue
++ * basis. Later if we add any events those do not depend on queue number, then we may
++ * may need may need to add masking per event.
++ */
++ if (!client || (event_type >= HIF_EVENT_MAX) || (qno >= HIF_CLIENT_QUEUES_MAX) )
++ return;
++
++ if (!test_and_set_bit(qno, &client->queue_mask[event_type])) {
++ client->event_handler(client->priv, event_type, qno);
++ }
++
++}
++
++
++/*This function releases Rx queue descriptors memory and pre-filled buffers
++ *
++ * @param[in] client hif_client context
++ */
++static void hif_lib_client_release_rx_buffers(struct hif_client_s *client)
++{
++ struct rx_queue_desc *desc;
++ int qno, ii;
++ void *buf;
++
++ for (qno = 0; qno < client->rx_qn; qno++) {
++ desc = client->rx_q[qno].base;
++
++ for (ii = 0; ii < client->rx_q[qno].size; ii++) {
++ buf = (void *)desc->data;
++ if (buf) {
++ buf -= pfe_pkt_headroom;
++
++ if (page_mode)
++ free_page((unsigned long)buf);
++ else
++ kfree(buf);
++
++ desc->ctrl = 0;
++ }
++
++ desc++;
++ }
++ }
++
++ kfree(client->rx_qbase);
++}
++
++
++/*This function allocates memory for the rxq descriptors and pre-fill rx queues
++ * with buffers.
++ * @param[in] client client context
++ * @param[in] q_size size of the rxQ, all queues are of same size
++ */
++static int hif_lib_client_init_rx_buffers(struct hif_client_s *client, int q_size)
++{
++ struct rx_queue_desc *desc;
++ struct hif_client_rx_queue *queue;
++ int ii, qno;
++
++ /*Allocate memory for the client queues */
++ client->rx_qbase = kzalloc(client->rx_qn * q_size * sizeof(struct rx_queue_desc), GFP_KERNEL);
++ if (!client->rx_qbase){
++ goto err;
++ }
++
++ for (qno = 0; qno < client->rx_qn; qno++) {
++ queue = &client->rx_q[qno];
++
++ queue->base = client->rx_qbase + qno * q_size * sizeof(struct rx_queue_desc);
++ queue->size = q_size;
++ queue->read_idx = 0;
++ queue->write_idx = 0;
++
++ dbg_print_info("rx queue: %d, base: %p, size: %d \n", qno, queue->base, queue->size);
++ }
++
++ for (qno = 0; qno < client->rx_qn; qno++) {
++ queue = &client->rx_q[qno];
++ desc = queue->base;
++
++ for (ii = 0; ii < queue->size; ii++) {
++ desc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) | CL_DESC_OWN;
++ desc++;
++ }
++ }
++
++ return 0;
++
++err:
++ return 1;
++}
++
++#define inc_cl_idx(idxname) idxname = (idxname+1) & (queue->size-1)
++
++static void hif_lib_client_cleanup_tx_queue(struct hif_client_tx_queue *queue)
++{
++ dbg_print_info( "%s\n", __func__);
++
++ /* Check if there are any pending packets. Client must flush the tx queues
++ before unregistering, by calling by calling hif_lib_tx_get_next_complete() */
++ /* Hif no longer calls since we are no longer registered */
++
++ if (queue->tx_pending)
++ printk(KERN_ERR "%s: pending transmit packets\n", __func__);
++}
++
++static void hif_lib_client_release_tx_buffers(struct hif_client_s *client)
++{
++ int qno;
++
++ dbg_print_info("%s\n", __func__);
++
++ for (qno = 0; qno < client->tx_qn; qno++) {
++ hif_lib_client_cleanup_tx_queue(&client->tx_q[qno]);
++ }
++
++ kfree(client->tx_qbase);
++}
++
++static int hif_lib_client_init_tx_buffers(struct hif_client_s *client, int q_size)
++{
++ struct hif_client_tx_queue *queue;
++ int qno;
++
++ client->tx_qbase = kzalloc(client->tx_qn * q_size * sizeof(struct tx_queue_desc), GFP_KERNEL);
++ if (!client->tx_qbase) {
++ return 1;
++ }
++
++ for (qno = 0; qno < client->tx_qn; qno++) {
++ queue = &client->tx_q[qno];
++
++ queue->base = client->tx_qbase + qno * q_size * sizeof(struct tx_queue_desc);
++ queue->size = q_size;
++ queue->read_idx = 0;
++ queue->write_idx = 0;
++ queue->tx_pending = 0;
++ queue->nocpy_flag = 0;
++ queue->prev_tmu_tx_pkts = 0;
++ queue->done_tmu_tx_pkts = 0;
++
++ dbg_print_info("tx queue: %d, base: %p, size: %d \n", qno, queue->base, queue->size);
++ }
++
++ return 0;
++}
++
++static int hif_lib_event_dummy( void *priv, int event_type, int qno)
++{
++ return 0;
++}
++
++int hif_lib_client_register(struct hif_client_s *client)
++{
++ struct hif_shm *hif_shm;
++ struct hif_client_shm *client_shm;
++ int err, i;
++// int loop_cnt = 0;
++
++ dbg_print_info("%s\n", __func__);
++
++ /*Allocate memory before spin_lock*/
++ if (hif_lib_client_init_rx_buffers(client, client->rx_qsize)) {
++ err = -ENOMEM;
++ goto err_rx;
++ }
++
++ if (hif_lib_client_init_tx_buffers(client, client->tx_qsize)) {
++ err = -ENOMEM;
++ goto err_tx;
++ }
++
++ spin_lock_bh(&pfe->hif.lock);
++ if (!(client->pfe) || (client->id >= HIF_CLIENTS_MAX) || (pfe->hif_client[client->id])) {
++ err = -EINVAL;
++ goto err;
++ }
++
++ hif_shm = client->pfe->hif.shm;
++
++ if (!client->event_handler)
++ client->event_handler = hif_lib_event_dummy;
++
++ /*Initialize client specific shared memory */
++ client_shm = (struct hif_client_shm *)&hif_shm->client[client->id];
++ client_shm->rx_qbase = (unsigned long int)client->rx_qbase;
++ client_shm->rx_qsize = client->rx_qsize;
++ client_shm->tx_qbase = (unsigned long int)client->tx_qbase;
++ client_shm->tx_qsize = client->tx_qsize;
++ client_shm->ctrl = (client->tx_qn << CLIENT_CTRL_TX_Q_CNT_OFST) | (client->rx_qn << CLIENT_CTRL_RX_Q_CNT_OFST);
++// spin_lock_init(&client->rx_lock);
++
++ for (i = 0; i < HIF_EVENT_MAX; i++) {
++ client->queue_mask[i] = 0; /* By default all events are unmasked */
++ }
++
++ /*Indicate to HIF driver*/
++ hif_lib_indicate_hif(&pfe->hif, REQUEST_CL_REGISTER, client->id, 0);
++
++ dbg_print_info("%s: client: %p, client_id: %d, tx_qsize: %d, rx_qsize: %d\n",
++ __func__, client, client->id, client->tx_qsize, client->rx_qsize);
++
++ client->cpu_id = -1;
++
++ pfe->hif_client[client->id] = client;
++ spin_unlock_bh(&pfe->hif.lock);
++
++ return 0;
++
++err:
++ spin_unlock_bh(&pfe->hif.lock);
++ hif_lib_client_release_tx_buffers(client);
++
++err_tx:
++ hif_lib_client_release_rx_buffers(client);
++
++err_rx:
++ return err;
++}
++
++int hif_lib_client_unregister(struct hif_client_s *client)
++{
++ struct pfe *pfe = client->pfe;
++ u32 client_id = client->id;
++
++ printk(KERN_INFO "%s : client: %p, client_id: %d, txQ_depth: %d, rxQ_depth: %d\n",
++ __func__, client, client->id, client->tx_qsize, client->rx_qsize);
++
++
++ spin_lock_bh(&pfe->hif.lock);
++ hif_lib_indicate_hif(&pfe->hif, REQUEST_CL_UNREGISTER, client->id, 0);
++
++ hif_lib_client_release_tx_buffers(client);
++ hif_lib_client_release_rx_buffers(client);
++ pfe->hif_client[client_id] = NULL;
++ spin_unlock_bh(&pfe->hif.lock);
++
++ return 0;
++}
++
++int hif_lib_event_handler_start(struct hif_client_s *client, int event, int qno)
++{
++ struct hif_client_rx_queue *queue = &client->rx_q[qno];
++ struct rx_queue_desc *desc = queue->base + queue->read_idx;
++
++ if ((event >= HIF_EVENT_MAX) || ( qno >= HIF_CLIENT_QUEUES_MAX)) {
++ dbg_print_info("%s: Unsupported event : %d queue number : %d\n", __func__, event, qno);
++ return -1;
++ }
++
++ test_and_clear_bit(qno, &client->queue_mask[event]);
++
++ switch (event) {
++ case EVENT_RX_PKT_IND:
++ if (!(desc->ctrl & CL_DESC_OWN))
++ hif_lib_indicate_client(client->id, EVENT_RX_PKT_IND, qno);
++ break;
++
++ case EVENT_HIGH_RX_WM:
++ case EVENT_TXDONE_IND:
++ default:
++ break;
++ }
++
++ return 0;
++}
++
++
++/*This function gets one packet from the specified client queue
++ * It also refill the rx buffer */
++void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int *ofst, unsigned int *rx_ctrl, unsigned int *desc_ctrl, void **priv_data)
++{
++ struct hif_client_rx_queue *queue = &client->rx_q[qno];
++ struct rx_queue_desc *desc;
++ void *pkt = NULL;
++
++ //printk(KERN_INFO "%s\n", __func__);
++#if defined(CONFIG_PLATFORM_EMULATION)
++ printk(KERN_INFO "%s:qno:%d cid:%d desc:%p rdidx:%d \n",
++ __func__, qno, client->id, desc,
++ queue->read_idx);
++#endif
++
++ /* Following lock is to protect rx queue access from, hif_lib_event_handler_start.
++ * In general below lock is not required, because hif_lib_xmit_pkt and
++ * hif_lib_event_handler_start are called from napi poll and which is not
++ * re-entrant. But if some client use in different way this lock is required.
++ */
++ //spin_lock_irqsave(&client->rx_lock, flags);
++ desc = queue->base + queue->read_idx;
++ if (!(desc->ctrl & CL_DESC_OWN)) {
++ pkt = desc->data - pfe_pkt_headroom;
++
++ *rx_ctrl = desc->client_ctrl;
++ *desc_ctrl = desc->ctrl;
++
++ if (desc->ctrl & CL_DESC_FIRST) {
++ u16 size = *rx_ctrl >> HIF_CTRL_RX_OFFSET_OFST;
++
++ if (size) {
++ *len = CL_DESC_BUF_LEN(desc->ctrl) - PFE_PKT_HEADER_SZ - size;
++ *ofst = pfe_pkt_headroom + PFE_PKT_HEADER_SZ + size;
++ *priv_data = desc->data + PFE_PKT_HEADER_SZ;
++ } else {
++ *len = CL_DESC_BUF_LEN(desc->ctrl) - PFE_PKT_HEADER_SZ;
++ *ofst = pfe_pkt_headroom + PFE_PKT_HEADER_SZ;
++ *priv_data = NULL;
++ }
++
++ } else {
++ *len = CL_DESC_BUF_LEN(desc->ctrl);
++ *ofst = pfe_pkt_headroom;
++ }
++
++ desc->data = NULL; // Needed so we don't free a buffer/page twice on module_exit
++ smp_wmb();
++
++ desc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) | CL_DESC_OWN;
++ inc_cl_idx(queue->read_idx);
++ }
++
++ //spin_unlock_irqrestore(&client->rx_lock, flags);
++ return pkt;
++}
++
++static inline void hif_hdr_write(struct hif_hdr *pkt_hdr, unsigned int client_id, unsigned int qno, u32 client_ctrl)
++{
++ /* Optimize the write since the destinaton may be non-cacheable */
++ if (!((unsigned long)pkt_hdr & 0x3)) {
++ ((u32 *)pkt_hdr)[0] = (client_ctrl << 16) | (qno << 8) | client_id;
++ } else {
++ ((u16 *)pkt_hdr)[0] = (qno << 8) | (client_id & 0xFF);
++ ((u16 *)pkt_hdr)[1] = (client_ctrl & 0xFFFF);
++ }
++}
++
++/*This function puts the given packet in the specific client queue */
++void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void *data, unsigned int len, u32 client_ctrl, unsigned int flags, void *client_data)
++{
++ struct hif_client_tx_queue *queue = &client->tx_q[qno];
++ struct tx_queue_desc *desc = queue->base + queue->write_idx;
++
++ //printk(KERN_INFO "%s\n",__func__);
++
++ /* First buffer */
++ if (flags & HIF_FIRST_BUFFER)
++ {
++ data -= sizeof(struct hif_hdr);
++ len += sizeof(struct hif_hdr);
++
++ hif_hdr_write(data, client->id, qno, client_ctrl);
++ }
++
++ desc->data = client_data;
++ desc->ctrl = CL_DESC_OWN | CL_DESC_FLAGS(flags);
++
++ __hif_xmit_pkt(&pfe->hif, client->id, qno, data, len, flags);
++
++ inc_cl_idx(queue->write_idx);
++ queue->tx_pending++;
++ queue->jiffies_last_packet = jiffies;
++
++}
++
++/*This function puts the given packet in the specific client queue */
++int hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void *data, unsigned int len, u32 client_ctrl, void *client_data)
++{
++ struct hif_client_tx_queue *queue = &client->tx_q[qno];
++ struct tx_queue_desc *desc = queue->base + queue->write_idx;
++
++ //printk(KERN_INFO "%s\n",__func__);
++
++ if (queue->tx_pending < queue->size) {
++ /*Construct pkt header */
++
++ data -= sizeof(struct hif_hdr);
++ len += sizeof(struct hif_hdr);
++
++ hif_hdr_write(data, client->id, qno, client_ctrl);
++
++ desc->data = client_data;
++ desc->ctrl = CL_DESC_OWN | CL_DESC_FLAGS(HIF_FIRST_BUFFER | HIF_LAST_BUFFER | HIF_DATA_VALID);
++
++ if (hif_xmit_pkt(&pfe->hif, client->id, qno, data, len))
++ return 1;
++
++ inc_cl_idx(queue->write_idx);
++ queue->tx_pending++;
++ queue->jiffies_last_packet = jiffies;
++
++ return 0;
++ }
++
++ dbg_print_info("%s Tx client %d qno %d is full\n",__func__, client->id, qno);
++ return 1;
++}
++
++void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno, unsigned int *flags, int count)
++{
++ struct hif_client_tx_queue *queue = &client->tx_q[qno];
++ struct tx_queue_desc *desc = queue->base + queue->read_idx;
++
++ dbg_print_info("%s: qno : %d rd_indx: %d pending:%d\n",__func__, qno, queue->read_idx, queue->tx_pending);
++
++ if (!queue->tx_pending )
++ return NULL;
++
++ if (queue->nocpy_flag && !queue->done_tmu_tx_pkts) {
++ u32 tmu_tx_pkts = be32_to_cpu(pe_dmem_read(TMU0_ID + client->id, virt_to_tmu_dmem(&tx_trans[qno]), 4));
++
++ if (queue->prev_tmu_tx_pkts > tmu_tx_pkts)
++ queue->done_tmu_tx_pkts = UINT_MAX - queue->prev_tmu_tx_pkts + tmu_tx_pkts;
++ else
++ queue->done_tmu_tx_pkts = tmu_tx_pkts - queue->prev_tmu_tx_pkts;
++
++ queue->prev_tmu_tx_pkts = tmu_tx_pkts;
++
++ if (!queue->done_tmu_tx_pkts) {
++ return NULL;
++ }
++ }
++
++ if (desc->ctrl & CL_DESC_OWN) {
++ hif_tx_done_process(&pfe->hif, count);
++
++ //Check again, if packets done in tx queue.
++ if (desc->ctrl & CL_DESC_OWN)
++ return NULL;
++ }
++
++ inc_cl_idx(queue->read_idx);
++ queue->tx_pending--;
++
++ *flags = CL_DESC_GET_FLAGS(desc->ctrl);
++
++ if (queue->done_tmu_tx_pkts && (*flags & HIF_LAST_BUFFER))
++ queue->done_tmu_tx_pkts--;
++
++
++ return desc->data;
++}
++
++//FIXME: TMU queues length mapping needs to be declared in shared PFE/PFE_CTRL header
++static void hif_lib_tmu_credit_init(struct pfe *pfe)
++{
++ int i, q;
++
++ for (i = 0; i < NUM_GEMAC_SUPPORT; i++)
++ for (q = 0; q < emac_txq_cnt; q++) {
++ pfe->tmu_credit.tx_credit_max[i][q] = (q == 0) ? DEFAULT_Q0_QDEPTH : DEFAULT_MAX_QDEPTH;
++ pfe->tmu_credit.tx_credit[i][q] = pfe->tmu_credit.tx_credit_max[i][q];
++ }
++}
++/** __hif_lib_update_credit
++ *
++ * @param[in] client hif client context
++ * @param[in] queue queue number in match with TMU
++ */
++void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue)
++{
++ unsigned int tmu_tx_packets, tmp;
++
++ if (tx_qos) {
++ tmu_tx_packets = be32_to_cpu(pe_dmem_read(TMU0_ID + client->id, virt_to_tmu_dmem(&tx_trans[queue]), 4));
++
++ // tx_packets counter overflowed
++ if (tmu_tx_packets > pfe->tmu_credit.tx_packets[client->id][queue]) {
++ tmp = UINT_MAX - tmu_tx_packets + pfe->tmu_credit.tx_packets[client->id][queue];
++ pfe->tmu_credit.tx_credit[client->id][queue] = pfe->tmu_credit.tx_credit_max[client->id][queue] - tmp;
++ }
++ // TMU tx <= pfe_eth tx, normal case or both OF since last time
++ else
++ pfe->tmu_credit.tx_credit[client->id][queue] = pfe->tmu_credit.tx_credit_max[client->id][queue] - (pfe->tmu_credit.tx_packets[client->id][queue] - tmu_tx_packets);
++ }
++}
++
++/** hif_lib_update_credit
++ *
++ * @param[in] client hif client context
++ * @param[in] queue queue number in match with TMU
++ */
++void hif_lib_update_credit(struct hif_client_s *client, unsigned int queue)
++{
++ spin_lock_bh(&pfe->hif.tx_lock);
++ __hif_lib_update_credit(client, queue);
++ spin_unlock_bh(&pfe->hif.tx_lock);
++}
++
++int pfe_hif_lib_init(struct pfe *pfe)
++{
++ int rc;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ if (lro_mode) {
++ page_mode = 1;
++ pfe_pkt_size = min(PAGE_SIZE, MAX_PFE_PKT_SIZE);
++ pfe_pkt_headroom = 0;
++ } else {
++ page_mode = 0;
++ pfe_pkt_size = PFE_PKT_SIZE;
++ pfe_pkt_headroom = PFE_PKT_HEADROOM;
++ }
++
++ if (tx_qos)
++ emac_txq_cnt = EMAC_TXQ_CNT / 2;
++ else
++ emac_txq_cnt = EMAC_TXQ_CNT;
++
++ hif_lib_tmu_credit_init(pfe);
++ pfe->hif.shm = &ghif_shm;
++ rc = pfe_hif_shm_init(pfe->hif.shm);
++
++ return rc;
++}
++
++
++void pfe_hif_lib_exit(struct pfe *pfe)
++{
++ printk(KERN_INFO "%s\n", __func__);
++
++ pfe_hif_shm_clean(pfe->hif.shm);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.h
+@@ -0,0 +1,219 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _PFE_HIF_LIB_H_
++#define _PFE_HIF_LIB_H_
++
++#include "pfe_hif.h"
++
++#ifdef HIF_LIB_DEBUG
++#define dbg_print_info( fmt, args...) \
++ printk(KERN_INFO fmt, ##args)
++#else
++#define dbg_print_info( fmt, args...)
++#endif
++
++#define HIF_CL_REQ_TIMEOUT 10
++
++#if defined(CONFIG_COMCERTO_ZONE_DMA_NCNB)
++#define GFP_DMA_PFE (GFP_DMA_NCNB | __GFP_NOWARN)
++#else
++#define GFP_DMA_PFE 0
++#endif
++
++enum {
++ REQUEST_CL_REGISTER = 0,
++ REQUEST_CL_UNREGISTER,
++ HIF_REQUEST_MAX
++};
++
++enum {
++ EVENT_HIGH_RX_WM = 0, /* Event to indicate that client rx queue is reached water mark level */
++ EVENT_RX_PKT_IND, /* Event to indicate that, packet recieved for client */
++ EVENT_TXDONE_IND, /* Event to indicate that, packet tx done for client */
++ HIF_EVENT_MAX
++};
++
++/*structure to store client queue info */
++
++/*structure to store client queue info */
++struct hif_client_rx_queue {
++ struct rx_queue_desc *base;
++ u32 size;
++ u32 read_idx;
++ u32 write_idx;
++};
++
++struct hif_client_tx_queue {
++ struct tx_queue_desc *base;
++ u32 size;
++ u32 read_idx;
++ u32 write_idx;
++ u32 tx_pending;
++ unsigned long jiffies_last_packet;
++ u32 nocpy_flag;
++ u32 prev_tmu_tx_pkts;
++ u32 done_tmu_tx_pkts;
++ u32 cur_tso_hdr_p;
++ int tso_buf_cnt;
++};
++
++struct hif_client_s
++{
++ int id;
++ int tx_qn;
++ int rx_qn;
++ void *rx_qbase;
++ void *tx_qbase;
++ /* FIXME tx/rx_qsize fields can be removed after per queue depth is supported*/
++ int tx_qsize;
++ int rx_qsize;
++ int cpu_id;
++
++// spinlock_t rx_lock;
++ struct hif_client_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX];
++ struct hif_client_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX];
++ int (*event_handler)(void *priv, int event, int data);
++ unsigned long queue_mask[HIF_EVENT_MAX];
++ struct pfe *pfe;
++ void *priv;
++};
++
++
++/* Client specific shared memory
++ * It contains number of Rx/Tx queues, base addresses and queue sizes */
++struct hif_client_shm {
++ u32 ctrl; /*0-7: number of Rx queues, 8-15: number of tx queues */
++ unsigned long rx_qbase; /*Rx queue base address */
++ u32 rx_qsize; /*each Rx queue size, all Rx queues are of same size */
++ unsigned long tx_qbase; /* Tx queue base address */
++ u32 tx_qsize; /*each Tx queue size, all Tx queues are of same size */
++};
++
++/*Client shared memory ctrl bit description */
++#define CLIENT_CTRL_RX_Q_CNT_OFST 0
++#define CLIENT_CTRL_TX_Q_CNT_OFST 8
++#define CLIENT_CTRL_RX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_RX_Q_CNT_OFST) & 0xFF)
++#define CLIENT_CTRL_TX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_TX_Q_CNT_OFST) & 0xFF)
++
++
++
++/*Shared memory used to communicate between HIF driver and host/client drivers
++ * Before starting the hif driver rx_buf_pool ans rx_buf_pool_cnt should be
++ * initialized with host buffers and buffers count in the pool.
++ * rx_buf_pool_cnt should be >= HIF_RX_DESC_NT.
++ *
++ */
++struct hif_shm {
++ u32 rx_buf_pool_cnt; /*Number of rx buffers available*/
++ void *rx_buf_pool[HIF_RX_DESC_NT];/*Rx buffers required to initialize HIF rx descriptors */
++ unsigned long gClient_status[2]; /*Global client status bit mask */
++ u32 hif_qfull; /*TODO Client-id that caused for the TMU3 queue stop */
++ u32 hif_qresume; /*TODO */
++ struct hif_client_shm client[HIF_CLIENTS_MAX]; /* Client specific shared memory */
++};
++
++
++#define CL_DESC_OWN (1 << 31) /* This sets owner ship to HIF driver */
++#define CL_DESC_LAST (1 << 30) /* This indicates last packet for multi buffers handling */
++#define CL_DESC_FIRST (1 << 29) /* This indicates first packet for multi buffers handling */
++#define CL_DESC_BUF_LEN(x) ((x) & 0xFFFF)
++#define CL_DESC_FLAGS(x) (((x) & 0xF) << 16)
++#define CL_DESC_GET_FLAGS(x) (((x) >> 16) & 0xF)
++
++struct rx_queue_desc {
++ void *data;
++ u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/
++ u32 client_ctrl;
++};
++
++struct tx_queue_desc {
++ void *data;
++ u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/
++};
++
++/* HIF Rx is not working properly for 2-byte aligned buffers and
++ * ip_header should be 4byte aligned for better iperformance.
++ * "ip_header = 64 + 6(hif_header) + 14 (MAC Header)" will be 4byte aligned.
++ */
++#define PFE_PKT_HEADER_SZ sizeof(struct hif_hdr)
++#define PFE_BUF_SIZE 2048 /* must be big enough for headroom, pkt size and skb shared info */
++#define PFE_PKT_HEADROOM 128
++#define SKB_SHARED_INFO_SIZE 256 /* At least sizeof(struct skb_shared_info) bytes */
++
++//#define PFE_PKT_SIZE 1544 /* maximum ethernet packet size */
++#define PFE_PKT_SIZE (PFE_BUF_SIZE - PFE_PKT_HEADROOM - SKB_SHARED_INFO_SIZE) /* maximum ethernet packet size after reassembly offload*/
++#define MAX_L2_HDR_SIZE 14 /* Not correct for VLAN/PPPoE */
++#define MAX_L3_HDR_SIZE 20 /* Not correct for IPv6 */
++#define MAX_L4_HDR_SIZE 60 /* TCP with maximum options */
++#define MAX_HDR_SIZE (MAX_L2_HDR_SIZE + MAX_L3_HDR_SIZE + MAX_L4_HDR_SIZE)
++#define MAX_WIFI_HDR_SIZE (MAX_L2_HDR_SIZE + MAX_L3_HDR_SIZE + 6)
++#define MAX_PFE_PKT_SIZE 16380UL /* Used in page mode to clamp packet size to the maximum supported by the hif hw interface (<16KiB) */
++
++extern unsigned int pfe_pkt_size;
++extern unsigned int pfe_pkt_headroom;
++extern unsigned int page_mode;
++extern unsigned int lro_mode;
++extern unsigned int tx_qos;
++extern unsigned int emac_txq_cnt;
++
++int pfe_hif_lib_init(struct pfe *pfe);
++void pfe_hif_lib_exit(struct pfe *pfe);
++int hif_lib_client_register(struct hif_client_s *client);
++int hif_lib_client_unregister(struct hif_client_s *client);
++void __hif_lib_xmit_tso_hdr(struct hif_client_s *client, unsigned int qno, u32 client_ctrl, unsigned int ip_off, unsigned int ip_id, unsigned int ip_len, unsigned int tcp_off, unsigned int tcp_seq);
++void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void *data, unsigned int len, u32 client_ctrl, unsigned int flags, void *client_data);
++int hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void *data, unsigned int len, u32 client_ctrl, void *client_data);
++void hif_lib_indicate_client(int cl_id, int event, int data);
++int hif_lib_event_handler_start( struct hif_client_s *client, int event, int data );
++int hif_lib_tmu_queue_start( struct hif_client_s *client, int qno );
++int hif_lib_tmu_queue_stop( struct hif_client_s *client, int qno );
++void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno, unsigned int *flags, int count);
++void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int *ofst, unsigned int *rx_ctrl, unsigned int *desc_ctrl, void **priv_data);
++void hif_lib_update_credit(struct hif_client_s *client, unsigned int qno);
++void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue);
++void hif_lib_set_rx_cpu_affinity(struct hif_client_s *client, int cpu_id);
++void hif_lib_set_tx_queue_nocpy(struct hif_client_s *client, int qno, int enable);
++static inline int hif_lib_tx_avail(struct hif_client_s *client, unsigned int qno)
++{
++ struct hif_client_tx_queue *queue = &client->tx_q[qno];
++
++ return (queue->size - queue->tx_pending);
++}
++
++static inline int hif_lib_get_tx_wrIndex(struct hif_client_s *client, unsigned int qno)
++{
++ struct hif_client_tx_queue *queue = &client->tx_q[qno];
++
++ return queue->write_idx;
++}
++
++
++static inline int hif_lib_tx_pending(struct hif_client_s *client, unsigned int qno)
++{
++ struct hif_client_tx_queue *queue = &client->tx_q[qno];
++
++ return queue->tx_pending;
++}
++
++#define hif_lib_tx_credit_avail(pfe, id, qno) pfe->tmu_credit.tx_credit[id][qno]
++#define hif_lib_tx_credit_max(pfe, id, qno) pfe->tmu_credit.tx_credit_max[id][qno]
++#define hif_lib_tx_credit_use(pfe, id, qno, credit) do {if (tx_qos) {pfe->tmu_credit.tx_credit[id][qno]-= credit; pfe->tmu_credit.tx_packets[id][qno]+=credit;}} while (0)
++
++#endif /* _PFE_HIF_LIB_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hw.c
+@@ -0,0 +1,188 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include "pfe_mod.h"
++#include "pfe_hw.h"
++
++/* Functions to handle most of pfe hw register initialization */
++
++int pfe_hw_init(struct pfe *pfe, int resume)
++{
++ CLASS_CFG class_cfg = {
++ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO,
++ .route_table_baseaddr = pfe->ddr_phys_baseaddr + ROUTE_TABLE_BASEADDR,
++ .route_table_hash_bits = ROUTE_TABLE_HASH_BITS,
++ };
++
++ TMU_CFG tmu_cfg = {
++ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO,
++ .llm_base_addr = pfe->ddr_phys_baseaddr + TMU_LLM_BASEADDR,
++ .llm_queue_len = TMU_LLM_QUEUE_LEN,
++ };
++
++#if !defined(CONFIG_UTIL_DISABLED)
++ UTIL_CFG util_cfg = {
++ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO,
++ };
++#endif
++
++ BMU_CFG bmu1_cfg = {
++ .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR + BMU1_LMEM_BASEADDR),
++ .count = BMU1_BUF_COUNT,
++ .size = BMU1_BUF_SIZE,
++ };
++
++ BMU_CFG bmu2_cfg = {
++ .baseaddr = DDR_PHYS_TO_PFE(pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR),
++ .count = BMU2_BUF_COUNT,
++ .size = BMU2_BUF_SIZE,
++ };
++
++ GPI_CFG egpi1_cfg = {
++ .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,
++ .tmlf_txthres = EGPI1_TMLF_TXTHRES,
++ .aseq_len = EGPI1_ASEQ_LEN,
++ };
++
++ GPI_CFG egpi2_cfg = {
++ .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,
++ .tmlf_txthres = EGPI2_TMLF_TXTHRES,
++ .aseq_len = EGPI2_ASEQ_LEN,
++ };
++
++#if defined(CONFIG_PLATFORM_C2000)
++ GPI_CFG egpi3_cfg = {
++ .lmem_rtry_cnt = EGPI3_LMEM_RTRY_CNT,
++ .tmlf_txthres = EGPI3_TMLF_TXTHRES,
++ .aseq_len = EGPI3_ASEQ_LEN,
++ };
++#endif
++
++ GPI_CFG hgpi_cfg = {
++ .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,
++ .tmlf_txthres = HGPI_TMLF_TXTHRES,
++ .aseq_len = HGPI_ASEQ_LEN,
++ };
++
++ printk(KERN_INFO "%s\n", __func__);
++
++#if defined(CONFIG_PLATFORM_LS1012A) && !defined(LS1012A_PFE_RESET_WA)
++ /* LS1012A needs this to make PE work correctly */
++ writel(0x3, CLASS_PE_SYS_CLK_RATIO);
++ writel(0x3, TMU_PE_SYS_CLK_RATIO);
++ writel(0x3, UTIL_PE_SYS_CLK_RATIO);
++ udelay(10);
++#endif
++
++ printk(KERN_INFO "CLASS version: %x\n", readl(CLASS_VERSION));
++ printk(KERN_INFO "TMU version: %x\n", readl(TMU_VERSION));
++
++ printk(KERN_INFO "BMU1 version: %x\n", readl(BMU1_BASE_ADDR + BMU_VERSION));
++ printk(KERN_INFO "BMU2 version: %x\n", readl(BMU2_BASE_ADDR + BMU_VERSION));
++#if defined(CONFIG_PLATFORM_C2000)
++ printk(KERN_INFO "EMAC1 network cfg: %x\n", readl(EMAC1_BASE_ADDR + EMAC_NETWORK_CONFIG));
++ printk(KERN_INFO "EMAC2 network cfg: %x\n", readl(EMAC2_BASE_ADDR + EMAC_NETWORK_CONFIG));
++#if !defined(CONFIG_PLATFORM_PCI)
++ printk(KERN_INFO "EMAC3 network cfg: %x\n", readl(EMAC3_BASE_ADDR + EMAC_NETWORK_CONFIG));
++#endif
++#else
++ //TODO print MTIP config
++#endif
++
++ printk(KERN_INFO "EGPI1 version: %x\n", readl(EGPI1_BASE_ADDR + GPI_VERSION));
++ printk(KERN_INFO "EGPI2 version: %x\n", readl(EGPI2_BASE_ADDR + GPI_VERSION));
++#if !defined(CONFIG_PLATFORM_PCI) && !defined(CONFIG_PLATFORM_LS1012A)
++ printk(KERN_INFO "EGPI3 version: %x\n", readl(EGPI3_BASE_ADDR + GPI_VERSION));
++#endif
++ printk(KERN_INFO "HGPI version: %x\n", readl(HGPI_BASE_ADDR + GPI_VERSION));
++
++#if !defined(CONFIG_PLATFORM_PCI)
++ printk(KERN_INFO "GPT version: %x\n", readl(CBUS_GPT_VERSION));
++#endif
++
++ printk(KERN_INFO "HIF version: %x\n", readl(HIF_VERSION));
++ printk(KERN_INFO "HIF NOPCY version: %x\n", readl(HIF_NOCPY_VERSION));
++
++#if !defined(CONFIG_UTIL_DISABLED)
++ printk(KERN_INFO "UTIL version: %x\n", readl(UTIL_VERSION));
++#endif
++ while(!(readl(TMU_CTRL) & ECC_MEM_INIT_DONE)) ;
++
++ hif_rx_disable();
++ hif_tx_disable();
++
++ bmu_init(BMU1_BASE_ADDR, &bmu1_cfg);
++
++ printk(KERN_INFO "bmu_init(1) done\n");
++
++ bmu_init(BMU2_BASE_ADDR, &bmu2_cfg);
++
++ printk(KERN_INFO "bmu_init(2) done\n");
++
++ class_cfg.resume = resume ? 1 : 0;
++
++ class_init(&class_cfg);
++
++ printk(KERN_INFO "class_init() done\n");
++
++ tmu_init(&tmu_cfg);
++
++ printk(KERN_INFO "tmu_init() done\n");
++#if !defined(CONFIG_UTIL_DISABLED)
++ util_init(&util_cfg);
++
++ printk(KERN_INFO "util_init() done\n");
++#endif
++ gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);
++
++ printk(KERN_INFO "gpi_init(1) done\n");
++
++ gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);
++
++ printk(KERN_INFO "gpi_init(2) done\n");
++#if !defined(CONFIG_PLATFORM_PCI) && !defined(CONFIG_PLATFORM_LS1012A)
++ gpi_init(EGPI3_BASE_ADDR, &egpi3_cfg);
++
++ printk(KERN_INFO "gpi_init(3) done\n");
++#endif
++ gpi_init(HGPI_BASE_ADDR, &hgpi_cfg);
++
++ printk(KERN_INFO "gpi_init(hif) done\n");
++
++ bmu_enable(BMU1_BASE_ADDR);
++
++ printk(KERN_INFO "bmu_enable(1) done\n");
++
++ bmu_enable(BMU2_BASE_ADDR);
++
++ printk(KERN_INFO "bmu_enable(2) done\n");
++
++ return 0;
++}
++
++void pfe_hw_exit(struct pfe *pfe)
++{
++ printk(KERN_INFO "%s\n", __func__);
++
++ bmu_disable(BMU1_BASE_ADDR);
++ bmu_reset(BMU1_BASE_ADDR);
++
++ bmu_disable(BMU2_BASE_ADDR);
++ bmu_reset(BMU2_BASE_ADDR);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hw.h
+@@ -0,0 +1,32 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _PFE_HW_H_
++#define _PFE_HW_H_
++
++#if !defined(CONFIG_PLATFORM_PCI)
++#define PE_SYS_CLK_RATIO 1 /* SYS/AXI = 250MHz, HFE = 500MHz */
++#else
++#define PE_SYS_CLK_RATIO 0 /* SYS = 40MHz, HFE = 40MHz */
++#endif
++
++int pfe_hw_init(struct pfe *pfe, int resume);
++void pfe_hw_exit(struct pfe *pfe);
++
++#endif /* _PFE_HW_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c
+@@ -0,0 +1,341 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/of_net.h>
++#include <linux/of_address.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++#include <linux/mfd/syscon.h>
++#include <linux/regmap.h>
++
++
++#include "pfe_mod.h"
++
++struct comcerto_pfe_platform_data pfe_platform_data;
++
++
++
++static int pfe_get_gemac_if_proprties(struct device_node *parent, int port, int if_cnt,
++ struct comcerto_pfe_platform_data *pdata)
++{
++ struct device_node *gem = NULL, *phy = NULL;
++ int size;
++ int ii = 0, phy_id = 0;
++ const u32 *addr;
++ const void *mac_addr;
++
++ for (ii = 0; ii < if_cnt; ii++) {
++ gem = of_get_next_child(parent, gem);
++ if (!gem)
++ goto err;
++ addr = of_get_property(gem, "reg", &size);
++ if (addr && (be32_to_cpup(addr) == port))
++ break;
++ }
++
++ if (ii >= if_cnt) {
++ printk(KERN_ERR "%s:%d Failed to find interface = %d\n", __func__, __LINE__, if_cnt);
++ goto err;
++ }
++
++ pdata->comcerto_eth_pdata[port].gem_id = port;
++
++ mac_addr = of_get_mac_address(gem);
++
++ if (mac_addr) {
++ memcpy(pdata->comcerto_eth_pdata[port].mac_addr, mac_addr, ETH_ALEN);
++ }
++
++ if ((pdata->comcerto_eth_pdata[port].mii_config = of_get_phy_mode(gem)) < 0)
++ printk(KERN_ERR "%s:%d Incorrect Phy mode....\n", __func__, __LINE__);
++
++
++ addr = of_get_property(gem, "fsl,gemac-bus-id", &size);
++ if (!addr)
++ printk(KERN_ERR "%s:%d Invalid gemac-bus-id....\n", __func__, __LINE__);
++ else
++ pdata->comcerto_eth_pdata[port].bus_id = be32_to_cpup(addr);
++
++ addr = of_get_property(gem, "fsl,gemac-phy-id", &size);
++ if (!addr)
++ printk(KERN_ERR "%s:%d Invalid gemac-phy-id....\n", __func__, __LINE__);
++ else
++ phy_id = pdata->comcerto_eth_pdata[port].phy_id = be32_to_cpup(addr);
++
++ addr = of_get_property(gem, "fsl,mdio-mux-val", &size);
++ if (!addr)
++ printk(KERN_ERR "%s: Invalid mdio-mux-val....\n", __func__);
++ else
++ phy_id = pdata->comcerto_eth_pdata[port].mdio_muxval= be32_to_cpup(addr);
++
++
++ addr = of_get_property(gem, "fsl,pfe-phy-if-flags", &size);
++ if (!addr)
++ printk(KERN_ERR "%s:%d Invalid pfe-phy-if-flags....\n", __func__, __LINE__);
++ else
++ pdata->comcerto_eth_pdata[port].phy_flags = be32_to_cpup(addr);
++
++ addr = of_get_property(gem, "fsl,pfe-gemac-mode", &size);
++ if (!addr)
++ printk(KERN_ERR "%s:%d Invalid pfe-gemac-mode....\n", __func__, __LINE__);
++ else
++ pdata->comcerto_eth_pdata[port].gemac_mode = be32_to_cpup(addr);
++
++
++ /* If PHY is enabled, read mdio properties */
++ if (pdata->comcerto_eth_pdata[port].phy_flags & GEMAC_NO_PHY)
++ goto done;
++
++ phy = of_get_next_child(gem, NULL);
++
++ addr = of_get_property(phy, "reg", &size);
++
++ if (!addr)
++ printk(KERN_ERR "%s:%d Invalid phy enable flag....\n", __func__, __LINE__);
++ else
++ pdata->comcerto_mdio_pdata[port].enabled = be32_to_cpup(addr);
++
++ addr = of_get_property (phy, "fsl,mdio-phy-mask", &size);
++ if (!addr)
++ printk(KERN_ERR "%s:%d Unable to read mdio-phy-mask....\n", __func__, __LINE__);
++ else
++ pdata->comcerto_mdio_pdata[port].phy_mask= be32_to_cpup(addr);
++ pdata->comcerto_mdio_pdata[port].irq[0] = PHY_POLL;
++
++done:
++
++ return 0;
++
++err:
++ return -1;
++}
++/**
++ * pfe_platform_probe -
++ *
++ *
++ */
++static int pfe_platform_probe(struct platform_device *pdev)
++{
++ struct resource res;
++ int ii, rc, interface_count = 0, size = 0;
++ const u32 *prop;
++ struct device_node *np;
++
++ np = pdev->dev.of_node;
++
++ if (!np) {
++ printk(KERN_ERR "Invalid device node\n");
++ return -EINVAL;
++ }
++
++ pfe = kzalloc(sizeof(struct pfe), GFP_KERNEL);
++ if (!pfe) {
++ rc = -ENOMEM;
++ goto err_alloc;
++ }
++
++ platform_set_drvdata(pdev, pfe);
++
++ dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
++
++ if (of_address_to_resource(np, 2, &res))
++ {
++ rc = -ENOMEM;
++ printk(KERN_ERR "failed to get ddr resource\n");
++ goto err_ddr;
++ }
++
++
++ pfe->ddr_phys_baseaddr = res.start;
++ pfe->ddr_size = resource_size(&res);
++
++ //pfe->ddr_baseaddr = ioremap(res.start, resource_size(&res));
++ pfe->ddr_baseaddr = phys_to_virt(res.start);
++ if (!pfe->ddr_baseaddr) {
++ printk(KERN_ERR "ioremap() ddr failed\n");
++ rc = -ENOMEM;
++ goto err_ddr;
++ }
++
++ /*printk("%s:%d : DDR Res : Phy addr:len = %x:%x Mapped addr : %x\n", __func__, __LINE__,
++ pfe->ddr_phys_baseaddr, pfe->ddr_size, pfe->ddr_baseaddr);*/
++
++ pfe->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,"fsl,pfe-scfg");
++ if (IS_ERR(pfe->scfg)) {
++ dev_err(&pdev->dev, "No syscfg phandle specified\n");
++ return PTR_ERR(pfe->scfg);
++ }
++ /*printk("%s scfg %p\n",__func__,pfe->scfg);*/
++
++
++#if 1
++ if (!(pfe->cbus_baseaddr = of_iomap(np, 1)))
++ {
++ rc = -ENOMEM;
++ printk(KERN_ERR "failed to get axi resource\n");
++ goto err_axi;
++ }
++
++ /*printk("%s:%d : AXI Mapped addr : %lx\n", __func__, __LINE__, pfe->cbus_baseaddr);
++ printk("%s:%d : AXI Mapped addr : phys %lx\n", __func__, __LINE__, virt_to_phys(pfe->cbus_baseaddr));*/
++#else
++
++ if (of_address_to_resource(np, 1, &res))
++ {
++ rc = -ENOMEM;
++ printk(KERN_ERR "failed to get AXI resource\n");
++ goto err_iram;
++ }
++ pfe->cbus_baseaddr = ioremap(res.start, resource_size(&res));
++ if (!pfe->cbus_baseaddr) {
++ printk(KERN_INFO "ioremap() AXI failed %lx %x\n", res.start, resource_size(&res));
++ rc = -ENOMEM;
++ goto err_iram;
++ }
++ printk("%s:%d : AXI Mapped addr : %x PHY addr = %x\n", __func__, __LINE__, pfe->cbus_baseaddr, res.start);
++#endif
++
++ pfe->hif_irq = platform_get_irq(pdev, 0);
++ if (pfe->hif_irq < 0) {
++ printk(KERN_ERR "platform_get_irq_byname(hif) failed\n");
++ rc = pfe->hif_irq;
++ goto err_hif_irq;
++ }
++ /*printk("hif_irq: %d \n", pfe->hif_irq);*/
++
++ /* Read interface count */
++ prop = of_get_property(np, "fsl,pfe-num-interfaces", &size);
++ if (!prop) {
++ printk(KERN_ERR "Failed to read number of interfaces\n");
++ rc = -ENXIO;
++ goto err_prop;
++ }
++
++ interface_count = be32_to_cpup(prop);
++ /*printk(KERN_INFO "%s:%d Number of interfaces : %d\n", __func__, __LINE__, interface_count);*/
++ if (interface_count <= 0) {
++ printk(KERN_ERR "No ethernet interface count : %d\n", interface_count);
++ rc = -ENXIO;
++ goto err_prop;
++ }
++
++ for (ii = 0; ii < interface_count; ii++) {
++ pfe_get_gemac_if_proprties(np, ii, interface_count, &pfe_platform_data);
++ }
++
++
++ pfe->dev = &pdev->dev;
++
++ pfe->dev->platform_data = &pfe_platform_data;
++
++ //FIXME get the correct clock from dts
++ pfe->ctrl.sys_clk = 250000; // save sys_clk value as KHz
++
++ rc = pfe_probe(pfe);
++ if (rc < 0)
++ goto err_probe;
++
++ return 0;
++
++err_probe:
++err_prop:
++ /*TODO complet the code */
++err_hif_irq:
++ iounmap(pfe->cbus_baseaddr);
++
++err_axi:
++ iounmap(pfe->ddr_baseaddr);
++
++err_ddr:
++ platform_set_drvdata(pdev, NULL);
++
++ kfree(pfe);
++
++err_alloc:
++ return rc;
++}
++
++
++/**
++ * pfe_platform_remove -
++ *
++ *
++ */
++static int pfe_platform_remove(struct platform_device *pdev)
++{
++ struct pfe *pfe = platform_get_drvdata(pdev);
++ int rc;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ rc = pfe_remove(pfe);
++
++ iounmap(pfe->cbus_baseaddr);
++ iounmap(pfe->ddr_baseaddr);
++
++ platform_set_drvdata(pdev, NULL);
++
++ kfree(pfe);
++
++ return rc;
++}
++
++static struct of_device_id pfe_match[] = {
++ {
++ .compatible = "fsl,pfe",
++ },
++ {},
++};
++MODULE_DEVICE_TABLE(of, pfe_match);
++
++static struct platform_driver pfe_platform_driver = {
++ .probe = pfe_platform_probe,
++ .remove = pfe_platform_remove,
++ .driver = {
++ .name = "pfe",
++ .of_match_table = pfe_match,
++ },
++};
++
++#if 0
++static int __init pfe_module_init(void)
++{
++ printk(KERN_INFO "%s\n", __func__);
++
++ return platform_driver_register(&pfe_platform_driver);
++}
++
++
++static void __exit pfe_module_exit(void)
++{
++ platform_driver_unregister(&pfe_platform_driver);
++
++ printk(KERN_INFO "%s\n", __func__);
++}
++module_init(pfe_module_init);
++module_exit(pfe_module_exit);
++#endif
++
++module_platform_driver(pfe_platform_driver);
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("PFE Ethernet driver");
++MODULE_AUTHOR("NXP DNCPE");
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_mod.c
+@@ -0,0 +1,140 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/dma-mapping.h>
++#include "pfe_mod.h"
++
++struct pfe *pfe;
++
++/**
++ * pfe_probe -
++ *
++ *
++ */
++int pfe_probe(struct pfe *pfe)
++{
++ int rc;
++
++
++ if (DDR_MAX_SIZE > pfe->ddr_size) {
++ printk(KERN_ERR "%s: required DDR memory (%x) above platform ddr memory (%x)\n", __func__, DDR_MAX_SIZE, pfe->ddr_size);
++ rc = -ENOMEM;
++ goto err_hw;
++ }
++
++ if (((int) (pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR) & (8*SZ_1M - 1)) != 0) {
++ printk(KERN_ERR "%s: BMU2 base address (0x%x) must be aligned on 8MB boundary\n", __func__, (int) pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR);
++ rc = -ENOMEM;
++ goto err_hw;
++ }
++
++
++ printk(KERN_INFO "cbus_baseaddr: %lx, ddr_baseaddr: %lx, ddr_phys_baseaddr: %lx, ddr_size: %x\n",
++ (unsigned long)pfe->cbus_baseaddr, (unsigned long)pfe->ddr_baseaddr,
++ pfe->ddr_phys_baseaddr, pfe->ddr_size);
++
++ pfe_lib_init(pfe->cbus_baseaddr, pfe->ddr_baseaddr, pfe->ddr_phys_baseaddr, pfe->ddr_size);
++
++ rc = pfe_hw_init(pfe, 0);
++ if (rc < 0)
++ goto err_hw;
++
++ rc = pfe_hif_lib_init(pfe);
++ if (rc < 0)
++ goto err_hif_lib;
++
++ rc = pfe_hif_init(pfe);
++ if (rc < 0)
++ goto err_hif;
++
++ rc = pfe_firmware_init(pfe);
++ if (rc < 0)
++ goto err_firmware;
++
++ rc = pfe_ctrl_init(pfe);
++ if (rc < 0)
++ goto err_ctrl;
++
++ rc = pfe_eth_init(pfe);
++ if (rc < 0)
++ goto err_eth;
++
++ rc = pfe_sysfs_init(pfe);
++ if(rc < 0)
++ goto err_sysfs;
++
++ rc = pfe_debugfs_init(pfe);
++ if (rc < 0)
++ goto err_debugfs;
++
++ return 0;
++
++err_debugfs:
++ pfe_sysfs_exit(pfe);
++
++err_sysfs:
++ pfe_eth_exit(pfe);
++
++err_eth:
++ pfe_ctrl_exit(pfe);
++
++err_ctrl:
++ pfe_firmware_exit(pfe);
++
++err_firmware:
++ pfe_hif_exit(pfe);
++
++err_hif:
++ pfe_hif_lib_exit(pfe);
++
++err_hif_lib:
++ pfe_hw_exit(pfe);
++
++err_hw:
++ return rc;
++}
++
++
++/**
++ * pfe_remove -
++ *
++ *
++ */
++int pfe_remove(struct pfe *pfe)
++{
++ printk(KERN_INFO "%s\n", __func__);
++
++ pfe_debugfs_exit(pfe);
++
++ pfe_sysfs_exit(pfe);
++
++ pfe_eth_exit(pfe);
++
++ pfe_ctrl_exit(pfe);
++
++ pfe_firmware_exit(pfe);
++
++ pfe_hif_exit(pfe);
++
++ pfe_hif_lib_exit(pfe);
++
++ pfe_hw_exit(pfe);
++
++ return 0;
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_mod.h
+@@ -0,0 +1,163 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _PFE_MOD_H_
++#define _PFE_MOD_H_
++
++#include <linux/device.h>
++#include <linux/elf.h>
++
++struct pfe;
++
++#include "config.h"
++#include "pfe_hw.h"
++#include "pfe_firmware.h"
++#include "pfe_ctrl.h"
++#include "pfe_hif.h"
++#include "pfe_hif_lib.h"
++#include "pfe_eth.h"
++#include "pfe_sysfs.h"
++#include "pfe_perfmon.h"
++#include "pfe_debugfs.h"
++
++struct pfe_tmu_credit {
++ /* Number of allowed TX packet in-flight, matches TMU queue size */
++ unsigned int tx_credit[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];
++ unsigned int tx_credit_max[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];
++ unsigned int tx_packets[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];
++};
++
++struct pfe {
++ struct regmap *scfg;
++ unsigned long ddr_phys_baseaddr;
++ void *ddr_baseaddr;
++ unsigned int ddr_size;
++ void *cbus_baseaddr;
++ void *apb_baseaddr;
++ unsigned long iram_phys_baseaddr;
++ void *iram_baseaddr;
++ unsigned long ipsec_phys_baseaddr;
++ void *ipsec_baseaddr;
++ int hif_irq;
++ int hif_client_irq;
++ struct device *dev;
++ struct dentry *dentry;
++ struct pfe_ctrl ctrl;
++ struct pfe_hif hif;
++ struct pfe_eth eth;
++ struct hif_client_s *hif_client[HIF_CLIENTS_MAX];
++#if defined(CFG_DIAGS)
++ struct pfe_diags diags;
++#endif
++ struct pfe_tmu_credit tmu_credit;
++ struct pfe_cpumon cpumon;
++ struct pfe_memmon memmon;
++ int wake;
++ struct clk * hfe_clock;
++};
++
++extern struct pfe *pfe;
++
++int pfe_probe(struct pfe *pfe);
++int pfe_remove(struct pfe *pfe);
++
++#ifndef SZ_1K
++#define SZ_1K 1024
++#endif
++
++#ifndef SZ_1M
++#define SZ_1M (1024 * 1024)
++#endif
++
++/* DDR Mapping */
++#if !defined(CONFIG_PLATFORM_PCI)
++#define ROUTE_TABLE_BASEADDR 0
++#define ROUTE_TABLE_HASH_BITS 15 /**< 32K entries */
++#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
++#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
++#define BMU2_BUF_COUNT (4096 - 256) /**< This is to get a total DDR size of 12MiB */
++#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
++#define UTIL_CODE_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
++#define UTIL_CODE_SIZE (128 * SZ_1K)
++#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
++#define UTIL_DDR_DATA_SIZE (64 * SZ_1K)
++#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
++#define CLASS_DDR_DATA_SIZE (32 * SZ_1K)
++#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
++#define TMU_DDR_DATA_SIZE (32 * SZ_1K)
++#define TMU_LLM_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
++#define TMU_LLM_QUEUE_LEN (8 * 512) /**< Must be power of two and at least 16 * 8 = 128 bytes */
++#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
++
++#define DDR_MAX_SIZE (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
++
++#else
++
++#define UTIL_CODE_BASEADDR 0
++#if defined(CONFIG_UTIL_DISABLED)
++#define UTIL_CODE_SIZE (0 * SZ_1K)
++#else
++#define UTIL_CODE_SIZE (8 * SZ_1K)
++#endif
++#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
++#define UTIL_DDR_DATA_SIZE (0 * SZ_1K)
++#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
++#define CLASS_DDR_DATA_SIZE (0 * SZ_1K)
++#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
++#define TMU_DDR_DATA_SIZE (0 * SZ_1K)
++#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
++#define ROUTE_TABLE_HASH_BITS 5 /**< 32 entries */
++#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
++#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
++#define BMU2_BUF_COUNT 16
++#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
++#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
++#define TMU_LLM_QUEUE_LEN (16 * 8) /**< Must be power of two and at least 16 * 8 = 128 bytes */
++#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
++#define HIF_DESC_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
++#define HIF_RX_DESC_SIZE (16*HIF_RX_DESC_NT)
++#define HIF_TX_DESC_SIZE (16*HIF_TX_DESC_NT)
++#define HIF_DESC_SIZE (HIF_RX_DESC_SIZE + HIF_TX_DESC_SIZE)
++#define HIF_RX_PKT_DDR_BASEADDR (HIF_DESC_BASEADDR + HIF_DESC_SIZE)
++#define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE)
++#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
++#define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE)
++#define ROUTE_BASEADDR (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
++#define ROUTE_SIZE (2 * CLASS_ROUTE_SIZE)
++
++#define DDR_MAX_SIZE (ROUTE_BASEADDR + ROUTE_SIZE)
++
++#define PFE_HOST_TO_PCI(addr) (((u32)addr)- ((u32)DDR_BASE_ADDR))
++#define PFE_PCI_TO_HOST(addr) (((u32)addr)+ ((u32)DDR_BASE_ADDR))
++#endif
++
++/* IRAM Mapping */
++#define IPSEC_IRAM_BASEADDR 0
++#define IPSEC_IRAM_SIZE 0x2000
++
++/* LMEM Mapping */
++#define BMU1_LMEM_BASEADDR 0
++#define BMU1_BUF_COUNT 256
++#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
++#define IPSEC_LMEM_BASEADDR (BMU1_LMEM_BASEADDR + BMU1_LMEM_SIZE)
++#define IPSEC_LMEM_SIZE (30 * 1024)
++
++
++
++#endif /* _PFE_MOD_H */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_perfmon.c
+@@ -0,0 +1,175 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++/* PFE performance monitoring functions */
++
++#include "pfe_ctrl_hal.h"
++#include "pfe_perfmon.h"
++
++static TIMER_ENTRY cpumon_timer;
++
++u32 CLASS_DMEM_SH2(cpu_ticks[2]);
++u32 TMU_DMEM_SH2(cpu_ticks[2]);
++#if !defined(CONFIG_UTIL_DISABLED)
++u32 UTIL_DMEM_SH2(cpu_ticks[2]);
++#endif
++
++#define compute_active_pct(total_ticks, active_ticks) ((active_ticks * 100 + (total_ticks >> 1)) / total_ticks)
++
++static void cpumon_timer_handler(void)
++{
++ int id;
++ u32 dmem_addr;
++ u32 ticks[2];
++ u32 total, active;
++ struct pfe_ctrl *ctrl = &pfe->ctrl;
++ struct pfe_cpumon *cpumon = &pfe->cpumon;
++
++ // Process class PE's
++ total = active = 0;
++ dmem_addr = virt_to_class_dmem(&class_cpu_ticks[0]);
++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++)
++ {
++ cpumon->cpu_usage_pct[id] = 0;
++ if (pe_sync_stop(ctrl, (1 << id)) < 0)
++ continue;
++ ticks[0] = be32_to_cpu(pe_dmem_read(id, dmem_addr, 4));
++ ticks[1] = be32_to_cpu(pe_dmem_read(id, dmem_addr + 4, 4));
++ pe_dmem_write(id, 0, dmem_addr, 4);
++ pe_dmem_write(id, 0, dmem_addr + 4, 4);
++ pe_start(ctrl, (1 << id));
++ ticks[0] >>= 8; // divide both values by 256, so multiply by 100 won't overflow
++ ticks[1] >>= 8;
++ total += ticks[0];
++ active += ticks[1];
++ if (ticks[0] != 0)
++ cpumon->cpu_usage_pct[id] = compute_active_pct(ticks[0], ticks[1]);
++ }
++ if (total != 0)
++ cpumon->class_usage_pct = compute_active_pct(total, active);
++ else
++ cpumon->class_usage_pct = 0;
++
++ // Process TMU PE's
++ total = active = 0;
++ dmem_addr = virt_to_tmu_dmem(&tmu_cpu_ticks[0]);
++ for (id = TMU0_ID; id <= TMU_MAX_ID; id++)
++ {
++#if defined(CONFIG_PLATFORM_LS1012A)
++ if(id == TMU2_ID) continue;
++#endif
++ cpumon->cpu_usage_pct[id] = 0;
++ if (pe_sync_stop(ctrl, (1 << id)) < 0)
++ continue;
++ ticks[0] = be32_to_cpu(pe_dmem_read(id, dmem_addr, 4));
++ ticks[1] = be32_to_cpu(pe_dmem_read(id, dmem_addr + 4, 4));
++ pe_dmem_write(id, 0, dmem_addr, 4);
++ pe_dmem_write(id, 0, dmem_addr + 4, 4);
++ pe_start(ctrl, (1 << id));
++ ticks[0] >>= 8; // divide both values by 256, so multiply by 100 won't overflow
++ ticks[1] >>= 8;
++ if (ticks[0] != 0)
++ cpumon->cpu_usage_pct[id] = compute_active_pct(ticks[0], ticks[1]);
++ }
++#if !defined(CONFIG_UTIL_DISABLED)
++ // Process Util PE
++ dmem_addr = virt_to_util_dmem(&util_cpu_ticks[0]);
++ cpumon->cpu_usage_pct[UTIL_ID] = 0;
++ if (pe_sync_stop(ctrl, (1 << UTIL_ID)) < 0)
++ return;
++ ticks[0] = be32_to_cpu(pe_dmem_read(UTIL_ID, dmem_addr, 4));
++ ticks[1] = be32_to_cpu(pe_dmem_read(UTIL_ID, dmem_addr + 4, 4));
++ pe_dmem_write(UTIL_ID, 0, dmem_addr, 4);
++ pe_dmem_write(UTIL_ID, 0, dmem_addr + 4, 4);
++ pe_start(ctrl, (1 << UTIL_ID));
++ ticks[0] >>= 8; // divide both values by 256, so multiply by 100 won't overflow
++ ticks[1] >>= 8;
++ if (ticks[0] != 0)
++ cpumon->cpu_usage_pct[UTIL_ID] = compute_active_pct(ticks[0], ticks[1]);
++#endif
++}
++
++static int pfe_cpumon_init(struct pfe *pfe)
++{
++ timer_init(&cpumon_timer, cpumon_timer_handler);
++ timer_add(&cpumon_timer, CT_CPUMON_INTERVAL);
++ return 0;
++}
++
++static void pfe_cpumon_exit(struct pfe *pfe)
++{
++ timer_del(&cpumon_timer);
++}
++
++
++/*********************************************************************************/
++
++// Memory monitor functions
++
++void * pfe_kmalloc(size_t size, int flags)
++{
++ struct pfe_memmon *memmon = &pfe->memmon;
++ void *ptr;
++ ptr = kmalloc(size, flags);
++ if (ptr)
++ memmon->kernel_memory_allocated += ksize(ptr);
++ return ptr;
++}
++
++void * pfe_kzalloc(size_t size, int flags)
++{
++ struct pfe_memmon *memmon = &pfe->memmon;
++ void *ptr;
++ ptr = kzalloc(size, flags);
++ if (ptr)
++ memmon->kernel_memory_allocated += ksize(ptr);
++ return ptr;
++}
++
++void pfe_kfree(void *ptr)
++{
++ struct pfe_memmon *memmon = &pfe->memmon;
++ memmon->kernel_memory_allocated -= ksize(ptr);
++ kfree(ptr);
++}
++
++static int pfe_memmon_init(struct pfe *pfe)
++{
++ return 0;
++}
++
++static void pfe_memmon_exit(struct pfe *pfe)
++{
++}
++
++/*********************************************************************************/
++
++
++int pfe_perfmon_init(struct pfe *pfe)
++{
++ pfe_cpumon_init(pfe);
++ pfe_memmon_init(pfe);
++ return 0;
++}
++
++void pfe_perfmon_exit(struct pfe *pfe)
++{
++ pfe_cpumon_exit(pfe);
++ pfe_memmon_exit(pfe);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_perfmon.h
+@@ -0,0 +1,41 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _PFE_PERFMON_H_
++#define _PFE_PERFMON_H_
++
++#define CT_CPUMON_INTERVAL (1 * TIMER_TICKS_PER_SEC)
++
++struct pfe_cpumon {
++ u32 cpu_usage_pct[MAX_PE];
++ u32 class_usage_pct;
++};
++
++struct pfe_memmon {
++ u32 kernel_memory_allocated;
++};
++
++void * pfe_kmalloc(size_t size, int flags);
++void * pfe_kzalloc(size_t size, int flags);
++void pfe_kfree(void *ptr);
++
++int pfe_perfmon_init(struct pfe *pfe);
++void pfe_perfmon_exit(struct pfe *pfe);
++
++#endif /* _PFE_PERFMON_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_platform.c
+@@ -0,0 +1,358 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++
++#include "pfe_mod.h"
++
++/**
++ * pfe_platform_probe -
++ *
++ *
++ */
++static int pfe_platform_probe(struct platform_device *pdev)
++{
++ struct resource *r;
++ int rc;
++ struct clk *clk_axi;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ pfe = kzalloc(sizeof(struct pfe), GFP_KERNEL);
++ if (!pfe) {
++ rc = -ENOMEM;
++ goto err_alloc;
++ }
++
++ platform_set_drvdata(pdev, pfe);
++
++ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ddr");
++ if (!r) {
++ printk(KERN_INFO "platform_get_resource_byname(ddr) failed\n");
++ rc = -ENXIO;
++ goto err_ddr;
++ }
++
++ pfe->ddr_phys_baseaddr = r->start;
++ pfe->ddr_size = resource_size(r);
++
++ pfe->ddr_baseaddr = ioremap(r->start, resource_size(r));
++ if (!pfe->ddr_baseaddr) {
++ printk(KERN_INFO "ioremap() ddr failed\n");
++ rc = -ENOMEM;
++ goto err_ddr;
++ }
++
++ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "axi");
++ if (!r) {
++ printk(KERN_INFO "platform_get_resource_byname(axi) failed\n");
++ rc = -ENXIO;
++ goto err_axi;
++ }
++
++ pfe->cbus_baseaddr = ioremap(r->start, resource_size(r));
++ if (!pfe->cbus_baseaddr) {
++ printk(KERN_INFO "ioremap() axi failed\n");
++ rc = -ENOMEM;
++ goto err_axi;
++ }
++
++ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb");
++ if (!r) {
++ printk(KERN_INFO "platform_get_resource_byname(apb) failed\n");
++ rc = -ENXIO;
++ goto err_apb;
++ }
++
++ pfe->apb_baseaddr = ioremap(r->start, resource_size(r));
++ if (!pfe->apb_baseaddr) {
++ printk(KERN_INFO "ioremap() apb failed\n");
++ rc = -ENOMEM;
++ goto err_apb;
++ }
++
++ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iram");
++ if (!r) {
++ printk(KERN_INFO "platform_get_resource_byname(iram) failed\n");
++ rc = -ENXIO;
++ goto err_iram;
++ }
++
++ pfe->iram_phys_baseaddr = r->start;
++ pfe->iram_baseaddr = ioremap(r->start, resource_size(r));
++ if (!pfe->iram_baseaddr) {
++ printk(KERN_INFO "ioremap() iram failed\n");
++ rc = -ENOMEM;
++ goto err_iram;
++ }
++
++ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ipsec");
++ if (!r) {
++ printk(KERN_INFO "platform_get_resource_byname(ipsec) failed\n");
++ rc = -ENXIO;
++ goto err_ipsec;
++ }
++
++ pfe->ipsec_phys_baseaddr = r->start;
++ /* Just map only initial 1MB , as its enough to access espah engine
++ */
++ //pfe->ipsec_baseaddr = ioremap(r->start, resource_size(r));
++ pfe->ipsec_baseaddr = ioremap(r->start, 1*1024*1024);
++ if (!pfe->ipsec_baseaddr) {
++ printk(KERN_INFO "ioremap() ipsec failed\n");
++ rc = -ENOMEM;
++ goto err_ipsec;
++ }
++
++ printk(KERN_INFO "ipsec: baseaddr :%x --- %x\n", (u32)pfe->ipsec_phys_baseaddr, (u32)pfe->ipsec_baseaddr);
++
++ pfe->hif_irq = platform_get_irq_byname(pdev, "hif");
++ if (pfe->hif_irq < 0) {
++ printk(KERN_INFO "platform_get_irq_byname(hif) failed\n");
++ rc = pfe->hif_irq;
++ goto err_hif_irq;
++ }
++
++#if 0
++ pfe->hif_client_irq = platform_get_irq_byname(pdev, "hif_client");
++ if (pfe->hif_client_irq < 0) {
++ printk(KERN_INFO "platform_get_irq_byname(hif_client) failed\n");
++ rc = pfe->hif_client_irq;
++ goto err_hif_irq;
++ }
++#endif
++
++ pfe->dev = &pdev->dev;
++
++
++ /* Get the system clock */
++ clk_axi = clk_get(NULL,"axi");
++ if (IS_ERR(clk_axi)) {
++ printk(KERN_INFO "clk_get call failed\n");
++ rc = -ENXIO;
++ goto err_clk;
++ }
++
++ /* HFE core clock */
++ pfe->hfe_clock = clk_get(NULL, "hfe_core");
++ if (IS_ERR(pfe->hfe_clock)) {
++ printk(KERN_INFO "clk_get call failed\n");
++ rc = -ENXIO;
++ goto err_hfe_clock;
++ }
++
++ clk_disable(pfe->hfe_clock);
++ c2000_block_reset(COMPONENT_PFE_SYS, 1);
++ mdelay(1);
++ c2000_block_reset(COMPONENT_PFE_SYS, 0);
++ clk_enable(pfe->hfe_clock);
++
++ pfe->ctrl.clk_axi = clk_axi;
++ pfe->ctrl.sys_clk = clk_get_rate(clk_axi) / 1000; // save sys_clk value as KHz
++
++ rc = pfe_probe(pfe);
++ if (rc < 0)
++ goto err_probe;
++
++ return 0;
++
++err_probe:
++ clk_put(pfe->hfe_clock);
++err_hfe_clock:
++ clk_put(clk_axi);
++err_clk:
++err_hif_irq:
++ iounmap(pfe->ipsec_baseaddr);
++err_ipsec:
++ iounmap(pfe->iram_baseaddr);
++err_iram:
++ iounmap(pfe->apb_baseaddr);
++
++err_apb:
++ iounmap(pfe->cbus_baseaddr);
++
++err_axi:
++ iounmap(pfe->ddr_baseaddr);
++
++err_ddr:
++ platform_set_drvdata(pdev, NULL);
++
++ kfree(pfe);
++
++err_alloc:
++ return rc;
++}
++
++
++/**
++ * pfe_platform_remove -
++ *
++ *
++ */
++static int pfe_platform_remove(struct platform_device *pdev)
++{
++ struct pfe *pfe = platform_get_drvdata(pdev);
++ int rc;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ rc = pfe_remove(pfe);
++
++ c2000_block_reset(COMPONENT_PFE_SYS, 1);
++ clk_disable(pfe->hfe_clock);
++ clk_put(pfe->hfe_clock);
++ clk_put(pfe->ctrl.clk_axi);
++ iounmap(pfe->ipsec_baseaddr);
++ iounmap(pfe->iram_baseaddr);
++ iounmap(pfe->apb_baseaddr);
++ iounmap(pfe->cbus_baseaddr);
++ iounmap(pfe->ddr_baseaddr);
++
++ platform_set_drvdata(pdev, NULL);
++
++ kfree(pfe);
++
++ return rc;
++}
++
++#ifdef CONFIG_PM
++
++#ifdef CONFIG_PM_SLEEP
++static int pfe_platform_suspend(struct device *dev)
++{
++ struct pfe *pfe = platform_get_drvdata(to_platform_device(dev));
++ struct net_device *netdev;
++ int i;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ pfe->wake = 0;
++
++ for (i = 0; i < (NUM_GEMAC_SUPPORT - 1); i++ ) {
++ netdev = pfe->eth.eth_priv[i]->dev;
++
++ netif_device_detach(netdev);
++
++ if (netif_running(netdev))
++ if(pfe_eth_suspend(netdev))
++ pfe->wake =1;
++ }
++
++ /* Shutdown PFE only if we're not waking up the system */
++ if (!pfe->wake) {
++ pfe_ctrl_suspend(&pfe->ctrl);
++ pfe_hif_exit(pfe);
++ pfe_hif_lib_exit(pfe);
++
++ class_disable();
++ tmu_disable(0xf);
++#if !defined(CONFIG_UTIL_DISABLED)
++ util_disable();
++#endif
++ pfe_hw_exit(pfe);
++ c2000_block_reset(COMPONENT_PFE_SYS, 1);
++ clk_disable(pfe->hfe_clock);
++ }
++
++ return 0;
++}
++
++static int pfe_platform_resume(struct device *dev)
++{
++ struct pfe *pfe = platform_get_drvdata(to_platform_device(dev));
++ struct net_device *netdev;
++ int i;
++
++ printk(KERN_INFO "%s\n", __func__);
++
++ if (!pfe->wake) {
++ /* Sequence follows VLSI recommendation (bug 71927) */
++ c2000_block_reset(COMPONENT_PFE_SYS, 1);
++ mdelay(1);
++ c2000_block_reset(COMPONENT_PFE_SYS, 0);
++ clk_enable(pfe->hfe_clock);
++
++ pfe_hw_init(pfe, 1);
++ pfe_hif_lib_init(pfe);
++ pfe_hif_init(pfe);
++#if !defined(CONFIG_UTIL_DISABLED)
++ util_enable();
++#endif
++ tmu_enable(0xf);
++ class_enable();
++ pfe_ctrl_resume(&pfe->ctrl);
++ }
++
++ for(i = 0; i < (NUM_GEMAC_SUPPORT - 1); i++) {
++ netdev = pfe->eth.eth_priv[i]->dev;
++
++ if (pfe->eth.eth_priv[i]->mii_bus)
++ pfe_eth_mdio_reset(pfe->eth.eth_priv[i]->mii_bus);
++
++ if (netif_running(netdev))
++ pfe_eth_resume(netdev);
++
++ netif_device_attach(netdev);
++ }
++ return 0;
++}
++#else
++#define pfe_platform_suspend NULL
++#define pfe_platform_resume NULL
++#endif
++
++static const struct dev_pm_ops pfe_platform_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(pfe_platform_suspend, pfe_platform_resume)
++};
++
++#endif
++
++static struct platform_driver pfe_platform_driver = {
++ .probe = pfe_platform_probe,
++ .remove = pfe_platform_remove,
++ .driver = {
++ .name = "pfe",
++#ifdef CONFIG_PM
++ .pm = &pfe_platform_pm_ops,
++#endif
++ },
++};
++
++
++static int __init pfe_module_init(void)
++{
++ printk(KERN_INFO "%s\n", __func__);
++
++ return platform_driver_register(&pfe_platform_driver);
++}
++
++
++static void __exit pfe_module_exit(void)
++{
++ platform_driver_unregister(&pfe_platform_driver);
++
++ printk(KERN_INFO "%s\n", __func__);
++}
++
++MODULE_LICENSE("GPL");
++module_init(pfe_module_init);
++module_exit(pfe_module_exit);
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_sysfs.c
+@@ -0,0 +1,855 @@
++/*
++ * (C) Copyright 2011
++ * Author : Freescale Semiconductor, Inc.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ * */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include "pfe_mod.h"
++#include "pfe_ctrl_hal.h"
++
++#define PE_EXCEPTION_DUMP_ADDRESS 0x1fa8
++#define NUM_QUEUES 16
++
++static char register_name[20][5] = {
++ "EPC", "ECAS", "EID", "ED",
++ "r0", "r1", "r2", "r3",
++ "r4", "r5", "r6", "r7",
++ "r8", "r9", "r10", "r11",
++ "r12", "r13", "r14", "r15",
++};
++
++static char exception_name[14][20] = {
++ "Reset",
++ "HardwareFailure",
++ "NMI",
++ "InstBreakpoint",
++ "DataBreakpoint",
++ "Unsupported",
++ "PrivilegeViolation",
++ "InstBusError",
++ "DataBusError",
++ "AlignmentError",
++ "ArithmeticError",
++ "SystemCall",
++ "MemoryManagement",
++ "Interrupt",
++};
++
++static unsigned long class_do_clear = 0;
++static unsigned long tmu_do_clear = 0;
++#if !defined(CONFIG_UTIL_DISABLED)
++static unsigned long util_do_clear = 0;
++#endif
++
++u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset);
++
++static ssize_t display_pe_status(char *buf, int id, u32 dmem_addr, unsigned long do_clear)
++{
++ ssize_t len = 0;
++ u32 val;
++ char statebuf[5];
++ struct pfe_cpumon *cpumon = &pfe->cpumon;
++ u32 debug_indicator;
++ u32 debug[20];
++
++ *(u32 *)statebuf = pe_dmem_read(id, dmem_addr, 4);
++ dmem_addr += 4;
++
++ statebuf[4] = '\0';
++ len += sprintf(buf + len, "state=%4s ", statebuf);
++
++ val = pe_dmem_read(id, dmem_addr, 4);
++ dmem_addr += 4;
++ len += sprintf(buf + len, "ctr=%08x ", cpu_to_be32(val));
++
++ val = pe_dmem_read(id, dmem_addr, 4);
++ if (do_clear && val)
++ pe_dmem_write(id, 0, dmem_addr, 4);
++ dmem_addr += 4;
++ len += sprintf(buf + len, "rx=%u ", cpu_to_be32(val));
++
++ val = pe_dmem_read(id, dmem_addr, 4);
++ if (do_clear && val)
++ pe_dmem_write(id, 0, dmem_addr, 4);
++ dmem_addr += 4;
++ if (id >= TMU0_ID && id <= TMU_MAX_ID)
++ len += sprintf(buf + len, "qstatus=%x", cpu_to_be32(val));
++ else
++ len += sprintf(buf + len, "tx=%u", cpu_to_be32(val));
++
++ val = pe_dmem_read(id, dmem_addr, 4);
++ if (do_clear && val)
++ pe_dmem_write(id, 0, dmem_addr, 4);
++ dmem_addr += 4;
++ if (val)
++ len += sprintf(buf + len, " drop=%u", cpu_to_be32(val));
++
++ len += sprintf(buf + len, " load=%d%%", cpumon->cpu_usage_pct[id]);
++
++ len += sprintf(buf + len, "\n");
++
++ debug_indicator = pe_dmem_read(id, dmem_addr, 4);
++ dmem_addr += 4;
++ if (!strncmp((char *)&debug_indicator, "DBUG", 4))
++ {
++ int j, last = 0;
++ for (j = 0; j < 16; j++)
++ {
++ debug[j] = pe_dmem_read(id, dmem_addr, 4);
++ if (debug[j])
++ {
++ if (do_clear)
++ pe_dmem_write(id, 0, dmem_addr, 4);
++ last = j + 1;
++ }
++ dmem_addr += 4;
++ }
++ for (j = 0; j < last; j++)
++ {
++ len += sprintf(buf + len, "%08x%s", cpu_to_be32(debug[j]),
++ (j & 0x7) == 0x7 || j == last - 1 ? "\n" : " ");
++ }
++ }
++
++ if (!strncmp(statebuf, "DEAD", 4))
++ {
++ u32 i, dump = PE_EXCEPTION_DUMP_ADDRESS;
++
++ len += sprintf(buf + len, "Exception details:\n");
++ for (i = 0; i < 20; i++) {
++ debug[i] = pe_dmem_read(id, dump, 4);
++ dump +=4;
++ if (i == 2)
++ len += sprintf(buf + len, "%4s = %08x (=%s) ", register_name[i], cpu_to_be32(debug[i]), exception_name[min((u32) cpu_to_be32(debug[i]), (u32)13)]);
++ else
++ len += sprintf(buf + len, "%4s = %08x%s", register_name[i], cpu_to_be32(debug[i]),
++ (i & 0x3) == 0x3 || i == 19 ? "\n" : " ");
++ }
++ }
++
++ return len;
++}
++
++static ssize_t class_phy_stats(char *buf, int phy)
++{
++ ssize_t len = 0;
++ int off1 = phy * 0x28;
++ int off2 = phy * 0x10;
++
++ if (phy == 3)
++ off1 = CLASS_PHY4_RX_PKTS - CLASS_PHY1_RX_PKTS;
++
++ len += sprintf(buf + len, "phy: %d\n", phy);
++ len += sprintf(buf + len, " rx: %10u, tx: %10u, intf: %10u, ipv4: %10u, ipv6: %10u\n",
++ readl(CLASS_PHY1_RX_PKTS + off1), readl(CLASS_PHY1_TX_PKTS + off1),
++ readl(CLASS_PHY1_INTF_MATCH_PKTS + off1), readl(CLASS_PHY1_V4_PKTS + off1),
++ readl(CLASS_PHY1_V6_PKTS + off1));
++
++ len += sprintf(buf + len, " icmp: %10u, igmp: %10u, tcp: %10u, udp: %10u\n",
++ readl(CLASS_PHY1_ICMP_PKTS + off2), readl(CLASS_PHY1_IGMP_PKTS + off2),
++ readl(CLASS_PHY1_TCP_PKTS + off2), readl(CLASS_PHY1_UDP_PKTS + off2));
++
++ len += sprintf(buf + len, " err\n");
++ len += sprintf(buf + len, " lp: %10u, intf: %10u, l3: %10u, chcksum: %10u, ttl: %10u\n",
++ readl(CLASS_PHY1_LP_FAIL_PKTS + off1), readl(CLASS_PHY1_INTF_FAIL_PKTS + off1),
++ readl(CLASS_PHY1_L3_FAIL_PKTS + off1), readl(CLASS_PHY1_CHKSUM_ERR_PKTS + off1),
++ readl(CLASS_PHY1_TTL_ERR_PKTS + off1));
++
++ return len;
++}
++
++/** qm_read_drop_stat
++ * This function is used to read the drop statistics from the TMU
++ * hw drop counter. Since the hw counter is always cleared afer
++ * reading, this function maintains the previous drop count, and
++ * adds the new value to it. That value can be retrieved by
++ * passing a pointer to it with the total_drops arg.
++ *
++ * @param tmu TMU number (0 - 3)
++ * @param queue queue number (0 - 15)
++ * @param total_drops pointer to location to store total drops (or NULL)
++ * @param do_reset if TRUE, clear total drops after updating
++ *
++ */
++
++u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset)
++{
++ static u32 qtotal[TMU_MAX_ID + 1][NUM_QUEUES];
++ u32 val;
++ writel((tmu << 8) | queue, TMU_TEQ_CTRL);
++ writel((tmu << 8) | queue, TMU_LLM_CTRL);
++ val = readl(TMU_TEQ_DROP_STAT);
++ qtotal[tmu][queue] += val;
++ if (total_drops)
++ *total_drops = qtotal[tmu][queue];
++ if (do_reset)
++ qtotal[tmu][queue] = 0;
++ return val;
++}
++
++static ssize_t tmu_queue_stats(char *buf, int tmu, int queue)
++{
++ ssize_t len = 0;
++ u32 drops;
++
++ len += sprintf(buf + len, "%d-%02d, ", tmu, queue);
++
++ drops = qm_read_drop_stat(tmu, queue, NULL, 0);
++
++ /* Select queue */
++ writel((tmu << 8) | queue, TMU_TEQ_CTRL);
++ writel((tmu << 8) | queue, TMU_LLM_CTRL);
++
++ len += sprintf(buf + len, "(teq) drop: %10u, tx: %10u (llm) head: %08x, tail: %08x, drop: %10u\n",
++ drops, readl(TMU_TEQ_TRANS_STAT),
++ readl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR),
++ readl(TMU_LLM_QUE_DROPCNT));
++
++ return len;
++}
++
++
++static ssize_t tmu_queues(char *buf, int tmu)
++{
++ ssize_t len = 0;
++ int queue;
++
++ for (queue = 0; queue < 16; queue++)
++ len += tmu_queue_stats(buf + len, tmu, queue);
++
++ return len;
++}
++
++static ssize_t tmu_ctx(char *buf, int tmu)
++{
++ ssize_t len = 0;
++ int i;
++ u32 val, tmu_context_addr = TMU_CONTEXT_ADDR;
++
++ len += sprintf(buf+len, " TMU %d \n", TMU0_ID+tmu);
++ for (i = 1; i <= 160 ; i++, tmu_context_addr += 4)
++ {
++ val = pe_dmem_read(TMU0_ID+tmu, tmu_context_addr , 4);
++ if (i == 5)
++ len += sprintf(buf+len, "\nShapers: Each shaper structure is 8 bytes and there are 10 shapers\n");
++
++ if (i == 25)
++ len += sprintf(buf+len, "\nScheduler: Each scheduler structure is 48 bytes and there are 8 schedulers\n");
++ if (i == 121)
++ len += sprintf(buf+len, "\nQueue: Each queue structure is 2 bytes and there are 16 queues\n");
++
++ if (i == 129)
++ len += sprintf(buf+len, "\nqlenmasks array for 16 queues\n");
++ if (i == 145)
++ len += sprintf(buf+len, "\nqresultmap array for 16 queues\n");
++ if (i%8 == 0)
++ len += sprintf(buf+len, "%08x \n", cpu_to_be32(val));
++ else
++ len += sprintf(buf+len, "%08x ", cpu_to_be32(val));
++ }
++
++ len += sprintf(buf+len, "\n");
++
++ return len;
++}
++
++static ssize_t block_version(char *buf, void *addr)
++{
++ ssize_t len = 0;
++ u32 val;
++
++ val = readl(addr);
++ len += sprintf(buf + len, "revision: %x, version: %x, id: %x\n", (val >> 24) & 0xff, (val >> 16) & 0xff, val & 0xffff);
++
++ return len;
++}
++
++static ssize_t bmu(char *buf, int id, void *base)
++{
++ ssize_t len = 0;
++
++ len += sprintf(buf + len, "bmu: %d\n ", id);
++
++ len += block_version(buf + len, base + BMU_VERSION);
++
++ len += sprintf(buf + len, " buf size: %x\n", (1 << readl(base + BMU_BUF_SIZE)));
++ len += sprintf(buf + len, " buf count: %x\n", readl(base + BMU_BUF_CNT));
++ len += sprintf(buf + len, " buf rem: %x\n", readl(base + BMU_REM_BUF_CNT));
++ len += sprintf(buf + len, " buf curr: %x\n", readl(base + BMU_CURR_BUF_CNT));
++ len += sprintf(buf + len, " free err: %x\n", readl(base + BMU_FREE_ERR_ADDR));
++
++ return len;
++}
++
++static ssize_t gpi(char *buf, int id, void *base)
++{
++ ssize_t len = 0;
++ u32 val;
++
++ len += sprintf(buf + len, "gpi%d:\n ", id);
++ len += block_version(buf + len, base + GPI_VERSION);
++
++ len += sprintf(buf + len, " tx under stick: %x\n", readl(base + GPI_FIFO_STATUS));
++ val = readl(base + GPI_FIFO_DEBUG);
++ len += sprintf(buf + len, " tx pkts: %x\n", (val >> 23) & 0x3f);
++ len += sprintf(buf + len, " rx pkts: %x\n", (val >> 18) & 0x3f);
++ len += sprintf(buf + len, " tx bytes: %x\n", (val >> 9) & 0x1ff);
++ len += sprintf(buf + len, " rx bytes: %x\n", (val >> 0) & 0x1ff);
++ len += sprintf(buf + len, " overrun: %x\n", readl(base + GPI_OVERRUN_DROPCNT));
++
++ return len;
++}
++
++static ssize_t pfe_set_class(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++ class_do_clear = simple_strtoul(buf, NULL, 0);
++ return count;
++}
++
++static ssize_t pfe_show_class(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ ssize_t len = 0;
++ int id;
++ u32 val;
++ struct pfe_cpumon *cpumon = &pfe->cpumon;
++
++ len += block_version(buf + len, CLASS_VERSION);
++
++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++)
++ {
++ len += sprintf(buf + len, "%d: ", id - CLASS0_ID);
++
++ val = readl(CLASS_PE0_DEBUG + id * 4);
++ len += sprintf(buf + len, "pc=1%04x ", val & 0xffff);
++
++ len += display_pe_status(buf + len, id, PESTATUS_ADDR_CLASS, class_do_clear);
++ }
++ len += sprintf(buf + len, "aggregate load=%d%%\n\n", cpumon->class_usage_pct);
++
++ len += sprintf(buf + len, "pe status: 0x%x\n", readl(CLASS_PE_STATUS));
++ len += sprintf(buf + len, "max buf cnt: 0x%x afull thres: 0x%x\n", readl(CLASS_MAX_BUF_CNT), readl(CLASS_AFULL_THRES));
++ len += sprintf(buf + len, "tsq max cnt: 0x%x tsq fifo thres: 0x%x\n", readl(CLASS_TSQ_MAX_CNT), readl(CLASS_TSQ_FIFO_THRES));
++ len += sprintf(buf + len, "state: 0x%x\n", readl(CLASS_STATE));
++
++ len += class_phy_stats(buf + len, 0);
++ len += class_phy_stats(buf + len, 1);
++ len += class_phy_stats(buf + len, 2);
++ len += class_phy_stats(buf + len, 3);
++
++ return len;
++}
++
++static ssize_t pfe_set_tmu(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++ tmu_do_clear = simple_strtoul(buf, NULL, 0);
++ return count;
++}
++
++static ssize_t pfe_show_tmu(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ ssize_t len = 0;
++ int id;
++ u32 val;
++
++ len += block_version(buf + len, TMU_VERSION);
++
++ for (id = TMU0_ID; id <= TMU_MAX_ID; id++)
++ {
++#if defined(CONFIG_PLATFORM_LS1012A)
++ if(id == TMU2_ID) continue;
++#endif
++ len += sprintf(buf + len, "%d: ", id - TMU0_ID);
++
++ len += display_pe_status(buf + len, id, PESTATUS_ADDR_TMU, tmu_do_clear);
++ }
++
++ len += sprintf(buf + len, "pe status: %x\n", readl(TMU_PE_STATUS));
++ len += sprintf(buf + len, "inq fifo cnt: %x\n", readl(TMU_PHY_INQ_FIFO_CNT));
++ val = readl(TMU_INQ_STAT);
++ len += sprintf(buf + len, "inq wr ptr: %x\n", val & 0x3ff);
++ len += sprintf(buf + len, "inq rd ptr: %x\n", val >> 10);
++
++
++ return len;
++}
++
++
++static unsigned long drops_do_clear = 0;
++static u32 CLASS_DMEM_SH2(drop_counter)[CLASS_NUM_DROP_COUNTERS];
++#if !defined(CONFIG_UTIL_DISABLED)
++static u32 UTIL_DMEM_SH2(drop_counter)[UTIL_NUM_DROP_COUNTERS];
++#endif
++
++char *class_drop_description[CLASS_NUM_DROP_COUNTERS] = {
++ "ICC",
++ "Host Pkt Error",
++ "Rx Error",
++ "IPsec Outbound",
++ "IPsec Inbound",
++ "EXPT IPsec Error",
++ "Reassembly",
++ "Fragmenter",
++ "NAT-T",
++ "Socket",
++ "Multicast",
++ "NAT-PT",
++ "Tx Disabled",
++};
++
++#if !defined(CONFIG_UTIL_DISABLED)
++char *util_drop_description[UTIL_NUM_DROP_COUNTERS] = {
++ "IPsec Outbound",
++ "IPsec Inbound",
++ "IPsec Rate Limiter",
++ "Fragmenter",
++ "Socket",
++ "Tx Disabled",
++ "Rx Error",
++};
++#endif
++
++static ssize_t pfe_set_drops(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++ drops_do_clear = simple_strtoul(buf, NULL, 0);
++ return count;
++}
++
++static u32 tmu_drops[4][16];
++static ssize_t pfe_show_drops(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ ssize_t len = 0;
++ int id, dropnum;
++ int tmu, queue;
++ u32 val;
++ u32 dmem_addr;
++ int num_class_drops = 0, num_tmu_drops = 0, num_util_drops = 0;
++ struct pfe_ctrl *ctrl = &pfe->ctrl;
++
++ memset(class_drop_counter, 0, sizeof(class_drop_counter));
++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++)
++ {
++ if (drops_do_clear)
++ pe_sync_stop(ctrl, (1 << id));
++ for (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS; dropnum++)
++ {
++ dmem_addr = virt_to_class_dmem(&class_drop_counter[dropnum]);
++ val = be32_to_cpu(pe_dmem_read(id, dmem_addr, 4));
++ class_drop_counter[dropnum] += val;
++ num_class_drops += val;
++ if (drops_do_clear)
++ pe_dmem_write(id, 0, dmem_addr, 4);
++ }
++ if (drops_do_clear)
++ pe_start(ctrl, (1 << id));
++ }
++
++#if !defined(CONFIG_UTIL_DISABLED)
++ if (drops_do_clear)
++ pe_sync_stop(ctrl, (1 << UTIL_ID));
++ for (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++)
++ {
++ dmem_addr = virt_to_util_dmem(&util_drop_counter[dropnum]);
++ val = be32_to_cpu(pe_dmem_read(UTIL_ID, dmem_addr, 4));
++ util_drop_counter[dropnum] = val;
++ num_util_drops += val;
++ if (drops_do_clear)
++ pe_dmem_write(UTIL_ID, 0, dmem_addr, 4);
++ }
++ if (drops_do_clear)
++ pe_start(ctrl, (1 << UTIL_ID));
++#endif
++ for (tmu = 0; tmu < 4; tmu++)
++ {
++ for (queue = 0; queue < 16; queue++)
++ {
++ qm_read_drop_stat(tmu, queue, &tmu_drops[tmu][queue], drops_do_clear);
++ num_tmu_drops += tmu_drops[tmu][queue];
++ }
++ }
++
++ if (num_class_drops == 0 && num_util_drops == 0 && num_tmu_drops == 0)
++ len += sprintf(buf + len, "No PE drops\n\n");
++
++ if (num_class_drops > 0)
++ {
++ len += sprintf(buf + len, "Class PE drops --\n");
++ for (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS; dropnum++)
++ {
++ if (class_drop_counter[dropnum] > 0)
++ len += sprintf(buf + len, " %s: %d\n", class_drop_description[dropnum], class_drop_counter[dropnum]);
++ }
++ len += sprintf(buf + len, "\n");
++ }
++
++#if !defined(CONFIG_UTIL_DISABLED)
++ if (num_util_drops > 0)
++ {
++ len += sprintf(buf + len, "Util PE drops --\n");
++ for (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++)
++ {
++ if (util_drop_counter[dropnum] > 0)
++ len += sprintf(buf + len, " %s: %d\n", util_drop_description[dropnum], util_drop_counter[dropnum]);
++ }
++ len += sprintf(buf + len, "\n");
++ }
++#endif
++ if (num_tmu_drops > 0)
++ {
++ len += sprintf(buf + len, "TMU drops --\n");
++ for (tmu = 0; tmu < 4; tmu++)
++ {
++ for (queue = 0; queue < 16; queue++)
++ {
++ if (tmu_drops[tmu][queue] > 0)
++ len += sprintf(buf + len, " TMU%d-Q%d: %d\n", tmu, queue, tmu_drops[tmu][queue]);
++ }
++ }
++ len += sprintf(buf + len, "\n");
++ }
++
++ return len;
++}
++
++static ssize_t pfe_show_tmu0_queues(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return tmu_queues(buf, 0);
++}
++
++static ssize_t pfe_show_tmu1_queues(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return tmu_queues(buf, 1);
++}
++
++static ssize_t pfe_show_tmu2_queues(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return tmu_queues(buf, 2);
++}
++
++static ssize_t pfe_show_tmu3_queues(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return tmu_queues(buf, 3);
++}
++
++static ssize_t pfe_show_tmu0_ctx(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return tmu_ctx(buf, 0);
++}
++static ssize_t pfe_show_tmu1_ctx(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return tmu_ctx(buf, 1);
++}
++static ssize_t pfe_show_tmu2_ctx(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return tmu_ctx(buf, 2);
++}
++
++static ssize_t pfe_show_tmu3_ctx(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return tmu_ctx(buf, 3);
++}
++
++
++#if !defined(CONFIG_UTIL_DISABLED)
++static ssize_t pfe_set_util(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++ util_do_clear = simple_strtoul(buf, NULL, 0);
++ return count;
++}
++
++static ssize_t pfe_show_util(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ ssize_t len = 0;
++ struct pfe_ctrl *ctrl = &pfe->ctrl;
++
++
++ len += block_version(buf + len, UTIL_VERSION);
++
++ pe_sync_stop(ctrl, (1 << UTIL_ID));
++ len += display_pe_status(buf + len, UTIL_ID, PESTATUS_ADDR_UTIL, util_do_clear);
++ pe_start(ctrl, (1 << UTIL_ID));
++
++ len += sprintf(buf + len, "pe status: %x\n", readl(UTIL_PE_STATUS));
++ len += sprintf(buf + len, "max buf cnt: %x\n", readl(UTIL_MAX_BUF_CNT));
++ len += sprintf(buf + len, "tsq max cnt: %x\n", readl(UTIL_TSQ_MAX_CNT));
++
++ return len;
++}
++#endif
++
++static ssize_t pfe_show_bmu(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ ssize_t len = 0;
++
++ len += bmu(buf + len, 1, BMU1_BASE_ADDR);
++ len += bmu(buf + len, 2, BMU2_BASE_ADDR);
++
++ return len;
++}
++
++static ssize_t pfe_show_hif(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ ssize_t len = 0;
++
++ len += sprintf(buf + len, "hif:\n ");
++ len += block_version(buf + len, HIF_VERSION);
++
++ len += sprintf(buf + len, " tx curr bd: %x\n", readl(HIF_TX_CURR_BD_ADDR));
++ len += sprintf(buf + len, " tx status: %x\n", readl(HIF_TX_STATUS));
++ len += sprintf(buf + len, " tx dma status: %x\n", readl(HIF_TX_DMA_STATUS));
++
++ len += sprintf(buf + len, " rx curr bd: %x\n", readl(HIF_RX_CURR_BD_ADDR));
++ len += sprintf(buf + len, " rx status: %x\n", readl(HIF_RX_STATUS));
++ len += sprintf(buf + len, " rx dma status: %x\n", readl(HIF_RX_DMA_STATUS));
++
++ len += sprintf(buf + len, "hif nocopy:\n ");
++ len += block_version(buf + len, HIF_NOCPY_VERSION);
++
++ len += sprintf(buf + len, " tx curr bd: %x\n", readl(HIF_NOCPY_TX_CURR_BD_ADDR));
++ len += sprintf(buf + len, " tx status: %x\n", readl(HIF_NOCPY_TX_STATUS));
++ len += sprintf(buf + len, " tx dma status: %x\n", readl(HIF_NOCPY_TX_DMA_STATUS));
++
++ len += sprintf(buf + len, " rx curr bd: %x\n", readl(HIF_NOCPY_RX_CURR_BD_ADDR));
++ len += sprintf(buf + len, " rx status: %x\n", readl(HIF_NOCPY_RX_STATUS));
++ len += sprintf(buf + len, " rx dma status: %x\n", readl(HIF_NOCPY_RX_DMA_STATUS));
++
++ return len;
++}
++
++
++static ssize_t pfe_show_gpi(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ ssize_t len = 0;
++
++ len += gpi(buf + len, 0, EGPI1_BASE_ADDR);
++ len += gpi(buf + len, 1, EGPI2_BASE_ADDR);
++#if !defined(CONFIG_PLATFORM_LS1012A)
++ len += gpi(buf + len, 2, EGPI3_BASE_ADDR);
++#endif
++ len += gpi(buf + len, 3, HGPI_BASE_ADDR);
++
++ return len;
++}
++
++static ssize_t pfe_show_pfemem(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ ssize_t len = 0;
++ struct pfe_memmon *memmon = &pfe->memmon;
++
++ len += sprintf(buf + len, "Kernel Memory: %d Bytes (%d KB)\n", memmon->kernel_memory_allocated, (memmon->kernel_memory_allocated + 1023) / 1024);
++
++ return len;
++}
++
++#ifdef HIF_NAPI_STATS
++static ssize_t pfe_show_hif_napi_stats(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ struct platform_device *pdev = to_platform_device(dev);
++ struct pfe *pfe = platform_get_drvdata(pdev);
++ ssize_t len = 0;
++
++ len += sprintf(buf + len, "sched: %u\n", pfe->hif.napi_counters[NAPI_SCHED_COUNT]);
++ len += sprintf(buf + len, "poll: %u\n", pfe->hif.napi_counters[NAPI_POLL_COUNT]);
++ len += sprintf(buf + len, "packet: %u\n", pfe->hif.napi_counters[NAPI_PACKET_COUNT]);
++ len += sprintf(buf + len, "budget: %u\n", pfe->hif.napi_counters[NAPI_FULL_BUDGET_COUNT]);
++ len += sprintf(buf + len, "desc: %u\n", pfe->hif.napi_counters[NAPI_DESC_COUNT]);
++ len += sprintf(buf + len, "full: %u\n", pfe->hif.napi_counters[NAPI_CLIENT_FULL_COUNT]);
++
++ return len;
++}
++
++static ssize_t pfe_set_hif_napi_stats(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct platform_device *pdev = to_platform_device(dev);
++ struct pfe *pfe = platform_get_drvdata(pdev);
++
++ memset(pfe->hif.napi_counters, 0, sizeof(pfe->hif.napi_counters));
++
++ return count;
++}
++
++static DEVICE_ATTR(hif_napi_stats, 0644, pfe_show_hif_napi_stats, pfe_set_hif_napi_stats);
++#endif
++
++
++static DEVICE_ATTR(class, 0644, pfe_show_class, pfe_set_class);
++static DEVICE_ATTR(tmu, 0644, pfe_show_tmu, pfe_set_tmu);
++#if !defined(CONFIG_UTIL_DISABLED)
++static DEVICE_ATTR(util, 0644, pfe_show_util, pfe_set_util);
++#endif
++static DEVICE_ATTR(bmu, 0444, pfe_show_bmu, NULL);
++static DEVICE_ATTR(hif, 0444, pfe_show_hif, NULL);
++static DEVICE_ATTR(gpi, 0444, pfe_show_gpi, NULL);
++static DEVICE_ATTR(drops, 0644, pfe_show_drops, pfe_set_drops);
++static DEVICE_ATTR(tmu0_queues, 0444, pfe_show_tmu0_queues, NULL);
++static DEVICE_ATTR(tmu1_queues, 0444, pfe_show_tmu1_queues, NULL);
++static DEVICE_ATTR(tmu2_queues, 0444, pfe_show_tmu2_queues, NULL);
++static DEVICE_ATTR(tmu3_queues, 0444, pfe_show_tmu3_queues, NULL);
++static DEVICE_ATTR(tmu0_ctx, 0444, pfe_show_tmu0_ctx, NULL);
++static DEVICE_ATTR(tmu1_ctx, 0444, pfe_show_tmu1_ctx, NULL);
++static DEVICE_ATTR(tmu2_ctx, 0444, pfe_show_tmu2_ctx, NULL);
++static DEVICE_ATTR(tmu3_ctx, 0444, pfe_show_tmu3_ctx, NULL);
++static DEVICE_ATTR(pfemem, 0444, pfe_show_pfemem, NULL);
++
++
++int pfe_sysfs_init(struct pfe *pfe)
++{
++ if (device_create_file(pfe->dev, &dev_attr_class))
++ goto err_class;
++
++ if (device_create_file(pfe->dev, &dev_attr_tmu))
++ goto err_tmu;
++
++#if !defined(CONFIG_UTIL_DISABLED)
++ if (device_create_file(pfe->dev, &dev_attr_util))
++ goto err_util;
++#endif
++
++ if (device_create_file(pfe->dev, &dev_attr_bmu))
++ goto err_bmu;
++
++ if (device_create_file(pfe->dev, &dev_attr_hif))
++ goto err_hif;
++
++ if (device_create_file(pfe->dev, &dev_attr_gpi))
++ goto err_gpi;
++
++ if (device_create_file(pfe->dev, &dev_attr_drops))
++ goto err_drops;
++
++ if (device_create_file(pfe->dev, &dev_attr_tmu0_queues))
++ goto err_tmu0_queues;
++
++ if (device_create_file(pfe->dev, &dev_attr_tmu1_queues))
++ goto err_tmu1_queues;
++
++ if (device_create_file(pfe->dev, &dev_attr_tmu2_queues))
++ goto err_tmu2_queues;
++
++ if (device_create_file(pfe->dev, &dev_attr_tmu3_queues))
++ goto err_tmu3_queues;
++
++ if (device_create_file(pfe->dev, &dev_attr_tmu0_ctx))
++ goto err_tmu0_ctx;
++
++ if (device_create_file(pfe->dev, &dev_attr_tmu1_ctx))
++ goto err_tmu1_ctx;
++
++ if (device_create_file(pfe->dev, &dev_attr_tmu2_ctx))
++ goto err_tmu2_ctx;
++
++ if (device_create_file(pfe->dev, &dev_attr_tmu3_ctx))
++ goto err_tmu3_ctx;
++
++ if (device_create_file(pfe->dev, &dev_attr_pfemem))
++ goto err_pfemem;
++
++#ifdef HIF_NAPI_STATS
++ if (device_create_file(pfe->dev, &dev_attr_hif_napi_stats))
++ goto err_hif_napi_stats;
++#endif
++
++ return 0;
++
++#ifdef HIF_NAPI_STATS
++err_hif_napi_stats:
++ device_remove_file(pfe->dev, &dev_attr_pfemem);
++#endif
++
++err_pfemem:
++ device_remove_file(pfe->dev, &dev_attr_tmu3_ctx);
++
++err_tmu3_ctx:
++ device_remove_file(pfe->dev, &dev_attr_tmu2_ctx);
++
++err_tmu2_ctx:
++ device_remove_file(pfe->dev, &dev_attr_tmu1_ctx);
++
++err_tmu1_ctx:
++ device_remove_file(pfe->dev, &dev_attr_tmu0_ctx);
++
++err_tmu0_ctx:
++ device_remove_file(pfe->dev, &dev_attr_tmu3_queues);
++
++err_tmu3_queues:
++ device_remove_file(pfe->dev, &dev_attr_tmu2_queues);
++
++err_tmu2_queues:
++ device_remove_file(pfe->dev, &dev_attr_tmu1_queues);
++
++err_tmu1_queues:
++ device_remove_file(pfe->dev, &dev_attr_tmu0_queues);
++
++err_tmu0_queues:
++ device_remove_file(pfe->dev, &dev_attr_drops);
++
++err_drops:
++ device_remove_file(pfe->dev, &dev_attr_gpi);
++
++err_gpi:
++ device_remove_file(pfe->dev, &dev_attr_hif);
++
++err_hif:
++ device_remove_file(pfe->dev, &dev_attr_bmu);
++
++err_bmu:
++#if !defined(CONFIG_UTIL_DISABLED)
++ device_remove_file(pfe->dev, &dev_attr_util);
++
++err_util:
++#endif
++ device_remove_file(pfe->dev, &dev_attr_tmu);
++
++err_tmu:
++ device_remove_file(pfe->dev, &dev_attr_class);
++
++err_class:
++ return -1;
++}
++
++
++void pfe_sysfs_exit(struct pfe *pfe)
++{
++#ifdef HIF_NAPI_STATS
++ device_remove_file(pfe->dev, &dev_attr_hif_napi_stats);
++#endif
++
++ device_remove_file(pfe->dev, &dev_attr_pfemem);
++ device_remove_file(pfe->dev, &dev_attr_tmu3_ctx);
++ device_remove_file(pfe->dev, &dev_attr_tmu2_ctx);
++ device_remove_file(pfe->dev, &dev_attr_tmu1_ctx);
++ device_remove_file(pfe->dev, &dev_attr_tmu0_ctx);
++ device_remove_file(pfe->dev, &dev_attr_tmu3_queues);
++ device_remove_file(pfe->dev, &dev_attr_tmu2_queues);
++ device_remove_file(pfe->dev, &dev_attr_tmu1_queues);
++ device_remove_file(pfe->dev, &dev_attr_tmu0_queues);
++ device_remove_file(pfe->dev, &dev_attr_drops);
++ device_remove_file(pfe->dev, &dev_attr_gpi);
++ device_remove_file(pfe->dev, &dev_attr_hif);
++ device_remove_file(pfe->dev, &dev_attr_bmu);
++#if !defined(CONFIG_UTIL_DISABLED)
++ device_remove_file(pfe->dev, &dev_attr_util);
++#endif
++ device_remove_file(pfe->dev, &dev_attr_tmu);
++ device_remove_file(pfe->dev, &dev_attr_class);
++}
++
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_sysfs.h
+@@ -0,0 +1,34 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _PFE_SYSFS_H_
++#define _PFE_SYSFS_H_
++
++#include <linux/proc_fs.h>
++
++#define PESTATUS_ADDR_CLASS 0x800
++#define PESTATUS_ADDR_TMU 0x80
++#define PESTATUS_ADDR_UTIL 0x0
++
++#define TMU_CONTEXT_ADDR 0x3c8
++#define IPSEC_CNTRS_ADDR 0x840
++
++int pfe_sysfs_init(struct pfe *pfe);
++void pfe_sysfs_exit(struct pfe *pfe);
++#endif /* _PFE_SYSFS_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/platform.h
+@@ -0,0 +1,25 @@
++/*
++ *
++ * Copyright (C) 2007 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef _PLATFORM_H_
++#define _PLATFORM_H_
++
++#define virt_to_phys(virt) ((unsigned long)virt)
++
++#endif /* _PLATFORM_H_ */
+--- a/include/linux/skbuff.h
++++ b/include/linux/skbuff.h
+@@ -858,6 +858,17 @@ static inline struct sk_buff *alloc_skb_
+ return __alloc_skb(size, priority, SKB_ALLOC_FCLONE, NUMA_NO_NODE);
+ }
+
++extern struct sk_buff *__alloc_skb_header(unsigned int size, void *data,
++ gfp_t gfp_mask,
++ int fclone,
++ int node);
++static inline struct sk_buff *alloc_skb_header(unsigned int size,
++ u8 *data,
++ gfp_t priority)
++{
++ return __alloc_skb_header(size, data, priority, 0, -1);
++}
++
+ struct sk_buff *__alloc_skb_head(gfp_t priority, int node);
+ static inline struct sk_buff *alloc_skb_head(gfp_t priority)
+ {
+--- a/net/core/skbuff.c
++++ b/net/core/skbuff.c
+@@ -283,6 +283,90 @@ nodata:
+ EXPORT_SYMBOL(__alloc_skb);
+
+ /**
++ * __alloc_skb_header - allocate a network buffer
++ * @size: size to allocate
++ * @gfp_mask: allocation mask
++ * @fclone: allocate from fclone cache instead of head cache
++ * and allocate a cloned (child) skb
++ *
++ * Allocate a new &sk_buff. The returned buffer has no headroom and a
++ * tail room of size bytes. The object has a reference count of one.
++ * The return is the buffer. On a failure the return is %NULL.
++ *
++ * Buffers may only be allocated from interrupts using a @gfp_mask of
++ * %GFP_ATOMIC.
++ */
++struct sk_buff *__alloc_skb_header(unsigned int size, void *data,
++ gfp_t gfp_mask, int fclone, int node)
++{
++ struct kmem_cache *cache;
++ struct skb_shared_info *shinfo;
++ struct sk_buff *skb;
++
++ cache = fclone ? skbuff_fclone_cache : skbuff_head_cache;
++
++ if (size <= SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) {
++ skb = NULL;
++ goto out;
++ }
++
++ /* Get the HEAD */
++ skb = kmem_cache_alloc_node(cache, gfp_mask & ~__GFP_DMA, node);
++ if (!skb)
++ goto out;
++ prefetchw(skb);
++
++ /* kmalloc might give us more room than requested.
++ * Put skb_shared_info exactly at the end of allocated zone,
++ * to allow max possible filling before reallocation.
++ */
++ size = SKB_WITH_OVERHEAD(ksize(data));
++ prefetchw(data + size);
++
++ /* Only clear those fields we need to clear, not those that we will
++ * actually initialise below. Hence, don't put any more fields after
++ * the tail pointer in struct sk_buff!
++ */
++ memset(skb, 0, offsetof(struct sk_buff, tail));
++ /* Account for allocated memory : skb + skb->head */
++ skb->truesize = SKB_TRUESIZE(size);
++ atomic_set(&skb->users, 1);
++ skb->head = data;
++ skb->data = data;
++ skb_reset_tail_pointer(skb);
++ skb->end = skb->tail + size;
++#ifdef NET_SKBUFF_DATA_USES_OFFSET
++ skb->mac_header = ~0U;
++#endif
++
++#if defined(CONFIG_COMCERTO_CUSTOM_SKB_LAYOUT)
++ skb->mspd_data = NULL;
++ skb->mspd_len = 0;
++#endif
++
++ /* make sure we initialize shinfo sequentially */
++ shinfo = skb_shinfo(skb);
++ memset(shinfo, 0, offsetof(struct skb_shared_info, dataref));
++ atomic_set(&shinfo->dataref, 1);
++ kmemcheck_annotate_variable(shinfo->destructor_arg);
++
++ if (fclone) {
++ struct sk_buff *child = skb + 1;
++ atomic_t *fclone_ref = (atomic_t *)(child + 1);
++
++ kmemcheck_annotate_bitfield(child, flags1);
++ kmemcheck_annotate_bitfield(child, flags2);
++ skb->fclone = SKB_FCLONE_ORIG;
++ atomic_set(fclone_ref, 1);
++
++ child->fclone = SKB_FCLONE_UNAVAILABLE;
++ }
++out:
++ return skb;
++}
++EXPORT_SYMBOL(__alloc_skb_header);
++
++/**
+ * __build_skb - build a network buffer
+ * @data: data buffer provided by caller
+ * @frag_size: size of data, or 0 if head was kmalloced
--- /dev/null
+From 9112596c3c7b7b8b1eded3323765fa711dc58e74 Mon Sep 17 00:00:00 2001
+From: Tang Yuantian <Yuantian.Tang@nxp.com>
+Date: Thu, 25 Aug 2016 10:38:28 +0800
+Subject: [PATCH 073/113] ls1012a: added clock configuration
+
+commit c9c11181191938b77bfd61e5094a63955cf711fd
+[context adjustment]
+[don't apply fsl-ls1012a.dtsi]
+
+Currently ls1012a used the clock configuration of ls1043a's.
+But there is a little different between them. This patch added
+ls1012a its own clock configuration.
+
+Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
+Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
+---
+ drivers/clk/clk-qoriq.c | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/drivers/clk/clk-qoriq.c
++++ b/drivers/clk/clk-qoriq.c
+@@ -195,6 +195,14 @@ static const struct clockgen_muxinfo t10
+ }
+ };
+
++static const struct clockgen_muxinfo ls1012a_cmux = {
++ {
++ [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
++ {},
++ [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++ }
++};
++
+ static const struct clockgen_muxinfo t1040_cmux = {
+ {
+ [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
+@@ -475,6 +483,16 @@ static const struct clockgen_chipinfo ch
+ .pll_mask = 0x03,
+ },
+ {
++ .compat = "fsl,ls1012a-clockgen",
++ .cmux_groups = {
++ &ls1012a_cmux
++ },
++ .cmux_to_group = {
++ 0, -1
++ },
++ .pll_mask = 0x03,
++ },
++ {
+ .compat = "fsl,ls1043a-clockgen",
+ .init_periph = t2080_init_periph,
+ .cmux_groups = {
+@@ -1268,6 +1286,7 @@ CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qo
+ CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
++CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
+
+ /* Legacy nodes */
+ CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
--- /dev/null
+From cfe7a6abd3d7e9ffeed8230847bbe2f680757305 Mon Sep 17 00:00:00 2001
+From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Date: Sun, 24 Apr 2016 23:43:19 +0530
+Subject: [PATCH 114/123] drivers: PCIE enable for Linux
+
+[This patch from sdk release, just context adjustment]
+Add support for PCIE for LS1012A in kernel
+
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ drivers/irqchip/irq-ls-scfg-msi.c | 1 +
+ drivers/pci/host/pci-layerscape.c | 7 +++++++
+ 2 files changed, 8 insertions(+)
+
+--- a/drivers/irqchip/irq-ls-scfg-msi.c
++++ b/drivers/irqchip/irq-ls-scfg-msi.c
+@@ -219,6 +219,7 @@ static int ls_scfg_msi_remove(struct pla
+ }
+
+ static const struct of_device_id ls_scfg_msi_id[] = {
++ { .compatible = "fsl,ls1012a-msi", },
+ { .compatible = "fsl,1s1021a-msi", },
+ { .compatible = "fsl,1s1043a-msi", },
+ {},
+--- a/drivers/pci/host/pci-layerscape.c
++++ b/drivers/pci/host/pci-layerscape.c
+@@ -192,6 +192,12 @@ static struct ls_pcie_drvdata ls1021_drv
+ .ops = &ls1021_pcie_host_ops,
+ };
+
++static struct ls_pcie_drvdata ls1012_drvdata = {
++ .lut_offset = 0xC0000,
++ .ltssm_shift = 24,
++ .ops = &ls_pcie_host_ops,
++};
++
+ static struct ls_pcie_drvdata ls1043_drvdata = {
+ .lut_offset = 0x10000,
+ .ltssm_shift = 24,
+@@ -205,6 +211,7 @@ static struct ls_pcie_drvdata ls2080_drv
+ };
+
+ static const struct of_device_id ls_pcie_of_match[] = {
++ { .compatible = "fsl,ls1012a-pcie", .data = &ls1012_drvdata },
+ { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
+ { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
+ { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
--- /dev/null
+From 5d661761fd2354e4f976c83143a1bf7c1ecad766 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Tue, 20 Sep 2016 16:07:10 +0800
+Subject: [PATCH 115/115] PCI: layerscape: call dw_pcie_setup_rc() in host
+ initialization
+
+A previous patch moved some Root Complex programming from
+dw_pcie_host_init() to dw_pcie_setup_rc() where it belongs,
+while the pci-layerscape driver didn't call dw_pcie_setup_rc()
+anywhere after that. This patch is to add dw_pcie_setup_rc()
+calling in layerscape host initialization to fix ls1012a pci
+issue caused by that patch.
+
+Fixes: c49b76f3c613("PCI: designware: Move Root Complex setup
+ code to dw_pcie_setup_rc()")
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/pci/host/pci-layerscape.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/pci/host/pci-layerscape.c
++++ b/drivers/pci/host/pci-layerscape.c
+@@ -148,6 +148,7 @@ static void ls_pcie_host_init(struct pci
+ {
+ struct ls_pcie *pcie = to_ls_pcie(pp);
+
++ dw_pcie_setup_rc(pp);
+ iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
+ ls_pcie_fix_class(pcie);
+ ls_pcie_clear_multifunction(pcie);
projects / openwrt / openwrt.git / commitdiff