+++ /dev/null
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_AT803X_PHY=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-# CONFIG_CLKEVT_RT3352 is not set
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7620A_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=m
-CONFIG_HZ_PERIODIC=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INET_LRO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_WORK=y
-CONFIG_M25PXX_USE_FAST_READ=y
-CONFIG_MDIO_BOARDINFO=y
-# CONFIG_MII is not set
-CONFIG_MIPS=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND_MT7620=y
-CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_UIMAGE_SPLIT=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK=y
-CONFIG_NET_RALINK_GSW_MT7620=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NLS=m
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PINCONF is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINMUX=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RALINK=y
-CONFIG_RALINK_USBPHY=y
-CONFIG_RALINK_WDT=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_SAMSUNG_USB2PHY is not set
-# CONFIG_SAMSUNG_USB3PHY is not set
-# CONFIG_SAMSUNG_USBPHY is not set
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SOC_MT7620=y
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_RT2880=y
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_USB=m
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_COMMON=m
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_PHY=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-# CONFIG_CLKEVT_RT3352 is not set
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7620A_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=m
-CONFIG_HZ_PERIODIC=y
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_M25PXX_USE_FAST_READ=y
-CONFIG_MDIO_BOARDINFO=y
-# CONFIG_MII is not set
-CONFIG_MIPS=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-# CONFIG_MTD_NAND_MT7620 is not set
-CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_UIMAGE_SPLIT=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK=y
-CONFIG_NET_RALINK_GSW_MT7620=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NLS=m
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-# CONFIG_PCI is not set
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PINCONF is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINMUX=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RALINK=y
-CONFIG_RALINK_GDMA=y
-CONFIG_RALINK_USBPHY=y
-CONFIG_RALINK_WDT=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_SAMSUNG_USB2PHY is not set
-# CONFIG_SAMSUNG_USB3PHY is not set
-# CONFIG_SAMSUNG_USBPHY is not set
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SOC_MT7620=y
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_RT2880=y
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_USB=m
-# CONFIG_USB_ARCH_HAS_XHCI is not set
-CONFIG_USB_COMMON=m
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_PHY=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-# CONFIG_32B_DESC is not set
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_BOARD_SCACHE=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_CEVT_GIC is not set
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_MIPSR2_IRQ_EI=y
-CONFIG_CPU_MIPSR2_IRQ_VI=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7621_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_ESW_DOUBLE_VLAN_TAG=y
-# CONFIG_GE1_MII_AN is not set
-# CONFIG_GE1_MII_FORCE_100 is not set
-# CONFIG_GE1_RGMII_AN is not set
-CONFIG_GE1_RGMII_FORCE_1000=y
-# CONFIG_GE1_RGMII_NONE is not set
-# CONFIG_GE1_RVMII_FORCE_100 is not set
-# CONFIG_GE1_TRGMII_FORCE_1200 is not set
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-# CONFIG_GPIO_MT7621 is not set
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=m
-CONFIG_HZ_PERIODIC=y
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_GIC=y
-CONFIG_IRQ_WORK=y
-# CONFIG_LAN_WAN_SUPPORT is not set
-CONFIG_M25PXX_USE_FAST_READ=y
-CONFIG_MDIO_BOARDINFO=y
-# CONFIG_MII is not set
-CONFIG_MIPS=y
-CONFIG_MIPS_CMP=y
-CONFIG_MIPS_CPU_SCACHE=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=6
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT=y
-# CONFIG_MIPS_MT_DISABLED is not set
-CONFIG_MIPS_MT_FPAFF=y
-CONFIG_MIPS_MT_SMP=y
-# CONFIG_MIPS_MT_SMTC is not set
-CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
-# CONFIG_MIPS_VPE_LOADER is not set
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MT7621_ASIC=y
-# CONFIG_MT7621_WDT is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_UIMAGE_SPLIT=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-# CONFIG_NET_RALINK is not set
-CONFIG_NLS=m
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NR_CPUS=4
-CONFIG_NR_CPUS_DEFAULT_2=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PDMA_NEW=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PINCONF is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINMUX=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RAETH=y
-CONFIG_RAETH_CHECKSUM_OFFLOAD=y
-# CONFIG_RAETH_GMAC2 is not set
-# CONFIG_RAETH_HW_VLAN_RX is not set
-# CONFIG_RAETH_HW_VLAN_TX is not set
-# CONFIG_RAETH_LRO is not set
-# CONFIG_RAETH_NAPI is not set
-# CONFIG_RAETH_QDMA is not set
-CONFIG_RAETH_SCATTER_GATHER_RX_DMA=y
-# CONFIG_RAETH_SKB_RECYCLE_2K is not set
-# CONFIG_RAETH_SPECIAL_TAG is not set
-# CONFIG_RAETH_TSO is not set
-CONFIG_RALINK=y
-CONFIG_RALINK_MT7621=y
-CONFIG_RALINK_USBPHY=y
-# CONFIG_RALINK_WDT is not set
-CONFIG_RA_NAT_NONE=y
-# CONFIG_RA_NETWORK_TASKLET_BH is not set
-CONFIG_RA_NETWORK_WORKQUEUE_BH=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RT_3052_ESW=y
-# CONFIG_SAMSUNG_USB2PHY is not set
-# CONFIG_SAMSUNG_USB3PHY is not set
-# CONFIG_SAMSUNG_USBPHY is not set
-CONFIG_SCHED_SMT=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SMP=y
-CONFIG_SMP_UP=y
-# CONFIG_SOC_MT7620 is not set
-CONFIG_SOC_MT7621=y
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_RT2880=y
-CONFIG_STOP_MACHINE=y
-CONFIG_SWCONFIG=y
-CONFIG_SYNC_R4K=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS_CMP=y
-CONFIG_SYS_SUPPORTS_MULTITHREADING=y
-CONFIG_SYS_SUPPORTS_SCHED_SMT=y
-CONFIG_SYS_SUPPORTS_SMP=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TREE_RCU=y
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_USB=m
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_COMMON=m
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_MT7621_XHCI_PLATFORM=y
-CONFIG_USB_PHY=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USB_XHCI_HCD=m
-# CONFIG_USB_XHCI_HCD_DEBUGGING is not set
-CONFIG_USB_XHCI_PLATFORM=y
-CONFIG_USE_GENERIC_SMP_HELPERS=y
-CONFIG_USE_OF=y
-CONFIG_WAN_AT_P0=y
-# CONFIG_WAN_AT_P4 is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WEAK_ORDERING=y
-CONFIG_XPS=y
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-From d11f6e47eb748f27ba325bd843cc88bae3ad0e8a Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Tue, 29 Jan 2013 21:11:55 +0100
-Subject: [PATCH 01/25] MTD: m25p80: allow loading mtd name from OF
-
-In accordance with the physmap flash we should honour the linux,mtd-name
-property when deciding what name the mtd device has.
-
-Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/mtd/devices/m25p80.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/drivers/mtd/devices/m25p80.c
-+++ b/drivers/mtd/devices/m25p80.c
-@@ -927,10 +927,13 @@ static int m25p_probe(struct spi_device
- unsigned i;
- struct mtd_part_parser_data ppdata;
- struct device_node __maybe_unused *np = spi->dev.of_node;
-+ const char __maybe_unused *of_mtd_name = NULL;
-
- #ifdef CONFIG_MTD_OF_PARTS
- if (!of_device_is_available(np))
- return -ENODEV;
-+ of_property_read_string(spi->dev.of_node,
-+ "linux,mtd-name", &of_mtd_name);
- #endif
-
- /* Platform data helps sort out which chip type we have, as
-@@ -1006,6 +1009,8 @@ static int m25p_probe(struct spi_device
-
- if (data && data->name)
- flash->mtd.name = data->name;
-+ else if (of_mtd_name)
-+ flash->mtd.name = of_mtd_name;
- else
- flash->mtd.name = dev_name(&spi->dev);
-
+++ /dev/null
-From 080f1a0c539180a88066fb004a8c31eefdf74161 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 9 Aug 2013 18:47:27 +0200
-Subject: [PATCH 02/25] reset: Fix compile when reset RESET_CONTROLLER is not
- selected
-
-Drivers need to protect their reset api calls with #ifdef to avoid compile
-errors.
-
-This patch adds dummy wrappers in the same way that linux/of.h does it.
-
-Cc: linux-kernel@vger.kernel.org
-Cc: Philipp Zabel <p.zabel@pengutronix.de>
-Cc: Gabor Juhos <juhosg@openwrt.org>
----
- include/linux/reset-controller.h | 16 ++++++++++++++
- include/linux/reset.h | 43 ++++++++++++++++++++++++++++++++++++++
- 2 files changed, 59 insertions(+)
-
---- a/include/linux/reset-controller.h
-+++ b/include/linux/reset-controller.h
-@@ -45,7 +45,23 @@ struct reset_controller_dev {
- unsigned int nr_resets;
- };
-
-+#if defined(CONFIG_RESET_CONTROLLER)
-+
- int reset_controller_register(struct reset_controller_dev *rcdev);
- void reset_controller_unregister(struct reset_controller_dev *rcdev);
-
-+#else
-+
-+static inline int reset_controller_register(struct reset_controller_dev *rcdev)
-+{
-+ return -ENOSYS;
-+}
-+
-+void reset_controller_unregister(struct reset_controller_dev *rcdev)
-+{
-+
-+}
-+
-+#endif
-+
- #endif
---- a/include/linux/reset.h
-+++ b/include/linux/reset.h
-@@ -1,9 +1,13 @@
- #ifndef _LINUX_RESET_H_
- #define _LINUX_RESET_H_
-
-+#include <linux/err.h>
-+
- struct device;
- struct reset_control;
-
-+#if defined(CONFIG_RESET_CONTROLLER)
-+
- int reset_control_reset(struct reset_control *rstc);
- int reset_control_assert(struct reset_control *rstc);
- int reset_control_deassert(struct reset_control *rstc);
-@@ -14,4 +18,43 @@ struct reset_control *devm_reset_control
-
- int device_reset(struct device *dev);
-
-+#else /* CONFIG_RESET_CONTROLLER */
-+
-+static inline int reset_control_reset(struct reset_control *rstc)
-+{
-+ return -ENOSYS;
-+}
-+
-+static inline int reset_control_assert(struct reset_control *rstc)
-+{
-+ return -ENOSYS;
-+}
-+
-+static inline int reset_control_deassert(struct reset_control *rstc)
-+{
-+ return -ENOSYS;
-+}
-+
-+static inline struct reset_control *reset_control_get(struct device *dev, const char *id)
-+{
-+ return ERR_PTR(-ENOSYS);
-+}
-+
-+static inline void reset_control_put(struct reset_control *rstc)
-+{
-+
-+}
-+
-+static inline struct reset_control *devm_reset_control_get(struct device *dev, const char *id)
-+{
-+ return ERR_PTR(-ENOSYS);
-+}
-+
-+static inline int device_reset(struct device *dev)
-+{
-+ return -ENOSYS;
-+}
-+
-+#endif
-+
- #endif
+++ /dev/null
-From 8b87087423057f8a06423702f3035634d6e8cd73 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 19:57:20 +0200
-Subject: [PATCH 03/25] DT: Add documentation for rt2880-wdt
-
-This document describes the binding of the watchdog core found ralink wireless
-SoC.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Cc: linux-watchdog@vger.kernel.org
-Cc: linux-mips@linux-mips.org
-Cc: devicetree-discuss@lists.ozlabs.org
----
- .../devicetree/bindings/watchdog/rt2880-wdt.txt | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/watchdog/rt2880-wdt.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/watchdog/rt2880-wdt.txt
-@@ -0,0 +1,19 @@
-+Ralink Watchdog Timers
-+
-+Required properties :
-+- compatible: must be "ralink,rt2880-wdt"
-+- reg: physical base address of the controller and length of the register range
-+
-+Optional properties :
-+- interrupt-parent: phandle to the INTC device node
-+- interrupts: Specify the INTC interrupt number
-+
-+Example:
-+
-+ watchdog@120 {
-+ compatible = "ralink,rt2880-wdt";
-+ reg = <0x120 0x10>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <1>;
-+ };
+++ /dev/null
-From 78046b68c1fc757162e32c83f59c3a94e794bf2e Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 13:51:58 +0200
-Subject: [PATCH 04/25] watchdog: MIPS: add ralink watchdog driver
-
-Add a driver for the watchdog timer found on Ralink SoC
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Cc: linux-watchdog@vger.kernel.org
-Cc: linux-mips@linux-mips.org
----
- drivers/watchdog/Kconfig | 7 ++
- drivers/watchdog/Makefile | 1 +
- drivers/watchdog/rt2880_wdt.c | 208 +++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 216 insertions(+)
- create mode 100644 drivers/watchdog/rt2880_wdt.c
-
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -1113,6 +1113,13 @@ config LANTIQ_WDT
- help
- Hardware driver for the Lantiq SoC Watchdog Timer.
-
-+config RALINK_WDT
-+ tristate "Ralink SoC watchdog"
-+ select WATCHDOG_CORE
-+ depends on RALINK
-+ help
-+ Hardware driver for the Ralink SoC Watchdog Timer.
-+
- # PARISC Architecture
-
- # POWERPC Architecture
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -135,6 +135,7 @@ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
- obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o
- octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
- obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o
-+obj-$(CONFIG_RALINK_WDT) += rt2880_wdt.o
-
- # PARISC Architecture
-
---- /dev/null
-+++ b/drivers/watchdog/rt2880_wdt.c
-@@ -0,0 +1,208 @@
-+/*
-+ * Ralink RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
-+ *
-+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ *
-+ * This driver was based on: drivers/watchdog/softdog.c
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/reset.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/watchdog.h>
-+#include <linux/miscdevice.h>
-+#include <linux/moduleparam.h>
-+#include <linux/platform_device.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+
-+#define SYSC_RSTSTAT 0x38
-+#define WDT_RST_CAUSE BIT(1)
-+
-+#define RALINK_WDT_TIMEOUT 30
-+#define RALINK_WDT_PRESCALE 65536
-+
-+#define TIMER_REG_TMR1LOAD 0x00
-+#define TIMER_REG_TMR1CTL 0x08
-+
-+#define TMRSTAT_TMR1RST BIT(5)
-+
-+#define TMR1CTL_ENABLE BIT(7)
-+#define TMR1CTL_MODE_SHIFT 4
-+#define TMR1CTL_MODE_MASK 0x3
-+#define TMR1CTL_MODE_FREE_RUNNING 0x0
-+#define TMR1CTL_MODE_PERIODIC 0x1
-+#define TMR1CTL_MODE_TIMEOUT 0x2
-+#define TMR1CTL_MODE_WDT 0x3
-+#define TMR1CTL_PRESCALE_MASK 0xf
-+#define TMR1CTL_PRESCALE_65536 0xf
-+
-+static struct clk *rt288x_wdt_clk;
-+static unsigned long rt288x_wdt_freq;
-+static void __iomem *rt288x_wdt_base;
-+
-+static bool nowayout = WATCHDOG_NOWAYOUT;
-+module_param(nowayout, bool, 0);
-+MODULE_PARM_DESC(nowayout,
-+ "Watchdog cannot be stopped once started (default="
-+ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
-+
-+static inline void rt_wdt_w32(unsigned reg, u32 val)
-+{
-+ iowrite32(val, rt288x_wdt_base + reg);
-+}
-+
-+static inline u32 rt_wdt_r32(unsigned reg)
-+{
-+ return ioread32(rt288x_wdt_base + reg);
-+}
-+
-+static int rt288x_wdt_ping(struct watchdog_device *w)
-+{
-+ rt_wdt_w32(TIMER_REG_TMR1LOAD, w->timeout * rt288x_wdt_freq);
-+
-+ return 0;
-+}
-+
-+static int rt288x_wdt_start(struct watchdog_device *w)
-+{
-+ u32 t;
-+
-+ t = rt_wdt_r32(TIMER_REG_TMR1CTL);
-+ t &= ~(TMR1CTL_MODE_MASK << TMR1CTL_MODE_SHIFT |
-+ TMR1CTL_PRESCALE_MASK);
-+ t |= (TMR1CTL_MODE_WDT << TMR1CTL_MODE_SHIFT |
-+ TMR1CTL_PRESCALE_65536);
-+ rt_wdt_w32(TIMER_REG_TMR1CTL, t);
-+
-+ rt288x_wdt_ping(w);
-+
-+ t = rt_wdt_r32(TIMER_REG_TMR1CTL);
-+ t |= TMR1CTL_ENABLE;
-+ rt_wdt_w32(TIMER_REG_TMR1CTL, t);
-+
-+ return 0;
-+}
-+
-+static int rt288x_wdt_stop(struct watchdog_device *w)
-+{
-+ u32 t;
-+
-+ rt288x_wdt_ping(w);
-+
-+ t = rt_wdt_r32(TIMER_REG_TMR1CTL);
-+ t &= ~TMR1CTL_ENABLE;
-+ rt_wdt_w32(TIMER_REG_TMR1CTL, t);
-+
-+ return 0;
-+}
-+
-+static int rt288x_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
-+{
-+ w->timeout = t;
-+ rt288x_wdt_ping(w);
-+
-+ return 0;
-+}
-+
-+static int rt288x_wdt_bootcause(void)
-+{
-+ if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
-+ return WDIOF_CARDRESET;
-+
-+ return 0;
-+}
-+
-+static struct watchdog_info rt288x_wdt_info = {
-+ .identity = "Ralink Watchdog",
-+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
-+};
-+
-+static struct watchdog_ops rt288x_wdt_ops = {
-+ .owner = THIS_MODULE,
-+ .start = rt288x_wdt_start,
-+ .stop = rt288x_wdt_stop,
-+ .ping = rt288x_wdt_ping,
-+ .set_timeout = rt288x_wdt_set_timeout,
-+};
-+
-+static struct watchdog_device rt288x_wdt_dev = {
-+ .info = &rt288x_wdt_info,
-+ .ops = &rt288x_wdt_ops,
-+ .min_timeout = 1,
-+};
-+
-+static int rt288x_wdt_probe(struct platform_device *pdev)
-+{
-+ struct resource *res;
-+ int ret;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ rt288x_wdt_base = devm_request_and_ioremap(&pdev->dev, res);
-+ if (IS_ERR(rt288x_wdt_base))
-+ return PTR_ERR(rt288x_wdt_base);
-+
-+ rt288x_wdt_clk = devm_clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(rt288x_wdt_clk))
-+ return PTR_ERR(rt288x_wdt_clk);
-+
-+ device_reset(&pdev->dev);
-+
-+ rt288x_wdt_freq = clk_get_rate(rt288x_wdt_clk) / RALINK_WDT_PRESCALE;
-+
-+ rt288x_wdt_dev.dev = &pdev->dev;
-+ rt288x_wdt_dev.bootstatus = rt288x_wdt_bootcause();
-+
-+ rt288x_wdt_dev.max_timeout = (0xfffful / rt288x_wdt_freq);
-+ rt288x_wdt_dev.timeout = rt288x_wdt_dev.max_timeout;
-+
-+ watchdog_set_nowayout(&rt288x_wdt_dev, nowayout);
-+
-+ ret = watchdog_register_device(&rt288x_wdt_dev);
-+ if (!ret)
-+ dev_info(&pdev->dev, "Initialized\n");
-+
-+ return 0;
-+}
-+
-+static int rt288x_wdt_remove(struct platform_device *pdev)
-+{
-+ watchdog_unregister_device(&rt288x_wdt_dev);
-+
-+ return 0;
-+}
-+
-+static void rt288x_wdt_shutdown(struct platform_device *pdev)
-+{
-+ rt288x_wdt_stop(&rt288x_wdt_dev);
-+}
-+
-+static const struct of_device_id rt288x_wdt_match[] = {
-+ { .compatible = "ralink,rt2880-wdt" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
-+
-+static struct platform_driver rt288x_wdt_driver = {
-+ .probe = rt288x_wdt_probe,
-+ .remove = rt288x_wdt_remove,
-+ .shutdown = rt288x_wdt_shutdown,
-+ .driver = {
-+ .name = KBUILD_MODNAME,
-+ .owner = THIS_MODULE,
-+ .of_match_table = rt288x_wdt_match,
-+ },
-+};
-+
-+module_platform_driver(rt288x_wdt_driver);
-+
-+MODULE_DESCRIPTION("MediaTek/Ralink RT288x/RT3xxx hardware watchdog driver");
-+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
+++ /dev/null
-From ad68c2865b360f1b637432b4cbcaaf101d2687b9 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 19:45:30 +0200
-Subject: [PATCH 05/25] DT: Add documentation for gpio-ralink
-
-Describe gpio-ralink binding.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: devicetree@vger.kernel.org
-Cc: linux-gpio@vger.kernel.org
----
- .../devicetree/bindings/gpio/gpio-ralink.txt | 40 ++++++++++++++++++++
- 1 file changed, 40 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
-@@ -0,0 +1,40 @@
-+Ralink SoC GPIO controller bindings
-+
-+Required properties:
-+- compatible:
-+ - "ralink,rt2880-gpio" for Ralink controllers
-+- #gpio-cells : Should be two.
-+ - first cell is the pin number
-+ - second cell is used to specify optional parameters (unused)
-+- gpio-controller : Marks the device node as a GPIO controller
-+- reg : Physical base address and length of the controller's registers
-+- interrupt-parent: phandle to the INTC device node
-+- interrupts : Specify the INTC interrupt number
-+- ralink,num-gpios : Specify the number of GPIOs
-+- ralink,register-map : The register layout depends on the GPIO bank and actual
-+ SoC type. Register offsets need to be in this order.
-+ [ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
-+
-+Optional properties:
-+- ralink,gpio-base : Specify the GPIO chips base number
-+
-+Example:
-+
-+ gpio0: gpio@600 {
-+ compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
-+
-+ #gpio-cells = <2>;
-+ gpio-controller;
-+
-+ reg = <0x600 0x34>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <6>;
-+
-+ ralink,gpio-base = <0>;
-+ ralink,num-gpios = <24>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 20 24 28 2c
-+ 30 34 ];
-+
-+ };
+++ /dev/null
-From 55833373cf527dc94bc6c63b68d0f39591667a5d Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 14:00:25 +0200
-Subject: [PATCH 06/25] GPIO: MIPS: ralink: add gpio driver for ralink SoC
-
-Add gpio driver for Ralink SoC. This driver makes the gpio core on
-RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: linux-gpio@vger.kernel.org
----
- arch/mips/Kconfig | 1 +
- arch/mips/include/asm/mach-ralink/gpio.h | 24 +++
- drivers/gpio/Kconfig | 6 +
- drivers/gpio/Makefile | 1 +
- drivers/gpio/gpio-ralink.c | 337 ++++++++++++++++++++++++++++++
- 5 files changed, 369 insertions(+)
- create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
- create mode 100644 drivers/gpio/gpio-ralink.c
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -444,6 +444,7 @@ config RALINK
- select SYS_HAS_EARLY_PRINTK
- select HAVE_MACH_CLKDEV
- select CLKDEV_LOOKUP
-+ select ARCH_REQUIRE_GPIOLIB
-
- config SGI_IP22
- bool "SGI IP22 (Indy/Indigo2)"
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ralink/gpio.h
-@@ -0,0 +1,24 @@
-+/*
-+ * Ralink SoC GPIO API support
-+ *
-+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ */
-+
-+#ifndef __ASM_MACH_RALINK_GPIO_H
-+#define __ASM_MACH_RALINK_GPIO_H
-+
-+#define ARCH_NR_GPIOS 128
-+#include <asm-generic/gpio.h>
-+
-+#define gpio_get_value __gpio_get_value
-+#define gpio_set_value __gpio_set_value
-+#define gpio_cansleep __gpio_cansleep
-+#define gpio_to_irq __gpio_to_irq
-+
-+#endif /* __ASM_MACH_RALINK_GPIO_H */
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -209,6 +209,12 @@ config GPIO_RCAR
- help
- Say yes here to support GPIO on Renesas R-Car SoCs.
-
-+config GPIO_RALINK
-+ bool "Ralink GPIO Support"
-+ depends on RALINK
-+ help
-+ Say yes here to support the Ralink SoC GPIO device
-+
- config GPIO_SPEAR_SPICS
- bool "ST SPEAr13xx SPI Chip Select as GPIO support"
- depends on PLAT_SPEAR
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -56,6 +56,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf85
- obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
- obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
- obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
-+obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
- obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
- obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
- obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
---- /dev/null
-+++ b/drivers/gpio/gpio-ralink.c
-@@ -0,0 +1,345 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/io.h>
-+#include <linux/gpio.h>
-+#include <linux/spinlock.h>
-+#include <linux/platform_device.h>
-+#include <linux/of_irq.h>
-+#include <linux/irqdomain.h>
-+#include <linux/interrupt.h>
-+
-+enum ralink_gpio_reg {
-+ GPIO_REG_INT = 0,
-+ GPIO_REG_EDGE,
-+ GPIO_REG_RENA,
-+ GPIO_REG_FENA,
-+ GPIO_REG_DATA,
-+ GPIO_REG_DIR,
-+ GPIO_REG_POL,
-+ GPIO_REG_SET,
-+ GPIO_REG_RESET,
-+ GPIO_REG_TOGGLE,
-+ GPIO_REG_MAX
-+};
-+
-+struct ralink_gpio_chip {
-+ struct gpio_chip chip;
-+ u8 regs[GPIO_REG_MAX];
-+
-+ spinlock_t lock;
-+ void __iomem *membase;
-+ struct irq_domain *domain;
-+ int irq;
-+
-+ u32 rising;
-+ u32 falling;
-+};
-+
-+#define MAP_MAX 4
-+static struct irq_domain *irq_map[MAP_MAX];
-+static int irq_map_count;
-+static atomic_t irq_refcount = ATOMIC_INIT(0);
-+
-+static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
-+{
-+ struct ralink_gpio_chip *rg;
-+
-+ rg = container_of(chip, struct ralink_gpio_chip, chip);
-+
-+ return rg;
-+}
-+
-+static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
-+{
-+ iowrite32(val, rg->membase + rg->regs[reg]);
-+}
-+
-+static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
-+{
-+ return ioread32(rg->membase + rg->regs[reg]);
-+}
-+
-+static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-+{
-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+
-+ rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
-+}
-+
-+static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
-+{
-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+
-+ return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
-+}
-+
-+static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-+{
-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+ unsigned long flags;
-+ u32 t;
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ t = rt_gpio_r32(rg, GPIO_REG_DIR);
-+ t &= ~BIT(offset);
-+ rt_gpio_w32(rg, GPIO_REG_DIR, t);
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int ralink_gpio_direction_output(struct gpio_chip *chip,
-+ unsigned offset, int value)
-+{
-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+ unsigned long flags;
-+ u32 t;
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ ralink_gpio_set(chip, offset, value);
-+ t = rt_gpio_r32(rg, GPIO_REG_DIR);
-+ t |= BIT(offset);
-+ rt_gpio_w32(rg, GPIO_REG_DIR, t);
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
-+{
-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+
-+ if (rg->irq < 1)
-+ return -1;
-+
-+ return irq_create_mapping(rg->domain, pin);
-+}
-+
-+static void ralink_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
-+{
-+ int i;
-+
-+ for (i = 0; i < irq_map_count; i++) {
-+ struct irq_domain *domain = irq_map[i];
-+ struct ralink_gpio_chip *rg;
-+ unsigned long pending;
-+ int bit;
-+
-+ rg = (struct ralink_gpio_chip *) domain->host_data;
-+ pending = rt_gpio_r32(rg, GPIO_REG_INT);
-+
-+ for_each_set_bit(bit, &pending, rg->chip.ngpio) {
-+ u32 map = irq_find_mapping(domain, bit);
-+ generic_handle_irq(map);
-+ rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
-+ }
-+ }
-+}
-+
-+static void ralink_gpio_irq_unmask(struct irq_data *d)
-+{
-+ struct ralink_gpio_chip *rg;
-+ unsigned long flags;
-+ u32 val;
-+
-+ rg = (struct ralink_gpio_chip *) d->domain->host_data;
-+ val = rt_gpio_r32(rg, GPIO_REG_RENA);
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ rt_gpio_w32(rg, GPIO_REG_RENA, val | (BIT(d->hwirq) & rg->rising));
-+ rt_gpio_w32(rg, GPIO_REG_FENA, val | (BIT(d->hwirq) & rg->falling));
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+}
-+
-+static void ralink_gpio_irq_mask(struct irq_data *d)
-+{
-+ struct ralink_gpio_chip *rg;
-+ unsigned long flags;
-+ u32 val;
-+
-+ rg = (struct ralink_gpio_chip *) d->domain->host_data;
-+ val = rt_gpio_r32(rg, GPIO_REG_RENA);
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ rt_gpio_w32(rg, GPIO_REG_FENA, val & ~BIT(d->hwirq));
-+ rt_gpio_w32(rg, GPIO_REG_RENA, val & ~BIT(d->hwirq));
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+}
-+
-+static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
-+{
-+ struct ralink_gpio_chip *rg;
-+ u32 mask = BIT(d->hwirq);
-+
-+ rg = (struct ralink_gpio_chip *) d->domain->host_data;
-+
-+ if (type == IRQ_TYPE_PROBE) {
-+ if ((rg->rising | rg->falling) & mask)
-+ return 0;
-+
-+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
-+ }
-+
-+ if (type & IRQ_TYPE_EDGE_RISING)
-+ rg->rising |= mask;
-+ else
-+ rg->rising &= ~mask;
-+
-+ if (type & IRQ_TYPE_EDGE_FALLING)
-+ rg->falling |= mask;
-+ else
-+ rg->falling &= ~mask;
-+
-+ return 0;
-+}
-+
-+static struct irq_chip ralink_gpio_irq_chip = {
-+ .name = "GPIO",
-+ .irq_unmask = ralink_gpio_irq_unmask,
-+ .irq_mask = ralink_gpio_irq_mask,
-+ .irq_mask_ack = ralink_gpio_irq_mask,
-+ .irq_set_type = ralink_gpio_irq_type,
-+};
-+
-+static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
-+{
-+ irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
-+ irq_set_handler_data(irq, d);
-+
-+ return 0;
-+}
-+
-+static const struct irq_domain_ops irq_domain_ops = {
-+ .xlate = irq_domain_xlate_onecell,
-+ .map = gpio_map,
-+};
-+
-+static void ralink_gpio_irq_init(struct device_node *np,
-+ struct ralink_gpio_chip *rg)
-+{
-+ if (irq_map_count >= MAP_MAX)
-+ return;
-+
-+ rg->irq = irq_of_parse_and_map(np, 0);
-+ if (!rg->irq)
-+ return;
-+
-+ rg->domain = irq_domain_add_linear(np, rg->chip.ngpio,
-+ &irq_domain_ops, rg);
-+ if (!rg->domain) {
-+ dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
-+ return;
-+ }
-+
-+ irq_map[irq_map_count++] = rg->domain;
-+
-+ rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
-+ rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
-+
-+ if (!atomic_read(&irq_refcount))
-+ irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
-+ atomic_inc(&irq_refcount);
-+
-+ dev_info(rg->chip.dev, "registering %d irq handlers\n", rg->chip.ngpio);
-+}
-+
-+static int ralink_gpio_request(struct gpio_chip *chip, unsigned offset)
-+{
-+ int gpio = chip->base + offset;
-+
-+ return pinctrl_request_gpio(gpio);
-+}
-+
-+static int ralink_gpio_probe(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ struct ralink_gpio_chip *rg;
-+ const __be32 *ngpio, *gpiobase;
-+
-+ if (!res) {
-+ dev_err(&pdev->dev, "failed to find resource\n");
-+ return -ENOMEM;
-+ }
-+
-+ rg = devm_kzalloc(&pdev->dev,
-+ sizeof(struct ralink_gpio_chip), GFP_KERNEL);
-+ if (!rg)
-+ return -ENOMEM;
-+
-+ rg->membase = devm_request_and_ioremap(&pdev->dev, res);
-+ if (!rg->membase) {
-+ dev_err(&pdev->dev, "cannot remap I/O memory region\n");
-+ return -ENOMEM;
-+ }
-+
-+ if (of_property_read_u8_array(np, "ralink,register-map",
-+ rg->regs, GPIO_REG_MAX)) {
-+ dev_err(&pdev->dev, "failed to read register definition\n");
-+ return -EINVAL;
-+ }
-+
-+ ngpio = of_get_property(np, "ralink,num-gpios", NULL);
-+ if (!ngpio) {
-+ dev_err(&pdev->dev, "failed to read number of pins\n");
-+ return -EINVAL;
-+ }
-+
-+ gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
-+ if (gpiobase)
-+ rg->chip.base = be32_to_cpu(*gpiobase);
-+ else
-+ rg->chip.base = -1;
-+
-+ spin_lock_init(&rg->lock);
-+
-+ rg->chip.dev = &pdev->dev;
-+ rg->chip.label = dev_name(&pdev->dev);
-+ rg->chip.of_node = np;
-+ rg->chip.ngpio = be32_to_cpu(*ngpio);
-+ rg->chip.direction_input = ralink_gpio_direction_input;
-+ rg->chip.direction_output = ralink_gpio_direction_output;
-+ rg->chip.get = ralink_gpio_get;
-+ rg->chip.set = ralink_gpio_set;
-+ rg->chip.request = ralink_gpio_request;
-+ rg->chip.to_irq = ralink_gpio_to_irq;
-+
-+ /* set polarity to low for all lines */
-+ rt_gpio_w32(rg, GPIO_REG_POL, 0);
-+
-+ dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
-+
-+ ralink_gpio_irq_init(np, rg);
-+
-+ return gpiochip_add(&rg->chip);
-+}
-+
-+static const struct of_device_id ralink_gpio_match[] = {
-+ { .compatible = "ralink,rt2880-gpio" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, ralink_gpio_match);
-+
-+static struct platform_driver ralink_gpio_driver = {
-+ .probe = ralink_gpio_probe,
-+ .driver = {
-+ .name = "rt2880_gpio",
-+ .owner = THIS_MODULE,
-+ .of_match_table = ralink_gpio_match,
-+ },
-+};
-+
-+static int __init ralink_gpio_init(void)
-+{
-+ return platform_driver_register(&ralink_gpio_driver);
-+}
-+
-+subsys_initcall(ralink_gpio_init);
+++ /dev/null
-From 4e694014a11a407e309f62c7daade545ba71dcf1 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 13:54:22 +0200
-Subject: [PATCH 09/25] MIPS: ralink: add support for reset-controller API
-
-Add a helper for reseting different devices on the SoC.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/Kconfig | 1 +
- arch/mips/ralink/common.h | 2 ++
- arch/mips/ralink/of.c | 3 +++
- arch/mips/ralink/reset.c | 62 +++++++++++++++++++++++++++++++++++++++++++++
- 4 files changed, 68 insertions(+)
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -374,6 +374,7 @@ config MACH_VR41XX
- select CSRC_R4K
- select SYS_HAS_CPU_VR41XX
- select ARCH_REQUIRE_GPIOLIB
-+ select ARCH_HAS_RESET_CONTROLLER
-
- config NXP_STB220
- bool "NXP STB220 board"
---- a/arch/mips/ralink/common.h
-+++ b/arch/mips/ralink/common.h
-@@ -46,6 +46,8 @@ extern void ralink_of_remap(void);
- extern void ralink_clk_init(void);
- extern void ralink_clk_add(const char *dev, unsigned long rate);
-
-+extern void ralink_rst_init(void);
-+
- extern void prom_soc_init(struct ralink_soc_info *soc_info);
-
- __iomem void *plat_of_remap_node(const char *node);
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -110,6 +110,9 @@ static int __init plat_of_setup(void)
- if (of_platform_populate(NULL, of_ids, NULL, NULL))
- panic("failed to populate DT\n");
-
-+ /* make sure ithat the reset controller is setup early */
-+ ralink_rst_init();
-+
- return 0;
- }
-
---- a/arch/mips/ralink/reset.c
-+++ b/arch/mips/ralink/reset.c
-@@ -10,6 +10,8 @@
-
- #include <linux/pm.h>
- #include <linux/io.h>
-+#include <linux/of.h>
-+#include <linux/reset-controller.h>
-
- #include <asm/reboot.h>
-
-@@ -19,6 +21,66 @@
- #define SYSC_REG_RESET_CTRL 0x034
- #define RSTCTL_RESET_SYSTEM BIT(0)
-
-+static int ralink_assert_device(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ u32 val;
-+
-+ if (id < 8)
-+ return -1;
-+
-+ val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
-+ val |= BIT(id);
-+ rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
-+
-+ return 0;
-+}
-+
-+static int ralink_deassert_device(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ u32 val;
-+
-+ if (id < 8)
-+ return -1;
-+
-+ val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
-+ val &= ~BIT(id);
-+ rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
-+
-+ return 0;
-+}
-+
-+static int ralink_reset_device(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ ralink_assert_device(rcdev, id);
-+ return ralink_deassert_device(rcdev, id);
-+}
-+
-+static struct reset_control_ops reset_ops = {
-+ .reset = ralink_reset_device,
-+ .assert = ralink_assert_device,
-+ .deassert = ralink_deassert_device,
-+};
-+
-+static struct reset_controller_dev reset_dev = {
-+ .ops = &reset_ops,
-+ .owner = THIS_MODULE,
-+ .nr_resets = 32,
-+ .of_reset_n_cells = 1,
-+};
-+
-+void ralink_rst_init(void)
-+{
-+ reset_dev.of_node = of_find_compatible_node(NULL, NULL,
-+ "ralink,rt2880-reset");
-+ if (!reset_dev.of_node)
-+ pr_err("Failed to find reset controller node");
-+ else
-+ reset_controller_register(&reset_dev);
-+}
-+
- static void ralink_restart(char *command)
- {
- local_irq_disable();
+++ /dev/null
-From 1cd8a1dc8e942bd130dc40ff801f37ad296495e3 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 13:41:04 +0200
-Subject: [PATCH 10/25] MIPS: ralink: add support for periodic timer irq
-
-Adds a driver for the periodic timer found on Ralink SoC.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/Makefile | 2 +-
- arch/mips/ralink/timer.c | 185 +++++++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 186 insertions(+), 1 deletion(-)
- create mode 100644 arch/mips/ralink/timer.c
-
---- a/arch/mips/ralink/Makefile
-+++ b/arch/mips/ralink/Makefile
-@@ -6,7 +6,7 @@
- # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
- # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-
--obj-y := prom.o of.o reset.o clk.o irq.o
-+obj-y := prom.o of.o reset.o clk.o irq.o timer.o
-
- obj-$(CONFIG_SOC_RT288X) += rt288x.o
- obj-$(CONFIG_SOC_RT305X) += rt305x.o
---- /dev/null
-+++ b/arch/mips/ralink/timer.c
-@@ -0,0 +1,185 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+*/
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/interrupt.h>
-+#include <linux/timer.h>
-+#include <linux/of_gpio.h>
-+#include <linux/clk.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+
-+#define TIMER_REG_TMRSTAT 0x00
-+#define TIMER_REG_TMR0LOAD 0x10
-+#define TIMER_REG_TMR0CTL 0x18
-+
-+#define TMRSTAT_TMR0INT BIT(0)
-+
-+#define TMR0CTL_ENABLE BIT(7)
-+#define TMR0CTL_MODE_PERIODIC BIT(4)
-+#define TMR0CTL_PRESCALER 1
-+#define TMR0CTL_PRESCALE_VAL (0xf - TMR0CTL_PRESCALER)
-+#define TMR0CTL_PRESCALE_DIV (65536 / BIT(TMR0CTL_PRESCALER))
-+
-+struct rt_timer {
-+ struct device *dev;
-+ void __iomem *membase;
-+ int irq;
-+ unsigned long timer_freq;
-+ unsigned long timer_div;
-+};
-+
-+static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val)
-+{
-+ __raw_writel(val, rt->membase + reg);
-+}
-+
-+static inline u32 rt_timer_r32(struct rt_timer *rt, u8 reg)
-+{
-+ return __raw_readl(rt->membase + reg);
-+}
-+
-+static irqreturn_t rt_timer_irq(int irq, void *_rt)
-+{
-+ struct rt_timer *rt = (struct rt_timer *) _rt;
-+
-+ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
-+ rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+
-+static int rt_timer_request(struct rt_timer *rt)
-+{
-+ int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED,
-+ dev_name(rt->dev), rt);
-+ if (err) {
-+ dev_err(rt->dev, "failed to request irq\n");
-+ } else {
-+ u32 t = TMR0CTL_MODE_PERIODIC | TMR0CTL_PRESCALE_VAL;
-+ rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
-+ }
-+ return err;
-+}
-+
-+static void rt_timer_free(struct rt_timer *rt)
-+{
-+ free_irq(rt->irq, rt);
-+}
-+
-+static int rt_timer_config(struct rt_timer *rt, unsigned long divisor)
-+{
-+ if (rt->timer_freq < divisor)
-+ rt->timer_div = rt->timer_freq;
-+ else
-+ rt->timer_div = divisor;
-+
-+ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
-+
-+ return 0;
-+}
-+
-+static int rt_timer_enable(struct rt_timer *rt)
-+{
-+ u32 t;
-+
-+ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
-+
-+ t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
-+ t |= TMR0CTL_ENABLE;
-+ rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
-+
-+ return 0;
-+}
-+
-+static void rt_timer_disable(struct rt_timer *rt)
-+{
-+ u32 t;
-+
-+ t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
-+ t &= ~TMR0CTL_ENABLE;
-+ rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
-+}
-+
-+static int rt_timer_probe(struct platform_device *pdev)
-+{
-+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ struct rt_timer *rt;
-+ struct clk *clk;
-+
-+ rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL);
-+ if (!rt) {
-+ dev_err(&pdev->dev, "failed to allocate memory\n");
-+ return -ENOMEM;
-+ }
-+
-+ rt->irq = platform_get_irq(pdev, 0);
-+ if (!rt->irq) {
-+ dev_err(&pdev->dev, "failed to load irq\n");
-+ return -ENOENT;
-+ }
-+
-+ rt->membase = devm_request_and_ioremap(&pdev->dev, res);
-+ if (IS_ERR(rt->membase))
-+ return PTR_ERR(rt->membase);
-+
-+ clk = devm_clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(clk)) {
-+ dev_err(&pdev->dev, "failed get clock rate\n");
-+ return PTR_ERR(clk);
-+ }
-+
-+ rt->timer_freq = clk_get_rate(clk) / TMR0CTL_PRESCALE_DIV;
-+ if (!rt->timer_freq)
-+ return -EINVAL;
-+
-+ rt->dev = &pdev->dev;
-+ platform_set_drvdata(pdev, rt);
-+
-+ rt_timer_request(rt);
-+ rt_timer_config(rt, 2);
-+ rt_timer_enable(rt);
-+
-+ dev_info(&pdev->dev, "maximum frequncy is %luHz\n", rt->timer_freq);
-+
-+ return 0;
-+}
-+
-+static int rt_timer_remove(struct platform_device *pdev)
-+{
-+ struct rt_timer *rt = platform_get_drvdata(pdev);
-+
-+ rt_timer_disable(rt);
-+ rt_timer_free(rt);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id rt_timer_match[] = {
-+ { .compatible = "ralink,rt2880-timer" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, rt_timer_match);
-+
-+static struct platform_driver rt_timer_driver = {
-+ .probe = rt_timer_probe,
-+ .remove = rt_timer_remove,
-+ .driver = {
-+ .name = "rt-timer",
-+ .owner = THIS_MODULE,
-+ .of_match_table = rt_timer_match
-+ },
-+};
-+
-+module_platform_driver(rt_timer_driver);
-+
-+MODULE_DESCRIPTION("Ralink RT2880 timer");
-+MODULE_AUTHOR("John Crispin <blogic@openwrt.org");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From 3b511d972b556712f89ccc68825c0ec8f398dc5c Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 13:46:09 +0200
-Subject: [PATCH 11/25] MIPS: ralink: add support for systick timer found on
- newer ralink SoC
-
-Newer Ralink SoC (MT7620x and RT5350) have a 50KHz clock that runs independent
-of the SoC master clock. If we want to automatic frequency scaling to work we
-need to use the systick timer as the clock source.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/Kconfig | 7 ++
- arch/mips/ralink/Makefile | 2 +
- arch/mips/ralink/cevt-rt3352.c | 145 ++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 154 insertions(+)
- create mode 100644 arch/mips/ralink/cevt-rt3352.c
-
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -1,5 +1,12 @@
- if RALINK
-
-+config CLKEVT_RT3352
-+ bool "Systick Clockevent source"
-+ depends on SOC_RT305X || SOC_MT7620
-+ default y
-+ select CLKSRC_OF
-+ select CLKSRC_MMIO
-+
- choice
- prompt "Ralink SoC selection"
- default SOC_RT305X
---- a/arch/mips/ralink/Makefile
-+++ b/arch/mips/ralink/Makefile
-@@ -8,6 +8,8 @@
-
- obj-y := prom.o of.o reset.o clk.o irq.o timer.o
-
-+obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
-+
- obj-$(CONFIG_SOC_RT288X) += rt288x.o
- obj-$(CONFIG_SOC_RT305X) += rt305x.o
- obj-$(CONFIG_SOC_RT3883) += rt3883.o
---- /dev/null
-+++ b/arch/mips/ralink/cevt-rt3352.c
-@@ -0,0 +1,145 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2013 by John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/clockchips.h>
-+#include <linux/clocksource.h>
-+#include <linux/interrupt.h>
-+#include <linux/reset.h>
-+#include <linux/init.h>
-+#include <linux/time.h>
-+#include <linux/of.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_address.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+
-+#define SYSTICK_FREQ (50 * 1000)
-+
-+#define SYSTICK_CONFIG 0x00
-+#define SYSTICK_COMPARE 0x04
-+#define SYSTICK_COUNT 0x08
-+
-+/* route systick irq to mips irq 7 instead of the r4k-timer */
-+#define CFG_EXT_STK_EN 0x2
-+/* enable the counter */
-+#define CFG_CNT_EN 0x1
-+
-+struct systick_device {
-+ void __iomem *membase;
-+ struct clock_event_device dev;
-+ int irq_requested;
-+ int freq_scale;
-+};
-+
-+static void systick_set_clock_mode(enum clock_event_mode mode,
-+ struct clock_event_device *evt);
-+
-+static int systick_next_event(unsigned long delta,
-+ struct clock_event_device *evt)
-+{
-+ struct systick_device *sdev;
-+ u32 count;
-+
-+ sdev = container_of(evt, struct systick_device, dev);
-+ count = ioread32(sdev->membase + SYSTICK_COUNT);
-+ count = (count + delta) % SYSTICK_FREQ;
-+ iowrite32(count + delta, sdev->membase + SYSTICK_COMPARE);
-+
-+ return 0;
-+}
-+
-+static void systick_event_handler(struct clock_event_device *dev)
-+{
-+ /* noting to do here */
-+}
-+
-+static irqreturn_t systick_interrupt(int irq, void *dev_id)
-+{
-+ struct clock_event_device *dev = (struct clock_event_device *) dev_id;
-+
-+ dev->event_handler(dev);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static struct systick_device systick = {
-+ .dev = {
-+ /*
-+ * cevt-r4k uses 300, make sure systick
-+ * gets used if available
-+ */
-+ .rating = 310,
-+ .features = CLOCK_EVT_FEAT_ONESHOT,
-+ .set_next_event = systick_next_event,
-+ .set_mode = systick_set_clock_mode,
-+ .event_handler = systick_event_handler,
-+ },
-+};
-+
-+static struct irqaction systick_irqaction = {
-+ .handler = systick_interrupt,
-+ .flags = IRQF_PERCPU | IRQF_TIMER,
-+ .dev_id = &systick.dev,
-+};
-+
-+static void systick_set_clock_mode(enum clock_event_mode mode,
-+ struct clock_event_device *evt)
-+{
-+ struct systick_device *sdev;
-+
-+ sdev = container_of(evt, struct systick_device, dev);
-+
-+ switch (mode) {
-+ case CLOCK_EVT_MODE_ONESHOT:
-+ if (!sdev->irq_requested)
-+ setup_irq(systick.dev.irq, &systick_irqaction);
-+ sdev->irq_requested = 1;
-+ iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN,
-+ systick.membase + SYSTICK_CONFIG);
-+ break;
-+
-+ case CLOCK_EVT_MODE_SHUTDOWN:
-+ if (sdev->irq_requested)
-+ free_irq(systick.dev.irq, &systick_irqaction);
-+ sdev->irq_requested = 0;
-+ iowrite32(0, systick.membase + SYSTICK_CONFIG);
-+ break;
-+
-+ default:
-+ pr_err("%s: Unhandeled mips clock_mode\n", systick.dev.name);
-+ break;
-+ }
-+}
-+
-+static void __init ralink_systick_init(struct device_node *np)
-+{
-+ systick.membase = of_iomap(np, 0);
-+ if (!systick.membase)
-+ return;
-+
-+ systick_irqaction.name = np->name;
-+ systick.dev.name = np->name;
-+ clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
-+ systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);
-+ systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);
-+ systick.dev.irq = irq_of_parse_and_map(np, 0);
-+ if (!systick.dev.irq) {
-+ pr_err("%s: request_irq failed", np->name);
-+ return;
-+ }
-+
-+ clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
-+ SYSTICK_FREQ, 301, 16, clocksource_mmio_readl_up);
-+
-+ clockevents_register_device(&systick.dev);
-+
-+ pr_info("%s: runing - mult: %d, shift: %d\n",
-+ np->name, systick.dev.mult, systick.dev.shift);
-+}
-+
-+CLOCKSOURCE_OF_DECLARE(systick, "ralink,cevt-systick", ralink_systick_init);
+++ /dev/null
-From c4d6a957efb0c8d919302598ae547bde05137461 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 13:48:39 +0200
-Subject: [PATCH 12/25] MIPS: ralink: probe clocksources from OF
-
-Make plat_time_init() call clocksource_of_init() allowing the systick cevt
-to load.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/clk.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/mips/ralink/clk.c
-+++ b/arch/mips/ralink/clk.c
-@@ -69,4 +69,5 @@ void __init plat_time_init(void)
- pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
- mips_hpt_frequency = clk_get_rate(clk) / 2;
- clk_put(clk);
-+ clocksource_of_init();
- }
+++ /dev/null
-From 2d17c793a9cd3f67351d1a15c099ef2464e81f47 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 20 May 2013 20:30:11 +0200
-Subject: [PATCH 13/25] MIPS: ralink: mt7620: add verbose ram info
-
-Make the code print which of SDRAM, DDR1 or DDR2 was detected.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -214,16 +214,19 @@ void prom_soc_init(struct ralink_soc_inf
-
- switch (dram_type) {
- case SYSCFG0_DRAM_TYPE_SDRAM:
-+ pr_info("Board has SDRAM\n");
- soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
- soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
- break;
-
- case SYSCFG0_DRAM_TYPE_DDR1:
-+ pr_info("Board has DDR1\n");
- soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
- soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
- break;
-
- case SYSCFG0_DRAM_TYPE_DDR2:
-+ pr_info("Board has DDR2\n");
- soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
- soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
- break;
+++ /dev/null
-From d0da9f08ef37e9f639e3b7995d722684da2410a2 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 23 May 2013 18:46:25 +0200
-Subject: [PATCH 14/25] MIPS: ralink: mt7620: add spi clock definition
-
-The definition of the spi clock is missing.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -167,6 +167,7 @@ void __init ralink_clk_init(void)
- ralink_clk_add("cpu", cpu_rate);
- ralink_clk_add("10000100.timer", 40000000);
- ralink_clk_add("10000500.uart", 40000000);
-+ ralink_clk_add("10000b00.spi", 40000000);
- ralink_clk_add("10000c00.uartlite", 40000000);
- }
-
+++ /dev/null
-From 51db62f58431d9a89c55f59f98879829dcfddcaf Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 13:50:11 +0200
-Subject: [PATCH 15/25] MIPS: ralink: mt7620: add wdt clock definition
-
-The definition of the wdt clock is missing.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -166,6 +166,7 @@ void __init ralink_clk_init(void)
-
- ralink_clk_add("cpu", cpu_rate);
- ralink_clk_add("10000100.timer", 40000000);
-+ ralink_clk_add("10000120.watchdog", 40000000);
- ralink_clk_add("10000500.uart", 40000000);
- ralink_clk_add("10000b00.spi", 40000000);
- ralink_clk_add("10000c00.uartlite", 40000000);
+++ /dev/null
-From 011f4bdba0dd4d1dff6d33b1a65541fc4f09c78e Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 24 May 2013 21:28:08 +0200
-Subject: [PATCH 16/25] MIPS: ralink: mt7620: fix usb issue during frequency
- scaling
-
-If the USB HCD is running and the cpu is scaled too low, then the USB stops
-working. Increase the idle speed of the core to fix this if the kernel is
-built with USB support.
-
-The values are taken from the Ralink SDK Kernel.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/mach-ralink/mt7620.h | 1 +
- arch/mips/ralink/mt7620.c | 19 +++++++++++++++++++
- 2 files changed, 20 insertions(+)
-
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -20,6 +20,7 @@
- #define SYSC_REG_CHIP_REV 0x0c
- #define SYSC_REG_SYSTEM_CONFIG0 0x10
- #define SYSC_REG_SYSTEM_CONFIG1 0x14
-+#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
- #define SYSC_REG_CPLL_CONFIG0 0x54
- #define SYSC_REG_CPLL_CONFIG1 0x58
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -20,6 +20,12 @@
-
- #include "common.h"
-
-+/* clock scaling */
-+#define CLKCFG_FDIV_MASK 0x1f00
-+#define CLKCFG_FDIV_USB_VAL 0x0300
-+#define CLKCFG_FFRAC_MASK 0x001f
-+#define CLKCFG_FFRAC_USB_VAL 0x0003
-+
- /* does the board have sdram or ddram */
- static int dram_type;
-
-@@ -170,6 +176,19 @@ void __init ralink_clk_init(void)
- ralink_clk_add("10000500.uart", 40000000);
- ralink_clk_add("10000b00.spi", 40000000);
- ralink_clk_add("10000c00.uartlite", 40000000);
-+
-+ if (IS_ENABLED(CONFIG_USB)) {
-+ /*
-+ * When the CPU goes into sleep mode, the BUS clock will be too low for
-+ * USB to function properly
-+ */
-+ u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
-+
-+ val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
-+ val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
-+
-+ rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
-+ }
- }
-
- void __init ralink_of_remap(void)
+++ /dev/null
-From c16c0b66594cb0be44e150dbe3fda747817b873d Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 17:50:53 +0200
-Subject: [PATCH 17/25] MIPS: ralink: mt7620: this SoC has ehci and ohci hosts
-
-Select the the EHCI and OHCI symbols.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/Kconfig | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -29,6 +29,8 @@ choice
-
- config SOC_MT7620
- bool "MT7620"
-+ select USB_ARCH_HAS_OHCI
-+ select USB_ARCH_HAS_EHCI
-
- endchoice
-
+++ /dev/null
-From c464a54f9a4a959d09206583b11ae99740e0f267 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 9 Aug 2013 20:12:59 +0200
-Subject: [PATCH 18/25] DT: Add documentation for spi-rt2880
-
-Describe the SPI master found on the MIPS based Ralink RT2880 SoC.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- .../devicetree/bindings/spi/spi-rt2880.txt | 28 ++++++++++++++++++++
- 1 file changed, 28 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/spi/spi-rt2880.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/spi/spi-rt2880.txt
-@@ -0,0 +1,28 @@
-+Ralink SoC RT2880 SPI master controller.
-+
-+This SPI controller is found on most wireless SoCs made by ralink.
-+
-+Required properties:
-+- compatible : "ralink,rt2880-spi"
-+- reg : The register base for the controller.
-+- #address-cells : <1>, as required by generic SPI binding.
-+- #size-cells : <0>, also as required by generic SPI binding.
-+
-+Child nodes as per the generic SPI binding.
-+
-+Example:
-+
-+ spi@b00 {
-+ compatible = "ralink,rt2880-spi";
-+ reg = <0xb00 0x100>;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ m25p80@0 {
-+ compatible = "m25p80";
-+ reg = <0>;
-+ spi-max-frequency = <10000000>;
-+ };
-+ };
-+
+++ /dev/null
-From 43c36279a0e822de608c1e825826bbac3238d8a2 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 22 Apr 2013 23:16:18 +0200
-Subject: [PATCH 19/25] SPI: ralink: add Ralink SoC spi driver
-
-Add the driver needed to make SPI work on Ralink SoC.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: John Crispin <blogic@openwrt.org>
----
- drivers/spi/Kconfig | 6 +
- drivers/spi/Makefile | 1 +
- drivers/spi/spi-rt2880.c | 450 ++++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 457 insertions(+)
- create mode 100644 drivers/spi/spi-rt2880.c
-
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -354,6 +354,12 @@ config SPI_RSPI
- help
- SPI driver for Renesas RSPI blocks.
-
-+config SPI_RT2880
-+ tristate "Ralink RT288x SPI Controller"
-+ depends on RALINK
-+ help
-+ This selects a driver for the Ralink RT288x/RT305x SPI Controller.
-+
- config SPI_S3C24XX
- tristate "Samsung S3C24XX series SPI"
- depends on ARCH_S3C24XX
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -56,6 +56,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_
- obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
- obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
- obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
-+obj-$(CONFIG_SPI_RT2880) += spi-rt2880.o
- obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
- spi-s3c24xx-hw-y := spi-s3c24xx.o
- spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
---- /dev/null
-+++ b/drivers/spi/spi-rt2880.c
-@@ -0,0 +1,432 @@
-+/*
-+ * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
-+ *
-+ * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
-+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
-+ *
-+ * Some parts are based on spi-orion.c:
-+ * Author: Shadi Ammouri <shadi@marvell.com>
-+ * Copyright (C) 2007-2008 Marvell Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/delay.h>
-+#include <linux/io.h>
-+#include <linux/reset.h>
-+#include <linux/spi/spi.h>
-+#include <linux/platform_device.h>
-+
-+#define DRIVER_NAME "spi-rt2880"
-+/* only one slave is supported*/
-+#define RALINK_NUM_CHIPSELECTS 1
-+/* in usec */
-+#define RALINK_SPI_WAIT_MAX_LOOP 2000
-+
-+#define RAMIPS_SPI_STAT 0x00
-+#define RAMIPS_SPI_CFG 0x10
-+#define RAMIPS_SPI_CTL 0x14
-+#define RAMIPS_SPI_DATA 0x20
-+#define RAMIPS_SPI_FIFO_STAT 0x38
-+
-+/* SPISTAT register bit field */
-+#define SPISTAT_BUSY BIT(0)
-+
-+/* SPICFG register bit field */
-+#define SPICFG_LSBFIRST 0
-+#define SPICFG_MSBFIRST BIT(8)
-+#define SPICFG_SPICLKPOL BIT(6)
-+#define SPICFG_RXCLKEDGE_FALLING BIT(5)
-+#define SPICFG_TXCLKEDGE_FALLING BIT(4)
-+#define SPICFG_SPICLK_PRESCALE_MASK 0x7
-+#define SPICFG_SPICLK_DIV2 0
-+#define SPICFG_SPICLK_DIV4 1
-+#define SPICFG_SPICLK_DIV8 2
-+#define SPICFG_SPICLK_DIV16 3
-+#define SPICFG_SPICLK_DIV32 4
-+#define SPICFG_SPICLK_DIV64 5
-+#define SPICFG_SPICLK_DIV128 6
-+#define SPICFG_SPICLK_DISABLE 7
-+
-+/* SPICTL register bit field */
-+#define SPICTL_HIZSDO BIT(3)
-+#define SPICTL_STARTWR BIT(2)
-+#define SPICTL_STARTRD BIT(1)
-+#define SPICTL_SPIENA BIT(0)
-+
-+/* SPIFIFOSTAT register bit field */
-+#define SPIFIFOSTAT_TXFULL BIT(17)
-+
-+struct rt2880_spi {
-+ struct spi_master *master;
-+ void __iomem *base;
-+ unsigned int sys_freq;
-+ unsigned int speed;
-+ struct clk *clk;
-+ spinlock_t lock;
-+};
-+
-+static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
-+{
-+ return spi_master_get_devdata(spi->master);
-+}
-+
-+static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
-+{
-+ return ioread32(rs->base + reg);
-+}
-+
-+static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg, u32 val)
-+{
-+ iowrite32(val, rs->base + reg);
-+}
-+
-+static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
-+{
-+ void __iomem *addr = rs->base + reg;
-+ unsigned long flags;
-+ u32 val;
-+
-+ spin_lock_irqsave(&rs->lock, flags);
-+ val = ioread32(addr);
-+ val |= mask;
-+ iowrite32(val, addr);
-+ spin_unlock_irqrestore(&rs->lock, flags);
-+}
-+
-+static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
-+{
-+ void __iomem *addr = rs->base + reg;
-+ unsigned long flags;
-+ u32 val;
-+
-+ spin_lock_irqsave(&rs->lock, flags);
-+ val = ioread32(addr);
-+ val &= ~mask;
-+ iowrite32(val, addr);
-+ spin_unlock_irqrestore(&rs->lock, flags);
-+}
-+
-+static int rt2880_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
-+{
-+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
-+ u32 rate;
-+ u32 prescale;
-+ u32 reg;
-+
-+ dev_dbg(&spi->dev, "speed:%u\n", speed);
-+
-+ /*
-+ * the supported rates are: 2, 4, 8, ... 128
-+ * round up as we look for equal or less speed
-+ */
-+ rate = DIV_ROUND_UP(rs->sys_freq, speed);
-+ dev_dbg(&spi->dev, "rate-1:%u\n", rate);
-+ rate = roundup_pow_of_two(rate);
-+ dev_dbg(&spi->dev, "rate-2:%u\n", rate);
-+
-+ /* check if requested speed is too small */
-+ if (rate > 128)
-+ return -EINVAL;
-+
-+ if (rate < 2)
-+ rate = 2;
-+
-+ /* Convert the rate to SPI clock divisor value. */
-+ prescale = ilog2(rate / 2);
-+ dev_dbg(&spi->dev, "prescale:%u\n", prescale);
-+
-+ reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
-+ reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
-+ rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
-+ rs->speed = speed;
-+ return 0;
-+}
-+
-+/*
-+ * called only when no transfer is active on the bus
-+ */
-+static int
-+rt2880_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
-+{
-+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
-+ unsigned int speed = spi->max_speed_hz;
-+ int rc;
-+
-+ if ((t != NULL) && t->speed_hz)
-+ speed = t->speed_hz;
-+
-+ if (rs->speed != speed) {
-+ dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
-+ rc = rt2880_spi_baudrate_set(spi, speed);
-+ if (rc)
-+ return rc;
-+ }
-+
-+ return 0;
-+}
-+
-+static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable)
-+{
-+ if (enable)
-+ rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
-+ else
-+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
-+}
-+
-+static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
-+{
-+ int i;
-+
-+ for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
-+ u32 status;
-+
-+ status = rt2880_spi_read(rs, RAMIPS_SPI_STAT);
-+ if ((status & SPISTAT_BUSY) == 0)
-+ return 0;
-+
-+ cpu_relax();
-+ udelay(1);
-+ }
-+
-+ return -ETIMEDOUT;
-+}
-+
-+static unsigned int
-+rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
-+{
-+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
-+ unsigned count = 0;
-+ u8 *rx = xfer->rx_buf;
-+ const u8 *tx = xfer->tx_buf;
-+ int err;
-+
-+ dev_dbg(&spi->dev, "read (%d): %s %s\n", xfer->len,
-+ (tx != NULL) ? "tx" : " ",
-+ (rx != NULL) ? "rx" : " ");
-+
-+ if (tx) {
-+ for (count = 0; count < xfer->len; count++) {
-+ rt2880_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
-+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
-+ err = rt2880_spi_wait_till_ready(rs);
-+ if (err) {
-+ dev_err(&spi->dev, "TX failed, err=%d\n", err);
-+ goto out;
-+ }
-+ }
-+ }
-+
-+ if (rx) {
-+ for (count = 0; count < xfer->len; count++) {
-+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
-+ err = rt2880_spi_wait_till_ready(rs);
-+ if (err) {
-+ dev_err(&spi->dev, "RX failed, err=%d\n", err);
-+ goto out;
-+ }
-+ rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
-+ }
-+ }
-+
-+out:
-+ return count;
-+}
-+
-+static int rt2880_spi_transfer_one_message(struct spi_master *master,
-+ struct spi_message *m)
-+{
-+ struct rt2880_spi *rs = spi_master_get_devdata(master);
-+ struct spi_device *spi = m->spi;
-+ struct spi_transfer *t = NULL;
-+ int par_override = 0;
-+ int status = 0;
-+ int cs_active = 0;
-+
-+ /* Load defaults */
-+ status = rt2880_spi_setup_transfer(spi, NULL);
-+ if (status < 0)
-+ goto msg_done;
-+
-+ list_for_each_entry(t, &m->transfers, transfer_list) {
-+ if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
-+ dev_err(&spi->dev,
-+ "message rejected: invalid transfer data buffers\n");
-+ status = -EIO;
-+ goto msg_done;
-+ }
-+
-+ if (t->speed_hz && t->speed_hz < (rs->sys_freq / 128)) {
-+ dev_err(&spi->dev,
-+ "message rejected: device min speed (%d Hz) exceeds required transfer speed (%d Hz)\n",
-+ (rs->sys_freq / 128), t->speed_hz);
-+ status = -EIO;
-+ goto msg_done;
-+ }
-+
-+ if (par_override || t->speed_hz || t->bits_per_word) {
-+ par_override = 1;
-+ status = rt2880_spi_setup_transfer(spi, t);
-+ if (status < 0)
-+ goto msg_done;
-+ if (!t->speed_hz && !t->bits_per_word)
-+ par_override = 0;
-+ }
-+
-+ if (!cs_active) {
-+ rt2880_spi_set_cs(rs, 1);
-+ cs_active = 1;
-+ }
-+
-+ if (t->len)
-+ m->actual_length += rt2880_spi_write_read(spi, t);
-+
-+ if (t->delay_usecs)
-+ udelay(t->delay_usecs);
-+
-+ if (t->cs_change) {
-+ rt2880_spi_set_cs(rs, 0);
-+ cs_active = 0;
-+ }
-+ }
-+
-+msg_done:
-+ if (cs_active)
-+ rt2880_spi_set_cs(rs, 0);
-+
-+ m->status = status;
-+ spi_finalize_current_message(master);
-+
-+ return 0;
-+}
-+
-+static int rt2880_spi_setup(struct spi_device *spi)
-+{
-+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
-+
-+ if ((spi->max_speed_hz == 0) ||
-+ (spi->max_speed_hz > (rs->sys_freq / 2)))
-+ spi->max_speed_hz = (rs->sys_freq / 2);
-+
-+ if (spi->max_speed_hz < (rs->sys_freq / 128)) {
-+ dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
-+ spi->max_speed_hz);
-+ return -EINVAL;
-+ }
-+
-+ /*
-+ * baudrate & width will be set rt2880_spi_setup_transfer
-+ */
-+ return 0;
-+}
-+
-+static void rt2880_spi_reset(struct rt2880_spi *rs)
-+{
-+ rt2880_spi_write(rs, RAMIPS_SPI_CFG,
-+ SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
-+ SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
-+ rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
-+}
-+
-+static int rt2880_spi_probe(struct platform_device *pdev)
-+{
-+ struct spi_master *master;
-+ struct rt2880_spi *rs;
-+ unsigned long flags;
-+ void __iomem *base;
-+ struct resource *r;
-+ int status = 0;
-+ struct clk *clk;
-+
-+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ base = devm_ioremap_resource(&pdev->dev, r);
-+ if (IS_ERR(base))
-+ return PTR_ERR(base);
-+
-+ clk = devm_clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(clk)) {
-+ dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
-+ status);
-+ return PTR_ERR(clk);
-+ }
-+
-+ status = clk_prepare_enable(clk);
-+ if (status)
-+ return status;
-+
-+ master = spi_alloc_master(&pdev->dev, sizeof(*rs));
-+ if (master == NULL) {
-+ dev_dbg(&pdev->dev, "master allocation failed\n");
-+ return -ENOMEM;
-+ }
-+
-+ /* we support only mode 0, and no options */
-+ master->mode_bits = 0;
-+
-+ master->setup = rt2880_spi_setup;
-+ master->transfer_one_message = rt2880_spi_transfer_one_message;
-+ master->num_chipselect = RALINK_NUM_CHIPSELECTS;
-+ master->bits_per_word_mask = SPI_BPW_MASK(8);
-+ master->dev.of_node = pdev->dev.of_node;
-+
-+ dev_set_drvdata(&pdev->dev, master);
-+
-+ rs = spi_master_get_devdata(master);
-+ rs->base = base;
-+ rs->clk = clk;
-+ rs->master = master;
-+ rs->sys_freq = clk_get_rate(rs->clk);
-+ dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
-+ spin_lock_irqsave(&rs->lock, flags);
-+
-+ device_reset(&pdev->dev);
-+
-+ rt2880_spi_reset(rs);
-+
-+ return spi_register_master(master);
-+}
-+
-+static int rt2880_spi_remove(struct platform_device *pdev)
-+{
-+ struct spi_master *master;
-+ struct rt2880_spi *rs;
-+
-+ master = dev_get_drvdata(&pdev->dev);
-+ rs = spi_master_get_devdata(master);
-+
-+ clk_disable(rs->clk);
-+ spi_unregister_master(master);
-+
-+ return 0;
-+}
-+
-+MODULE_ALIAS("platform:" DRIVER_NAME);
-+
-+static const struct of_device_id rt2880_spi_match[] = {
-+ { .compatible = "ralink,rt2880-spi" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, rt2880_spi_match);
-+
-+static struct platform_driver rt2880_spi_driver = {
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ .of_match_table = rt2880_spi_match,
-+ },
-+ .probe = rt2880_spi_probe,
-+ .remove = rt2880_spi_remove,
-+};
-+
-+module_platform_driver(rt2880_spi_driver);
-+
-+MODULE_DESCRIPTION("Ralink SPI driver");
-+MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
-+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From 5845a3aa53cf42893db05662aa9bb91387949ff6 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 12 Aug 2013 18:11:33 +0200
-Subject: [PATCH 22/25] MIPS: ralink: update dts files
-
-Add the devicetree nodes needed to make the newly merged drivers work.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/dts/mt7620a.dtsi | 135 +++++++++++++++++++++++
- arch/mips/ralink/dts/rt3050.dtsi | 156 ++++++++++++++++++++++++++
- arch/mips/ralink/dts/rt3883.dtsi | 219 +++++++++++++++++++++++++++++++++++++
- 3 files changed, 510 insertions(+)
-
---- a/arch/mips/ralink/dts/mt7620a.dtsi
-+++ b/arch/mips/ralink/dts/mt7620a.dtsi
-@@ -29,10 +29,32 @@
- reg = <0x0 0x100>;
- };
-
-+ timer@100 {
-+ compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
-+ reg = <0x100 0x20>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <1>;
-+ };
-+
-+ watchdog@120 {
-+ compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
-+ reg = <0x120 0x10>;
-+
-+ resets = <&rstctrl 8>;
-+ reset-names = "wdt";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <1>;
-+ };
-+
- intc: intc@200 {
- compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
- reg = <0x200 0x100>;
-
-+ resets = <&rstctrl 19>;
-+ reset-names = "intc";
-+
- interrupt-controller;
- #interrupt-cells = <1>;
-
-@@ -43,16 +65,129 @@
- memc@300 {
- compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
- reg = <0x300 0x100>;
-+
-+ resets = <&rstctrl 20>;
-+ reset-names = "mc";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <3>;
-+ };
-+
-+ uart@500 {
-+ compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
-+ reg = <0x500 0x100>;
-+
-+ resets = <&rstctrl 12>;
-+ reset-names = "uart";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <5>;
-+
-+ reg-shift = <2>;
-+
-+ status = "disabled";
-+ };
-+
-+ gpio0: gpio@600 {
-+ compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
-+ reg = <0x600 0x34>;
-+
-+ resets = <&rstctrl 13>;
-+ reset-names = "pio";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <6>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <0>;
-+ ralink,num-gpios = <24>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 20 24 28 2c
-+ 30 34 ];
-+
-+ status = "disabled";
-+ };
-+
-+ gpio1: gpio@638 {
-+ compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
-+ reg = <0x638 0x24>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <6>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <24>;
-+ ralink,num-gpios = <16>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 10 14 18 1c
-+ 20 24 ];
-+
-+ status = "disabled";
-+ };
-+
-+ gpio2: gpio@660 {
-+ compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
-+ reg = <0x660 0x24>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <6>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <40>;
-+ ralink,num-gpios = <32>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 10 14 18 1c
-+ 20 24 ];
-+
-+ status = "disabled";
-+ };
-+
-+ spi@b00 {
-+ compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
-+ reg = <0xb00 0x100>;
-+
-+ resets = <&rstctrl 18>;
-+ reset-names = "spi";
-+
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ status = "disabled";
- };
-
- uartlite@c00 {
- compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
- reg = <0xc00 0x100>;
-
-+ resets = <&rstctrl 19>;
-+ reset-names = "uartl";
-+
- interrupt-parent = <&intc>;
- interrupts = <12>;
-
- reg-shift = <2>;
- };
-+
-+ systick@d00 {
-+ compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
-+ reg = <0xd00 0x10>;
-+
-+ resets = <&rstctrl 28>;
-+ reset-names = "intc";
-+
-+ interrupt-parent = <&cpuintc>;
-+ interrupts = <7>;
-+ };
-+ };
-+
-+ rstctrl: rstctrl {
-+ compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
-+ #reset-cells = <1>;
- };
- };
---- a/arch/mips/ralink/dts/rt3050.dtsi
-+++ b/arch/mips/ralink/dts/rt3050.dtsi
-@@ -9,6 +9,10 @@
- };
- };
-
-+ chosen {
-+ bootargs = "console=ttyS0,57600";
-+ };
-+
- cpuintc: cpuintc@0 {
- #address-cells = <0>;
- #interrupt-cells = <1>;
-@@ -29,10 +33,32 @@
- reg = <0x0 0x100>;
- };
-
-+ timer@100 {
-+ compatible = "ralink,rt3052-timer", "ralink,rt2880-timer";
-+ reg = <0x100 0x20>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <1>;
-+ };
-+
-+ watchdog@120 {
-+ compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
-+ reg = <0x120 0x10>;
-+
-+ resets = <&rstctrl 8>;
-+ reset-names = "wdt";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <1>;
-+ };
-+
- intc: intc@200 {
- compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
- reg = <0x200 0x100>;
-
-+ resets = <&rstctrl 19>;
-+ reset-names = "intc";
-+
- interrupt-controller;
- #interrupt-cells = <1>;
-
-@@ -43,17 +69,144 @@
- memc@300 {
- compatible = "ralink,rt3052-memc", "ralink,rt3050-memc";
- reg = <0x300 0x100>;
-+
-+ resets = <&rstctrl 20>;
-+ reset-names = "mc";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <3>;
-+ };
-+
-+ uart@500 {
-+ compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
-+ reg = <0x500 0x100>;
-+
-+ resets = <&rstctrl 12>;
-+ reset-names = "uart";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <5>;
-+
-+ reg-shift = <2>;
-+
-+ status = "disabled";
-+ };
-+
-+ gpio0: gpio@600 {
-+ compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
-+ reg = <0x600 0x34>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <0>;
-+ ralink,num-gpios = <24>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 20 24 28 2c
-+ 30 34 ];
-+
-+ resets = <&rstctrl 13>;
-+ reset-names = "pio";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <6>;
-+
-+ status = "disabled";
-+ };
-+
-+ gpio1: gpio@638 {
-+ compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
-+ reg = <0x638 0x24>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <24>;
-+ ralink,num-gpios = <16>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 10 14 18 1c
-+ 20 24 ];
-+
-+ status = "disabled";
-+ };
-+
-+ gpio2: gpio@660 {
-+ compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
-+ reg = <0x660 0x24>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <40>;
-+ ralink,num-gpios = <12>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 10 14 18 1c
-+ 20 24 ];
-+
-+ status = "disabled";
-+ };
-+
-+ spi@b00 {
-+ compatible = "ralink,rt3050-spi", "ralink,rt2880-spi";
-+ reg = <0xb00 0x100>;
-+
-+ resets = <&rstctrl 18>;
-+ reset-names = "spi";
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ status = "disabled";
- };
-
- uartlite@c00 {
- compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
- reg = <0xc00 0x100>;
-
-+ resets = <&rstctrl 19>;
-+ reset-names = "uartl";
-+
- interrupt-parent = <&intc>;
- interrupts = <12>;
-
- reg-shift = <2>;
- };
-+
-+ };
-+
-+ rstctrl: rstctrl {
-+ compatible = "ralink,rt3050-reset", "ralink,rt2880-reset";
-+ #reset-cells = <1>;
-+ };
-+
-+ ethernet@10100000 {
-+ compatible = "ralink,rt3050-eth";
-+ reg = <0x10100000 10000>;
-+
-+ interrupt-parent = <&cpuintc>;
-+ interrupts = <5>;
-+
-+ status = "disabled";
-+ };
-+
-+ esw@10110000 {
-+ compatible = "ralink,rt3050-esw";
-+ reg = <0x10110000 8000>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <17>;
-+
-+ status = "disabled";
-+ };
-+
-+ wmac@10180000 {
-+ compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac";
-+ reg = <0x10180000 40000>;
-+
-+ interrupt-parent = <&cpuintc>;
-+ interrupts = <6>;
-+
-+ status = "disabled";
- };
-
- usb@101c0000 {
-@@ -63,6 +216,9 @@
- interrupt-parent = <&intc>;
- interrupts = <18>;
-
-+ resets = <&rstctrl 22>;
-+ reset-names = "otg";
-+
- status = "disabled";
- };
- };
---- a/arch/mips/ralink/dts/rt3883.dtsi
-+++ b/arch/mips/ralink/dts/rt3883.dtsi
-@@ -29,10 +29,32 @@
- reg = <0x0 0x100>;
- };
-
-+ timer@100 {
-+ compatible = "ralink,rt3883-timer", "ralink,rt2880-timer";
-+ reg = <0x100 0x20>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <1>;
-+ };
-+
-+ watchdog@120 {
-+ compatible = "ralink,rt3883-wdt", "ralink,rt2880-wdt";
-+ reg = <0x120 0x10>;
-+
-+ resets = <&rstctrl 8>;
-+ reset-names = "wdt";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <1>;
-+ };
-+
- intc: intc@200 {
- compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
- reg = <0x200 0x100>;
-
-+ resets = <&rstctrl 19>;
-+ reset-names = "intc";
-+
- interrupt-controller;
- #interrupt-cells = <1>;
-
-@@ -43,16 +65,213 @@
- memc@300 {
- compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
- reg = <0x300 0x100>;
-+
-+ resets = <&rstctrl 20>;
-+ reset-names = "mc";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <3>;
-+ };
-+
-+ uart@500 {
-+ compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
-+ reg = <0x500 0x100>;
-+
-+ resets = <&rstctrl 12>;
-+ reset-names = "uart";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <5>;
-+
-+ reg-shift = <2>;
-+
-+ status = "disabled";
-+ };
-+
-+ gpio0: gpio@600 {
-+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
-+ reg = <0x600 0x34>;
-+
-+ resets = <&rstctrl 13>;
-+ reset-names = "pio";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <6>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <0>;
-+ ralink,num-gpios = <24>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 20 24 28 2c
-+ 30 34 ];
-+
-+ status = "disabled";
-+ };
-+
-+ gpio1: gpio@638 {
-+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
-+ reg = <0x638 0x24>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <24>;
-+ ralink,num-gpios = <16>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 10 14 18 1c
-+ 20 24 ];
-+
-+ status = "disabled";
-+ };
-+
-+ gpio2: gpio@660 {
-+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
-+ reg = <0x660 0x24>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <40>;
-+ ralink,num-gpios = <32>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 10 14 18 1c
-+ 20 24 ];
-+
-+ status = "disabled";
-+ };
-+
-+ gpio3: gpio@688 {
-+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
-+ reg = <0x688 0x24>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <72>;
-+ ralink,num-gpios = <24>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 10 14 18 1c
-+ 20 24 ];
-+
-+ status = "disabled";
-+ };
-+
-+ spi0: spi@b00 {
-+ compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
-+ reg = <0xb00 0x100>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ resets = <&rstctrl 18>;
-+ reset-names = "spi";
-+
-+ status = "disabled";
- };
-
- uartlite@c00 {
- compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
- reg = <0xc00 0x100>;
-
-+ resets = <&rstctrl 19>;
-+ reset-names = "uartl";
-+
- interrupt-parent = <&intc>;
- interrupts = <12>;
-
- reg-shift = <2>;
- };
- };
-+
-+ rstctrl: rstctrl {
-+ compatible = "ralink,rt3883-reset", "ralink,rt2880-reset";
-+ #reset-cells = <1>;
-+ };
-+
-+ pci@10140000 {
-+ compatible = "ralink,rt3883-pci";
-+ reg = <0x10140000 0x20000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges; /* direct mapping */
-+
-+ status = "disabled";
-+
-+ pciintc: interrupt-controller {
-+ interrupt-controller;
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
-+
-+ interrupt-parent = <&cpuintc>;
-+ interrupts = <4>;
-+ };
-+
-+ host-bridge {
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+
-+ device_type = "pci";
-+
-+ bus-range = <0 255>;
-+ ranges = <
-+ 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
-+ 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
-+ >;
-+
-+ interrupt-map-mask = <0xf800 0 0 7>;
-+ interrupt-map = <
-+ /* IDSEL 17 */
-+ 0x8800 0 0 1 &pciintc 18
-+ 0x8800 0 0 2 &pciintc 18
-+ 0x8800 0 0 3 &pciintc 18
-+ 0x8800 0 0 4 &pciintc 18
-+ /* IDSEL 18 */
-+ 0x9000 0 0 1 &pciintc 19
-+ 0x9000 0 0 2 &pciintc 19
-+ 0x9000 0 0 3 &pciintc 19
-+ 0x9000 0 0 4 &pciintc 19
-+ >;
-+
-+ pci-bridge@1 {
-+ reg = <0x0800 0 0 0 0>;
-+ device_type = "pci";
-+ #interrupt-cells = <1>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ status = "disabled";
-+
-+ ralink,pci-slot = <1>;
-+
-+ interrupt-map-mask = <0x0 0 0 0>;
-+ interrupt-map = <0x0 0 0 0 &pciintc 20>;
-+ };
-+
-+ pci-slot@17 {
-+ reg = <0x8800 0 0 0 0>;
-+ device_type = "pci";
-+ #interrupt-cells = <1>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ ralink,pci-slot = <17>;
-+
-+ status = "disabled";
-+ };
-+
-+ pci-slot@18 {
-+ reg = <0x9000 0 0 0 0>;
-+ device_type = "pci";
-+ #interrupt-cells = <1>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ ralink,pci-slot = <18>;
-+
-+ status = "disabled";
-+ };
-+ };
-+ };
- };
+++ /dev/null
-From f6dc5d40c766e5ff9b18b93a1b6f7a576655f9c4 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 16:26:41 +0200
-Subject: [PATCH 21/25] MIPS: ralink: add cpu frequency scaling
-
-This feature will break udelay() and cause the delay loop to have longer delays
-when the frequency is scaled causing a performance hit.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/cevt-rt3352.c | 36 ++++++++++++++++++++++++++++++++++++
- 1 file changed, 36 insertions(+)
-
---- a/arch/mips/ralink/cevt-rt3352.c
-+++ b/arch/mips/ralink/cevt-rt3352.c
-@@ -29,6 +29,10 @@
- /* enable the counter */
- #define CFG_CNT_EN 0x1
-
-+/* mt7620 frequency scaling defines */
-+#define CLK_LUT_CFG 0x40
-+#define SLEEP_EN BIT(31)
-+
- struct systick_device {
- void __iomem *membase;
- struct clock_event_device dev;
-@@ -36,6 +40,8 @@ struct systick_device {
- int freq_scale;
- };
-
-+static void (*systick_freq_scaling)(struct systick_device *sdev, int status);
-+
- static void systick_set_clock_mode(enum clock_event_mode mode,
- struct clock_event_device *evt);
-
-@@ -87,6 +93,21 @@ static struct irqaction systick_irqactio
- .dev_id = &systick.dev,
- };
-
-+static inline void mt7620_freq_scaling(struct systick_device *sdev, int status)
-+{
-+ if (sdev->freq_scale == status)
-+ return;
-+
-+ sdev->freq_scale = status;
-+
-+ pr_info("%s: %s autosleep mode\n", systick.dev.name,
-+ (status) ? ("enable") : ("disable"));
-+ if (status)
-+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG);
-+ else
-+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG);
-+}
-+
- static void systick_set_clock_mode(enum clock_event_mode mode,
- struct clock_event_device *evt)
- {
-@@ -101,9 +122,13 @@ static void systick_set_clock_mode(enum
- sdev->irq_requested = 1;
- iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN,
- systick.membase + SYSTICK_CONFIG);
-+ if (systick_freq_scaling)
-+ systick_freq_scaling(sdev, 1);
- break;
-
- case CLOCK_EVT_MODE_SHUTDOWN:
-+ if (systick_freq_scaling)
-+ systick_freq_scaling(sdev, 0);
- if (sdev->irq_requested)
- free_irq(systick.dev.irq, &systick_irqaction);
- sdev->irq_requested = 0;
-@@ -116,12 +141,23 @@ static void systick_set_clock_mode(enum
- }
- }
-
-+static const struct of_device_id systick_match[] = {
-+ { .compatible = "ralink,mt7620-systick", .data = mt7620_freq_scaling},
-+ {},
-+};
-+
- static void __init ralink_systick_init(struct device_node *np)
- {
-+ const struct of_device_id *match;
-+
- systick.membase = of_iomap(np, 0);
- if (!systick.membase)
- return;
-
-+ match = of_match_node(systick_match, np);
-+ if (match)
-+ systick_freq_scaling = match->data;
-+
- systick_irqaction.name = np->name;
- systick.dev.name = np->name;
- clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
+++ /dev/null
-From patchwork Fri Aug 23 12:03:20 2013
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-Subject: [v3] MIPS: add driver for the built-in PCI controller of the RT3883
- SoC
-From: Gabor Juhos <juhosg@openwrt.org>
-X-Patchwork-Id: 5758
-Message-Id: <1377259400-21211-1-git-send-email-juhosg@openwrt.org>
-To: Ralf Baechle <ralf@linux-mips.org>
-Cc: linux-mips@linux-mips.org, Gabor Juhos <juhosg@openwrt.org>,
- devicetree@vger.kernel.org
-Date: Fri, 23 Aug 2013 14:03:20 +0200
-
-The Ralink RT3883 SoCs have a built-in PCI Host Controller
-device. The patch adds a platform driver and device tree
-binding documentation for that.
-
-The patch also enables the HW_HAS_PCI config option. This
-is required in order to be able to enable the PCI support.
-
-Cc: devicetree@vger.kernel.org
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: John Crispin <blogic@openwrt.org>
-
----
-Changes since v2:
- - fix compiler warning:
-
- CC arch/mips/pci/pci-rt3883.o
- arch/mips/pci/pci-rt3883.c: In function 'rt3883_pci_probe':
- arch/mips/pci/pci-rt3883.c:458:4: warning: use of 'h' length modifier with 'a' type character [-Wformat]
-
-Changes since v1:
- - change the 'status' property to optional in the binding doc
- - add board specific example to the binding doc
-
-rt3883-pci: fix-build-warning
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- .../devicetree/bindings/pci/ralink,rt3883-pci.txt | 190 ++++++
- arch/mips/pci/Makefile | 1 +
- arch/mips/pci/pci-rt3883.c | 636 ++++++++++++++++++++
- arch/mips/ralink/Kconfig | 1 +
- 4 files changed, 828 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt
- create mode 100644 arch/mips/pci/pci-rt3883.c
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt
-@@ -0,0 +1,190 @@
-+* Mediatek/Ralink RT3883 PCI controller
-+
-+1) Main node
-+
-+ Required properties:
-+
-+ - compatible: must be "ralink,rt3883-pci"
-+
-+ - reg: specifies the physical base address of the controller and
-+ the length of the memory mapped region.
-+
-+ - #address-cells: specifies the number of cells needed to encode an
-+ address. The value must be 1.
-+
-+ - #size-cells: specifies the number of cells used to represent the size
-+ of an address. The value must be 1.
-+
-+ - ranges: specifies the translation between child address space and parent
-+ address space
-+
-+ Optional properties:
-+
-+ - status: indicates the operational status of the device.
-+ Value must be either "disabled" or "okay".
-+
-+2) Child nodes
-+
-+ The main node must have two child nodes which describes the built-in
-+ interrupt controller and the PCI host bridge.
-+
-+ a) Interrupt controller:
-+
-+ Required properties:
-+
-+ - interrupt-controller: identifies the node as an interrupt controller
-+
-+ - #address-cells: specifies the number of cells needed to encode an
-+ address. The value must be 0. As such, 'interrupt-map' nodes do not
-+ have to specify a parent unit address.
-+
-+ - #interrupt-cells: specifies the number of cells needed to encode an
-+ interrupt source. The value must be 1.
-+
-+ - interrupt-parent: the phandle for the interrupt controller that
-+ services interrupts for this device.
-+
-+ - interrupts: specifies the interrupt source of the parent interrupt
-+ controller. The format of the interrupt specifier depends on the
-+ parent interrupt controller.
-+
-+ b) PCI host bridge:
-+
-+ Required properties:
-+
-+ - #address-cells: specifies the number of cells needed to encode an
-+ address. The value must be 0.
-+
-+ - #size-cells: specifies the number of cells used to represent the size
-+ of an address. The value must be 2.
-+
-+ - #interrupt-cells: specifies the number of cells needed to encode an
-+ interrupt source. The value must be 1.
-+
-+ - device_type: must be "pci"
-+
-+ - bus-range: PCI bus numbers covered
-+
-+ - ranges: specifies the ranges for the PCI memory and I/O regions
-+
-+ - interrupt-map-mask,
-+ - interrupt-map: standard PCI properties to define the mapping of the
-+ PCI interface to interrupt numbers.
-+
-+ The PCI host bridge node migh have additional sub-nodes representing
-+ the onboard PCI devices/PCI slots. Each such sub-node must have the
-+ following mandatory properties:
-+
-+ - reg: used only for interrupt mapping, so only the first four bytes
-+ are used to refer to the correct bus number and device number.
-+
-+ - device_type: must be "pci"
-+
-+ If a given sub-node represents a PCI bridge it must have following
-+ mandatory properties as well:
-+
-+ - #address-cells: must be set to <3>
-+
-+ - #size-cells: must set to <2>
-+
-+ - #interrupt-cells: must be set to <1>
-+
-+ - interrupt-map-mask,
-+ - interrupt-map: standard PCI properties to define the mapping of the
-+ PCI interface to interrupt numbers.
-+
-+ Besides the required properties the sub-nodes may have these optional
-+ properties:
-+
-+ - status: indicates the operational status of the sub-node.
-+ Value must be either "disabled" or "okay".
-+
-+3) Example:
-+
-+ a) SoC specific dtsi file:
-+
-+ pci@10140000 {
-+ compatible = "ralink,rt3883-pci";
-+ reg = <0x10140000 0x20000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges; /* direct mapping */
-+
-+ status = "disabled";
-+
-+ pciintc: interrupt-controller {
-+ interrupt-controller;
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
-+
-+ interrupt-parent = <&cpuintc>;
-+ interrupts = <4>;
-+ };
-+
-+ host-bridge {
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+
-+ device_type = "pci";
-+
-+ bus-range = <0 255>;
-+ ranges = <
-+ 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
-+ 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
-+ >;
-+
-+ interrupt-map-mask = <0xf800 0 0 7>;
-+ interrupt-map = <
-+ /* IDSEL 17 */
-+ 0x8800 0 0 1 &pciintc 18
-+ 0x8800 0 0 2 &pciintc 18
-+ 0x8800 0 0 3 &pciintc 18
-+ 0x8800 0 0 4 &pciintc 18
-+ /* IDSEL 18 */
-+ 0x9000 0 0 1 &pciintc 19
-+ 0x9000 0 0 2 &pciintc 19
-+ 0x9000 0 0 3 &pciintc 19
-+ 0x9000 0 0 4 &pciintc 19
-+ >;
-+
-+ pci-bridge@1 {
-+ reg = <0x0800 0 0 0 0>;
-+ device_type = "pci";
-+ #interrupt-cells = <1>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ interrupt-map-mask = <0x0 0 0 0>;
-+ interrupt-map = <0x0 0 0 0 &pciintc 20>;
-+
-+ status = "disabled";
-+ };
-+
-+ pci-slot@17 {
-+ reg = <0x8800 0 0 0 0>;
-+ device_type = "pci";
-+
-+ status = "disabled";
-+ };
-+
-+ pci-slot@18 {
-+ reg = <0x9000 0 0 0 0>;
-+ device_type = "pci";
-+
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
-+ b) Board specific dts file:
-+
-+ pci@10140000 {
-+ status = "okay";
-+
-+ host-bridge {
-+ pci-bridge@1 {
-+ status = "okay";
-+ };
-+ };
-+ };
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
- obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
- obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
- obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
-+obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
- obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
- obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
- obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
---- /dev/null
-+++ b/arch/mips/pci/pci-rt3883.c
-@@ -0,0 +1,636 @@
-+/*
-+ * Ralink RT3662/RT3883 SoC PCI support
-+ *
-+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
-+ *
-+ * Parts of this file are based on Ralink's 2.6.21 BSP
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/pci.h>
-+#include <linux/io.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_pci.h>
-+#include <linux/platform_device.h>
-+
-+#include <asm/mach-ralink/rt3883.h>
-+#include <asm/mach-ralink/ralink_regs.h>
-+
-+#define RT3883_MEMORY_BASE 0x00000000
-+#define RT3883_MEMORY_SIZE 0x02000000
-+
-+#define RT3883_PCI_REG_PCICFG 0x00
-+#define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
-+#define RT3883_PCICFG_P2P_BR_DEVNUM_S 16
-+#define RT3883_PCICFG_PCIRST BIT(1)
-+#define RT3883_PCI_REG_PCIRAW 0x04
-+#define RT3883_PCI_REG_PCIINT 0x08
-+#define RT3883_PCI_REG_PCIENA 0x0c
-+
-+#define RT3883_PCI_REG_CFGADDR 0x20
-+#define RT3883_PCI_REG_CFGDATA 0x24
-+#define RT3883_PCI_REG_MEMBASE 0x28
-+#define RT3883_PCI_REG_IOBASE 0x2c
-+#define RT3883_PCI_REG_ARBCTL 0x80
-+
-+#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
-+#define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
-+#define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
-+#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
-+#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
-+#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
-+#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
-+
-+#define RT3883_PCI_MODE_NONE 0
-+#define RT3883_PCI_MODE_PCI BIT(0)
-+#define RT3883_PCI_MODE_PCIE BIT(1)
-+#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
-+
-+#define RT3883_PCI_IRQ_COUNT 32
-+
-+#define RT3883_P2P_BR_DEVNUM 1
-+
-+struct rt3883_pci_controller {
-+ void __iomem *base;
-+ spinlock_t lock;
-+
-+ struct device_node *intc_of_node;
-+ struct irq_domain *irq_domain;
-+
-+ struct pci_controller pci_controller;
-+ struct resource io_res;
-+ struct resource mem_res;
-+
-+ bool pcie_ready;
-+};
-+
-+static inline struct rt3883_pci_controller *
-+pci_bus_to_rt3883_controller(struct pci_bus *bus)
-+{
-+ struct pci_controller *hose;
-+
-+ hose = (struct pci_controller *) bus->sysdata;
-+ return container_of(hose, struct rt3883_pci_controller, pci_controller);
-+}
-+
-+static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
-+ unsigned reg)
-+{
-+ return ioread32(rpc->base + reg);
-+}
-+
-+static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
-+ u32 val, unsigned reg)
-+{
-+ iowrite32(val, rpc->base + reg);
-+}
-+
-+static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
-+ unsigned int func, unsigned int where)
-+{
-+ return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
-+ 0x80000000;
-+}
-+
-+static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
-+ unsigned bus, unsigned slot,
-+ unsigned func, unsigned reg)
-+{
-+ unsigned long flags;
-+ u32 address;
-+ u32 ret;
-+
-+ address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
-+
-+ spin_lock_irqsave(&rpc->lock, flags);
-+ rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
-+ ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
-+ spin_unlock_irqrestore(&rpc->lock, flags);
-+
-+ return ret;
-+}
-+
-+static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
-+ unsigned bus, unsigned slot,
-+ unsigned func, unsigned reg, u32 val)
-+{
-+ unsigned long flags;
-+ u32 address;
-+
-+ address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
-+
-+ spin_lock_irqsave(&rpc->lock, flags);
-+ rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
-+ rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
-+ spin_unlock_irqrestore(&rpc->lock, flags);
-+}
-+
-+static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
-+{
-+ struct rt3883_pci_controller *rpc;
-+ u32 pending;
-+
-+ rpc = irq_get_handler_data(irq);
-+
-+ pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
-+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
-+
-+ if (!pending) {
-+ spurious_interrupt();
-+ return;
-+ }
-+
-+ while (pending) {
-+ unsigned bit = __ffs(pending);
-+
-+ irq = irq_find_mapping(rpc->irq_domain, bit);
-+ generic_handle_irq(irq);
-+
-+ pending &= ~BIT(bit);
-+ }
-+}
-+
-+static void rt3883_pci_irq_unmask(struct irq_data *d)
-+{
-+ struct rt3883_pci_controller *rpc;
-+ u32 t;
-+
-+ rpc = irq_data_get_irq_chip_data(d);
-+
-+ t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
-+ rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
-+ /* flush write */
-+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
-+}
-+
-+static void rt3883_pci_irq_mask(struct irq_data *d)
-+{
-+ struct rt3883_pci_controller *rpc;
-+ u32 t;
-+
-+ rpc = irq_data_get_irq_chip_data(d);
-+
-+ t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
-+ rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
-+ /* flush write */
-+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
-+}
-+
-+static struct irq_chip rt3883_pci_irq_chip = {
-+ .name = "RT3883 PCI",
-+ .irq_mask = rt3883_pci_irq_mask,
-+ .irq_unmask = rt3883_pci_irq_unmask,
-+ .irq_mask_ack = rt3883_pci_irq_mask,
-+};
-+
-+static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
-+ irq_hw_number_t hw)
-+{
-+ irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
-+ irq_set_chip_data(irq, d->host_data);
-+
-+ return 0;
-+}
-+
-+static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
-+ .map = rt3883_pci_irq_map,
-+ .xlate = irq_domain_xlate_onecell,
-+};
-+
-+static int rt3883_pci_irq_init(struct device *dev,
-+ struct rt3883_pci_controller *rpc)
-+{
-+ int irq;
-+
-+ irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
-+ if (irq == 0) {
-+ dev_err(dev, "%s has no IRQ",
-+ of_node_full_name(rpc->intc_of_node));
-+ return -EINVAL;
-+ }
-+
-+ /* disable all interrupts */
-+ rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
-+
-+ rpc->irq_domain =
-+ irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
-+ &rt3883_pci_irq_domain_ops,
-+ rpc);
-+ if (!rpc->irq_domain) {
-+ dev_err(dev, "unable to add IRQ domain\n");
-+ return -ENODEV;
-+ }
-+
-+ irq_set_handler_data(irq, rpc);
-+ irq_set_chained_handler(irq, rt3883_pci_irq_handler);
-+
-+ return 0;
-+}
-+
-+static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 *val)
-+{
-+ struct rt3883_pci_controller *rpc;
-+ unsigned long flags;
-+ u32 address;
-+ u32 data;
-+
-+ rpc = pci_bus_to_rt3883_controller(bus);
-+
-+ if (!rpc->pcie_ready && bus->number == 1)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
-+ PCI_FUNC(devfn), where);
-+
-+ spin_lock_irqsave(&rpc->lock, flags);
-+ rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
-+ data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
-+ spin_unlock_irqrestore(&rpc->lock, flags);
-+
-+ switch (size) {
-+ case 1:
-+ *val = (data >> ((where & 3) << 3)) & 0xff;
-+ break;
-+ case 2:
-+ *val = (data >> ((where & 3) << 3)) & 0xffff;
-+ break;
-+ case 4:
-+ *val = data;
-+ break;
-+ }
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 val)
-+{
-+ struct rt3883_pci_controller *rpc;
-+ unsigned long flags;
-+ u32 address;
-+ u32 data;
-+
-+ rpc = pci_bus_to_rt3883_controller(bus);
-+
-+ if (!rpc->pcie_ready && bus->number == 1)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
-+ PCI_FUNC(devfn), where);
-+
-+ spin_lock_irqsave(&rpc->lock, flags);
-+ rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
-+ data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
-+
-+ switch (size) {
-+ case 1:
-+ data = (data & ~(0xff << ((where & 3) << 3))) |
-+ (val << ((where & 3) << 3));
-+ break;
-+ case 2:
-+ data = (data & ~(0xffff << ((where & 3) << 3))) |
-+ (val << ((where & 3) << 3));
-+ break;
-+ case 4:
-+ data = val;
-+ break;
-+ }
-+
-+ rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
-+ spin_unlock_irqrestore(&rpc->lock, flags);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static struct pci_ops rt3883_pci_ops = {
-+ .read = rt3883_pci_config_read,
-+ .write = rt3883_pci_config_write,
-+};
-+
-+static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
-+{
-+ u32 syscfg1;
-+ u32 rstctrl;
-+ u32 clkcfg1;
-+ u32 t;
-+
-+ rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
-+ syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
-+ clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
-+
-+ if (mode & RT3883_PCI_MODE_PCIE) {
-+ rstctrl |= RT3883_RSTCTRL_PCIE;
-+ rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
-+
-+ /* setup PCI PAD drive mode */
-+ syscfg1 &= ~(0x30);
-+ syscfg1 |= (2 << 4);
-+ rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
-+
-+ t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
-+ t &= ~BIT(31);
-+ rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
-+
-+ t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
-+ t &= 0x80ffffff;
-+ rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
-+
-+ t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
-+ t |= 0xa << 24;
-+ rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
-+
-+ t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
-+ t |= BIT(31);
-+ rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
-+
-+ msleep(50);
-+
-+ rstctrl &= ~RT3883_RSTCTRL_PCIE;
-+ rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
-+ }
-+
-+ syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
-+
-+ clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
-+
-+ if (mode & RT3883_PCI_MODE_PCI) {
-+ clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
-+ rstctrl &= ~RT3883_RSTCTRL_PCI;
-+ }
-+
-+ if (mode & RT3883_PCI_MODE_PCIE) {
-+ clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
-+ rstctrl &= ~RT3883_RSTCTRL_PCIE;
-+ }
-+
-+ rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
-+ rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
-+ rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
-+
-+ msleep(500);
-+
-+ /*
-+ * setup the device number of the P2P bridge
-+ * and de-assert the reset line
-+ */
-+ t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
-+ rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
-+
-+ /* flush write */
-+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
-+ msleep(500);
-+
-+ if (mode & RT3883_PCI_MODE_PCIE) {
-+ msleep(500);
-+
-+ t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
-+
-+ rpc->pcie_ready = t & BIT(0);
-+
-+ if (!rpc->pcie_ready) {
-+ /* reset the PCIe block */
-+ t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
-+ t |= RT3883_RSTCTRL_PCIE;
-+ rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
-+ t &= ~RT3883_RSTCTRL_PCIE;
-+ rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
-+
-+ /* turn off PCIe clock */
-+ t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
-+ t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
-+ rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
-+
-+ t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
-+ t &= ~0xf000c080;
-+ rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
-+ }
-+ }
-+
-+ /* enable PCI arbiter */
-+ rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
-+}
-+
-+static int rt3883_pci_probe(struct platform_device *pdev)
-+{
-+ struct rt3883_pci_controller *rpc;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *np = dev->of_node;
-+ struct resource *res;
-+ struct device_node *child;
-+ u32 val;
-+ int err;
-+ int mode;
-+
-+ rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
-+ if (!rpc)
-+ return -ENOMEM;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!res)
-+ return -EINVAL;
-+
-+ rpc->base = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(rpc->base))
-+ return PTR_ERR(rpc->base);
-+
-+ /* find the interrupt controller child node */
-+ for_each_child_of_node(np, child) {
-+ if (of_get_property(child, "interrupt-controller", NULL) &&
-+ of_node_get(child)) {
-+ rpc->intc_of_node = child;
-+ break;
-+ }
-+ }
-+
-+ if (!rpc->intc_of_node) {
-+ dev_err(dev, "%s has no %s child node",
-+ of_node_full_name(rpc->intc_of_node),
-+ "interrupt controller");
-+ return -EINVAL;
-+ }
-+
-+ /* find the PCI host bridge child node */
-+ for_each_child_of_node(np, child) {
-+ if (child->type &&
-+ of_node_cmp(child->type, "pci") == 0 &&
-+ of_node_get(child)) {
-+ rpc->pci_controller.of_node = child;
-+ break;
-+ }
-+ }
-+
-+ if (!rpc->pci_controller.of_node) {
-+ dev_err(dev, "%s has no %s child node",
-+ of_node_full_name(rpc->intc_of_node),
-+ "PCI host bridge");
-+ err = -EINVAL;
-+ goto err_put_intc_node;
-+ }
-+
-+ mode = RT3883_PCI_MODE_NONE;
-+ for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
-+ int devfn;
-+
-+ if (!child->type ||
-+ of_node_cmp(child->type, "pci") != 0)
-+ continue;
-+
-+ devfn = of_pci_get_devfn(child);
-+ if (devfn < 0)
-+ continue;
-+
-+ switch (PCI_SLOT(devfn)) {
-+ case 1:
-+ mode |= RT3883_PCI_MODE_PCIE;
-+ break;
-+
-+ case 17:
-+ case 18:
-+ mode |= RT3883_PCI_MODE_PCI;
-+ break;
-+ }
-+ }
-+
-+ if (mode == RT3883_PCI_MODE_NONE) {
-+ dev_err(dev, "unable to determine PCI mode\n");
-+ err = -EINVAL;
-+ goto err_put_hb_node;
-+ }
-+
-+ dev_info(dev, "mode:%s%s\n",
-+ (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
-+ (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
-+
-+ rt3883_pci_preinit(rpc, mode);
-+
-+ rpc->pci_controller.pci_ops = &rt3883_pci_ops;
-+ rpc->pci_controller.io_resource = &rpc->io_res;
-+ rpc->pci_controller.mem_resource = &rpc->mem_res;
-+
-+ /* Load PCI I/O and memory resources from DT */
-+ pci_load_of_ranges(&rpc->pci_controller,
-+ rpc->pci_controller.of_node);
-+
-+ rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
-+ rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
-+
-+ ioport_resource.start = rpc->io_res.start;
-+ ioport_resource.end = rpc->io_res.end;
-+
-+ /* PCI */
-+ rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
-+ rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
-+ rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
-+ rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
-+ rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
-+
-+ /* PCIe */
-+ rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
-+ rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
-+ rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
-+ rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
-+ rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
-+
-+ err = rt3883_pci_irq_init(dev, rpc);
-+ if (err)
-+ goto err_put_hb_node;
-+
-+ /* PCIe */
-+ val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
-+ val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
-+ rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
-+
-+ /* PCI */
-+ val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
-+ val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
-+ rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
-+
-+ if (mode == RT3883_PCI_MODE_PCIE) {
-+ rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
-+ rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
-+
-+ rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
-+ PCI_BASE_ADDRESS_0,
-+ RT3883_MEMORY_BASE);
-+ /* flush write */
-+ rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
-+ PCI_BASE_ADDRESS_0);
-+ } else {
-+ rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
-+ PCI_IO_BASE, 0x00000101);
-+ }
-+
-+ register_pci_controller(&rpc->pci_controller);
-+
-+ return 0;
-+
-+err_put_hb_node:
-+ of_node_put(rpc->pci_controller.of_node);
-+err_put_intc_node:
-+ of_node_put(rpc->intc_of_node);
-+ return err;
-+}
-+
-+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ struct of_irq dev_irq;
-+ int err;
-+ int irq;
-+
-+ err = of_irq_map_pci(dev, &dev_irq);
-+ if (err) {
-+ pr_err("pci %s: unable to get irq map, err=%d\n",
-+ pci_name((struct pci_dev *) dev), err);
-+ return 0;
-+ }
-+
-+ irq = irq_create_of_mapping(dev_irq.controller,
-+ dev_irq.specifier,
-+ dev_irq.size);
-+
-+ if (irq == 0)
-+ pr_crit("pci %s: no irq found for pin %u\n",
-+ pci_name((struct pci_dev *) dev), pin);
-+ else
-+ pr_info("pci %s: using irq %d for pin %u\n",
-+ pci_name((struct pci_dev *) dev), irq, pin);
-+
-+ return irq;
-+}
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+ return 0;
-+}
-+
-+static const struct of_device_id rt3883_pci_ids[] = {
-+ { .compatible = "ralink,rt3883-pci" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, rt3883_pci_ids);
-+
-+static struct platform_driver rt3883_pci_driver = {
-+ .probe = rt3883_pci_probe,
-+ .driver = {
-+ .name = "rt3883-pci",
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(rt3883_pci_ids),
-+ },
-+};
-+
-+static int __init rt3883_pci_init(void)
-+{
-+ return platform_driver_register(&rt3883_pci_driver);
-+}
-+
-+postcore_initcall(rt3883_pci_init);
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -26,6 +26,7 @@ choice
- bool "RT3883"
- select USB_ARCH_HAS_OHCI
- select USB_ARCH_HAS_EHCI
-+ select HW_HAS_PCI
-
- config SOC_MT7620
- bool "MT7620"
+++ /dev/null
-From 1be15a87eea5f26fb24b6aac332530cd3e2d984e Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 14 Jul 2013 23:08:11 +0200
-Subject: [PATCH 100/133] MIPS: use set_mode() to enable/disable the cevt-r4k
- irq
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/kernel/cevt-r4k.c | 39 ++++++++++++++++++++++++++-------------
- 1 file changed, 26 insertions(+), 13 deletions(-)
-
---- a/arch/mips/kernel/cevt-r4k.c
-+++ b/arch/mips/kernel/cevt-r4k.c
-@@ -38,12 +38,6 @@ static int mips_next_event(unsigned long
-
- #endif /* CONFIG_MIPS_MT_SMTC */
-
--void mips_set_clock_mode(enum clock_event_mode mode,
-- struct clock_event_device *evt)
--{
-- /* Nothing to do ... */
--}
--
- DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
- int cp0_timer_irq_installed;
-
-@@ -90,9 +84,38 @@ struct irqaction c0_compare_irqaction =
- .name = "timer",
- };
-
-+void mips_set_clock_mode(enum clock_event_mode mode,
-+ struct clock_event_device *evt)
-+{
-+#ifdef CONFIG_CEVT_SYSTICK_QUIRK
-+ switch (mode) {
-+ case CLOCK_EVT_MODE_ONESHOT:
-+ if (cp0_timer_irq_installed)
-+ break;
-+
-+ cp0_timer_irq_installed = 1;
-+
-+ setup_irq(evt->irq, &c0_compare_irqaction);
-+ break;
-+
-+ case CLOCK_EVT_MODE_SHUTDOWN:
-+ if (!cp0_timer_irq_installed)
-+ break;
-+
-+ cp0_timer_irq_installed = 0;
-+ free_irq(evt->irq, &c0_compare_irqaction);
-+ break;
-+
-+ default:
-+ pr_err("Unhandeled mips clock_mode\n");
-+ break;
-+ }
-+#endif
-+}
-
- void mips_event_handler(struct clock_event_device *dev)
- {
-+
- }
-
- /*
-@@ -215,12 +238,14 @@ int __cpuinit r4k_clockevent_init(void)
- #endif
- clockevents_register_device(cd);
-
-+#ifndef CONFIG_CEVT_SYSTICK_QUIRK
- if (cp0_timer_irq_installed)
- return 0;
-
- cp0_timer_irq_installed = 1;
-
- setup_irq(irq, &c0_compare_irqaction);
-+#endif
-
- return 0;
- }
+++ /dev/null
-From 5689333e7e4396a827a2cb6fa1242159e9af56de Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 20 May 2013 20:57:09 +0200
-Subject: [PATCH 101/133] MIPS: ralink: add verbose pmu info
-
-Print the PMU and LDO settings on boot.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -26,6 +26,22 @@
- #define CLKCFG_FFRAC_MASK 0x001f
- #define CLKCFG_FFRAC_USB_VAL 0x0003
-
-+/* analog */
-+#define PMU0_CFG 0x88
-+#define PMU_SW_SET BIT(28)
-+#define A_DCDC_EN BIT(24)
-+#define A_SSC_PERI BIT(19)
-+#define A_SSC_GEN BIT(18)
-+#define A_SSC_M 0x3
-+#define A_SSC_S 16
-+#define A_DLY_M 0x7
-+#define A_DLY_S 8
-+#define A_VTUNE_M 0xff
-+
-+/* digital */
-+#define PMU1_CFG 0x8C
-+#define DIG_SW_SEL BIT(25)
-+
- /* does the board have sdram or ddram */
- static int dram_type;
-
-@@ -208,6 +224,8 @@ void prom_soc_init(struct ralink_soc_inf
- u32 n1;
- u32 rev;
- u32 cfg0;
-+ u32 pmu0;
-+ u32 pmu1;
-
- n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
- n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
-@@ -255,4 +273,12 @@ void prom_soc_init(struct ralink_soc_inf
- BUG();
- }
- soc_info->mem_base = MT7620_DRAM_BASE;
-+
-+ pmu0 = __raw_readl(sysc + PMU0_CFG);
-+ pmu1 = __raw_readl(sysc + PMU1_CFG);
-+
-+ pr_info("Analog PMU set to %s control\n",
-+ (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
-+ pr_info("Digital PMU set to %s control\n",
-+ (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
- }
+++ /dev/null
-From 23d18a1b3d0a7e5faa08b6bece6692667c930975 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Tue, 21 May 2013 15:50:31 +0200
-Subject: [PATCH 102/133] MIPS: ralink: adds a bootrom dumper module
-
-This patch adds a trivial driver that allows userland to extract the bootrom of
-a SoC via debugfs.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/Makefile | 2 ++
- arch/mips/ralink/bootrom.c | 48 ++++++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 50 insertions(+)
- create mode 100644 arch/mips/ralink/bootrom.c
-
---- a/arch/mips/ralink/Makefile
-+++ b/arch/mips/ralink/Makefile
-@@ -17,4 +17,6 @@ obj-$(CONFIG_SOC_MT7620) += mt7620.o
-
- obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-
-+obj-$(CONFIG_DEBUG_FS) += bootrom.o
-+
- obj-y += dts/
---- /dev/null
-+++ b/arch/mips/ralink/bootrom.c
-@@ -0,0 +1,48 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/debugfs.h>
-+#include <linux/seq_file.h>
-+
-+#define BOOTROM_OFFSET 0x10118000
-+#define BOOTROM_SIZE 0x8000
-+
-+static void __iomem *membase = (void __iomem*) KSEG1ADDR(BOOTROM_OFFSET);
-+
-+static int bootrom_show(struct seq_file *s, void *unused)
-+{
-+ seq_write(s, membase, BOOTROM_SIZE);
-+
-+ return 0;
-+}
-+
-+static int bootrom_open(struct inode *inode, struct file *file)
-+{
-+ return single_open(file, bootrom_show, NULL);
-+}
-+
-+static const struct file_operations bootrom_file_ops = {
-+ .open = bootrom_open,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = single_release,
-+};
-+
-+static int bootrom_setup(void)
-+{
-+ if (!debugfs_create_file("bootrom", 0444,
-+ NULL, NULL, &bootrom_file_ops)) {
-+ pr_err("Failed to create bootrom debugfs file\n");
-+
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+postcore_initcall(bootrom_setup);
+++ /dev/null
-From c5fe00f24f56b15f982dda355089986d57488b36 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 16 May 2013 23:28:23 +0200
-Subject: [PATCH 103/133] MIPS: ralink: add illegal access driver
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/Makefile | 2 +
- arch/mips/ralink/ill_acc.c | 87 ++++++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 89 insertions(+)
- create mode 100644 arch/mips/ralink/ill_acc.c
-
---- a/arch/mips/ralink/Makefile
-+++ b/arch/mips/ralink/Makefile
-@@ -10,6 +10,8 @@ obj-y := prom.o of.o reset.o clk.o irq.o
-
- obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
-
-+obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
-+
- obj-$(CONFIG_SOC_RT288X) += rt288x.o
- obj-$(CONFIG_SOC_RT305X) += rt305x.o
- obj-$(CONFIG_SOC_RT3883) += rt3883.o
---- /dev/null
-+++ b/arch/mips/ralink/ill_acc.c
-@@ -0,0 +1,87 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/interrupt.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_irq.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+
-+#define REG_ILL_ACC_ADDR 0x10
-+#define REG_ILL_ACC_TYPE 0x14
-+
-+#define ILL_INT_STATUS BIT(31)
-+#define ILL_ACC_WRITE BIT(30)
-+#define ILL_ACC_LEN_M 0xff
-+#define ILL_ACC_OFF_M 0xf
-+#define ILL_ACC_OFF_S 16
-+#define ILL_ACC_ID_M 0x7
-+#define ILL_ACC_ID_S 8
-+
-+#define DRV_NAME "ill_acc"
-+
-+static const char *ill_acc_ids[] = {
-+ "cpu", "dma", "ppe", "pdma rx","pdma tx", "pci/e", "wmac", "usb",
-+};
-+
-+static irqreturn_t ill_acc_irq_handler(int irq, void *_priv)
-+{
-+ struct device *dev = (struct device *) _priv;
-+ u32 addr = rt_memc_r32(REG_ILL_ACC_ADDR);
-+ u32 type = rt_memc_r32(REG_ILL_ACC_TYPE);
-+
-+ dev_err(dev, "illegal %s access from %s - addr:0x%08x offset:%d len:%d\n",
-+ (type & ILL_ACC_WRITE) ? ("write") : ("read"),
-+ ill_acc_ids[(type >> ILL_ACC_ID_S) & ILL_ACC_ID_M],
-+ addr, (type >> ILL_ACC_OFF_S) & ILL_ACC_OFF_M,
-+ type & ILL_ACC_LEN_M);
-+
-+ rt_memc_w32(REG_ILL_ACC_TYPE, REG_ILL_ACC_TYPE);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int __init ill_acc_of_setup(void)
-+{
-+ struct platform_device *pdev;
-+ struct device_node *np;
-+ int irq;
-+
-+ /* somehow this driver breaks on RT5350 */
-+ if (of_machine_is_compatible("ralink,rt5350-soc"))
-+ return -EINVAL;
-+
-+ np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-memc");
-+ if (!np)
-+ return -EINVAL;
-+
-+ pdev = of_find_device_by_node(np);
-+ if (!pdev) {
-+ pr_err("%s: failed to lookup pdev\n", np->name);
-+ return -EINVAL;
-+ }
-+
-+ irq = irq_of_parse_and_map(np, 0);
-+ if (!irq) {
-+ dev_err(&pdev->dev, "failed to get irq\n");
-+ return -EINVAL;
-+ }
-+
-+ if (request_irq(irq, ill_acc_irq_handler, 0, "ill_acc", &pdev->dev)) {
-+ dev_err(&pdev->dev, "failed to request irq\n");
-+ return -EINVAL;
-+ }
-+
-+ rt_memc_w32(ILL_INT_STATUS, REG_ILL_ACC_TYPE);
-+
-+ dev_info(&pdev->dev, "irq registered\n");
-+
-+ return 0;
-+}
-+
-+arch_initcall(ill_acc_of_setup);
+++ /dev/null
-From b83808826ac7a5c727f5314b5a3bf07fcd6ec929 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 23 May 2013 18:50:56 +0200
-Subject: [PATCH 104/133] MIPS: ralink: workaround DTB memory issue
-
-If the DTB is too big a bug happens on boot when init ram is freed.
-This is a temporary fix until the real cause is found.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/of.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -74,7 +74,7 @@ void __init device_tree_init(void)
- unflatten_device_tree();
-
- /* free the space reserved for the dt blob */
-- free_bootmem(base, size);
-+ //free_bootmem(base, size);
- }
-
- void __init plat_mem_setup(void)
+++ /dev/null
-From 6f72aea69951479b7daad1d38b506ede4f8a1676 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 16 Mar 2014 04:38:07 +0000
-Subject: [PATCH 105/133] MIPS: ralink: add missing clk_set_rate() to clk.c
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/clk.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/arch/mips/ralink/clk.c
-+++ b/arch/mips/ralink/clk.c
-@@ -56,6 +56,12 @@ unsigned long clk_get_rate(struct clk *c
- }
- EXPORT_SYMBOL_GPL(clk_get_rate);
-
-+int clk_set_rate(struct clk *clk, unsigned long rate)
-+{
-+ return -1;
-+}
-+EXPORT_SYMBOL_GPL(clk_set_rate);
-+
- void __init plat_time_init(void)
- {
- struct clk *clk;
+++ /dev/null
-From 45ba0675286e2a71f6a577833ab13b951bb7e31a Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 16 Mar 2014 04:40:02 +0000
-Subject: [PATCH 106/133] MIPS: ralink: add support for MT7620n
-
-This is the small version of MT7620a.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/mach-ralink/mt7620.h | 7 ++-----
- arch/mips/ralink/mt7620.c | 19 ++++++++++++-------
- 2 files changed, 14 insertions(+), 12 deletions(-)
-
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -24,11 +24,8 @@
- #define SYSC_REG_CPLL_CONFIG0 0x54
- #define SYSC_REG_CPLL_CONFIG1 0x58
-
--#define MT7620N_CHIP_NAME0 0x33365452
--#define MT7620N_CHIP_NAME1 0x20203235
--
--#define MT7620A_CHIP_NAME0 0x3637544d
--#define MT7620A_CHIP_NAME1 0x20203032
-+#define MT7620_CHIP_NAME0 0x3637544d
-+#define MT7620_CHIP_NAME1 0x20203032
-
- #define CHIP_REV_PKG_MASK 0x1
- #define CHIP_REV_PKG_SHIFT 16
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -226,22 +226,27 @@ void prom_soc_init(struct ralink_soc_inf
- u32 cfg0;
- u32 pmu0;
- u32 pmu1;
-+ u32 bga;
-
- n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
- n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
-+ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
-+ bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
-
-- if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
-- name = "MT7620N";
-- soc_info->compatible = "ralink,mt7620n-soc";
-- } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
-+ if (n0 != MT7620_CHIP_NAME0 || n1 != MT7620_CHIP_NAME1)
-+ panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
-+
-+ if (bga) {
- name = "MT7620A";
- soc_info->compatible = "ralink,mt7620a-soc";
- } else {
-- panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
-+ name = "MT7620N";
-+ soc_info->compatible = "ralink,mt7620n-soc";
-+#ifdef CONFIG_PCI
-+ panic("mt7620n is only supported for non pci kernels");
-+#endif
- }
-
-- rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
--
- snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
- "Ralink %s ver:%u eco:%u",
- name,
+++ /dev/null
-From ee46d05eefefb0fb40b5682b4f6f3876b496044b Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 16 Mar 2014 04:40:48 +0000
-Subject: [PATCH 107/133] MIPS: ralink: allow manual memory override
-
-RT5350 relies on the bootloader setting up the memc correctly.
-On sme boards the setup is incorrect leading to 32 MB being available but only 16 being recognized. Allow these boards to manually override the memory range
-.
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/of.c | 16 +++++++++++++++-
- 1 file changed, 15 insertions(+), 1 deletion(-)
-
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -77,6 +77,17 @@ void __init device_tree_init(void)
- //free_bootmem(base, size);
- }
-
-+static int memory_dtb;
-+
-+static int __init early_init_dt_find_memory(unsigned long node, const char *uname,
-+ int depth, void *data)
-+{
-+ if (depth == 1 && !strcmp(uname, "memory@0"))
-+ memory_dtb = 1;
-+
-+ return 0;
-+}
-+
- void __init plat_mem_setup(void)
- {
- set_io_port_base(KSEG1);
-@@ -87,7 +98,10 @@ void __init plat_mem_setup(void)
- */
- __dt_setup_arch(&__dtb_start);
-
-- if (soc_info.mem_size)
-+ of_scan_flat_dt(early_init_dt_find_memory, NULL);
-+ if (memory_dtb)
-+ of_scan_flat_dt(early_init_dt_scan_memory, NULL);
-+ else if (soc_info.mem_size)
- add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
- BOOT_MEM_RAM);
- else
+++ /dev/null
-From 1fe4d719d1c973c01f4b6a4c0de47bfac77e3eca Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 19 May 2013 00:42:23 +0200
-Subject: [PATCH 108/133] MIPS: ralink: add rt_sysc_m32 helper
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/mach-ralink/ralink_regs.h | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
-+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
-@@ -26,6 +26,13 @@ static inline u32 rt_sysc_r32(unsigned r
- return __raw_readl(rt_sysc_membase + reg);
- }
-
-+static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg)
-+{
-+ u32 val = rt_sysc_r32(reg) & ~clr;
-+
-+ __raw_writel(val | set, rt_sysc_membase + reg);
-+}
-+
- static inline void rt_memc_w32(u32 val, unsigned reg)
- {
- __raw_writel(val, rt_memc_membase + reg);
+++ /dev/null
-From ca21f813087ca5a8b02ec00efcd9c3f3fbf3bc1f Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 24 Mar 2013 17:17:17 +0100
-Subject: [PATCH 109/133] MIPS: ralink: add pseudo pwm led trigger based on
- timer0
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/timer.c | 213 ++++++++++++++++++++++++++++++++++++++++++----
- 1 file changed, 197 insertions(+), 16 deletions(-)
-
---- a/arch/mips/ralink/timer.c
-+++ b/arch/mips/ralink/timer.c
-@@ -12,6 +12,8 @@
- #include <linux/timer.h>
- #include <linux/of_gpio.h>
- #include <linux/clk.h>
-+#include <linux/leds.h>
-+#include <linux/slab.h>
-
- #include <asm/mach-ralink/ralink_regs.h>
-
-@@ -23,16 +25,34 @@
-
- #define TMR0CTL_ENABLE BIT(7)
- #define TMR0CTL_MODE_PERIODIC BIT(4)
--#define TMR0CTL_PRESCALER 1
-+#define TMR0CTL_PRESCALER 2
- #define TMR0CTL_PRESCALE_VAL (0xf - TMR0CTL_PRESCALER)
- #define TMR0CTL_PRESCALE_DIV (65536 / BIT(TMR0CTL_PRESCALER))
-
-+struct rt_timer_gpio {
-+ struct list_head list;
-+ struct led_classdev *led;
-+};
-+
- struct rt_timer {
-- struct device *dev;
-- void __iomem *membase;
-- int irq;
-- unsigned long timer_freq;
-- unsigned long timer_div;
-+ struct device *dev;
-+ void __iomem *membase;
-+ int irq;
-+
-+ unsigned long timer_freq;
-+ unsigned long timer_div;
-+
-+ struct list_head gpios;
-+ struct led_trigger led_trigger;
-+ unsigned int duty_cycle;
-+ unsigned int duty;
-+
-+ unsigned int fade;
-+ unsigned int fade_min;
-+ unsigned int fade_max;
-+ unsigned int fade_speed;
-+ unsigned int fade_dir;
-+ unsigned int fade_count;
- };
-
- static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val)
-@@ -48,18 +68,46 @@ static inline u32 rt_timer_r32(struct rt
- static irqreturn_t rt_timer_irq(int irq, void *_rt)
- {
- struct rt_timer *rt = (struct rt_timer *) _rt;
-+ struct rt_timer_gpio *gpio;
-+ unsigned int val;
-
-- rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
-+ if (rt->fade && (rt->fade_count++ > rt->fade_speed)) {
-+ rt->fade_count = 0;
-+ if (rt->duty_cycle <= rt->fade_min)
-+ rt->fade_dir = 1;
-+ else if (rt->duty_cycle >= rt->fade_max)
-+ rt->fade_dir = 0;
-+
-+ if (rt->fade_dir)
-+ rt->duty_cycle += 1;
-+ else
-+ rt->duty_cycle -= 1;
-+
-+ }
-+
-+ val = rt->timer_freq / rt->timer_div;
-+ if (rt->duty)
-+ val *= rt->duty_cycle;
-+ else
-+ val *= (100 - rt->duty_cycle);
-+ val /= 100;
-+
-+ if (!list_empty(&rt->gpios))
-+ list_for_each_entry(gpio, &rt->gpios, list)
-+ led_set_brightness(gpio->led, !!rt->duty);
-+
-+ rt->duty = !rt->duty;
-+
-+ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, val + 1);
- rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT);
-
- return IRQ_HANDLED;
- }
-
--
- static int rt_timer_request(struct rt_timer *rt)
- {
-- int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED,
-- dev_name(rt->dev), rt);
-+ int err = devm_request_irq(rt->dev, rt->irq, rt_timer_irq,
-+ IRQF_DISABLED, dev_name(rt->dev), rt);
- if (err) {
- dev_err(rt->dev, "failed to request irq\n");
- } else {
-@@ -81,8 +129,6 @@ static int rt_timer_config(struct rt_tim
- else
- rt->timer_div = divisor;
-
-- rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
--
- return 0;
- }
-
-@@ -108,11 +154,128 @@ static void rt_timer_disable(struct rt_t
- rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
- }
-
-+static ssize_t led_fade_show(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct led_classdev *led_cdev = dev_get_drvdata(dev);
-+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
-+
-+ return sprintf(buf, "speed: %d, min: %d, max: %d\n", rt->fade_speed, rt->fade_min, rt->fade_max);
-+}
-+
-+static ssize_t led_fade_store(struct device *dev,
-+ struct device_attribute *attr, const char *buf, size_t size)
-+{
-+ struct led_classdev *led_cdev = dev_get_drvdata(dev);
-+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
-+ unsigned int speed = 0, min = 0, max = 0;
-+ ssize_t ret = -EINVAL;
-+
-+ ret = sscanf(buf, "%u %u %u", &speed, &min, &max);
-+
-+ if (ret == 3) {
-+ rt->fade_speed = speed;
-+ rt->fade_min = min;
-+ rt->fade_max = max;
-+ rt->fade = 1;
-+ } else {
-+ rt->fade = 0;
-+ }
-+
-+ return size;
-+}
-+
-+static DEVICE_ATTR(fade, 0644, led_fade_show, led_fade_store);
-+
-+static ssize_t led_duty_cycle_show(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct led_classdev *led_cdev = dev_get_drvdata(dev);
-+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
-+
-+ return sprintf(buf, "%u\n", rt->duty_cycle);
-+}
-+
-+static ssize_t led_duty_cycle_store(struct device *dev,
-+ struct device_attribute *attr, const char *buf, size_t size)
-+{
-+ struct led_classdev *led_cdev = dev_get_drvdata(dev);
-+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
-+ unsigned long state;
-+ ssize_t ret = -EINVAL;
-+
-+ ret = kstrtoul(buf, 10, &state);
-+ if (ret)
-+ return ret;
-+
-+ if (state <= 100)
-+ rt->duty_cycle = state;
-+ else
-+ rt->duty_cycle = 100;
-+
-+ rt->fade = 0;
-+
-+ return size;
-+}
-+
-+static DEVICE_ATTR(duty_cycle, 0644, led_duty_cycle_show, led_duty_cycle_store);
-+
-+static void rt_timer_trig_activate(struct led_classdev *led_cdev)
-+{
-+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
-+ struct rt_timer_gpio *gpio_data;
-+ int rc;
-+
-+ led_cdev->trigger_data = NULL;
-+ gpio_data = kzalloc(sizeof(*gpio_data), GFP_KERNEL);
-+ if (!gpio_data)
-+ return;
-+
-+ rc = device_create_file(led_cdev->dev, &dev_attr_duty_cycle);
-+ if (rc)
-+ goto err_gpio;
-+ rc = device_create_file(led_cdev->dev, &dev_attr_fade);
-+ if (rc)
-+ goto err_out_duty_cycle;
-+
-+ led_cdev->activated = true;
-+ led_cdev->trigger_data = gpio_data;
-+ gpio_data->led = led_cdev;
-+ list_add(&gpio_data->list, &rt->gpios);
-+ led_cdev->trigger_data = gpio_data;
-+ rt_timer_enable(rt);
-+ return;
-+
-+err_out_duty_cycle:
-+ device_remove_file(led_cdev->dev, &dev_attr_duty_cycle);
-+
-+err_gpio:
-+ kfree(gpio_data);
-+}
-+
-+static void rt_timer_trig_deactivate(struct led_classdev *led_cdev)
-+{
-+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
-+ struct rt_timer_gpio *gpio_data = (struct rt_timer_gpio*) led_cdev->trigger_data;
-+
-+ if (led_cdev->activated) {
-+ device_remove_file(led_cdev->dev, &dev_attr_duty_cycle);
-+ device_remove_file(led_cdev->dev, &dev_attr_fade);
-+ led_cdev->activated = false;
-+ }
-+
-+ list_del(&gpio_data->list);
-+ rt_timer_disable(rt);
-+ led_set_brightness(led_cdev, LED_OFF);
-+}
-+
- static int rt_timer_probe(struct platform_device *pdev)
- {
- struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ const __be32 *divisor;
- struct rt_timer *rt;
- struct clk *clk;
-+ int ret;
-
- rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL);
- if (!rt) {
-@@ -140,12 +303,29 @@ static int rt_timer_probe(struct platfor
- if (!rt->timer_freq)
- return -EINVAL;
-
-+ rt->duty_cycle = 100;
- rt->dev = &pdev->dev;
- platform_set_drvdata(pdev, rt);
-
-- rt_timer_request(rt);
-- rt_timer_config(rt, 2);
-- rt_timer_enable(rt);
-+ ret = rt_timer_request(rt);
-+ if (ret)
-+ return ret;
-+
-+ divisor = of_get_property(pdev->dev.of_node, "ralink,divisor", NULL);
-+ if (divisor)
-+ rt_timer_config(rt, be32_to_cpu(*divisor));
-+ else
-+ rt_timer_config(rt, 200);
-+
-+ rt->led_trigger.name = "pwmtimer",
-+ rt->led_trigger.activate = rt_timer_trig_activate,
-+ rt->led_trigger.deactivate = rt_timer_trig_deactivate,
-+
-+ ret = led_trigger_register(&rt->led_trigger);
-+ if (ret)
-+ return ret;
-+
-+ INIT_LIST_HEAD(&rt->gpios);
-
- dev_info(&pdev->dev, "maximum frequncy is %luHz\n", rt->timer_freq);
-
-@@ -156,6 +336,7 @@ static int rt_timer_remove(struct platfo
- {
- struct rt_timer *rt = platform_get_drvdata(pdev);
-
-+ led_trigger_unregister(&rt->led_trigger);
- rt_timer_disable(rt);
- rt_timer_free(rt);
-
-@@ -180,6 +361,6 @@ static struct platform_driver rt_timer_d
-
- module_platform_driver(rt_timer_driver);
-
--MODULE_DESCRIPTION("Ralink RT2880 timer");
-+MODULE_DESCRIPTION("Ralink RT2880 timer / pseudo pwm");
- MODULE_AUTHOR("John Crispin <blogic@openwrt.org");
- MODULE_LICENSE("GPL");
+++ /dev/null
-From f57edea9db0f7f437bc4f2ae408f6dd8bfbb9062 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 16 Mar 2014 04:53:02 +0000
-Subject: [PATCH 110/133] MIPS: ralink: add a helper for reading the ECO
- version
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/mach-ralink/mt7620.h | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -79,4 +79,9 @@
- #define MT7620_GPIO_MODE_EPHY BIT(15)
- #define MT7620_GPIO_MODE_WDT BIT(22)
-
-+static inline int mt7620_get_eco(void)
-+{
-+ return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
-+}
-+
- #endif
+++ /dev/null
-From 2d7e32d4825e20e9db4f0dff6b3e3c25c8c7ad7d Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Tue, 3 Dec 2013 17:05:05 +0100
-Subject: [PATCH 111/133] DMA: ralink: add rt2880 dma engine
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/dma/Kconfig | 6 +
- drivers/dma/Makefile | 1 +
- drivers/dma/dmaengine.c | 26 ++
- drivers/dma/ralink-gdma.c | 577 +++++++++++++++++++++++++++++++++++++++++++++
- include/linux/dmaengine.h | 1 +
- 5 files changed, 611 insertions(+)
- create mode 100644 drivers/dma/ralink-gdma.c
-
---- a/drivers/dma/Kconfig
-+++ b/drivers/dma/Kconfig
-@@ -312,6 +312,12 @@ config MMP_PDMA
- help
- Support the MMP PDMA engine for PXA and MMP platfrom.
-
-+config DMA_RALINK
-+ tristate "RALINK DMA support"
-+ depends on RALINK && SOC_MT7620
-+ select DMA_ENGINE
-+ select DMA_VIRTUAL_CHANNELS
-+
- config DMA_ENGINE
- bool
-
---- a/drivers/dma/Makefile
-+++ b/drivers/dma/Makefile
-@@ -38,3 +38,4 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
- obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
- obj-$(CONFIG_DMA_OMAP) += omap-dma.o
- obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
-+obj-$(CONFIG_DMA_RALINK) += ralink-gdma.o
---- a/drivers/dma/dmaengine.c
-+++ b/drivers/dma/dmaengine.c
-@@ -504,6 +504,32 @@ static struct dma_chan *private_candidat
- }
-
- /**
-+ * dma_request_slave_channel - try to get specific channel exclusively
-+ * @chan: target channel
-+ */
-+struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
-+{
-+ int err = -EBUSY;
-+
-+ /* lock against __dma_request_channel */
-+ mutex_lock(&dma_list_mutex);
-+
-+ if (chan->client_count == 0) {
-+ err = dma_chan_get(chan);
-+ if (err)
-+ pr_debug("%s: failed to get %s: (%d)\n",
-+ __func__, dma_chan_name(chan), err);
-+ } else
-+ chan = NULL;
-+
-+ mutex_unlock(&dma_list_mutex);
-+
-+ return chan;
-+}
-+EXPORT_SYMBOL_GPL(dma_get_slave_channel);
-+
-+
-+/**
- * dma_request_channel - try to allocate an exclusive channel
- * @mask: capabilities that the channel must satisfy
- * @fn: optional callback to disposition available channels
---- /dev/null
-+++ b/drivers/dma/ralink-gdma.c
-@@ -0,0 +1,577 @@
-+/*
-+ * Copyright (C) 2013, Lars-Peter Clausen <lars@metafoo.de>
-+ * GDMA4740 DMAC support
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ */
-+
-+#include <linux/dmaengine.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/err.h>
-+#include <linux/init.h>
-+#include <linux/list.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/spinlock.h>
-+#include <linux/irq.h>
-+#include <linux/of_dma.h>
-+
-+#include "virt-dma.h"
-+
-+#define GDMA_NR_CHANS 16
-+
-+#define GDMA_REG_SRC_ADDR(x) (0x00 + (x) * 0x10)
-+#define GDMA_REG_DST_ADDR(x) (0x04 + (x) * 0x10)
-+
-+#define GDMA_REG_CTRL0(x) (0x08 + (x) * 0x10)
-+#define GDMA_REG_CTRL0_TX_MASK 0xffff
-+#define GDMA_REG_CTRL0_TX_SHIFT 16
-+#define GDMA_REG_CTRL0_CURR_MASK 0xff
-+#define GDMA_REG_CTRL0_CURR_SHIFT 8
-+#define GDMA_REG_CTRL0_SRC_ADDR_FIXED BIT(7)
-+#define GDMA_REG_CTRL0_DST_ADDR_FIXED BIT(6)
-+#define GDMA_REG_CTRL0_BURST_MASK 0x7
-+#define GDMA_REG_CTRL0_BURST_SHIFT 3
-+#define GDMA_REG_CTRL0_DONE_INT BIT(2)
-+#define GDMA_REG_CTRL0_ENABLE BIT(1)
-+#define GDMA_REG_CTRL0_HW_MODE 0
-+
-+#define GDMA_REG_CTRL1(x) (0x0c + (x) * 0x10)
-+#define GDMA_REG_CTRL1_SEG_MASK 0xf
-+#define GDMA_REG_CTRL1_SEG_SHIFT 22
-+#define GDMA_REG_CTRL1_REQ_MASK 0x3f
-+#define GDMA_REG_CTRL1_SRC_REQ_SHIFT 16
-+#define GDMA_REG_CTRL1_DST_REQ_SHIFT 8
-+#define GDMA_REG_CTRL1_CONTINOUS BIT(14)
-+#define GDMA_REG_CTRL1_NEXT_MASK 0x1f
-+#define GDMA_REG_CTRL1_NEXT_SHIFT 3
-+#define GDMA_REG_CTRL1_COHERENT BIT(2)
-+#define GDMA_REG_CTRL1_FAIL BIT(1)
-+#define GDMA_REG_CTRL1_MASK BIT(0)
-+
-+#define GDMA_REG_UNMASK_INT 0x200
-+#define GDMA_REG_DONE_INT 0x204
-+
-+#define GDMA_REG_GCT 0x220
-+#define GDMA_REG_GCT_CHAN_MASK 0x3
-+#define GDMA_REG_GCT_CHAN_SHIFT 3
-+#define GDMA_REG_GCT_VER_MASK 0x3
-+#define GDMA_REG_GCT_VER_SHIFT 1
-+#define GDMA_REG_GCT_ARBIT_RR BIT(0)
-+
-+enum gdma_dma_transfer_size {
-+ GDMA_TRANSFER_SIZE_4BYTE = 0,
-+ GDMA_TRANSFER_SIZE_8BYTE = 1,
-+ GDMA_TRANSFER_SIZE_16BYTE = 2,
-+ GDMA_TRANSFER_SIZE_32BYTE = 3,
-+};
-+
-+struct gdma_dma_sg {
-+ dma_addr_t addr;
-+ unsigned int len;
-+};
-+
-+struct gdma_dma_desc {
-+ struct virt_dma_desc vdesc;
-+
-+ enum dma_transfer_direction direction;
-+ bool cyclic;
-+
-+ unsigned int num_sgs;
-+ struct gdma_dma_sg sg[];
-+};
-+
-+struct gdma_dmaengine_chan {
-+ struct virt_dma_chan vchan;
-+ unsigned int id;
-+
-+ dma_addr_t fifo_addr;
-+ unsigned int transfer_shift;
-+
-+ struct gdma_dma_desc *desc;
-+ unsigned int next_sg;
-+};
-+
-+struct gdma_dma_dev {
-+ struct dma_device ddev;
-+ void __iomem *base;
-+ struct clk *clk;
-+
-+ struct gdma_dmaengine_chan chan[GDMA_NR_CHANS];
-+};
-+
-+static struct gdma_dma_dev *gdma_dma_chan_get_dev(
-+ struct gdma_dmaengine_chan *chan)
-+{
-+ return container_of(chan->vchan.chan.device, struct gdma_dma_dev,
-+ ddev);
-+}
-+
-+static struct gdma_dmaengine_chan *to_gdma_dma_chan(struct dma_chan *c)
-+{
-+ return container_of(c, struct gdma_dmaengine_chan, vchan.chan);
-+}
-+
-+static struct gdma_dma_desc *to_gdma_dma_desc(struct virt_dma_desc *vdesc)
-+{
-+ return container_of(vdesc, struct gdma_dma_desc, vdesc);
-+}
-+
-+static inline uint32_t gdma_dma_read(struct gdma_dma_dev *dma_dev,
-+ unsigned int reg)
-+{
-+ return readl(dma_dev->base + reg);
-+}
-+
-+static inline void gdma_dma_write(struct gdma_dma_dev *dma_dev,
-+ unsigned reg, uint32_t val)
-+{
-+ //printk("gdma --> %p = 0x%08X\n", dma_dev->base + reg, val);
-+ writel(val, dma_dev->base + reg);
-+}
-+
-+static inline void gdma_dma_write_mask(struct gdma_dma_dev *dma_dev,
-+ unsigned int reg, uint32_t val, uint32_t mask)
-+{
-+ uint32_t tmp;
-+
-+ tmp = gdma_dma_read(dma_dev, reg);
-+ tmp &= ~mask;
-+ tmp |= val;
-+ gdma_dma_write(dma_dev, reg, tmp);
-+}
-+
-+static struct gdma_dma_desc *gdma_dma_alloc_desc(unsigned int num_sgs)
-+{
-+ return kzalloc(sizeof(struct gdma_dma_desc) +
-+ sizeof(struct gdma_dma_sg) * num_sgs, GFP_ATOMIC);
-+}
-+
-+static enum gdma_dma_transfer_size gdma_dma_maxburst(u32 maxburst)
-+{
-+ if (maxburst <= 7)
-+ return GDMA_TRANSFER_SIZE_4BYTE;
-+ else if (maxburst <= 15)
-+ return GDMA_TRANSFER_SIZE_8BYTE;
-+ else if (maxburst <= 31)
-+ return GDMA_TRANSFER_SIZE_16BYTE;
-+
-+ return GDMA_TRANSFER_SIZE_32BYTE;
-+}
-+
-+static int gdma_dma_slave_config(struct dma_chan *c,
-+ const struct dma_slave_config *config)
-+{
-+ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
-+ struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
-+ enum gdma_dma_transfer_size transfer_size;
-+ uint32_t flags;
-+ uint32_t ctrl0, ctrl1;
-+
-+ switch (config->direction) {
-+ case DMA_MEM_TO_DEV:
-+ ctrl1 = 32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT;
-+ ctrl1 |= config->slave_id << GDMA_REG_CTRL1_DST_REQ_SHIFT;
-+ flags = GDMA_REG_CTRL0_DST_ADDR_FIXED;
-+ transfer_size = gdma_dma_maxburst(config->dst_maxburst);
-+ chan->fifo_addr = config->dst_addr;
-+ break;
-+
-+ case DMA_DEV_TO_MEM:
-+ ctrl1 = config->slave_id << GDMA_REG_CTRL1_SRC_REQ_SHIFT;
-+ ctrl1 |= 32 << GDMA_REG_CTRL1_DST_REQ_SHIFT;
-+ flags = GDMA_REG_CTRL0_SRC_ADDR_FIXED;
-+ transfer_size = gdma_dma_maxburst(config->src_maxburst);
-+ chan->fifo_addr = config->src_addr;
-+ break;
-+
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ chan->transfer_shift = 1 + transfer_size;
-+
-+ ctrl0 = flags | GDMA_REG_CTRL0_HW_MODE;
-+ ctrl0 |= GDMA_REG_CTRL0_DONE_INT;
-+
-+ ctrl1 &= ~(GDMA_REG_CTRL1_NEXT_MASK << GDMA_REG_CTRL1_NEXT_SHIFT);
-+ ctrl1 |= chan->id << GDMA_REG_CTRL1_NEXT_SHIFT;
-+ ctrl1 |= GDMA_REG_CTRL1_FAIL;
-+ ctrl1 &= ~GDMA_REG_CTRL1_CONTINOUS;
-+ gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0);
-+ gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1);
-+
-+ return 0;
-+}
-+
-+static int gdma_dma_terminate_all(struct dma_chan *c)
-+{
-+ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
-+ struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
-+ unsigned long flags;
-+ LIST_HEAD(head);
-+
-+ spin_lock_irqsave(&chan->vchan.lock, flags);
-+ gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id), 0,
-+ GDMA_REG_CTRL0_ENABLE);
-+ chan->desc = NULL;
-+ vchan_get_all_descriptors(&chan->vchan, &head);
-+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
-+
-+ vchan_dma_desc_free_list(&chan->vchan, &head);
-+
-+ return 0;
-+}
-+
-+static int gdma_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
-+ unsigned long arg)
-+{
-+ struct dma_slave_config *config = (struct dma_slave_config *)arg;
-+
-+ switch (cmd) {
-+ case DMA_SLAVE_CONFIG:
-+ return gdma_dma_slave_config(chan, config);
-+ case DMA_TERMINATE_ALL:
-+ return gdma_dma_terminate_all(chan);
-+ default:
-+ return -ENOSYS;
-+ }
-+}
-+
-+static int gdma_dma_start_transfer(struct gdma_dmaengine_chan *chan)
-+{
-+ struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
-+ dma_addr_t src_addr, dst_addr;
-+ struct virt_dma_desc *vdesc;
-+ struct gdma_dma_sg *sg;
-+
-+ gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id), 0,
-+ GDMA_REG_CTRL0_ENABLE);
-+
-+ if (!chan->desc) {
-+ vdesc = vchan_next_desc(&chan->vchan);
-+ if (!vdesc)
-+ return 0;
-+ chan->desc = to_gdma_dma_desc(vdesc);
-+ chan->next_sg = 0;
-+ }
-+
-+ if (chan->next_sg == chan->desc->num_sgs)
-+ chan->next_sg = 0;
-+
-+ sg = &chan->desc->sg[chan->next_sg];
-+
-+ if (chan->desc->direction == DMA_MEM_TO_DEV) {
-+ src_addr = sg->addr;
-+ dst_addr = chan->fifo_addr;
-+ } else {
-+ src_addr = chan->fifo_addr;
-+ dst_addr = sg->addr;
-+ }
-+ gdma_dma_write(dma_dev, GDMA_REG_SRC_ADDR(chan->id), src_addr);
-+ gdma_dma_write(dma_dev, GDMA_REG_DST_ADDR(chan->id), dst_addr);
-+ gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id),
-+ (sg->len << GDMA_REG_CTRL0_TX_SHIFT) | GDMA_REG_CTRL0_ENABLE,
-+ GDMA_REG_CTRL0_TX_MASK << GDMA_REG_CTRL0_TX_SHIFT);
-+ chan->next_sg++;
-+ gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL1(chan->id), 0, GDMA_REG_CTRL1_MASK);
-+
-+ return 0;
-+}
-+
-+static void gdma_dma_chan_irq(struct gdma_dmaengine_chan *chan)
-+{
-+ spin_lock(&chan->vchan.lock);
-+ if (chan->desc) {
-+ if (chan->desc && chan->desc->cyclic) {
-+ vchan_cyclic_callback(&chan->desc->vdesc);
-+ } else {
-+ if (chan->next_sg == chan->desc->num_sgs) {
-+ chan->desc = NULL;
-+ vchan_cookie_complete(&chan->desc->vdesc);
-+ }
-+ }
-+ }
-+ gdma_dma_start_transfer(chan);
-+ spin_unlock(&chan->vchan.lock);
-+}
-+
-+static irqreturn_t gdma_dma_irq(int irq, void *devid)
-+{
-+ struct gdma_dma_dev *dma_dev = devid;
-+ uint32_t unmask, done;
-+ unsigned int i;
-+
-+ unmask = gdma_dma_read(dma_dev, GDMA_REG_UNMASK_INT);
-+ gdma_dma_write(dma_dev, GDMA_REG_UNMASK_INT, unmask);
-+ done = gdma_dma_read(dma_dev, GDMA_REG_DONE_INT);
-+
-+ for (i = 0; i < GDMA_NR_CHANS; ++i)
-+ if (done & BIT(i))
-+ gdma_dma_chan_irq(&dma_dev->chan[i]);
-+ gdma_dma_write(dma_dev, GDMA_REG_DONE_INT, done);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static void gdma_dma_issue_pending(struct dma_chan *c)
-+{
-+ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&chan->vchan.lock, flags);
-+ if (vchan_issue_pending(&chan->vchan) && !chan->desc)
-+ gdma_dma_start_transfer(chan);
-+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
-+}
-+
-+static struct dma_async_tx_descriptor *gdma_dma_prep_slave_sg(
-+ struct dma_chan *c, struct scatterlist *sgl,
-+ unsigned int sg_len, enum dma_transfer_direction direction,
-+ unsigned long flags, void *context)
-+{
-+ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
-+ struct gdma_dma_desc *desc;
-+ struct scatterlist *sg;
-+ unsigned int i;
-+
-+ desc = gdma_dma_alloc_desc(sg_len);
-+ if (!desc)
-+ return NULL;
-+
-+ for_each_sg(sgl, sg, sg_len, i) {
-+ desc->sg[i].addr = sg_dma_address(sg);
-+ desc->sg[i].len = sg_dma_len(sg);
-+ }
-+
-+ desc->num_sgs = sg_len;
-+ desc->direction = direction;
-+ desc->cyclic = false;
-+
-+ return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
-+}
-+
-+static struct dma_async_tx_descriptor *gdma_dma_prep_dma_cyclic(
-+ struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
-+ size_t period_len, enum dma_transfer_direction direction,
-+ unsigned long flags, void *context)
-+{
-+ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
-+ struct gdma_dma_desc *desc;
-+ unsigned int num_periods, i;
-+
-+ if (buf_len % period_len)
-+ return NULL;
-+
-+ num_periods = buf_len / period_len;
-+
-+ desc = gdma_dma_alloc_desc(num_periods);
-+ if (!desc)
-+ return NULL;
-+
-+ for (i = 0; i < num_periods; i++) {
-+ desc->sg[i].addr = buf_addr;
-+ desc->sg[i].len = period_len;
-+ buf_addr += period_len;
-+ }
-+
-+ desc->num_sgs = num_periods;
-+ desc->direction = direction;
-+ desc->cyclic = true;
-+
-+ return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
-+}
-+
-+static size_t gdma_dma_desc_residue(struct gdma_dmaengine_chan *chan,
-+ struct gdma_dma_desc *desc, unsigned int next_sg)
-+{
-+ struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
-+ unsigned int residue, count;
-+ unsigned int i;
-+
-+ residue = 0;
-+
-+ for (i = next_sg; i < desc->num_sgs; i++)
-+ residue += desc->sg[i].len;
-+
-+ if (next_sg != 0) {
-+ count = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id));
-+ count >>= GDMA_REG_CTRL0_CURR_SHIFT;
-+ count &= GDMA_REG_CTRL0_CURR_MASK;
-+ residue += count << chan->transfer_shift;
-+ }
-+
-+ return residue;
-+}
-+
-+static enum dma_status gdma_dma_tx_status(struct dma_chan *c,
-+ dma_cookie_t cookie, struct dma_tx_state *state)
-+{
-+ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
-+ struct virt_dma_desc *vdesc;
-+ enum dma_status status;
-+ unsigned long flags;
-+
-+ status = dma_cookie_status(c, cookie, state);
-+ if (status == DMA_SUCCESS || !state)
-+ return status;
-+
-+ spin_lock_irqsave(&chan->vchan.lock, flags);
-+ vdesc = vchan_find_desc(&chan->vchan, cookie);
-+ if (cookie == chan->desc->vdesc.tx.cookie) {
-+ state->residue = gdma_dma_desc_residue(chan, chan->desc,
-+ chan->next_sg);
-+ } else if (vdesc) {
-+ state->residue = gdma_dma_desc_residue(chan,
-+ to_gdma_dma_desc(vdesc), 0);
-+ } else {
-+ state->residue = 0;
-+ }
-+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
-+
-+ return status;
-+}
-+
-+static int gdma_dma_alloc_chan_resources(struct dma_chan *c)
-+{
-+ return 0;
-+}
-+
-+static void gdma_dma_free_chan_resources(struct dma_chan *c)
-+{
-+ vchan_free_chan_resources(to_virt_chan(c));
-+}
-+
-+static void gdma_dma_desc_free(struct virt_dma_desc *vdesc)
-+{
-+ kfree(container_of(vdesc, struct gdma_dma_desc, vdesc));
-+}
-+
-+static struct dma_chan *
-+of_dma_xlate_by_chan_id(struct of_phandle_args *dma_spec,
-+ struct of_dma *ofdma)
-+{
-+ struct gdma_dma_dev *dma_dev = ofdma->of_dma_data;
-+ unsigned int request = dma_spec->args[0];
-+
-+ if (request >= GDMA_NR_CHANS)
-+ return NULL;
-+
-+ return dma_get_slave_channel(&(dma_dev->chan[request].vchan.chan));
-+}
-+
-+static int gdma_dma_probe(struct platform_device *pdev)
-+{
-+ struct gdma_dmaengine_chan *chan;
-+ struct gdma_dma_dev *dma_dev;
-+ struct dma_device *dd;
-+ unsigned int i;
-+ struct resource *res;
-+ uint32_t gct;
-+ int ret;
-+ int irq;
-+
-+
-+ dma_dev = devm_kzalloc(&pdev->dev, sizeof(*dma_dev), GFP_KERNEL);
-+ if (!dma_dev)
-+ return -EINVAL;
-+
-+ dd = &dma_dev->ddev;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ dma_dev->base = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(dma_dev->base))
-+ return PTR_ERR(dma_dev->base);
-+
-+ dma_cap_set(DMA_SLAVE, dd->cap_mask);
-+ dma_cap_set(DMA_CYCLIC, dd->cap_mask);
-+ dd->device_alloc_chan_resources = gdma_dma_alloc_chan_resources;
-+ dd->device_free_chan_resources = gdma_dma_free_chan_resources;
-+ dd->device_tx_status = gdma_dma_tx_status;
-+ dd->device_issue_pending = gdma_dma_issue_pending;
-+ dd->device_prep_slave_sg = gdma_dma_prep_slave_sg;
-+ dd->device_prep_dma_cyclic = gdma_dma_prep_dma_cyclic;
-+ dd->device_control = gdma_dma_control;
-+ dd->dev = &pdev->dev;
-+ dd->chancnt = GDMA_NR_CHANS;
-+ INIT_LIST_HEAD(&dd->channels);
-+
-+ for (i = 0; i < dd->chancnt; i++) {
-+ chan = &dma_dev->chan[i];
-+ chan->id = i;
-+ chan->vchan.desc_free = gdma_dma_desc_free;
-+ vchan_init(&chan->vchan, dd);
-+ }
-+
-+ ret = dma_async_device_register(dd);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_dma_controller_register(pdev->dev.of_node,
-+ of_dma_xlate_by_chan_id, dma_dev);
-+ if (ret)
-+ goto err_unregister;
-+
-+ irq = platform_get_irq(pdev, 0);
-+ ret = request_irq(irq, gdma_dma_irq, 0, dev_name(&pdev->dev), dma_dev);
-+ if (ret)
-+ goto err_unregister;
-+
-+ gdma_dma_write(dma_dev, GDMA_REG_UNMASK_INT, 0);
-+ gdma_dma_write(dma_dev, GDMA_REG_DONE_INT, BIT(dd->chancnt) - 1);
-+
-+ gct = gdma_dma_read(dma_dev, GDMA_REG_GCT);
-+ dev_info(&pdev->dev, "revision: %d, channels: %d\n",
-+ (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
-+ 8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) & GDMA_REG_GCT_CHAN_MASK));
-+ platform_set_drvdata(pdev, dma_dev);
-+
-+ gdma_dma_write(dma_dev, GDMA_REG_GCT, GDMA_REG_GCT_ARBIT_RR);
-+
-+ return 0;
-+
-+err_unregister:
-+ dma_async_device_unregister(dd);
-+ return ret;
-+}
-+
-+static int gdma_dma_remove(struct platform_device *pdev)
-+{
-+ struct gdma_dma_dev *dma_dev = platform_get_drvdata(pdev);
-+ int irq = platform_get_irq(pdev, 0);
-+
-+ free_irq(irq, dma_dev);
-+ of_dma_controller_free(pdev->dev.of_node);
-+ dma_async_device_unregister(&dma_dev->ddev);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id gdma_of_match_table[] = {
-+ { .compatible = "ralink,rt2880-gdma" },
-+ { },
-+};
-+
-+static struct platform_driver gdma_dma_driver = {
-+ .probe = gdma_dma_probe,
-+ .remove = gdma_dma_remove,
-+ .driver = {
-+ .name = "gdma-rt2880",
-+ .owner = THIS_MODULE,
-+ .of_match_table = gdma_of_match_table,
-+ },
-+};
-+module_platform_driver(gdma_dma_driver);
-+
-+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
-+MODULE_DESCRIPTION("GDMA4740 DMA driver");
-+MODULE_LICENSE("GPLv2");
---- a/include/linux/dmaengine.h
-+++ b/include/linux/dmaengine.h
-@@ -999,6 +999,7 @@ static inline void dma_release_channel(s
- int dma_async_device_register(struct dma_device *device);
- void dma_async_device_unregister(struct dma_device *device);
- void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
-+struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
- struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
- struct dma_chan *net_dma_find_channel(void);
- #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
+++ /dev/null
-From d4398d880eba386cb85d0a1a2ba39a336876dc0a Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Tue, 3 Dec 2013 20:18:13 +0100
-Subject: [PATCH 112/133] asoc: add mt7620 support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/of.c | 2 +
- sound/soc/Kconfig | 1 +
- sound/soc/Makefile | 1 +
- sound/soc/ralink/Kconfig | 15 ++
- sound/soc/ralink/Makefile | 11 +
- sound/soc/ralink/mt7620-i2s.c | 466 ++++++++++++++++++++++++++++++++++++++
- sound/soc/ralink/mt7620-wm8960.c | 125 ++++++++++
- sound/soc/soc-io.c | 10 -
- 8 files changed, 621 insertions(+), 10 deletions(-)
- create mode 100644 sound/soc/ralink/Kconfig
- create mode 100644 sound/soc/ralink/Makefile
- create mode 100644 sound/soc/ralink/mt7620-i2s.c
- create mode 100644 sound/soc/ralink/mt7620-wm8960.c
-
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -15,6 +15,7 @@
- #include <linux/of_fdt.h>
- #include <linux/kernel.h>
- #include <linux/bootmem.h>
-+#include <linux/module.h>
- #include <linux/of_platform.h>
- #include <linux/of_address.h>
-
-@@ -25,6 +26,7 @@
- #include "common.h"
-
- __iomem void *rt_sysc_membase;
-+EXPORT_SYMBOL(rt_sysc_membase);
- __iomem void *rt_memc_membase;
-
- extern struct boot_param_header __dtb_start;
---- a/sound/soc/Kconfig
-+++ b/sound/soc/Kconfig
-@@ -48,6 +48,7 @@ source "sound/soc/kirkwood/Kconfig"
- source "sound/soc/mid-x86/Kconfig"
- source "sound/soc/mxs/Kconfig"
- source "sound/soc/pxa/Kconfig"
-+source "sound/soc/ralink/Kconfig"
- source "sound/soc/samsung/Kconfig"
- source "sound/soc/s6000/Kconfig"
- source "sound/soc/sh/Kconfig"
---- a/sound/soc/Makefile
-+++ b/sound/soc/Makefile
-@@ -26,6 +26,7 @@ obj-$(CONFIG_SND_SOC) += nuc900/
- obj-$(CONFIG_SND_SOC) += omap/
- obj-$(CONFIG_SND_SOC) += kirkwood/
- obj-$(CONFIG_SND_SOC) += pxa/
-+obj-$(CONFIG_SND_SOC) += ralink/
- obj-$(CONFIG_SND_SOC) += samsung/
- obj-$(CONFIG_SND_SOC) += s6000/
- obj-$(CONFIG_SND_SOC) += sh/
---- /dev/null
-+++ b/sound/soc/ralink/Kconfig
-@@ -0,0 +1,15 @@
-+config SND_MT7620_SOC_I2S
-+ depends on SOC_MT7620 && SND_SOC
-+ select SND_SOC_GENERIC_DMAENGINE_PCM
-+ tristate "SoC Audio (I2S protocol) for Ralink MT7620 SoC"
-+ help
-+ Say Y if you want to use I2S protocol and I2S codec on Ingenic MT7620
-+ based boards.
-+
-+config SND_MT7620_SOC_WM8960
-+ tristate "SoC Audio support for Ralink WM8960"
-+ select SND_MT7620_SOC_I2S
-+ select SND_SOC_WM8960
-+ help
-+ Say Y if you want to add support for ASoC audio on the Qi LB60 board
-+ a.k.a Qi Ben NanoNote.
---- /dev/null
-+++ b/sound/soc/ralink/Makefile
-@@ -0,0 +1,11 @@
-+#
-+# Jz4740 Platform Support
-+#
-+snd-soc-mt7620-i2s-objs := mt7620-i2s.o
-+
-+obj-$(CONFIG_SND_MT7620_SOC_I2S) += snd-soc-mt7620-i2s.o
-+
-+# Jz4740 Machine Support
-+snd-soc-mt7620-wm8960-objs := mt7620-wm8960.o
-+
-+obj-$(CONFIG_SND_MT7620_SOC_WM8960) += snd-soc-mt7620-wm8960.o
---- /dev/null
-+++ b/sound/soc/ralink/mt7620-i2s.c
-@@ -0,0 +1,466 @@
-+/*
-+ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+
-+#include <linux/delay.h>
-+
-+#include <linux/dma-mapping.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/initval.h>
-+#include <sound/dmaengine_pcm.h>
-+
-+#include <ralink_regs.h>
-+
-+#define I2S_REG_CFG0 0x00
-+#define I2S_REG_CFG0_EN BIT(31)
-+#define I2S_REG_CFG0_DMA_EN BIT(30)
-+#define I2S_REG_CFG0_BYTE_SWAP BIT(28)
-+#define I2S_REG_CFG0_TX_EN BIT(24)
-+#define I2S_REG_CFG0_RX_EN BIT(20)
-+#define I2S_REG_CFG0_SLAVE BIT(16)
-+#define I2S_REG_CFG0_RX_THRES 12
-+#define I2S_REG_CFG0_TX_THRES 4
-+#define I2S_REG_CFG0_DFT_THRES (4 << I2S_REG_CFG0_RX_THRES) | \
-+ (4 << I2S_REG_CFG0_TX_THRES)
-+
-+#define I2S_REG_INT_STATUS 0x04
-+#define I2S_REG_INT_EN 0x08
-+#define I2S_REG_FF_STATUS 0x0c
-+#define I2S_REG_WREG 0x10
-+#define I2S_REG_RREG 0x14
-+#define I2S_REG_CFG1 0x18
-+
-+#define I2S_REG_DIVCMP 0x20
-+#define I2S_REG_DIVINT 0x24
-+#define I2S_REG_CLK_EN BIT(31)
-+
-+struct mt7620_i2s {
-+ struct resource *mem;
-+ void __iomem *base;
-+ dma_addr_t phys_base;
-+
-+ struct snd_dmaengine_dai_dma_data playback_dma_data;
-+ struct snd_dmaengine_dai_dma_data capture_dma_data;
-+};
-+
-+static inline uint32_t mt7620_i2s_read(const struct mt7620_i2s *i2s,
-+ unsigned int reg)
-+{
-+ return readl(i2s->base + reg);
-+}
-+
-+static inline void mt7620_i2s_write(const struct mt7620_i2s *i2s,
-+ unsigned int reg, uint32_t value)
-+{
-+ //printk("i2s --> %p = 0x%08X\n", i2s->base + reg, value);
-+ writel(value, i2s->base + reg);
-+}
-+
-+static int mt7620_i2s_startup(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+ uint32_t cfg;
-+
-+ if (dai->active)
-+ return 0;
-+
-+ cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
-+ cfg |= I2S_REG_CFG0_EN;
-+ mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
-+
-+ return 0;
-+}
-+
-+static void mt7620_i2s_shutdown(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+ uint32_t cfg;
-+
-+ if (dai->active)
-+ return;
-+
-+ cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
-+ cfg &= ~I2S_REG_CFG0_EN;
-+ mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
-+}
-+
-+static int mt7620_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
-+ struct snd_soc_dai *dai)
-+{
-+ struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+
-+ uint32_t cfg;
-+ uint32_t mask;
-+
-+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-+ mask = I2S_REG_CFG0_TX_EN;
-+ else
-+ mask = I2S_REG_CFG0_RX_EN;
-+
-+ cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
-+
-+ switch (cmd) {
-+ case SNDRV_PCM_TRIGGER_START:
-+ case SNDRV_PCM_TRIGGER_RESUME:
-+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-+ cfg |= mask;
-+ break;
-+ case SNDRV_PCM_TRIGGER_STOP:
-+ case SNDRV_PCM_TRIGGER_SUSPEND:
-+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-+ cfg &= ~mask;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ if (cfg & (I2S_REG_CFG0_TX_EN | I2S_REG_CFG0_RX_EN))
-+ cfg |= I2S_REG_CFG0_DMA_EN;
-+ else
-+ cfg &= ~I2S_REG_CFG0_DMA_EN;
-+
-+ mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
-+
-+ return 0;
-+}
-+
-+static int mt7620_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
-+{
-+ struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+ uint32_t cfg;
-+
-+ cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
-+
-+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
-+ case SND_SOC_DAIFMT_CBS_CFS:
-+ cfg |= I2S_REG_CFG0_SLAVE;
-+ break;
-+ case SND_SOC_DAIFMT_CBM_CFM:
-+ cfg &= ~I2S_REG_CFG0_SLAVE;
-+ break;
-+ case SND_SOC_DAIFMT_CBM_CFS:
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
-+ case SND_SOC_DAIFMT_I2S:
-+ case SND_SOC_DAIFMT_MSB:
-+ cfg &= ~I2S_REG_CFG0_BYTE_SWAP;
-+ break;
-+ case SND_SOC_DAIFMT_LSB:
-+ cfg |= I2S_REG_CFG0_BYTE_SWAP;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
-+ case SND_SOC_DAIFMT_NB_NF:
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
-+
-+ return 0;
-+}
-+
-+static int mt7620_i2s_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
-+{
-+
-+ return 0;
-+}
-+
-+unsigned long i2sMaster_inclk_int[11] = {
-+ 78, 56, 52, 39, 28, 26, 19, 14, 13, 9, 6};
-+unsigned long i2sMaster_inclk_comp[11] = {
-+ 64, 352, 42, 32, 176, 21, 272, 88, 10, 455, 261};
-+
-+
-+static int mt7620_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
-+ unsigned int freq, int dir)
-+{
-+ struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+
-+ printk("Internal REFCLK with fractional division\n");
-+
-+ mt7620_i2s_write(i2s, I2S_REG_DIVINT, i2sMaster_inclk_int[7]);
-+ mt7620_i2s_write(i2s, I2S_REG_DIVCMP,
-+ i2sMaster_inclk_comp[7] | I2S_REG_CLK_EN);
-+
-+/* struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+ struct clk *parent;
-+ int ret = 0;
-+
-+ switch (clk_id) {
-+ case JZ4740_I2S_CLKSRC_EXT:
-+ parent = clk_get(NULL, "ext");
-+ clk_set_parent(i2s->clk_i2s, parent);
-+ break;
-+ case JZ4740_I2S_CLKSRC_PLL:
-+ parent = clk_get(NULL, "pll half");
-+ clk_set_parent(i2s->clk_i2s, parent);
-+ ret = clk_set_rate(i2s->clk_i2s, freq);
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+ clk_put(parent);
-+
-+ return ret;*/
-+ return 0;
-+}
-+
-+static int mt7620_i2s_suspend(struct snd_soc_dai *dai)
-+{
-+ struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+ uint32_t cfg;
-+
-+ if (dai->active) {
-+ cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
-+ cfg &= ~I2S_REG_CFG0_TX_EN;
-+ mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
-+ }
-+
-+ return 0;
-+}
-+
-+static int mt7620_i2s_resume(struct snd_soc_dai *dai)
-+{
-+ struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+ uint32_t cfg;
-+
-+ if (dai->active) {
-+ cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
-+ cfg |= I2S_REG_CFG0_TX_EN;
-+ mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
-+ }
-+
-+ return 0;
-+}
-+
-+static void mt7620_i2c_init_pcm_config(struct mt7620_i2s *i2s)
-+{
-+ struct snd_dmaengine_dai_dma_data *dma_data;
-+
-+ /* Playback */
-+ dma_data = &i2s->playback_dma_data;
-+ dma_data->maxburst = 16;
-+ dma_data->slave_id = 2; //JZ4740_DMA_TYPE_AIC_TRANSMIT;
-+ dma_data->addr = i2s->phys_base + I2S_REG_WREG;
-+
-+ /* Capture */
-+ dma_data = &i2s->capture_dma_data;
-+ dma_data->maxburst = 16;
-+ dma_data->slave_id = 3; //JZ4740_DMA_TYPE_AIC_RECEIVE;
-+ dma_data->addr = i2s->phys_base + I2S_REG_RREG;
-+}
-+
-+static int mt7620_i2s_dai_probe(struct snd_soc_dai *dai)
-+{
-+ struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+ uint32_t data;
-+
-+ mt7620_i2c_init_pcm_config(i2s);
-+ dai->playback_dma_data = &i2s->playback_dma_data;
-+ dai->capture_dma_data = &i2s->capture_dma_data;
-+
-+ /* set share pins to i2s/gpio mode and i2c mode */
-+ data = rt_sysc_r32(0x60);
-+ data &= 0xFFFFFFE2;
-+ data |= 0x00000018;
-+ rt_sysc_w32(data, 0x60);
-+
-+ printk("Internal REFCLK with fractional division\n");
-+
-+ mt7620_i2s_write(i2s, I2S_REG_CFG0, I2S_REG_CFG0_DFT_THRES);
-+ mt7620_i2s_write(i2s, I2S_REG_CFG1, 0);
-+ mt7620_i2s_write(i2s, I2S_REG_INT_EN, 0);
-+
-+ mt7620_i2s_write(i2s, I2S_REG_DIVINT, i2sMaster_inclk_int[7]);
-+ mt7620_i2s_write(i2s, I2S_REG_DIVCMP,
-+ i2sMaster_inclk_comp[7] | I2S_REG_CLK_EN);
-+
-+ return 0;
-+}
-+
-+static int mt7620_i2s_dai_remove(struct snd_soc_dai *dai)
-+{
-+ return 0;
-+}
-+
-+static const struct snd_soc_dai_ops mt7620_i2s_dai_ops = {
-+ .startup = mt7620_i2s_startup,
-+ .shutdown = mt7620_i2s_shutdown,
-+ .trigger = mt7620_i2s_trigger,
-+ .hw_params = mt7620_i2s_hw_params,
-+ .set_fmt = mt7620_i2s_set_fmt,
-+ .set_sysclk = mt7620_i2s_set_sysclk,
-+};
-+
-+#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
-+ SNDRV_PCM_FMTBIT_S16_LE)
-+
-+static struct snd_soc_dai_driver mt7620_i2s_dai = {
-+ .probe = mt7620_i2s_dai_probe,
-+ .remove = mt7620_i2s_dai_remove,
-+ .playback = {
-+ .channels_min = 1,
-+ .channels_max = 2,
-+ .rates = SNDRV_PCM_RATE_8000_48000,
-+ .formats = JZ4740_I2S_FMTS,
-+ },
-+ .capture = {
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = SNDRV_PCM_RATE_8000_48000,
-+ .formats = JZ4740_I2S_FMTS,
-+ },
-+ .symmetric_rates = 1,
-+ .ops = &mt7620_i2s_dai_ops,
-+ .suspend = mt7620_i2s_suspend,
-+ .resume = mt7620_i2s_resume,
-+};
-+
-+static const struct snd_pcm_hardware mt7620_pcm_hardware = {
-+ .info = SNDRV_PCM_INFO_MMAP |
-+ SNDRV_PCM_INFO_MMAP_VALID |
-+ SNDRV_PCM_INFO_INTERLEAVED |
-+ SNDRV_PCM_INFO_BLOCK_TRANSFER,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
-+ .period_bytes_min = PAGE_SIZE,
-+ .period_bytes_max = 64 * 1024,
-+ .periods_min = 2,
-+ .periods_max = 128,
-+ .buffer_bytes_max = 128 * 1024,
-+ .fifo_size = 32,
-+};
-+
-+static const struct snd_dmaengine_pcm_config mt7620_dmaengine_pcm_config = {
-+ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
-+ .pcm_hardware = &mt7620_pcm_hardware,
-+ .prealloc_buffer_size = 256 * PAGE_SIZE,
-+};
-+
-+static const struct snd_soc_component_driver mt7620_i2s_component = {
-+ .name = "mt7620-i2s",
-+};
-+
-+static int mt7620_i2s_dev_probe(struct platform_device *pdev)
-+{
-+ struct mt7620_i2s *i2s;
-+ int ret;
-+
-+ snd_dmaengine_pcm_register(&pdev->dev,
-+ &mt7620_dmaengine_pcm_config,
-+ SND_DMAENGINE_PCM_FLAG_COMPAT);
-+
-+ i2s = kzalloc(sizeof(*i2s), GFP_KERNEL);
-+ if (!i2s)
-+ return -ENOMEM;
-+
-+ i2s->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!i2s->mem) {
-+ ret = -ENOENT;
-+ goto err_free;
-+ }
-+
-+ i2s->mem = request_mem_region(i2s->mem->start, resource_size(i2s->mem),
-+ pdev->name);
-+ if (!i2s->mem) {
-+ ret = -EBUSY;
-+ goto err_free;
-+ }
-+
-+ i2s->base = ioremap_nocache(i2s->mem->start, resource_size(i2s->mem));
-+ if (!i2s->base) {
-+ ret = -EBUSY;
-+ goto err_release_mem_region;
-+ }
-+
-+ i2s->phys_base = i2s->mem->start;
-+
-+ platform_set_drvdata(pdev, i2s);
-+ ret = snd_soc_register_component(&pdev->dev, &mt7620_i2s_component,
-+ &mt7620_i2s_dai, 1);
-+
-+ if (!ret) {
-+ dev_err(&pdev->dev, "loaded\n");
-+ return ret;
-+ }
-+
-+ dev_err(&pdev->dev, "Failed to register DAI\n");
-+ iounmap(i2s->base);
-+
-+err_release_mem_region:
-+ release_mem_region(i2s->mem->start, resource_size(i2s->mem));
-+err_free:
-+ kfree(i2s);
-+
-+ return ret;
-+}
-+
-+static int mt7620_i2s_dev_remove(struct platform_device *pdev)
-+{
-+ struct mt7620_i2s *i2s = platform_get_drvdata(pdev);
-+
-+ snd_soc_unregister_component(&pdev->dev);
-+
-+ iounmap(i2s->base);
-+ release_mem_region(i2s->mem->start, resource_size(i2s->mem));
-+
-+ kfree(i2s);
-+
-+ snd_dmaengine_pcm_unregister(&pdev->dev);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id mt7620_i2s_match[] = {
-+ { .compatible = "ralink,mt7620a-i2s" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, mt7620_i2s_match);
-+
-+static struct platform_driver mt7620_i2s_driver = {
-+ .probe = mt7620_i2s_dev_probe,
-+ .remove = mt7620_i2s_dev_remove,
-+ .driver = {
-+ .name = "mt7620-i2s",
-+ .owner = THIS_MODULE,
-+ .of_match_table = mt7620_i2s_match,
-+ },
-+};
-+
-+module_platform_driver(mt7620_i2s_driver);
-+
-+MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
-+MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:mt7620-i2s");
---- /dev/null
-+++ b/sound/soc/ralink/mt7620-wm8960.c
-@@ -0,0 +1,125 @@
-+/*
-+ * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/of.h>
-+#include <linux/timer.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/soc.h>
-+
-+
-+static const struct snd_soc_dapm_widget mt7620_wm8960_widgets[] = {
-+ SND_SOC_DAPM_SPK("Speaker", NULL),
-+};
-+
-+static const struct snd_soc_dapm_route mt7620_wm8960_routes[] = {
-+ {"Speaker", NULL, "HP_L"},
-+ {"Speaker", NULL, "HP_R"},
-+};
-+
-+#define MT7620_DAIFMT (SND_SOC_DAIFMT_I2S | \
-+ SND_SOC_DAIFMT_NB_NF | \
-+ SND_SOC_DAIFMT_CBM_CFM)
-+
-+static int mt7620_wm8960_codec_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+ struct snd_soc_codec *codec = rtd->codec;
-+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+ struct snd_soc_dapm_context *dapm = &codec->dapm;
-+ int ret;
-+
-+ snd_soc_dapm_enable_pin(dapm, "HP_L");
-+ snd_soc_dapm_enable_pin(dapm, "HP_R");
-+
-+ ret = snd_soc_dai_set_fmt(cpu_dai, MT7620_DAIFMT);
-+ if (ret < 0) {
-+ dev_err(codec->dev, "Failed to set cpu dai format: %d\n", ret);
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static struct snd_soc_dai_link mt7620_wm8960_dai = {
-+ .name = "mt7620",
-+ .stream_name = "mt7620",
-+ .init = mt7620_wm8960_codec_init,
-+ .codec_dai_name = "wm8960-hifi",
-+};
-+
-+static struct snd_soc_card mt7620_wm8960 = {
-+ .name = "mt7620-wm8960",
-+ .owner = THIS_MODULE,
-+ .dai_link = &mt7620_wm8960_dai,
-+ .num_links = 1,
-+
-+ .dapm_widgets = mt7620_wm8960_widgets,
-+ .num_dapm_widgets = ARRAY_SIZE(mt7620_wm8960_widgets),
-+ .dapm_routes = mt7620_wm8960_routes,
-+ .num_dapm_routes = ARRAY_SIZE(mt7620_wm8960_routes),
-+};
-+
-+static int mt7620_wm8960_probe(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ struct snd_soc_card *card = &mt7620_wm8960;
-+ int ret;
-+
-+ card->dev = &pdev->dev;
-+
-+ mt7620_wm8960_dai.cpu_of_node = of_parse_phandle(np, "cpu-dai", 0);
-+ mt7620_wm8960_dai.codec_of_node = of_parse_phandle(np, "codec-dai", 0);
-+ mt7620_wm8960_dai.platform_of_node = mt7620_wm8960_dai.cpu_of_node;
-+
-+ ret = snd_soc_register_card(card);
-+ if (ret) {
-+ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n",
-+ ret);
-+ }
-+ return ret;
-+}
-+
-+static int mt7620_wm8960_remove(struct platform_device *pdev)
-+{
-+ struct snd_soc_card *card = platform_get_drvdata(pdev);
-+
-+ snd_soc_unregister_card(card);
-+ return 0;
-+}
-+
-+static const struct of_device_id mt7620_audio_match[] = {
-+ { .compatible = "ralink,wm8960-audio" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, mt7620_audio_match);
-+
-+static struct platform_driver mt7620_wm8960_driver = {
-+ .driver = {
-+ .name = "wm8960-audio",
-+ .owner = THIS_MODULE,
-+ .of_match_table = mt7620_audio_match,
-+ },
-+ .probe = mt7620_wm8960_probe,
-+ .remove = mt7620_wm8960_remove,
-+};
-+
-+module_platform_driver(mt7620_wm8960_driver);
-+
-+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
-+MODULE_DESCRIPTION("ALSA SoC QI LB60 Audio support");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:qi-lb60-audio");
---- a/sound/soc/soc-io.c
-+++ b/sound/soc/soc-io.c
-@@ -19,7 +19,6 @@
-
- #include <trace/events/asoc.h>
-
--#ifdef CONFIG_REGMAP
- static int hw_write(struct snd_soc_codec *codec, unsigned int reg,
- unsigned int value)
- {
-@@ -161,12 +160,3 @@ int snd_soc_codec_set_cache_io(struct sn
- return PTR_RET(codec->control_data);
- }
- EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
--#else
--int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
-- int addr_bits, int data_bits,
-- enum snd_soc_control_type control)
--{
-- return -ENOTSUPP;
--}
--EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
--#endif
+++ /dev/null
-From 47bbf432252b39361728c7685292dc9f889e6537 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 19 Aug 2013 13:49:52 +0200
-Subject: [PATCH 113/133] pinctrl: ralink: add pinctrl driver
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/Kconfig | 2 +
- arch/mips/include/asm/mach-ralink/mt7620.h | 41 ++-
- arch/mips/include/asm/mach-ralink/pinmux.h | 53 ++++
- arch/mips/include/asm/mach-ralink/rt305x.h | 34 +-
- arch/mips/include/asm/mach-ralink/rt3883.h | 16 +-
- arch/mips/ralink/common.h | 19 --
- arch/mips/ralink/mt7620.c | 161 ++++------
- arch/mips/ralink/rt305x.c | 146 ++++-----
- arch/mips/ralink/rt3883.c | 173 +++--------
- drivers/pinctrl/Kconfig | 5 +
- drivers/pinctrl/Makefile | 1 +
- drivers/pinctrl/pinctrl-rt2880.c | 467 ++++++++++++++++++++++++++++
- 12 files changed, 740 insertions(+), 378 deletions(-)
- create mode 100644 arch/mips/include/asm/mach-ralink/pinmux.h
- create mode 100644 drivers/pinctrl/pinctrl-rt2880.c
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -446,6 +446,8 @@ config RALINK
- select HAVE_MACH_CLKDEV
- select CLKDEV_LOOKUP
- select ARCH_REQUIRE_GPIOLIB
-+ select PINCTRL
-+ select PINCTRL_RT2880
-
- config SGI_IP22
- bool "SGI IP22 (Indy/Indigo2)"
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -56,7 +56,6 @@
- #define MT7620_DDR2_SIZE_MIN 32
- #define MT7620_DDR2_SIZE_MAX 256
-
--#define MT7620_GPIO_MODE_I2C BIT(0)
- #define MT7620_GPIO_MODE_UART0_SHIFT 2
- #define MT7620_GPIO_MODE_UART0_MASK 0x7
- #define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
-@@ -68,16 +67,36 @@
- #define MT7620_GPIO_MODE_GPIO_UARTF 0x5
- #define MT7620_GPIO_MODE_GPIO_I2S 0x6
- #define MT7620_GPIO_MODE_GPIO 0x7
--#define MT7620_GPIO_MODE_UART1 BIT(5)
--#define MT7620_GPIO_MODE_MDIO BIT(8)
--#define MT7620_GPIO_MODE_RGMII1 BIT(9)
--#define MT7620_GPIO_MODE_RGMII2 BIT(10)
--#define MT7620_GPIO_MODE_SPI BIT(11)
--#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
--#define MT7620_GPIO_MODE_WLED BIT(13)
--#define MT7620_GPIO_MODE_JTAG BIT(15)
--#define MT7620_GPIO_MODE_EPHY BIT(15)
--#define MT7620_GPIO_MODE_WDT BIT(22)
-+
-+#define MT7620_GPIO_MODE_NAND 0
-+#define MT7620_GPIO_MODE_SD 1
-+#define MT7620_GPIO_MODE_ND_SD_GPIO 2
-+#define MT7620_GPIO_MODE_ND_SD_MASK 0x3
-+#define MT7620_GPIO_MODE_ND_SD_SHIFT 18
-+
-+#define MT7620_GPIO_MODE_PCIE_RST 0
-+#define MT7620_GPIO_MODE_PCIE_REF 1
-+#define MT7620_GPIO_MODE_PCIE_GPIO 2
-+#define MT7620_GPIO_MODE_PCIE_MASK 0x3
-+#define MT7620_GPIO_MODE_PCIE_SHIFT 16
-+
-+#define MT7620_GPIO_MODE_WDT_RST 0
-+#define MT7620_GPIO_MODE_WDT_REF 1
-+#define MT7620_GPIO_MODE_WDT_GPIO 2
-+#define MT7620_GPIO_MODE_WDT_MASK 0x3
-+#define MT7620_GPIO_MODE_WDT_SHIFT 21
-+
-+#define MT7620_GPIO_MODE_I2C 0
-+#define MT7620_GPIO_MODE_UART1 5
-+#define MT7620_GPIO_MODE_MDIO 8
-+#define MT7620_GPIO_MODE_RGMII1 9
-+#define MT7620_GPIO_MODE_RGMII2 10
-+#define MT7620_GPIO_MODE_SPI 11
-+#define MT7620_GPIO_MODE_SPI_REF_CLK 12
-+#define MT7620_GPIO_MODE_WLED 13
-+#define MT7620_GPIO_MODE_JTAG 15
-+#define MT7620_GPIO_MODE_EPHY 15
-+#define MT7620_GPIO_MODE_PA 20
-
- static inline int mt7620_get_eco(void)
- {
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ralink/pinmux.h
-@@ -0,0 +1,53 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * publishhed by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#ifndef _RT288X_PINMUX_H__
-+#define _RT288X_PINMUX_H__
-+
-+#define FUNC(name, value, pin_first, pin_count) { name, value, pin_first, pin_count }
-+#define GRP(_name, _func, _mask, _shift) \
-+ { .name = _name, .mask = _mask, .shift = _shift, \
-+ .func = _func, .gpio = _mask, \
-+ .func_count = ARRAY_SIZE(_func) }
-+
-+#define GRP_G(_name, _func, _mask, _gpio, _shift) \
-+ { .name = _name, .mask = _mask, .shift = _shift, \
-+ .func = _func, .gpio = _gpio, \
-+ .func_count = ARRAY_SIZE(_func) }
-+
-+struct rt2880_pmx_group;
-+
-+struct rt2880_pmx_func {
-+ const char *name;
-+ const char value;
-+
-+ int pin_first;
-+ int pin_count;
-+ int *pins;
-+
-+ int *groups;
-+ int group_count;
-+
-+ int enabled;
-+};
-+
-+struct rt2880_pmx_group {
-+ const char *name;
-+ int enabled;
-+
-+ const u32 shift;
-+ const char mask;
-+ const char gpio;
-+
-+ struct rt2880_pmx_func *func;
-+ int func_count;
-+};
-+
-+extern struct rt2880_pmx_group *rt2880_pinmux_data;
-+
-+#endif
---- a/arch/mips/include/asm/mach-ralink/rt305x.h
-+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
-@@ -125,24 +125,28 @@ static inline int soc_is_rt5350(void)
- #define RT305X_GPIO_GE0_TXD0 40
- #define RT305X_GPIO_GE0_RXCLK 51
-
--#define RT305X_GPIO_MODE_I2C BIT(0)
--#define RT305X_GPIO_MODE_SPI BIT(1)
- #define RT305X_GPIO_MODE_UART0_SHIFT 2
- #define RT305X_GPIO_MODE_UART0_MASK 0x7
- #define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
--#define RT305X_GPIO_MODE_UARTF 0x0
--#define RT305X_GPIO_MODE_PCM_UARTF 0x1
--#define RT305X_GPIO_MODE_PCM_I2S 0x2
--#define RT305X_GPIO_MODE_I2S_UARTF 0x3
--#define RT305X_GPIO_MODE_PCM_GPIO 0x4
--#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
--#define RT305X_GPIO_MODE_GPIO_I2S 0x6
--#define RT305X_GPIO_MODE_GPIO 0x7
--#define RT305X_GPIO_MODE_UART1 BIT(5)
--#define RT305X_GPIO_MODE_JTAG BIT(6)
--#define RT305X_GPIO_MODE_MDIO BIT(7)
--#define RT305X_GPIO_MODE_SDRAM BIT(8)
--#define RT305X_GPIO_MODE_RGMII BIT(9)
-+#define RT305X_GPIO_MODE_UARTF 0
-+#define RT305X_GPIO_MODE_PCM_UARTF 1
-+#define RT305X_GPIO_MODE_PCM_I2S 2
-+#define RT305X_GPIO_MODE_I2S_UARTF 3
-+#define RT305X_GPIO_MODE_PCM_GPIO 4
-+#define RT305X_GPIO_MODE_GPIO_UARTF 5
-+#define RT305X_GPIO_MODE_GPIO_I2S 6
-+#define RT305X_GPIO_MODE_GPIO 7
-+
-+#define RT305X_GPIO_MODE_I2C 0
-+#define RT305X_GPIO_MODE_SPI 1
-+#define RT305X_GPIO_MODE_UART1 5
-+#define RT305X_GPIO_MODE_JTAG 6
-+#define RT305X_GPIO_MODE_MDIO 7
-+#define RT305X_GPIO_MODE_SDRAM 8
-+#define RT305X_GPIO_MODE_RGMII 9
-+#define RT5350_GPIO_MODE_PHY_LED 14
-+#define RT3352_GPIO_MODE_LNA 18
-+#define RT3352_GPIO_MODE_PA 20
-
- #define RT3352_SYSC_REG_SYSCFG0 0x010
- #define RT3352_SYSC_REG_SYSCFG1 0x014
---- a/arch/mips/include/asm/mach-ralink/rt3883.h
-+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
-@@ -112,8 +112,6 @@
- #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
- #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
-
--#define RT3883_GPIO_MODE_I2C BIT(0)
--#define RT3883_GPIO_MODE_SPI BIT(1)
- #define RT3883_GPIO_MODE_UART0_SHIFT 2
- #define RT3883_GPIO_MODE_UART0_MASK 0x7
- #define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
-@@ -125,11 +123,15 @@
- #define RT3883_GPIO_MODE_GPIO_UARTF 0x5
- #define RT3883_GPIO_MODE_GPIO_I2S 0x6
- #define RT3883_GPIO_MODE_GPIO 0x7
--#define RT3883_GPIO_MODE_UART1 BIT(5)
--#define RT3883_GPIO_MODE_JTAG BIT(6)
--#define RT3883_GPIO_MODE_MDIO BIT(7)
--#define RT3883_GPIO_MODE_GE1 BIT(9)
--#define RT3883_GPIO_MODE_GE2 BIT(10)
-+
-+#define RT3883_GPIO_MODE_I2C 0
-+#define RT3883_GPIO_MODE_SPI 1
-+#define RT3883_GPIO_MODE_UART1 5
-+#define RT3883_GPIO_MODE_JTAG 6
-+#define RT3883_GPIO_MODE_MDIO 7
-+#define RT3883_GPIO_MODE_GE1 9
-+#define RT3883_GPIO_MODE_GE2 10
-+
- #define RT3883_GPIO_MODE_PCI_SHIFT 11
- #define RT3883_GPIO_MODE_PCI_MASK 0x7
- #define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
---- a/arch/mips/ralink/common.h
-+++ b/arch/mips/ralink/common.h
-@@ -11,25 +11,6 @@
-
- #define RAMIPS_SYS_TYPE_LEN 32
-
--struct ralink_pinmux_grp {
-- const char *name;
-- u32 mask;
-- int gpio_first;
-- int gpio_last;
--};
--
--struct ralink_pinmux {
-- struct ralink_pinmux_grp *mode;
-- struct ralink_pinmux_grp *uart;
-- int uart_shift;
-- u32 uart_mask;
-- void (*wdt_reset)(void);
-- struct ralink_pinmux_grp *pci;
-- int pci_shift;
-- u32 pci_mask;
--};
--extern struct ralink_pinmux rt_gpio_pinmux;
--
- struct ralink_soc_info {
- unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
- unsigned char *compatible;
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -17,6 +17,7 @@
- #include <asm/mipsregs.h>
- #include <asm/mach-ralink/ralink_regs.h>
- #include <asm/mach-ralink/mt7620.h>
-+#include <asm/mach-ralink/pinmux.h>
-
- #include "common.h"
-
-@@ -48,118 +49,58 @@ static int dram_type;
- /* the pll dividers */
- static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
-
--static struct ralink_pinmux_grp mode_mux[] = {
-- {
-- .name = "i2c",
-- .mask = MT7620_GPIO_MODE_I2C,
-- .gpio_first = 1,
-- .gpio_last = 2,
-- }, {
-- .name = "spi",
-- .mask = MT7620_GPIO_MODE_SPI,
-- .gpio_first = 3,
-- .gpio_last = 6,
-- }, {
-- .name = "uartlite",
-- .mask = MT7620_GPIO_MODE_UART1,
-- .gpio_first = 15,
-- .gpio_last = 16,
-- }, {
-- .name = "wdt",
-- .mask = MT7620_GPIO_MODE_WDT,
-- .gpio_first = 17,
-- .gpio_last = 17,
-- }, {
-- .name = "mdio",
-- .mask = MT7620_GPIO_MODE_MDIO,
-- .gpio_first = 22,
-- .gpio_last = 23,
-- }, {
-- .name = "rgmii1",
-- .mask = MT7620_GPIO_MODE_RGMII1,
-- .gpio_first = 24,
-- .gpio_last = 35,
-- }, {
-- .name = "spi refclk",
-- .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
-- .gpio_first = 37,
-- .gpio_last = 39,
-- }, {
-- .name = "jtag",
-- .mask = MT7620_GPIO_MODE_JTAG,
-- .gpio_first = 40,
-- .gpio_last = 44,
-- }, {
-- /* shared lines with jtag */
-- .name = "ephy",
-- .mask = MT7620_GPIO_MODE_EPHY,
-- .gpio_first = 40,
-- .gpio_last = 44,
-- }, {
-- .name = "nand",
-- .mask = MT7620_GPIO_MODE_JTAG,
-- .gpio_first = 45,
-- .gpio_last = 59,
-- }, {
-- .name = "rgmii2",
-- .mask = MT7620_GPIO_MODE_RGMII2,
-- .gpio_first = 60,
-- .gpio_last = 71,
-- }, {
-- .name = "wled",
-- .mask = MT7620_GPIO_MODE_WLED,
-- .gpio_first = 72,
-- .gpio_last = 72,
-- }, {0}
-+static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
-+static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
-+static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
-+static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
-+static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
-+static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
-+static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
-+static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
-+static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
-+static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
-+static struct rt2880_pmx_func uartf_grp[] = {
-+ FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
-+ FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
-+ FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
-+ FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
-+ FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
-+ FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
-+ FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
- };
--
--static struct ralink_pinmux_grp uart_mux[] = {
-- {
-- .name = "uartf",
-- .mask = MT7620_GPIO_MODE_UARTF,
-- .gpio_first = 7,
-- .gpio_last = 14,
-- }, {
-- .name = "pcm uartf",
-- .mask = MT7620_GPIO_MODE_PCM_UARTF,
-- .gpio_first = 7,
-- .gpio_last = 14,
-- }, {
-- .name = "pcm i2s",
-- .mask = MT7620_GPIO_MODE_PCM_I2S,
-- .gpio_first = 7,
-- .gpio_last = 14,
-- }, {
-- .name = "i2s uartf",
-- .mask = MT7620_GPIO_MODE_I2S_UARTF,
-- .gpio_first = 7,
-- .gpio_last = 14,
-- }, {
-- .name = "pcm gpio",
-- .mask = MT7620_GPIO_MODE_PCM_GPIO,
-- .gpio_first = 11,
-- .gpio_last = 14,
-- }, {
-- .name = "gpio uartf",
-- .mask = MT7620_GPIO_MODE_GPIO_UARTF,
-- .gpio_first = 7,
-- .gpio_last = 10,
-- }, {
-- .name = "gpio i2s",
-- .mask = MT7620_GPIO_MODE_GPIO_I2S,
-- .gpio_first = 7,
-- .gpio_last = 10,
-- }, {
-- .name = "gpio",
-- .mask = MT7620_GPIO_MODE_GPIO,
-- }, {0}
-+static struct rt2880_pmx_func wdt_grp[] = {
-+ FUNC("wdt rst", 0, 17, 1),
-+ FUNC("wdt refclk", 0, 17, 1),
-+ };
-+static struct rt2880_pmx_func pcie_rst_grp[] = {
-+ FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
-+ FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
-+};
-+static struct rt2880_pmx_func nd_sd_grp[] = {
-+ FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
-+ FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
- };
-
--struct ralink_pinmux rt_gpio_pinmux = {
-- .mode = mode_mux,
-- .uart = uart_mux,
-- .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
-- .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
-+static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
-+ GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
-+ GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
-+ MT7620_GPIO_MODE_UART0_SHIFT),
-+ GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
-+ GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
-+ GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
-+ MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
-+ GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
-+ GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
-+ GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
-+ GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
-+ MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
-+ GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
-+ MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
-+ GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
-+ GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
-+ GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
-+ GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
-+ { 0 }
- };
-
- void __init ralink_clk_init(void)
-@@ -286,4 +227,6 @@ void prom_soc_init(struct ralink_soc_inf
- (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
- pr_info("Digital PMU set to %s control\n",
- (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
-+
-+ rt2880_pinmux_data = mt7620a_pinmux_data;
- }
---- a/arch/mips/ralink/rt305x.c
-+++ b/arch/mips/ralink/rt305x.c
-@@ -17,90 +17,71 @@
- #include <asm/mipsregs.h>
- #include <asm/mach-ralink/ralink_regs.h>
- #include <asm/mach-ralink/rt305x.h>
-+#include <asm/mach-ralink/pinmux.h>
-
- #include "common.h"
-
- enum rt305x_soc_type rt305x_soc;
-
--static struct ralink_pinmux_grp mode_mux[] = {
-- {
-- .name = "i2c",
-- .mask = RT305X_GPIO_MODE_I2C,
-- .gpio_first = RT305X_GPIO_I2C_SD,
-- .gpio_last = RT305X_GPIO_I2C_SCLK,
-- }, {
-- .name = "spi",
-- .mask = RT305X_GPIO_MODE_SPI,
-- .gpio_first = RT305X_GPIO_SPI_EN,
-- .gpio_last = RT305X_GPIO_SPI_CLK,
-- }, {
-- .name = "uartlite",
-- .mask = RT305X_GPIO_MODE_UART1,
-- .gpio_first = RT305X_GPIO_UART1_TXD,
-- .gpio_last = RT305X_GPIO_UART1_RXD,
-- }, {
-- .name = "jtag",
-- .mask = RT305X_GPIO_MODE_JTAG,
-- .gpio_first = RT305X_GPIO_JTAG_TDO,
-- .gpio_last = RT305X_GPIO_JTAG_TDI,
-- }, {
-- .name = "mdio",
-- .mask = RT305X_GPIO_MODE_MDIO,
-- .gpio_first = RT305X_GPIO_MDIO_MDC,
-- .gpio_last = RT305X_GPIO_MDIO_MDIO,
-- }, {
-- .name = "sdram",
-- .mask = RT305X_GPIO_MODE_SDRAM,
-- .gpio_first = RT305X_GPIO_SDRAM_MD16,
-- .gpio_last = RT305X_GPIO_SDRAM_MD31,
-- }, {
-- .name = "rgmii",
-- .mask = RT305X_GPIO_MODE_RGMII,
-- .gpio_first = RT305X_GPIO_GE0_TXD0,
-- .gpio_last = RT305X_GPIO_GE0_RXCLK,
-- }, {0}
-+static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
-+static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
-+static struct rt2880_pmx_func uartf_func[] = {
-+ FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
-+ FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
-+ FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
-+ FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
-+ FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
-+ FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
-+ FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
-+};
-+static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
-+static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
-+static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
-+static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
-+static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
-+static struct rt2880_pmx_func rt3352_rgmii_func[] = { FUNC("rgmii", 0, 24, 12) };
-+static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
-+static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
-+static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
-+static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
-+
-+static struct rt2880_pmx_group rt3050_pinmux_data[] = {
-+ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
-+ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
-+ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
-+ RT305X_GPIO_MODE_UART0_SHIFT),
-+ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
-+ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
-+ GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
-+ GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
-+ GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
-+ { 0 }
-+};
-+
-+static struct rt2880_pmx_group rt3352_pinmux_data[] = {
-+ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
-+ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
-+ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
-+ RT305X_GPIO_MODE_UART0_SHIFT),
-+ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
-+ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
-+ GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
-+ GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
-+ GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
-+ GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
-+ GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
-+ { 0 }
- };
-
--static struct ralink_pinmux_grp uart_mux[] = {
-- {
-- .name = "uartf",
-- .mask = RT305X_GPIO_MODE_UARTF,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_14,
-- }, {
-- .name = "pcm uartf",
-- .mask = RT305X_GPIO_MODE_PCM_UARTF,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_14,
-- }, {
-- .name = "pcm i2s",
-- .mask = RT305X_GPIO_MODE_PCM_I2S,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_14,
-- }, {
-- .name = "i2s uartf",
-- .mask = RT305X_GPIO_MODE_I2S_UARTF,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_14,
-- }, {
-- .name = "pcm gpio",
-- .mask = RT305X_GPIO_MODE_PCM_GPIO,
-- .gpio_first = RT305X_GPIO_10,
-- .gpio_last = RT305X_GPIO_14,
-- }, {
-- .name = "gpio uartf",
-- .mask = RT305X_GPIO_MODE_GPIO_UARTF,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_10,
-- }, {
-- .name = "gpio i2s",
-- .mask = RT305X_GPIO_MODE_GPIO_I2S,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_10,
-- }, {
-- .name = "gpio",
-- .mask = RT305X_GPIO_MODE_GPIO,
-- }, {0}
-+static struct rt2880_pmx_group rt5350_pinmux_data[] = {
-+ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
-+ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
-+ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
-+ RT305X_GPIO_MODE_UART0_SHIFT),
-+ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
-+ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
-+ GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
-+ { 0 }
- };
-
- static void rt305x_wdt_reset(void)
-@@ -114,14 +95,6 @@ static void rt305x_wdt_reset(void)
- rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
- }
-
--struct ralink_pinmux rt_gpio_pinmux = {
-- .mode = mode_mux,
-- .uart = uart_mux,
-- .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
-- .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
-- .wdt_reset = rt305x_wdt_reset,
--};
--
- static unsigned long rt5350_get_mem_size(void)
- {
- void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
-@@ -290,11 +263,14 @@ void prom_soc_init(struct ralink_soc_inf
- soc_info->mem_base = RT305X_SDRAM_BASE;
- if (soc_is_rt5350()) {
- soc_info->mem_size = rt5350_get_mem_size();
-+ rt2880_pinmux_data = rt5350_pinmux_data;
- } else if (soc_is_rt305x() || soc_is_rt3350()) {
- soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
- soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
-+ rt2880_pinmux_data = rt3050_pinmux_data;
- } else if (soc_is_rt3352()) {
- soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
- soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
-+ rt2880_pinmux_data = rt3352_pinmux_data;
- }
- }
---- a/arch/mips/ralink/rt3883.c
-+++ b/arch/mips/ralink/rt3883.c
-@@ -17,132 +17,50 @@
- #include <asm/mipsregs.h>
- #include <asm/mach-ralink/ralink_regs.h>
- #include <asm/mach-ralink/rt3883.h>
-+#include <asm/mach-ralink/pinmux.h>
-
- #include "common.h"
-
--static struct ralink_pinmux_grp mode_mux[] = {
-- {
-- .name = "i2c",
-- .mask = RT3883_GPIO_MODE_I2C,
-- .gpio_first = RT3883_GPIO_I2C_SD,
-- .gpio_last = RT3883_GPIO_I2C_SCLK,
-- }, {
-- .name = "spi",
-- .mask = RT3883_GPIO_MODE_SPI,
-- .gpio_first = RT3883_GPIO_SPI_CS0,
-- .gpio_last = RT3883_GPIO_SPI_MISO,
-- }, {
-- .name = "uartlite",
-- .mask = RT3883_GPIO_MODE_UART1,
-- .gpio_first = RT3883_GPIO_UART1_TXD,
-- .gpio_last = RT3883_GPIO_UART1_RXD,
-- }, {
-- .name = "jtag",
-- .mask = RT3883_GPIO_MODE_JTAG,
-- .gpio_first = RT3883_GPIO_JTAG_TDO,
-- .gpio_last = RT3883_GPIO_JTAG_TCLK,
-- }, {
-- .name = "mdio",
-- .mask = RT3883_GPIO_MODE_MDIO,
-- .gpio_first = RT3883_GPIO_MDIO_MDC,
-- .gpio_last = RT3883_GPIO_MDIO_MDIO,
-- }, {
-- .name = "ge1",
-- .mask = RT3883_GPIO_MODE_GE1,
-- .gpio_first = RT3883_GPIO_GE1_TXD0,
-- .gpio_last = RT3883_GPIO_GE1_RXCLK,
-- }, {
-- .name = "ge2",
-- .mask = RT3883_GPIO_MODE_GE2,
-- .gpio_first = RT3883_GPIO_GE2_TXD0,
-- .gpio_last = RT3883_GPIO_GE2_RXCLK,
-- }, {
-- .name = "pci",
-- .mask = RT3883_GPIO_MODE_PCI,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {
-- .name = "lna a",
-- .mask = RT3883_GPIO_MODE_LNA_A,
-- .gpio_first = RT3883_GPIO_LNA_PE_A0,
-- .gpio_last = RT3883_GPIO_LNA_PE_A2,
-- }, {
-- .name = "lna g",
-- .mask = RT3883_GPIO_MODE_LNA_G,
-- .gpio_first = RT3883_GPIO_LNA_PE_G0,
-- .gpio_last = RT3883_GPIO_LNA_PE_G2,
-- }, {0}
-+static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
-+static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
-+static struct rt2880_pmx_func uartf_func[] = {
-+ FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
-+ FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
-+ FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
-+ FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
-+ FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
-+ FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
-+ FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
- };
--
--static struct ralink_pinmux_grp uart_mux[] = {
-- {
-- .name = "uartf",
-- .mask = RT3883_GPIO_MODE_UARTF,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_14,
-- }, {
-- .name = "pcm uartf",
-- .mask = RT3883_GPIO_MODE_PCM_UARTF,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_14,
-- }, {
-- .name = "pcm i2s",
-- .mask = RT3883_GPIO_MODE_PCM_I2S,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_14,
-- }, {
-- .name = "i2s uartf",
-- .mask = RT3883_GPIO_MODE_I2S_UARTF,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_14,
-- }, {
-- .name = "pcm gpio",
-- .mask = RT3883_GPIO_MODE_PCM_GPIO,
-- .gpio_first = RT3883_GPIO_11,
-- .gpio_last = RT3883_GPIO_14,
-- }, {
-- .name = "gpio uartf",
-- .mask = RT3883_GPIO_MODE_GPIO_UARTF,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_10,
-- }, {
-- .name = "gpio i2s",
-- .mask = RT3883_GPIO_MODE_GPIO_I2S,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_10,
-- }, {
-- .name = "gpio",
-- .mask = RT3883_GPIO_MODE_GPIO,
-- }, {0}
-+static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
-+static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
-+static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
-+static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
-+static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
-+static struct rt2880_pmx_func pci_func[] = {
-+ FUNC("pci-dev", 0, 40, 32),
-+ FUNC("pci-host2", 1, 40, 32),
-+ FUNC("pci-host1", 2, 40, 32),
-+ FUNC("pci-fnc", 3, 40, 32)
- };
-+static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
-+static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
-
--static struct ralink_pinmux_grp pci_mux[] = {
-- {
-- .name = "pci-dev",
-- .mask = 0,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {
-- .name = "pci-host2",
-- .mask = 1,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {
-- .name = "pci-host1",
-- .mask = 2,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {
-- .name = "pci-fnc",
-- .mask = 3,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {
-- .name = "pci-gpio",
-- .mask = 7,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {0}
-+static struct rt2880_pmx_group rt3883_pinmux_data[] = {
-+ GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
-+ GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
-+ GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
-+ RT3883_GPIO_MODE_UART0_SHIFT),
-+ GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
-+ GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
-+ GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
-+ GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
-+ GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
-+ GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
-+ RT3883_GPIO_MODE_PCI_SHIFT),
-+ GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
-+ GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
-+ { 0 }
- };
-
- static void rt3883_wdt_reset(void)
-@@ -155,17 +73,6 @@ static void rt3883_wdt_reset(void)
- rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
- }
-
--struct ralink_pinmux rt_gpio_pinmux = {
-- .mode = mode_mux,
-- .uart = uart_mux,
-- .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
-- .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
-- .wdt_reset = rt3883_wdt_reset,
-- .pci = pci_mux,
-- .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
-- .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
--};
--
- void __init ralink_clk_init(void)
- {
- unsigned long cpu_rate, sys_rate;
-@@ -243,4 +150,6 @@ void prom_soc_init(struct ralink_soc_inf
- soc_info->mem_base = RT3883_SDRAM_BASE;
- soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
- soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
-+
-+ rt2880_pinmux_data = rt3883_pinmux_data;
- }
---- a/drivers/pinctrl/Kconfig
-+++ b/drivers/pinctrl/Kconfig
-@@ -114,6 +114,11 @@ config PINCTRL_LANTIQ
- select PINMUX
- select PINCONF
-
-+config PINCTRL_RT2880
-+ bool
-+ depends on RALINK
-+ select PINMUX
-+
- config PINCTRL_FALCON
- bool
- depends on SOC_FALCON
---- a/drivers/pinctrl/Makefile
-+++ b/drivers/pinctrl/Makefile
-@@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinc
- obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
- obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
- obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
-+obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
-
- obj-$(CONFIG_PLAT_ORION) += mvebu/
- obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
---- /dev/null
-+++ b/drivers/pinctrl/pinctrl-rt2880.c
-@@ -0,0 +1,467 @@
-+/*
-+ * linux/drivers/pinctrl/pinctrl-rt2880.c
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * publishhed by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/io.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/of.h>
-+#include <linux/pinctrl/pinctrl.h>
-+#include <linux/pinctrl/pinconf.h>
-+#include <linux/pinctrl/pinmux.h>
-+#include <linux/pinctrl/consumer.h>
-+#include <linux/pinctrl/machine.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+#include <asm/mach-ralink/pinmux.h>
-+#include <asm/mach-ralink/mt7620.h>
-+
-+#include "core.h"
-+
-+#define SYSC_REG_GPIO_MODE 0x60
-+
-+struct rt2880_priv {
-+ struct device *dev;
-+
-+ struct pinctrl_pin_desc *pads;
-+ struct pinctrl_desc *desc;
-+
-+ struct rt2880_pmx_func **func;
-+ int func_count;
-+
-+ struct rt2880_pmx_group *groups;
-+ const char **group_names;
-+ int group_count;
-+
-+ uint8_t *gpio;
-+ int max_pins;
-+};
-+
-+struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
-+
-+static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ return p->group_count;
-+}
-+
-+static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
-+ unsigned group)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ if (group >= p->group_count)
-+ return NULL;
-+
-+ return p->group_names[group];
-+}
-+
-+static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
-+ unsigned group,
-+ const unsigned **pins,
-+ unsigned *num_pins)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ if (group >= p->group_count)
-+ return -EINVAL;
-+
-+ *pins = p->groups[group].func[0].pins;
-+ *num_pins = p->groups[group].func[0].pin_count;
-+
-+ return 0;
-+}
-+
-+static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev,
-+ struct pinctrl_map *map, unsigned num_maps)
-+{
-+ int i;
-+
-+ for (i = 0; i < num_maps; i++)
-+ if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
-+ map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
-+ kfree(map[i].data.configs.configs);
-+ kfree(map);
-+}
-+
-+static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev,
-+ struct seq_file *s,
-+ unsigned offset)
-+{
-+ seq_printf(s, "ralink pio");
-+}
-+
-+static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev,
-+ struct device_node *np,
-+ struct pinctrl_map **map)
-+{
-+ const char *function;
-+ int func = of_property_read_string(np, "ralink,function", &function);
-+ int grps = of_property_count_strings(np, "ralink,group");
-+ int i;
-+
-+ if (func || !grps)
-+ return;
-+
-+ for (i = 0; i < grps; i++) {
-+ const char *group;
-+
-+ of_property_read_string_index(np, "ralink,group", i, &group);
-+
-+ (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
-+ (*map)->name = function;
-+ (*map)->data.mux.group = group;
-+ (*map)->data.mux.function = function;
-+ (*map)++;
-+ }
-+}
-+
-+static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev,
-+ struct device_node *np_config,
-+ struct pinctrl_map **map,
-+ unsigned *num_maps)
-+{
-+ int max_maps = 0;
-+ struct pinctrl_map *tmp;
-+ struct device_node *np;
-+
-+ for_each_child_of_node(np_config, np) {
-+ int ret = of_property_count_strings(np, "ralink,group");
-+
-+ if (ret >= 0)
-+ max_maps += ret;
-+ }
-+
-+ if (!max_maps)
-+ return max_maps;
-+
-+ *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
-+ if (!*map)
-+ return -ENOMEM;
-+
-+ tmp = *map;
-+
-+ for_each_child_of_node(np_config, np)
-+ rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp);
-+ *num_maps = max_maps;
-+
-+ return 0;
-+}
-+
-+static const struct pinctrl_ops rt2880_pctrl_ops = {
-+ .get_groups_count = rt2880_get_group_count,
-+ .get_group_name = rt2880_get_group_name,
-+ .get_group_pins = rt2880_get_group_pins,
-+ .pin_dbg_show = rt2880_pinctrl_pin_dbg_show,
-+ .dt_node_to_map = rt2880_pinctrl_dt_node_to_map,
-+ .dt_free_map = rt2880_pinctrl_dt_free_map,
-+};
-+
-+static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ return p->func_count;
-+}
-+
-+static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
-+ unsigned func)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ return p->func[func]->name;
-+}
-+
-+static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
-+ unsigned func,
-+ const char * const **groups,
-+ unsigned * const num_groups)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ if (p->func[func]->group_count == 1)
-+ *groups = &p->group_names[p->func[func]->groups[0]];
-+ else
-+ *groups = p->group_names;
-+
-+ *num_groups = p->func[func]->group_count;
-+
-+ return 0;
-+}
-+
-+static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
-+ unsigned func,
-+ unsigned group)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+ u32 mode = 0;
-+ int i;
-+
-+ /* dont allow double use */
-+ if (p->groups[group].enabled) {
-+ dev_err(p->dev, "%s is already enabled\n", p->groups[group].name);
-+ return -EBUSY;
-+ }
-+
-+ p->groups[group].enabled = 1;
-+ p->func[func]->enabled = 1;
-+
-+ mode = rt_sysc_r32(SYSC_REG_GPIO_MODE);
-+ mode &= ~(p->groups[group].mask << p->groups[group].shift);
-+
-+ /* mark the pins as gpio */
-+ for (i = 0; i < p->groups[group].func[0].pin_count; i++)
-+ p->gpio[p->groups[group].func[0].pins[i]] = 1;
-+
-+ /* function 0 is gpio and needs special handling */
-+ if (func == 0) {
-+ mode |= p->groups[group].gpio << p->groups[group].shift;
-+ } else {
-+ for (i = 0; i < p->func[func]->pin_count; i++)
-+ p->gpio[p->func[func]->pins[i]] = 0;
-+ mode |= p->func[func]->value << p->groups[group].shift;
-+ }
-+ rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
-+
-+
-+ return 0;
-+}
-+
-+static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
-+ struct pinctrl_gpio_range *range,
-+ unsigned pin)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ if (!p->gpio[pin]) {
-+ dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct pinmux_ops rt2880_pmx_group_ops = {
-+ .get_functions_count = rt2880_pmx_func_count,
-+ .get_function_name = rt2880_pmx_func_name,
-+ .get_function_groups = rt2880_pmx_group_get_groups,
-+ .enable = rt2880_pmx_group_enable,
-+ .gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
-+};
-+
-+static struct pinctrl_desc rt2880_pctrl_desc = {
-+ .owner = THIS_MODULE,
-+ .name = "rt2880-pinmux",
-+ .pctlops = &rt2880_pctrl_ops,
-+ .pmxops = &rt2880_pmx_group_ops,
-+};
-+
-+static struct rt2880_pmx_func gpio_func = {
-+ .name = "gpio",
-+};
-+
-+static int rt2880_pinmux_index(struct rt2880_priv *p)
-+{
-+ struct rt2880_pmx_func **f;
-+ struct rt2880_pmx_group *mux = p->groups;
-+ int i, j, c = 0;
-+
-+ /* count the mux functions */
-+ while (mux->name) {
-+ p->group_count++;
-+ mux++;
-+ }
-+
-+ /* allocate the group names array needed by the gpio function */
-+ p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL);
-+ if (!p->group_names)
-+ return -1;
-+
-+ for (i = 0; i < p->group_count; i++) {
-+ p->group_names[i] = p->groups[i].name;
-+ p->func_count += p->groups[i].func_count;
-+ }
-+
-+ /* we have a dummy function[0] for gpio */
-+ p->func_count++;
-+
-+ /* allocate our function and group mapping index buffers */
-+ f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL);
-+ gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL);
-+ if (!f || !gpio_func.groups)
-+ return -1;
-+
-+ /* add a backpointer to the function so it knows its group */
-+ gpio_func.group_count = p->group_count;
-+ for (i = 0; i < gpio_func.group_count; i++)
-+ gpio_func.groups[i] = i;
-+
-+ f[c] = &gpio_func;
-+ c++;
-+
-+ /* add remaining functions */
-+ for (i = 0; i < p->group_count; i++) {
-+ for (j = 0; j < p->groups[i].func_count; j++) {
-+ f[c] = &p->groups[i].func[j];
-+ f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL);
-+ f[c]->groups[0] = i;
-+ f[c]->group_count = 1;
-+ c++;
-+ }
-+ }
-+ return 0;
-+}
-+
-+static int rt2880_pinmux_pins(struct rt2880_priv *p)
-+{
-+ int i, j;
-+
-+ /* loop over the functions and initialize the pins array. also work out the highest pin used */
-+ for (i = 0; i < p->func_count; i++) {
-+ int pin;
-+
-+ if (!p->func[i]->pin_count)
-+ continue;
-+
-+ p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL);
-+ for (j = 0; j < p->func[i]->pin_count; j++)
-+ p->func[i]->pins[j] = p->func[i]->pin_first + j;
-+
-+ pin = p->func[i]->pin_first + p->func[i]->pin_count;
-+ if (pin > p->max_pins)
-+ p->max_pins = pin;
-+ }
-+
-+ /* the buffer that tells us which pins are gpio */
-+ p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins,
-+ GFP_KERNEL);
-+ /* the pads needed to tell pinctrl about our pins */
-+ p->pads = devm_kzalloc(p->dev,
-+ sizeof(struct pinctrl_pin_desc) * p->max_pins,
-+ GFP_KERNEL);
-+ if (!p->pads || !p->gpio ) {
-+ dev_err(p->dev, "Failed to allocate gpio data\n");
-+ return -ENOMEM;
-+ }
-+
-+ memset(p->gpio, 1, sizeof(uint8_t) * p->max_pins);
-+ for (i = 0; i < p->func_count; i++) {
-+ if (!p->func[i]->pin_count)
-+ continue;
-+
-+ for (j = 0; j < p->func[i]->pin_count; j++)
-+ p->gpio[p->func[i]->pins[j]] = 0;
-+ }
-+
-+ /* pin 0 is always a gpio */
-+ p->gpio[0] = 1;
-+
-+ /* set the pads */
-+ for (i = 0; i < p->max_pins; i++) {
-+ /* strlen("ioXY") + 1 = 5 */
-+ char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
-+
-+ if (!name) {
-+ dev_err(p->dev, "Failed to allocate pad name\n");
-+ return -ENOMEM;
-+ }
-+ snprintf(name, 5, "io%d", i);
-+ p->pads[i].number = i;
-+ p->pads[i].name = name;
-+ }
-+ p->desc->pins = p->pads;
-+ p->desc->npins = p->max_pins;
-+
-+ return 0;
-+}
-+
-+static int rt2880_pinmux_probe(struct platform_device *pdev)
-+{
-+ struct rt2880_priv *p;
-+ struct pinctrl_dev *dev;
-+ struct device_node *np;
-+
-+ if (!rt2880_pinmux_data)
-+ return -ENOSYS;
-+
-+ /* setup the private data */
-+ p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
-+ if (!p)
-+ return -ENOMEM;
-+
-+ p->dev = &pdev->dev;
-+ p->desc = &rt2880_pctrl_desc;
-+ p->groups = rt2880_pinmux_data;
-+ platform_set_drvdata(pdev, p);
-+
-+ /* init the device */
-+ if (rt2880_pinmux_index(p)) {
-+ dev_err(&pdev->dev, "failed to load index\n");
-+ return -EINVAL;
-+ }
-+ if (rt2880_pinmux_pins(p)) {
-+ dev_err(&pdev->dev, "failed to load pins\n");
-+ return -EINVAL;
-+ }
-+ dev = pinctrl_register(p->desc, &pdev->dev, p);
-+ if (IS_ERR(dev))
-+ return PTR_ERR(dev);
-+
-+ /* finalize by adding gpio ranges for enables gpio controllers */
-+ for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") {
-+ const __be32 *ngpio, *gpiobase;
-+ struct pinctrl_gpio_range *range;
-+ char *name;
-+
-+ if (!of_device_is_available(np))
-+ continue;
-+
-+ ngpio = of_get_property(np, "ralink,num-gpios", NULL);
-+ gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
-+ if (!ngpio || !gpiobase) {
-+ dev_err(&pdev->dev, "failed to load chip info\n");
-+ return -EINVAL;
-+ }
-+
-+ range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL);
-+ range->name = name = (char *) &range[1];
-+ sprintf(name, "pio");
-+ range->npins = __be32_to_cpu(*ngpio);
-+ range->base = __be32_to_cpu(*gpiobase);
-+ range->pin_base = range->base;
-+ pinctrl_add_gpio_range(dev, range);
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id rt2880_pinmux_match[] = {
-+ { .compatible = "ralink,rt2880-pinmux" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, rt2880_pinmux_match);
-+
-+static struct platform_driver rt2880_pinmux_driver = {
-+ .probe = rt2880_pinmux_probe,
-+ .driver = {
-+ .name = "rt2880-pinmux",
-+ .owner = THIS_MODULE,
-+ .of_match_table = rt2880_pinmux_match,
-+ },
-+};
-+
-+int __init rt2880_pinmux_init(void)
-+{
-+ return platform_driver_register(&rt2880_pinmux_driver);
-+}
-+
-+core_initcall_sync(rt2880_pinmux_init);
+++ /dev/null
-From b7040c3ad7b8daf8309d083e9248cfa577075cfb Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 21 Mar 2013 18:27:29 +0100
-Subject: [PATCH 114/133] PCI: MIPS: adds rt2880 pci support
-
-Add support for the pci found on the rt2880 SoC.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/pci/Makefile | 1 +
- arch/mips/pci/pci-rt2880.c | 281 ++++++++++++++++++++++++++++++++++++++++++++
- arch/mips/ralink/Kconfig | 1 +
- 3 files changed, 283 insertions(+)
- create mode 100644 arch/mips/pci/pci-rt2880.c
-
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
- obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
- obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
- obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
-+obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
- obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
- obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
- obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
---- /dev/null
-+++ b/arch/mips/pci/pci-rt2880.c
-@@ -0,0 +1,281 @@
-+/*
-+ * Ralink RT288x SoC PCI register definitions
-+ *
-+ * Copyright (C) 2009 John Crispin <blogic@openwrt.org>
-+ * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
-+ *
-+ * Parts of this file are based on Ralink's 2.6.21 BSP
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/pci.h>
-+#include <linux/io.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_pci.h>
-+
-+#include <asm/mach-ralink/rt288x.h>
-+
-+#define RT2880_PCI_BASE 0x00440000
-+#define RT288X_CPU_IRQ_PCI 4
-+
-+#define RT2880_PCI_MEM_BASE 0x20000000
-+#define RT2880_PCI_MEM_SIZE 0x10000000
-+#define RT2880_PCI_IO_BASE 0x00460000
-+#define RT2880_PCI_IO_SIZE 0x00010000
-+
-+#define RT2880_PCI_REG_PCICFG_ADDR 0x00
-+#define RT2880_PCI_REG_PCIMSK_ADDR 0x0c
-+#define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10
-+#define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18
-+#define RT2880_PCI_REG_CONFIG_ADDR 0x20
-+#define RT2880_PCI_REG_CONFIG_DATA 0x24
-+#define RT2880_PCI_REG_MEMBASE 0x28
-+#define RT2880_PCI_REG_IOBASE 0x2c
-+#define RT2880_PCI_REG_ID 0x30
-+#define RT2880_PCI_REG_CLASS 0x34
-+#define RT2880_PCI_REG_SUBID 0x38
-+#define RT2880_PCI_REG_ARBCTL 0x80
-+
-+static void __iomem *rt2880_pci_base;
-+static DEFINE_SPINLOCK(rt2880_pci_lock);
-+
-+static u32 rt2880_pci_reg_read(u32 reg)
-+{
-+ return readl(rt2880_pci_base + reg);
-+}
-+
-+static void rt2880_pci_reg_write(u32 val, u32 reg)
-+{
-+ writel(val, rt2880_pci_base + reg);
-+}
-+
-+static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
-+ unsigned int func, unsigned int where)
-+{
-+ return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
-+ 0x80000000);
-+}
-+
-+static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 *val)
-+{
-+ unsigned long flags;
-+ u32 address;
-+ u32 data;
-+
-+ address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
-+ PCI_FUNC(devfn), where);
-+
-+ spin_lock_irqsave(&rt2880_pci_lock, flags);
-+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
-+ data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
-+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
-+
-+ switch (size) {
-+ case 1:
-+ *val = (data >> ((where & 3) << 3)) & 0xff;
-+ break;
-+ case 2:
-+ *val = (data >> ((where & 3) << 3)) & 0xffff;
-+ break;
-+ case 4:
-+ *val = data;
-+ break;
-+ }
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 val)
-+{
-+ unsigned long flags;
-+ u32 address;
-+ u32 data;
-+
-+ address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
-+ PCI_FUNC(devfn), where);
-+
-+ spin_lock_irqsave(&rt2880_pci_lock, flags);
-+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
-+ data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
-+
-+ switch (size) {
-+ case 1:
-+ data = (data & ~(0xff << ((where & 3) << 3))) |
-+ (val << ((where & 3) << 3));
-+ break;
-+ case 2:
-+ data = (data & ~(0xffff << ((where & 3) << 3))) |
-+ (val << ((where & 3) << 3));
-+ break;
-+ case 4:
-+ data = val;
-+ break;
-+ }
-+
-+ rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
-+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static struct pci_ops rt2880_pci_ops = {
-+ .read = rt2880_pci_config_read,
-+ .write = rt2880_pci_config_write,
-+};
-+
-+static struct resource rt2880_pci_mem_resource = {
-+ .name = "PCI MEM space",
-+ .start = RT2880_PCI_MEM_BASE,
-+ .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct resource rt2880_pci_io_resource = {
-+ .name = "PCI IO space",
-+ .start = RT2880_PCI_IO_BASE,
-+ .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
-+ .flags = IORESOURCE_IO,
-+};
-+
-+static struct pci_controller rt2880_pci_controller = {
-+ .pci_ops = &rt2880_pci_ops,
-+ .mem_resource = &rt2880_pci_mem_resource,
-+ .io_resource = &rt2880_pci_io_resource,
-+};
-+
-+static inline u32 rt2880_pci_read_u32(unsigned long reg)
-+{
-+ unsigned long flags;
-+ u32 address;
-+ u32 ret;
-+
-+ address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
-+
-+ spin_lock_irqsave(&rt2880_pci_lock, flags);
-+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
-+ ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
-+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
-+
-+ return ret;
-+}
-+
-+static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
-+{
-+ unsigned long flags;
-+ u32 address;
-+
-+ address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
-+
-+ spin_lock_irqsave(&rt2880_pci_lock, flags);
-+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
-+ rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
-+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
-+}
-+
-+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ u16 cmd;
-+ int irq = -1;
-+
-+ if (dev->bus->number != 0)
-+ return irq;
-+
-+ switch (PCI_SLOT(dev->devfn)) {
-+ case 0x00:
-+ rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
-+ (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
-+ break;
-+ case 0x11:
-+ irq = RT288X_CPU_IRQ_PCI;
-+ break;
-+ default:
-+ printk("%s:%s[%d] trying to alloc unknown pci irq\n",
-+ __FILE__, __func__, __LINE__);
-+ BUG();
-+ break;
-+ }
-+
-+ pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
-+ pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
-+ pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
-+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
-+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
-+ PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
-+ pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
-+ pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
-+ dev->irq);
-+ return irq;
-+}
-+
-+static int rt288x_pci_probe(struct platform_device *pdev)
-+{
-+ void __iomem *io_map_base;
-+ int i;
-+
-+ rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
-+
-+ io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
-+ rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
-+ set_io_port_base((unsigned long) io_map_base);
-+
-+ ioport_resource.start = RT2880_PCI_IO_BASE;
-+ ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
-+
-+ rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
-+ for(i = 0; i < 0xfffff; i++) {}
-+
-+ rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
-+ rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
-+ rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
-+ rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
-+ rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
-+ rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
-+ rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
-+ rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
-+ rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
-+
-+ rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
-+ (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
-+
-+ register_pci_controller(&rt2880_pci_controller);
-+ return 0;
-+}
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+ return 0;
-+}
-+
-+static const struct of_device_id rt288x_pci_match[] = {
-+ { .compatible = "ralink,rt288x-pci" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, rt288x_pci_match);
-+
-+static struct platform_driver rt288x_pci_driver = {
-+ .probe = rt288x_pci_probe,
-+ .driver = {
-+ .name = "rt288x-pci",
-+ .owner = THIS_MODULE,
-+ .of_match_table = rt288x_pci_match,
-+ },
-+};
-+
-+int __init pcibios_init(void)
-+{
-+ int ret = platform_driver_register(&rt288x_pci_driver);
-+ if (ret)
-+ pr_info("rt288x-pci: Error registering platform driver!");
-+ return ret;
-+}
-+
-+arch_initcall(pcibios_init);
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -15,6 +15,7 @@ choice
-
- config SOC_RT288X
- bool "RT288x"
-+ select HW_HAS_PCI
-
- config SOC_RT305X
- bool "RT305x"
+++ /dev/null
-From 686f5642c74323f7e7eafb93c2b85df589cbf66e Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sat, 18 May 2013 22:06:15 +0200
-Subject: [PATCH 115/133] PCI: MIPS: adds mt7620a pcie driver
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/pci/Makefile | 1 +
- arch/mips/pci/pci-mt7620a.c | 363 +++++++++++++++++++++++++++++++++++++++++++
- arch/mips/ralink/Kconfig | 1 +
- 3 files changed, 365 insertions(+)
- create mode 100644 arch/mips/pci/pci-mt7620a.c
-
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
- obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
- obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
- obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
-+obj-$(CONFIG_SOC_MT7620) += pci-mt7620a.o
- obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
- obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
- obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
---- /dev/null
-+++ b/arch/mips/pci/pci-mt7620a.c
-@@ -0,0 +1,363 @@
-+/*
-+ * Ralink MT7620A SoC PCI support
-+ *
-+ * Copyright (C) 2007-2013 Bruce Chang
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/pci.h>
-+#include <linux/io.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_pci.h>
-+#include <linux/reset.h>
-+#include <linux/platform_device.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+
-+#define RALINK_PCI_MM_MAP_BASE 0x20000000
-+#define RALINK_PCI_IO_MAP_BASE 0x10160000
-+
-+#define RALINK_INT_PCIE0 4
-+#define RALINK_SYSTEM_CONTROL_BASE 0xb0000000
-+#define RALINK_SYSCFG1 0x14
-+#define RALINK_CLKCFG1 0x30
-+#define RALINK_GPIOMODE 0x60
-+#define RALINK_PCIE_CLK_GEN 0x7c
-+#define RALINK_PCIE_CLK_GEN1 0x80
-+#define PCIEPHY0_CFG 0x90
-+#define PPLL_CFG1 0x9c
-+#define PPLL_DRV 0xa0
-+#define RALINK_PCI_HOST_MODE_EN (1<<7)
-+#define RALINK_PCIE_RC_MODE_EN (1<<8)
-+#define RALINK_PCIE_RST (1<<23)
-+#define RALINK_PCI_RST (1<<24)
-+#define RALINK_PCI_CLK_EN (1<<19)
-+#define RALINK_PCIE_CLK_EN (1<<21)
-+#define PCI_SLOTx2 (1<<11)
-+#define PCI_SLOTx1 (2<<11)
-+#define PDRV_SW_SET (1<<31)
-+#define LC_CKDRVPD_ (1<<19)
-+
-+#define RALINK_PCI_CONFIG_ADDR 0x20
-+#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
-+#define MEMORY_BASE 0x0
-+#define RALINK_PCIE0_RST (1<<26)
-+#define RALINK_PCI_BASE 0xB0140000
-+#define RALINK_PCI_MEMBASE 0x28
-+#define RALINK_PCI_IOBASE 0x2C
-+
-+#define RT6855_PCIE0_OFFSET 0x2000
-+
-+#define RALINK_PCI_PCICFG_ADDR 0x00
-+#define RALINK_PCI0_BAR0SETUP_ADDR 0x10
-+#define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
-+#define RALINK_PCI0_ID 0x30
-+#define RALINK_PCI0_CLASS 0x34
-+#define RALINK_PCI0_SUBID 0x38
-+#define RALINK_PCI0_STATUS 0x50
-+#define RALINK_PCI_PCIMSK_ADDR 0x0C
-+
-+#define RALINK_PCIE0_CLK_EN (1 << 26)
-+
-+#define BUSY 0x80000000
-+#define WAITRETRY_MAX 10
-+#define WRITE_MODE (1UL << 23)
-+#define DATA_SHIFT 0
-+#define ADDR_SHIFT 8
-+
-+
-+static void __iomem *bridge_base;
-+static void __iomem *pcie_base;
-+
-+static struct reset_control *rstpcie0;
-+
-+static inline void bridge_w32(u32 val, unsigned reg)
-+{
-+ iowrite32(val, bridge_base + reg);
-+}
-+
-+static inline u32 bridge_r32(unsigned reg)
-+{
-+ return ioread32(bridge_base + reg);
-+}
-+
-+static inline void pcie_w32(u32 val, unsigned reg)
-+{
-+ iowrite32(val, pcie_base + reg);
-+}
-+
-+static inline u32 pcie_r32(unsigned reg)
-+{
-+ return ioread32(pcie_base + reg);
-+}
-+
-+static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
-+{
-+ u32 val = pcie_r32(reg);
-+ val &= ~clr;
-+ val |= set;
-+ pcie_w32(val, reg);
-+}
-+
-+int wait_pciephy_busy(void)
-+{
-+ unsigned long reg_value = 0x0, retry = 0;
-+
-+ while (1) {
-+ //reg_value = rareg(READMODE, PCIEPHY0_CFG, 0);
-+ reg_value = pcie_r32(PCIEPHY0_CFG);
-+
-+ if (reg_value & BUSY)
-+ mdelay(100);
-+ else
-+ break;
-+ if (retry++ > WAITRETRY_MAX){
-+ printk("PCIE-PHY retry failed.\n");
-+ return -1;
-+ }
-+ }
-+ return 0;
-+}
-+
-+static void pcie_phy(unsigned long addr, unsigned long val)
-+{
-+ wait_pciephy_busy();
-+ pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
-+ mdelay(1);
-+ wait_pciephy_busy();
-+}
-+
-+static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
-+{
-+ unsigned int slot = PCI_SLOT(devfn);
-+ u8 func = PCI_FUNC(devfn);
-+ u32 address;
-+ u32 data;
-+
-+ address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
-+ bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
-+ data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
-+
-+ switch (size) {
-+ case 1:
-+ *val = (data >> ((where & 3) << 3)) & 0xff;
-+ break;
-+ case 2:
-+ *val = (data >> ((where & 3) << 3)) & 0xffff;
-+ break;
-+ case 4:
-+ *val = data;
-+ break;
-+ }
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
-+{
-+ unsigned int slot = PCI_SLOT(devfn);
-+ u8 func = PCI_FUNC(devfn);
-+ u32 address;
-+ u32 data;
-+
-+ address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
-+ bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
-+ data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
-+
-+ switch (size) {
-+ case 1:
-+ data = (data & ~(0xff << ((where & 3) << 3))) |
-+ (val << ((where & 3) << 3));
-+ break;
-+ case 2:
-+ data = (data & ~(0xffff << ((where & 3) << 3))) |
-+ (val << ((where & 3) << 3));
-+ break;
-+ case 4:
-+ data = val;
-+ break;
-+ }
-+
-+ bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+struct pci_ops mt7620a_pci_ops= {
-+ .read = pci_config_read,
-+ .write = pci_config_write,
-+};
-+
-+static struct resource mt7620a_res_pci_mem1 = {
-+ .name = "pci memory",
-+ .start = RALINK_PCI_MM_MAP_BASE,
-+ .end = (u32) ((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
-+ .flags = IORESOURCE_MEM,
-+};
-+static struct resource mt7620a_res_pci_io1 = {
-+ .name = "pci io",
-+ .start = RALINK_PCI_IO_MAP_BASE,
-+ .end = (u32) ((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
-+ .flags = IORESOURCE_IO,
-+};
-+
-+struct pci_controller mt7620a_controller = {
-+ .pci_ops = &mt7620a_pci_ops,
-+ .mem_resource = &mt7620a_res_pci_mem1,
-+ .io_resource = &mt7620a_res_pci_io1,
-+ .mem_offset = 0x00000000UL,
-+ .io_offset = 0x00000000UL,
-+ .io_map_base = 0xa0000000,
-+};
-+
-+static int mt7620a_pci_probe(struct platform_device *pdev)
-+{
-+ struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+
-+ rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
-+ if (IS_ERR(rstpcie0))
-+ return PTR_ERR(rstpcie0);
-+
-+ bridge_base = devm_request_and_ioremap(&pdev->dev, bridge_res);
-+ if (!bridge_base)
-+ return -ENOMEM;
-+
-+ pcie_base = devm_request_and_ioremap(&pdev->dev, pcie_res);
-+ if (!pcie_base)
-+ return -ENOMEM;
-+
-+ iomem_resource.start = 0;
-+ iomem_resource.end= ~0;
-+ ioport_resource.start= 0;
-+ ioport_resource.end = ~0;
-+
-+ /* PCIE: bypass PCIe DLL */
-+ pcie_phy(0x0, 0x80);
-+ pcie_phy(0x1, 0x04);
-+ /* PCIE: Elastic buffer control */
-+ pcie_phy(0x68, 0xB4);
-+
-+ reset_control_assert(rstpcie0);
-+ rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
-+ rt_sysc_m32(1<<19, 1<<31, PPLL_DRV);
-+ rt_sysc_m32(0x3 << 16, 0, RALINK_GPIOMODE);
-+
-+ reset_control_deassert(rstpcie0);
-+ rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
-+
-+ mdelay(100);
-+
-+ if (!(rt_sysc_r32(PPLL_CFG1) & 1<<23)) {
-+ printk("MT7620 PPLL unlock\n");
-+ reset_control_assert(rstpcie0);
-+ rt_sysc_m32(BIT(26), 0, RALINK_CLKCFG1);
-+ return 0;
-+ }
-+ rt_sysc_m32((0x1<<18) | (0x1<<17), (0x1 << 19) | (0x1 << 31), PPLL_DRV);
-+
-+ mdelay(100);
-+ reset_control_assert(rstpcie0);
-+ rt_sysc_m32(0x30, 2 << 4, RALINK_SYSCFG1);
-+
-+ rt_sysc_m32(~0x7fffffff, 0x80000000, RALINK_PCIE_CLK_GEN);
-+ rt_sysc_m32(~0x80ffffff, 0xa << 24, RALINK_PCIE_CLK_GEN1);
-+
-+ mdelay(50);
-+ reset_control_deassert(rstpcie0);
-+ pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
-+ mdelay(100);
-+
-+ if (( pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
-+ reset_control_assert(rstpcie0);
-+ rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
-+ rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
-+ printk("PCIE0 no card, disable it(RST&CLK)\n");
-+ }
-+
-+ bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
-+ bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
-+
-+ pcie_w32(0x7FFF0000, RALINK_PCI0_BAR0SETUP_ADDR);
-+ pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
-+ pcie_w32(0x08021814, RALINK_PCI0_ID);
-+ pcie_w32(0x06040001, RALINK_PCI0_CLASS);
-+ pcie_w32(0x28801814, RALINK_PCI0_SUBID);
-+ pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
-+
-+ register_pci_controller(&mt7620a_controller);
-+
-+ return 0;
-+}
-+
-+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ const struct resource *res;
-+ u16 cmd;
-+ u32 val;
-+ int i, irq = 0;
-+
-+ if ((dev->bus->number == 0) && (slot == 0)) {
-+ pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
-+ pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
-+ pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
-+ } else if ((dev->bus->number == 1) && (slot == 0x0)) {
-+ irq = RALINK_INT_PCIE0;
-+ } else {
-+ printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
-+ return 0;
-+ }
-+
-+ for (i = 0; i < 6; i++) {
-+ res = &dev->resource[i];
-+ }
-+
-+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
-+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
-+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
-+
-+ // FIXME
-+ cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
-+ pci_write_config_word(dev, PCI_COMMAND, cmd);
-+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
-+ //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
-+
-+ return irq;
-+}
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+ return 0;
-+}
-+
-+static const struct of_device_id mt7620a_pci_ids[] = {
-+ { .compatible = "ralink,mt7620a-pci" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, mt7620a_pci_ids);
-+
-+static struct platform_driver mt7620a_pci_driver = {
-+ .probe = mt7620a_pci_probe,
-+ .driver = {
-+ .name = "mt7620a-pci",
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(mt7620a_pci_ids),
-+ },
-+};
-+
-+static int __init mt7620a_pci_init(void)
-+{
-+ return platform_driver_register(&mt7620a_pci_driver);
-+}
-+
-+arch_initcall(mt7620a_pci_init);
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -33,6 +33,7 @@ choice
- bool "MT7620"
- select USB_ARCH_HAS_OHCI
- select USB_ARCH_HAS_EHCI
-+ select HW_HAS_PCI
-
- endchoice
-
+++ /dev/null
-From bed88d4cb806d2738528cb7d368d6df79d9c1424 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sat, 11 May 2013 23:40:19 +0200
-Subject: [PATCH 116/133] NET: multi phy support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/net/phy/phy.c | 9 ++++++---
- include/linux/phy.h | 2 +-
- 2 files changed, 7 insertions(+), 4 deletions(-)
-
---- a/drivers/net/phy/phy.c
-+++ b/drivers/net/phy/phy.c
-@@ -820,7 +820,8 @@ void phy_state_machine(struct work_struc
- * negotiation for now */
- if (!phydev->link) {
- phydev->state = PHY_NOLINK;
-- netif_carrier_off(phydev->attached_dev);
-+ if (!phydev->no_auto_carrier_off)
-+ netif_carrier_off(phydev->attached_dev);
- phydev->adjust_link(phydev->attached_dev);
- break;
- }
-@@ -890,7 +891,8 @@ void phy_state_machine(struct work_struc
- netif_carrier_on(phydev->attached_dev);
- } else {
- phydev->state = PHY_NOLINK;
-- netif_carrier_off(phydev->attached_dev);
-+ if (!phydev->no_auto_carrier_off)
-+ netif_carrier_off(phydev->attached_dev);
- }
-
- phydev->adjust_link(phydev->attached_dev);
-@@ -902,7 +904,8 @@ void phy_state_machine(struct work_struc
- case PHY_HALTED:
- if (phydev->link) {
- phydev->link = 0;
-- netif_carrier_off(phydev->attached_dev);
-+ if (!phydev->no_auto_carrier_off)
-+ netif_carrier_off(phydev->attached_dev);
- phydev->adjust_link(phydev->attached_dev);
- }
- break;
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -298,7 +298,7 @@ struct phy_device {
-
- struct phy_c45_device_ids c45_ids;
- bool is_c45;
--
-+ bool no_auto_carrier_off;
- enum phy_state state;
-
- u32 dev_flags;
+++ /dev/null
-From 1282a0da09e059288eb8b576998ea001680f6628 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 14 Jul 2013 23:26:15 +0200
-Subject: [PATCH 117/133] NET: add of_get_mac_address_mtd()
-
-Many embedded devices have information such as mac addresses stored inside mtd
-devices. This patch allows us to add a property inside a node describing a
-network interface. The new property points at a mtd partition with an offset
-where the mac address can be found.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/of/of_net.c | 37 +++++++++++++++++++++++++++++++++++++
- include/linux/of_net.h | 1 +
- 2 files changed, 38 insertions(+)
-
---- a/drivers/of/of_net.c
-+++ b/drivers/of/of_net.c
-@@ -10,6 +10,7 @@
- #include <linux/of_net.h>
- #include <linux/phy.h>
- #include <linux/export.h>
-+#include <linux/mtd/mtd.h>
-
- /**
- * It maps 'enum phy_interface_t' found in include/linux/phy.h
-@@ -92,3 +93,39 @@ const void *of_get_mac_address(struct de
- return NULL;
- }
- EXPORT_SYMBOL(of_get_mac_address);
-+
-+int of_get_mac_address_mtd(struct device_node *np, void *mac)
-+{
-+ struct device_node *mtd_np = NULL;
-+ size_t retlen;
-+ int size, ret;
-+ struct mtd_info *mtd;
-+ const char *part;
-+ const __be32 *list;
-+ phandle phandle;
-+
-+ list = of_get_property(np, "mtd-mac-address", &size);
-+ if (!list || (size != (2 * sizeof(*list))))
-+ return -ENOENT;
-+
-+ phandle = be32_to_cpup(list++);
-+ if (phandle)
-+ mtd_np = of_find_node_by_phandle(phandle);
-+
-+ if (!mtd_np)
-+ return -ENOENT;
-+
-+ part = of_get_property(mtd_np, "label", NULL);
-+ if (!part)
-+ part = mtd_np->name;
-+
-+ mtd = get_mtd_device_nm(part);
-+ if (IS_ERR(mtd))
-+ return PTR_ERR(mtd);
-+
-+ ret = mtd_read(mtd, be32_to_cpup(list), 6, &retlen, (u_char *) mac);
-+ put_mtd_device(mtd);
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL_GPL(of_get_mac_address_mtd);
---- a/include/linux/of_net.h
-+++ b/include/linux/of_net.h
-@@ -11,6 +11,7 @@
- #include <linux/of.h>
- extern const int of_get_phy_mode(struct device_node *np);
- extern const void *of_get_mac_address(struct device_node *np);
-+extern int of_get_mac_address_mtd(struct device_node *np, void *mac);
- #else
- static inline const int of_get_phy_mode(struct device_node *np)
- {
+++ /dev/null
-From b7d9374aee4b47a76dadaf1fe7f6838087c9c62d Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 22 Apr 2013 23:20:03 +0200
-Subject: [PATCH 118/133] NET: MIPS: add ralink SoC ethernet driver
-
-Add support for Ralink FE and ESW.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- .../include/asm/mach-ralink/rt305x_esw_platform.h | 27 +
- arch/mips/ralink/rt305x.c | 1 +
- drivers/net/ethernet/Kconfig | 1 +
- drivers/net/ethernet/Makefile | 1 +
- drivers/net/ethernet/ralink/Kconfig | 32 +
- drivers/net/ethernet/ralink/Makefile | 18 +
- drivers/net/ethernet/ralink/esw_rt3052.c | 1463 ++++++++++++++++++++
- drivers/net/ethernet/ralink/esw_rt3052.h | 32 +
- drivers/net/ethernet/ralink/gsw_mt7620a.c | 566 ++++++++
- drivers/net/ethernet/ralink/gsw_mt7620a.h | 30 +
- drivers/net/ethernet/ralink/mdio.c | 244 ++++
- drivers/net/ethernet/ralink/mdio.h | 29 +
- drivers/net/ethernet/ralink/mdio_rt2880.c | 232 ++++
- drivers/net/ethernet/ralink/mdio_rt2880.h | 26 +
- drivers/net/ethernet/ralink/mt7530.c | 467 +++++++
- drivers/net/ethernet/ralink/mt7530.h | 20 +
- drivers/net/ethernet/ralink/ralink_soc_eth.c | 845 +++++++++++
- drivers/net/ethernet/ralink/ralink_soc_eth.h | 384 +++++
- drivers/net/ethernet/ralink/soc_mt7620.c | 172 +++
- drivers/net/ethernet/ralink/soc_rt2880.c | 51 +
- drivers/net/ethernet/ralink/soc_rt305x.c | 113 ++
- drivers/net/ethernet/ralink/soc_rt3883.c | 60 +
- 22 files changed, 4814 insertions(+)
- create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
- create mode 100644 drivers/net/ethernet/ralink/Kconfig
- create mode 100644 drivers/net/ethernet/ralink/Makefile
- create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
- create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
- create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
- create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
- create mode 100644 drivers/net/ethernet/ralink/mdio.c
- create mode 100644 drivers/net/ethernet/ralink/mdio.h
- create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
- create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
- create mode 100644 drivers/net/ethernet/ralink/mt7530.c
- create mode 100644 drivers/net/ethernet/ralink/mt7530.h
- create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
- create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
- create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
- create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
- create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
- create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
-
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
-@@ -0,0 +1,27 @@
-+/*
-+ * Ralink RT305x SoC platform device registration
-+ *
-+ * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#ifndef _RT305X_ESW_PLATFORM_H
-+#define _RT305X_ESW_PLATFORM_H
-+
-+enum {
-+ RT305X_ESW_VLAN_CONFIG_NONE = 0,
-+ RT305X_ESW_VLAN_CONFIG_LLLLW,
-+ RT305X_ESW_VLAN_CONFIG_WLLLL,
-+};
-+
-+struct rt305x_esw_platform_data
-+{
-+ u8 vlan_config;
-+ u32 reg_initval_fct2;
-+ u32 reg_initval_fpa2;
-+};
-+
-+#endif /* _RT305X_ESW_PLATFORM_H */
---- a/arch/mips/ralink/rt305x.c
-+++ b/arch/mips/ralink/rt305x.c
-@@ -194,6 +194,7 @@ void __init ralink_clk_init(void)
- }
-
- ralink_clk_add("cpu", cpu_rate);
-+ ralink_clk_add("sys", sys_rate);
- ralink_clk_add("10000b00.spi", sys_rate);
- ralink_clk_add("10000100.timer", wdt_rate);
- ralink_clk_add("10000120.watchdog", wdt_rate);
---- a/drivers/net/ethernet/Kconfig
-+++ b/drivers/net/ethernet/Kconfig
-@@ -135,6 +135,7 @@ config ETHOC
- source "drivers/net/ethernet/packetengines/Kconfig"
- source "drivers/net/ethernet/pasemi/Kconfig"
- source "drivers/net/ethernet/qlogic/Kconfig"
-+source "drivers/net/ethernet/ralink/Kconfig"
- source "drivers/net/ethernet/realtek/Kconfig"
- source "drivers/net/ethernet/renesas/Kconfig"
- source "drivers/net/ethernet/rdc/Kconfig"
---- a/drivers/net/ethernet/Makefile
-+++ b/drivers/net/ethernet/Makefile
-@@ -53,6 +53,7 @@ obj-$(CONFIG_ETHOC) += ethoc.o
- obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
- obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
- obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
-+obj-$(CONFIG_NET_RALINK) += ralink/
- obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
- obj-$(CONFIG_SH_ETH) += renesas/
- obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
---- /dev/null
-+++ b/drivers/net/ethernet/ralink/Kconfig
-@@ -0,0 +1,32 @@
-+config NET_RALINK
-+ tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
-+ depends on RALINK
-+ help
-+ This driver supports the ethernet mac inside the ralink wisocs
-+
-+if NET_RALINK
-+
-+config NET_RALINK_MDIO
-+ def_bool NET_RALINK
-+ depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
-+ select PHYLIB
-+
-+config NET_RALINK_MDIO_RT2880
-+ def_bool NET_RALINK
-+ depends on (SOC_RT288X || SOC_RT3883)
-+ select NET_RALINK_MDIO
-+
-+config NET_RALINK_ESW_RT3052
-+ def_bool NET_RALINK
-+ depends on SOC_RT305X
-+ select PHYLIB
-+ select SWCONFIG
-+
-+config NET_RALINK_GSW_MT7620
-+ def_bool NET_RALINK
-+ depends on SOC_MT7620
-+ select INET_LRO
-+ select NET_RALINK_MDIO
-+ select PHYLIB
-+ select SWCONFIG
-+endif
---- /dev/null
-+++ b/drivers/net/ethernet/ralink/Makefile
-@@ -0,0 +1,18 @@
-+#
-+# Makefile for the Ralink SoCs built-in ethernet macs
-+#
-+
-+ralink-eth-y += ralink_soc_eth.o
-+
-+ralink-eth-$(CONFIG_NET_RALINK_MDIO) += mdio.o
-+ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880) += mdio_rt2880.o
-+
-+ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052) += esw_rt3052.o
-+ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620) += gsw_mt7620a.o mt7530.o
-+
-+ralink-eth-$(CONFIG_SOC_RT288X) += soc_rt2880.o
-+ralink-eth-$(CONFIG_SOC_RT305X) += soc_rt305x.o
-+ralink-eth-$(CONFIG_SOC_RT3883) += soc_rt3883.o
-+ralink-eth-$(CONFIG_SOC_MT7620) += soc_mt7620.o
-+
-+obj-$(CONFIG_NET_RALINK) += ralink-eth.o
---- /dev/null
-+++ b/drivers/net/ethernet/ralink/esw_rt3052.c
-@@ -0,0 +1,1463 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
-+ *
-+ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/init.h>
-+#include <linux/skbuff.h>
-+#include <linux/etherdevice.h>
-+#include <linux/ethtool.h>
-+#include <linux/platform_device.h>
-+#include <linux/of_device.h>
-+#include <linux/clk.h>
-+#include <linux/of_net.h>
-+#include <linux/of_mdio.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+
-+#include "ralink_soc_eth.h"
-+
-+#include <linux/ioport.h>
-+#include <linux/switch.h>
-+#include <linux/mii.h>
-+
-+#include <ralink_regs.h>
-+#include <asm/mach-ralink/rt305x.h>
-+#include <asm/mach-ralink/rt305x_esw_platform.h>
-+
-+/*
-+ * HW limitations for this switch:
-+ * - No large frame support (PKT_MAX_LEN at most 1536)
-+ * - Can't have untagged vlan and tagged vlan on one port at&n
projects / openwrt / openwrt.git / commitdiff