pr_debug("Found parallel flash\n");
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
-@@ -18,6 +18,7 @@
+@@ -19,6 +19,7 @@
#include <linux/ssb/ssb_driver_gige.h>
#include <linux/dma-mapping.h>
#include <linux/pci.h>
#include <linux/mmc/sdio_func.h>
#include <linux/slab.h>
-@@ -534,6 +535,15 @@ static int ssb_devices_register(struct s
+@@ -540,6 +541,15 @@ static int ssb_devices_register(struct s
dev_idx++;
}
/* Unwind the already registered devices. */
--- a/drivers/ssb/ssb_private.h
+++ b/drivers/ssb/ssb_private.h
-@@ -211,4 +211,16 @@ static inline void b43_pci_ssb_bridge_ex
- extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
- extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
+@@ -242,4 +242,16 @@ static inline int ssb_watchdog_register(
+ }
+ #endif /* CONFIG_SSB_EMBEDDED */
+#ifdef CONFIG_SSB_SFLASH
+/* driver_chipcommon_sflash.c */
#define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */
#define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
#define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
-@@ -591,6 +604,9 @@ struct ssb_chipcommon {
- /* Fast Powerup Delay constant */
- u16 fast_pwrup_delay;
+@@ -593,6 +606,9 @@ struct ssb_chipcommon {
struct ssb_chipcommon_pmu pmu;
+ u32 ticks_per_ms;
+ u32 max_timer_ms;
+#ifdef CONFIG_SSB_SFLASH
+ struct bcm47xx_sflash sflash;
+#endif
}
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
-@@ -543,6 +543,14 @@ static int ssb_devices_register(struct s
+@@ -549,6 +549,14 @@ static int ssb_devices_register(struct s
"Error registering serial flash\n");
}
#endif
error:
--- a/drivers/ssb/ssb_private.h
+++ b/drivers/ssb/ssb_private.h
-@@ -223,4 +223,6 @@ static inline int ssb_sflash_init(struct
+@@ -254,4 +254,6 @@ static inline int ssb_sflash_init(struct
}
#endif /* CONFIG_SSB_SFLASH */
e->name, sflash->size / 1024, sflash->blocksize,
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
-@@ -1,6 +1,8 @@
- #ifndef LINUX_BCMA_DRIVER_CC_H_
- #define LINUX_BCMA_DRIVER_CC_H_
+@@ -3,6 +3,8 @@
+
+ #include <linux/platform_device.h>
+#include <linux/mtd/bcm47xx_sflash.h>
+
/** ChipCommon core registers. **/
#define BCMA_CC_ID 0x0000
#define BCMA_CC_ID_ID 0x0000FFFF
-@@ -516,17 +518,6 @@ struct bcma_pflash {
+@@ -518,17 +520,6 @@ struct bcma_pflash {
u32 window_size;
};
#ifdef CONFIG_BCMA_NFLASH
struct mtd_info;
-@@ -561,7 +552,7 @@ struct bcma_drv_cc {
+@@ -563,7 +554,7 @@ struct bcma_drv_cc {
#ifdef CONFIG_BCMA_DRIVER_MIPS
struct bcma_pflash pflash;
#ifdef CONFIG_BCMA_SFLASH
+}
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
-@@ -2,6 +2,7 @@
- #define LINUX_BCMA_DRIVER_CC_H_
+@@ -4,6 +4,7 @@
+ #include <linux/platform_device.h>
#include <linux/mtd/bcm47xx_sflash.h>
+#include <linux/mtd/bcm47xx_nand.h>
/** ChipCommon core registers. **/
#define BCMA_CC_ID 0x0000
-@@ -519,17 +520,6 @@ struct bcma_pflash {
+@@ -521,17 +522,6 @@ struct bcma_pflash {
};
struct bcma_serial_port {
void *regs;
unsigned long clockspeed;
-@@ -555,7 +545,7 @@ struct bcma_drv_cc {
+@@ -557,7 +547,7 @@ struct bcma_drv_cc {
struct bcm47xx_sflash sflash;
#endif
#ifdef CONFIG_BCMA_NFLASH
#endif
int nr_serial_ports;
-@@ -613,4 +603,13 @@ extern void bcma_chipco_regctl_maskset(s
+@@ -616,4 +606,13 @@ extern void bcma_chipco_regctl_maskset(s
u32 offset, u32 mask, u32 set);
extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
--- a/drivers/ssb/embedded.c
+++ b/drivers/ssb/embedded.c
-@@ -136,6 +136,18 @@ u32 ssb_gpio_polarity(struct ssb_bus *bu
+@@ -171,6 +171,18 @@ u32 ssb_gpio_polarity(struct ssb_bus *bu
}
EXPORT_SYMBOL(ssb_gpio_polarity);
--- a/drivers/bcma/driver_chipcommon.c
+++ b/drivers/bcma/driver_chipcommon.c
-@@ -70,6 +70,8 @@ void bcma_core_chipcommon_init(struct bc
- (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
+@@ -158,6 +158,8 @@ void bcma_core_chipcommon_init(struct bc
}
+ cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
+ spin_lock_init(&cc->gpio_lock);
+
cc->setup_done = true;
}
-@@ -92,34 +94,81 @@ u32 bcma_chipco_irq_status(struct bcma_d
+@@ -197,34 +199,81 @@ u32 bcma_chipco_irq_status(struct bcma_d
u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
{
void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
-@@ -551,6 +551,9 @@ struct bcma_drv_cc {
- int nr_serial_ports;
- struct bcma_serial_port serial_ports[4];
+@@ -555,6 +555,9 @@ struct bcma_drv_cc {
#endif /* CONFIG_BCMA_DRIVER_MIPS */
+ u32 ticks_per_ms;
+ struct platform_device *watchdog;
+
+ /* Lock for GPIO register access. */
+ spinlock_t gpio_lock;
};
/* Register access */
-@@ -581,13 +584,22 @@ void bcma_chipco_irq_mask(struct bcma_dr
+@@ -584,13 +587,22 @@ void bcma_chipco_irq_mask(struct bcma_dr
u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
pr_debug("Found parallel flash\n");
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
-@@ -18,6 +18,7 @@
+@@ -19,6 +19,7 @@
#include <linux/ssb/ssb_driver_gige.h>
#include <linux/dma-mapping.h>
#include <linux/pci.h>
#include <linux/mmc/sdio_func.h>
#include <linux/slab.h>
-@@ -534,6 +535,15 @@ static int ssb_devices_register(struct s
+@@ -540,6 +541,15 @@ static int ssb_devices_register(struct s
dev_idx++;
}
/* Unwind the already registered devices. */
--- a/drivers/ssb/ssb_private.h
+++ b/drivers/ssb/ssb_private.h
-@@ -211,4 +211,16 @@ static inline void b43_pci_ssb_bridge_ex
- extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
- extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
+@@ -242,4 +242,16 @@ static inline int ssb_watchdog_register(
+ }
+ #endif /* CONFIG_SSB_EMBEDDED */
+#ifdef CONFIG_SSB_SFLASH
+/* driver_chipcommon_sflash.c */
#define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */
#define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
#define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
-@@ -591,6 +604,9 @@ struct ssb_chipcommon {
- /* Fast Powerup Delay constant */
- u16 fast_pwrup_delay;
+@@ -593,6 +606,9 @@ struct ssb_chipcommon {
struct ssb_chipcommon_pmu pmu;
+ u32 ticks_per_ms;
+ u32 max_timer_ms;
+#ifdef CONFIG_SSB_SFLASH
+ struct bcm47xx_sflash sflash;
+#endif
}
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
-@@ -543,6 +543,14 @@ static int ssb_devices_register(struct s
+@@ -549,6 +549,14 @@ static int ssb_devices_register(struct s
"Error registering serial flash\n");
}
#endif
error:
--- a/drivers/ssb/ssb_private.h
+++ b/drivers/ssb/ssb_private.h
-@@ -223,4 +223,6 @@ static inline int ssb_sflash_init(struct
+@@ -254,4 +254,6 @@ static inline int ssb_sflash_init(struct
}
#endif /* CONFIG_SSB_SFLASH */
e->name, sflash->size / 1024, sflash->blocksize,
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
-@@ -1,6 +1,8 @@
- #ifndef LINUX_BCMA_DRIVER_CC_H_
- #define LINUX_BCMA_DRIVER_CC_H_
+@@ -3,6 +3,8 @@
+
+ #include <linux/platform_device.h>
+#include <linux/mtd/bcm47xx_sflash.h>
+
/** ChipCommon core registers. **/
#define BCMA_CC_ID 0x0000
#define BCMA_CC_ID_ID 0x0000FFFF
-@@ -516,17 +518,6 @@ struct bcma_pflash {
+@@ -518,17 +520,6 @@ struct bcma_pflash {
u32 window_size;
};
#ifdef CONFIG_BCMA_NFLASH
struct mtd_info;
-@@ -561,7 +552,7 @@ struct bcma_drv_cc {
+@@ -563,7 +554,7 @@ struct bcma_drv_cc {
#ifdef CONFIG_BCMA_DRIVER_MIPS
struct bcma_pflash pflash;
#ifdef CONFIG_BCMA_SFLASH
+}
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
-@@ -2,6 +2,7 @@
- #define LINUX_BCMA_DRIVER_CC_H_
+@@ -4,6 +4,7 @@
+ #include <linux/platform_device.h>
#include <linux/mtd/bcm47xx_sflash.h>
+#include <linux/mtd/bcm47xx_nand.h>
/** ChipCommon core registers. **/
#define BCMA_CC_ID 0x0000
-@@ -519,17 +520,6 @@ struct bcma_pflash {
+@@ -521,17 +522,6 @@ struct bcma_pflash {
};
struct bcma_serial_port {
void *regs;
unsigned long clockspeed;
-@@ -555,7 +545,7 @@ struct bcma_drv_cc {
+@@ -557,7 +547,7 @@ struct bcma_drv_cc {
struct bcm47xx_sflash sflash;
#endif
#ifdef CONFIG_BCMA_NFLASH
#endif
int nr_serial_ports;
-@@ -613,4 +603,13 @@ extern void bcma_chipco_regctl_maskset(s
+@@ -616,4 +606,13 @@ extern void bcma_chipco_regctl_maskset(s
u32 offset, u32 mask, u32 set);
extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
--- a/drivers/ssb/embedded.c
+++ b/drivers/ssb/embedded.c
-@@ -136,6 +136,18 @@ u32 ssb_gpio_polarity(struct ssb_bus *bu
+@@ -171,6 +171,18 @@ u32 ssb_gpio_polarity(struct ssb_bus *bu
}
EXPORT_SYMBOL(ssb_gpio_polarity);
--- a/drivers/bcma/driver_chipcommon.c
+++ b/drivers/bcma/driver_chipcommon.c
-@@ -70,6 +70,8 @@ void bcma_core_chipcommon_init(struct bc
- (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
+@@ -158,6 +158,8 @@ void bcma_core_chipcommon_init(struct bc
}
+ cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
+ spin_lock_init(&cc->gpio_lock);
+
cc->setup_done = true;
}
-@@ -92,34 +94,81 @@ u32 bcma_chipco_irq_status(struct bcma_d
+@@ -197,34 +199,81 @@ u32 bcma_chipco_irq_status(struct bcma_d
u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
{
void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
-@@ -551,6 +551,9 @@ struct bcma_drv_cc {
- int nr_serial_ports;
- struct bcma_serial_port serial_ports[4];
+@@ -555,6 +555,9 @@ struct bcma_drv_cc {
#endif /* CONFIG_BCMA_DRIVER_MIPS */
+ u32 ticks_per_ms;
+ struct platform_device *watchdog;
+
+ /* Lock for GPIO register access. */
+ spinlock_t gpio_lock;
};
/* Register access */
-@@ -581,13 +584,22 @@ void bcma_chipco_irq_mask(struct bcma_dr
+@@ -584,13 +587,22 @@ void bcma_chipco_irq_mask(struct bcma_dr
u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
if (ret) {
unregister_reboot_notifier(&bcm47xx_wdt_notifier);
return ret;
-@@ -292,10 +188,8 @@ static int __init bcm47xx_wdt_init(void)
+@@ -292,10 +188,7 @@ static int __init bcm47xx_wdt_init(void)
static void __exit bcm47xx_wdt_exit(void)
{
- bcm47xx_wdt_stop();
-
- misc_deregister(&bcm47xx_wdt_miscdev);
-+ watchdog_stop(&bcm47xx_wdt_wdd);
+ watchdog_unregister_device(&bcm47xx_wdt_wdd);
unregister_reboot_notifier(&bcm47xx_wdt_notifier);
}
-@@ -306,4 +200,3 @@ module_exit(bcm47xx_wdt_exit);
+@@ -306,4 +199,3 @@ module_exit(bcm47xx_wdt_exit);
MODULE_AUTHOR("Aleksandar Radovanovic");
MODULE_DESCRIPTION("Watchdog driver for Broadcom BCM47xx");
MODULE_LICENSE("GPL");
return NOTIFY_DONE;
}
-@@ -146,57 +130,72 @@ static struct watchdog_ops bcm47xx_wdt_o
+@@ -146,56 +130,72 @@ static struct watchdog_ops bcm47xx_wdt_o
.set_timeout = bcm47xx_wdt_set_timeout,
};
-static void __exit bcm47xx_wdt_exit(void)
+static int __devexit bcm47xx_wdt_remove(struct platform_device *pdev)
{
-- watchdog_stop(&bcm47xx_wdt_wdd);
- watchdog_unregister_device(&bcm47xx_wdt_wdd);
+ struct bcm47xx_wdt *wdt = dev_get_platdata(&pdev->dev);
+
+MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
MODULE_DESCRIPTION("Watchdog driver for Broadcom BCM47xx");
MODULE_LICENSE("GPL");
---- /dev/null
+--- a/include/linux/bcm47xx_wdt.h
+++ b/include/linux/bcm47xx_wdt.h
-@@ -0,0 +1,27 @@
-+#ifndef LINUX_BCM47XX_WDT_H_
-+#define LINUX_BCM47XX_WDT_H_
-+
+@@ -1,7 +1,10 @@
+ #ifndef LINUX_BCM47XX_WDT_H_
+ #define LINUX_BCM47XX_WDT_H_
+
+#include <linux/notifier.h>
+#include <linux/timer.h>
-+#include <linux/types.h>
+ #include <linux/types.h>
+#include <linux/watchdog.h>
-+
-+
-+struct bcm47xx_wdt {
-+ u32 (*timer_set)(struct bcm47xx_wdt *, u32);
-+ u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
-+
-+ void *driver_data;
+
+
+ struct bcm47xx_wdt {
+@@ -10,6 +13,12 @@ struct bcm47xx_wdt {
+ u32 max_timer_ms;
+
+ void *driver_data;
+
+ struct watchdog_device wdd;
+ struct notifier_block notifier;
+
+ struct timer_list soft_timer;
+ atomic_t soft_ticks;
-+};
-+
-+static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
-+{
-+ return wdt->driver_data;
-+}
-+#endif /* LINUX_BCM47XX_WDT_H_ */
+ };
+
+ static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
--- a/drivers/watchdog/bcm47xx_wdt.c
+++ b/drivers/watchdog/bcm47xx_wdt.c
-@@ -44,12 +44,13 @@ MODULE_PARM_DESC(nowayout,
- "Watchdog cannot be stopped once started (default="
- __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+@@ -30,7 +30,7 @@
+ #define DRV_NAME "bcm47xx_wdt"
-+
- static inline struct bcm47xx_wdt *bcm47xx_wdt_get(struct watchdog_device *wdd)
- {
+ #define WDT_DEFAULT_TIME 30 /* seconds */
+-#define WDT_MAX_TIME 255 /* seconds */
++#define WDT_SOFTTIMER_MAX 255 /* seconds */
+
+ static int wdt_time = WDT_DEFAULT_TIME;
+ static bool nowayout = WATCHDOG_NOWAYOUT;
+@@ -49,7 +49,7 @@ static inline struct bcm47xx_wdt *bcm47x
return container_of(wdd, struct bcm47xx_wdt, wdd);
}
{
struct bcm47xx_wdt *wdt = (struct bcm47xx_wdt *)data;
u32 next_tick = min(wdt->wdd.timeout * 1000, wdt->max_timer_ms);
-@@ -62,7 +63,7 @@ static void bcm47xx_timer_tick(unsigned
+@@ -62,7 +62,7 @@ static void bcm47xx_timer_tick(unsigned
}
}
{
struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
-@@ -71,17 +72,17 @@ static int bcm47xx_wdt_keepalive(struct
+@@ -71,17 +71,17 @@ static int bcm47xx_wdt_keepalive(struct
return 0;
}
{
struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
-@@ -91,8 +92,8 @@ static int bcm47xx_wdt_stop(struct watch
+@@ -91,12 +91,12 @@ static int bcm47xx_wdt_stop(struct watch
return 0;
}
+static int bcm47xx_wdt_soft_set_timeout(struct watchdog_device *wdd,
+ unsigned int new_time)
{
- if (new_time < 1 || new_time > WDT_MAX_TIME) {
+- if (new_time < 1 || new_time > WDT_MAX_TIME) {
++ if (new_time < 1 || new_time > WDT_SOFTTIMER_MAX) {
pr_warn("timeout value must be 1<=x<=%d, using %d\n",
-@@ -122,12 +123,12 @@ static int bcm47xx_wdt_notify_sys(struct
+- WDT_MAX_TIME, new_time);
++ WDT_SOFTTIMER_MAX, new_time);
+ return -EINVAL;
+ }
+
+@@ -122,12 +122,12 @@ static int bcm47xx_wdt_notify_sys(struct
return NOTIFY_DONE;
}
};
static int __devinit bcm47xx_wdt_probe(struct platform_device *pdev)
-@@ -138,10 +139,10 @@ static int __devinit bcm47xx_wdt_probe(s
+@@ -138,10 +138,10 @@ static int __devinit bcm47xx_wdt_probe(s
if (!wdt)
return -ENXIO;
--- /dev/null
+--- a/drivers/watchdog/bcm47xx_wdt.c
++++ b/drivers/watchdog/bcm47xx_wdt.c
+@@ -32,11 +32,11 @@
+ #define WDT_DEFAULT_TIME 30 /* seconds */
+ #define WDT_SOFTTIMER_MAX 255 /* seconds */
+
+-static int wdt_time = WDT_DEFAULT_TIME;
++static int timeout = WDT_DEFAULT_TIME;
+ static bool nowayout = WATCHDOG_NOWAYOUT;
+
+-module_param(wdt_time, int, 0);
+-MODULE_PARM_DESC(wdt_time, "Watchdog time in seconds. (default="
++module_param(timeout, int, 0);
++MODULE_PARM_DESC(timeout, "Watchdog time in seconds. (default="
+ __MODULE_STRING(WDT_DEFAULT_TIME) ")");
+
+ module_param(nowayout, bool, 0);
+@@ -160,7 +160,7 @@ static int __devinit bcm47xx_wdt_probe(s
+ goto err_notifier;
+
+ pr_info("BCM47xx Watchdog Timer enabled (%d seconds%s)\n",
+- wdt_time, nowayout ? ", nowayout" : "");
++ timeout, nowayout ? ", nowayout" : "");
+ return 0;
+
+ err_notifier:
+++ /dev/null
---- a/drivers/watchdog/bcm47xx_wdt.c
-+++ b/drivers/watchdog/bcm47xx_wdt.c
-@@ -30,13 +30,13 @@
- #define DRV_NAME "bcm47xx_wdt"
-
- #define WDT_DEFAULT_TIME 30 /* seconds */
--#define WDT_MAX_TIME 255 /* seconds */
-+#define WDT_SOFTTIMER_MAX 3600 /* seconds */
-
--static int wdt_time = WDT_DEFAULT_TIME;
-+static int timeout = WDT_DEFAULT_TIME;
- static bool nowayout = WATCHDOG_NOWAYOUT;
-
--module_param(wdt_time, int, 0);
--MODULE_PARM_DESC(wdt_time, "Watchdog time in seconds. (default="
-+module_param(timeout, int, 0);
-+MODULE_PARM_DESC(timeout, "Watchdog time in seconds. (default="
- __MODULE_STRING(WDT_DEFAULT_TIME) ")");
-
- module_param(nowayout, bool, 0);
-@@ -95,9 +95,9 @@ static int bcm47xx_wdt_soft_stop(struct
- static int bcm47xx_wdt_soft_set_timeout(struct watchdog_device *wdd,
- unsigned int new_time)
- {
-- if (new_time < 1 || new_time > WDT_MAX_TIME) {
-+ if (new_time < 1 || new_time > WDT_SOFTTIMER_MAX) {
- pr_warn("timeout value must be 1<=x<=%d, using %d\n",
-- WDT_MAX_TIME, new_time);
-+ WDT_SOFTTIMER_MAX, new_time);
- return -EINVAL;
- }
-
-@@ -161,7 +161,7 @@ static int __devinit bcm47xx_wdt_probe(s
- goto err_notifier;
-
- pr_info("BCM47xx Watchdog Timer enabled (%d seconds%s)\n",
-- wdt_time, nowayout ? ", nowayout" : "");
-+ timeout, nowayout ? ", nowayout" : "");
- return 0;
-
- err_notifier:
@@ -31,6 +31,7 @@
#define WDT_DEFAULT_TIME 30 /* seconds */
- #define WDT_SOFTTIMER_MAX 3600 /* seconds */
+ #define WDT_SOFTTIMER_MAX 255 /* seconds */
+#define WDT_SOFTTIMER_THRESHOLD 60 /* seconds */
static int timeout = WDT_DEFAULT_TIME;
static bool nowayout = WATCHDOG_NOWAYOUT;
-@@ -50,6 +51,53 @@ static inline struct bcm47xx_wdt *bcm47x
+@@ -49,6 +50,53 @@ static inline struct bcm47xx_wdt *bcm47x
return container_of(wdd, struct bcm47xx_wdt, wdd);
}
static void bcm47xx_wdt_soft_timer_tick(unsigned long data)
{
struct bcm47xx_wdt *wdt = (struct bcm47xx_wdt *)data;
-@@ -134,15 +182,22 @@ static struct watchdog_ops bcm47xx_wdt_s
+@@ -133,15 +181,22 @@ static struct watchdog_ops bcm47xx_wdt_s
static int __devinit bcm47xx_wdt_probe(struct platform_device *pdev)
{
int ret;
wdt->wdd.info = &bcm47xx_wdt_info;
wdt->wdd.timeout = WDT_DEFAULT_TIME;
ret = wdt->wdd.ops->set_timeout(&wdt->wdd, timeout);
-@@ -160,14 +215,16 @@ static int __devinit bcm47xx_wdt_probe(s
+@@ -159,14 +214,16 @@ static int __devinit bcm47xx_wdt_probe(s
if (ret)
goto err_notifier;
return ret;
}
---- a/include/linux/bcm47xx_wdt.h
-+++ b/include/linux/bcm47xx_wdt.h
-@@ -10,6 +10,7 @@
- struct bcm47xx_wdt {
- u32 (*timer_set)(struct bcm47xx_wdt *, u32);
- u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
-+ u32 max_timer_ms;
-
- void *driver_data;
-
+++ /dev/null
---- a/drivers/bcma/driver_chipcommon.c
-+++ b/drivers/bcma/driver_chipcommon.c
-@@ -4,6 +4,7 @@
- *
- * Copyright 2005, Broadcom Corporation
- * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
-+ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
- *
- * Licensed under the GNU/GPL. See COPYING for details.
- */
-@@ -22,6 +23,14 @@ static inline u32 bcma_cc_write32_masked
- return value;
- }
-
-+static u32 bcma_chipco_alp_clock(struct bcma_drv_cc *cc)
-+{
-+ if (cc->capabilities & BCMA_CC_CAP_PMU)
-+ return bcma_pmu_alp_clock(cc);
-+
-+ return 20000000;
-+}
-+
- void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
- {
- if (cc->early_setup_done)
-@@ -180,8 +189,7 @@ void bcma_chipco_serial_init(struct bcma
- struct bcma_serial_port *ports = cc->serial_ports;
-
- if (ccrev >= 11 && ccrev != 15) {
-- /* Fixed ALP clock */
-- baud_base = bcma_pmu_alp_clock(cc);
-+ baud_base = bcma_chipco_alp_clock(cc);
- if (ccrev >= 21) {
- /* Turn off UART clock before switching clocksource. */
- bcma_cc_write32(cc, BCMA_CC_CORECTL,
+++ /dev/null
---- a/drivers/bcma/driver_chipcommon.c
-+++ b/drivers/bcma/driver_chipcommon.c
-@@ -31,6 +31,28 @@ static u32 bcma_chipco_alp_clock(struct
- return 20000000;
- }
-
-+static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
-+{
-+ struct bcma_bus *bus = cc->core->bus;
-+ u32 nb;
-+
-+ if (cc->capabilities & BCMA_CC_CAP_PMU) {
-+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
-+ nb = 32;
-+ else if (cc->core->id.rev < 26)
-+ nb = 16;
-+ else
-+ nb = (cc->core->id.rev >= 37) ? 32 : 24;
-+ } else {
-+ nb = 28;
-+ }
-+ if (nb == 32)
-+ return 0xffffffff;
-+ else
-+ return (1 << nb) - 1;
-+}
-+
-+
- void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
- {
- if (cc->early_setup_done)
-@@ -87,8 +109,23 @@ void bcma_core_chipcommon_init(struct bc
- /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
- void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
- {
-- /* instant NMI */
-- bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
-+ u32 maxt;
-+ enum bcma_clkmode clkmode;
-+
-+ maxt = bcma_chipco_watchdog_get_max_timer(cc);
-+ if (cc->capabilities & BCMA_CC_CAP_PMU) {
-+ if (ticks == 1)
-+ ticks = 2;
-+ else if (ticks > maxt)
-+ ticks = maxt;
-+ bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
-+ } else {
-+ clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
-+ bcma_core_set_clockmode(cc->core, clkmode);
-+ if (ticks > maxt)
-+ ticks = maxt;
-+ bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
-+ }
- }
-
- void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
+++ /dev/null
---- a/drivers/bcma/driver_chipcommon.c
-+++ b/drivers/bcma/driver_chipcommon.c
-@@ -10,6 +10,7 @@
- */
-
- #include "bcma_private.h"
-+#include <linux/bcm47xx_wdt.h>
- #include <linux/export.h>
- #include <linux/bcma/bcma.h>
-
-@@ -52,6 +53,39 @@ static u32 bcma_chipco_watchdog_get_max_
- return (1 << nb) - 1;
- }
-
-+static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
-+ u32 ticks)
-+{
-+ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
-+
-+ return bcma_chipco_watchdog_timer_set(cc, ticks);
-+}
-+
-+static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
-+ u32 ms)
-+{
-+ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
-+ u32 ticks;
-+
-+ ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
-+ return ticks / cc->ticks_per_ms;
-+}
-+
-+static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
-+{
-+ struct bcma_bus *bus = cc->core->bus;
-+
-+ if (cc->capabilities & BCMA_CC_CAP_PMU) {
-+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
-+ /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
-+ return bcma_chipco_alp_clock(cc) / 4000;
-+ else
-+ /* based on 32KHz ILP clock */
-+ return 32;
-+ } else {
-+ return bcma_chipco_alp_clock(cc) / 1000;
-+ }
-+}
-
- void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
- {
-@@ -102,12 +136,13 @@ void bcma_core_chipcommon_init(struct bc
- }
-
- spin_lock_init(&cc->gpio_lock);
-+ cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
-
- cc->setup_done = true;
- }
-
- /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
--void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
-+u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
- {
- u32 maxt;
- enum bcma_clkmode clkmode;
-@@ -126,6 +161,7 @@ void bcma_chipco_watchdog_timer_set(stru
- ticks = maxt;
- bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
- }
-+ return ticks;
- }
-
- void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
---- a/include/linux/bcma/bcma_driver_chipcommon.h
-+++ b/include/linux/bcma/bcma_driver_chipcommon.h
-@@ -554,6 +554,7 @@ struct bcma_drv_cc {
-
- /* Lock for GPIO register access. */
- spinlock_t gpio_lock;
-+ u32 ticks_per_ms;
- };
-
- /* Register access */
-@@ -577,8 +578,7 @@ extern void bcma_chipco_resume(struct bc
-
- void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
-
--extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
-- u32 ticks);
-+extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
-
- void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
-
+++ /dev/null
---- a/drivers/bcma/bcma_private.h
-+++ b/drivers/bcma/bcma_private.h
-@@ -85,6 +85,8 @@ extern void __exit bcma_host_pci_exit(vo
- /* driver_pci.c */
- u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
-
-+extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
-+
- #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
- bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
- void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
---- a/drivers/bcma/driver_chipcommon.c
-+++ b/drivers/bcma/driver_chipcommon.c
-@@ -12,6 +12,7 @@
- #include "bcma_private.h"
- #include <linux/bcm47xx_wdt.h>
- #include <linux/export.h>
-+#include <linux/platform_device.h>
- #include <linux/bcma/bcma.h>
-
- static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
-@@ -87,6 +88,27 @@ static int bcma_chipco_watchdog_ticks_pe
- }
- }
-
-+int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
-+{
-+ struct bcm47xx_wdt wdt = {};
-+ struct platform_device *pdev;
-+
-+ wdt.driver_data = cc;
-+ wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
-+ wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
-+ wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
-+
-+ pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
-+ cc->core->bus->num, &wdt,
-+ sizeof(wdt));
-+ if (IS_ERR(pdev))
-+ return PTR_ERR(pdev);
-+
-+ cc->watchdog = pdev;
-+
-+ return 0;
-+}
-+
- void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
- {
- if (cc->early_setup_done)
---- a/drivers/bcma/main.c
-+++ b/drivers/bcma/main.c
-@@ -173,6 +173,12 @@ static int bcma_register_cores(struct bc
- }
- #endif
-
-+ if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
-+ err = bcma_chipco_watchdog_register(&bus->drv_cc);
-+ if (err)
-+ bcma_err(bus, "Error registering watchdog driver\n");
-+ }
-+
- return 0;
- }
-
-@@ -185,6 +191,8 @@ static void bcma_unregister_cores(struct
- if (core->dev_registered)
- device_unregister(&core->dev);
- }
-+ if (bus->hosttype == BCMA_HOSTTYPE_SOC)
-+ platform_device_unregister(bus->drv_cc.watchdog);
- }
-
- int __devinit bcma_bus_register(struct bcma_bus *bus)
---- a/include/linux/bcma/bcma_driver_chipcommon.h
-+++ b/include/linux/bcma/bcma_driver_chipcommon.h
-@@ -4,6 +4,8 @@
- #include <linux/mtd/bcm47xx_sflash.h>
- #include <linux/mtd/bcm47xx_nand.h>
-
-+#include <linux/platform_device.h>
-+
- /** ChipCommon core registers. **/
- #define BCMA_CC_ID 0x0000
- #define BCMA_CC_ID_ID 0x0000FFFF
-@@ -555,6 +557,7 @@ struct bcma_drv_cc {
- /* Lock for GPIO register access. */
- spinlock_t gpio_lock;
- u32 ticks_per_ms;
-+ struct platform_device *watchdog;
- };
-
- /* Register access */
+++ /dev/null
---- a/drivers/ssb/driver_chipcommon.c
-+++ b/drivers/ssb/driver_chipcommon.c
-@@ -280,6 +280,14 @@ static void calc_fast_powerup_delay(stru
- cc->fast_pwrup_delay = tmp;
- }
-
-+static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
-+{
-+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
-+ return ssb_pmu_get_alp_clock(cc);
-+
-+ return 20000000;
-+}
-+
- void ssb_chipcommon_init(struct ssb_chipcommon *cc)
- {
- if (!cc->dev)
-@@ -474,11 +482,7 @@ int ssb_chipco_serial_init(struct ssb_ch
- | SSB_CHIPCO_CORECTL_UARTCLK0);
- } else if ((ccrev >= 11) && (ccrev != 15)) {
- /* Fixed ALP clock */
-- baud_base = 20000000;
-- if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
-- /* FIXME: baud_base is different for devices with a PMU */
-- SSB_WARN_ON(1);
-- }
-+ baud_base = ssb_chipco_alp_clock(cc);
- div = 1;
- if (ccrev >= 21) {
- /* Turn off UART clock before switching clocksource. */
---- a/drivers/ssb/driver_chipcommon_pmu.c
-+++ b/drivers/ssb/driver_chipcommon_pmu.c
-@@ -618,6 +618,33 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
- EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
- EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
-
-+static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
-+{
-+ u32 crystalfreq;
-+ const struct pmu0_plltab_entry *e = NULL;
-+
-+ crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
-+ SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
-+ e = pmu0_plltab_find_entry(crystalfreq);
-+ BUG_ON(!e);
-+ return e->freq * 1000;
-+}
-+
-+u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
-+{
-+ struct ssb_bus *bus = cc->dev->bus;
-+
-+ switch (bus->chip_id) {
-+ case 0x5354:
-+ ssb_pmu_get_alp_clock_clk0(cc);
-+ default:
-+ ssb_printk(KERN_ERR PFX
-+ "ERROR: PMU alp clock unknown for device %04X\n",
-+ bus->chip_id);
-+ return 0;
-+ }
-+}
-+
- u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
- {
- struct ssb_bus *bus = cc->dev->bus;
---- a/drivers/ssb/ssb_private.h
-+++ b/drivers/ssb/ssb_private.h
-@@ -210,6 +210,7 @@ static inline void b43_pci_ssb_bridge_ex
- /* driver_chipcommon_pmu.c */
- extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
- extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
-+extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
-
- #ifdef CONFIG_SSB_SFLASH
- /* driver_chipcommon_sflash.c */
+++ /dev/null
---- a/drivers/ssb/driver_chipcommon.c
-+++ b/drivers/ssb/driver_chipcommon.c
-@@ -288,6 +288,24 @@ static u32 ssb_chipco_alp_clock(struct s
- return 20000000;
- }
-
-+static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
-+{
-+ u32 nb;
-+
-+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
-+ if (cc->dev->id.revision < 26)
-+ nb = 16;
-+ else
-+ nb = (cc->dev->id.revision >= 37) ? 32 : 24;
-+ } else {
-+ nb = 28;
-+ }
-+ if (nb == 32)
-+ return 0xffffffff;
-+ else
-+ return (1 << nb) - 1;
-+}
-+
- void ssb_chipcommon_init(struct ssb_chipcommon *cc)
- {
- if (!cc->dev)
-@@ -405,8 +423,24 @@ void ssb_chipco_timing_init(struct ssb_c
- /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
- void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
- {
-- /* instant NMI */
-- chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
-+ u32 maxt;
-+ enum ssb_clkmode clkmode;
-+
-+ maxt = ssb_chipco_watchdog_get_max_timer(cc);
-+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
-+ if (ticks == 1)
-+ ticks = 2;
-+ else if (ticks > maxt)
-+ ticks = maxt;
-+ chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
-+ } else {
-+ clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
-+ ssb_chipco_set_clockmode(cc, clkmode);
-+ if (ticks > maxt)
-+ ticks = maxt;
-+ /* instant NMI */
-+ chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
-+ }
- }
-
- void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
+++ /dev/null
---- a/drivers/ssb/driver_chipcommon.c
-+++ b/drivers/ssb/driver_chipcommon.c
-@@ -4,6 +4,7 @@
- *
- * Copyright 2005, Broadcom Corporation
- * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
-+ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
- *
- * Licensed under the GNU/GPL. See COPYING for details.
- */
-@@ -12,6 +13,7 @@
- #include <linux/ssb/ssb_regs.h>
- #include <linux/export.h>
- #include <linux/pci.h>
-+#include <linux/bcm47xx_wdt.h>
-
- #include "ssb_private.h"
-
-@@ -306,6 +308,43 @@ static u32 ssb_chipco_watchdog_get_max_t
- return (1 << nb) - 1;
- }
-
-+u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
-+{
-+ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
-+
-+ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
-+ return 0;
-+
-+ return ssb_chipco_watchdog_timer_set(cc, ticks);
-+}
-+
-+u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
-+{
-+ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
-+ u32 ticks;
-+
-+ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
-+ return 0;
-+
-+ ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
-+ return ticks / cc->ticks_per_ms;
-+}
-+
-+static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
-+{
-+ struct ssb_bus *bus = cc->dev->bus;
-+
-+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
-+ /* based on 32KHz ILP clock */
-+ return 32;
-+ } else {
-+ if (cc->dev->id.revision < 18)
-+ return ssb_clockspeed(bus) / 1000;
-+ else
-+ return ssb_chipco_alp_clock(cc) / 1000;
-+ }
-+}
-+
- void ssb_chipcommon_init(struct ssb_chipcommon *cc)
- {
- if (!cc->dev)
-@@ -323,6 +362,11 @@ void ssb_chipcommon_init(struct ssb_chip
- chipco_powercontrol_init(cc);
- ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
- calc_fast_powerup_delay(cc);
-+
-+ if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
-+ cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
-+ cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
-+ }
- }
-
- void ssb_chipco_suspend(struct ssb_chipcommon *cc)
-@@ -421,7 +465,7 @@ void ssb_chipco_timing_init(struct ssb_c
- }
-
- /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
--void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
-+u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
- {
- u32 maxt;
- enum ssb_clkmode clkmode;
-@@ -441,6 +485,7 @@ void ssb_chipco_watchdog_timer_set(struc
- /* instant NMI */
- chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
- }
-+ return ticks;
- }
-
- void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
---- a/drivers/ssb/ssb_private.h
-+++ b/drivers/ssb/ssb_private.h
-@@ -3,6 +3,7 @@
-
- #include <linux/ssb/ssb.h>
- #include <linux/types.h>
-+#include <linux/bcm47xx_wdt.h>
-
-
- #define PFX "ssb: "
-@@ -226,4 +227,8 @@ static inline int ssb_sflash_init(struct
-
- extern struct platform_device ssb_pflash_dev;
-
-+extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
-+ u32 ticks);
-+extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
-+
- #endif /* LINUX_SSB_PRIVATE_H_ */
---- a/include/linux/ssb/ssb_driver_chipcommon.h
-+++ b/include/linux/ssb/ssb_driver_chipcommon.h
-@@ -607,6 +607,8 @@ struct ssb_chipcommon {
- #ifdef CONFIG_SSB_SFLASH
- struct bcm47xx_sflash sflash;
- #endif
-+ u32 ticks_per_ms;
-+ u32 max_timer_ms;
- };
-
- static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
-@@ -646,8 +648,7 @@ enum ssb_clkmode {
- extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
- enum ssb_clkmode mode);
-
--extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
-- u32 ticks);
-+extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
-
- void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
-
+++ /dev/null
---- a/drivers/ssb/driver_extif.c
-+++ b/drivers/ssb/driver_extif.c
-@@ -112,9 +112,10 @@ void ssb_extif_get_clockcontrol(struct s
- *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
- }
-
--void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
-- u32 ticks)
-+void ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
- {
-+ if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
-+ ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
- extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
- }
-
---- a/include/linux/ssb/ssb_driver_extif.h
-+++ b/include/linux/ssb/ssb_driver_extif.h
-@@ -152,6 +152,7 @@
- /* watchdog */
- #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
-
-+#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
-
-
- #ifdef CONFIG_SSB_DRIVER_EXTIF
+++ /dev/null
---- a/drivers/ssb/driver_extif.c
-+++ b/drivers/ssb/driver_extif.c
-@@ -112,11 +112,30 @@ void ssb_extif_get_clockcontrol(struct s
- *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
- }
-
--void ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
-+u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
-+{
-+ struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
-+
-+ return ssb_extif_watchdog_timer_set(extif, ticks);
-+}
-+
-+u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
-+{
-+ struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
-+ u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
-+
-+ ticks = ssb_extif_watchdog_timer_set(extif, ticks);
-+
-+ return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
-+}
-+
-+u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
- {
- if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
- ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
- extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
-+
-+ return ticks;
- }
-
- u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
---- a/drivers/ssb/ssb_private.h
-+++ b/drivers/ssb/ssb_private.h
-@@ -231,4 +231,19 @@ extern u32 ssb_chipco_watchdog_timer_set
- u32 ticks);
- extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
-
-+#ifdef CONFIG_SSB_DRIVER_EXTIF
-+extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
-+extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
-+#else
-+static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
-+ u32 ticks)
-+{
-+ return 0;
-+}
-+static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
-+ u32 ms)
-+{
-+ return 0;
-+}
-+#endif
- #endif /* LINUX_SSB_PRIVATE_H_ */
---- a/include/linux/ssb/ssb_driver_extif.h
-+++ b/include/linux/ssb/ssb_driver_extif.h
-@@ -153,6 +153,8 @@
- #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
-
- #define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
-+#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \
-+ / (SSB_EXTIF_WATCHDOG_CLK / 1000))
-
-
- #ifdef CONFIG_SSB_DRIVER_EXTIF
-@@ -172,8 +174,7 @@ extern void ssb_extif_get_clockcontrol(s
- extern void ssb_extif_timing_init(struct ssb_extif *extif,
- unsigned long ns);
-
--extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
-- u32 ticks);
-+extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
-
- /* Extif GPIO pin access */
- u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
-@@ -206,9 +207,9 @@ void ssb_extif_get_clockcontrol(struct s
- }
-
- static inline
--void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
-- u32 ticks)
-+u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
- {
-+ return 0;
- }
-
- #endif /* CONFIG_SSB_DRIVER_EXTIF */
+++ /dev/null
---- a/drivers/ssb/embedded.c
-+++ b/drivers/ssb/embedded.c
-@@ -4,11 +4,13 @@
- *
- * Copyright 2005-2008, Broadcom Corporation
- * Copyright 2006-2008, Michael Buesch <m@bues.ch>
-+ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
- *
- * Licensed under the GNU/GPL. See COPYING for details.
- */
-
- #include <linux/export.h>
-+#include <linux/platform_device.h>
- #include <linux/ssb/ssb.h>
- #include <linux/ssb/ssb_embedded.h>
- #include <linux/ssb/ssb_driver_pci.h>
-@@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bu
- }
- EXPORT_SYMBOL(ssb_watchdog_timer_set);
-
-+int ssb_watchdog_register(struct ssb_bus *bus)
-+{
-+ struct bcm47xx_wdt wdt = {};
-+ struct platform_device *pdev;
-+
-+ if (ssb_chipco_available(&bus->chipco)) {
-+ wdt.driver_data = &bus->chipco;
-+ wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
-+ wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
-+ wdt.max_timer_ms = bus->chipco.max_timer_ms;
-+ } else if (ssb_extif_available(&bus->extif)) {
-+ wdt.driver_data = &bus->extif;
-+ wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
-+ wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
-+ wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
-+ } else {
-+ return -ENODEV;
-+ }
-+
-+ pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
-+ bus->busnumber, &wdt,
-+ sizeof(wdt));
-+ if (IS_ERR(pdev)) {
-+ ssb_dprintk(KERN_INFO PFX
-+ "can not register watchdog device, err: %li\n",
-+ PTR_ERR(pdev));
-+ return PTR_ERR(pdev);
-+ }
-+
-+ bus->watchdog = pdev;
-+ return 0;
-+}
-+
- u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
- {
- unsigned long flags;
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -13,6 +13,7 @@
- #include <linux/delay.h>
- #include <linux/io.h>
- #include <linux/module.h>
-+#include <linux/platform_device.h>
- #include <linux/ssb/ssb.h>
- #include <linux/ssb/ssb_regs.h>
- #include <linux/ssb/ssb_driver_gige.h>
-@@ -434,6 +435,11 @@ static void ssb_devices_unregister(struc
- if (sdev->dev)
- device_unregister(sdev->dev);
- }
-+
-+#ifdef CONFIG_SSB_EMBEDDED
-+ if (bus->bustype == SSB_BUSTYPE_SSB)
-+ platform_device_unregister(bus->watchdog);
-+#endif
- }
-
- void ssb_bus_unregister(struct ssb_bus *bus)
-@@ -579,6 +585,8 @@ static int __devinit ssb_attach_queued_b
- if (err)
- goto error;
- ssb_pcicore_init(&bus->pcicore);
-+ if (bus->bustype == SSB_BUSTYPE_SSB)
-+ ssb_watchdog_register(bus);
- ssb_bus_may_powerdown(bus);
-
- err = ssb_devices_register(bus);
---- a/drivers/ssb/ssb_private.h
-+++ b/drivers/ssb/ssb_private.h
-@@ -246,4 +246,14 @@ static inline u32 ssb_extif_watchdog_tim
- return 0;
- }
- #endif
-+
-+#ifdef CONFIG_SSB_EMBEDDED
-+extern int ssb_watchdog_register(struct ssb_bus *bus);
-+#else /* CONFIG_SSB_EMBEDDED */
-+static inline int ssb_watchdog_register(struct ssb_bus *bus)
-+{
-+ return 0;
-+}
-+#endif /* CONFIG_SSB_EMBEDDED */
-+
- #endif /* LINUX_SSB_PRIVATE_H_ */
---- a/include/linux/ssb/ssb.h
-+++ b/include/linux/ssb/ssb.h
-@@ -8,6 +8,7 @@
- #include <linux/pci.h>
- #include <linux/mod_devicetable.h>
- #include <linux/dma-mapping.h>
-+#include <linux/platform_device.h>
-
- #include <linux/ssb/ssb_regs.h>
-
-@@ -432,6 +433,7 @@ struct ssb_bus {
- #ifdef CONFIG_SSB_EMBEDDED
- /* Lock for GPIO register access. */
- spinlock_t gpio_lock;
-+ struct platform_device *watchdog;
- #endif /* EMBEDDED */
-
- /* Internal-only stuff follows. Do not touch. */
--- a/drivers/ssb/b43_pci_bridge.c
+++ b/drivers/ssb/b43_pci_bridge.c
-@@ -29,11 +29,14 @@ static const struct pci_device_id b43_pc
+@@ -29,11 +29,15 @@ static const struct pci_device_id b43_pc
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
{ 0, },
};
MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
+--- a/drivers/ssb/driver_chipcommon.c
++++ b/drivers/ssb/driver_chipcommon.c
+@@ -4,6 +4,7 @@
+ *
+ * Copyright 2005, Broadcom Corporation
+ * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+@@ -12,6 +13,7 @@
+ #include <linux/ssb/ssb_regs.h>
+ #include <linux/export.h>
+ #include <linux/pci.h>
++#include <linux/bcm47xx_wdt.h>
+
+ #include "ssb_private.h"
+
+@@ -280,6 +282,69 @@ static void calc_fast_powerup_delay(stru
+ cc->fast_pwrup_delay = tmp;
+ }
+
++static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
++{
++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
++ return ssb_pmu_get_alp_clock(cc);
++
++ return 20000000;
++}
++
++static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
++{
++ u32 nb;
++
++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
++ if (cc->dev->id.revision < 26)
++ nb = 16;
++ else
++ nb = (cc->dev->id.revision >= 37) ? 32 : 24;
++ } else {
++ nb = 28;
++ }
++ if (nb == 32)
++ return 0xffffffff;
++ else
++ return (1 << nb) - 1;
++}
++
++u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
++{
++ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
++
++ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
++ return 0;
++
++ return ssb_chipco_watchdog_timer_set(cc, ticks);
++}
++
++u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
++{
++ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
++ u32 ticks;
++
++ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
++ return 0;
++
++ ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
++ return ticks / cc->ticks_per_ms;
++}
++
++static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
++{
++ struct ssb_bus *bus = cc->dev->bus;
++
++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
++ /* based on 32KHz ILP clock */
++ return 32;
++ } else {
++ if (cc->dev->id.revision < 18)
++ return ssb_clockspeed(bus) / 1000;
++ else
++ return ssb_chipco_alp_clock(cc) / 1000;
++ }
++}
++
+ void ssb_chipcommon_init(struct ssb_chipcommon *cc)
+ {
+ if (!cc->dev)
+@@ -297,6 +362,11 @@ void ssb_chipcommon_init(struct ssb_chip
+ chipco_powercontrol_init(cc);
+ ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
+ calc_fast_powerup_delay(cc);
++
++ if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
++ cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
++ cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
++ }
+ }
+
+ void ssb_chipco_suspend(struct ssb_chipcommon *cc)
+@@ -395,10 +465,27 @@ void ssb_chipco_timing_init(struct ssb_c
+ }
+
+ /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
+-void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
++u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
+ {
+- /* instant NMI */
+- chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
++ u32 maxt;
++ enum ssb_clkmode clkmode;
++
++ maxt = ssb_chipco_watchdog_get_max_timer(cc);
++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
++ if (ticks == 1)
++ ticks = 2;
++ else if (ticks > maxt)
++ ticks = maxt;
++ chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
++ } else {
++ clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
++ ssb_chipco_set_clockmode(cc, clkmode);
++ if (ticks > maxt)
++ ticks = maxt;
++ /* instant NMI */
++ chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
++ }
++ return ticks;
+ }
+
+ void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
+@@ -473,12 +560,7 @@ int ssb_chipco_serial_init(struct ssb_ch
+ chipco_read32(cc, SSB_CHIPCO_CORECTL)
+ | SSB_CHIPCO_CORECTL_UARTCLK0);
+ } else if ((ccrev >= 11) && (ccrev != 15)) {
+- /* Fixed ALP clock */
+- baud_base = 20000000;
+- if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
+- /* FIXME: baud_base is different for devices with a PMU */
+- SSB_WARN_ON(1);
+- }
++ baud_base = ssb_chipco_alp_clock(cc);
+ div = 1;
+ if (ccrev >= 21) {
+ /* Turn off UART clock before switching clocksource. */
--- a/drivers/ssb/driver_chipcommon_pmu.c
+++ b/drivers/ssb/driver_chipcommon_pmu.c
@@ -13,6 +13,9 @@
ssb_pmu0_pllinit_r0(cc, crystalfreq);
break;
case 0x4322:
-@@ -607,3 +614,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
+@@ -339,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
+ chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
+ }
+ break;
++ case 43222:
++ break;
+ default:
+ ssb_printk(KERN_ERR PFX
+ "ERROR: PLL init unknown for device %04X\n",
+@@ -427,6 +436,7 @@ static void ssb_pmu_resources_init(struc
+ min_msk = 0xCBB;
+ break;
+ case 0x4322:
++ case 43222:
+ /* We keep the default settings:
+ * min_msk = 0xCBB
+ * max_msk = 0x7FFFF
+@@ -607,3 +617,61 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
+
++static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
++{
++ u32 crystalfreq;
++ const struct pmu0_plltab_entry *e = NULL;
++
++ crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
++ SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
++ e = pmu0_plltab_find_entry(crystalfreq);
++ BUG_ON(!e);
++ return e->freq * 1000;
++}
++
++u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
++{
++ struct ssb_bus *bus = cc->dev->bus;
++
++ switch (bus->chip_id) {
++ case 0x5354:
++ ssb_pmu_get_alp_clock_clk0(cc);
++ default:
++ ssb_printk(KERN_ERR PFX
++ "ERROR: PMU alp clock unknown for device %04X\n",
++ bus->chip_id);
++ return 0;
++ }
++}
++
+u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
+{
+ struct ssb_bus *bus = cc->dev->bus;
+ return 0;
+ }
+}
+--- a/drivers/ssb/driver_extif.c
++++ b/drivers/ssb/driver_extif.c
+@@ -112,10 +112,30 @@ void ssb_extif_get_clockcontrol(struct s
+ *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
+ }
+
+-void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
+- u32 ticks)
++u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
+ {
++ struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
++
++ return ssb_extif_watchdog_timer_set(extif, ticks);
++}
++
++u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
++{
++ struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
++ u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
++
++ ticks = ssb_extif_watchdog_timer_set(extif, ticks);
++
++ return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
++}
++
++u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
++{
++ if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
++ ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
+ extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
++
++ return ticks;
+ }
+
+ u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
--- a/drivers/ssb/driver_mipscore.c
+++ b/drivers/ssb/driver_mipscore.c
+@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
+ {
+ struct ssb_bus *bus = mcore->dev->bus;
+
+- if (bus->extif.dev)
++ if (ssb_extif_available(&bus->extif))
+ mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
+- else if (bus->chipco.dev)
++ else if (ssb_chipco_available(&bus->chipco))
+ mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
+ else
+ mcore->nr_serial_ports = 0;
@@ -190,16 +190,32 @@ static void ssb_mips_flash_detect(struct
{
struct ssb_bus *bus = mcore->dev->bus;
- mcore->flash_window = 0x1c000000;
- mcore->flash_window_size = 0x02000000;
+ /* When there is no chipcommon on the bus there is 4MB flash */
-+ if (!bus->chipco.dev) {
++ if (!ssb_chipco_available(&bus->chipco)) {
+ mcore->pflash.present = true;
+ mcore->pflash.buswidth = 2;
+ mcore->pflash.window = SSB_FLASH1;
}
}
-@@ -208,6 +224,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
+@@ -208,9 +224,12 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
struct ssb_bus *bus = mcore->dev->bus;
u32 pll_type, n, m, rate = 0;
+- if (bus->extif.dev) {
+ if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
+ return ssb_pmu_get_cpu_clock(&bus->chipco);
+
- if (bus->extif.dev) {
++ if (ssb_extif_available(&bus->extif)) {
ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
- } else if (bus->chipco.dev) {
+- } else if (bus->chipco.dev) {
++ } else if (ssb_chipco_available(&bus->chipco)) {
+ ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
+ } else
+ return 0;
+@@ -246,9 +265,9 @@ void ssb_mipscore_init(struct ssb_mipsco
+ hz = 100000000;
+ ns = 1000000000 / hz;
+
+- if (bus->extif.dev)
++ if (ssb_extif_available(&bus->extif))
+ ssb_extif_timing_init(&bus->extif, ns);
+- else if (bus->chipco.dev)
++ else if (ssb_chipco_available(&bus->chipco))
+ ssb_chipco_timing_init(&bus->chipco, ns);
+
+ /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
+--- a/drivers/ssb/embedded.c
++++ b/drivers/ssb/embedded.c
+@@ -4,11 +4,13 @@
+ *
+ * Copyright 2005-2008, Broadcom Corporation
+ * Copyright 2006-2008, Michael Buesch <m@bues.ch>
++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+ #include <linux/export.h>
++#include <linux/platform_device.h>
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_embedded.h>
+ #include <linux/ssb/ssb_driver_pci.h>
+@@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bu
+ }
+ EXPORT_SYMBOL(ssb_watchdog_timer_set);
+
++int ssb_watchdog_register(struct ssb_bus *bus)
++{
++ struct bcm47xx_wdt wdt = {};
++ struct platform_device *pdev;
++
++ if (ssb_chipco_available(&bus->chipco)) {
++ wdt.driver_data = &bus->chipco;
++ wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
++ wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
++ wdt.max_timer_ms = bus->chipco.max_timer_ms;
++ } else if (ssb_extif_available(&bus->extif)) {
++ wdt.driver_data = &bus->extif;
++ wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
++ wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
++ wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
++ } else {
++ return -ENODEV;
++ }
++
++ pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
++ bus->busnumber, &wdt,
++ sizeof(wdt));
++ if (IS_ERR(pdev)) {
++ ssb_dprintk(KERN_INFO PFX
++ "can not register watchdog device, err: %li\n",
++ PTR_ERR(pdev));
++ return PTR_ERR(pdev);
++ }
++
++ bus->watchdog = pdev;
++ return 0;
++}
++
+ u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
+ {
+ unsigned long flags;
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
-@@ -140,19 +140,6 @@ static void ssb_device_put(struct ssb_de
+@@ -13,6 +13,7 @@
+ #include <linux/delay.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
++#include <linux/platform_device.h>
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_regs.h>
+ #include <linux/ssb/ssb_driver_gige.h>
+@@ -140,19 +141,6 @@ static void ssb_device_put(struct ssb_de
put_device(dev->dev);
}
static int ssb_device_resume(struct device *dev)
{
struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
-@@ -250,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
+@@ -250,11 +238,9 @@ int ssb_devices_freeze(struct ssb_bus *b
ssb_device_put(sdev);
continue;
}
sdrv->remove(sdev);
ctx->device_frozen[i] = 1;
}
-@@ -293,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
+@@ -293,7 +279,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
dev_name(sdev->dev));
result = err;
}
ssb_device_put(sdev);
}
-@@ -1094,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
+@@ -449,6 +434,11 @@ static void ssb_devices_unregister(struc
+ if (sdev->dev)
+ device_unregister(sdev->dev);
+ }
++
++#ifdef CONFIG_SSB_EMBEDDED
++ if (bus->bustype == SSB_BUSTYPE_SSB)
++ platform_device_unregister(bus->watchdog);
++#endif
+ }
+
+ void ssb_bus_unregister(struct ssb_bus *bus)
+@@ -577,6 +567,8 @@ static int __devinit ssb_attach_queued_b
+ if (err)
+ goto error;
+ ssb_pcicore_init(&bus->pcicore);
++ if (bus->bustype == SSB_BUSTYPE_SSB)
++ ssb_watchdog_register(bus);
+ ssb_bus_may_powerdown(bus);
+
+ err = ssb_devices_register(bus);
+@@ -1094,6 +1086,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
u32 plltype;
u32 clkctl_n, clkctl_m;
if (ssb_extif_available(&bus->extif))
ssb_extif_get_clockcontrol(&bus->extif, &plltype,
&clkctl_n, &clkctl_m);
+@@ -1131,8 +1126,7 @@ static u32 ssb_tmslow_reject_bitmask(str
+ case SSB_IDLOW_SSBREV_27: /* same here */
+ return SSB_TMSLOW_REJECT; /* this is a guess */
+ default:
+- printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
+- WARN_ON(1);
++ WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
+ }
+ return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
+ }
--- a/drivers/ssb/pci.c
+++ b/drivers/ssb/pci.c
@@ -178,6 +178,18 @@ err_pci:
GOTO_ERROR_ON((tuple->size != 3) &&
--- a/drivers/ssb/ssb_private.h
+++ b/drivers/ssb/ssb_private.h
-@@ -207,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
+@@ -3,6 +3,7 @@
+
+ #include <linux/ssb/ssb.h>
+ #include <linux/types.h>
++#include <linux/bcm47xx_wdt.h>
+
+
+ #define PFX "ssb: "
+@@ -207,4 +208,38 @@ static inline void b43_pci_ssb_bridge_ex
}
#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
+/* driver_chipcommon_pmu.c */
+extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
+extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
++extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
++
++extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
++ u32 ticks);
++extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
++
++#ifdef CONFIG_SSB_DRIVER_EXTIF
++extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
++extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
++#else
++static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
++ u32 ticks)
++{
++ return 0;
++}
++static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
++ u32 ms)
++{
++ return 0;
++}
++#endif
++
++#ifdef CONFIG_SSB_EMBEDDED
++extern int ssb_watchdog_register(struct ssb_bus *bus);
++#else /* CONFIG_SSB_EMBEDDED */
++static inline int ssb_watchdog_register(struct ssb_bus *bus)
++{
++ return 0;
++}
++#endif /* CONFIG_SSB_EMBEDDED */
+
#endif /* LINUX_SSB_PRIVATE_H_ */
--- a/include/linux/ssb/ssb.h
+++ b/include/linux/ssb/ssb.h
-@@ -16,6 +16,12 @@ struct pcmcia_device;
+@@ -8,6 +8,7 @@
+ #include <linux/pci.h>
+ #include <linux/mod_devicetable.h>
+ #include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
+
+ #include <linux/ssb/ssb_regs.h>
+
+@@ -16,6 +17,12 @@ struct pcmcia_device;
struct ssb_bus;
struct ssb_driver;
struct ssb_sprom {
u8 revision;
u8 il0mac[6]; /* MAC address for 802.11b/g */
-@@ -26,9 +32,12 @@ struct ssb_sprom {
+@@ -26,9 +33,12 @@ struct ssb_sprom {
u8 et0mdcport; /* MDIO for enet0 */
u8 et1mdcport; /* MDIO for enet1 */
u16 board_rev; /* Board revision number from SPROM. */
u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
u16 pa0b0;
-@@ -47,10 +56,10 @@ struct ssb_sprom {
+@@ -47,10 +57,10 @@ struct ssb_sprom {
u8 gpio1; /* GPIO pin 1 */
u8 gpio2; /* GPIO pin 2 */
u8 gpio3; /* GPIO pin 3 */
u8 itssi_a; /* Idle TSSI Target for A-PHY */
u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
u8 tri2g; /* 2.4GHz TX isolation */
-@@ -61,8 +70,8 @@ struct ssb_sprom {
+@@ -61,8 +71,8 @@ struct ssb_sprom {
u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
u8 rssisav2g; /* 2GHz RSSI params */
u8 rssismc2g;
u8 rssismf2g;
-@@ -82,16 +91,13 @@ struct ssb_sprom {
+@@ -82,16 +92,13 @@ struct ssb_sprom {
u16 boardflags2_hi; /* Board flags (bits 48-63) */
/* TODO store board flags in a single u64 */
} antenna_gain;
struct {
-@@ -103,14 +109,85 @@ struct ssb_sprom {
+@@ -103,14 +110,85 @@ struct ssb_sprom {
} ghz5;
} fem;
};
-@@ -166,6 +243,7 @@ struct ssb_bus_ops {
+@@ -166,6 +244,7 @@ struct ssb_bus_ops {
#define SSB_DEV_MINI_MACPHY 0x823
#define SSB_DEV_ARM_1176 0x824
#define SSB_DEV_ARM_7TDMI 0x825
/* Vendor-ID values */
#define SSB_VENDOR_BROADCOM 0x4243
+@@ -354,6 +433,7 @@ struct ssb_bus {
+ #ifdef CONFIG_SSB_EMBEDDED
+ /* Lock for GPIO register access. */
+ spinlock_t gpio_lock;
++ struct platform_device *watchdog;
+ #endif /* EMBEDDED */
+
+ /* Internal-only stuff follows. Do not touch. */
--- a/include/linux/ssb/ssb_driver_chipcommon.h
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
@@ -504,7 +504,9 @@
/* Status register bits for ST flashes */
#define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */
+@@ -589,6 +591,8 @@ struct ssb_chipcommon {
+ /* Fast Powerup Delay constant */
+ u16 fast_pwrup_delay;
+ struct ssb_chipcommon_pmu pmu;
++ u32 ticks_per_ms;
++ u32 max_timer_ms;
+ };
+
+ static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
+@@ -628,8 +632,7 @@ enum ssb_clkmode {
+ extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
+ enum ssb_clkmode mode);
+
+-extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
+- u32 ticks);
++extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
+
+ void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
+
+--- a/include/linux/ssb/ssb_driver_extif.h
++++ b/include/linux/ssb/ssb_driver_extif.h
+@@ -152,6 +152,9 @@
+ /* watchdog */
+ #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
+
++#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
++#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \
++ / (SSB_EXTIF_WATCHDOG_CLK / 1000))
+
+
+ #ifdef CONFIG_SSB_DRIVER_EXTIF
+@@ -171,8 +174,7 @@ extern void ssb_extif_get_clockcontrol(s
+ extern void ssb_extif_timing_init(struct ssb_extif *extif,
+ unsigned long ns);
+
+-extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
+- u32 ticks);
++extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
+
+ /* Extif GPIO pin access */
+ u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
+@@ -205,10 +207,52 @@ void ssb_extif_get_clockcontrol(struct s
+ }
+
+ static inline
+-void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
+- u32 ticks)
++void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
+ {
+ }
+
++static inline
++u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
++ u32 value)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
++ u32 value)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
++ u32 value)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
++ u32 value)
++{
++ return 0;
++}
++
++#ifdef CONFIG_SSB_SERIAL
++static inline int ssb_extif_serial_init(struct ssb_extif *extif,
++ struct ssb_serial_port *ports)
++{
++ return 0;
++}
++#endif /* CONFIG_SSB_SERIAL */
++
+ #endif /* CONFIG_SSB_DRIVER_EXTIF */
+ #endif /* LINUX_SSB_EXTIFCORE_H_ */
--- a/include/linux/ssb/ssb_driver_gige.h
+++ b/include/linux/ssb/ssb_driver_gige.h
@@ -2,6 +2,7 @@
+#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
+#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
+#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
-+#define SSB_SPROM8_TEMPDELTA 0x00BA
++#define SSB_SPROM8_TEMPDELTA 0x00BC
+#define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
+#define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
+#define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
+++ /dev/null
---- a/drivers/ssb/b43_pci_bridge.c
-+++ b/drivers/ssb/b43_pci_bridge.c
-@@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
-+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
- { 0, },
- };
- MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
--- /dev/null
+--- /dev/null
++++ b/include/linux/bcm47xx_wdt.h
+@@ -0,0 +1,19 @@
++#ifndef LINUX_BCM47XX_WDT_H_
++#define LINUX_BCM47XX_WDT_H_
++
++#include <linux/types.h>
++
++
++struct bcm47xx_wdt {
++ u32 (*timer_set)(struct bcm47xx_wdt *, u32);
++ u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
++ u32 max_timer_ms;
++
++ void *driver_data;
++};
++
++static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
++{
++ return wdt->driver_data;
++}
++#endif /* LINUX_BCM47XX_WDT_H_ */
+++ /dev/null
---- a/drivers/ssb/driver_chipcommon_pmu.c
-+++ b/drivers/ssb/driver_chipcommon_pmu.c
-@@ -346,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
- chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
- }
- break;
-+ case 43222:
-+ break;
- default:
- ssb_printk(KERN_ERR PFX
- "ERROR: PLL init unknown for device %04X\n",
-@@ -434,6 +436,7 @@ static void ssb_pmu_resources_init(struc
- min_msk = 0xCBB;
- break;
- case 0x4322:
-+ case 43222:
- /* We keep the default settings:
- * min_msk = 0xCBB
- * max_msk = 0x7FFFF
void bcma_bus_unregister(struct bcma_bus *bus);
int __init bcma_bus_early_register(struct bcma_bus *bus,
struct bcma_device *core_cc,
-@@ -42,14 +51,42 @@ void bcma_chipco_serial_init(struct bcma
- u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
- u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
+@@ -39,8 +48,32 @@ void bcma_chipco_serial_init(struct bcma
+ #endif /* CONFIG_BCMA_DRIVER_MIPS */
+ /* driver_chipcommon_pmu.c */
+-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
+-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
++u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
++u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
++
+#ifdef CONFIG_BCMA_SFLASH
+/* driver_chipcommon_sflash.c */
+int bcma_sflash_init(struct bcma_drv_cc *cc);
+ return 0;
+}
+#endif /* CONFIG_BCMA_NFLASH */
-+
+
#ifdef CONFIG_BCMA_HOST_PCI
/* host_pci.c */
- extern int __init bcma_host_pci_init(void);
+@@ -48,8 +81,14 @@ extern int __init bcma_host_pci_init(voi
extern void __exit bcma_host_pci_exit(void);
#endif /* CONFIG_BCMA_HOST_PCI */
+/* driver_pci.c */
+u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
++
++extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
+
#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
-void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
}
--- a/drivers/bcma/driver_chipcommon.c
+++ b/drivers/bcma/driver_chipcommon.c
-@@ -22,12 +22,9 @@ static inline u32 bcma_cc_write32_masked
+@@ -4,12 +4,15 @@
+ *
+ * Copyright 2005, Broadcom Corporation
+ * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+ #include "bcma_private.h"
++#include <linux/bcm47xx_wdt.h>
+ #include <linux/export.h>
++#include <linux/platform_device.h>
+ #include <linux/bcma/bcma.h>
+
+ static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
+@@ -22,12 +25,93 @@ static inline u32 bcma_cc_write32_masked
return value;
}
-void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
-+void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
++static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
{
- u32 leddc_on = 10;
- u32 leddc_off = 90;
--
++ if (cc->capabilities & BCMA_CC_CAP_PMU)
++ return bcma_pmu_get_alp_clock(cc);
+
- if (cc->setup_done)
++ return 20000000;
++}
++
++static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
++{
++ struct bcma_bus *bus = cc->core->bus;
++ u32 nb;
++
++ if (cc->capabilities & BCMA_CC_CAP_PMU) {
++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
++ nb = 32;
++ else if (cc->core->id.rev < 26)
++ nb = 16;
++ else
++ nb = (cc->core->id.rev >= 37) ? 32 : 24;
++ } else {
++ nb = 28;
++ }
++ if (nb == 32)
++ return 0xffffffff;
++ else
++ return (1 << nb) - 1;
++}
++
++static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
++ u32 ticks)
++{
++ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
++
++ return bcma_chipco_watchdog_timer_set(cc, ticks);
++}
++
++static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
++ u32 ms)
++{
++ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
++ u32 ticks;
++
++ ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
++ return ticks / cc->ticks_per_ms;
++}
++
++static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
++{
++ struct bcma_bus *bus = cc->core->bus;
++
++ if (cc->capabilities & BCMA_CC_CAP_PMU) {
++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
++ /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
++ return bcma_chipco_get_alp_clock(cc) / 4000;
++ else
++ /* based on 32KHz ILP clock */
++ return 32;
++ } else {
++ return bcma_chipco_get_alp_clock(cc) / 1000;
++ }
++}
++
++int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
++{
++ struct bcm47xx_wdt wdt = {};
++ struct platform_device *pdev;
++
++ wdt.driver_data = cc;
++ wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
++ wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
++ wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
++
++ pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
++ cc->core->bus->num, &wdt,
++ sizeof(wdt));
++ if (IS_ERR(pdev))
++ return PTR_ERR(pdev);
++
++ cc->watchdog = pdev;
++
++ return 0;
++}
++
++void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
++{
+ if (cc->early_setup_done)
return;
if (cc->core->id.rev >= 11)
-@@ -36,6 +33,22 @@ void bcma_core_chipcommon_init(struct bc
+@@ -36,6 +120,22 @@ void bcma_core_chipcommon_init(struct bc
if (cc->core->id.rev >= 35)
cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
if (cc->core->id.rev >= 20) {
bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
-@@ -44,7 +57,7 @@ void bcma_core_chipcommon_init(struct bc
+@@ -44,7 +144,7 @@ void bcma_core_chipcommon_init(struct bc
if (cc->capabilities & BCMA_CC_CAP_PMU)
bcma_pmu_init(cc);
if (cc->capabilities & BCMA_CC_CAP_PCTL)
if (cc->core->id.rev >= 16) {
if (cc->core->bus->sprom.leddc_on_time &&
-@@ -137,8 +150,7 @@ void bcma_chipco_serial_init(struct bcma
+@@ -56,15 +156,33 @@ void bcma_core_chipcommon_init(struct bc
+ ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
+ (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
+ }
++ cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
+
+ cc->setup_done = true;
+ }
+
+ /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
+-void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
++u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
+ {
+- /* instant NMI */
+- bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
++ u32 maxt;
++ enum bcma_clkmode clkmode;
++
++ maxt = bcma_chipco_watchdog_get_max_timer(cc);
++ if (cc->capabilities & BCMA_CC_CAP_PMU) {
++ if (ticks == 1)
++ ticks = 2;
++ else if (ticks > maxt)
++ ticks = maxt;
++ bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
++ } else {
++ clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
++ bcma_core_set_clockmode(cc->core, clkmode);
++ if (ticks > maxt)
++ ticks = maxt;
++ /* instant NMI */
++ bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
++ }
++ return ticks;
+ }
+
+ void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
+@@ -118,8 +236,7 @@ void bcma_chipco_serial_init(struct bcma
+ struct bcma_serial_port *ports = cc->serial_ports;
+
+ if (ccrev >= 11 && ccrev != 15) {
+- /* Fixed ALP clock */
+- baud_base = bcma_pmu_alp_clock(cc);
++ baud_base = bcma_chipco_get_alp_clock(cc);
+ if (ccrev >= 21) {
+ /* Turn off UART clock before switching clocksource. */
+ bcma_cc_write32(cc, BCMA_CC_CORECTL,
+@@ -137,8 +254,7 @@ void bcma_chipco_serial_init(struct bcma
| BCMA_CC_CORECTL_UARTCLKEN);
}
} else {
if (cc->pmu.rev == 1)
bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
~BCMA_CC_PMU_CTL_NOILPONW);
-@@ -174,12 +164,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
+@@ -174,37 +164,31 @@ void bcma_pmu_init(struct bcma_drv_cc *c
bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
BCMA_CC_PMU_CTL_NOILPONW);
bcma_pmu_workarounds(cc);
}
-@@ -188,23 +173,22 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
+-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
++u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
+ {
struct bcma_bus *bus = cc->core->bus;
switch (bus->chipinfo.id) {
}
return BCMA_CC_PMU_ALP_CLOCK;
}
+@@ -212,7 +196,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
+ /* Find the output of the "m" pll divider given pll controls that start with
+ * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
+ */
+-static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
++static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
+ {
+ u32 tmp, div, ndiv, p1, p2, fc;
+ struct bcma_bus *bus = cc->core->bus;
@@ -221,7 +205,8 @@ static u32 bcma_pmu_clock(struct bcma_dr
BUG_ON(!m || m > 4);
/* Detect failure in clock setting */
tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
if (tmp & 0x40000)
-@@ -247,33 +232,62 @@ static u32 bcma_pmu_clock(struct bcma_dr
+@@ -240,60 +225,95 @@ static u32 bcma_pmu_clock(struct bcma_dr
+ ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
+
+ /* Do calculation in Mhz */
+- fc = bcma_pmu_alp_clock(cc) / 1000000;
++ fc = bcma_pmu_get_alp_clock(cc) / 1000000;
+ fc = (p1 * ndiv * fc) / p2;
+
+ /* Return clock in Hertz */
return (fc / div) * 1000000;
}
-+static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
++static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
+{
+ u32 tmp, ndiv, p1div, p2div;
+ u32 clock;
+
/* query bus clock frequency for PMU-enabled chipcommon */
-u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
-+static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
++static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
{
struct bcma_bus *bus = cc->core->bus;
- case 0x4716:
- case 0x4748:
- case 47162:
-+ case BCMA_CHIP_ID_BCM4716:
-+ case BCMA_CHIP_ID_BCM4748:
-+ case BCMA_CHIP_ID_BCM47162:
- return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
- BCMA_CC_PMU5_MAINPLL_SSB);
+- return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
+- BCMA_CC_PMU5_MAINPLL_SSB);
- case 0x5356:
-+ case BCMA_CHIP_ID_BCM5356:
- return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
- BCMA_CC_PMU5_MAINPLL_SSB);
+- return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
+- BCMA_CC_PMU5_MAINPLL_SSB);
- case 0x5357:
- case 0x4749:
-+ case BCMA_CHIP_ID_BCM5357:
-+ case BCMA_CHIP_ID_BCM4749:
- return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
- BCMA_CC_PMU5_MAINPLL_SSB);
+- return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
+- BCMA_CC_PMU5_MAINPLL_SSB);
- case 0x5300:
- return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
- BCMA_CC_PMU5_MAINPLL_SSB);
- case 53572:
++ case BCMA_CHIP_ID_BCM4716:
++ case BCMA_CHIP_ID_BCM4748:
++ case BCMA_CHIP_ID_BCM47162:
++ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
++ BCMA_CC_PMU5_MAINPLL_SSB);
++ case BCMA_CHIP_ID_BCM5356:
++ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
++ BCMA_CC_PMU5_MAINPLL_SSB);
++ case BCMA_CHIP_ID_BCM5357:
++ case BCMA_CHIP_ID_BCM4749:
++ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
++ BCMA_CC_PMU5_MAINPLL_SSB);
+ case BCMA_CHIP_ID_BCM4706:
-+ return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
-+ BCMA_CC_PMU5_MAINPLL_SSB);
++ return bcma_pmu_pll_clock_bcm4706(cc,
++ BCMA_CC_PMU4706_MAINPLL_PLL0,
++ BCMA_CC_PMU5_MAINPLL_SSB);
+ case BCMA_CHIP_ID_BCM53572:
return 75000000;
default:
- pr_warn("No backplane clock specified for %04X device, "
- "pmu rev. %d, using default %d Hz\n",
- bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
-+ bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
++ bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
+ bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
}
return BCMA_CC_PMU_HT_CLOCK;
}
-@@ -283,17 +297,21 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
+
+ /* query cpu clock frequency for PMU-enabled chipcommon */
+-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
++u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
{
struct bcma_bus *bus = cc->core->bus;
+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
return 300000000;
++ /* New PMUs can have different clock for bus and CPU */
if (cc->pmu.rev >= 5) {
u32 pll;
switch (bus->chipinfo.id) {
- case 0x5356:
+ case BCMA_CHIP_ID_BCM4706:
-+ return bcma_pmu_clock_bcm4706(cc,
++ return bcma_pmu_pll_clock_bcm4706(cc,
+ BCMA_CC_PMU4706_MAINPLL_PLL0,
+ BCMA_CC_PMU5_MAINPLL_CPU);
+ case BCMA_CHIP_ID_BCM5356:
pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
break;
default:
-@@ -301,10 +319,188 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
+@@ -301,10 +321,189 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
break;
}
- /* TODO: if (bus->chipinfo.id == 0x5300)
- return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
- return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
- }
-
- return bcma_pmu_get_clockcontrol(cc);
- }
+- return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
++ return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
++ }
++
++ /* On old PMUs CPU has the same clock as the bus */
++ return bcma_pmu_get_bus_clock(cc);
++}
+
+static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
+ u32 value)
+ bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
+ bus->chipinfo.id);
+ break;
-+ }
-+
+ }
+
+- return bcma_pmu_get_clockcontrol(cc);
+ tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
+ bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
-+}
+ }
+EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
--- /dev/null
+++ b/drivers/bcma/driver_chipcommon_sflash.c
dev->bus->chipinfo.pkg == 11 &&
dev->id.id == BCMA_CORE_USB20_HOST;
}
+@@ -115,7 +115,7 @@ static void bcma_core_mips_set_irq(struc
+ bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
+ ~(1 << irqflag));
+ else
+- bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
++ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
+
+ /* assign the new one */
+ if (irq == 0) {
@@ -131,7 +131,7 @@ static void bcma_core_mips_set_irq(struc
/* backplane irq line is in use, find out who uses
* it and set user to irq 0
bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
}
}
-@@ -173,7 +173,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
+@@ -171,9 +171,9 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
+ struct bcma_bus *bus = mcore->core->bus;
+
if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
- return bcma_pmu_get_clockcpu(&bus->drv_cc);
+- return bcma_pmu_get_clockcpu(&bus->drv_cc);
++ return bcma_pmu_get_cpu_clock(&bus->drv_cc);
- pr_err("No PMU available, need this to get the cpu clock\n");
+ bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
+EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
--- a/drivers/bcma/driver_pci_host.c
+++ b/drivers/bcma/driver_pci_host.c
-@@ -2,13 +2,596 @@
+@@ -2,13 +2,600 @@
* Broadcom specific AMBA
* PCI Core in hostmode
*
+static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
+{
+ struct resource *res;
-+ int pos;
++ int pos, err;
+
+ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
+ /* This is not a device on the PCI-core bridge. */
+
+ for (pos = 0; pos < 6; pos++) {
+ res = &dev->resource[pos];
-+ if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
-+ pci_assign_resource(dev, pos);
++ if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
++ err = pci_assign_resource(dev, pos);
++ if (err)
++ pr_err("PCI: Problem fixing up the addresses on %s\n",
++ pci_name(dev));
++ }
+ }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
{
struct bcma_bus *bus = pci_get_drvdata(dev);
-@@ -265,9 +269,12 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
+@@ -234,7 +238,7 @@ static void bcma_host_pci_remove(struct
+ pci_set_drvdata(dev, NULL);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int bcma_host_pci_suspend(struct device *dev)
+ {
+ struct pci_dev *pdev = to_pci_dev(dev);
+@@ -257,17 +261,20 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
+ bcma_host_pci_resume);
+ #define BCMA_PM_OPS (&bcma_pm_ops)
+
+-#else /* CONFIG_PM */
++#else /* CONFIG_PM_SLEEP */
+
+ #define BCMA_PM_OPS NULL
+
+-#endif /* CONFIG_PM */
++#endif /* CONFIG_PM_SLEEP */
static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
switch (bus->hosttype) {
case BCMA_HOSTTYPE_PCI:
-@@ -111,41 +140,77 @@ static int bcma_register_cores(struct bc
+@@ -111,41 +140,85 @@ static int bcma_register_cores(struct bc
err = device_register(&core->dev);
if (err) {
+ bcma_err(bus, "Error registering NAND flash\n");
+ }
+#endif
++
++ if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
++ err = bcma_chipco_watchdog_register(&bus->drv_cc);
++ if (err)
++ bcma_err(bus, "Error registering watchdog driver\n");
++ }
+
return 0;
}
if (core->dev_registered)
device_unregister(&core->dev);
}
++ if (bus->hosttype == BCMA_HOSTTYPE_SOC)
++ platform_device_unregister(bus->drv_cc.watchdog);
}
-int bcma_bus_register(struct bcma_bus *bus)
if (core) {
bus->drv_cc.core = core;
bcma_core_chipcommon_init(&bus->drv_cc);
-@@ -159,30 +224,47 @@ int bcma_bus_register(struct bcma_bus *b
+@@ -159,30 +232,47 @@ int bcma_bus_register(struct bcma_bus *b
}
/* Init PCIE core */
}
int __init bcma_bus_early_register(struct bcma_bus *bus,
-@@ -196,14 +278,14 @@ int __init bcma_bus_early_register(struc
+@@ -196,14 +286,14 @@ int __init bcma_bus_early_register(struc
bcma_init_bus(bus);
match.manuf = BCMA_MANUF_BCM;
return -1;
}
-@@ -215,25 +297,25 @@ int __init bcma_bus_early_register(struc
+@@ -215,25 +305,25 @@ int __init bcma_bus_early_register(struc
/* Scan for mips core */
err = bcma_bus_scan_early(bus, &match, core_mips);
if (err) {
return 0;
}
-@@ -259,8 +341,7 @@ int bcma_bus_resume(struct bcma_bus *bus
+@@ -259,8 +349,7 @@ int bcma_bus_resume(struct bcma_bus *bus
struct bcma_device *core;
/* Init CC core */
#define BCMA_CORE_INVALID 0x700
#define BCMA_CORE_CHIPCOMMON 0x800
#define BCMA_CORE_ILINE20 0x801
-@@ -125,6 +138,36 @@ struct bcma_host_ops {
+@@ -125,6 +138,41 @@ struct bcma_host_ops {
#define BCMA_MAX_NR_CORES 16
+
+/* Chip IDs of SoCs */
+#define BCMA_CHIP_ID_BCM4706 0x5300
++#define BCMA_PKG_ID_BCM4706L 1
+#define BCMA_CHIP_ID_BCM4716 0x4716
+#define BCMA_PKG_ID_BCM4716 8
+#define BCMA_PKG_ID_BCM4717 9
+#define BCMA_CHIP_ID_BCM4749 0x4749
+#define BCMA_CHIP_ID_BCM5356 0x5356
+#define BCMA_CHIP_ID_BCM5357 0x5357
++#define BCMA_PKG_ID_BCM5358 9
++#define BCMA_PKG_ID_BCM47186 10
++#define BCMA_PKG_ID_BCM5357 11
+#define BCMA_CHIP_ID_BCM53572 53572
++#define BCMA_PKG_ID_BCM47188 9
+
struct bcma_device {
struct bcma_bus *bus;
struct bcma_device_id id;
-@@ -136,8 +179,10 @@ struct bcma_device {
+@@ -136,8 +184,10 @@ struct bcma_device {
bool dev_registered;
u8 core_index;
u32 wrap;
void __iomem *io_addr;
-@@ -175,6 +220,12 @@ int __bcma_driver_register(struct bcma_d
+@@ -175,6 +225,12 @@ int __bcma_driver_register(struct bcma_d
extern void bcma_driver_unregister(struct bcma_driver *drv);
struct bcma_bus {
/* The MMIO area. */
void __iomem *mmio;
-@@ -191,14 +242,18 @@ struct bcma_bus {
+@@ -191,14 +247,18 @@ struct bcma_bus {
struct bcma_chipinfo chipinfo;
/* We decided to share SPROM struct with SSB as long as we do not need
* any hacks for BCMA. This simplifies drivers code. */
-@@ -282,6 +337,7 @@ static inline void bcma_maskset16(struct
+@@ -282,6 +342,7 @@ static inline void bcma_maskset16(struct
bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
}
extern int bcma_core_enable(struct bcma_device *core, u32 flags);
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
-@@ -24,7 +24,7 @@
+@@ -1,6 +1,8 @@
+ #ifndef LINUX_BCMA_DRIVER_CC_H_
+ #define LINUX_BCMA_DRIVER_CC_H_
+
++#include <linux/platform_device.h>
++
+ /** ChipCommon core registers. **/
+ #define BCMA_CC_ID 0x0000
+ #define BCMA_CC_ID_ID 0x0000FFFF
+@@ -24,7 +26,7 @@
#define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
#define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
#define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
#define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
#define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
#define BCMA_PLLTYPE_NONE 0x00000000
-@@ -45,6 +45,7 @@
+@@ -45,6 +47,7 @@
#define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
#define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
#define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
#define BCMA_CC_CORECTL 0x0008
#define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
#define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
-@@ -56,6 +57,9 @@
+@@ -56,6 +59,9 @@
#define BCMA_CC_OTPS_HW_PROTECT 0x00000001
#define BCMA_CC_OTPS_SW_PROTECT 0x00000002
#define BCMA_CC_OTPS_CID_PROTECT 0x00000004
#define BCMA_CC_OTPC 0x0014 /* OTP control */
#define BCMA_CC_OTPC_RECWAIT 0xFF000000
#define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
-@@ -72,6 +76,8 @@
+@@ -72,6 +78,8 @@
#define BCMA_CC_OTPP_READ 0x40000000
#define BCMA_CC_OTPP_START 0x80000000
#define BCMA_CC_OTPP_BUSY 0x80000000
#define BCMA_CC_IRQSTAT 0x0020
#define BCMA_CC_IRQMASK 0x0024
#define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
-@@ -79,6 +85,22 @@
+@@ -79,6 +87,22 @@
#define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
#define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
#define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
#define BCMA_CC_JCMD_START 0x80000000
#define BCMA_CC_JCMD_BUSY 0x80000000
-@@ -108,10 +130,58 @@
+@@ -108,10 +132,58 @@
#define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
#define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
#define BCMA_CC_FLASHCTL 0x0040
#define BCMA_CC_BCAST_ADDR 0x0050
#define BCMA_CC_BCAST_DATA 0x0054
#define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
-@@ -181,6 +251,45 @@
+@@ -181,6 +253,45 @@
#define BCMA_CC_FLASH_CFG 0x0128
#define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
#define BCMA_CC_FLASH_WAITCNT 0x012C
/* 0x1E0 is defined as shared BCMA_CLKCTLST */
#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
#define BCMA_CC_UART0_DATA 0x0300
-@@ -240,7 +349,60 @@
+@@ -240,7 +351,60 @@
#define BCMA_CC_PLLCTL_ADDR 0x0660
#define BCMA_CC_PLLCTL_DATA 0x0664
#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
/* Divider allocation in 4716/47162/5356 */
#define BCMA_CC_PMU5_MAINPLL_CPU 1
-@@ -256,6 +418,15 @@
+@@ -256,6 +420,15 @@
/* 4706 PMU */
#define BCMA_CC_PMU4706_MAINPLL_PLL0 0
/* ALP clock on pre-PMU chips */
#define BCMA_CC_PMU_ALP_CLOCK 20000000
-@@ -284,6 +455,19 @@
+@@ -284,6 +457,19 @@
#define BCMA_CC_PPL_PCHI_OFF 5
#define BCMA_CC_PPL_PCHI_MASK 0x0000003f
/* BCM4331 ChipControl numbers. */
#define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
#define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
-@@ -297,9 +481,25 @@
+@@ -297,9 +483,25 @@
#define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
#define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
#define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
/* Data for the PMU, if available.
* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
*/
-@@ -310,11 +510,35 @@ struct bcma_chipcommon_pmu {
+@@ -310,11 +512,35 @@ struct bcma_chipcommon_pmu {
#ifdef CONFIG_BCMA_DRIVER_MIPS
struct bcma_pflash {
struct bcma_serial_port {
void *regs;
unsigned long clockspeed;
-@@ -330,11 +554,18 @@ struct bcma_drv_cc {
+@@ -330,15 +556,24 @@ struct bcma_drv_cc {
u32 capabilities;
u32 capabilities_ext;
u8 setup_done:1;
int nr_serial_ports;
struct bcma_serial_port serial_ports[4];
-@@ -355,6 +586,7 @@ struct bcma_drv_cc {
+ #endif /* CONFIG_BCMA_DRIVER_MIPS */
++ u32 ticks_per_ms;
++ struct platform_device *watchdog;
+ };
+
+ /* Register access */
+@@ -355,14 +590,14 @@ struct bcma_drv_cc {
bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
-@@ -378,6 +610,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm
+
+ void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
+
+-extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
+- u32 ticks);
++extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
+
+ void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
+
+@@ -378,6 +613,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm
/* PMU support */
extern void bcma_pmu_init(struct bcma_drv_cc *cc);
extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
u32 value);
-@@ -387,5 +620,6 @@ extern void bcma_chipco_chipctl_maskset(
+@@ -387,5 +623,6 @@ extern void bcma_chipco_chipctl_maskset(
u32 offset, u32 mask, u32 set);
extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
u32 offset, u32 mask, u32 set);
+#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
+
#endif /* LINUX_BCMA_REGS_H_ */
+--- a/drivers/net/wireless/b43/main.c
++++ b/drivers/net/wireless/b43/main.c
+@@ -4618,7 +4618,7 @@ static int b43_wireless_core_init(struct
+ switch (dev->dev->bus_type) {
+ #ifdef CONFIG_B43_BCMA
+ case B43_BUS_BCMA:
+- bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
++ bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
+ dev->dev->bdev, true);
+ break;
+ #endif
+--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
+@@ -533,7 +533,7 @@ ai_buscore_setup(struct si_info *sii, st
+
+ /* fixup necessary chip/core configurations */
+ if (!sii->pch) {
+- sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci.core);
++ sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci[0].core);
+ if (sii->pch == NULL)
+ return false;
+ }
+--- a/drivers/ssb/b43_pci_bridge.c
++++ b/drivers/ssb/b43_pci_bridge.c
+@@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
+ { 0, },
+ };
+ MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
+--- a/drivers/ssb/driver_chipcommon.c
++++ b/drivers/ssb/driver_chipcommon.c
+@@ -4,6 +4,7 @@
+ *
+ * Copyright 2005, Broadcom Corporation
+ * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+@@ -12,6 +13,7 @@
+ #include <linux/ssb/ssb_regs.h>
+ #include <linux/export.h>
+ #include <linux/pci.h>
++#include <linux/bcm47xx_wdt.h>
+
+ #include "ssb_private.h"
+
+@@ -280,6 +282,69 @@ static void calc_fast_powerup_delay(stru
+ cc->fast_pwrup_delay = tmp;
+ }
+
++static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
++{
++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
++ return ssb_pmu_get_alp_clock(cc);
++
++ return 20000000;
++}
++
++static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
++{
++ u32 nb;
++
++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
++ if (cc->dev->id.revision < 26)
++ nb = 16;
++ else
++ nb = (cc->dev->id.revision >= 37) ? 32 : 24;
++ } else {
++ nb = 28;
++ }
++ if (nb == 32)
++ return 0xffffffff;
++ else
++ return (1 << nb) - 1;
++}
++
++u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
++{
++ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
++
++ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
++ return 0;
++
++ return ssb_chipco_watchdog_timer_set(cc, ticks);
++}
++
++u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
++{
++ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
++ u32 ticks;
++
++ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
++ return 0;
++
++ ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
++ return ticks / cc->ticks_per_ms;
++}
++
++static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
++{
++ struct ssb_bus *bus = cc->dev->bus;
++
++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
++ /* based on 32KHz ILP clock */
++ return 32;
++ } else {
++ if (cc->dev->id.revision < 18)
++ return ssb_clockspeed(bus) / 1000;
++ else
++ return ssb_chipco_alp_clock(cc) / 1000;
++ }
++}
++
+ void ssb_chipcommon_init(struct ssb_chipcommon *cc)
+ {
+ if (!cc->dev)
+@@ -297,6 +362,11 @@ void ssb_chipcommon_init(struct ssb_chip
+ chipco_powercontrol_init(cc);
+ ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
+ calc_fast_powerup_delay(cc);
++
++ if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
++ cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
++ cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
++ }
+ }
+
+ void ssb_chipco_suspend(struct ssb_chipcommon *cc)
+@@ -395,10 +465,27 @@ void ssb_chipco_timing_init(struct ssb_c
+ }
+
+ /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
+-void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
++u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
+ {
+- /* instant NMI */
+- chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
++ u32 maxt;
++ enum ssb_clkmode clkmode;
++
++ maxt = ssb_chipco_watchdog_get_max_timer(cc);
++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
++ if (ticks == 1)
++ ticks = 2;
++ else if (ticks > maxt)
++ ticks = maxt;
++ chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
++ } else {
++ clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
++ ssb_chipco_set_clockmode(cc, clkmode);
++ if (ticks > maxt)
++ ticks = maxt;
++ /* instant NMI */
++ chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
++ }
++ return ticks;
+ }
+
+ void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
+@@ -473,12 +560,7 @@ int ssb_chipco_serial_init(struct ssb_ch
+ chipco_read32(cc, SSB_CHIPCO_CORECTL)
+ | SSB_CHIPCO_CORECTL_UARTCLK0);
+ } else if ((ccrev >= 11) && (ccrev != 15)) {
+- /* Fixed ALP clock */
+- baud_base = 20000000;
+- if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
+- /* FIXME: baud_base is different for devices with a PMU */
+- SSB_WARN_ON(1);
+- }
++ baud_base = ssb_chipco_alp_clock(cc);
+ div = 1;
+ if (ccrev >= 21) {
+ /* Turn off UART clock before switching clocksource. */
+--- a/drivers/ssb/driver_chipcommon_pmu.c
++++ b/drivers/ssb/driver_chipcommon_pmu.c
+@@ -346,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
+ chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
+ }
+ break;
++ case 43222:
++ break;
+ default:
+ ssb_printk(KERN_ERR PFX
+ "ERROR: PLL init unknown for device %04X\n",
+@@ -434,6 +436,7 @@ static void ssb_pmu_resources_init(struc
+ min_msk = 0xCBB;
+ break;
+ case 0x4322:
++ case 43222:
+ /* We keep the default settings:
+ * min_msk = 0xCBB
+ * max_msk = 0x7FFFF
+@@ -615,6 +618,33 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
+ EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
+ EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
+
++static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
++{
++ u32 crystalfreq;
++ const struct pmu0_plltab_entry *e = NULL;
++
++ crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
++ SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
++ e = pmu0_plltab_find_entry(crystalfreq);
++ BUG_ON(!e);
++ return e->freq * 1000;
++}
++
++u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
++{
++ struct ssb_bus *bus = cc->dev->bus;
++
++ switch (bus->chip_id) {
++ case 0x5354:
++ ssb_pmu_get_alp_clock_clk0(cc);
++ default:
++ ssb_printk(KERN_ERR PFX
++ "ERROR: PMU alp clock unknown for device %04X\n",
++ bus->chip_id);
++ return 0;
++ }
++}
++
+ u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
+ {
+ struct ssb_bus *bus = cc->dev->bus;
+--- a/drivers/ssb/driver_extif.c
++++ b/drivers/ssb/driver_extif.c
+@@ -112,10 +112,30 @@ void ssb_extif_get_clockcontrol(struct s
+ *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
+ }
+
+-void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
+- u32 ticks)
++u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
+ {
++ struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
++
++ return ssb_extif_watchdog_timer_set(extif, ticks);
++}
++
++u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
++{
++ struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
++ u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
++
++ ticks = ssb_extif_watchdog_timer_set(extif, ticks);
++
++ return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
++}
++
++u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
++{
++ if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
++ ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
+ extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
++
++ return ticks;
+ }
+
+ u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
--- a/drivers/ssb/driver_mipscore.c
+++ b/drivers/ssb/driver_mipscore.c
+@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
+ {
+ struct ssb_bus *bus = mcore->dev->bus;
+
+- if (bus->extif.dev)
++ if (ssb_extif_available(&bus->extif))
+ mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
+- else if (bus->chipco.dev)
++ else if (ssb_chipco_available(&bus->chipco))
+ mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
+ else
+ mcore->nr_serial_ports = 0;
@@ -190,16 +190,32 @@ static void ssb_mips_flash_detect(struct
{
struct ssb_bus *bus = mcore->dev->bus;
- mcore->flash_window = 0x1c000000;
- mcore->flash_window_size = 0x02000000;
+ /* When there is no chipcommon on the bus there is 4MB flash */
-+ if (!bus->chipco.dev) {
++ if (!ssb_chipco_available(&bus->chipco)) {
+ mcore->pflash.present = true;
+ mcore->pflash.buswidth = 2;
+ mcore->pflash.window = SSB_FLASH1;
}
}
+@@ -211,9 +227,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
+ if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
+ return ssb_pmu_get_cpu_clock(&bus->chipco);
+
+- if (bus->extif.dev) {
++ if (ssb_extif_available(&bus->extif)) {
+ ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
+- } else if (bus->chipco.dev) {
++ } else if (ssb_chipco_available(&bus->chipco)) {
+ ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
+ } else
+ return 0;
+@@ -249,9 +265,9 @@ void ssb_mipscore_init(struct ssb_mipsco
+ hz = 100000000;
+ ns = 1000000000 / hz;
+
+- if (bus->extif.dev)
++ if (ssb_extif_available(&bus->extif))
+ ssb_extif_timing_init(&bus->extif, ns);
+- else if (bus->chipco.dev)
++ else if (ssb_chipco_available(&bus->chipco))
+ ssb_chipco_timing_init(&bus->chipco, ns);
+
+ /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
+--- a/drivers/ssb/embedded.c
++++ b/drivers/ssb/embedded.c
+@@ -4,11 +4,13 @@
+ *
+ * Copyright 2005-2008, Broadcom Corporation
+ * Copyright 2006-2008, Michael Buesch <m@bues.ch>
++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+ #include <linux/export.h>
++#include <linux/platform_device.h>
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_embedded.h>
+ #include <linux/ssb/ssb_driver_pci.h>
+@@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bu
+ }
+ EXPORT_SYMBOL(ssb_watchdog_timer_set);
+
++int ssb_watchdog_register(struct ssb_bus *bus)
++{
++ struct bcm47xx_wdt wdt = {};
++ struct platform_device *pdev;
++
++ if (ssb_chipco_available(&bus->chipco)) {
++ wdt.driver_data = &bus->chipco;
++ wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
++ wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
++ wdt.max_timer_ms = bus->chipco.max_timer_ms;
++ } else if (ssb_extif_available(&bus->extif)) {
++ wdt.driver_data = &bus->extif;
++ wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
++ wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
++ wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
++ } else {
++ return -ENODEV;
++ }
++
++ pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
++ bus->busnumber, &wdt,
++ sizeof(wdt));
++ if (IS_ERR(pdev)) {
++ ssb_dprintk(KERN_INFO PFX
++ "can not register watchdog device, err: %li\n",
++ PTR_ERR(pdev));
++ return PTR_ERR(pdev);
++ }
++
++ bus->watchdog = pdev;
++ return 0;
++}
++
+ u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
+ {
+ unsigned long flags;
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -13,6 +13,7 @@
+ #include <linux/delay.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
++#include <linux/platform_device.h>
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_regs.h>
+ #include <linux/ssb/ssb_driver_gige.h>
+@@ -433,6 +434,11 @@ static void ssb_devices_unregister(struc
+ if (sdev->dev)
+ device_unregister(sdev->dev);
+ }
++
++#ifdef CONFIG_SSB_EMBEDDED
++ if (bus->bustype == SSB_BUSTYPE_SSB)
++ platform_device_unregister(bus->watchdog);
++#endif
+ }
+
+ void ssb_bus_unregister(struct ssb_bus *bus)
+@@ -561,6 +567,8 @@ static int __devinit ssb_attach_queued_b
+ if (err)
+ goto error;
+ ssb_pcicore_init(&bus->pcicore);
++ if (bus->bustype == SSB_BUSTYPE_SSB)
++ ssb_watchdog_register(bus);
+ ssb_bus_may_powerdown(bus);
+
+ err = ssb_devices_register(bus);
+@@ -1118,8 +1126,7 @@ static u32 ssb_tmslow_reject_bitmask(str
+ case SSB_IDLOW_SSBREV_27: /* same here */
+ return SSB_TMSLOW_REJECT; /* this is a guess */
+ default:
+- printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
+- WARN_ON(1);
++ WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
+ }
+ return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
+ }
+--- a/drivers/ssb/ssb_private.h
++++ b/drivers/ssb/ssb_private.h
+@@ -3,6 +3,7 @@
+
+ #include <linux/ssb/ssb.h>
+ #include <linux/types.h>
++#include <linux/bcm47xx_wdt.h>
+
+
+ #define PFX "ssb: "
+@@ -210,5 +211,35 @@ static inline void b43_pci_ssb_bridge_ex
+ /* driver_chipcommon_pmu.c */
+ extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
+ extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
++extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
++
++extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
++ u32 ticks);
++extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
++
++#ifdef CONFIG_SSB_DRIVER_EXTIF
++extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
++extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
++#else
++static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
++ u32 ticks)
++{
++ return 0;
++}
++static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
++ u32 ms)
++{
++ return 0;
++}
++#endif
++
++#ifdef CONFIG_SSB_EMBEDDED
++extern int ssb_watchdog_register(struct ssb_bus *bus);
++#else /* CONFIG_SSB_EMBEDDED */
++static inline int ssb_watchdog_register(struct ssb_bus *bus)
++{
++ return 0;
++}
++#endif /* CONFIG_SSB_EMBEDDED */
+
+ #endif /* LINUX_SSB_PRIVATE_H_ */
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -8,6 +8,7 @@
+ #include <linux/pci.h>
+ #include <linux/mod_devicetable.h>
+ #include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
+
+ #include <linux/ssb/ssb_regs.h>
+
+@@ -432,6 +433,7 @@ struct ssb_bus {
+ #ifdef CONFIG_SSB_EMBEDDED
+ /* Lock for GPIO register access. */
+ spinlock_t gpio_lock;
++ struct platform_device *watchdog;
+ #endif /* EMBEDDED */
+
+ /* Internal-only stuff follows. Do not touch. */
--- a/include/linux/ssb/ssb_driver_chipcommon.h
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
@@ -504,7 +504,9 @@
/* Status register bits for ST flashes */
#define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */
+@@ -589,6 +591,8 @@ struct ssb_chipcommon {
+ /* Fast Powerup Delay constant */
+ u16 fast_pwrup_delay;
+ struct ssb_chipcommon_pmu pmu;
++ u32 ticks_per_ms;
++ u32 max_timer_ms;
+ };
+
+ static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
+@@ -628,8 +632,7 @@ enum ssb_clkmode {
+ extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
+ enum ssb_clkmode mode);
+
+-extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
+- u32 ticks);
++extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
+
+ void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
+
+--- a/include/linux/ssb/ssb_driver_extif.h
++++ b/include/linux/ssb/ssb_driver_extif.h
+@@ -152,6 +152,9 @@
+ /* watchdog */
+ #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
+
++#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
++#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \
++ / (SSB_EXTIF_WATCHDOG_CLK / 1000))
+
+
+ #ifdef CONFIG_SSB_DRIVER_EXTIF
+@@ -171,8 +174,7 @@ extern void ssb_extif_get_clockcontrol(s
+ extern void ssb_extif_timing_init(struct ssb_extif *extif,
+ unsigned long ns);
+
+-extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
+- u32 ticks);
++extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
+
+ /* Extif GPIO pin access */
+ u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
+@@ -205,10 +207,52 @@ void ssb_extif_get_clockcontrol(struct s
+ }
+
+ static inline
+-void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
+- u32 ticks)
++void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
+ {
+ }
+
++static inline
++u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
++ u32 value)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
++ u32 value)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
++ u32 value)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
++ u32 value)
++{
++ return 0;
++}
++
++#ifdef CONFIG_SSB_SERIAL
++static inline int ssb_extif_serial_init(struct ssb_extif *extif,
++ struct ssb_serial_port *ports)
++{
++ return 0;
++}
++#endif /* CONFIG_SSB_SERIAL */
++
+ #endif /* CONFIG_SSB_DRIVER_EXTIF */
+ #endif /* LINUX_SSB_EXTIFCORE_H_ */
--- a/include/linux/ssb/ssb_driver_mips.h
+++ b/include/linux/ssb/ssb_driver_mips.h
@@ -13,6 +13,12 @@ struct ssb_serial_port {
};
extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
+--- a/include/linux/ssb/ssb_regs.h
++++ b/include/linux/ssb/ssb_regs.h
+@@ -485,7 +485,7 @@
+ #define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
+ #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
+ #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
+-#define SSB_SPROM8_TEMPDELTA 0x00BA
++#define SSB_SPROM8_TEMPDELTA 0x00BC
+ #define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
+ #define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
+ #define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
+++ /dev/null
---- a/drivers/ssb/b43_pci_bridge.c
-+++ b/drivers/ssb/b43_pci_bridge.c
-@@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
-+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
- { 0, },
- };
- MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
--- /dev/null
+--- /dev/null
++++ b/include/linux/bcm47xx_wdt.h
+@@ -0,0 +1,19 @@
++#ifndef LINUX_BCM47XX_WDT_H_
++#define LINUX_BCM47XX_WDT_H_
++
++#include <linux/types.h>
++
++
++struct bcm47xx_wdt {
++ u32 (*timer_set)(struct bcm47xx_wdt *, u32);
++ u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
++ u32 max_timer_ms;
++
++ void *driver_data;
++};
++
++static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
++{
++ return wdt->driver_data;
++}
++#endif /* LINUX_BCM47XX_WDT_H_ */
+++ /dev/null
---- a/drivers/ssb/driver_chipcommon_pmu.c
-+++ b/drivers/ssb/driver_chipcommon_pmu.c
-@@ -346,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
- chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
- }
- break;
-+ case 43222:
-+ break;
- default:
- ssb_printk(KERN_ERR PFX
- "ERROR: PLL init unknown for device %04X\n",
-@@ -434,6 +436,7 @@ static void ssb_pmu_resources_init(struc
- min_msk = 0xCBB;
- break;
- case 0x4322:
-+ case 43222:
- /* We keep the default settings:
- * min_msk = 0xCBB
- * max_msk = 0x7FFFF
config BCMA_DRIVER_GMAC_CMN
--- a/drivers/bcma/bcma_private.h
+++ b/drivers/bcma/bcma_private.h
-@@ -54,6 +54,7 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
+@@ -48,12 +48,13 @@ void bcma_chipco_serial_init(struct bcma
+ #endif /* CONFIG_BCMA_DRIVER_MIPS */
+
+ /* driver_chipcommon_pmu.c */
+-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
+-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
++u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
++u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
+
#ifdef CONFIG_BCMA_SFLASH
/* driver_chipcommon_sflash.c */
int bcma_sflash_init(struct bcma_drv_cc *cc);
#else
static inline int bcma_nflash_init(struct bcma_drv_cc *cc)
{
+@@ -82,6 +84,8 @@ extern void __exit bcma_host_pci_exit(vo
+ /* driver_pci.c */
+ u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
+
++extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
++
+ #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
+ bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
+ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
--- a/drivers/bcma/core.c
+++ b/drivers/bcma/core.c
@@ -65,7 +65,7 @@ void bcma_core_set_clockmode(struct bcma
BCMA_CLKCTLST_HAVEHT) {
--- a/drivers/bcma/driver_chipcommon.c
+++ b/drivers/bcma/driver_chipcommon.c
-@@ -22,12 +22,9 @@ static inline u32 bcma_cc_write32_masked
+@@ -4,12 +4,15 @@
+ *
+ * Copyright 2005, Broadcom Corporation
+ * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+ #include "bcma_private.h"
++#include <linux/bcm47xx_wdt.h>
+ #include <linux/export.h>
++#include <linux/platform_device.h>
+ #include <linux/bcma/bcma.h>
+
+ static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
+@@ -22,12 +25,93 @@ static inline u32 bcma_cc_write32_masked
return value;
}
-void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
-+void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
++static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
{
- u32 leddc_on = 10;
- u32 leddc_off = 90;
--
++ if (cc->capabilities & BCMA_CC_CAP_PMU)
++ return bcma_pmu_get_alp_clock(cc);
+
- if (cc->setup_done)
++ return 20000000;
++}
++
++static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
++{
++ struct bcma_bus *bus = cc->core->bus;
++ u32 nb;
++
++ if (cc->capabilities & BCMA_CC_CAP_PMU) {
++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
++ nb = 32;
++ else if (cc->core->id.rev < 26)
++ nb = 16;
++ else
++ nb = (cc->core->id.rev >= 37) ? 32 : 24;
++ } else {
++ nb = 28;
++ }
++ if (nb == 32)
++ return 0xffffffff;
++ else
++ return (1 << nb) - 1;
++}
++
++static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
++ u32 ticks)
++{
++ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
++
++ return bcma_chipco_watchdog_timer_set(cc, ticks);
++}
++
++static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
++ u32 ms)
++{
++ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
++ u32 ticks;
++
++ ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
++ return ticks / cc->ticks_per_ms;
++}
++
++static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
++{
++ struct bcma_bus *bus = cc->core->bus;
++
++ if (cc->capabilities & BCMA_CC_CAP_PMU) {
++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
++ /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
++ return bcma_chipco_get_alp_clock(cc) / 4000;
++ else
++ /* based on 32KHz ILP clock */
++ return 32;
++ } else {
++ return bcma_chipco_get_alp_clock(cc) / 1000;
++ }
++}
++
++int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
++{
++ struct bcm47xx_wdt wdt = {};
++ struct platform_device *pdev;
++
++ wdt.driver_data = cc;
++ wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
++ wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
++ wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
++
++ pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
++ cc->core->bus->num, &wdt,
++ sizeof(wdt));
++ if (IS_ERR(pdev))
++ return PTR_ERR(pdev);
++
++ cc->watchdog = pdev;
++
++ return 0;
++}
++
++void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
++{
+ if (cc->early_setup_done)
return;
if (cc->core->id.rev >= 11)
-@@ -36,6 +33,22 @@ void bcma_core_chipcommon_init(struct bc
+@@ -36,6 +120,22 @@ void bcma_core_chipcommon_init(struct bc
if (cc->core->id.rev >= 35)
cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
if (cc->core->id.rev >= 20) {
bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
+@@ -56,15 +156,33 @@ void bcma_core_chipcommon_init(struct bc
+ ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
+ (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
+ }
++ cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
+
+ cc->setup_done = true;
+ }
+
+ /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
+-void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
++u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
+ {
+- /* instant NMI */
+- bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
++ u32 maxt;
++ enum bcma_clkmode clkmode;
++
++ maxt = bcma_chipco_watchdog_get_max_timer(cc);
++ if (cc->capabilities & BCMA_CC_CAP_PMU) {
++ if (ticks == 1)
++ ticks = 2;
++ else if (ticks > maxt)
++ ticks = maxt;
++ bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
++ } else {
++ clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
++ bcma_core_set_clockmode(cc->core, clkmode);
++ if (ticks > maxt)
++ ticks = maxt;
++ /* instant NMI */
++ bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
++ }
++ return ticks;
+ }
+
+ void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
+@@ -118,8 +236,7 @@ void bcma_chipco_serial_init(struct bcma
+ struct bcma_serial_port *ports = cc->serial_ports;
+
+ if (ccrev >= 11 && ccrev != 15) {
+- /* Fixed ALP clock */
+- baud_base = bcma_pmu_alp_clock(cc);
++ baud_base = bcma_chipco_get_alp_clock(cc);
+ if (ccrev >= 21) {
+ /* Turn off UART clock before switching clocksource. */
+ bcma_cc_write32(cc, BCMA_CC_CORECTL,
--- a/drivers/bcma/driver_chipcommon_nflash.c
+++ b/drivers/bcma/driver_chipcommon_nflash.c
@@ -5,15 +5,40 @@
if (cc->pmu.rev == 1)
bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
~BCMA_CC_PMU_CTL_NOILPONW);
+@@ -162,7 +168,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
+ bcma_pmu_workarounds(cc);
+ }
+
+-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
++u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
+ {
+ struct bcma_bus *bus = cc->core->bus;
+
+@@ -190,7 +196,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
+ /* Find the output of the "m" pll divider given pll controls that start with
+ * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
+ */
+-static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
++static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
+ {
+ u32 tmp, div, ndiv, p1, p2, fc;
+ struct bcma_bus *bus = cc->core->bus;
+@@ -219,14 +225,14 @@ static u32 bcma_pmu_clock(struct bcma_dr
+ ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
+
+ /* Do calculation in Mhz */
+- fc = bcma_pmu_alp_clock(cc) / 1000000;
++ fc = bcma_pmu_get_alp_clock(cc) / 1000000;
+ fc = (p1 * ndiv * fc) / p2;
+
+ /* Return clock in Hertz */
+ return (fc / div) * 1000000;
+ }
+
+-static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
++static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
+ {
+ u32 tmp, ndiv, p1div, p2div;
+ u32 clock;
@@ -257,7 +263,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
}
/* query bus clock frequency for PMU-enabled chipcommon */
-u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
-+static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
++static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
+ {
+ struct bcma_bus *bus = cc->core->bus;
+
+@@ -265,40 +271,42 @@ u32 bcma_pmu_get_clockcontrol(struct bcm
+ case BCMA_CHIP_ID_BCM4716:
+ case BCMA_CHIP_ID_BCM4748:
+ case BCMA_CHIP_ID_BCM47162:
+- return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
+- BCMA_CC_PMU5_MAINPLL_SSB);
++ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
++ BCMA_CC_PMU5_MAINPLL_SSB);
+ case BCMA_CHIP_ID_BCM5356:
+- return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
+- BCMA_CC_PMU5_MAINPLL_SSB);
++ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
++ BCMA_CC_PMU5_MAINPLL_SSB);
+ case BCMA_CHIP_ID_BCM5357:
+ case BCMA_CHIP_ID_BCM4749:
+- return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
+- BCMA_CC_PMU5_MAINPLL_SSB);
++ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
++ BCMA_CC_PMU5_MAINPLL_SSB);
+ case BCMA_CHIP_ID_BCM4706:
+- return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
+- BCMA_CC_PMU5_MAINPLL_SSB);
++ return bcma_pmu_pll_clock_bcm4706(cc,
++ BCMA_CC_PMU4706_MAINPLL_PLL0,
++ BCMA_CC_PMU5_MAINPLL_SSB);
+ case BCMA_CHIP_ID_BCM53572:
+ return 75000000;
+ default:
+- bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
++ bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
+ bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
+ }
+ return BCMA_CC_PMU_HT_CLOCK;
+ }
+
+ /* query cpu clock frequency for PMU-enabled chipcommon */
+-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
++u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
{
struct bcma_bus *bus = cc->core->bus;
+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
+ return 300000000;
+
++ /* New PMUs can have different clock for bus and CPU */
+ if (cc->pmu.rev >= 5) {
+ u32 pll;
+ switch (bus->chipinfo.id) {
+ case BCMA_CHIP_ID_BCM4706:
+- return bcma_pmu_clock_bcm4706(cc,
++ return bcma_pmu_pll_clock_bcm4706(cc,
+ BCMA_CC_PMU4706_MAINPLL_PLL0,
+ BCMA_CC_PMU5_MAINPLL_CPU);
+ case BCMA_CHIP_ID_BCM5356:
+@@ -313,10 +321,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
+ break;
+ }
+
+- return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
++ return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
+ }
+
+- return bcma_pmu_get_clockcontrol(cc);
++ /* On old PMUs CPU has the same clock as the bus */
++ return bcma_pmu_get_bus_clock(cc);
+ }
+
+ static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
--- a/drivers/bcma/driver_chipcommon_sflash.c
+++ b/drivers/bcma/driver_chipcommon_sflash.c
@@ -5,15 +5,161 @@
}
--- a/drivers/bcma/driver_mips.c
+++ b/drivers/bcma/driver_mips.c
+@@ -115,7 +115,7 @@ static void bcma_core_mips_set_irq(struc
+ bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
+ ~(1 << irqflag));
+ else
+- bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
++ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
+
+ /* assign the new one */
+ if (irq == 0) {
+@@ -171,7 +171,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
+ struct bcma_bus *bus = mcore->core->bus;
+
+ if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
+- return bcma_pmu_get_clockcpu(&bus->drv_cc);
++ return bcma_pmu_get_cpu_clock(&bus->drv_cc);
+
+ bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
+ return 0;
@@ -181,47 +181,66 @@ EXPORT_SYMBOL(bcma_cpu_clock);
static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
{
register_pci_controller(&pc_host->pci_controller);
return;
}
+@@ -534,7 +538,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_
+ static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
+ {
+ struct resource *res;
+- int pos;
++ int pos, err;
+
+ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
+ /* This is not a device on the PCI-core bridge. */
+@@ -547,8 +551,12 @@ static void bcma_core_pci_fixup_addresse
+
+ for (pos = 0; pos < 6; pos++) {
+ res = &dev->resource[pos];
+- if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
+- pci_assign_resource(dev, pos);
++ if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
++ err = pci_assign_resource(dev, pos);
++ if (err)
++ pr_err("PCI: Problem fixing up the addresses on %s\n",
++ pci_name(dev));
++ }
+ }
+ }
+ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
--- a/drivers/bcma/host_pci.c
+++ b/drivers/bcma/host_pci.c
@@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct
.read8 = bcma_host_pci_read8,
.read16 = bcma_host_pci_read16,
.read32 = bcma_host_pci_read32,
+@@ -237,7 +238,7 @@ static void __devexit bcma_host_pci_remo
+ pci_set_drvdata(dev, NULL);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int bcma_host_pci_suspend(struct device *dev)
+ {
+ struct pci_dev *pdev = to_pci_dev(dev);
+@@ -260,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
+ bcma_host_pci_resume);
+ #define BCMA_PM_OPS (&bcma_pm_ops)
+
+-#else /* CONFIG_PM */
++#else /* CONFIG_PM_SLEEP */
+
+ #define BCMA_PM_OPS NULL
+
+-#endif /* CONFIG_PM */
++#endif /* CONFIG_PM_SLEEP */
+
+ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
@@ -272,6 +273,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
static void bcma_release_core_dev(struct device *dev)
{
struct bcma_device *core = container_of(dev, struct bcma_device, dev);
-@@ -136,6 +149,22 @@ static int bcma_register_cores(struct bc
+@@ -136,6 +149,28 @@ static int bcma_register_cores(struct bc
dev_id++;
}
+ bcma_err(bus, "Error registering NAND flash\n");
+ }
+#endif
++
++ if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
++ err = bcma_chipco_watchdog_register(&bus->drv_cc);
++ if (err)
++ bcma_err(bus, "Error registering watchdog driver\n");
++ }
+
return 0;
}
-@@ -166,6 +195,20 @@ int __devinit bcma_bus_register(struct b
+@@ -148,6 +183,8 @@ static void bcma_unregister_cores(struct
+ if (core->dev_registered)
+ device_unregister(&core->dev);
+ }
++ if (bus->hosttype == BCMA_HOSTTYPE_SOC)
++ platform_device_unregister(bus->drv_cc.watchdog);
+ }
+
+ int __devinit bcma_bus_register(struct bcma_bus *bus)
+@@ -166,6 +203,20 @@ int __devinit bcma_bus_register(struct b
return -1;
}
/* Init CC core */
core = bcma_find_core(bus, bcma_cc_core_id(bus));
if (core) {
-@@ -181,10 +224,17 @@ int __devinit bcma_bus_register(struct b
+@@ -181,10 +232,17 @@ int __devinit bcma_bus_register(struct b
}
/* Init PCIE core */
}
/* Init GBIT MAC COMMON core */
-@@ -194,13 +244,6 @@ int __devinit bcma_bus_register(struct b
+@@ -194,13 +252,6 @@ int __devinit bcma_bus_register(struct b
bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
}
/* Register found cores */
bcma_register_cores(bus);
-@@ -211,7 +254,17 @@ int __devinit bcma_bus_register(struct b
+@@ -211,7 +262,17 @@ int __devinit bcma_bus_register(struct b
void bcma_bus_unregister(struct bcma_bus *bus)
{
}
int __init bcma_bus_early_register(struct bcma_bus *bus,
-@@ -248,18 +301,18 @@ int __init bcma_bus_early_register(struc
+@@ -248,18 +309,18 @@ int __init bcma_bus_early_register(struc
return -1;
}
struct bcma_device;
struct bcma_bus;
-@@ -251,7 +251,7 @@ struct bcma_bus {
+@@ -157,6 +157,7 @@ struct bcma_host_ops {
+
+ /* Chip IDs of SoCs */
+ #define BCMA_CHIP_ID_BCM4706 0x5300
++#define BCMA_PKG_ID_BCM4706L 1
+ #define BCMA_CHIP_ID_BCM4716 0x4716
+ #define BCMA_PKG_ID_BCM4716 8
+ #define BCMA_PKG_ID_BCM4717 9
+@@ -166,7 +167,11 @@ struct bcma_host_ops {
+ #define BCMA_CHIP_ID_BCM4749 0x4749
+ #define BCMA_CHIP_ID_BCM5356 0x5356
+ #define BCMA_CHIP_ID_BCM5357 0x5357
++#define BCMA_PKG_ID_BCM5358 9
++#define BCMA_PKG_ID_BCM47186 10
++#define BCMA_PKG_ID_BCM5357 11
+ #define BCMA_CHIP_ID_BCM53572 53572
++#define BCMA_PKG_ID_BCM47188 9
+
+ struct bcma_device {
+ struct bcma_bus *bus;
+@@ -251,7 +256,7 @@ struct bcma_bus {
u8 num;
struct bcma_drv_cc drv_cc;
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
-@@ -100,6 +100,7 @@
+@@ -1,6 +1,8 @@
+ #ifndef LINUX_BCMA_DRIVER_CC_H_
+ #define LINUX_BCMA_DRIVER_CC_H_
+
++#include <linux/platform_device.h>
++
+ /** ChipCommon core registers. **/
+ #define BCMA_CC_ID 0x0000
+ #define BCMA_CC_ID_ID 0x0000FFFF
+@@ -100,6 +102,7 @@
#define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
#define BCMA_CC_JCMD_START 0x80000000
#define BCMA_CC_JCMD_BUSY 0x80000000
-@@ -266,6 +267,29 @@
+@@ -266,6 +269,29 @@
#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
/* 0x1E0 is defined as shared BCMA_CLKCTLST */
#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
#define BCMA_CC_UART0_DATA 0x0300
-@@ -325,6 +349,60 @@
+@@ -325,6 +351,60 @@
#define BCMA_CC_PLLCTL_ADDR 0x0660
#define BCMA_CC_PLLCTL_DATA 0x0664
#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
/* Divider allocation in 4716/47162/5356 */
#define BCMA_CC_PMU5_MAINPLL_CPU 1
-@@ -415,6 +493,13 @@
+@@ -415,6 +495,13 @@
/* 4313 Chip specific ChipControl register bits */
#define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
/* Data for the PMU, if available.
* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
*/
-@@ -425,11 +510,35 @@ struct bcma_chipcommon_pmu {
+@@ -425,11 +512,35 @@ struct bcma_chipcommon_pmu {
#ifdef CONFIG_BCMA_DRIVER_MIPS
struct bcma_pflash {
struct bcma_serial_port {
void *regs;
unsigned long clockspeed;
-@@ -445,11 +554,18 @@ struct bcma_drv_cc {
+@@ -445,15 +556,24 @@ struct bcma_drv_cc {
u32 capabilities;
u32 capabilities_ext;
u8 setup_done:1;
int nr_serial_ports;
struct bcma_serial_port serial_ports[4];
-@@ -470,6 +586,7 @@ struct bcma_drv_cc {
+ #endif /* CONFIG_BCMA_DRIVER_MIPS */
++ u32 ticks_per_ms;
++ struct platform_device *watchdog;
+ };
+
+ /* Register access */
+@@ -470,14 +590,14 @@ struct bcma_drv_cc {
bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
-@@ -493,6 +610,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm
+
+ void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
+
+-extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
+- u32 ticks);
++extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
+
+ void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
+
+@@ -493,6 +613,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm
/* PMU support */
extern void bcma_pmu_init(struct bcma_drv_cc *cc);
--- /dev/null
+--- a/drivers/ssb/b43_pci_bridge.c
++++ b/drivers/ssb/b43_pci_bridge.c
+@@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
+ { 0, },
+ };
+ MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
+--- a/drivers/ssb/driver_chipcommon.c
++++ b/drivers/ssb/driver_chipcommon.c
+@@ -4,6 +4,7 @@
+ *
+ * Copyright 2005, Broadcom Corporation
+ * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+@@ -12,6 +13,7 @@
+ #include <linux/ssb/ssb_regs.h>
+ #include <linux/export.h>
+ #include <linux/pci.h>
++#include <linux/bcm47xx_wdt.h>
+
+ #include "ssb_private.h"
+
+@@ -280,6 +282,69 @@ static void calc_fast_powerup_delay(stru
+ cc->fast_pwrup_delay = tmp;
+ }
+
++static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
++{
++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
++ return ssb_pmu_get_alp_clock(cc);
++
++ return 20000000;
++}
++
++static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
++{
++ u32 nb;
++
++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
++ if (cc->dev->id.revision < 26)
++ nb = 16;
++ else
++ nb = (cc->dev->id.revision >= 37) ? 32 : 24;
++ } else {
++ nb = 28;
++ }
++ if (nb == 32)
++ return 0xffffffff;
++ else
++ return (1 << nb) - 1;
++}
++
++u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
++{
++ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
++
++ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
++ return 0;
++
++ return ssb_chipco_watchdog_timer_set(cc, ticks);
++}
++
++u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
++{
++ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
++ u32 ticks;
++
++ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
++ return 0;
++
++ ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
++ return ticks / cc->ticks_per_ms;
++}
++
++static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
++{
++ struct ssb_bus *bus = cc->dev->bus;
++
++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
++ /* based on 32KHz ILP clock */
++ return 32;
++ } else {
++ if (cc->dev->id.revision < 18)
++ return ssb_clockspeed(bus) / 1000;
++ else
++ return ssb_chipco_alp_clock(cc) / 1000;
++ }
++}
++
+ void ssb_chipcommon_init(struct ssb_chipcommon *cc)
+ {
+ if (!cc->dev)
+@@ -297,6 +362,11 @@ void ssb_chipcommon_init(struct ssb_chip
+ chipco_powercontrol_init(cc);
+ ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
+ calc_fast_powerup_delay(cc);
++
++ if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
++ cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
++ cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
++ }
+ }
+
+ void ssb_chipco_suspend(struct ssb_chipcommon *cc)
+@@ -395,10 +465,27 @@ void ssb_chipco_timing_init(struct ssb_c
+ }
+
+ /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
+-void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
++u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
+ {
+- /* instant NMI */
+- chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
++ u32 maxt;
++ enum ssb_clkmode clkmode;
++
++ maxt = ssb_chipco_watchdog_get_max_timer(cc);
++ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
++ if (ticks == 1)
++ ticks = 2;
++ else if (ticks > maxt)
++ ticks = maxt;
++ chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
++ } else {
++ clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
++ ssb_chipco_set_clockmode(cc, clkmode);
++ if (ticks > maxt)
++ ticks = maxt;
++ /* instant NMI */
++ chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
++ }
++ return ticks;
+ }
+
+ void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
+@@ -473,12 +560,7 @@ int ssb_chipco_serial_init(struct ssb_ch
+ chipco_read32(cc, SSB_CHIPCO_CORECTL)
+ | SSB_CHIPCO_CORECTL_UARTCLK0);
+ } else if ((ccrev >= 11) && (ccrev != 15)) {
+- /* Fixed ALP clock */
+- baud_base = 20000000;
+- if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
+- /* FIXME: baud_base is different for devices with a PMU */
+- SSB_WARN_ON(1);
+- }
++ baud_base = ssb_chipco_alp_clock(cc);
+ div = 1;
+ if (ccrev >= 21) {
+ /* Turn off UART clock before switching clocksource. */
+--- a/drivers/ssb/driver_chipcommon_pmu.c
++++ b/drivers/ssb/driver_chipcommon_pmu.c
+@@ -346,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
+ chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
+ }
+ break;
++ case 43222:
++ break;
+ default:
+ ssb_printk(KERN_ERR PFX
+ "ERROR: PLL init unknown for device %04X\n",
+@@ -434,6 +436,7 @@ static void ssb_pmu_resources_init(struc
+ min_msk = 0xCBB;
+ break;
+ case 0x4322:
++ case 43222:
+ /* We keep the default settings:
+ * min_msk = 0xCBB
+ * max_msk = 0x7FFFF
+@@ -615,6 +618,33 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
+ EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
+ EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
+
++static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
++{
++ u32 crystalfreq;
++ const struct pmu0_plltab_entry *e = NULL;
++
++ crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
++ SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
++ e = pmu0_plltab_find_entry(crystalfreq);
++ BUG_ON(!e);
++ return e->freq * 1000;
++}
++
++u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
++{
++ struct ssb_bus *bus = cc->dev->bus;
++
++ switch (bus->chip_id) {
++ case 0x5354:
++ ssb_pmu_get_alp_clock_clk0(cc);
++ default:
++ ssb_printk(KERN_ERR PFX
++ "ERROR: PMU alp clock unknown for device %04X\n",
++ bus->chip_id);
++ return 0;
++ }
++}
++
+ u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
+ {
+ struct ssb_bus *bus = cc->dev->bus;
+--- a/drivers/ssb/driver_extif.c
++++ b/drivers/ssb/driver_extif.c
+@@ -112,10 +112,30 @@ void ssb_extif_get_clockcontrol(struct s
+ *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
+ }
+
+-void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
+- u32 ticks)
++u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
+ {
++ struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
++
++ return ssb_extif_watchdog_timer_set(extif, ticks);
++}
++
++u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
++{
++ struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
++ u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
++
++ ticks = ssb_extif_watchdog_timer_set(extif, ticks);
++
++ return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
++}
++
++u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
++{
++ if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
++ ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
+ extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
++
++ return ticks;
+ }
+
+ u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
+--- a/drivers/ssb/driver_mipscore.c
++++ b/drivers/ssb/driver_mipscore.c
+@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
+ {
+ struct ssb_bus *bus = mcore->dev->bus;
+
+- if (bus->extif.dev)
++ if (ssb_extif_available(&bus->extif))
+ mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
+- else if (bus->chipco.dev)
++ else if (ssb_chipco_available(&bus->chipco))
+ mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
+ else
+ mcore->nr_serial_ports = 0;
+@@ -191,10 +191,11 @@ static void ssb_mips_flash_detect(struct
+ struct ssb_bus *bus = mcore->dev->bus;
+
+ /* When there is no chipcommon on the bus there is 4MB flash */
+- if (!bus->chipco.dev) {
+- mcore->flash_buswidth = 2;
+- mcore->flash_window = SSB_FLASH1;
+- mcore->flash_window_size = SSB_FLASH1_SZ;
++ if (!ssb_chipco_available(&bus->chipco)) {
++ mcore->pflash.present = true;
++ mcore->pflash.buswidth = 2;
++ mcore->pflash.window = SSB_FLASH1;
++ mcore->pflash.window_size = SSB_FLASH1_SZ;
+ return;
+ }
+
+@@ -206,13 +207,14 @@ static void ssb_mips_flash_detect(struct
+ break;
+ case SSB_CHIPCO_FLASHT_PARA:
+ pr_debug("Found parallel flash\n");
+- mcore->flash_window = SSB_FLASH2;
+- mcore->flash_window_size = SSB_FLASH2_SZ;
++ mcore->pflash.present = true;
++ mcore->pflash.window = SSB_FLASH2;
++ mcore->pflash.window_size = SSB_FLASH2_SZ;
+ if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
+ & SSB_CHIPCO_CFG_DS16) == 0)
+- mcore->flash_buswidth = 1;
++ mcore->pflash.buswidth = 1;
+ else
+- mcore->flash_buswidth = 2;
++ mcore->pflash.buswidth = 2;
+ break;
+ }
+ }
+@@ -225,9 +227,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
+ if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
+ return ssb_pmu_get_cpu_clock(&bus->chipco);
+
+- if (bus->extif.dev) {
++ if (ssb_extif_available(&bus->extif)) {
+ ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
+- } else if (bus->chipco.dev) {
++ } else if (ssb_chipco_available(&bus->chipco)) {
+ ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
+ } else
+ return 0;
+@@ -263,9 +265,9 @@ void ssb_mipscore_init(struct ssb_mipsco
+ hz = 100000000;
+ ns = 1000000000 / hz;
+
+- if (bus->extif.dev)
++ if (ssb_extif_available(&bus->extif))
+ ssb_extif_timing_init(&bus->extif, ns);
+- else if (bus->chipco.dev)
++ else if (ssb_chipco_available(&bus->chipco))
+ ssb_chipco_timing_init(&bus->chipco, ns);
+
+ /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
+--- a/drivers/ssb/embedded.c
++++ b/drivers/ssb/embedded.c
+@@ -4,11 +4,13 @@
+ *
+ * Copyright 2005-2008, Broadcom Corporation
+ * Copyright 2006-2008, Michael Buesch <m@bues.ch>
++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+ #include <linux/export.h>
++#include <linux/platform_device.h>
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_embedded.h>
+ #include <linux/ssb/ssb_driver_pci.h>
+@@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bu
+ }
+ EXPORT_SYMBOL(ssb_watchdog_timer_set);
+
++int ssb_watchdog_register(struct ssb_bus *bus)
++{
++ struct bcm47xx_wdt wdt = {};
++ struct platform_device *pdev;
++
++ if (ssb_chipco_available(&bus->chipco)) {
++ wdt.driver_data = &bus->chipco;
++ wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
++ wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
++ wdt.max_timer_ms = bus->chipco.max_timer_ms;
++ } else if (ssb_extif_available(&bus->extif)) {
++ wdt.driver_data = &bus->extif;
++ wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
++ wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
++ wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
++ } else {
++ return -ENODEV;
++ }
++
++ pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
++ bus->busnumber, &wdt,
++ sizeof(wdt));
++ if (IS_ERR(pdev)) {
++ ssb_dprintk(KERN_INFO PFX
++ "can not register watchdog device, err: %li\n",
++ PTR_ERR(pdev));
++ return PTR_ERR(pdev);
++ }
++
++ bus->watchdog = pdev;
++ return 0;
++}
++
+ u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
+ {
+ unsigned long flags;
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -13,6 +13,7 @@
+ #include <linux/delay.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
++#include <linux/platform_device.h>
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_regs.h>
+ #include <linux/ssb/ssb_driver_gige.h>
+@@ -433,6 +434,11 @@ static void ssb_devices_unregister(struc
+ if (sdev->dev)
+ device_unregister(sdev->dev);
+ }
++
++#ifdef CONFIG_SSB_EMBEDDED
++ if (bus->bustype == SSB_BUSTYPE_SSB)
++ platform_device_unregister(bus->watchdog);
++#endif
+ }
+
+ void ssb_bus_unregister(struct ssb_bus *bus)
+@@ -561,6 +567,8 @@ static int __devinit ssb_attach_queued_b
+ if (err)
+ goto error;
+ ssb_pcicore_init(&bus->pcicore);
++ if (bus->bustype == SSB_BUSTYPE_SSB)
++ ssb_watchdog_register(bus);
+ ssb_bus_may_powerdown(bus);
+
+ err = ssb_devices_register(bus);
+@@ -1118,8 +1126,7 @@ static u32 ssb_tmslow_reject_bitmask(str
+ case SSB_IDLOW_SSBREV_27: /* same here */
+ return SSB_TMSLOW_REJECT; /* this is a guess */
+ default:
+- printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
+- WARN_ON(1);
++ WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
+ }
+ return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
+ }
+--- a/drivers/ssb/ssb_private.h
++++ b/drivers/ssb/ssb_private.h
+@@ -3,6 +3,7 @@
+
+ #include <linux/ssb/ssb.h>
+ #include <linux/types.h>
++#include <linux/bcm47xx_wdt.h>
+
+
+ #define PFX "ssb: "
+@@ -210,5 +211,35 @@ static inline void b43_pci_ssb_bridge_ex
+ /* driver_chipcommon_pmu.c */
+ extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
+ extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
++extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
++
++extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
++ u32 ticks);
++extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
++
++#ifdef CONFIG_SSB_DRIVER_EXTIF
++extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
++extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
++#else
++static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
++ u32 ticks)
++{
++ return 0;
++}
++static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
++ u32 ms)
++{
++ return 0;
++}
++#endif
++
++#ifdef CONFIG_SSB_EMBEDDED
++extern int ssb_watchdog_register(struct ssb_bus *bus);
++#else /* CONFIG_SSB_EMBEDDED */
++static inline int ssb_watchdog_register(struct ssb_bus *bus)
++{
++ return 0;
++}
++#endif /* CONFIG_SSB_EMBEDDED */
+
+ #endif /* LINUX_SSB_PRIVATE_H_ */
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -8,6 +8,7 @@
+ #include <linux/pci.h>
+ #include <linux/mod_devicetable.h>
+ #include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
+
+ #include <linux/ssb/ssb_regs.h>
+
+@@ -432,6 +433,7 @@ struct ssb_bus {
+ #ifdef CONFIG_SSB_EMBEDDED
+ /* Lock for GPIO register access. */
+ spinlock_t gpio_lock;
++ struct platform_device *watchdog;
+ #endif /* EMBEDDED */
+
+ /* Internal-only stuff follows. Do not touch. */
+--- a/include/linux/ssb/ssb_driver_chipcommon.h
++++ b/include/linux/ssb/ssb_driver_chipcommon.h
+@@ -591,6 +591,8 @@ struct ssb_chipcommon {
+ /* Fast Powerup Delay constant */
+ u16 fast_pwrup_delay;
+ struct ssb_chipcommon_pmu pmu;
++ u32 ticks_per_ms;
++ u32 max_timer_ms;
+ };
+
+ static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
+@@ -630,8 +632,7 @@ enum ssb_clkmode {
+ extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
+ enum ssb_clkmode mode);
+
+-extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
+- u32 ticks);
++extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
+
+ void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
+
+--- a/include/linux/ssb/ssb_driver_extif.h
++++ b/include/linux/ssb/ssb_driver_extif.h
+@@ -152,6 +152,9 @@
+ /* watchdog */
+ #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
+
++#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
++#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \
++ / (SSB_EXTIF_WATCHDOG_CLK / 1000))
+
+
+ #ifdef CONFIG_SSB_DRIVER_EXTIF
+@@ -171,8 +174,7 @@ extern void ssb_extif_get_clockcontrol(s
+ extern void ssb_extif_timing_init(struct ssb_extif *extif,
+ unsigned long ns);
+
+-extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
+- u32 ticks);
++extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
+
+ /* Extif GPIO pin access */
+ u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
+@@ -205,10 +207,52 @@ void ssb_extif_get_clockcontrol(struct s
+ }
+
+ static inline
+-void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
+- u32 ticks)
++void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
+ {
+ }
+
++static inline
++u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
++ u32 value)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
++ u32 value)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
++ u32 value)
++{
++ return 0;
++}
++
++static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
++ u32 value)
++{
++ return 0;
++}
++
++#ifdef CONFIG_SSB_SERIAL
++static inline int ssb_extif_serial_init(struct ssb_extif *extif,
++ struct ssb_serial_port *ports)
++{
++ return 0;
++}
++#endif /* CONFIG_SSB_SERIAL */
++
+ #endif /* CONFIG_SSB_DRIVER_EXTIF */
+ #endif /* LINUX_SSB_EXTIFCORE_H_ */
+--- a/include/linux/ssb/ssb_driver_mips.h
++++ b/include/linux/ssb/ssb_driver_mips.h
+@@ -13,6 +13,12 @@ struct ssb_serial_port {
+ unsigned int reg_shift;
+ };
+
++struct ssb_pflash {
++ bool present;
++ u8 buswidth;
++ u32 window;
++ u32 window_size;
++};
+
+ struct ssb_mipscore {
+ struct ssb_device *dev;
+@@ -20,9 +26,7 @@ struct ssb_mipscore {
+ int nr_serial_ports;
+ struct ssb_serial_port serial_ports[4];
+
+- u8 flash_buswidth;
+- u32 flash_window;
+- u32 flash_window_size;
++ struct ssb_pflash pflash;
+ };
+
+ extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
+--- a/include/linux/ssb/ssb_regs.h
++++ b/include/linux/ssb/ssb_regs.h
+@@ -485,7 +485,7 @@
+ #define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
+ #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
+ #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
+-#define SSB_SPROM8_TEMPDELTA 0x00BA
++#define SSB_SPROM8_TEMPDELTA 0x00BC
+ #define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
+ #define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
+ #define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
+++ /dev/null
---- a/drivers/ssb/b43_pci_bridge.c
-+++ b/drivers/ssb/b43_pci_bridge.c
-@@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
-+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
- { 0, },
- };
- MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
--- /dev/null
+--- /dev/null
++++ b/include/linux/bcm47xx_wdt.h
+@@ -0,0 +1,19 @@
++#ifndef LINUX_BCM47XX_WDT_H_
++#define LINUX_BCM47XX_WDT_H_
++
++#include <linux/types.h>
++
++
++struct bcm47xx_wdt {
++ u32 (*timer_set)(struct bcm47xx_wdt *, u32);
++ u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
++ u32 max_timer_ms;
++
++ void *driver_data;
++};
++
++static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
++{
++ return wdt->driver_data;
++}
++#endif /* LINUX_BCM47XX_WDT_H_ */
+++ /dev/null
---- a/drivers/ssb/driver_chipcommon_pmu.c
-+++ b/drivers/ssb/driver_chipcommon_pmu.c
-@@ -346,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
- chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
- }
- break;
-+ case 43222:
-+ break;
- default:
- ssb_printk(KERN_ERR PFX
- "ERROR: PLL init unknown for device %04X\n",
-@@ -434,6 +436,7 @@ static void ssb_pmu_resources_init(struc
- min_msk = 0xCBB;
- break;
- case 0x4322:
-+ case 43222:
- /* We keep the default settings:
- * min_msk = 0xCBB
- * max_msk = 0x7FFFF
--- /dev/null
+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -43,8 +43,8 @@ static void early_nvram_init(void)
+ #ifdef CONFIG_BCM47XX_SSB
+ case BCM47XX_BUS_TYPE_SSB:
+ mcore_ssb = &bcm47xx_bus.ssb.mipscore;
+- base = mcore_ssb->flash_window;
+- lim = mcore_ssb->flash_window_size;
++ base = mcore_ssb->pflash.window;
++ lim = mcore_ssb->pflash.window_size;
+ break;
+ #endif
+ #ifdef CONFIG_BCM47XX_BCMA
+--- a/arch/mips/bcm47xx/wgt634u.c
++++ b/arch/mips/bcm47xx/wgt634u.c
+@@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
+ SSB_CHIPCO_IRQ_GPIO);
+ }
+
+- wgt634u_flash_data.width = mcore->flash_buswidth;
+- wgt634u_flash_resource.start = mcore->flash_window;
+- wgt634u_flash_resource.end = mcore->flash_window
+- + mcore->flash_window_size
++ wgt634u_flash_data.width = mcore->pflash.buswidth;
++ wgt634u_flash_resource.start = mcore->pflash.window;
++ wgt634u_flash_resource.end = mcore->pflash.window
++ + mcore->pflash.window_size
+ - 1;
+ return platform_add_devices(wgt634u_devices,
+ ARRAY_SIZE(wgt634u_devices));
+--- a/drivers/bcma/bcma_private.h
++++ b/drivers/bcma/bcma_private.h
+@@ -48,8 +48,8 @@ void bcma_chipco_serial_init(struct bcma
+ #endif /* CONFIG_BCMA_DRIVER_MIPS */
+
+ /* driver_chipcommon_pmu.c */
+-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
+-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
++u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
++u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
+
+ #ifdef CONFIG_BCMA_SFLASH
+ /* driver_chipcommon_sflash.c */
+@@ -84,6 +84,8 @@ extern void __exit bcma_host_pci_exit(vo
+ /* driver_pci.c */
+ u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
+
++extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
++
+ #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
+ bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
+ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
+--- a/drivers/bcma/driver_chipcommon.c
++++ b/drivers/bcma/driver_chipcommon.c
+@@ -4,12 +4,15 @@
+ *
+ * Copyright 2005, Broadcom Corporation
+ * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+ #include "bcma_private.h"
++#include <linux/bcm47xx_wdt.h>
+ #include <linux/export.h>
++#include <linux/platform_device.h>
+ #include <linux/bcma/bcma.h>
+
+ static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
+@@ -22,12 +25,93 @@ static inline u32 bcma_cc_write32_masked
+ return value;
+ }
+
+-void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
++static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
+ {
+- u32 leddc_on = 10;
+- u32 leddc_off = 90;
++ if (cc->capabilities & BCMA_CC_CAP_PMU)
++ return bcma_pmu_get_alp_clock(cc);
+
+- if (cc->setup_done)
++ return 20000000;
++}
++
++static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
++{
++ struct bcma_bus *bus = cc->core->bus;
++ u32 nb;
++
++ if (cc->capabilities & BCMA_CC_CAP_PMU) {
++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
++ nb = 32;
++ else if (cc->core->id.rev < 26)
++ nb = 16;
++ else
++ nb = (cc->core->id.rev >= 37) ? 32 : 24;
++ } else {
++ nb = 28;
++ }
++ if (nb == 32)
++ return 0xffffffff;
++ else
++ return (1 << nb) - 1;
++}
++
++static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
++ u32 ticks)
++{
++ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
++
++ return bcma_chipco_watchdog_timer_set(cc, ticks);
++}
++
++static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
++ u32 ms)
++{
++ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
++ u32 ticks;
++
++ ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
++ return ticks / cc->ticks_per_ms;
++}
++
++static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
++{
++ struct bcma_bus *bus = cc->core->bus;
++
++ if (cc->capabilities & BCMA_CC_CAP_PMU) {
++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
++ /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
++ return bcma_chipco_get_alp_clock(cc) / 4000;
++ else
++ /* based on 32KHz ILP clock */
++ return 32;
++ } else {
++ return bcma_chipco_get_alp_clock(cc) / 1000;
++ }
++}
++
++int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
++{
++ struct bcm47xx_wdt wdt = {};
++ struct platform_device *pdev;
++
++ wdt.driver_data = cc;
++ wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
++ wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
++ wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
++
++ pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
++ cc->core->bus->num, &wdt,
++ sizeof(wdt));
++ if (IS_ERR(pdev))
++ return PTR_ERR(pdev);
++
++ cc->watchdog = pdev;
++
++ return 0;
++}
++
++void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
++{
++ if (cc->early_setup_done)
+ return;
+
+ if (cc->core->id.rev >= 11)
+@@ -36,6 +120,22 @@ void bcma_core_chipcommon_init(struct bc
+ if (cc->core->id.rev >= 35)
+ cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
+
++ if (cc->capabilities & BCMA_CC_CAP_PMU)
++ bcma_pmu_early_init(cc);
++
++ cc->early_setup_done = true;
++}
++
++void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
++{
++ u32 leddc_on = 10;
++ u32 leddc_off = 90;
++
++ if (cc->setup_done)
++ return;
++
++ bcma_core_chipcommon_early_init(cc);
++
+ if (cc->core->id.rev >= 20) {
+ bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
+ bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
+@@ -56,15 +156,33 @@ void bcma_core_chipcommon_init(struct bc
+ ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
+ (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
+ }
++ cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
+
+ cc->setup_done = true;
+ }
+
+ /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
+-void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
++u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
+ {
+- /* instant NMI */
+- bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
++ u32 maxt;
++ enum bcma_clkmode clkmode;
++
++ maxt = bcma_chipco_watchdog_get_max_timer(cc);
++ if (cc->capabilities & BCMA_CC_CAP_PMU) {
++ if (ticks == 1)
++ ticks = 2;
++ else if (ticks > maxt)
++ ticks = maxt;
++ bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
++ } else {
++ clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
++ bcma_core_set_clockmode(cc->core, clkmode);
++ if (ticks > maxt)
++ ticks = maxt;
++ /* instant NMI */
++ bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
++ }
++ return ticks;
+ }
+
+ void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
+@@ -118,8 +236,7 @@ void bcma_chipco_serial_init(struct bcma
+ struct bcma_serial_port *ports = cc->serial_ports;
+
+ if (ccrev >= 11 && ccrev != 15) {
+- /* Fixed ALP clock */
+- baud_base = bcma_pmu_alp_clock(cc);
++ baud_base = bcma_chipco_get_alp_clock(cc);
+ if (ccrev >= 21) {
+ /* Turn off UART clock before switching clocksource. */
+ bcma_cc_write32(cc, BCMA_CC_CORECTL,
+--- a/drivers/bcma/driver_chipcommon_nflash.c
++++ b/drivers/bcma/driver_chipcommon_nflash.c
+@@ -32,6 +32,9 @@ int bcma_nflash_init(struct bcma_drv_cc
+ }
+
+ cc->nflash.present = true;
++ if (cc->core->id.rev == 38 &&
++ (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
++ cc->nflash.boot = true;
+
+ /* Prepare platform device, but don't register it yet. It's too early,
+ * malloc (required by device_private_init) is not available yet. */
+--- a/drivers/bcma/driver_chipcommon_pmu.c
++++ b/drivers/bcma/driver_chipcommon_pmu.c
+@@ -144,7 +144,7 @@ static void bcma_pmu_workarounds(struct
+ }
+ }
+
+-void bcma_pmu_init(struct bcma_drv_cc *cc)
++void bcma_pmu_early_init(struct bcma_drv_cc *cc)
+ {
+ u32 pmucap;
+
+@@ -153,7 +153,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
+
+ bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
+ cc->pmu.rev, pmucap);
++}
+
++void bcma_pmu_init(struct bcma_drv_cc *cc)
++{
+ if (cc->pmu.rev == 1)
+ bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
+ ~BCMA_CC_PMU_CTL_NOILPONW);
+@@ -165,7 +168,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
+ bcma_pmu_workarounds(cc);
+ }
+
+-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
++u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
+ {
+ struct bcma_bus *bus = cc->core->bus;
+
+@@ -193,7 +196,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
+ /* Find the output of the "m" pll divider given pll controls that start with
+ * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
+ */
+-static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
++static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
+ {
+ u32 tmp, div, ndiv, p1, p2, fc;
+ struct bcma_bus *bus = cc->core->bus;
+@@ -222,14 +225,14 @@ static u32 bcma_pmu_clock(struct bcma_dr
+ ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
+
+ /* Do calculation in Mhz */
+- fc = bcma_pmu_alp_clock(cc) / 1000000;
++ fc = bcma_pmu_get_alp_clock(cc) / 1000000;
+ fc = (p1 * ndiv * fc) / p2;
+
+ /* Return clock in Hertz */
+ return (fc / div) * 1000000;
+ }
+
+-static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
++static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
+ {
+ u32 tmp, ndiv, p1div, p2div;
+ u32 clock;
+@@ -260,7 +263,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
+ }
+
+ /* query bus clock frequency for PMU-enabled chipcommon */
+-static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
++static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
+ {
+ struct bcma_bus *bus = cc->core->bus;
+
+@@ -268,40 +271,42 @@ static u32 bcma_pmu_get_clockcontrol(str
+ case BCMA_CHIP_ID_BCM4716:
+ case BCMA_CHIP_ID_BCM4748:
+ case BCMA_CHIP_ID_BCM47162:
+- return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
+- BCMA_CC_PMU5_MAINPLL_SSB);
++ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
++ BCMA_CC_PMU5_MAINPLL_SSB);
+ case BCMA_CHIP_ID_BCM5356:
+- return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
+- BCMA_CC_PMU5_MAINPLL_SSB);
++ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
++ BCMA_CC_PMU5_MAINPLL_SSB);
+ case BCMA_CHIP_ID_BCM5357:
+ case BCMA_CHIP_ID_BCM4749:
+- return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
+- BCMA_CC_PMU5_MAINPLL_SSB);
++ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
++ BCMA_CC_PMU5_MAINPLL_SSB);
+ case BCMA_CHIP_ID_BCM4706:
+- return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
+- BCMA_CC_PMU5_MAINPLL_SSB);
++ return bcma_pmu_pll_clock_bcm4706(cc,
++ BCMA_CC_PMU4706_MAINPLL_PLL0,
++ BCMA_CC_PMU5_MAINPLL_SSB);
+ case BCMA_CHIP_ID_BCM53572:
+ return 75000000;
+ default:
+- bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
++ bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
+ bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
+ }
+ return BCMA_CC_PMU_HT_CLOCK;
+ }
+
+ /* query cpu clock frequency for PMU-enabled chipcommon */
+-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
++u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
+ {
+ struct bcma_bus *bus = cc->core->bus;
+
+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
+ return 300000000;
+
++ /* New PMUs can have different clock for bus and CPU */
+ if (cc->pmu.rev >= 5) {
+ u32 pll;
+ switch (bus->chipinfo.id) {
+ case BCMA_CHIP_ID_BCM4706:
+- return bcma_pmu_clock_bcm4706(cc,
++ return bcma_pmu_pll_clock_bcm4706(cc,
+ BCMA_CC_PMU4706_MAINPLL_PLL0,
+ BCMA_CC_PMU5_MAINPLL_CPU);
+ case BCMA_CHIP_ID_BCM5356:
+@@ -316,10 +321,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
+ break;
+ }
+
+- return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
++ return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
+ }
+
+- return bcma_pmu_get_clockcontrol(cc);
++ /* On old PMUs CPU has the same clock as the bus */
++ return bcma_pmu_get_bus_clock(cc);
+ }
+
+ static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
+--- a/drivers/bcma/driver_chipcommon_sflash.c
++++ b/drivers/bcma/driver_chipcommon_sflash.c
+@@ -12,7 +12,7 @@
+
+ static struct resource bcma_sflash_resource = {
+ .name = "bcma_sflash",
+- .start = BCMA_SFLASH,
++ .start = BCMA_SOC_FLASH2,
+ .end = 0,
+ .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
+ };
+@@ -31,15 +31,42 @@ struct bcma_sflash_tbl_e {
+ };
+
+ static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
+- { "", 0x14, 0x10000, 32, },
++ { "M25P20", 0x11, 0x10000, 4, },
++ { "M25P40", 0x12, 0x10000, 8, },
++
++ { "M25P16", 0x14, 0x10000, 32, },
++ { "M25P32", 0x14, 0x10000, 64, },
++ { "M25P64", 0x16, 0x10000, 128, },
++ { "M25FL128", 0x17, 0x10000, 256, },
+ { 0 },
+ };
+
+ static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
++ { "SST25WF512", 1, 0x1000, 16, },
++ { "SST25VF512", 0x48, 0x1000, 16, },
++ { "SST25WF010", 2, 0x1000, 32, },
++ { "SST25VF010", 0x49, 0x1000, 32, },
++ { "SST25WF020", 3, 0x1000, 64, },
++ { "SST25VF020", 0x43, 0x1000, 64, },
++ { "SST25WF040", 4, 0x1000, 128, },
++ { "SST25VF040", 0x44, 0x1000, 128, },
++ { "SST25VF040B", 0x8d, 0x1000, 128, },
++ { "SST25WF080", 5, 0x1000, 256, },
++ { "SST25VF080B", 0x8e, 0x1000, 256, },
++ { "SST25VF016", 0x41, 0x1000, 512, },
++ { "SST25VF032", 0x4a, 0x1000, 1024, },
++ { "SST25VF064", 0x4b, 0x1000, 2048, },
+ { 0 },
+ };
+
+ static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
++ { "AT45DB011", 0xc, 256, 512, },
++ { "AT45DB021", 0x14, 256, 1024, },
++ { "AT45DB041", 0x1c, 256, 2048, },
++ { "AT45DB081", 0x24, 256, 4096, },
++ { "AT45DB161", 0x2c, 512, 4096, },
++ { "AT45DB321", 0x34, 512, 8192, },
++ { "AT45DB642", 0x3c, 1024, 8192, },
+ { 0 },
+ };
+
+@@ -84,6 +111,8 @@ int bcma_sflash_init(struct bcma_drv_cc
+ break;
+ }
+ break;
++ case 0x13:
++ return -ENOTSUPP;
+ default:
+ for (e = bcma_sflash_st_tbl; e->name; e++) {
+ if (e->id == id)
+@@ -116,7 +145,7 @@ int bcma_sflash_init(struct bcma_drv_cc
+ return -ENOTSUPP;
+ }
+
+- sflash->window = BCMA_SFLASH;
++ sflash->window = BCMA_SOC_FLASH2;
+ sflash->blocksize = e->blocksize;
+ sflash->numblocks = e->numblocks;
+ sflash->size = sflash->blocksize * sflash->numblocks;
+--- a/drivers/bcma/driver_mips.c
++++ b/drivers/bcma/driver_mips.c
+@@ -115,7 +115,7 @@ static void bcma_core_mips_set_irq(struc
+ bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
+ ~(1 << irqflag));
+ else
+- bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
++ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
+
+ /* assign the new one */
+ if (irq == 0) {
+@@ -171,7 +171,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
+ struct bcma_bus *bus = mcore->core->bus;
+
+ if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
+- return bcma_pmu_get_clockcpu(&bus->drv_cc);
++ return bcma_pmu_get_cpu_clock(&bus->drv_cc);
+
+ bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
+ return 0;
+@@ -181,47 +181,66 @@ EXPORT_SYMBOL(bcma_cpu_clock);
+ static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
+ {
+ struct bcma_bus *bus = mcore->core->bus;
++ struct bcma_drv_cc *cc = &bus->drv_cc;
+
+- switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
++ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
+ case BCMA_CC_FLASHT_STSER:
+ case BCMA_CC_FLASHT_ATSER:
+ bcma_debug(bus, "Found serial flash\n");
+- bcma_sflash_init(&bus->drv_cc);
++ bcma_sflash_init(cc);
+ break;
+ case BCMA_CC_FLASHT_PARA:
+ bcma_debug(bus, "Found parallel flash\n");
+- bus->drv_cc.pflash.window = 0x1c000000;
+- bus->drv_cc.pflash.window_size = 0x02000000;
++ cc->pflash.present = true;
++ cc->pflash.window = BCMA_SOC_FLASH2;
++ cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
+
+- if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
++ if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
+ BCMA_CC_FLASH_CFG_DS) == 0)
+- bus->drv_cc.pflash.buswidth = 1;
++ cc->pflash.buswidth = 1;
+ else
+- bus->drv_cc.pflash.buswidth = 2;
++ cc->pflash.buswidth = 2;
+ break;
+ default:
+ bcma_err(bus, "Flash type not supported\n");
+ }
+
+- if (bus->drv_cc.core->id.rev == 38 ||
++ if (cc->core->id.rev == 38 ||
+ bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
+- if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
++ if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
+ bcma_debug(bus, "Found NAND flash\n");
+- bcma_nflash_init(&bus->drv_cc);
++ bcma_nflash_init(cc);
+ }
+ }
+ }
+
++void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
++{
++ struct bcma_bus *bus = mcore->core->bus;
++
++ if (mcore->early_setup_done)
++ return;
++
++ bcma_chipco_serial_init(&bus->drv_cc);
++ bcma_core_mips_flash_detect(mcore);
++
++ mcore->early_setup_done = true;
++}
++
+ void bcma_core_mips_init(struct bcma_drv_mips *mcore)
+ {
+ struct bcma_bus *bus;
+ struct bcma_device *core;
+ bus = mcore->core->bus;
+
++ if (mcore->setup_done)
++ return;
++
+ bcma_info(bus, "Initializing MIPS core...\n");
+
+- if (!mcore->setup_done)
+- mcore->assigned_irqs = 1;
++ bcma_core_mips_early_init(mcore);
++
++ mcore->assigned_irqs = 1;
+
+ /* Assign IRQs to all cores on the bus */
+ list_for_each_entry(core, &bus->cores, list) {
+@@ -256,10 +275,5 @@ void bcma_core_mips_init(struct bcma_drv
+ bcma_info(bus, "IRQ reconfiguration done\n");
+ bcma_core_mips_dump_irq(bus);
+
+- if (mcore->setup_done)
+- return;
+-
+- bcma_chipco_serial_init(&bus->drv_cc);
+- bcma_core_mips_flash_detect(mcore);
+ mcore->setup_done = true;
+ }
+--- a/drivers/bcma/driver_pci_host.c
++++ b/drivers/bcma/driver_pci_host.c
+@@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
+ chipid_top != 0x5300)
+ return false;
+
+- if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
+- bcma_info(bus, "This PCI core is disabled and not working\n");
+- return false;
+- }
+-
+ bcma_core_enable(pc->core, 0);
+
+ return !mips_busprobe32(tmp, pc->core->io_addr);
+@@ -396,6 +391,11 @@ void __devinit bcma_core_pci_hostmode_in
+
+ bcma_info(bus, "PCIEcore in host mode found\n");
+
++ if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
++ bcma_info(bus, "This PCIE core is disabled and not working\n");
++ return;
++ }
++
+ pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
+ if (!pc_host) {
+ bcma_err(bus, "can not allocate memory");
+@@ -452,6 +452,8 @@ void __devinit bcma_core_pci_hostmode_in
+ pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
+ pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
+ BCMA_SOC_PCI_MEM_SZ - 1;
++ pc_host->io_resource.start = 0x100;
++ pc_host->io_resource.end = 0x47F;
+ pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
+ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
+ tmp | BCMA_SOC_PCI_MEM);
+@@ -459,6 +461,8 @@ void __devinit bcma_core_pci_hostmode_in
+ pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
+ pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
+ BCMA_SOC_PCI_MEM_SZ - 1;
++ pc_host->io_resource.start = 0x480;
++ pc_host->io_resource.end = 0x7FF;
+ pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
+ pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
+ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
+@@ -534,7 +538,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_
+ static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
+ {
+ struct resource *res;
+- int pos;
++ int pos, err;
+
+ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
+ /* This is not a device on the PCI-core bridge. */
+@@ -547,8 +551,12 @@ static void bcma_core_pci_fixup_addresse
+
+ for (pos = 0; pos < 6; pos++) {
+ res = &dev->resource[pos];
+- if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
+- pci_assign_resource(dev, pos);
++ if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
++ err = pci_assign_resource(dev, pos);
++ if (err)
++ pr_err("PCI: Problem fixing up the addresses on %s\n",
++ pci_name(dev));
++ }
+ }
+ }
+ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
+--- a/drivers/bcma/host_pci.c
++++ b/drivers/bcma/host_pci.c
+@@ -238,7 +238,7 @@ static void __devexit bcma_host_pci_remo
+ pci_set_drvdata(dev, NULL);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int bcma_host_pci_suspend(struct device *dev)
+ {
+ struct pci_dev *pdev = to_pci_dev(dev);
+@@ -261,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
+ bcma_host_pci_resume);
+ #define BCMA_PM_OPS (&bcma_pm_ops)
+
+-#else /* CONFIG_PM */
++#else /* CONFIG_PM_SLEEP */
+
+ #define BCMA_PM_OPS NULL
+
+-#endif /* CONFIG_PM */
++#endif /* CONFIG_PM_SLEEP */
+
+ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
+--- a/drivers/bcma/main.c
++++ b/drivers/bcma/main.c
+@@ -81,6 +81,18 @@ struct bcma_device *bcma_find_core(struc
+ }
+ EXPORT_SYMBOL_GPL(bcma_find_core);
+
++static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
++ u8 unit)
++{
++ struct bcma_device *core;
++
++ list_for_each_entry(core, &bus->cores, list) {
++ if (core->id.id == coreid && core->core_unit == unit)
++ return core;
++ }
++ return NULL;
++}
++
+ static void bcma_release_core_dev(struct device *dev)
+ {
+ struct bcma_device *core = container_of(dev, struct bcma_device, dev);
+@@ -153,6 +165,12 @@ static int bcma_register_cores(struct bc
+ }
+ #endif
+
++ if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
++ err = bcma_chipco_watchdog_register(&bus->drv_cc);
++ if (err)
++ bcma_err(bus, "Error registering watchdog driver\n");
++ }
++
+ return 0;
+ }
+
+@@ -165,6 +183,8 @@ static void bcma_unregister_cores(struct
+ if (core->dev_registered)
+ device_unregister(&core->dev);
+ }
++ if (bus->hosttype == BCMA_HOSTTYPE_SOC)
++ platform_device_unregister(bus->drv_cc.watchdog);
+ }
+
+ int __devinit bcma_bus_register(struct bcma_bus *bus)
+@@ -183,6 +203,20 @@ int __devinit bcma_bus_register(struct b
+ return -1;
+ }
+
++ /* Early init CC core */
++ core = bcma_find_core(bus, bcma_cc_core_id(bus));
++ if (core) {
++ bus->drv_cc.core = core;
++ bcma_core_chipcommon_early_init(&bus->drv_cc);
++ }
++
++ /* Try to get SPROM */
++ err = bcma_sprom_get(bus);
++ if (err == -ENOENT) {
++ bcma_err(bus, "No SPROM available\n");
++ } else if (err)
++ bcma_err(bus, "Failed to get SPROM: %d\n", err);
++
+ /* Init CC core */
+ core = bcma_find_core(bus, bcma_cc_core_id(bus));
+ if (core) {
+@@ -198,10 +232,17 @@ int __devinit bcma_bus_register(struct b
+ }
+
+ /* Init PCIE core */
+- core = bcma_find_core(bus, BCMA_CORE_PCIE);
++ core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
+ if (core) {
+- bus->drv_pci.core = core;
+- bcma_core_pci_init(&bus->drv_pci);
++ bus->drv_pci[0].core = core;
++ bcma_core_pci_init(&bus->drv_pci[0]);
++ }
++
++ /* Init PCIE core */
++ core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
++ if (core) {
++ bus->drv_pci[1].core = core;
++ bcma_core_pci_init(&bus->drv_pci[1]);
+ }
+
+ /* Init GBIT MAC COMMON core */
+@@ -211,13 +252,6 @@ int __devinit bcma_bus_register(struct b
+ bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
+ }
+
+- /* Try to get SPROM */
+- err = bcma_sprom_get(bus);
+- if (err == -ENOENT) {
+- bcma_err(bus, "No SPROM available\n");
+- } else if (err)
+- bcma_err(bus, "Failed to get SPROM: %d\n", err);
+-
+ /* Register found cores */
+ bcma_register_cores(bus);
+
+@@ -275,18 +309,18 @@ int __init bcma_bus_early_register(struc
+ return -1;
+ }
+
+- /* Init CC core */
++ /* Early init CC core */
+ core = bcma_find_core(bus, bcma_cc_core_id(bus));
+ if (core) {
+ bus->drv_cc.core = core;
+- bcma_core_chipcommon_init(&bus->drv_cc);
++ bcma_core_chipcommon_early_init(&bus->drv_cc);
+ }
+
+- /* Init MIPS core */
++ /* Early init MIPS core */
+ core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
+ if (core) {
+ bus->drv_mips.core = core;
+- bcma_core_mips_init(&bus->drv_mips);
++ bcma_core_mips_early_init(&bus->drv_mips);
+ }
+
+ bcma_info(bus, "Early bus registered\n");
+--- a/drivers/bcma/sprom.c
++++ b/drivers/bcma/sprom.c
+@@ -595,8 +595,11 @@ int bcma_sprom_get(struct bcma_bus *bus)
+ bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
+
+ err = bcma_sprom_valid(sprom);
+- if (err)
++ if (err) {
++ bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
++ err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
+ goto out;
++ }
+
+ bcma_sprom_extract_r8(bus, sprom);
+
+--- a/include/linux/bcma/bcma.h
++++ b/include/linux/bcma/bcma.h
+@@ -157,6 +157,7 @@ struct bcma_host_ops {
+
+ /* Chip IDs of SoCs */
+ #define BCMA_CHIP_ID_BCM4706 0x5300
++#define BCMA_PKG_ID_BCM4706L 1
+ #define BCMA_CHIP_ID_BCM4716 0x4716
+ #define BCMA_PKG_ID_BCM4716 8
+ #define BCMA_PKG_ID_BCM4717 9
+@@ -166,7 +167,11 @@ struct bcma_host_ops {
+ #define BCMA_CHIP_ID_BCM4749 0x4749
+ #define BCMA_CHIP_ID_BCM5356 0x5356
+ #define BCMA_CHIP_ID_BCM5357 0x5357
++#define BCMA_PKG_ID_BCM5358 9
++#define BCMA_PKG_ID_BCM47186 10
++#define BCMA_PKG_ID_BCM5357 11
+ #define BCMA_CHIP_ID_BCM53572 53572
++#define BCMA_PKG_ID_BCM47188 9
+
+ struct bcma_device {
+ struct bcma_bus *bus;
+@@ -251,7 +256,7 @@ struct bcma_bus {
+ u8 num;
+
+ struct bcma_drv_cc drv_cc;
+- struct bcma_drv_pci drv_pci;
++ struct bcma_drv_pci drv_pci[2];
+ struct bcma_drv_mips drv_mips;
+ struct bcma_drv_gmac_cmn drv_gmac_cmn;
+
+--- a/include/linux/bcma/bcma_driver_chipcommon.h
++++ b/include/linux/bcma/bcma_driver_chipcommon.h
+@@ -1,6 +1,8 @@
+ #ifndef LINUX_BCMA_DRIVER_CC_H_
+ #define LINUX_BCMA_DRIVER_CC_H_
+
++#include <linux/platform_device.h>
++
+ /** ChipCommon core registers. **/
+ #define BCMA_CC_ID 0x0000
+ #define BCMA_CC_ID_ID 0x0000FFFF
+@@ -510,6 +512,7 @@ struct bcma_chipcommon_pmu {
+
+ #ifdef CONFIG_BCMA_DRIVER_MIPS
+ struct bcma_pflash {
++ bool present;
+ u8 buswidth;
+ u32 window;
+ u32 window_size;
+@@ -532,6 +535,7 @@ struct mtd_info;
+
+ struct bcma_nflash {
+ bool present;
++ bool boot; /* This is the flash the SoC boots from */
+
+ struct mtd_info *mtd;
+ };
+@@ -552,6 +556,7 @@ struct bcma_drv_cc {
+ u32 capabilities;
+ u32 capabilities_ext;
+ u8 setup_done:1;
++ u8 early_setup_done:1;
+ /* Fast Powerup Delay constant */
+ u16 fast_pwrup_delay;
+ struct bcma_chipcommon_pmu pmu;
+@@ -567,6 +572,8 @@ struct bcma_drv_cc {
+ int nr_serial_ports;
+ struct bcma_serial_port serial_ports[4];
+ #endif /* CONFIG_BCMA_DRIVER_MIPS */
++ u32 ticks_per_ms;
++ struct platform_device *watchdog;
+ };
+
+ /* Register access */
+@@ -583,14 +590,14 @@ struct bcma_drv_cc {
+ bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
+
+ extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
++extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
+
+ extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
+ extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
+
+ void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
+
+-extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
+- u32 ticks);
++extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
+
+ void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
+
+@@ -606,6 +613,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm
+
+ /* PMU support */
+ extern void bcma_pmu_init(struct bcma_drv_cc *cc);
++extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
+
+ extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
+ u32 value);
+--- a/include/linux/bcma/bcma_driver_mips.h
++++ b/include/linux/bcma/bcma_driver_mips.h
+@@ -35,13 +35,16 @@ struct bcma_device;
+ struct bcma_drv_mips {
+ struct bcma_device *core;
+ u8 setup_done:1;
++ u8 early_setup_done:1;
+ unsigned int assigned_irqs;
+ };
+
+ #ifdef CONFIG_BCMA_DRIVER_MIPS
+ extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
++extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
+ #else
+ static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
++static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
+ #endif
+
+ extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
+--- a/include/linux/bcma/bcma_regs.h
++++ b/include/linux/bcma/bcma_regs.h
+@@ -85,6 +85,9 @@
+ * (2 ZettaBytes), high 32 bits
+ */
+
+-#define BCMA_SFLASH 0x1c000000
++#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
++#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
++#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
++#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
+
+ #endif /* LINUX_BCMA_REGS_H_ */
+--- a/drivers/net/wireless/b43/main.c
++++ b/drivers/net/wireless/b43/main.c
+@@ -4652,7 +4652,7 @@ static int b43_wireless_core_init(struct
+ switch (dev->dev->bus_type) {
+ #ifdef CONFIG_B43_BCMA
+ case B43_BUS_BCMA:
+- bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
++ bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
+ dev->dev->bdev, true);
+ break;
+ #endif
+--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
+@@ -692,7 +692,7 @@ void ai_pci_up(struct si_pub *sih)
+ sii = container_of(sih, struct si_info, pub);
+
+ if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
+- bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
++ bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
+ }
+
+ /* Unconfigure and/or apply various WARs when going down */
+@@ -703,7 +703,7 @@ void ai_pci_down(struct si_pub *sih)
+ sii = container_of(sih, struct si_info, pub);
+
+ if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
+- bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
++ bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
+ }
+
+ /* Enable BT-COEX & Ex-PA for 4313 */
+--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
+@@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_
+ * Configure pci/pcmcia here instead of in brcms_c_attach()
+ * to allow mfg hotswap: down, hotswap (chip power cycle), up.
+ */
+- bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
++ bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
+ true);
+
+ /*
arch/mips/kernel/mips-mt-fpaff.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/arch/mips/kernel/mips-mt-fpaff.c b/arch/mips/kernel/mips-mt-fpaff.c
-index 33f63ba..fd814e0 100644
--- a/arch/mips/kernel/mips-mt-fpaff.c
+++ b/arch/mips/kernel/mips-mt-fpaff.c
-@@ -50,8 +50,8 @@ static bool check_same_owner(struct task_struct *p)
+@@ -50,8 +50,8 @@ static bool check_same_owner(struct task
rcu_read_lock();
pcred = __task_cred(p);
rcu_read_unlock();
return match;
}
---
-1.7.10.4
-
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
-@@ -839,10 +839,13 @@ static inline void cpu_probe_mips(struct
+@@ -838,10 +838,13 @@ static inline void cpu_probe_mips(struct
__cpu_name[cpu] = "MIPS 20Kc";
break;
case PRID_IMP_24K:
--- a/mm/shmem.c
+++ b/mm/shmem.c
-@@ -2769,6 +2769,15 @@ EXPORT_SYMBOL_GPL(shmem_truncate_range);
+@@ -2775,6 +2775,15 @@ EXPORT_SYMBOL_GPL(shmem_truncate_range);
/* common code */
/**
* shmem_file_setup - get an unlinked file living in tmpfs
* @name: name for dentry (to be seen in /proc/<pid>/maps
-@@ -2845,11 +2854,8 @@ int shmem_zero_setup(struct vm_area_stru
+@@ -2851,11 +2860,8 @@ int shmem_zero_setup(struct vm_area_stru
file = shmem_file_setup("dev/zero", size, vma->vm_flags);
if (IS_ERR(file))
return PTR_ERR(file);
projects / openwrt / openwrt.git / commitdiff