lantiq: dts: vr9: Add missing properties to the CPU port on the switch

The CPU port should define the phy-mode and and a PHY phandle or
fixed-link to indicate how the CPU port is connected to the SoC's
Ethernet controller. On xRX200 this is all internal connection, so use
phy-mode = "internal" along with a fixed-link that matches the
definition inside &eth0.

Linux 6.0 shows a warning since upstream commit e09e9873152e3f ("net:
dsa: make phylink-related OF properties mandatory on DSA and CPU
ports"). when these properties are missing. Adding the properties
before OpenWrt is updated to Linux 6.0 is harmless.

Suggested-by: Martin Schiller <ms@dev.tdt.de>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi
index 1089cdc80c2c1ea930ee3a972e19c3ded783f7ec..7fa2fac1ef519f2333343f0443b99f47d1959e31 100644 (file)
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi
@@ -448,7 +448,13 @@
                                port@6 {
                                        reg = <0x6>;
                                        label = "cpu";
+                                       phy-mode = "internal";
                                        ethernet = <&eth0>;
+
+                                       fixed-link {
+                                               speed = <1000>;
+                                               full-duplex;
+                                       };
                                };
                        };