--- /dev/null
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -139,6 +139,137 @@ static void qca955x_wmac_setup(void)
+ ath79_wmac_data.is_clk_25mhz = true;
+ }
+
++static bool __init
++ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
++{
++ int timeout = 1000;
++ u32 val;
++
++ __raw_readl(base + AR9300_OTP_BASE + (4 * addr));
++ while (timeout--) {
++ val = __raw_readl(base + AR9300_OTP_STATUS);
++ if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID)
++ break;
++
++ udelay(10);
++ }
++
++ if (!timeout)
++ return false;
++
++ *data = __raw_readl(base + AR9300_OTP_READ_DATA);
++ return true;
++}
++
++static bool __init
++ar93xx_wmac_otp_read(void __iomem *base, int addr, u8 *dest, int len)
++{
++ u32 data;
++ int i;
++
++ for (i = 0; i < len; i++) {
++ int offset = 8 * ((addr - i) % 4);
++
++ if (!ar93xx_wmac_otp_read_word(base, (addr - i) / 4, &data))
++ return false;
++
++ dest[i] = (data >> offset) & 0xff;
++ }
++
++ return true;
++}
++
++static bool __init
++ar93xx_wmac_otp_uncompress(void __iomem *base, int addr, int len, u8 *dest,
++ int dest_start, int dest_len)
++{
++ int dest_bytes = 0;
++ int offset = 0;
++ int end = addr - len;
++ u8 hdr[2];
++
++ while (addr > end) {
++ if (!ar93xx_wmac_otp_read(base, addr, hdr, 2))
++ return false;
++
++ addr -= 2;
++ offset += hdr[0];
++
++ if (offset <= dest_start + dest_len &&
++ offset + len >= dest_start) {
++ int data_offset = 0;
++ int dest_offset = 0;
++ int copy_len;
++
++ if (offset < dest_start)
++ data_offset = dest_start - offset;
++ else
++ dest_offset = offset - dest_start;
++
++ copy_len = len - data_offset;
++ if (copy_len > dest_len - dest_offset)
++ copy_len = dest_len - dest_offset;
++
++ ar93xx_wmac_otp_read(base, addr - data_offset,
++ dest + dest_offset,
++ copy_len);
++
++ dest_bytes += copy_len;
++ }
++ addr -= hdr[1];
++ }
++ return !!dest_bytes;
++}
++
++bool __init ar93xx_wmac_read_mac_address(u8 *dest)
++{
++ void __iomem *base;
++ bool ret = false;
++ int addr = 0x1ff;
++ unsigned int len;
++ u32 hdr_u32;
++ u8 *hdr = (u8 *) &hdr_u32;
++ u8 mac[6] = { 0x00, 0x02, 0x03, 0x04, 0x05, 0x06 };
++ int mac_start = 2, mac_end = 8;
++
++ BUG_ON(!soc_is_ar933x() && !soc_is_ar934x());
++ base = ioremap_nocache(AR933X_WMAC_BASE, AR933X_WMAC_SIZE);
++ while (addr > sizeof(hdr)) {
++ if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr)))
++ break;
++
++ if (hdr_u32 == 0 || hdr_u32 == ~0)
++ break;
++
++ len = (hdr[1] << 4) | (hdr[2] >> 4);
++ addr -= 4;
++
++ switch (hdr[0] >> 5) {
++ case 0:
++ if (len < mac_end)
++ break;
++
++ ar93xx_wmac_otp_read(base, addr - mac_start, mac, 6);
++ ret = true;
++ break;
++ case 3:
++ ret |= ar93xx_wmac_otp_uncompress(base, addr, len, mac,
++ mac_start, 6);
++ break;
++ default:
++ break;
++ }
++
++ addr -= len + 2;
++ }
++
++ iounmap(base);
++ if (ret)
++ memcpy(dest, mac, 6);
++
++ return ret;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+ if (soc_is_ar913x())
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -14,5 +14,6 @@
+
+ void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+ void ath79_register_wmac_simple(void);
++bool ar93xx_wmac_read_mac_address(u8 *dest);
+
+ #endif /* _ATH79_DEV_WMAC_H */
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -113,6 +113,14 @@
+ #define QCA955X_EHCI1_BASE 0x1b400000
+ #define QCA955X_EHCI_SIZE 0x200
+
++#define AR9300_OTP_BASE 0x14000
++#define AR9300_OTP_STATUS 0x15f18
++#define AR9300_OTP_STATUS_TYPE 0x7
++#define AR9300_OTP_STATUS_VALID 0x4
++#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
++#define AR9300_OTP_STATUS_SM_BUSY 0x1
++#define AR9300_OTP_READ_DATA 0x15f1c
++
+ /*
+ * DDR_CTRL block
+ */
--- /dev/null
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -270,6 +270,16 @@ bool __init ar93xx_wmac_read_mac_address
+ return ret;
+ }
+
++void __init ath79_wmac_disable_2ghz(void)
++{
++ ath79_wmac_data.disable_2ghz = true;
++}
++
++void __init ath79_wmac_disable_5ghz(void)
++{
++ ath79_wmac_data.disable_5ghz = true;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+ if (soc_is_ar913x())
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -14,6 +14,9 @@
+
+ void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+ void ath79_register_wmac_simple(void);
++void ath79_wmac_disable_2ghz(void);
++void ath79_wmac_disable_5ghz(void);
++
+ bool ar93xx_wmac_read_mac_address(u8 *dest);
+
+ #endif /* _ATH79_DEV_WMAC_H */
+#define QCA955X_NFC_BASE 0x1b000200
+#define QCA955X_NFC_SIZE 0xb8
- /*
- * DDR_CTRL block
-@@ -167,6 +183,9 @@
+ #define AR9300_OTP_BASE 0x14000
+ #define AR9300_OTP_STATUS 0x15f18
+@@ -175,6 +191,9 @@
#define AR71XX_AHB_DIV_SHIFT 20
#define AR71XX_AHB_DIV_MASK 0x7
#define AR724X_PLL_REG_CPU_CONFIG 0x00
#define AR724X_PLL_REG_PCIE_CONFIG 0x18
-@@ -179,6 +198,8 @@
+@@ -187,6 +206,8 @@
#define AR724X_DDR_DIV_SHIFT 22
#define AR724X_DDR_DIV_MASK 0x3
#define AR913X_PLL_REG_CPU_CONFIG 0x00
#define AR913X_PLL_REG_ETH_CONFIG 0x04
#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
-@@ -191,6 +212,9 @@
+@@ -199,6 +220,9 @@
#define AR913X_AHB_DIV_SHIFT 19
#define AR913X_AHB_DIV_MASK 0x1
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
-@@ -212,6 +236,8 @@
+@@ -220,6 +244,8 @@
#define AR934X_PLL_CPU_CONFIG_REG 0x00
#define AR934X_PLL_DDR_CONFIG_REG 0x04
#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
-@@ -244,6 +270,8 @@
+@@ -252,6 +278,8 @@
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
#define QCA955X_PLL_CLK_CTRL_REG 0x08
-@@ -370,16 +398,50 @@
+@@ -378,16 +406,50 @@
#define AR913X_RESET_USB_HOST BIT(5)
#define AR913X_RESET_USB_PHY BIT(4)
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
-@@ -520,6 +582,12 @@
+@@ -528,6 +590,12 @@
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
#define AR934X_GPIO_REG_FUNC 0x6c
#define AR71XX_GPIO_COUNT 16
-@@ -550,4 +618,133 @@
+@@ -558,4 +626,133 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
+++ /dev/null
---- a/arch/mips/ath79/dev-wmac.c
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -139,6 +139,137 @@ static void qca955x_wmac_setup(void)
- ath79_wmac_data.is_clk_25mhz = true;
- }
-
-+static bool __init
-+ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
-+{
-+ int timeout = 1000;
-+ u32 val;
-+
-+ __raw_readl(base + AR9300_OTP_BASE + (4 * addr));
-+ while (timeout--) {
-+ val = __raw_readl(base + AR9300_OTP_STATUS);
-+ if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID)
-+ break;
-+
-+ udelay(10);
-+ }
-+
-+ if (!timeout)
-+ return false;
-+
-+ *data = __raw_readl(base + AR9300_OTP_READ_DATA);
-+ return true;
-+}
-+
-+static bool __init
-+ar93xx_wmac_otp_read(void __iomem *base, int addr, u8 *dest, int len)
-+{
-+ u32 data;
-+ int i;
-+
-+ for (i = 0; i < len; i++) {
-+ int offset = 8 * ((addr - i) % 4);
-+
-+ if (!ar93xx_wmac_otp_read_word(base, (addr - i) / 4, &data))
-+ return false;
-+
-+ dest[i] = (data >> offset) & 0xff;
-+ }
-+
-+ return true;
-+}
-+
-+static bool __init
-+ar93xx_wmac_otp_uncompress(void __iomem *base, int addr, int len, u8 *dest,
-+ int dest_start, int dest_len)
-+{
-+ int dest_bytes = 0;
-+ int offset = 0;
-+ int end = addr - len;
-+ u8 hdr[2];
-+
-+ while (addr > end) {
-+ if (!ar93xx_wmac_otp_read(base, addr, hdr, 2))
-+ return false;
-+
-+ addr -= 2;
-+ offset += hdr[0];
-+
-+ if (offset <= dest_start + dest_len &&
-+ offset + len >= dest_start) {
-+ int data_offset = 0;
-+ int dest_offset = 0;
-+ int copy_len;
-+
-+ if (offset < dest_start)
-+ data_offset = dest_start - offset;
-+ else
-+ dest_offset = offset - dest_start;
-+
-+ copy_len = len - data_offset;
-+ if (copy_len > dest_len - dest_offset)
-+ copy_len = dest_len - dest_offset;
-+
-+ ar93xx_wmac_otp_read(base, addr - data_offset,
-+ dest + dest_offset,
-+ copy_len);
-+
-+ dest_bytes += copy_len;
-+ }
-+ addr -= hdr[1];
-+ }
-+ return !!dest_bytes;
-+}
-+
-+bool __init ar93xx_wmac_read_mac_address(u8 *dest)
-+{
-+ void __iomem *base;
-+ bool ret = false;
-+ int addr = 0x1ff;
-+ unsigned int len;
-+ u32 hdr_u32;
-+ u8 *hdr = (u8 *) &hdr_u32;
-+ u8 mac[6] = { 0x00, 0x02, 0x03, 0x04, 0x05, 0x06 };
-+ int mac_start = 2, mac_end = 8;
-+
-+ BUG_ON(!soc_is_ar933x() && !soc_is_ar934x());
-+ base = ioremap_nocache(AR933X_WMAC_BASE, AR933X_WMAC_SIZE);
-+ while (addr > sizeof(hdr)) {
-+ if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr)))
-+ break;
-+
-+ if (hdr_u32 == 0 || hdr_u32 == ~0)
-+ break;
-+
-+ len = (hdr[1] << 4) | (hdr[2] >> 4);
-+ addr -= 4;
-+
-+ switch (hdr[0] >> 5) {
-+ case 0:
-+ if (len < mac_end)
-+ break;
-+
-+ ar93xx_wmac_otp_read(base, addr - mac_start, mac, 6);
-+ ret = true;
-+ break;
-+ case 3:
-+ ret |= ar93xx_wmac_otp_uncompress(base, addr, len, mac,
-+ mac_start, 6);
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ addr -= len + 2;
-+ }
-+
-+ iounmap(base);
-+ if (ret)
-+ memcpy(dest, mac, 6);
-+
-+ return ret;
-+}
-+
- void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
- {
- if (soc_is_ar913x())
---- a/arch/mips/ath79/dev-wmac.h
-+++ b/arch/mips/ath79/dev-wmac.h
-@@ -14,5 +14,6 @@
-
- void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
- void ath79_register_wmac_simple(void);
-+bool ar93xx_wmac_read_mac_address(u8 *dest);
-
- #endif /* _ATH79_DEV_WMAC_H */
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -129,6 +129,14 @@
- #define QCA955X_NFC_BASE 0x1b000200
- #define QCA955X_NFC_SIZE 0xb8
-
-+#define AR9300_OTP_BASE 0x14000
-+#define AR9300_OTP_STATUS 0x15f18
-+#define AR9300_OTP_STATUS_TYPE 0x7
-+#define AR9300_OTP_STATUS_VALID 0x4
-+#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
-+#define AR9300_OTP_STATUS_SM_BUSY 0x1
-+#define AR9300_OTP_READ_DATA 0x15f1c
-+
- /*
- * DDR_CTRL block
- */
+++ /dev/null
---- a/arch/mips/ath79/dev-wmac.c
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -270,6 +270,16 @@ bool __init ar93xx_wmac_read_mac_address
- return ret;
- }
-
-+void __init ath79_wmac_disable_2ghz(void)
-+{
-+ ath79_wmac_data.disable_2ghz = true;
-+}
-+
-+void __init ath79_wmac_disable_5ghz(void)
-+{
-+ ath79_wmac_data.disable_5ghz = true;
-+}
-+
- void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
- {
- if (soc_is_ar913x())
---- a/arch/mips/ath79/dev-wmac.h
-+++ b/arch/mips/ath79/dev-wmac.h
-@@ -14,6 +14,9 @@
-
- void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
- void ath79_register_wmac_simple(void);
-+void ath79_wmac_disable_2ghz(void);
-+void ath79_wmac_disable_5ghz(void);
-+
- bool ar93xx_wmac_read_mac_address(u8 *dest);
-
- #endif /* _ATH79_DEV_WMAC_H */
--- /dev/null
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -139,6 +139,137 @@ static void qca955x_wmac_setup(void)
+ ath79_wmac_data.is_clk_25mhz = true;
+ }
+
++static bool __init
++ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
++{
++ int timeout = 1000;
++ u32 val;
++
++ __raw_readl(base + AR9300_OTP_BASE + (4 * addr));
++ while (timeout--) {
++ val = __raw_readl(base + AR9300_OTP_STATUS);
++ if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID)
++ break;
++
++ udelay(10);
++ }
++
++ if (!timeout)
++ return false;
++
++ *data = __raw_readl(base + AR9300_OTP_READ_DATA);
++ return true;
++}
++
++static bool __init
++ar93xx_wmac_otp_read(void __iomem *base, int addr, u8 *dest, int len)
++{
++ u32 data;
++ int i;
++
++ for (i = 0; i < len; i++) {
++ int offset = 8 * ((addr - i) % 4);
++
++ if (!ar93xx_wmac_otp_read_word(base, (addr - i) / 4, &data))
++ return false;
++
++ dest[i] = (data >> offset) & 0xff;
++ }
++
++ return true;
++}
++
++static bool __init
++ar93xx_wmac_otp_uncompress(void __iomem *base, int addr, int len, u8 *dest,
++ int dest_start, int dest_len)
++{
++ int dest_bytes = 0;
++ int offset = 0;
++ int end = addr - len;
++ u8 hdr[2];
++
++ while (addr > end) {
++ if (!ar93xx_wmac_otp_read(base, addr, hdr, 2))
++ return false;
++
++ addr -= 2;
++ offset += hdr[0];
++
++ if (offset <= dest_start + dest_len &&
++ offset + len >= dest_start) {
++ int data_offset = 0;
++ int dest_offset = 0;
++ int copy_len;
++
++ if (offset < dest_start)
++ data_offset = dest_start - offset;
++ else
++ dest_offset = offset - dest_start;
++
++ copy_len = len - data_offset;
++ if (copy_len > dest_len - dest_offset)
++ copy_len = dest_len - dest_offset;
++
++ ar93xx_wmac_otp_read(base, addr - data_offset,
++ dest + dest_offset,
++ copy_len);
++
++ dest_bytes += copy_len;
++ }
++ addr -= hdr[1];
++ }
++ return !!dest_bytes;
++}
++
++bool __init ar93xx_wmac_read_mac_address(u8 *dest)
++{
++ void __iomem *base;
++ bool ret = false;
++ int addr = 0x1ff;
++ unsigned int len;
++ u32 hdr_u32;
++ u8 *hdr = (u8 *) &hdr_u32;
++ u8 mac[6] = { 0x00, 0x02, 0x03, 0x04, 0x05, 0x06 };
++ int mac_start = 2, mac_end = 8;
++
++ BUG_ON(!soc_is_ar933x() && !soc_is_ar934x());
++ base = ioremap_nocache(AR933X_WMAC_BASE, AR933X_WMAC_SIZE);
++ while (addr > sizeof(hdr)) {
++ if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr)))
++ break;
++
++ if (hdr_u32 == 0 || hdr_u32 == ~0)
++ break;
++
++ len = (hdr[1] << 4) | (hdr[2] >> 4);
++ addr -= 4;
++
++ switch (hdr[0] >> 5) {
++ case 0:
++ if (len < mac_end)
++ break;
++
++ ar93xx_wmac_otp_read(base, addr - mac_start, mac, 6);
++ ret = true;
++ break;
++ case 3:
++ ret |= ar93xx_wmac_otp_uncompress(base, addr, len, mac,
++ mac_start, 6);
++ break;
++ default:
++ break;
++ }
++
++ addr -= len + 2;
++ }
++
++ iounmap(base);
++ if (ret)
++ memcpy(dest, mac, 6);
++
++ return ret;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+ if (soc_is_ar913x())
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -14,5 +14,6 @@
+
+ void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+ void ath79_register_wmac_simple(void);
++bool ar93xx_wmac_read_mac_address(u8 *dest);
+
+ #endif /* _ATH79_DEV_WMAC_H */
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -113,6 +113,14 @@
+ #define QCA955X_EHCI1_BASE 0x1b400000
+ #define QCA955X_EHCI_SIZE 0x200
+
++#define AR9300_OTP_BASE 0x14000
++#define AR9300_OTP_STATUS 0x15f18
++#define AR9300_OTP_STATUS_TYPE 0x7
++#define AR9300_OTP_STATUS_VALID 0x4
++#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
++#define AR9300_OTP_STATUS_SM_BUSY 0x1
++#define AR9300_OTP_READ_DATA 0x15f1c
++
+ /*
+ * DDR_CTRL block
+ */
--- /dev/null
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -270,6 +270,16 @@ bool __init ar93xx_wmac_read_mac_address
+ return ret;
+ }
+
++void __init ath79_wmac_disable_2ghz(void)
++{
++ ath79_wmac_data.disable_2ghz = true;
++}
++
++void __init ath79_wmac_disable_5ghz(void)
++{
++ ath79_wmac_data.disable_5ghz = true;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+ if (soc_is_ar913x())
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -14,6 +14,9 @@
+
+ void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+ void ath79_register_wmac_simple(void);
++void ath79_wmac_disable_2ghz(void);
++void ath79_wmac_disable_5ghz(void);
++
+ bool ar93xx_wmac_read_mac_address(u8 *dest);
+
+ #endif /* _ATH79_DEV_WMAC_H */
+#define QCA955X_NFC_BASE 0x1b000200
+#define QCA955X_NFC_SIZE 0xb8
- /*
- * DDR_CTRL block
-@@ -167,6 +183,9 @@
+ #define AR9300_OTP_BASE 0x14000
+ #define AR9300_OTP_STATUS 0x15f18
+@@ -175,6 +191,9 @@
#define AR71XX_AHB_DIV_SHIFT 20
#define AR71XX_AHB_DIV_MASK 0x7
#define AR724X_PLL_REG_CPU_CONFIG 0x00
#define AR724X_PLL_REG_PCIE_CONFIG 0x18
-@@ -179,6 +198,8 @@
+@@ -187,6 +206,8 @@
#define AR724X_DDR_DIV_SHIFT 22
#define AR724X_DDR_DIV_MASK 0x3
#define AR913X_PLL_REG_CPU_CONFIG 0x00
#define AR913X_PLL_REG_ETH_CONFIG 0x04
#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
-@@ -191,6 +212,9 @@
+@@ -199,6 +220,9 @@
#define AR913X_AHB_DIV_SHIFT 19
#define AR913X_AHB_DIV_MASK 0x1
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
-@@ -212,6 +236,8 @@
+@@ -220,6 +244,8 @@
#define AR934X_PLL_CPU_CONFIG_REG 0x00
#define AR934X_PLL_DDR_CONFIG_REG 0x04
#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
-@@ -244,6 +270,8 @@
+@@ -252,6 +278,8 @@
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
#define QCA955X_PLL_CLK_CTRL_REG 0x08
-@@ -370,16 +398,50 @@
+@@ -378,16 +406,50 @@
#define AR913X_RESET_USB_HOST BIT(5)
#define AR913X_RESET_USB_PHY BIT(4)
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
-@@ -520,6 +582,12 @@
+@@ -528,6 +590,12 @@
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
#define AR934X_GPIO_REG_FUNC 0x6c
#define AR71XX_GPIO_COUNT 16
-@@ -551,4 +619,133 @@
+@@ -559,4 +627,133 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
+++ /dev/null
---- a/arch/mips/ath79/dev-wmac.c
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -139,6 +139,137 @@ static void qca955x_wmac_setup(void)
- ath79_wmac_data.is_clk_25mhz = true;
- }
-
-+static bool __init
-+ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
-+{
-+ int timeout = 1000;
-+ u32 val;
-+
-+ __raw_readl(base + AR9300_OTP_BASE + (4 * addr));
-+ while (timeout--) {
-+ val = __raw_readl(base + AR9300_OTP_STATUS);
-+ if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID)
-+ break;
-+
-+ udelay(10);
-+ }
-+
-+ if (!timeout)
-+ return false;
-+
-+ *data = __raw_readl(base + AR9300_OTP_READ_DATA);
-+ return true;
-+}
-+
-+static bool __init
-+ar93xx_wmac_otp_read(void __iomem *base, int addr, u8 *dest, int len)
-+{
-+ u32 data;
-+ int i;
-+
-+ for (i = 0; i < len; i++) {
-+ int offset = 8 * ((addr - i) % 4);
-+
-+ if (!ar93xx_wmac_otp_read_word(base, (addr - i) / 4, &data))
-+ return false;
-+
-+ dest[i] = (data >> offset) & 0xff;
-+ }
-+
-+ return true;
-+}
-+
-+static bool __init
-+ar93xx_wmac_otp_uncompress(void __iomem *base, int addr, int len, u8 *dest,
-+ int dest_start, int dest_len)
-+{
-+ int dest_bytes = 0;
-+ int offset = 0;
-+ int end = addr - len;
-+ u8 hdr[2];
-+
-+ while (addr > end) {
-+ if (!ar93xx_wmac_otp_read(base, addr, hdr, 2))
-+ return false;
-+
-+ addr -= 2;
-+ offset += hdr[0];
-+
-+ if (offset <= dest_start + dest_len &&
-+ offset + len >= dest_start) {
-+ int data_offset = 0;
-+ int dest_offset = 0;
-+ int copy_len;
-+
-+ if (offset < dest_start)
-+ data_offset = dest_start - offset;
-+ else
-+ dest_offset = offset - dest_start;
-+
-+ copy_len = len - data_offset;
-+ if (copy_len > dest_len - dest_offset)
-+ copy_len = dest_len - dest_offset;
-+
-+ ar93xx_wmac_otp_read(base, addr - data_offset,
-+ dest + dest_offset,
-+ copy_len);
-+
-+ dest_bytes += copy_len;
-+ }
-+ addr -= hdr[1];
-+ }
-+ return !!dest_bytes;
-+}
-+
-+bool __init ar93xx_wmac_read_mac_address(u8 *dest)
-+{
-+ void __iomem *base;
-+ bool ret = false;
-+ int addr = 0x1ff;
-+ unsigned int len;
-+ u32 hdr_u32;
-+ u8 *hdr = (u8 *) &hdr_u32;
-+ u8 mac[6] = { 0x00, 0x02, 0x03, 0x04, 0x05, 0x06 };
-+ int mac_start = 2, mac_end = 8;
-+
-+ BUG_ON(!soc_is_ar933x() && !soc_is_ar934x());
-+ base = ioremap_nocache(AR933X_WMAC_BASE, AR933X_WMAC_SIZE);
-+ while (addr > sizeof(hdr)) {
-+ if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr)))
-+ break;
-+
-+ if (hdr_u32 == 0 || hdr_u32 == ~0)
-+ break;
-+
-+ len = (hdr[1] << 4) | (hdr[2] >> 4);
-+ addr -= 4;
-+
-+ switch (hdr[0] >> 5) {
-+ case 0:
-+ if (len < mac_end)
-+ break;
-+
-+ ar93xx_wmac_otp_read(base, addr - mac_start, mac, 6);
-+ ret = true;
-+ break;
-+ case 3:
-+ ret |= ar93xx_wmac_otp_uncompress(base, addr, len, mac,
-+ mac_start, 6);
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ addr -= len + 2;
-+ }
-+
-+ iounmap(base);
-+ if (ret)
-+ memcpy(dest, mac, 6);
-+
-+ return ret;
-+}
-+
- void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
- {
- if (soc_is_ar913x())
---- a/arch/mips/ath79/dev-wmac.h
-+++ b/arch/mips/ath79/dev-wmac.h
-@@ -14,5 +14,6 @@
-
- void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
- void ath79_register_wmac_simple(void);
-+bool ar93xx_wmac_read_mac_address(u8 *dest);
-
- #endif /* _ATH79_DEV_WMAC_H */
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -129,6 +129,14 @@
- #define QCA955X_NFC_BASE 0x1b000200
- #define QCA955X_NFC_SIZE 0xb8
-
-+#define AR9300_OTP_BASE 0x14000
-+#define AR9300_OTP_STATUS 0x15f18
-+#define AR9300_OTP_STATUS_TYPE 0x7
-+#define AR9300_OTP_STATUS_VALID 0x4
-+#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
-+#define AR9300_OTP_STATUS_SM_BUSY 0x1
-+#define AR9300_OTP_READ_DATA 0x15f1c
-+
- /*
- * DDR_CTRL block
- */
+++ /dev/null
---- a/arch/mips/ath79/dev-wmac.c
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -270,6 +270,16 @@ bool __init ar93xx_wmac_read_mac_address
- return ret;
- }
-
-+void __init ath79_wmac_disable_2ghz(void)
-+{
-+ ath79_wmac_data.disable_2ghz = true;
-+}
-+
-+void __init ath79_wmac_disable_5ghz(void)
-+{
-+ ath79_wmac_data.disable_5ghz = true;
-+}
-+
- void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
- {
- if (soc_is_ar913x())
---- a/arch/mips/ath79/dev-wmac.h
-+++ b/arch/mips/ath79/dev-wmac.h
-@@ -14,6 +14,9 @@
-
- void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
- void ath79_register_wmac_simple(void);
-+void ath79_wmac_disable_2ghz(void);
-+void ath79_wmac_disable_5ghz(void);
-+
- bool ar93xx_wmac_read_mac_address(u8 *dest);
-
- #endif /* _ATH79_DEV_WMAC_H */
projects / openwrt / openwrt.git / commitdiff