mvebu: add SolidRun ClearFog A1 support
authorLuka Perkov <luka@openwrt.org>
Wed, 17 Feb 2016 17:49:26 +0000 (17:49 +0000)
committerLuka Perkov <luka@openwrt.org>
Wed, 17 Feb 2016 17:49:26 +0000 (17:49 +0000)
Signed-off-by: Andrej Vlasic <andrej.vlasic@sartura.hr>
SVN-Revision: 48736

target/linux/mvebu/base-files/etc/board.d/02_network
target/linux/mvebu/base-files/lib/mvebu.sh
target/linux/mvebu/files/arch/arm/boot/dts/armada-388-clearfog.dts [new file with mode: 0644]
target/linux/mvebu/files/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi [new file with mode: 0644]
target/linux/mvebu/image/Makefile
target/linux/mvebu/patches-4.1/209-solidrun_clearfog.patch [new file with mode: 0644]
target/linux/mvebu/patches-4.4/209-solidrun_clearfog.patch [new file with mode: 0644]
target/linux/mvebu/profiles/solidrun.mk [new file with mode: 0644]

index 289a4b0..f81d0ac 100755 (executable)
@@ -31,6 +31,9 @@ armada-385-db-ap)
 armada-xp-gp)
        ucidef_set_interface_lan "eth0 eth1 eth2 eth3"
        ;;
+armada-388-clearfog)
+       ucidef_set_interfaces_lan_wan "eth0 eth1" "eth2"
+       ;;
 *)
        ucidef_set_interface_lan "eth0"
        ;;
index 09ebff3..836717d 100755 (executable)
@@ -49,6 +49,9 @@ mvebu_board_detect() {
        *"Marvell Armada XP Development Board DB-MV784MP-GP")
                name="armada-xp-gp"
                ;;
+       *"SolidRun Clearfog A1")
+               name="armada-388-clearfog"
+               ;;
        esac
 
        [ -z "$name" ] && name="unknown"
diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-388-clearfog.dts b/target/linux/mvebu/files/arch/arm/boot/dts/armada-388-clearfog.dts
new file mode 100644 (file)
index 0000000..c6e180e
--- /dev/null
@@ -0,0 +1,456 @@
+/*
+ * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
+ *
+ *  Copyright (C) 2015 Russell King
+ *
+ * This board is in development; the contents of this file work with
+ * the A1 rev 2.0 of the board, which does not represent final
+ * production board.  Things will change, don't expect this file to
+ * remain compatible info the future.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-388.dtsi"
+#include "armada-38x-solidrun-microsom.dtsi"
+
+/ {
+       model = "SolidRun Clearfog A1";
+       compatible = "solidrun,clearfog-a1", "marvell,armada388",
+               "marvell,armada385", "marvell,armada380";
+
+       aliases {
+               /* So that mvebu u-boot can update the MAC addresses */
+               ethernet1 = &eth0;
+               ethernet2 = &eth1;
+               ethernet3 = &eth2;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       reg_3p3v: regulator-3p3v {
+               compatible = "regulator-fixed";
+               regulator-name = "3P3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+       };
+
+       soc {
+               internal-regs {
+                       ethernet@30000 {
+                               phy-mode = "sgmii";
+                               status = "okay";
+
+                               fixed-link {
+                                       speed = <1000>;
+                                       full-duplex;
+                               };
+                       };
+
+                       ethernet@34000 {
+                               phy-mode = "sgmii";
+                               status = "okay";
+
+                               fixed-link {
+                                       speed = <1000>;
+                                       full-duplex;
+                               };
+                       };
+
+                       i2c@11000 {
+                               /* Is there anything on this? */
+                               clock-frequency = <100000>;
+                               pinctrl-0 = <&i2c0_pins>;
+                               pinctrl-names = "default";
+                               status = "okay";
+
+                               /*
+                                * PCA9655 GPIO expander, up to 1MHz clock.
+                                *  0-CON3 CLKREQ#
+                                *  1-CON3 PERST#
+                                *  2-CON2 PERST#
+                                *  3-CON3 W_DISABLE
+                                *  4-CON2 CLKREQ#
+                                *  5-USB3 overcurrent
+                                *  6-USB3 power
+                                *  7-CON2 W_DISABLE
+                                *  8-JP4 P1
+                                *  9-JP4 P4
+                                * 10-JP4 P5
+                                * 11-m.2 DEVSLP
+                                * 12-SFP_LOS
+                                * 13-SFP_TX_FAULT
+                                * 14-SFP_TX_DISABLE
+                                * 15-SFP_MOD_DEF0
+                                */
+                               expander0: gpio-expander@20 {
+                                       /*
+                                        * This is how it should be:
+                                        * compatible = "onnn,pca9655",
+                                        *       "nxp,pca9555";
+                                        * but you can't do this because of
+                                        * the way I2C works.
+                                        */
+                                       compatible = "nxp,pca9555";
+                                       gpio-controller;
+                                       #gpio-cells = <2>;
+                                       reg = <0x20>;
+
+                                       pcie1_0_clkreq {
+                                               gpio-hog;
+                                               gpios = <0 GPIO_ACTIVE_LOW>;
+                                               input;
+                                               line-name = "pcie1.0-clkreq";
+                                       };
+                                       pcie1_0_w_disable {
+                                               gpio-hog;
+                                               gpios = <3 GPIO_ACTIVE_LOW>;
+                                               output-low;
+                                               line-name = "pcie1.0-w-disable";
+                                       };
+                                       pcie2_0_clkreq {
+                                               gpio-hog;
+                                               gpios = <4 GPIO_ACTIVE_LOW>;
+                                               input;
+                                               line-name = "pcie2.0-clkreq";
+                                       };
+                                       pcie2_0_w_disable {
+                                               gpio-hog;
+                                               gpios = <7 GPIO_ACTIVE_LOW>;
+                                               output-low;
+                                               line-name = "pcie2.0-w-disable";
+                                       };
+                                       usb3_ilimit {
+                                               gpio-hog;
+                                               gpios = <5 GPIO_ACTIVE_LOW>;
+                                               input;
+                                               line-name = "usb3-current-limit";
+                                       };
+                                       usb3_power {
+                                               gpio-hog;
+                                               gpios = <6 GPIO_ACTIVE_HIGH>;
+                                               output-high;
+                                               line-name = "usb3-power";
+                                       };
+                                       m2_devslp {
+                                               gpio-hog;
+                                               gpios = <11 GPIO_ACTIVE_HIGH>;
+                                               output-low;
+                                               line-name = "m.2 devslp";
+                                       };
+                                       sfp_los {
+                                               /* SFP loss of signal */
+                                               gpio-hog;
+                                               gpios = <12 GPIO_ACTIVE_HIGH>;
+                                               input;
+                                               line-name = "sfp-los";
+                                       };
+                                       sfp_tx_fault {
+                                               /* SFP laser fault */
+                                               gpio-hog;
+                                               gpios = <13 GPIO_ACTIVE_HIGH>;
+                                               input;
+                                               line-name = "sfp-tx-fault";
+                                       };
+                                       sfp_tx_disable {
+                                               /* SFP transmit disable */
+                                               gpio-hog;
+                                               gpios = <14 GPIO_ACTIVE_HIGH>;
+                                               output-low;
+                                               line-name = "sfp-tx-disable";
+                                       };
+                                       sfp_mod_def0 {
+                                               /* SFP module present */
+                                               gpio-hog;
+                                               gpios = <15 GPIO_ACTIVE_LOW>;
+                                               input;
+                                               line-name = "sfp-mod-def0";
+                                       };
+                               };
+
+                               /* The MCP3021 is 100kHz clock only */
+                               mikrobus_adc: mcp3021@4c {
+                                       compatible = "microchip,mcp3021";
+                                       reg = <0x4c>;
+                               };
+
+                               /* Also something at 0x64 */
+                       };
+
+                       i2c@11100 {
+                               /*
+                                * Routed to SFP, mikrobus, and PCIe.
+                                * SFP limits this to 100kHz, and requires
+                                *  an AT24C01A/02/04 with address pins tied
+                                *  low, which takes addresses 0x50 and 0x51.
+                                * Mikrobus doesn't specify beyond an I2C
+                                *  bus being present.
+                                * PCIe uses ARP to assign addresses, or
+                                *  0x63-0x64.
+                                */
+                               clock-frequency = <100000>;
+                               pinctrl-0 = <&clearfog_i2c1_pins>;
+                               pinctrl-names = "default";
+                               status = "okay";
+                       };
+
+                       mdio@72004 {
+                               pinctrl-0 = <&mdio_pins>;
+                               pinctrl-names = "default";
+
+                               phy_dedicated: ethernet-phy@0 {
+                                       /*
+                                        * Annoyingly, the marvell phy driver
+                                        * configures the LED register, rather
+                                        * than preserving reset-loaded setting.
+                                        * We undo that rubbish here.
+                                        */
+                                       marvell,reg-init = <3 16 0 0x101e>;
+                                       reg = <0>;
+                               };
+                       };
+
+                       pinctrl@18000 {
+                               clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
+                                       marvell,pins = "mpp46";
+                                       marvell,function = "ref";
+                               };
+                               clearfog_dsa0_pins: clearfog-dsa0-pins {
+                                       marvell,pins = "mpp23", "mpp41";
+                                       marvell,function = "gpio";
+                               };
+                               clearfog_i2c1_pins: i2c1-pins {
+                                       /* SFP, PCIe, mSATA, mikrobus */
+                                       marvell,pins = "mpp26", "mpp27";
+                                       marvell,function = "i2c1";
+                               };
+                               clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
+                                       marvell,pins = "mpp20";
+                                       marvell,function = "gpio";
+                               };
+                               clearfog_sdhci_pins: clearfog-sdhci-pins {
+                                       marvell,pins = "mpp21", "mpp28",
+                                                      "mpp37", "mpp38",
+                                                      "mpp39", "mpp40";
+                                       marvell,function = "sd0";
+                               };
+                               clearfog_spi1_cs_pins: spi1-cs-pins {
+                                       marvell,pins = "mpp55";
+                                       marvell,function = "spi1";
+                               };
+                               mikro_pins: mikro-pins {
+                                       /* int: mpp22 rst: mpp29 */
+                                       marvell,pins = "mpp22", "mpp29";
+                                       marvell,function = "gpio";
+                               };
+                               mikro_spi_pins: mikro-spi-pins {
+                                       marvell,pins = "mpp43";
+                                       marvell,function = "spi1";
+                               };
+                               mikro_uart_pins: mikro-uart-pins {
+                                       marvell,pins = "mpp24", "mpp25";
+                                       marvell,function = "ua1";
+                               };
+                               rear_button_pins: rear-button-pins {
+                                       marvell,pins = "mpp34";
+                                       marvell,function = "gpio";
+                               };
+                       };
+
+                       sata@a8000 {
+                               /* pinctrl? */
+                               status = "okay";
+                       };
+
+                       sata@e0000 {
+                               /* pinctrl? */
+                               status = "okay";
+                       };
+
+                       sdhci@d8000 {
+                               bus-width = <4>;
+                               cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+                               no-1-8-v;
+                               pinctrl-0 = <&clearfog_sdhci_pins
+                                            &clearfog_sdhci_cd_pins>;
+                               pinctrl-names = "default";
+                               status = "okay";
+                               vmmc = <&reg_3p3v>;
+                               wp-inverted;
+                       };
+
+                       serial@12100 {
+                               /* mikrobus uart */
+                               pinctrl-0 = <&mikro_uart_pins>;
+                               pinctrl-names = "default";
+                               status = "okay";
+                       };
+
+                       spi@10680 {
+                               /*
+                                * We don't seem to have the W25Q32 on the
+                                * A1 Rev 2.0 boards, so disable SPI.
+                                * CS0: W25Q32 (doesn't appear to be present)
+                                * CS1:
+                                * CS2: mikrobus
+                                */
+                               pinctrl-0 = <&spi1_pins
+                                            &clearfog_spi1_cs_pins
+                                            &mikro_spi_pins>;
+                               pinctrl-names = "default";
+                               status = "okay";
+
+                               spi-flash@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       compatible = "w25q32", "jedec,spi-nor";
+                                       reg = <0>; /* Chip select 0 */
+                                       spi-max-frequency = <3000000>;
+                                       status = "disabled";
+                               };
+                       };
+
+                       usb@58000 {
+                               /* CON3, nearest  power. */
+                               status = "okay";
+                       };
+
+                       usb3@f0000 {
+                               /* CON2, nearest CPU, USB2 only. */
+                               status = "okay";
+                       };
+
+                       usb3@f8000 {
+                               /* CON7 */
+                               status = "okay";
+                       };
+               };
+
+               pcie-controller {
+                       status = "okay";
+                       /*
+                        * The two PCIe units are accessible through
+                        * the mini-PCIe connectors on the board.
+                        */
+                       pcie@2,0 {
+                               /* Port 1, Lane 0. CON3, nearest power. */
+                               reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
+                               status = "okay";
+                       };
+                       pcie@3,0 {
+                               /* Port 2, Lane 0. CON2, nearest CPU. */
+                               reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
+                               status = "okay";
+                       };
+               };
+       };
+
+       dsa@0 {
+               compatible = "marvell,dsa";
+               dsa,ethernet = <&eth1>;
+               dsa,mii-bus = <&mdio>;
+               pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
+               pinctrl-names = "default";
+               #address-cells = <2>;
+               #size-cells = <0>;
+
+               switch@0 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <4 0>;
+
+                       port@0 {
+                               reg = <0>;
+                               label = "lan1";
+                       };
+
+                       port@1 {
+                               reg = <1>;
+                               label = "lan2";
+                       };
+
+                       port@2 {
+                               reg = <2>;
+                               label = "lan3";
+                       };
+
+                       port@3 {
+                               reg = <3>;
+                               label = "lan4";
+                       };
+
+                       port@4 {
+                               reg = <4>;
+                               label = "lan5";
+                       };
+
+                       port@5 {
+                               reg = <5>;
+                               label = "cpu";
+                       };
+
+                       port@6 {
+                               /* 88E1512 external phy */
+                               reg = <6>;
+                               label = "lan6";
+                               fixed-link {
+                                       speed = <1000>;
+                                       full-duplex;
+                               };
+                       };
+               };
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+               pinctrl-0 = <&rear_button_pins>;
+               pinctrl-names = "default";
+
+               button_0 {
+                       /* The rear SW3 button */
+                       label = "Rear Button";
+                       gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+                       linux,can-disable;
+                       linux,code = <BTN_0>;
+               };
+       };
+};
diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/target/linux/mvebu/files/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
new file mode 100644 (file)
index 0000000..3f792a5
--- /dev/null
@@ -0,0 +1,115 @@
+/*
+ * Device Tree file for SolidRun Armada 38x Microsom
+ *
+ *  Copyright (C) 2015 Russell King
+ *
+ * This board is in development; the contents of this file work with
+ * the A1 rev 2.0 of the board, which does not represent final
+ * production board.  Things will change, don't expect this file to
+ * remain compatible info the future.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+       memory {
+               device_type = "memory";
+               reg = <0x00000000 0x10000000>; /* 256 MB */
+       };
+
+       soc {
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+                         MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+                         MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+                         MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
+
+               internal-regs {
+                       ethernet@70000 {
+                               pinctrl-0 = <&ge0_rgmii_pins>;
+                               pinctrl-names = "default";
+                               phy = <&phy_dedicated>;
+                               phy-mode = "rgmii-id";
+                               status = "okay";
+                       };
+
+                       mdio@72004 {
+                               /*
+                                * Add the phy clock here, so the phy can be
+                                * accessed to read its IDs prior to binding
+                                * with the driver.
+                                */
+                               pinctrl-0 = <&mdio_pins &microsom_phy_clk_pins>;
+                               pinctrl-names = "default";
+
+                               phy_dedicated: ethernet-phy@0 {
+                                       /*
+                                        * Annoyingly, the marvell phy driver
+                                        * configures the LED register, rather
+                                        * than preserving reset-loaded setting.
+                                        * We undo that rubbish here.
+                                        */
+                                       marvell,reg-init = <3 16 0 0x101e>;
+                                       reg = <0>;
+                               };
+                       };
+
+                       pinctrl@18000 {
+                               microsom_phy_clk_pins: microsom-phy-clk-pins {
+                                       marvell,pins = "mpp45";
+                                       marvell,function = "ref";
+                               };
+                       };
+
+                       rtc@a3800 {
+                               /*
+                                * If the rtc doesn't work, run "date reset"
+                                * twice in u-boot.
+                                */
+                               status = "okay";
+                       };
+
+                       serial@12000 {
+                               pinctrl-0 = <&uart0_pins>;
+                               pinctrl-names = "default";
+                               status = "okay";
+                       };
+               };
+       };
+};
index 123be9e..cb73c3b 100644 (file)
@@ -97,6 +97,26 @@ define NORProfile
   PROFILES_LIST += $(1)
 endef
 
+# $(1): Profile Name
+# $(2): DTB Name
+define MMCProfile
+  define Image/BuildKernel/Profile/$(1)
+       $(call Image/Build/DTB,$(2))
+       cp $(KDIR)/zImage-$(2) $(BIN_DIR)/zImage-$(1);
+       cp $(DTS_DIR)/$(2).dtb $(BIN_DIR)/$(1).dtb;
+    ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
+       $(call Image/Build/Profile,$(1)/Initramfs)
+    endif
+  endef
+
+  define Image/Build/Profile/$(1)/Initramfs
+       $(call Image/Build/DTB,$(2),-initramfs)
+       cp $(KDIR)/uImage-initramfs-$(2) $(BIN_DIR)/$(IMG_PREFIX)-$(2)-initramfs
+  endef
+
+  PROFILES_LIST += $(1)
+endef
+
 # $(1): Profile Name
 # $(2): Sub Profiles list
 define MultiProfile
@@ -141,6 +161,8 @@ $(eval $(call UBINORProfile,OpenBlocks-AX-3-4,armada-xp-openblocks-ax3-4,128KiB)
 # Boards with small NOR, where UBI doesn't make sense
 $(eval $(call NORProfile,388-RD,armada-388-rd,256KiB))
 
+$(eval $(call MMCProfile,Solidrun-Clearfog-A1,armada-388-clearfog))
+
 ###
 ### Linksys
 ###
diff --git a/target/linux/mvebu/patches-4.1/209-solidrun_clearfog.patch b/target/linux/mvebu/patches-4.1/209-solidrun_clearfog.patch
new file mode 100644 (file)
index 0000000..5e8c89b
--- /dev/null
@@ -0,0 +1,10 @@
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -636,6 +636,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
+       armada-385-linksys-caiman.dtb \
+       armada-385-linksys-cobra.dtb \
+       armada-385-linksys-shelby.dtb \
++      armada-388-clearfog.dtb \
+       armada-388-db.dtb \
+       armada-388-gp.dtb \
+       armada-388-rd.dtb
diff --git a/target/linux/mvebu/patches-4.4/209-solidrun_clearfog.patch b/target/linux/mvebu/patches-4.4/209-solidrun_clearfog.patch
new file mode 100644 (file)
index 0000000..80a0946
--- /dev/null
@@ -0,0 +1,10 @@
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -749,6 +749,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
+       armada-385-linksys-caiman.dtb \
+       armada-385-linksys-cobra.dtb \
+       armada-385-linksys-shelby.dtb \
++      armada-388-clearfog.dtb \
+       armada-388-db.dtb \
+       armada-388-gp.dtb \
+       armada-388-rd.dtb
diff --git a/target/linux/mvebu/profiles/solidrun.mk b/target/linux/mvebu/profiles/solidrun.mk
new file mode 100644 (file)
index 0000000..5aa61e2
--- /dev/null
@@ -0,0 +1,21 @@
+#
+# Copyright (C) 2016 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+define Profile/Solidrun-Clearfog-A1
+  NAME:=SolidRun ClearFog A1 board
+  PACKAGES:= \
+       kmod-usb3 kmod-usb2 kmod-usb-storage \
+       kmod-of-i2c kmod-i2c-core kmod-i2c-mv64xxx \
+       kmod-ata-core kmod-ata-marvell-sata \
+       kmod-thermal-armada kmod-rtc-marvell
+endef
+
+define Profile/Solidrun-Clearfog-A1/Description
+ Package set compatible with the SolidRun ClearFog A1 board
+endef
+
+$(eval $(call Profile,Solidrun-Clearfog-A1))