uboot-lantiq

fix arv752DPW and add arv7525PW

SVN-Revision: 27664

diff --git a/package/uboot-lantiq/Makefile b/package/uboot-lantiq/Makefile
index 404b540b6d6ecd8bf4831e84c895c8e5ea6235f6..015efcfe60153342aad43c40f186b4a9a144d4db 100644 (file)
--- a/package/uboot-lantiq/Makefile
+++ b/package/uboot-lantiq/Makefile
@@ -61,6 +61,9 @@ Package/uboot-lantiq-arv4520PW_brnboot=$(call Package/uboot-lantiq-template,arv4
 Package/uboot-lantiq-arv4525PW_flash=$(call Package/uboot-lantiq-template,arv4525PW_flash,NOR)
 Package/uboot-lantiq-arv4525PW_ramboot=$(call Package/uboot-lantiq-template,arv4525PW_ramboot,RAM)
 Package/uboot-lantiq-arv4525PW_brnboot=$(call Package/uboot-lantiq-template,arv4525PW_brnboot,BRN)
+Package/uboot-lantiq-arv7525PW_flash=$(call Package/uboot-lantiq-template,arv7525PW_flash,NOR)
+Package/uboot-lantiq-arv7525PW_ramboot=$(call Package/uboot-lantiq-template,arv7525PW_ramboot,RAM)
+Package/uboot-lantiq-arv7525PW_brnboot=$(call Package/uboot-lantiq-template,arv7525PW_brnboot,BRN)
 Package/uboot-lantiq-arv452CPW_flash=$(call Package/uboot-lantiq-template,arv452CPW_flash,NOR)
 Package/uboot-lantiq-arv452CPW_ramboot=$(call Package/uboot-lantiq-template,arv452CPW_ramboot,RAM)
 Package/uboot-lantiq-arv452CPW_brnboot=$(call Package/uboot-lantiq-template,arv452CPW_brnboot,BRN)
@@ -75,6 +78,7 @@ DDR_CONFIG_arv3527P_ramboot:=arcadyan_psc166_32
 DDR_CONFIG_arv4518PW_ramboot:=arcadyan_psc166_64
 DDR_CONFIG_arv4520PW_ramboot:=arcadyan_psc166_32
 DDR_CONFIG_arv4525PW_ramboot:=arcadyan_psc166_32
+DDR_CONFIG_arv7525PW_ramboot:=arcadyan_psc166_32
 DDR_CONFIG_arv452CPW_ramboot:=arcadyan_psc166_32
 DDR_CONFIG_arv752DPW_ramboot:=arcadyan_psc166_64
 DDR_CONFIG_arv752DPW22_ramboot:=arcadyan_psc166_64
@@ -153,6 +157,9 @@ $(eval $(call BuildPackage,uboot-lantiq-arv4520PW_ramboot))
 $(eval $(call BuildPackage,uboot-lantiq-arv4525PW_flash))
 $(eval $(call BuildPackage,uboot-lantiq-arv4525PW_brnboot))
 $(eval $(call BuildPackage,uboot-lantiq-arv4525PW_ramboot))
+$(eval $(call BuildPackage,uboot-lantiq-arv7525PW_flash))
+$(eval $(call BuildPackage,uboot-lantiq-arv7525PW_brnboot))
+$(eval $(call BuildPackage,uboot-lantiq-arv7525PW_ramboot))
 $(eval $(call BuildPackage,uboot-lantiq-arv452CPW_flash))
 $(eval $(call BuildPackage,uboot-lantiq-arv452CPW_brnboot))
 $(eval $(call BuildPackage,uboot-lantiq-arv452CPW_ramboot))

diff --git a/package/uboot-lantiq/files/board/arcadyan/board.c b/package/uboot-lantiq/files/board/arcadyan/board.c
index 005efbb0e4f3288c6fc02598a1bec6380fd9226a..57f4603628676492814c84ea753904ec8db10dd4 100644 (file)
--- a/package/uboot-lantiq/files/board/arcadyan/board.c
+++ b/package/uboot-lantiq/files/board/arcadyan/board.c
@@ -312,6 +312,107 @@ static int external_switch_rtl8306(void)
 }
 #endif
 
+#ifdef CONFIG_RTL8306G_SWITCH
+#define ID_RTL8306     0x5988
+
+static int external_switch_rtl8306G(void)
+{
+       unsigned short chipid,val;
+       int i;
+       static char * const name = "lq_cpe_eth";
+       unsigned int chipid2, chipver, chiptype;
+       char str[128];
+       int cpu_mask = 1 << 5;
+       udelay(100000);
+
+       puts("\nsearching for rtl8306 switch ... ");
+       if (miiphy_read(name, 4, 30, &chipid) == 0) {
+               if (chipid == ID_RTL8306) {
+                       puts("found\nReset Hard\n");
+#ifdef CONFIG_ARV752DPW
+                       //gpio 19
+                       //reset reset ping to high
+                       *DANUBE_GPIO_P1_DIR |= 8;
+                       *DANUBE_GPIO_P1_OUT |= 8;
+                       udelay(500*1000);
+                       *DANUBE_GPIO_P1_OUT &= ~(8); // now low again for at least 10 ms
+                       udelay(500*1000);
+                       *DANUBE_GPIO_P1_OUT |= 8;
+                       udelay(500*1000);
+                       puts("Done\n");
+#endif
+                       /* set led mode */
+
+                       miiphy_write(name, 0, 0, 0x3100);
+                       miiphy_write(name, 0, 18, 0x7fff);
+                       miiphy_write(name, 0, 19, 0xffff);
+                       miiphy_write(name, 0, 22, 0x877f);
+                       miiphy_write(name, 0, 24, 0x0ed1);
+
+                       miiphy_write(name, 1, 0, 0x3100);
+                       miiphy_write(name, 1, 22, 0x877f);
+                       miiphy_write(name, 1, 24, 0x1ed2);
+
+                       miiphy_write(name, 2, 0, 0x3100);
+                       miiphy_write(name, 2, 22, 0x877f);
+                       miiphy_write(name, 2, 23, 0x0020);
+                       miiphy_write(name, 2, 24, 0x2ed4);
+
+                       miiphy_write(name, 3, 0, 0x3100);
+                       miiphy_write(name, 3, 22, 0x877f);
+                       miiphy_write(name, 3, 24, 0x3ed8);
+
+                       miiphy_write(name, 4, 0, 0x3100);
+                       miiphy_write(name, 4, 22, 0x877f);
+                       miiphy_write(name, 4, 24, 0x4edf);
+
+                       miiphy_write(name, 5, 0, 0x3100);
+                       miiphy_write(name, 6, 0, 0x2100);
+
+                       //important. enable phy 5 link status, for rmii
+                       miiphy_write(name, 6, 22, 0x873f);
+
+                       miiphy_write(name, 6, 24, 0x8eff);
+                       //disable ports
+                       for (i=0;i<5;i++) {
+                               miiphy_read(name, 0, 24, &val);
+                               val&=~(1<<10);
+                               val&=~(1<<11);
+                               miiphy_write(name, 0, 24, val);
+                       }
+
+                       puts("Reset Soft\n");
+                       miiphy_write(name,0 ,0 ,1<<15);
+                       for (i=0;i<1000;i++)
+                       {
+                               miiphy_read(name,0 ,0 ,&val);
+                               if (!(val&1<<15))
+                                       break;
+                               udelay(1000);
+                       }
+                       if (i==1000)
+                               puts("Failed\n");
+                       else
+                               puts("Success\n");
+                       //enable ports egain
+                       for (i=0;i<5;i++) // enable ports
+                       {
+                               miiphy_read(name, 0, 24, &val);
+                               val|=(1<<10);
+                               val|=(1<<11);
+                               miiphy_write(name, 0, 24, val);
+                       }
+                       puts("\n");
+                       return 0;
+               }
+               puts("failed\n");
+       }
+       puts("\nno known switch found ... \n");
+
+       return 0;
+}
+#endif
+
 #ifdef CONFIG_AR8216_SWITCH
 static int external_switch_ar8216(void)
 {
@@ -345,6 +446,10 @@ int board_eth_init(bd_t *bis)
        *DANUBE_RCU_RST_REQ &=(unsigned long)~1;
        udelay(1000);
 
+#ifdef CONFIG_RTL8306G_SWITCH
+       if (external_switch_rtl8306G()<0)
+               return -1;
+#endif
 #ifdef CONFIG_RTL8306_SWITCH
        if (external_switch_rtl8306()<0)
                return -1;

diff --git a/package/uboot-lantiq/files/include/configs/arv7525PW.h b/package/uboot-lantiq/files/include/configs/arv7525PW.h
new file mode 100644 (file)
index 0000000..ffa5994
--- /dev/null
+++ b/package/uboot-lantiq/files/include/configs/arv7525PW.h
@@ -0,0 +1,18 @@
+#ifndef __CONFIG_H_7525PW
+#define __CONFIG_H_7525PW
+
+#define CONFIG_ARV7525         1
+#define CONFIG_ARCADYAN                "ARV7525PW"
+
+#define CONFIG_SYS_MAX_RAM     32*1024*1024
+#define CONFIG_USE_DDR_PSC_32   1
+#define        CONFIG_SYS_PROMPT       "ARV7525 => "
+
+#define CONFIG_BUTTON_PORT1
+#define CONFIG_BUTTON_PIN      13
+#define CONFIG_BUTTON_LEVEL    0
+
+
+#include "arcadyan-common.h"
+
+#endif

diff --git a/package/uboot-lantiq/files/include/configs/arv752DPW.h b/package/uboot-lantiq/files/include/configs/arv752DPW.h
index 7bf5fa5faf5b029fa4dc6d015bf06fe22cd74309..594ce61e6d753b2238fb9da9e0fd6a5592d4c49c 100644 (file)
--- a/package/uboot-lantiq/files/include/configs/arv752DPW.h
+++ b/package/uboot-lantiq/files/include/configs/arv752DPW.h
@@ -11,8 +11,6 @@
 #define CONFIG_RMII
 #define CONFIG_RTL8306G_SWITCH 1
 //#define CONFIG_EBU_GPIO              0x2
-#define CONFIG_SWITCH_PORT1
-#define CONFIG_SWITCH_PIN      3
 //#define CONFIG_BUTTON_PORT0
 //#define CONFIG_BUTTON_PIN    12
 

diff --git a/package/uboot-lantiq/patches/300-arcadyan.patch b/package/uboot-lantiq/patches/300-arcadyan.patch
index 92a57a25ca2bf240b39138d10f1fa41e75f36875..b98e86dc6003fc1864fa291c5946f778a0b295a8 100644 (file)
--- a/package/uboot-lantiq/patches/300-arcadyan.patch
+++ b/package/uboot-lantiq/patches/300-arcadyan.patch
@@ -39,7 +39,7 @@
  SRCS  := $(COBJS:.o=.c)
 --- a/Makefile
 +++ b/Makefile
-@@ -3414,6 +3414,40 @@
+@@ -3414,6 +3414,41 @@
  ## MIPS32 ifxcpe
  #########################################################################
  
@@ -74,6 +74,7 @@
 +$(eval $(call arcadyan, arv4510PW%config))
 +$(eval $(call arcadyan, arv4518PW%config))
 +$(eval $(call arcadyan, arv7518PW%config))
++$(eval $(call arcadyan, arv7525PW%config))
 +$(eval $(call arcadyan, arv752DPW%config))
 +$(eval $(call arcadyan, arv752DPW22%config))
 +