+++ /dev/null
-From 761432b4edfa1276726c082ba21199236c13a23f Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:50:54 +0100
-Subject: [PATCH 39/57] USB: adds dwc_otg
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/usb/Kconfig | 2 +
- drivers/usb/Makefile | 1 +
- drivers/usb/dwc_otg/Kconfig | 24 +
- drivers/usb/dwc_otg/Makefile | 25 +
- drivers/usb/dwc_otg/dummy_audio.c | 1575 +++++++++++++
- drivers/usb/dwc_otg/dwc_otg_attr.c | 966 ++++++++
- drivers/usb/dwc_otg/dwc_otg_attr.h | 67 +
- drivers/usb/dwc_otg/dwc_otg_cil.c | 3692 ++++++++++++++++++++++++++++++
- drivers/usb/dwc_otg/dwc_otg_cil.h | 1098 +++++++++
- drivers/usb/dwc_otg/dwc_otg_cil_intr.c | 750 ++++++
- drivers/usb/dwc_otg/dwc_otg_driver.c | 1273 ++++++++++
- drivers/usb/dwc_otg/dwc_otg_driver.h | 83 +
- drivers/usb/dwc_otg/dwc_otg_hcd.c | 2852 +++++++++++++++++++++++
- drivers/usb/dwc_otg/dwc_otg_hcd.h | 668 ++++++
- drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1873 +++++++++++++++
- drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 684 ++++++
- drivers/usb/dwc_otg/dwc_otg_pcd.c | 2523 ++++++++++++++++++++
- drivers/usb/dwc_otg/dwc_otg_pcd.h | 248 ++
- drivers/usb/dwc_otg/dwc_otg_pcd_intr.c | 3654 +++++++++++++++++++++++++++++
- drivers/usb/dwc_otg/dwc_otg_regs.h | 2075 +++++++++++++++++
- drivers/usb/dwc_otg/linux/dwc_otg_plat.h | 260 +++
- 21 files changed, 24393 insertions(+)
- create mode 100644 drivers/usb/dwc_otg/Kconfig
- create mode 100644 drivers/usb/dwc_otg/Makefile
- create mode 100644 drivers/usb/dwc_otg/dummy_audio.c
- create mode 100644 drivers/usb/dwc_otg/dwc_otg_attr.c
- create mode 100644 drivers/usb/dwc_otg/dwc_otg_attr.h
- create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.c
- create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.h
- create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_intr.c
- create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.c
- create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.h
- create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.c
- create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.h
- create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
- create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
- create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.c
- create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.h
- create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd_intr.c
- create mode 100644 drivers/usb/dwc_otg/dwc_otg_regs.h
- create mode 100644 drivers/usb/dwc_otg/linux/dwc_otg_plat.h
-
---- a/drivers/usb/Kconfig
-+++ b/drivers/usb/Kconfig
-@@ -88,6 +88,8 @@ if USB
-
- source "drivers/usb/core/Kconfig"
-
-+source "drivers/usb/dwc_otg/Kconfig"
-+
- source "drivers/usb/mon/Kconfig"
-
- source "drivers/usb/wusbcore/Kconfig"
---- a/drivers/usb/Makefile
-+++ b/drivers/usb/Makefile
-@@ -8,6 +8,7 @@ obj-$(CONFIG_USB) += core/
-
- obj-$(CONFIG_USB_DWC3) += dwc3/
- obj-$(CONFIG_USB_DWC2) += dwc2/
-+obj-$(CONFIG_DWC_OTG) += dwc_otg/
-
- obj-$(CONFIG_USB_MON) += mon/
-
---- /dev/null
-+++ b/drivers/usb/dwc_otg/Kconfig
-@@ -0,0 +1,24 @@
-+config DWC_OTG
-+ tristate "Ralink RT305X DWC_OTG support"
-+ depends on SOC_RT305X
-+ ---help---
-+ This driver supports Ralink DWC_OTG
-+
-+choice
-+ prompt "USB Operation Mode"
-+ depends on DWC_OTG
-+ default DWC_OTG_HOST_ONLY
-+
-+config DWC_OTG_HOST_ONLY
-+ bool "HOST ONLY MODE"
-+ depends on DWC_OTG
-+
-+config DWC_OTG_DEVICE_ONLY
-+ bool "DEVICE ONLY MODE"
-+ depends on DWC_OTG
-+
-+endchoice
-+
-+config DWC_OTG_DEBUG
-+ bool "Enable debug mode"
-+ depends on DWC_OTG
---- /dev/null
-+++ b/drivers/usb/dwc_otg/Makefile
-@@ -0,0 +1,25 @@
-+#
-+# Makefile for DWC_otg Highspeed USB controller driver
-+#
-+
-+ifeq ($(CONFIG_DWC_OTG_DEBUG),y)
-+EXTRA_CFLAGS += -DDEBUG
-+endif
-+
-+# Use one of the following flags to compile the software in host-only or
-+# device-only mode.
-+ifeq ($(CONFIG_DWC_OTG_HOST_ONLY),y)
-+EXTRA_CFLAGS += -DDWC_HOST_ONLY
-+EXTRA_CFLAGS += -DDWC_EN_ISOC
-+endif
-+
-+ifeq ($(CONFIG_DWC_OTG_DEVICE_ONLY),y)
-+EXTRA_CFLAGS += -DDWC_DEVICE_ONLY
-+endif
-+
-+obj-$(CONFIG_DWC_OTG) := dwc_otg.o
-+
-+dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o
-+dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
-+dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o
-+dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o
---- /dev/null
-+++ b/drivers/usb/dwc_otg/dummy_audio.c
-@@ -0,0 +1,1575 @@
-+/*
-+ * zero.c -- Gadget Zero, for USB development
-+ *
-+ * Copyright (C) 2003-2004 David Brownell
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+
-+/*
-+ * Gadget Zero only needs two bulk endpoints, and is an example of how you
-+ * can write a hardware-agnostic gadget driver running inside a USB device.
-+ *
-+ * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't
-+ * affect most of the driver.
-+ *
-+ * Use it with the Linux host/master side "usbtest" driver to get a basic
-+ * functional test of your device-side usb stack, or with "usb-skeleton".
-+ *
-+ * It supports two similar configurations. One sinks whatever the usb host
-+ * writes, and in return sources zeroes. The other loops whatever the host
-+ * writes back, so the host can read it. Module options include:
-+ *
-+ * buflen=N default N=4096, buffer size used
-+ * qlen=N default N=32, how many buffers in the loopback queue
-+ * loopdefault default false, list loopback config first
-+ *
-+ * Many drivers will only have one configuration, letting them be much
-+ * simpler if they also don't support high speed operation (like this
-+ * driver does).
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/delay.h>
-+#include <linux/ioport.h>
-+#include <linux/sched.h>
-+#include <linux/slab.h>
-+#include <linux/smp_lock.h>
-+#include <linux/errno.h>
-+#include <linux/init.h>
-+#include <linux/timer.h>
-+#include <linux/list.h>
-+#include <linux/interrupt.h>
-+#include <linux/uts.h>
-+#include <linux/version.h>
-+#include <linux/device.h>
-+#include <linux/moduleparam.h>
-+#include <linux/proc_fs.h>
-+
-+#include <asm/byteorder.h>
-+#include <asm/io.h>
-+#include <asm/irq.h>
-+#include <asm/system.h>
-+#include <asm/unaligned.h>
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
-+# include <linux/usb/ch9.h>
-+#else
-+# include <linux/usb_ch9.h>
-+#endif
-+
-+#include <linux/usb_gadget.h>
-+
-+
-+/*-------------------------------------------------------------------------*/
-+/*-------------------------------------------------------------------------*/
-+
-+
-+static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len)
-+{
-+ int count = 0;
-+ u8 c;
-+ u16 uchar;
-+
-+ /* this insists on correct encodings, though not minimal ones.
-+ * BUT it currently rejects legit 4-byte UTF-8 code points,
-+ * which need surrogate pairs. (Unicode 3.1 can use them.)
-+ */
-+ while (len != 0 && (c = (u8) *s++) != 0) {
-+ if (unlikely(c & 0x80)) {
-+ // 2-byte sequence:
-+ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
-+ if ((c & 0xe0) == 0xc0) {
-+ uchar = (c & 0x1f) << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ // 3-byte sequence (most CJKV characters):
-+ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
-+ } else if ((c & 0xf0) == 0xe0) {
-+ uchar = (c & 0x0f) << 12;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ /* no bogus surrogates */
-+ if (0xd800 <= uchar && uchar <= 0xdfff)
-+ goto fail;
-+
-+ // 4-byte sequence (surrogate pairs, currently rare):
-+ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
-+ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
-+ // (uuuuu = wwww + 1)
-+ // FIXME accept the surrogate code points (only)
-+
-+ } else
-+ goto fail;
-+ } else
-+ uchar = c;
-+ put_unaligned (cpu_to_le16 (uchar), cp++);
-+ count++;
-+ len--;
-+ }
-+ return count;
-+fail:
-+ return -1;
-+}
-+
-+
-+/**
-+ * usb_gadget_get_string - fill out a string descriptor
-+ * @table: of c strings encoded using UTF-8
-+ * @id: string id, from low byte of wValue in get string descriptor
-+ * @buf: at least 256 bytes
-+ *
-+ * Finds the UTF-8 string matching the ID, and converts it into a
-+ * string descriptor in utf16-le.
-+ * Returns length of descriptor (always even) or negative errno
-+ *
-+ * If your driver needs stings in multiple languages, you'll probably
-+ * "switch (wIndex) { ... }" in your ep0 string descriptor logic,
-+ * using this routine after choosing which set of UTF-8 strings to use.
-+ * Note that US-ASCII is a strict subset of UTF-8; any string bytes with
-+ * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1
-+ * characters (which are also widely used in C strings).
-+ */
-+int
-+usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf)
-+{
-+ struct usb_string *s;
-+ int len;
-+
-+ /* descriptor 0 has the language id */
-+ if (id == 0) {
-+ buf [0] = 4;
-+ buf [1] = USB_DT_STRING;
-+ buf [2] = (u8) table->language;
-+ buf [3] = (u8) (table->language >> 8);
-+ return 4;
-+ }
-+ for (s = table->strings; s && s->s; s++)
-+ if (s->id == id)
-+ break;
-+
-+ /* unrecognized: stall. */
-+ if (!s || !s->s)
-+ return -EINVAL;
-+
-+ /* string descriptors have length, tag, then UTF16-LE text */
-+ len = min ((size_t) 126, strlen (s->s));
-+ memset (buf + 2, 0, 2 * len); /* zero all the bytes */
-+ len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len);
-+ if (len < 0)
-+ return -EINVAL;
-+ buf [0] = (len + 1) * 2;
-+ buf [1] = USB_DT_STRING;
-+ return buf [0];
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+/*-------------------------------------------------------------------------*/
-+
-+
-+/**
-+ * usb_descriptor_fillbuf - fill buffer with descriptors
-+ * @buf: Buffer to be filled
-+ * @buflen: Size of buf
-+ * @src: Array of descriptor pointers, terminated by null pointer.
-+ *
-+ * Copies descriptors into the buffer, returning the length or a
-+ * negative error code if they can't all be copied. Useful when
-+ * assembling descriptors for an associated set of interfaces used
-+ * as part of configuring a composite device; or in other cases where
-+ * sets of descriptors need to be marshaled.
-+ */
-+int
-+usb_descriptor_fillbuf(void *buf, unsigned buflen,
-+ const struct usb_descriptor_header **src)
-+{
-+ u8 *dest = buf;
-+
-+ if (!src)
-+ return -EINVAL;
-+
-+ /* fill buffer from src[] until null descriptor ptr */
-+ for (; 0 != *src; src++) {
-+ unsigned len = (*src)->bLength;
-+
-+ if (len > buflen)
-+ return -EINVAL;
-+ memcpy(dest, *src, len);
-+ buflen -= len;
-+ dest += len;
-+ }
-+ return dest - (u8 *)buf;
-+}
-+
-+
-+/**
-+ * usb_gadget_config_buf - builts a complete configuration descriptor
-+ * @config: Header for the descriptor, including characteristics such
-+ * as power requirements and number of interfaces.
-+ * @desc: Null-terminated vector of pointers to the descriptors (interface,
-+ * endpoint, etc) defining all functions in this device configuration.
-+ * @buf: Buffer for the resulting configuration descriptor.
-+ * @length: Length of buffer. If this is not big enough to hold the
-+ * entire configuration descriptor, an error code will be returned.
-+ *
-+ * This copies descriptors into the response buffer, building a descriptor
-+ * for that configuration. It returns the buffer length or a negative
-+ * status code. The config.wTotalLength field is set to match the length
-+ * of the result, but other descriptor fields (including power usage and
-+ * interface count) must be set by the caller.
-+ *
-+ * Gadget drivers could use this when constructing a config descriptor
-+ * in response to USB_REQ_GET_DESCRIPTOR. They will need to patch the
-+ * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed.
-+ */
-+int usb_gadget_config_buf(
-+ const struct usb_config_descriptor *config,
-+ void *buf,
-+ unsigned length,
-+ const struct usb_descriptor_header **desc
-+)
-+{
-+ struct usb_config_descriptor *cp = buf;
-+ int len;
-+
-+ /* config descriptor first */
-+ if (length < USB_DT_CONFIG_SIZE || !desc)
-+ return -EINVAL;
-+ *cp = *config;
-+
-+ /* then interface/endpoint/class/vendor/... */
-+ len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,
-+ length - USB_DT_CONFIG_SIZE, desc);
-+ if (len < 0)
-+ return len;
-+ len += USB_DT_CONFIG_SIZE;
-+ if (len > 0xffff)
-+ return -EINVAL;
-+
-+ /* patch up the config descriptor */
-+ cp->bLength = USB_DT_CONFIG_SIZE;
-+ cp->bDescriptorType = USB_DT_CONFIG;
-+ cp->wTotalLength = cpu_to_le16(len);
-+ cp->bmAttributes |= USB_CONFIG_ATT_ONE;
-+ return len;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+/*-------------------------------------------------------------------------*/
-+
-+
-+#define RBUF_LEN (1024*1024)
-+static int rbuf_start;
-+static int rbuf_len;
-+static __u8 rbuf[RBUF_LEN];
-+
-+/*-------------------------------------------------------------------------*/
-+
-+#define DRIVER_VERSION "St Patrick's Day 2004"
-+
-+static const char shortname [] = "zero";
-+static const char longname [] = "YAMAHA YST-MS35D USB Speaker ";
-+
-+static const char source_sink [] = "source and sink data";
-+static const char loopback [] = "loop input to output";
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * driver assumes self-powered hardware, and
-+ * has no way for users to trigger remote wakeup.
-+ *
-+ * this version autoconfigures as much as possible,
-+ * which is reasonable for most "bulk-only" drivers.
-+ */
-+static const char *EP_IN_NAME; /* source */
-+static const char *EP_OUT_NAME; /* sink */
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* big enough to hold our biggest descriptor */
-+#define USB_BUFSIZ 512
-+
-+struct zero_dev {
-+ spinlock_t lock;
-+ struct usb_gadget *gadget;
-+ struct usb_request *req; /* for control responses */
-+
-+ /* when configured, we have one of two configs:
-+ * - source data (in to host) and sink it (out from host)
-+ * - or loop it back (out from host back in to host)
-+ */
-+ u8 config;
-+ struct usb_ep *in_ep, *out_ep;
-+
-+ /* autoresume timer */
-+ struct timer_list resume;
-+};
-+
-+#define xprintk(d,level,fmt,args...) \
-+ dev_printk(level , &(d)->gadget->dev , fmt , ## args)
-+
-+#ifdef DEBUG
-+#define DBG(dev,fmt,args...) \
-+ xprintk(dev , KERN_DEBUG , fmt , ## args)
-+#else
-+#define DBG(dev,fmt,args...) \
-+ do { } while (0)
-+#endif /* DEBUG */
-+
-+#ifdef VERBOSE
-+#define VDBG DBG
-+#else
-+#define VDBG(dev,fmt,args...) \
-+ do { } while (0)
-+#endif /* VERBOSE */
-+
-+#define ERROR(dev,fmt,args...) \
-+ xprintk(dev , KERN_ERR , fmt , ## args)
-+#define WARN(dev,fmt,args...) \
-+ xprintk(dev , KERN_WARNING , fmt , ## args)
-+#define INFO(dev,fmt,args...) \
-+ xprintk(dev , KERN_INFO , fmt , ## args)
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static unsigned buflen = 4096;
-+static unsigned qlen = 32;
-+static unsigned pattern = 0;
-+
-+module_param (buflen, uint, S_IRUGO|S_IWUSR);
-+module_param (qlen, uint, S_IRUGO|S_IWUSR);
-+module_param (pattern, uint, S_IRUGO|S_IWUSR);
-+
-+/*
-+ * if it's nonzero, autoresume says how many seconds to wait
-+ * before trying to wake up the host after suspend.
-+ */
-+static unsigned autoresume = 0;
-+module_param (autoresume, uint, 0);
-+
-+/*
-+ * Normally the "loopback" configuration is second (index 1) so
-+ * it's not the default. Here's where to change that order, to
-+ * work better with hosts where config changes are problematic.
-+ * Or controllers (like superh) that only support one config.
-+ */
-+static int loopdefault = 0;
-+
-+module_param (loopdefault, bool, S_IRUGO|S_IWUSR);
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Thanks to NetChip Technologies for donating this product ID.
-+ *
-+ * DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!!
-+ * Instead: allocate your own, using normal USB-IF procedures.
-+ */
-+#ifndef CONFIG_USB_ZERO_HNPTEST
-+#define DRIVER_VENDOR_NUM 0x0525 /* NetChip */
-+#define DRIVER_PRODUCT_NUM 0xa4a0 /* Linux-USB "Gadget Zero" */
-+#else
-+#define DRIVER_VENDOR_NUM 0x1a0a /* OTG test device IDs */
-+#define DRIVER_PRODUCT_NUM 0xbadd
-+#endif
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * DESCRIPTORS ... most are static, but strings and (full)
-+ * configuration descriptors are built on demand.
-+ */
-+
-+/*
-+#define STRING_MANUFACTURER 25
-+#define STRING_PRODUCT 42
-+#define STRING_SERIAL 101
-+*/
-+#define STRING_MANUFACTURER 1
-+#define STRING_PRODUCT 2
-+#define STRING_SERIAL 3
-+
-+#define STRING_SOURCE_SINK 250
-+#define STRING_LOOPBACK 251
-+
-+/*
-+ * This device advertises two configurations; these numbers work
-+ * on a pxa250 as well as more flexible hardware.
-+ */
-+#define CONFIG_SOURCE_SINK 3
-+#define CONFIG_LOOPBACK 2
-+
-+/*
-+static struct usb_device_descriptor
-+device_desc = {
-+ .bLength = sizeof device_desc,
-+ .bDescriptorType = USB_DT_DEVICE,
-+
-+ .bcdUSB = __constant_cpu_to_le16 (0x0200),
-+ .bDeviceClass = USB_CLASS_VENDOR_SPEC,
-+
-+ .idVendor = __constant_cpu_to_le16 (DRIVER_VENDOR_NUM),
-+ .idProduct = __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM),
-+ .iManufacturer = STRING_MANUFACTURER,
-+ .iProduct = STRING_PRODUCT,
-+ .iSerialNumber = STRING_SERIAL,
-+ .bNumConfigurations = 2,
-+};
-+*/
-+static struct usb_device_descriptor
-+device_desc = {
-+ .bLength = sizeof device_desc,
-+ .bDescriptorType = USB_DT_DEVICE,
-+ .bcdUSB = __constant_cpu_to_le16 (0x0100),
-+ .bDeviceClass = USB_CLASS_PER_INTERFACE,
-+ .bDeviceSubClass = 0,
-+ .bDeviceProtocol = 0,
-+ .bMaxPacketSize0 = 64,
-+ .bcdDevice = __constant_cpu_to_le16 (0x0100),
-+ .idVendor = __constant_cpu_to_le16 (0x0499),
-+ .idProduct = __constant_cpu_to_le16 (0x3002),
-+ .iManufacturer = STRING_MANUFACTURER,
-+ .iProduct = STRING_PRODUCT,
-+ .iSerialNumber = STRING_SERIAL,
-+ .bNumConfigurations = 1,
-+};
-+
-+static struct usb_config_descriptor
-+z_config = {
-+ .bLength = sizeof z_config,
-+ .bDescriptorType = USB_DT_CONFIG,
-+
-+ /* compute wTotalLength on the fly */
-+ .bNumInterfaces = 2,
-+ .bConfigurationValue = 1,
-+ .iConfiguration = 0,
-+ .bmAttributes = 0x40,
-+ .bMaxPower = 0, /* self-powered */
-+};
-+
-+
-+static struct usb_otg_descriptor
-+otg_descriptor = {
-+ .bLength = sizeof otg_descriptor,
-+ .bDescriptorType = USB_DT_OTG,
-+
-+ .bmAttributes = USB_OTG_SRP,
-+};
-+
-+/* one interface in each configuration */
-+#ifdef CONFIG_USB_GADGET_DUALSPEED
-+
-+/*
-+ * usb 2.0 devices need to expose both high speed and full speed
-+ * descriptors, unless they only run at full speed.
-+ *
-+ * that means alternate endpoint descriptors (bigger packets)
-+ * and a "device qualifier" ... plus more construction options
-+ * for the config descriptor.
-+ */
-+
-+static struct usb_qualifier_descriptor
-+dev_qualifier = {
-+ .bLength = sizeof dev_qualifier,
-+ .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
-+
-+ .bcdUSB = __constant_cpu_to_le16 (0x0200),
-+ .bDeviceClass = USB_CLASS_VENDOR_SPEC,
-+
-+ .bNumConfigurations = 2,
-+};
-+
-+
-+struct usb_cs_as_general_descriptor {
-+ __u8 bLength;
-+ __u8 bDescriptorType;
-+
-+ __u8 bDescriptorSubType;
-+ __u8 bTerminalLink;
-+ __u8 bDelay;
-+ __u16 wFormatTag;
-+} __attribute__ ((packed));
-+
-+struct usb_cs_as_format_descriptor {
-+ __u8 bLength;
-+ __u8 bDescriptorType;
-+
-+ __u8 bDescriptorSubType;
-+ __u8 bFormatType;
-+ __u8 bNrChannels;
-+ __u8 bSubframeSize;
-+ __u8 bBitResolution;
-+ __u8 bSamfreqType;
-+ __u8 tLowerSamFreq[3];
-+ __u8 tUpperSamFreq[3];
-+} __attribute__ ((packed));
-+
-+static const struct usb_interface_descriptor
-+z_audio_control_if_desc = {
-+ .bLength = sizeof z_audio_control_if_desc,
-+ .bDescriptorType = USB_DT_INTERFACE,
-+ .bInterfaceNumber = 0,
-+ .bAlternateSetting = 0,
-+ .bNumEndpoints = 0,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = 0x1,
-+ .bInterfaceProtocol = 0,
-+ .iInterface = 0,
-+};
-+
-+static const struct usb_interface_descriptor
-+z_audio_if_desc = {
-+ .bLength = sizeof z_audio_if_desc,
-+ .bDescriptorType = USB_DT_INTERFACE,
-+ .bInterfaceNumber = 1,
-+ .bAlternateSetting = 0,
-+ .bNumEndpoints = 0,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = 0x2,
-+ .bInterfaceProtocol = 0,
-+ .iInterface = 0,
-+};
-+
-+static const struct usb_interface_descriptor
-+z_audio_if_desc2 = {
-+ .bLength = sizeof z_audio_if_desc,
-+ .bDescriptorType = USB_DT_INTERFACE,
-+ .bInterfaceNumber = 1,
-+ .bAlternateSetting = 1,
-+ .bNumEndpoints = 1,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = 0x2,
-+ .bInterfaceProtocol = 0,
-+ .iInterface = 0,
-+};
-+
-+static const struct usb_cs_as_general_descriptor
-+z_audio_cs_as_if_desc = {
-+ .bLength = 7,
-+ .bDescriptorType = 0x24,
-+
-+ .bDescriptorSubType = 0x01,
-+ .bTerminalLink = 0x01,
-+ .bDelay = 0x0,
-+ .wFormatTag = __constant_cpu_to_le16 (0x0001)
-+};
-+
-+
-+static const struct usb_cs_as_format_descriptor
-+z_audio_cs_as_format_desc = {
-+ .bLength = 0xe,
-+ .bDescriptorType = 0x24,
-+
-+ .bDescriptorSubType = 2,
-+ .bFormatType = 1,
-+ .bNrChannels = 1,
-+ .bSubframeSize = 1,
-+ .bBitResolution = 8,
-+ .bSamfreqType = 0,
-+ .tLowerSamFreq = {0x7e, 0x13, 0x00},
-+ .tUpperSamFreq = {0xe2, 0xd6, 0x00},
-+};
-+
-+static const struct usb_endpoint_descriptor
-+z_iso_ep = {
-+ .bLength = 0x09,
-+ .bDescriptorType = 0x05,
-+ .bEndpointAddress = 0x04,
-+ .bmAttributes = 0x09,
-+ .wMaxPacketSize = 0x0038,
-+ .bInterval = 0x01,
-+ .bRefresh = 0x00,
-+ .bSynchAddress = 0x00,
-+};
-+
-+static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+// 9 bytes
-+static char z_ac_interface_header_desc[] =
-+{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };
-+
-+// 12 bytes
-+static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02,
-+ 0x03, 0x00, 0x00, 0x00};
-+// 13 bytes
-+static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00,
-+ 0x02, 0x00, 0x02, 0x00, 0x00};
-+// 9 bytes
-+static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02,
-+ 0x00};
-+
-+static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00,
-+ 0x00};
-+
-+static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00,
-+ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
-+ 0x00};
-+
-+static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00,
-+ 0x00};
-+
-+static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00,
-+ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
-+ 0x00};
-+
-+static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00,
-+ 0x00};
-+
-+static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00,
-+ 0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,
-+ 0x00};
-+
-+static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00,
-+ 0x00};
-+
-+static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00,
-+ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,
-+ 0x00};
-+
-+static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,
-+ 0x00};
-+
-+static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00,
-+ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,
-+ 0x00};
-+
-+static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+
-+
-+static const struct usb_descriptor_header *z_function [] = {
-+ (struct usb_descriptor_header *) &z_audio_control_if_desc,
-+ (struct usb_descriptor_header *) &z_ac_interface_header_desc,
-+ (struct usb_descriptor_header *) &z_0,
-+ (struct usb_descriptor_header *) &z_1,
-+ (struct usb_descriptor_header *) &z_2,
-+ (struct usb_descriptor_header *) &z_audio_if_desc,
-+ (struct usb_descriptor_header *) &z_audio_if_desc2,
-+ (struct usb_descriptor_header *) &z_audio_cs_as_if_desc,
-+ (struct usb_descriptor_header *) &z_audio_cs_as_format_desc,
-+ (struct usb_descriptor_header *) &z_iso_ep,
-+ (struct usb_descriptor_header *) &z_iso_ep2,
-+ (struct usb_descriptor_header *) &za_0,
-+ (struct usb_descriptor_header *) &za_1,
-+ (struct usb_descriptor_header *) &za_2,
-+ (struct usb_descriptor_header *) &za_3,
-+ (struct usb_descriptor_header *) &za_4,
-+ (struct usb_descriptor_header *) &za_5,
-+ (struct usb_descriptor_header *) &za_6,
-+ (struct usb_descriptor_header *) &za_7,
-+ (struct usb_descriptor_header *) &za_8,
-+ (struct usb_descriptor_header *) &za_9,
-+ (struct usb_descriptor_header *) &za_10,
-+ (struct usb_descriptor_header *) &za_11,
-+ (struct usb_descriptor_header *) &za_12,
-+ (struct usb_descriptor_header *) &za_13,
-+ (struct usb_descriptor_header *) &za_14,
-+ (struct usb_descriptor_header *) &za_15,
-+ (struct usb_descriptor_header *) &za_16,
-+ (struct usb_descriptor_header *) &za_17,
-+ (struct usb_descriptor_header *) &za_18,
-+ (struct usb_descriptor_header *) &za_19,
-+ (struct usb_descriptor_header *) &za_20,
-+ (struct usb_descriptor_header *) &za_21,
-+ (struct usb_descriptor_header *) &za_22,
-+ (struct usb_descriptor_header *) &za_23,
-+ (struct usb_descriptor_header *) &za_24,
-+ NULL,
-+};
-+
-+/* maxpacket and other transfer characteristics vary by speed. */
-+#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs))
-+
-+#else
-+
-+/* if there's no high speed support, maxpacket doesn't change. */
-+#define ep_desc(g,hs,fs) fs
-+
-+#endif /* !CONFIG_USB_GADGET_DUALSPEED */
-+
-+static char manufacturer [40];
-+//static char serial [40];
-+static char serial [] = "Ser 00 em";
-+
-+/* static strings, in UTF-8 */
-+static struct usb_string strings [] = {
-+ { STRING_MANUFACTURER, manufacturer, },
-+ { STRING_PRODUCT, longname, },
-+ { STRING_SERIAL, serial, },
-+ { STRING_LOOPBACK, loopback, },
-+ { STRING_SOURCE_SINK, source_sink, },
-+ { } /* end of list */
-+};
-+
-+static struct usb_gadget_strings stringtab = {
-+ .language = 0x0409, /* en-us */
-+ .strings = strings,
-+};
-+
-+/*
-+ * config descriptors are also handcrafted. these must agree with code
-+ * that sets configurations, and with code managing interfaces and their
-+ * altsettings. other complexity may come from:
-+ *
-+ * - high speed support, including "other speed config" rules
-+ * - multiple configurations
-+ * - interfaces with alternate settings
-+ * - embedded class or vendor-specific descriptors
-+ *
-+ * this handles high speed, and has a second config that could as easily
-+ * have been an alternate interface setting (on most hardware).
-+ *
-+ * NOTE: to demonstrate (and test) more USB capabilities, this driver
-+ * should include an altsetting to test interrupt transfers, including
-+ * high bandwidth modes at high speed. (Maybe work like Intel's test
-+ * device?)
-+ */
-+static int
-+config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index)
-+{
-+ int len;
-+ const struct usb_descriptor_header **function;
-+
-+ function = z_function;
-+ len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function);
-+ if (len < 0)
-+ return len;
-+ ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
-+ return len;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static struct usb_request *
-+alloc_ep_req (struct usb_ep *ep, unsigned length)
-+{
-+ struct usb_request *req;
-+
-+ req = usb_ep_alloc_request (ep, GFP_ATOMIC);
-+ if (req) {
-+ req->length = length;
-+ req->buf = usb_ep_alloc_buffer (ep, length,
-+ &req->dma, GFP_ATOMIC);
-+ if (!req->buf) {
-+ usb_ep_free_request (ep, req);
-+ req = NULL;
-+ }
-+ }
-+ return req;
-+}
-+
-+static void free_ep_req (struct usb_ep *ep, struct usb_request *req)
-+{
-+ if (req->buf)
-+ usb_ep_free_buffer (ep, req->buf, req->dma, req->length);
-+ usb_ep_free_request (ep, req);
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* optionally require specific source/sink data patterns */
-+
-+static int
-+check_read_data (
-+ struct zero_dev *dev,
-+ struct usb_ep *ep,
-+ struct usb_request *req
-+)
-+{
-+ unsigned i;
-+ u8 *buf = req->buf;
-+
-+ for (i = 0; i < req->actual; i++, buf++) {
-+ switch (pattern) {
-+ /* all-zeroes has no synchronization issues */
-+ case 0:
-+ if (*buf == 0)
-+ continue;
-+ break;
-+ /* mod63 stays in sync with short-terminated transfers,
-+ * or otherwise when host and gadget agree on how large
-+ * each usb transfer request should be. resync is done
-+ * with set_interface or set_config.
-+ */
-+ case 1:
-+ if (*buf == (u8)(i % 63))
-+ continue;
-+ break;
-+ }
-+ ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf);
-+ usb_ep_set_halt (ep);
-+ return -EINVAL;
-+ }
-+ return 0;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void zero_reset_config (struct zero_dev *dev)
-+{
-+ if (dev->config == 0)
-+ return;
-+
-+ DBG (dev, "reset config\n");
-+
-+ /* just disable endpoints, forcing completion of pending i/o.
-+ * all our completion handlers free their requests in this case.
-+ */
-+ if (dev->in_ep) {
-+ usb_ep_disable (dev->in_ep);
-+ dev->in_ep = NULL;
-+ }
-+ if (dev->out_ep) {
-+ usb_ep_disable (dev->out_ep);
-+ dev->out_ep = NULL;
-+ }
-+ dev->config = 0;
-+ del_timer (&dev->resume);
-+}
-+
-+#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos))
-+
-+static void
-+zero_isoc_complete (struct usb_ep *ep, struct usb_request *req)
-+{
-+ struct zero_dev *dev = ep->driver_data;
-+ int status = req->status;
-+ int i, j;
-+
-+ switch (status) {
-+
-+ case 0: /* normal completion? */
-+ //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual);
-+ for (i=0, j=rbuf_start; i<req->actual; i++) {
-+ //printk ("%02x ", ((__u8*)req->buf)[i]);
-+ rbuf[j] = ((__u8*)req->buf)[i];
-+ j++;
-+ if (j >= RBUF_LEN) j=0;
-+ }
-+ rbuf_start = j;
-+ //printk ("\n\n");
-+
-+ if (rbuf_len < RBUF_LEN) {
-+ rbuf_len += req->actual;
-+ if (rbuf_len > RBUF_LEN) {
-+ rbuf_len = RBUF_LEN;
-+ }
-+ }
-+
-+ break;
-+
-+ /* this endpoint is normally active while we're configured */
-+ case -ECONNABORTED: /* hardware forced ep reset */
-+ case -ECONNRESET: /* request dequeued */
-+ case -ESHUTDOWN: /* disconnect from host */
-+ VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status,
-+ req->actual, req->length);
-+ if (ep == dev->out_ep)
-+ check_read_data (dev, ep, req);
-+ free_ep_req (ep, req);
-+ return;
-+
-+ case -EOVERFLOW: /* buffer overrun on read means that
-+ * we didn't provide a big enough
-+ * buffer.
-+ */
-+ default:
-+#if 1
-+ DBG (dev, "%s complete --> %d, %d/%d\n", ep->name,
-+ status, req->actual, req->length);
-+#endif
-+ case -EREMOTEIO: /* short read */
-+ break;
-+ }
-+
-+ status = usb_ep_queue (ep, req, GFP_ATOMIC);
-+ if (status) {
-+ ERROR (dev, "kill %s: resubmit %d bytes --> %d\n",
-+ ep->name, req->length, status);
-+ usb_ep_set_halt (ep);
-+ /* FIXME recover later ... somehow */
-+ }
-+}
-+
-+static struct usb_request *
-+zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags)
-+{
-+ struct usb_request *req;
-+ int status;
-+
-+ req = alloc_ep_req (ep, 512);
-+ if (!req)
-+ return NULL;
-+
-+ req->complete = zero_isoc_complete;
-+
-+ status = usb_ep_queue (ep, req, gfp_flags);
-+ if (status) {
-+ struct zero_dev *dev = ep->driver_data;
-+
-+ ERROR (dev, "start %s --> %d\n", ep->name, status);
-+ free_ep_req (ep, req);
-+ req = NULL;
-+ }
-+
-+ return req;
-+}
-+
-+/* change our operational config. this code must agree with the code
-+ * that returns config descriptors, and altsetting code.
-+ *
-+ * it's also responsible for power management interactions. some
-+ * configurations might not work with our current power sources.
-+ *
-+ * note that some device controller hardware will constrain what this
-+ * code can do, perhaps by disallowing more than one configuration or
-+ * by limiting configuration choices (like the pxa2xx).
-+ */
-+static int
-+zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags)
-+{
-+ int result = 0;
-+ struct usb_gadget *gadget = dev->gadget;
-+ const struct usb_endpoint_descriptor *d;
-+ struct usb_ep *ep;
-+
-+ if (number == dev->config)
-+ return 0;
-+
-+ zero_reset_config (dev);
-+
-+ gadget_for_each_ep (ep, gadget) {
-+
-+ if (strcmp (ep->name, "ep4") == 0) {
-+
-+ d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6
-+ result = usb_ep_enable (ep, d);
-+
-+ if (result == 0) {
-+ ep->driver_data = dev;
-+ dev->in_ep = ep;
-+
-+ if (zero_start_isoc_ep (ep, gfp_flags) != 0) {
-+
-+ dev->in_ep = ep;
-+ continue;
-+ }
-+
-+ usb_ep_disable (ep);
-+ result = -EIO;
-+ }
-+ }
-+
-+ }
-+
-+ dev->config = number;
-+ return result;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req)
-+{
-+ if (req->status || req->actual != req->length)
-+ DBG ((struct zero_dev *) ep->driver_data,
-+ "setup complete --> %d, %d/%d\n",
-+ req->status, req->actual, req->length);
-+}
-+
-+/*
-+ * The setup() callback implements all the ep0 functionality that's
-+ * not handled lower down, in hardware or the hardware driver (like
-+ * device and endpoint feature flags, and their status). It's all
-+ * housekeeping for the gadget function we're implementing. Most of
-+ * the work is in config-specific setup.
-+ */
-+static int
-+zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
-+{
-+ struct zero_dev *dev = get_gadget_data (gadget);
-+ struct usb_request *req = dev->req;
-+ int value = -EOPNOTSUPP;
-+
-+ /* usually this stores reply data in the pre-allocated ep0 buffer,
-+ * but config change events will reconfigure hardware.
-+ */
-+ req->zero = 0;
-+ switch (ctrl->bRequest) {
-+
-+ case USB_REQ_GET_DESCRIPTOR:
-+
-+ switch (ctrl->wValue >> 8) {
-+
-+ case USB_DT_DEVICE:
-+ value = min (ctrl->wLength, (u16) sizeof device_desc);
-+ memcpy (req->buf, &device_desc, value);
-+ break;
-+#ifdef CONFIG_USB_GADGET_DUALSPEED
-+ case USB_DT_DEVICE_QUALIFIER:
-+ if (!gadget->is_dualspeed)
-+ break;
-+ value = min (ctrl->wLength, (u16) sizeof dev_qualifier);
-+ memcpy (req->buf, &dev_qualifier, value);
-+ break;
-+
-+ case USB_DT_OTHER_SPEED_CONFIG:
-+ if (!gadget->is_dualspeed)
-+ break;
-+ // FALLTHROUGH
-+#endif /* CONFIG_USB_GADGET_DUALSPEED */
-+ case USB_DT_CONFIG:
-+ value = config_buf (gadget, req->buf,
-+ ctrl->wValue >> 8,
-+ ctrl->wValue & 0xff);
-+ if (value >= 0)
-+ value = min (ctrl->wLength, (u16) value);
-+ break;
-+
-+ case USB_DT_STRING:
-+ /* wIndex == language code.
-+ * this driver only handles one language, you can
-+ * add string tables for other languages, using
-+ * any UTF-8 characters
-+ */
-+ value = usb_gadget_get_string (&stringtab,
-+ ctrl->wValue & 0xff, req->buf);
-+ if (value >= 0) {
-+ value = min (ctrl->wLength, (u16) value);
-+ }
-+ break;
-+ }
-+ break;
-+
-+ /* currently two configs, two speeds */
-+ case USB_REQ_SET_CONFIGURATION:
-+ if (ctrl->bRequestType != 0)
-+ goto unknown;
-+
-+ spin_lock (&dev->lock);
-+ value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC);
-+ spin_unlock (&dev->lock);
-+ break;
-+ case USB_REQ_GET_CONFIGURATION:
-+ if (ctrl->bRequestType != USB_DIR_IN)
-+ goto unknown;
-+ *(u8 *)req->buf = dev->config;
-+ value = min (ctrl->wLength, (u16) 1);
-+ break;
-+
-+ /* until we add altsetting support, or other interfaces,
-+ * only 0/0 are possible. pxa2xx only supports 0/0 (poorly)
-+ * and already killed pending endpoint I/O.
-+ */
-+ case USB_REQ_SET_INTERFACE:
-+
-+ if (ctrl->bRequestType != USB_RECIP_INTERFACE)
-+ goto unknown;
-+ spin_lock (&dev->lock);
-+ if (dev->config) {
-+ u8 config = dev->config;
-+
-+ /* resets interface configuration, forgets about
-+ * previous transaction state (queued bufs, etc)
-+ * and re-inits endpoint state (toggle etc)
-+ * no response queued, just zero status == success.
-+ * if we had more than one interface we couldn't
-+ * use this "reset the config" shortcut.
-+ */
-+ zero_reset_config (dev);
-+ zero_set_config (dev, config, GFP_ATOMIC);
-+ value = 0;
-+ }
-+ spin_unlock (&dev->lock);
-+ break;
-+ case USB_REQ_GET_INTERFACE:
-+ if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) {
-+ value = ctrl->wLength;
-+ break;
-+ }
-+ else {
-+ if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
-+ goto unknown;
-+ if (!dev->config)
-+ break;
-+ if (ctrl->wIndex != 0) {
-+ value = -EDOM;
-+ break;
-+ }
-+ *(u8 *)req->buf = 0;
-+ value = min (ctrl->wLength, (u16) 1);
-+ }
-+ break;
-+
-+ /*
-+ * These are the same vendor-specific requests supported by
-+ * Intel's USB 2.0 compliance test devices. We exceed that
-+ * device spec by allowing multiple-packet requests.
-+ */
-+ case 0x5b: /* control WRITE test -- fill the buffer */
-+ if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR))
-+ goto unknown;
-+ if (ctrl->wValue || ctrl->wIndex)
-+ break;
-+ /* just read that many bytes into the buffer */
-+ if (ctrl->wLength > USB_BUFSIZ)
-+ break;
-+ value = ctrl->wLength;
-+ break;
-+ case 0x5c: /* control READ test -- return the buffer */
-+ if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR))
-+ goto unknown;
-+ if (ctrl->wValue || ctrl->wIndex)
-+ break;
-+ /* expect those bytes are still in the buffer; send back */
-+ if (ctrl->wLength > USB_BUFSIZ
-+ || ctrl->wLength != req->length)
-+ break;
-+ value = ctrl->wLength;
-+ break;
-+
-+ case 0x01: // SET_CUR
-+ case 0x02:
-+ case 0x03:
-+ case 0x04:
-+ case 0x05:
-+ value = ctrl->wLength;
-+ break;
-+ case 0x81:
-+ switch (ctrl->wValue) {
-+ case 0x0201:
-+ case 0x0202:
-+ ((u8*)req->buf)[0] = 0x00;
-+ ((u8*)req->buf)[1] = 0xe3;
-+ break;
-+ case 0x0300:
-+ case 0x0500:
-+ ((u8*)req->buf)[0] = 0x00;
-+ break;
-+ }
-+ //((u8*)req->buf)[0] = 0x81;
-+ //((u8*)req->buf)[1] = 0x81;
-+ value = ctrl->wLength;
-+ break;
-+ case 0x82:
-+ switch (ctrl->wValue) {
-+ case 0x0201:
-+ case 0x0202:
-+ ((u8*)req->buf)[0] = 0x00;
-+ ((u8*)req->buf)[1] = 0xc3;
-+ break;
-+ case 0x0300:
-+ case 0x0500:
-+ ((u8*)req->buf)[0] = 0x00;
-+ break;
-+ }
-+ //((u8*)req->buf)[0] = 0x82;
-+ //((u8*)req->buf)[1] = 0x82;
-+ value = ctrl->wLength;
-+ break;
-+ case 0x83:
-+ switch (ctrl->wValue) {
-+ case 0x0201:
-+ case 0x0202:
-+ ((u8*)req->buf)[0] = 0x00;
-+ ((u8*)req->buf)[1] = 0x00;
-+ break;
-+ case 0x0300:
-+ ((u8*)req->buf)[0] = 0x60;
-+ break;
-+ case 0x0500:
-+ ((u8*)req->buf)[0] = 0x18;
-+ break;
-+ }
-+ //((u8*)req->buf)[0] = 0x83;
-+ //((u8*)req->buf)[1] = 0x83;
-+ value = ctrl->wLength;
-+ break;
-+ case 0x84:
-+ switch (ctrl->wValue) {
-+ case 0x0201:
-+ case 0x0202:
-+ ((u8*)req->buf)[0] = 0x00;
-+ ((u8*)req->buf)[1] = 0x01;
-+ break;
-+ case 0x0300:
-+ case 0x0500:
-+ ((u8*)req->buf)[0] = 0x08;
-+ break;
-+ }
-+ //((u8*)req->buf)[0] = 0x84;
-+ //((u8*)req->buf)[1] = 0x84;
-+ value = ctrl->wLength;
-+ break;
-+ case 0x85:
-+ ((u8*)req->buf)[0] = 0x85;
-+ ((u8*)req->buf)[1] = 0x85;
-+ value = ctrl->wLength;
-+ break;
-+
-+
-+ default:
-+unknown:
-+ printk("unknown control req%02x.%02x v%04x i%04x l%d\n",
-+ ctrl->bRequestType, ctrl->bRequest,
-+ ctrl->wValue, ctrl->wIndex, ctrl->wLength);
-+ }
-+
-+ /* respond with data transfer before status phase? */
-+ if (value >= 0) {
-+ req->length = value;
-+ req->zero = value < ctrl->wLength
-+ && (value % gadget->ep0->maxpacket) == 0;
-+ value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC);
-+ if (value < 0) {
-+ DBG (dev, "ep_queue < 0 --> %d\n", value);
-+ req->status = 0;
-+ zero_setup_complete (gadget->ep0, req);
-+ }
-+ }
-+
-+ /* device either stalls (value < 0) or reports success */
-+ return value;
-+}
-+
-+static void
-+zero_disconnect (struct usb_gadget *gadget)
-+{
-+ struct zero_dev *dev = get_gadget_data (gadget);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave (&dev->lock, flags);
-+ zero_reset_config (dev);
-+
-+ /* a more significant application might have some non-usb
-+ * activities to quiesce here, saving resources like power
-+ * or pushing the notification up a network stack.
-+ */
-+ spin_unlock_irqrestore (&dev->lock, flags);
-+
-+ /* next we may get setup() calls to enumerate new connections;
-+ * or an unbind() during shutdown (including removing module).
-+ */
-+}
-+
-+static void
-+zero_autoresume (unsigned long _dev)
-+{
-+ struct zero_dev *dev = (struct zero_dev *) _dev;
-+ int status;
-+
-+ /* normally the host would be woken up for something
-+ * more significant than just a timer firing...
-+ */
-+ if (dev->gadget->speed != USB_SPEED_UNKNOWN) {
-+ status = usb_gadget_wakeup (dev->gadget);
-+ DBG (dev, "wakeup --> %d\n", status);
-+ }
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void
-+zero_unbind (struct usb_gadget *gadget)
-+{
-+ struct zero_dev *dev = get_gadget_data (gadget);
-+
-+ DBG (dev, "unbind\n");
-+
-+ /* we've already been disconnected ... no i/o is active */
-+ if (dev->req)
-+ free_ep_req (gadget->ep0, dev->req);
-+ del_timer_sync (&dev->resume);
-+ kfree (dev);
-+ set_gadget_data (gadget, NULL);
-+}
-+
-+static int
-+zero_bind (struct usb_gadget *gadget)
-+{
-+ struct zero_dev *dev;
-+ //struct usb_ep *ep;
-+
-+ printk("binding\n");
-+ /*
-+ * DRIVER POLICY CHOICE: you may want to do this differently.
-+ * One thing to avoid is reusing a bcdDevice revision code
-+ * with different host-visible configurations or behavior
-+ * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc
-+ */
-+ //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201);
-+
-+
-+ /* ok, we made sense of the hardware ... */
-+ dev = kmalloc (sizeof *dev, SLAB_KERNEL);
-+ if (!dev)
-+ return -ENOMEM;
-+ memset (dev, 0, sizeof *dev);
-+ spin_lock_init (&dev->lock);
-+ dev->gadget = gadget;
-+ set_gadget_data (gadget, dev);
-+
-+ /* preallocate control response and buffer */
-+ dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL);
-+ if (!dev->req)
-+ goto enomem;
-+ dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ,
-+ &dev->req->dma, GFP_KERNEL);
-+ if (!dev->req->buf)
-+ goto enomem;
-+
-+ dev->req->complete = zero_setup_complete;
-+
-+ device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
-+
-+#ifdef CONFIG_USB_GADGET_DUALSPEED
-+ /* assume ep0 uses the same value for both speeds ... */
-+ dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0;
-+
-+ /* and that all endpoints are dual-speed */
-+ //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress;
-+ //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress;
-+#endif
-+
-+ usb_gadget_set_selfpowered (gadget);
-+
-+ init_timer (&dev->resume);
-+ dev->resume.function = zero_autoresume;
-+ dev->resume.data = (unsigned long) dev;
-+
-+ gadget->ep0->driver_data = dev;
-+
-+ INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname);
-+ INFO (dev, "using %s, OUT %s IN %s\n", gadget->name,
-+ EP_OUT_NAME, EP_IN_NAME);
-+
-+ snprintf (manufacturer, sizeof manufacturer,
-+ UTS_SYSNAME " " UTS_RELEASE " with %s",
-+ gadget->name);
-+
-+ return 0;
-+
-+enomem:
-+ zero_unbind (gadget);
-+ return -ENOMEM;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void
-+zero_suspend (struct usb_gadget *gadget)
-+{
-+ struct zero_dev *dev = get_gadget_data (gadget);
-+
-+ if (gadget->speed == USB_SPEED_UNKNOWN)
-+ return;
-+
-+ if (autoresume) {
-+ mod_timer (&dev->resume, jiffies + (HZ * autoresume));
-+ DBG (dev, "suspend, wakeup in %d seconds\n", autoresume);
-+ } else
-+ DBG (dev, "suspend\n");
-+}
-+
-+static void
-+zero_resume (struct usb_gadget *gadget)
-+{
-+ struct zero_dev *dev = get_gadget_data (gadget);
-+
-+ DBG (dev, "resume\n");
-+ del_timer (&dev->resume);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static struct usb_gadget_driver zero_driver = {
-+#ifdef CONFIG_USB_GADGET_DUALSPEED
-+ .speed = USB_SPEED_HIGH,
-+#else
-+ .speed = USB_SPEED_FULL,
-+#endif
-+ .function = (char *) longname,
-+ .bind = zero_bind,
-+ .unbind = zero_unbind,
-+
-+ .setup = zero_setup,
-+ .disconnect = zero_disconnect,
-+
-+ .suspend = zero_suspend,
-+ .resume = zero_resume,
-+
-+ .driver = {
-+ .name = (char *) shortname,
-+ // .shutdown = ...
-+ // .suspend = ...
-+ // .resume = ...
-+ },
-+};
-+
-+MODULE_AUTHOR ("David Brownell");
-+MODULE_LICENSE ("Dual BSD/GPL");
-+
-+static struct proc_dir_entry *pdir, *pfile;
-+
-+static int isoc_read_data (char *page, char **start,
-+ off_t off, int count,
-+ int *eof, void *data)
-+{
-+ int i;
-+ static int c = 0;
-+ static int done = 0;
-+ static int s = 0;
-+
-+/*
-+ printk ("\ncount: %d\n", count);
-+ printk ("rbuf_start: %d\n", rbuf_start);
-+ printk ("rbuf_len: %d\n", rbuf_len);
-+ printk ("off: %d\n", off);
-+ printk ("start: %p\n\n", *start);
-+*/
-+ if (done) {
-+ c = 0;
-+ done = 0;
-+ *eof = 1;
-+ return 0;
-+ }
-+
-+ if (c == 0) {
-+ if (rbuf_len == RBUF_LEN)
-+ s = rbuf_start;
-+ else s = 0;
-+ }
-+
-+ for (i=0; i<count && c<rbuf_len; i++, c++) {
-+ page[i] = rbuf[(c+s) % RBUF_LEN];
-+ }
-+ *start = page;
-+
-+ if (c >= rbuf_len) {
-+ *eof = 1;
-+ done = 1;
-+ }
-+
-+
-+ return i;
-+}
-+
-+static int __init init (void)
-+{
-+
-+ int retval = 0;
-+
-+ pdir = proc_mkdir("isoc_test", NULL);
-+ if(pdir == NULL) {
-+ retval = -ENOMEM;
-+ printk("Error creating dir\n");
-+ goto done;
-+ }
-+ pdir->owner = THIS_MODULE;
-+
-+ pfile = create_proc_read_entry("isoc_data",
-+ 0444, pdir,
-+ isoc_read_data,
-+ NULL);
-+ if (pfile == NULL) {
-+ retval = -ENOMEM;
-+ printk("Error creating file\n");
-+ goto no_file;
-+ }
-+ pfile->owner = THIS_MODULE;
-+
-+ return usb_gadget_register_driver (&zero_driver);
-+
-+ no_file:
-+ remove_proc_entry("isoc_data", NULL);
-+ done:
-+ return retval;
-+}
-+module_init (init);
-+
-+static void __exit cleanup (void)
-+{
-+
-+ usb_gadget_unregister_driver (&zero_driver);
-+
-+ remove_proc_entry("isoc_data", pdir);
-+ remove_proc_entry("isoc_test", NULL);
-+}
-+module_exit (cleanup);
---- /dev/null
-+++ b/drivers/usb/dwc_otg/dwc_otg_attr.c
-@@ -0,0 +1,966 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
-+ * $Revision: 1.2 $
-+ * $Date: 2008-11-21 05:39:15 $
-+ * $Change: 1064918 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ *
-+ * The diagnostic interface will provide access to the controller for
-+ * bringing up the hardware and testing. The Linux driver attributes
-+ * feature will be used to provide the Linux Diagnostic
-+ * Interface. These attributes are accessed through sysfs.
-+ */
-+
-+/** @page "Linux Module Attributes"
-+ *
-+ * The Linux module attributes feature is used to provide the Linux
-+ * Diagnostic Interface. These attributes are accessed through sysfs.
-+ * The diagnostic interface will provide access to the controller for
-+ * bringing up the hardware and testing.
-+
-+
-+ The following table shows the attributes.
-+ <table>
-+ <tr>
-+ <td><b> Name</b></td>
-+ <td><b> Description</b></td>
-+ <td><b> Access</b></td>
-+ </tr>
-+
-+ <tr>
-+ <td> mode </td>
-+ <td> Returns the current mode: 0 for device mode, 1 for host mode</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hnpcapable </td>
-+ <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
-+ Read returns the current value.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> srpcapable </td>
-+ <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
-+ Read returns the current value.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hnp </td>
-+ <td> Initiates the Host Negotiation Protocol. Read returns the status.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> srp </td>
-+ <td> Initiates the Session Request Protocol. Read returns the status.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> buspower </td>
-+ <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> bussuspend </td>
-+ <td> Suspends the USB bus.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> busconnected </td>
-+ <td> Gets the connection status of the bus</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gotgctl </td>
-+ <td> Gets or sets the Core Control Status Register.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gusbcfg </td>
-+ <td> Gets or sets the Core USB Configuration Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> grxfsiz </td>
-+ <td> Gets or sets the Receive FIFO Size Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gnptxfsiz </td>
-+ <td> Gets or sets the non-periodic Transmit Size Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gpvndctl </td>
-+ <td> Gets or sets the PHY Vendor Control Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> ggpio </td>
-+ <td> Gets the value in the lower 16-bits of the General Purpose IO Register
-+ or sets the upper 16 bits.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> guid </td>
-+ <td> Gets or sets the value of the User ID Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gsnpsid </td>
-+ <td> Gets the value of the Synopsys ID Regester</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> devspeed </td>
-+ <td> Gets or sets the device speed setting in the DCFG register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> enumspeed </td>
-+ <td> Gets the device enumeration Speed.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hptxfsiz </td>
-+ <td> Gets the value of the Host Periodic Transmit FIFO</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hprt0 </td>
-+ <td> Gets or sets the value in the Host Port Control and Status Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> regoffset </td>
-+ <td> Sets the register offset for the next Register Access</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> regvalue </td>
-+ <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> remote_wakeup </td>
-+ <td> On read, shows the status of Remote Wakeup. On write, initiates a remote
-+ wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
-+ Wakeup signalling bit in the Device Control Register is set for 1
-+ milli-second.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> regdump </td>
-+ <td> Dumps the contents of core registers.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> spramdump </td>
-+ <td> Dumps the contents of core registers.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hcddump </td>
-+ <td> Dumps the current HCD state.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hcd_frrem </td>
-+ <td> Shows the average value of the Frame Remaining
-+ field in the Host Frame Number/Frame Remaining register when an SOF interrupt
-+ occurs. This can be used to determine the average interrupt latency. Also
-+ shows the average Frame Remaining value for start_transfer and the "a" and
-+ "b" sample points. The "a" and "b" sample points may be used during debugging
-+ bto determine how long it takes to execute a section of the HCD code.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> rd_reg_test </td>
-+ <td> Displays the time required to read the GNPTXFSIZ register many times
-+ (the output shows the number of times the register is read).
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> wr_reg_test </td>
-+ <td> Displays the time required to write the GNPTXFSIZ register many times
-+ (the output shows the number of times the register is written).
-+ <td> Read</td>
-+ </tr>
-+
-+ </table>
-+
-+ Example usage:
-+ To get the current mode:
-+ cat /sys/devices/lm0/mode
-+
-+ To power down the USB:
-+ echo 0 > /sys/devices/lm0/buspower
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/errno.h>
-+#include <linux/types.h>
-+#include <linux/stat.h> /* permission constants */
-+#include <linux/version.h>
-+
-+#include <asm/io.h>
-+
-+#include "linux/dwc_otg_plat.h"
-+#include "dwc_otg_attr.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_pcd.h"
-+#include "dwc_otg_hcd.h"
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+/*
-+ * MACROs for defining sysfs attribute
-+ */
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
-+ uint32_t val; \
-+ val = dwc_read_reg32 (_addr_); \
-+ val = (val & (_mask_)) >> _shift_; \
-+ return sprintf (buf, "%s = 0x%x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+ const char *buf, size_t count) \
-+{ \
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
-+ uint32_t set = simple_strtoul(buf, NULL, 16); \
-+ uint32_t clear = set; \
-+ clear = ((~clear) << _shift_) & _mask_; \
-+ set = (set << _shift_) & _mask_; \
-+ dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
-+ dwc_modify_reg32(_addr_, clear, set); \
-+ return count; \
-+}
-+
-+/*
-+ * MACROs for defining sysfs attribute for 32-bit registers
-+ */
-+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
-+ uint32_t val; \
-+ val = dwc_read_reg32 (_addr_); \
-+ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+ const char *buf, size_t count) \
-+{ \
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
-+ uint32_t val = simple_strtoul(buf, NULL, 16); \
-+ dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
-+ dwc_write_reg32(_addr_, val); \
-+ return count; \
-+}
-+
-+#else
-+
-+/*
-+ * MACROs for defining sysfs attribute
-+ */
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \
-+{ \
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
-+ uint32_t val; \
-+ val = dwc_read_reg32 (_addr_); \
-+ val = (val & (_mask_)) >> _shift_; \
-+ return sprintf (buf, "%s = 0x%x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \
-+{ \
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
-+ uint32_t set = simple_strtoul(buf, NULL, 16); \
-+ uint32_t clear = set; \
-+ clear = ((~clear) << _shift_) & _mask_; \
-+ set = (set << _shift_) & _mask_; \
-+ dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
-+ dwc_modify_reg32(_addr_, clear, set); \
-+ return count; \
-+}
-+
-+/*
-+ * MACROs for defining sysfs attribute for 32-bit registers
-+ */
-+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \
-+{ \
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
-+ uint32_t val; \
-+ val = dwc_read_reg32 (_addr_); \
-+ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \
-+{ \
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
-+ uint32_t val = simple_strtoul(buf, NULL, 16); \
-+ dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
-+ dwc_write_reg32(_addr_, val); \
-+ return count; \
-+}
-+
-+#endif
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
-+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
-+DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
-+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
-+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
-+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
-+
-+#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
-+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
-+DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
-+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
-+
-+#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
-+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
-+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
-+
-+
-+/** @name Functions for Show/Store of Attributes */
-+/**@{*/
-+
-+/**
-+ * Show the register offset of the Register Access.
-+ */
-+static ssize_t regoffset_show( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+ return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset);
-+}
-+
-+/**
-+ * Set the register offset for the next Register Access Read/Write
-+ */
-+static ssize_t regoffset_store( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ const char *buf,
-+ size_t count )
-+{
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ uint32_t offset = simple_strtoul(buf, NULL, 16);
-+ //dev_dbg(_dev, "Offset=0x%08x\n", offset);
-+ if (offset < 0x00040000 ) {
-+ otg_dev->reg_offset = offset;
-+ }
-+ else {
-+ dev_err( _dev, "invalid offset\n" );
-+ }
-+
-+ return count;
-+}
-+DEVICE_ATTR(regoffset, S_IRUGO|S_IWUSR, (void *)regoffset_show, regoffset_store);
-+
-+
-+/**
-+ * Show the value of the register at the offset in the reg_offset
-+ * attribute.
-+ */
-+static ssize_t regvalue_show( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ uint32_t val;
-+ volatile uint32_t *addr;
-+
-+ if (otg_dev->reg_offset != 0xFFFFFFFF &&
-+ 0 != otg_dev->base) {
-+ /* Calculate the address */
-+ addr = (uint32_t*)(otg_dev->reg_offset +
-+ (uint8_t*)otg_dev->base);
-+ //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
-+ val = dwc_read_reg32( addr );
-+ return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1,
-+ "Reg@0x%06x = 0x%08x\n",
-+ otg_dev->reg_offset, val);
-+ }
-+ else {
-+ dev_err(_dev, "Invalid offset (0x%0x)\n",
-+ otg_dev->reg_offset);
-+ return sprintf(buf, "invalid offset\n" );
-+ }
-+}
-+
-+/**
-+ * Store the value in the register at the offset in the reg_offset
-+ * attribute.
-+ *
-+ */
-+static ssize_t regvalue_store( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ const char *buf,
-+ size_t count )
-+{
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ volatile uint32_t * addr;
-+ uint32_t val = simple_strtoul(buf, NULL, 16);
-+ //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
-+ if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
-+ /* Calculate the address */
-+ addr = (uint32_t*)(otg_dev->reg_offset +
-+ (uint8_t*)otg_dev->base);
-+ //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
-+ dwc_write_reg32( addr, val );
-+ }
-+ else {
-+ dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
-+ otg_dev->reg_offset);
-+ }
-+ return count;
-+}
-+DEVICE_ATTR(regvalue, S_IRUGO|S_IWUSR, regvalue_show, regvalue_store);
-+
-+/*
-+ * Attributes
-+ */
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode");
-+
-+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
-+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected");
-+
-+DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID");
-+DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed");
-+
-+DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0");
-+
-+
-+/**
-+ * @todo Add code to initiate the HNP.
-+ */
-+/**
-+ * Show the HNP status bit
-+ */
-+static ssize_t hnp_show( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ gotgctl_data_t val;
-+ val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
-+ return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs);
-+}
-+
-+/**
-+ * Set the HNP Request bit
-+ */
-+static ssize_t hnp_store( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ const char *buf,
-+ size_t count )
-+{
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ uint32_t in = simple_strtoul(buf, NULL, 16);
-+ uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl);
-+ gotgctl_data_t mem;
-+ mem.d32 = dwc_read_reg32(addr);
-+ mem.b.hnpreq = in;
-+ dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
-+ dwc_write_reg32(addr, mem.d32);
-+ return count;
-+}
-+DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
-+
-+/**
-+ * @todo Add code to initiate the SRP.
-+ */
-+/**
-+ * Show the SRP status bit
-+ */
-+static ssize_t srp_show( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ char *buf)
-+{
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ gotgctl_data_t val;
-+ val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
-+ return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs);
-+#else
-+ return sprintf(buf, "Host Only Mode!\n");
-+#endif
-+}
-+
-+
-+
-+/**
-+ * Set the SRP Request bit
-+ */
-+static ssize_t srp_store( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ const char *buf,
-+ size_t count )
-+{
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ dwc_otg_pcd_initiate_srp(otg_dev->pcd);
-+#endif
-+ return count;
-+}
-+DEVICE_ATTR(srp, 0644, srp_show, srp_store);
-+
-+/**
-+ * @todo Need to do more for power on/off?
-+ */
-+/**
-+ * Show the Bus Power status
-+ */
-+static ssize_t buspower_show( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ hprt0_data_t val;
-+ val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
-+ return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr);
-+}
-+
-+
-+/**
-+ * Set the Bus Power status
-+ */
-+static ssize_t buspower_store( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ const char *buf,
-+ size_t count )
-+{
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ uint32_t on = simple_strtoul(buf, NULL, 16);
-+ uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
-+ hprt0_data_t mem;
-+
-+ mem.d32 = dwc_read_reg32(addr);
-+ mem.b.prtpwr = on;
-+
-+ //dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
-+ dwc_write_reg32(addr, mem.d32);
-+
-+ return count;
-+}
-+DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
-+
-+/**
-+ * @todo Need to do more for suspend?
-+ */
-+/**
-+ * Show the Bus Suspend status
-+ */
-+static ssize_t bussuspend_show( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ hprt0_data_t val;
-+ val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
-+ return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp);
-+}
-+
-+/**
-+ * Set the Bus Suspend status
-+ */
-+static ssize_t bussuspend_store( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ const char *buf,
-+ size_t count )
-+{
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ uint32_t in = simple_strtoul(buf, NULL, 16);
-+ uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
-+ hprt0_data_t mem;
-+ mem.d32 = dwc_read_reg32(addr);
-+ mem.b.prtsusp = in;
-+ dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
-+ dwc_write_reg32(addr, mem.d32);
-+ return count;
-+}
-+DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
-+
-+/**
-+ * Show the status of Remote Wakeup.
-+ */
-+static ssize_t remote_wakeup_show( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ char *buf)
-+{
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ dctl_data_t val;
-+ val.d32 =
-+ dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl);
-+ return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n",
-+ val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable);
-+#else
-+ return sprintf(buf, "Host Only Mode!\n");
-+#endif
-+}
-+/**
-+ * Initiate a remote wakeup of the host. The Device control register
-+ * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
-+ * flag is set.
-+ *
-+ */
-+static ssize_t remote_wakeup_store( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ const char *buf,
-+ size_t count )
-+{
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ uint32_t val = simple_strtoul(buf, NULL, 16);
-+ if (val&1) {
-+ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
-+ }
-+ else {
-+ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
-+ }
-+#endif
-+ return count;
-+}
-+DEVICE_ATTR(remote_wakeup, S_IRUGO|S_IWUSR, remote_wakeup_show,
-+ remote_wakeup_store);
-+
-+/**
-+ * Dump global registers and either host or device registers (depending on the
-+ * current mode of the core).
-+ */
-+static ssize_t regdump_show( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ dwc_otg_dump_global_registers( otg_dev->core_if);
-+ if (dwc_otg_is_host_mode(otg_dev->core_if)) {
-+ dwc_otg_dump_host_registers( otg_dev->core_if);
-+ } else {
-+ dwc_otg_dump_dev_registers( otg_dev->core_if);
-+
-+ }
-+ return sprintf( buf, "Register Dump\n" );
-+}
-+
-+DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0);
-+
-+/**
-+ * Dump global registers and either host or device registers (depending on the
-+ * current mode of the core).
-+ */
-+static ssize_t spramdump_show( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ dwc_otg_dump_spram( otg_dev->core_if);
-+
-+ return sprintf( buf, "SPRAM Dump\n" );
-+}
-+
-+DEVICE_ATTR(spramdump, S_IRUGO|S_IWUSR, spramdump_show, 0);
-+
-+/**
-+ * Dump the current hcd state.
-+ */
-+static ssize_t hcddump_show( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ char *buf)
-+{
-+#ifndef DWC_DEVICE_ONLY
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ dwc_otg_hcd_dump_state(otg_dev->hcd);
-+#endif
-+ return sprintf( buf, "HCD Dump\n" );
-+}
-+
-+DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0);
-+
-+/**
-+ * Dump the average frame remaining at SOF. This can be used to
-+ * determine average interrupt latency. Frame remaining is also shown for
-+ * start transfer and two additional sample points.
-+ */
-+static ssize_t hcd_frrem_show( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ char *buf)
-+{
-+#ifndef DWC_DEVICE_ONLY
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ dwc_otg_hcd_dump_frrem(otg_dev->hcd);
-+#endif
-+ return sprintf( buf, "HCD Dump Frame Remaining\n" );
-+}
-+
-+DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0);
-+
-+/**
-+ * Displays the time required to read the GNPTXFSIZ register many times (the
-+ * output shows the number of times the register is read).
-+ */
-+#define RW_REG_COUNT 10000000
-+#define MSEC_PER_JIFFIE 1000/HZ
-+static ssize_t rd_reg_test_show( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ int i;
-+ int time;
-+ int start_jiffies;
-+
-+ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
-+ HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
-+ start_jiffies = jiffies;
-+ for (i = 0; i < RW_REG_COUNT; i++) {
-+ dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
-+ }
-+ time = jiffies - start_jiffies;
-+ return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
-+ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time );
-+}
-+
-+DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0);
-+
-+/**
-+ * Displays the time required to write the GNPTXFSIZ register many times (the
-+ * output shows the number of times the register is written).
-+ */
-+static ssize_t wr_reg_test_show( struct device *_dev,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+ struct device_attribute *attr,
-+#endif
-+ char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-+
-+ uint32_t reg_val;
-+ int i;
-+ int time;
-+ int start_jiffies;
-+
-+ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
-+ HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
-+ reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
-+ start_jiffies = jiffies;
-+ for (i = 0; i < RW_REG_COUNT; i++) {
-+ dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val);
-+ }
-+ time = jiffies - start_jiffies;
-+ return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
-+ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
-+}
-+
-+DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0);
-+/**@}*/
-+
-+/**
-+ * Create the device files
-+ */
-+void dwc_otg_attr_create (struct device *dev)
-+{
-+ int error;
-+
-+ error = device_create_file(dev, &dev_attr_regoffset);
-+ error = device_create_file(dev, &dev_attr_regvalue);
-+ error = device_create_file(dev, &dev_attr_mode);
-+ error = device_create_file(dev, &dev_attr_hnpcapable);
-+ error = device_create_file(dev, &dev_attr_srpcapable);
-+ error = device_create_file(dev, &dev_attr_hnp);
-+ error = device_create_file(dev, &dev_attr_srp);
-+ error = device_create_file(dev, &dev_attr_buspower);
-+ error = device_create_file(dev, &dev_attr_bussuspend);
-+ error = device_create_file(dev, &dev_attr_busconnected);
-+ error = device_create_file(dev, &dev_attr_gotgctl);
-+ error = device_create_file(dev, &dev_attr_gusbcfg);
-+ error = device_create_file(dev, &dev_attr_grxfsiz);
-+ error = device_create_file(dev, &dev_attr_gnptxfsiz);
-+ error = device_create_file(dev, &dev_attr_gpvndctl);
-+ error = device_create_file(dev, &dev_attr_ggpio);
-+ error = device_create_file(dev, &dev_attr_guid);
-+ error = device_create_file(dev, &dev_attr_gsnpsid);
-+ error = device_create_file(dev, &dev_attr_devspeed);
-+ error = device_create_file(dev, &dev_attr_enumspeed);
-+ error = device_create_file(dev, &dev_attr_hptxfsiz);
-+ error = device_create_file(dev, &dev_attr_hprt0);
-+ error = device_create_file(dev, &dev_attr_remote_wakeup);
-+ error = device_create_file(dev, &dev_attr_regdump);
-+ error = device_create_file(dev, &dev_attr_spramdump);
-+ error = device_create_file(dev, &dev_attr_hcddump);
-+ error = device_create_file(dev, &dev_attr_hcd_frrem);
-+ error = device_create_file(dev, &dev_attr_rd_reg_test);
-+ error = device_create_file(dev, &dev_attr_wr_reg_test);
-+}
-+
-+/**
-+ * Remove the device files
-+ */
-+void dwc_otg_attr_remove (struct device *dev)
-+{
-+ device_remove_file(dev, &dev_attr_regoffset);
-+ device_remove_file(dev, &dev_attr_regvalue);
-+ device_remove_file(dev, &dev_attr_mode);
-+ device_remove_file(dev, &dev_attr_hnpcapable);
-+ device_remove_file(dev, &dev_attr_srpcapable);
-+ device_remove_file(dev, &dev_attr_hnp);
-+ device_remove_file(dev, &dev_attr_srp);
-+ device_remove_file(dev, &dev_attr_buspower);
-+ device_remove_file(dev, &dev_attr_bussuspend);
-+ device_remove_file(dev, &dev_attr_busconnected);
-+ device_remove_file(dev, &dev_attr_gotgctl);
-+ device_remove_file(dev, &dev_attr_gusbcfg);
-+ device_remove_file(dev, &dev_attr_grxfsiz);
-+ device_remove_file(dev, &dev_attr_gnptxfsiz);
-+ device_remove_file(dev, &dev_attr_gpvndctl);
-+ device_remove_file(dev, &dev_attr_ggpio);
-+ device_remove_file(dev, &dev_attr_guid);
-+ device_remove_file(dev, &dev_attr_gsnpsid);
-+ device_remove_file(dev, &dev_attr_devspeed);
-+ device_remove_file(dev, &dev_attr_enumspeed);
-+ device_remove_file(dev, &dev_attr_hptxfsiz);
-+ device_remove_file(dev, &dev_attr_hprt0);
-+ device_remove_file(dev, &dev_attr_remote_wakeup);
-+ device_remove_file(dev, &dev_attr_regdump);
-+ device_remove_file(dev, &dev_attr_spramdump);
-+ device_remove_file(dev, &dev_attr_hcddump);
-+ device_remove_file(dev, &dev_attr_hcd_frrem);
-+ device_remove_file(dev, &dev_attr_rd_reg_test);
-+ device_remove_file(dev, &dev_attr_wr_reg_test);
-+}
---- /dev/null
-+++ b/drivers/usb/dwc_otg/dwc_otg_attr.h
-@@ -0,0 +1,67 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
-+ * $Revision: 1.2 $
-+ * $Date: 2008-11-21 05:39:15 $
-+ * $Change: 477051 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#if !defined(__DWC_OTG_ATTR_H__)
-+#define __DWC_OTG_ATTR_H__
-+
-+/** @file
-+ * This file contains the interface to the Linux device attributes.
-+ */
-+extern struct device_attribute dev_attr_regoffset;
-+extern struct device_attribute dev_attr_regvalue;
-+
-+extern struct device_attribute dev_attr_mode;
-+extern struct device_attribute dev_attr_hnpcapable;
-+extern struct device_attribute dev_attr_srpcapable;
-+extern struct device_attribute dev_attr_hnp;
-+extern struct device_attribute dev_attr_srp;
-+extern struct device_attribute dev_attr_buspower;
-+extern struct device_attribute dev_attr_bussuspend;
-+extern struct device_attribute dev_attr_busconnected;
-+extern struct device_attribute dev_attr_gotgctl;
-+extern struct device_attribute dev_attr_gusbcfg;
-+extern struct device_attribute dev_attr_grxfsiz;
-+extern struct device_attribute dev_attr_gnptxfsiz;
-+extern struct device_attribute dev_attr_gpvndctl;
-+extern struct device_attribute dev_attr_ggpio;
-+extern struct device_attribute dev_attr_guid;
-+extern struct device_attribute dev_attr_gsnpsid;
-+extern struct device_attribute dev_attr_devspeed;
-+extern struct device_attribute dev_attr_enumspeed;
-+extern struct device_attribute dev_attr_hptxfsiz;
-+extern struct device_attribute dev_attr_hprt0;
-+
-+void dwc_otg_attr_create (struct device *dev);
-+void dwc_otg_attr_remove (struct device *dev);
-+
-+#endif
---- /dev/null
-+++ b/drivers/usb/dwc_otg/dwc_otg_cil.c
-@@ -0,0 +1,3692 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
-+ * $Revision: 1.7 $
-+ * $Date: 2008-12-22 11:43:05 $
-+ * $Change: 1117667 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ *
-+ * The Core Interface Layer provides basic services for accessing and
-+ * managing the DWC_otg hardware. These services are used by both the
-+ * Host Controller Driver and the Peripheral Controller Driver.
-+ *
-+ * The CIL manages the memory map for the core so that the HCD and PCD
-+ * don't have to do this separately. It also handles basic tasks like
-+ * reading/writing the registers and data FIFOs in the controller.
-+ * Some of the data access functions provide encapsulation of several
-+ * operations required to perform a task, such as writing multiple
-+ * registers to start a transfer. Finally, the CIL performs basic
-+ * services that are not specific to either the host or device modes
-+ * of operation. These services include management of the OTG Host
-+ * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
-+ * Diagnostic API is also provided to allow testing of the controller
-+ * hardware.
-+ *
-+ * The Core Interface Layer has the following requirements:
-+ * - Provides basic controller operations.
-+ * - Minimal use of OS services.
-+ * - The OS services used will be abstracted by using inline functions
-+ * or macros.
-+ *
-+ */
-+#include <asm/unaligned.h>
-+#include <linux/dma-mapping.h>
-+#ifdef DEBUG
-+#include <linux/jiffies.h>
-+#endif
-+
-+#include "linux/dwc_otg_plat.h"
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_cil.h"
-+
-+/* Included only to access hc->qh for non-dword buffer handling
-+ * TODO: account it
-+ */
-+#include "dwc_otg_hcd.h"
-+
-+/**
-+ * This function is called to initialize the DWC_otg CSR data
-+ * structures. The register addresses in the device and host
-+ * structures are initialized from the base address supplied by the
-+ * caller. The calling function must make the OS calls to get the
-+ * base address of the DWC_otg controller registers. The core_params
-+ * argument holds the parameters that specify how the core should be
-+ * configured.
-+ *
-+ * @param[in] reg_base_addr Base address of DWC_otg core registers
-+ * @param[in] core_params Pointer to the core configuration parameters
-+ *
-+ */
-+dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *reg_base_addr,
-+ dwc_otg_core_params_t *core_params)
-+{
-+ dwc_otg_core_if_t *core_if = 0;
-+ dwc_otg_dev_if_t *dev_if = 0;
-+ dwc_otg_host_if_t *host_if = 0;
-+ uint8_t *reg_base = (uint8_t *)reg_base_addr;
-+ int i = 0;
-+
-+ DWC_DEBUGPL(DBG_CILV, "%s(%p,%p)\n", __func__, reg_base_addr, core_params);
-+
-+ core_if = kmalloc(sizeof(dwc_otg_core_if_t), GFP_KERNEL);
-+
-+ if (core_if == 0) {
-+ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_core_if_t failed\n");
-+ return 0;
-+ }
-+
-+ memset(core_if, 0, sizeof(dwc_otg_core_if_t));
-+
-+ core_if->core_params = core_params;
-+ core_if->core_global_regs = (dwc_otg_core_global_regs_t *)reg_base;
-+
-+ /*
-+ * Allocate the Device Mode structures.
-+ */
-+ dev_if = kmalloc(sizeof(dwc_otg_dev_if_t), GFP_KERNEL);
-+
-+ if (dev_if == 0) {
-+ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
-+ kfree(core_if);
-+ return 0;
-+ }
-+
-+ dev_if->dev_global_regs =
-+ (dwc_otg_device_global_regs_t *)(reg_base + DWC_DEV_GLOBAL_REG_OFFSET);
-+
-+ for (i=0; i<MAX_EPS_CHANNELS; i++)
-+ {
-+ dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
-+ (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
-+ (i * DWC_EP_REG_OFFSET));
-+
-+ dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
-+ (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
-+ (i * DWC_EP_REG_OFFSET));
-+ DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
-+ i, &dev_if->in_ep_regs[i]->diepctl);
-+ DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
-+ i, &dev_if->out_ep_regs[i]->doepctl);
-+ }
-+
-+ dev_if->speed = 0; // unknown
-+
-+ core_if->dev_if = dev_if;
-+
-+ /*
-+ * Allocate the Host Mode structures.
-+ */
-+ host_if = kmalloc(sizeof(dwc_otg_host_if_t), GFP_KERNEL);
-+
-+ if (host_if == 0) {
-+ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_host_if_t failed\n");
-+ kfree(dev_if);
-+ kfree(core_if);
-+ return 0;
-+ }
-+
-+ host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
-+ (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
-+
-+ host_if->hprt0 = (uint32_t*)(reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
-+
-+ for (i=0; i<MAX_EPS_CHANNELS; i++)
-+ {
-+ host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
-+ (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
-+ (i * DWC_OTG_CHAN_REGS_OFFSET));
-+ DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
-+ i, &host_if->hc_regs[i]->hcchar);
-+ }
-+
-+ host_if->num_host_channels = MAX_EPS_CHANNELS;
-+ core_if->host_if = host_if;
-+
-+ for (i=0; i<MAX_EPS_CHANNELS; i++)
-+ {
-+ core_if->data_fifo[i] =
-+ (uint32_t *)(reg_base + DWC_OTG_DATA_FIFO_OFFSET +
-+ (i * DWC_OTG_DATA_FIFO_SIZE));
-+ DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n",
-+ i, (unsigned)core_if->data_fifo[i]);
-+ }
-+
-+ core_if->pcgcctl = (uint32_t*)(reg_base + DWC_OTG_PCGCCTL_OFFSET);
-+
-+ /*
-+ * Store the contents of the hardware configuration registers here for
-+ * easy access later.
-+ */
-+ core_if->hwcfg1.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg1);
-+ core_if->hwcfg2.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg2);
-+ core_if->hwcfg3.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg3);
-+ core_if->hwcfg4.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg4);
-+
-+ DWC_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",core_if->hwcfg1.d32);
-+ DWC_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",core_if->hwcfg2.d32);
-+ DWC_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",core_if->hwcfg3.d32);
-+ DWC_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",core_if->hwcfg4.d32);
-+
-+ core_if->hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
-+ core_if->dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
-+
-+ DWC_DEBUGPL(DBG_CILV,"hcfg=%08x\n",core_if->hcfg.d32);
-+ DWC_DEBUGPL(DBG_CILV,"dcfg=%08x\n",core_if->dcfg.d32);
-+
-+ DWC_DEBUGPL(DBG_CILV,"op_mode=%0x\n",core_if->hwcfg2.b.op_mode);
-+ DWC_DEBUGPL(DBG_CILV,"arch=%0x\n",core_if->hwcfg2.b.architecture);
-+ DWC_DEBUGPL(DBG_CILV,"num_dev_ep=%d\n",core_if->hwcfg2.b.num_dev_ep);
-+ DWC_DEBUGPL(DBG_CILV,"num_host_chan=%d\n",core_if->hwcfg2.b.num_host_chan);
-+ DWC_DEBUGPL(DBG_CILV,"nonperio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.nonperio_tx_q_depth);
-+ DWC_DEBUGPL(DBG_CILV,"host_perio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.host_perio_tx_q_depth);
-+ DWC_DEBUGPL(DBG_CILV,"dev_token_q_depth=0x%0x\n",core_if->hwcfg2.b.dev_token_q_depth);
-+
-+ DWC_DEBUGPL(DBG_CILV,"Total FIFO SZ=%d\n", core_if->hwcfg3.b.dfifo_depth);
-+ DWC_DEBUGPL(DBG_CILV,"xfer_size_cntr_width=%0x\n", core_if->hwcfg3.b.xfer_size_cntr_width);
-+
-+ /*
-+ * Set the SRP sucess bit for FS-I2c
-+ */
-+ core_if->srp_success = 0;
-+ core_if->srp_timer_started = 0;
-+
-+
-+ /*
-+ * Create new workqueue and init works
-+ */
-+ core_if->wq_otg = create_singlethread_workqueue("dwc_otg");
-+ if(core_if->wq_otg == 0) {
-+ DWC_DEBUGPL(DBG_CIL, "Creation of wq_otg failed\n");
-+ kfree(host_if);
-+ kfree(dev_if);
-+ kfree(core_if);
-+ return 0 * HZ;
-+ }
-+
-+
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
-+
-+ INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change, core_if);
-+ INIT_WORK(&core_if->w_wkp, w_wakeup_detected, core_if);
-+
-+#else
-+
-+ INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change);
-+ INIT_DELAYED_WORK(&core_if->w_wkp, w_wakeup_detected);
-+
-+#endif
-+ return core_if;
-+}
-+
-+/**
-+ * This function frees the structures allocated by dwc_otg_cil_init().
-+ *
-+ * @param[in] core_if The core interface pointer returned from
-+ * dwc_otg_cil_init().
-+ *
-+ */
-+void dwc_otg_cil_remove(dwc_otg_core_if_t *core_if)
-+{
-+ /* Disable all interrupts */
-+ dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 1, 0);
-+ dwc_write_reg32(&core_if->core_global_regs->gintmsk, 0);
-+
-+ if (core_if->wq_otg) {
-+ destroy_workqueue(core_if->wq_otg);
-+ }
-+ if (core_if->dev_if) {
-+ kfree(core_if->dev_if);
-+ }
-+ if (core_if->host_if) {
-+ kfree(core_if->host_if);
-+ }
-+ kfree(core_if);
-+}
-+
-+/**
-+ * This function enables the controller's Global Interrupt in the AHB Config
-+ * register.
-+ *
-+ * @param[in] core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t *core_if)
-+{
-+ gahbcfg_data_t ahbcfg = { .d32 = 0};
-+ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
-+ dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
-+}
-+
-+/**
-+ * This function disables the controller's Global Interrupt in the AHB Config
-+ * register.
-+ *
-+ * @param[in] core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t *core_if)
-+{
-+ gahbcfg_data_t ahbcfg = { .d32 = 0};
-+ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
-+ dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
-+}
-+
-+/**
-+ * This function initializes the commmon interrupts, used in both
-+ * device and host modes.
-+ *
-+ * @param[in] core_if Programming view of the DWC_otg controller
-+ *
-+ */
-+static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t *core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs =
-+ core_if->core_global_regs;
-+ gintmsk_data_t intr_mask = { .d32 = 0};
-+
-+ /* Clear any pending OTG Interrupts */
-+ dwc_write_reg32(&global_regs->gotgint, 0xFFFFFFFF);
-+
-+ /* Clear any pending interrupts */
-+ dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /*
-+ * Enable the interrupts in the GINTMSK.
-+ */
-+ intr_mask.b.modemismatch = 1;
-+ intr_mask.b.otgintr = 1;
-+
-+ if (!core_if->dma_enable) {
-+ intr_mask.b.rxstsqlvl = 1;
-+ }
-+
-+ intr_mask.b.conidstschng = 1;
-+ intr_mask.b.wkupintr = 1;
-+ intr_mask.b.disconnect = 1;
-+ intr_mask.b.usbsuspend = 1;
-+ intr_mask.b.sessreqintr = 1;
-+ dwc_write_reg32(&global_regs->gintmsk, intr_mask.d32);
-+}
-+
-+/**
-+ * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
-+ * type.
-+ */
-+static void init_fslspclksel(dwc_otg_core_if_t *core_if)
-+{
-+ uint32_t val;
-+ hcfg_data_t hcfg;
-+
-+ if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
-+ (core_if->hwcfg2.b.fs_phy_type == 1) &&
-+ (core_if->core_params->ulpi_fs_ls)) ||
-+ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
-+ /* Full speed PHY */
-+ val = DWC_HCFG_48_MHZ;
-+ }
-+ else {
-+ /* High speed PHY running at full speed or high speed */
-+ val = DWC_HCFG_30_60_MHZ;
-+ }
-+
-+ DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
-+ hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
-+ hcfg.b.fslspclksel = val;
-+ dwc_write_reg32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
-+}
-+
-+/**
-+ * Initializes the DevSpd field of the DCFG register depending on the PHY type
-+ * and the enumeration speed of the device.
-+ */
-+static void init_devspd(dwc_otg_core_if_t *core_if)
-+{
-+ uint32_t val;
-+ dcfg_data_t dcfg;
-+
-+ if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
-+ (core_if->hwcfg2.b.fs_phy_type == 1) &&
-+ (core_if->core_params->ulpi_fs_ls)) ||
-+ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
-+ /* Full speed PHY */
-+ val = 0x3;
-+ }
-+ else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
-+ /* High speed PHY running at full speed */
-+ val = 0x1;
-+ }
-+ else {
-+ /* High speed PHY running at high speed */
-+ val = 0x0;
-+ }
-+
-+ DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
-+
-+ dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
-+ dcfg.b.devspd = val;
-+ dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
-+}
-+
-+/**
-+ * This function calculates the number of IN EPS
-+ * using GHWCFG1 and GHWCFG2 registers values
-+ *
-+ * @param core_if Programming view of the DWC_otg controller
-+ */
-+static uint32_t calc_num_in_eps(dwc_otg_core_if_t *core_if)
-+{
-+ uint32_t num_in_eps = 0;
-+ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
-+ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
-+ uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
-+ int i;
-+
-+
-+ for(i = 0; i < num_eps; ++i)
-+ {
-+ if(!(hwcfg1 & 0x1))
-+ num_in_eps++;
-+
-+ hwcfg1 >>= 2;
-+ }
-+
-+ if(core_if->hwcfg4.b.ded_fifo_en) {
-+ num_in_eps = (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
-+ }
-+
-+ return num_in_eps;
-+}
-+
-+
-+/**
-+ * This function calculates the number of OUT EPS
-+ * using GHWCFG1 and GHWCFG2 registers values
-+ *
-+ * @param core_if Programming view of the DWC_otg controller
-+ */
-+static uint32_t calc_num_out_eps(dwc_otg_core_if_t *core_if)
-+{
-+ uint32_t num_out_eps = 0;
-+ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
-+ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
-+ int i;
-+
-+ for(i = 0; i < num_eps; ++i)
-+ {
-+ if(!(hwcfg1 & 0x2))
-+ num_out_eps++;
-+
-+ hwcfg1 >>= 2;
-+ }
-+ return num_out_eps;
-+}
-+/**
-+ * This function initializes the DWC_otg controller registers and
-+ * prepares the core for device mode or host mode operation.
-+ *
-+ * @param core_if Programming view of the DWC_otg controller
-+ *
-+ */
-+void dwc_otg_core_init(dwc_otg_core_if_t *core_if)
-+{
-+ int i = 0;
-+ dwc_otg_core_global_regs_t *global_regs =
-+ core_if->core_global_regs;
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ gahbcfg_data_t ahbcfg = { .d32 = 0 };
-+ gusbcfg_data_t usbcfg = { .d32 = 0 };
-+ gi2cctl_data_t i2cctl = { .d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
-+
-+ /* Common Initialization */
-+
-+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
-+
-+// usbcfg.b.tx_end_delay = 1;
-+ /* Program the ULPI External VBUS bit if needed */
-+ usbcfg.b.ulpi_ext_vbus_drv =
-+ (core_if->core_params->phy_ulpi_ext_vbus == DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
-+
-+ /* Set external TS Dline pulsing */
-+ usbcfg.b.term_sel_dl_pulse = (core_if->core_params->ts_dline == 1) ? 1 : 0;
-+ dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
-+
-+
-+ /* Reset the Controller */
-+ dwc_otg_core_reset(core_if);
-+
-+ /* Initialize parameters from Hardware configuration registers. */
-+ dev_if->num_in_eps = calc_num_in_eps(core_if);
-+ dev_if->num_out_eps = calc_num_out_eps(core_if);
-+
-+
-+ DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n", core_if->hwcfg4.b.num_dev_perio_in_ep);
-+
-+ for (i=0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
-+ {
-+ dev_if->perio_tx_fifo_size[i] =
-+ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
-+ DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
-+ i, dev_if->perio_tx_fifo_size[i]);
-+ }
-+
-+ for (i=0; i < core_if->hwcfg4.b.num_in_eps; i++)
-+ {
-+ dev_if->tx_fifo_size[i] =
-+ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
-+ DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
-+ i, dev_if->perio_tx_fifo_size[i]);
-+ }
-+
-+ core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
-+ core_if->rx_fifo_size =
-+ dwc_read_reg32(&global_regs->grxfsiz);
-+ core_if->nperio_tx_fifo_size =
-+ dwc_read_reg32(&global_regs->gnptxfsiz) >> 16;
-+
-+ DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", core_if->nperio_tx_fifo_size);
-+
-+ /* This programming sequence needs to happen in FS mode before any other
-+ * programming occurs */
-+ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
-+ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
-+ /* If FS mode with FS PHY */
-+
-+ /* core_init() is now called on every switch so only call the
-+ * following for the first time through. */
-+ if (!core_if->phy_init_done) {
-+ core_if->phy_init_done = 1;
-+ DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
-+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
-+ usbcfg.b.physel = 1;
-+ dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
-+
-+ /* Reset after a PHY select */
-+ dwc_otg_core_reset(core_if);
-+ }
-+
-+ /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
-+ * do this on HNP Dev/Host mode switches (done in dev_init and
-+ * host_init). */
-+ if (dwc_otg_is_host_mode(core_if)) {
-+ init_fslspclksel(core_if);
-+ }
-+ else {
-+ init_devspd(core_if);
-+ }
-+
-+ if (core_if->core_params->i2c_enable) {
-+ DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
-+ /* Program GUSBCFG.OtgUtmifsSel to I2C */
-+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
-+ usbcfg.b.otgutmifssel = 1;
-+ dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
-+
-+ /* Program GI2CCTL.I2CEn */
-+ i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl);
-+ i2cctl.b.i2cdevaddr = 1;
-+ i2cctl.b.i2cen = 0;
-+ dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32);
-+ i2cctl.b.i2cen = 1;
-+ dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32);
-+ }
-+
-+ } /* endif speed == DWC_SPEED_PARAM_FULL */
-+
-+ else {
-+ /* High speed PHY. */
-+ if (!core_if->phy_init_done) {
-+ core_if->phy_init_done = 1;
-+ /* HS PHY parameters. These parameters are preserved
-+ * during soft reset so only program the first time. Do
-+ * a soft reset immediately after setting phyif. */
-+ usbcfg.b.ulpi_utmi_sel = core_if->core_params->phy_type;
-+ if (usbcfg.b.ulpi_utmi_sel == 1) {
-+ /* ULPI interface */
-+ usbcfg.b.phyif = 0;
-+ usbcfg.b.ddrsel = core_if->core_params->phy_ulpi_ddr;
-+ }
-+ else {
-+ /* UTMI+ interface */
-+ if (core_if->core_params->phy_utmi_width == 16) {
-+ usbcfg.b.phyif = 1;
-+ }
-+ else {
-+ usbcfg.b.phyif = 0;
-+ }
-+ }
-+
-+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
-+
-+ /* Reset after setting the PHY parameters */
-+ dwc_otg_core_reset(core_if);
-+ }
-+ }
-+
-+ if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
-+ (core_if->hwcfg2.b.fs_phy_type == 1) &&
-+ (core_if->core_params->ulpi_fs_ls)) {
-+ DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
-+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
-+ usbcfg.b.ulpi_fsls = 1;
-+ usbcfg.b.ulpi_clk_sus_m = 1;
-+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
-+ }
-+ else {
-+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
-+ usbcfg.b.ulpi_fsls = 0;
-+ usbcfg.b.ulpi_clk_sus_m = 0;
-+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
-+ }
-+
-+ /* Program the GAHBCFG Register.*/
-+ switch (core_if->hwcfg2.b.architecture) {
-+
-+ case DWC_SLAVE_ONLY_ARCH:
-+ DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
-+ ahbcfg.b.nptxfemplvl_txfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
-+ ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
-+ core_if->dma_enable = 0;
-+ core_if->dma_desc_enable = 0;
-+ break;
-+
-+ case DWC_EXT_DMA_ARCH:
-+ DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
-+ ahbcfg.b.hburstlen = core_if->core_params->dma_burst_size;
-+ core_if->dma_enable = (core_if->core_params->dma_enable != 0);
-+ core_if->dma_desc_enable = (core_if->core_params->dma_desc_enable != 0);
-+ break;
-+
-+ case DWC_INT_DMA_ARCH:
-+ DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
-+ ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR;
-+ core_if->dma_enable = (core_if->core_params->dma_enable != 0);
-+ core_if->dma_desc_enable = (core_if->core_params->dma_desc_enable != 0);
-+ break;
-+
-+ }
-+ ahbcfg.b.dmaenable = core_if->dma_enable;
-+ dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32);
-+
-+ core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
-+
-+ core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
-+ core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
-+ DWC_PRINT("Periodic Transfer Interrupt Enhancement - %s\n", ((core_if->pti_enh_enable) ? "enabled": "disabled"));
-+ DWC_PRINT("Multiprocessor Interrupt Enhancement - %s\n", ((core_if->multiproc_int_enable) ? "enabled": "disabled"));
-+
-+ /*
-+ * Program the GUSBCFG register.
-+ */
-+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
-+
-+ switch (core_if->hwcfg2.b.op_mode) {
-+ case DWC_MODE_HNP_SRP_CAPABLE:
-+ usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
-+ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
-+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
-+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+ break;
-+
-+ case DWC_MODE_SRP_ONLY_CAPABLE:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
-+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+ break;
-+
-+ case DWC_MODE_NO_HNP_SRP_CAPABLE:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = 0;
-+ break;
-+
-+ case DWC_MODE_SRP_CAPABLE_DEVICE:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
-+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+ break;
-+
-+ case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = 0;
-+ break;
-+
-+ case DWC_MODE_SRP_CAPABLE_HOST:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
-+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+ break;
-+
-+ case DWC_MODE_NO_SRP_CAPABLE_HOST:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = 0;
-+ break;
-+ }
-+
-+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
-+
-+ /* Enable common interrupts */
-+ dwc_otg_enable_common_interrupts(core_if);
-+
-+ /* Do device or host intialization based on mode during PCD
-+ * and HCD initialization */
-+ if (dwc_otg_is_host_mode(core_if)) {
-+ DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
-+ core_if->op_state = A_HOST;
-+ }
-+ else {
-+ DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
-+ core_if->op_state = B_PERIPHERAL;
-+#ifdef DWC_DEVICE_ONLY
-+ dwc_otg_core_dev_init(core_if);
-+#endif
-+ }
-+}
-+
-+
-+/**
-+ * This function enables the Device mode interrupts.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ */
-+void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *core_if)
-+{
-+ gintmsk_data_t intr_mask = { .d32 = 0};
-+ dwc_otg_core_global_regs_t *global_regs =
-+ core_if->core_global_regs;
-+
-+ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
-+
-+ /* Disable all interrupts. */
-+ dwc_write_reg32(&global_regs->gintmsk, 0);
-+
-+ /* Clear any pending interrupts */
-+ dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* Enable the common interrupts */
-+ dwc_otg_enable_common_interrupts(core_if);
-+
-+ /* Enable interrupts */
-+ intr_mask.b.usbreset = 1;
-+ intr_mask.b.enumdone = 1;
-+
-+ if(!core_if->multiproc_int_enable) {
-+ intr_mask.b.inepintr = 1;
-+ intr_mask.b.outepintr = 1;
-+ }
-+
-+ intr_mask.b.erlysuspend = 1;
-+
-+ if(core_if->en_multiple_tx_fifo == 0) {
-+ intr_mask.b.epmismatch = 1;
-+ }
-+
-+
-+#ifdef DWC_EN_ISOC
-+ if(core_if->dma_enable) {
-+ if(core_if->dma_desc_enable == 0) {
-+ if(core_if->pti_enh_enable) {
-+ dctl_data_t dctl = { .d32 = 0 };
-+ dctl.b.ifrmnum = 1;
-+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ } else {
-+ intr_mask.b.incomplisoin = 1;
-+ intr_mask.b.incomplisoout = 1;
-+ }
-+ }
-+ } else {
-+ intr_mask.b.incomplisoin = 1;
-+ intr_mask.b.incomplisoout = 1;
-+ }
-+#endif // DWC_EN_ISOC
-+
-+/** @todo NGS: Should this be a module parameter? */
-+#ifdef USE_PERIODIC_EP
-+ intr_mask.b.isooutdrop = 1;
-+ intr_mask.b.eopframe = 1;
-+ intr_mask.b.incomplisoin = 1;
-+ intr_mask.b.incomplisoout = 1;
-+#endif
-+
-+ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
-+
-+ DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
-+ dwc_read_reg32(&global_regs->gintmsk));
-+}
-+
-+/**
-+ * This function initializes the DWC_otg controller registers for
-+ * device mode.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ */
-+void dwc_otg_core_dev_init(dwc_otg_core_if_t *core_if)
-+{
-+ int i;
-+ dwc_otg_core_global_regs_t *global_regs =
-+ core_if->core_global_regs;
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ dwc_otg_core_params_t *params = core_if->core_params;
-+ dcfg_data_t dcfg = { .d32 = 0};
-+ grstctl_t resetctl = { .d32 = 0 };
-+ uint32_t rx_fifo_size;
-+ fifosize_data_t nptxfifosize;
-+ fifosize_data_t txfifosize;
-+ dthrctl_data_t dthrctl;
-+ fifosize_data_t ptxfifosize;
-+
-+ /* Restart the Phy Clock */
-+ dwc_write_reg32(core_if->pcgcctl, 0);
-+
-+ /* Device configuration register */
-+ init_devspd(core_if);
-+ dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg);
-+ dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
-+ dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
-+
-+ dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+ /* Configure data FIFO sizes */
-+ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
-+ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", core_if->total_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", params->dev_rx_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", params->dev_nperio_tx_fifo_size);
-+
-+ /* Rx FIFO */
-+ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
-+ dwc_read_reg32(&global_regs->grxfsiz));
-+
-+ rx_fifo_size = params->dev_rx_fifo_size;
-+ dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size);
-+
-+ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
-+ dwc_read_reg32(&global_regs->grxfsiz));
-+
-+ /** Set Periodic Tx FIFO Mask all bits 0 */
-+ core_if->p_tx_msk = 0;
-+
-+ /** Set Tx FIFO Mask all bits 0 */
-+ core_if->tx_msk = 0;
-+
-+ if(core_if->en_multiple_tx_fifo == 0) {
-+ /* Non-periodic Tx FIFO */
-+ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
-+ dwc_read_reg32(&global_regs->gnptxfsiz));
-+
-+ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
-+ nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
-+
-+ dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
-+
-+ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
-+ dwc_read_reg32(&global_regs->gnptxfsiz));
-+
-+ /**@todo NGS: Fix Periodic FIFO Sizing! */
-+ /*
-+ * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
-+ * Indexes of the FIFO size module parameters in the
-+ * dev_perio_tx_fifo_size array and the FIFO size registers in
-+ * the dptxfsiz array run from 0 to 14.
-+ */
-+ /** @todo Finish debug of this */
-+ ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
-+ for (i=0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
-+ {
-+ ptxfifosize.b.depth = params->dev_perio_tx_fifo_size[i];
-+ DWC_DEBUGPL(DBG_CIL, "initial dptxfsiz_dieptxf[%d]=%08x\n", i,
-+ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
-+ dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i],
-+ ptxfifosize.d32);
-+ DWC_DEBUGPL(DBG_CIL, "new dptxfsiz_dieptxf[%d]=%08x\n", i,
-+ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
-+ ptxfifosize.b.startaddr += ptxfifosize.b.depth;
-+ }
-+ }
-+ else {
-+ /*
-+ * Tx FIFOs These FIFOs are numbered from 1 to 15.
-+ * Indexes of the FIFO size module parameters in the
-+ * dev_tx_fifo_size array and the FIFO size registers in
-+ * the dptxfsiz_dieptxf array run from 0 to 14.
-+ */
-+
-+
-+ /* Non-periodic Tx FIFO */
-+ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
-+ dwc_read_reg32(&global_regs->gnptxfsiz));
-+
-+ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
-+ nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
-+
-+ dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
-+
-+ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
-+ dwc_read_reg32(&global_regs->gnptxfsiz));
-+
-+ txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
-+ /*
-+ Modify by kaiker ,for RT3052 device mode config
-+
-+ In RT3052,Since the _core_if->hwcfg4.b.num_dev_perio_in_ep is
-+ configed to 0 so these TX_FIF0 not config.IN EP will can't
-+ more than 1 if not modify it.
-+
-+ */
-+#if 1
-+ for (i=1 ; i <= dev_if->num_in_eps; i++)
-+#else
-+ for (i=1; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
-+#endif
-+ {
-+
-+ txfifosize.b.depth = params->dev_tx_fifo_size[i];
-+
-+ DWC_DEBUGPL(DBG_CIL, "initial dptxfsiz_dieptxf[%d]=%08x\n", i,
-+ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
-+
-+ dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i-1],
-+ txfifosize.d32);
-+
-+ DWC_DEBUGPL(DBG_CIL, "new dptxfsiz_dieptxf[%d]=%08x\n", i,
-+ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i-1]));
-+
-+ txfifosize.b.startaddr += txfifosize.b.depth;
-+ }
-+ }
-+ }
-+ /* Flush the FIFOs */
-+ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
-+ dwc_otg_flush_rx_fifo(core_if);
-+
-+ /* Flush the Learning Queue. */
-+ resetctl.b.intknqflsh = 1;
-+ dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32);
-+
-+ /* Clear all pending Device Interrupts */
-+
-+ if(core_if->multiproc_int_enable) {
-+ }
-+
-+ /** @todo - if the condition needed to be checked
-+ * or in any case all pending interrutps should be cleared?
-+ */
-+ if(core_if->multiproc_int_enable) {
-+ for(i = 0; i < core_if->dev_if->num_in_eps; ++i) {
-+ dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[i], 0);
-+ }
-+
-+ for(i = 0; i < core_if->dev_if->num_out_eps; ++i) {
-+ dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[i], 0);
-+ }
-+
-+ dwc_write_reg32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
-+ dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, 0);
-+ } else {
-+ dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, 0);
-+ dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, 0);
-+ dwc_write_reg32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
-+ dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, 0);
-+ }
-+
-+ for (i=0; i <= dev_if->num_in_eps; i++)
-+ {
-+ depctl_data_t depctl;
-+ depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
-+ if (depctl.b.epena) {
-+ depctl.d32 = 0;
-+ depctl.b.epdis = 1;
-+ depctl.b.snak = 1;
-+ }
-+ else {
-+ depctl.d32 = 0;
-+ }
-+
-+ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
-+
-+
-+ dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
-+ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0);
-+ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
-+ }
-+
-+ for (i=0; i <= dev_if->num_out_eps; i++)
-+ {
-+ depctl_data_t depctl;
-+ depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
-+ if (depctl.b.epena) {
-+ depctl.d32 = 0;
-+ depctl.b.epdis = 1;
-+ depctl.b.snak = 1;
-+ }
-+ else {
-+ depctl.d32 = 0;
-+ }
-+
-+ dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
-+
-+ dwc_write_reg32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
-+ dwc_write_reg32(&dev_if->out_ep_regs[i]->doepdma, 0);
-+ dwc_write_reg32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
-+ }
-+
-+ if(core_if->en_multiple_tx_fifo && core_if->dma_enable) {
-+ dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
-+ dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
-+ dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
-+
-+ dev_if->rx_thr_length = params->rx_thr_length;
-+ dev_if->tx_thr_length = params->tx_thr_length;
-+
-+ dev_if->setup_desc_index = 0;
-+
-+ dthrctl.d32 = 0;
-+ dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
-+ dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
-+ dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
-+ dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
-+ dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
-+
-+ dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl, dthrctl.d32);
-+
-+ DWC_DEBUGPL(DBG_CIL, "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
-+ dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en, dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len, dthrctl.b.rx_thr_len);
-+
-+ }
-+
-+ dwc_otg_enable_device_interrupts(core_if);
-+
-+ {
-+ diepmsk_data_t msk = { .d32 = 0 };
-+ msk.b.txfifoundrn = 1;
-+ if(core_if->multiproc_int_enable) {
-+ dwc_modify_reg32(&dev_if->dev_global_regs->diepeachintmsk[0], msk.d32, msk.d32);
-+ } else {
-+ dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, msk.d32, msk.d32);
-+ }
-+ }
-+
-+
-+ if(core_if->multiproc_int_enable) {
-+ /* Set NAK on Babble */
-+ dctl_data_t dctl = { .d32 = 0};
-+ dctl.b.nakonbble = 1;
-+ dwc_modify_reg32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ }
-+}
-+
-+/**
-+ * This function enables the Host mode interrupts.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ */
-+void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ gintmsk_data_t intr_mask = { .d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
-+
-+ /* Disable all interrupts. */
-+ dwc_write_reg32(&global_regs->gintmsk, 0);
-+
-+ /* Clear any pending interrupts. */
-+ dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* Enable the common interrupts */
-+ dwc_otg_enable_common_interrupts(core_if);
-+
-+ /*
-+ * Enable host mode interrupts without disturbing common
-+ * interrupts.
-+ */
-+ intr_mask.b.sofintr = 1;
-+ intr_mask.b.portintr = 1;
-+ intr_mask.b.hcintr = 1;
-+
-+ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
-+}
-+
-+/**
-+ * This function disables the Host Mode interrupts.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ */
-+void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs =
-+ core_if->core_global_regs;
-+ gintmsk_data_t intr_mask = { .d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
-+
-+ /*
-+ * Disable host mode interrupts without disturbing common
-+ * interrupts.
-+ */
-+ intr_mask.b.sofintr = 1;
-+ intr_mask.b.portintr = 1;
-+ intr_mask.b.hcintr = 1;
-+ intr_mask.b.ptxfempty = 1;
-+ intr_mask.b.nptxfempty = 1;
-+
-+ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
-+}
-+
-+/**
-+ * This function initializes the DWC_otg controller registers for
-+ * host mode.
-+ *
-+ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
-+ * request queues. Host channels are reset to ensure that they are ready for
-+ * performing transfers.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ */
-+void dwc_otg_core_host_init(dwc_otg_core_if_t *core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ dwc_otg_host_if_t *host_if = core_if->host_if;
-+ dwc_otg_core_params_t *params = core_if->core_params;
-+ hprt0_data_t hprt0 = { .d32 = 0 };
-+ fifosize_data_t nptxfifosize;
-+ fifosize_data_t ptxfifosize;
-+ int i;
-+ hcchar_data_t hcchar;
-+ hcfg_data_t hcfg;
-+ dwc_otg_hc_regs_t *hc_regs;
-+ int num_channels;
-+ gotgctl_data_t gotgctl = { .d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_CILV,"%s(%p)\n", __func__, core_if);
-+
-+ /* Restart the Phy Clock */
-+ dwc_write_reg32(core_if->pcgcctl, 0);
-+
-+ /* Initialize Host Configuration Register */
-+ init_fslspclksel(core_if);
-+ if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL)
-+ {
-+ hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
-+ hcfg.b.fslssupp = 1;
-+ dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32);
-+ }
-+
-+ /* Configure data FIFO sizes */
-+ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
-+ DWC_DEBUGPL(DBG_CIL,"Total FIFO Size=%d\n", core_if->total_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL,"Rx FIFO Size=%d\n", params->host_rx_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL,"NP Tx FIFO Size=%d\n", params->host_nperio_tx_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL,"P Tx FIFO Size=%d\n", params->host_perio_tx_fifo_size);
-+
-+ /* Rx FIFO */
-+ DWC_DEBUGPL(DBG_CIL,"initial grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
-+ dwc_write_reg32(&global_regs->grxfsiz, params->host_rx_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL,"new grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
-+
-+ /* Non-periodic Tx FIFO */
-+ DWC_DEBUGPL(DBG_CIL,"initial gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz));
-+ nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
-+ nptxfifosize.b.startaddr = params->host_rx_fifo_size;
-+ dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
-+ DWC_DEBUGPL(DBG_CIL,"new gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz));
-+
-+ /* Periodic Tx FIFO */
-+ DWC_DEBUGPL(DBG_CIL,"initial hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz));
-+ ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
-+ ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
-+ dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32);
-+ DWC_DEBUGPL(DBG_CIL,"new hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz));
-+ }
-+
-+ /* Clear Host Set HNP Enable in the OTG Control Register */
-+ gotgctl.b.hstsethnpen = 1;
-+ dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0);
-+
-+ /* Make sure the FIFOs are flushed. */
-+ dwc_otg_flush_tx_fifo(core_if, 0x10 /* all Tx FIFOs */);
-+ dwc_otg_flush_rx_fifo(core_if);
-+
-+ /* Flush out any leftover queued requests. */
-+ num_channels = core_if->core_params->host_channels;
-+ for (i = 0; i < num_channels; i++)
-+ {
-+ hc_regs = core_if->host_if->hc_regs[i];
-+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
-+ hcchar.b.chen = 0;
-+ hcchar.b.chdis = 1;
-+ hcchar.b.epdir = 0;
-+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
-+ }
-+
-+ /* Halt all channels to put them into a known state. */
-+ for (i = 0; i < num_channels; i++)
-+ {
-+ int count = 0;
-+ hc_regs = core_if->host_if->hc_regs[i];
-+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 1;
-+ hcchar.b.epdir = 0;
-+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
-+ do {
-+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
-+ if (++count > 1000)
-+ {
-+ DWC_ERROR("%s: Unable to clear halt on channel %d\n",
-+ __func__, i);
-+ break;
-+ }
-+ }
-+ while (hcchar.b.chen);
-+ }
-+
-+ /* Turn on the vbus power. */
-+ DWC_PRINT("Init: Port Power? op_state=%d\n", core_if->op_state);
-+ if (core_if->op_state == A_HOST) {
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ DWC_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr);
-+ if (hprt0.b.prtpwr == 0) {
-+ hprt0.b.prtpwr = 1;
-+ dwc_write_reg32(host_if->hprt0, hprt0.d32);
-+ }
-+ }
-+
-+ dwc_otg_enable_host_interrupts(core_if);
-+}
-+
-+/**
-+ * Prepares a host channel for transferring packets to/from a specific
-+ * endpoint. The HCCHARn register is set up with the characteristics specified
-+ * in _hc. Host channel interrupts that may need to be serviced while this
-+ * transfer is in progress are enabled.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ * @param hc Information needed to initialize the host channel
-+ */
-+void dwc_otg_hc_init(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
-+{
-+ uint32_t intr_enable;
-+ hcintmsk_data_t hc_intr_mask;
-+ gintmsk_data_t gintmsk = { .d32 = 0 };
-+ hcchar_data_t hcchar;
-+ hcsplt_data_t hcsplt;
-+
-+ uint8_t hc_num = hc->hc_num;
-+ dwc_otg_host_if_t *host_if = core_if->host_if;
-+ dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
-+
-+ /* Clear old interrupt conditions for this host channel. */
-+ hc_intr_mask.d32 = 0xFFFFFFFF;
-+ hc_intr_mask.b.reserved = 0;
-+ dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32);
-+
-+ /* Enable channel interrupts required for this transfer. */
-+ hc_intr_mask.d32 = 0;
-+ hc_intr_mask.b.chhltd = 1;
-+ if (core_if->dma_enable) {
-+ hc_intr_mask.b.ahberr = 1;
-+ if (hc->error_state && !hc->do_split &&
-+ hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
-+ hc_intr_mask.b.ack = 1;
-+ if (hc->ep_is_in) {
-+ hc_intr_mask.b.datatglerr = 1;
-+ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
-+ hc_intr_mask.b.nak = 1;
-+ }
-+ }
-+ }
-+ }
-+ else {
-+ switch (hc->ep_type) {
-+ case DWC_OTG_EP_TYPE_CONTROL:
-+ case DWC_OTG_EP_TYPE_BULK:
-+ hc_intr_mask.b.xfercompl = 1;
-+ hc_intr_mask.b.stall = 1;
-+ hc_intr_mask.b.xacterr = 1;
-+ hc_intr_mask.b.datatglerr = 1;
-+ if (hc->ep_is_in) {
-+ hc_intr_mask.b.bblerr = 1;
-+ }
-+ else {
-+ hc_intr_mask.b.nak = 1;
-+ hc_intr_mask.b.nyet = 1;
-+ if (hc->do_ping) {
-+ hc_intr_mask.b.ack = 1;
-+ }
-+ }
-+
-+ if (hc->do_split) {
-+ hc_intr_mask.b.nak = 1;
-+ if (hc->complete_split) {
-+ hc_intr_mask.b.nyet = 1;
-+ }
-+ else {
-+ hc_intr_mask.b.ack = 1;
-+ }
-+ }
-+
-+ if (hc->error_state) {
-+ hc_intr_mask.b.ack = 1;
-+ }
-+ break;
-+ case DWC_OTG_EP_TYPE_INTR:
-+ hc_intr_mask.b.xfercompl = 1;
-+ hc_intr_mask.b.nak = 1;
-+ hc_intr_mask.b.stall = 1;
-+ hc_intr_mask.b.xacterr = 1;
-+ hc_intr_mask.b.datatglerr = 1;
-+ hc_intr_mask.b.frmovrun = 1;
-+
-+ if (hc->ep_is_in) {
-+ hc_intr_mask.b.bblerr = 1;
-+ }
-+ if (hc->error_state) {
-+ hc_intr_mask.b.ack = 1;
-+ }
-+ if (hc->do_split) {
-+ if (hc->complete_split) {
-+ hc_intr_mask.b.nyet = 1;
-+ }
-+ else {
-+ hc_intr_mask.b.ack = 1;
-+ }
-+ }
-+ break;
-+ case DWC_OTG_EP_TYPE_ISOC:
-+ hc_intr_mask.b.xfercompl = 1;
-+ hc_intr_mask.b.frmovrun = 1;
-+ hc_intr_mask.b.ack = 1;
-+
-+ if (hc->ep_is_in) {
-+ hc_intr_mask.b.xacterr = 1;
-+ hc_intr_mask.b.bblerr = 1;
-+ }
-+ break;
-+ }
-+ }
-+ dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32);
-+
-+// if(hc->ep_type == DWC_OTG_EP_TYPE_BULK && !hc->ep_is_in)
-+// hc->max_packet = 512;
-+ /* Enable the top level host channel interrupt. */
-+ intr_enable = (1 << hc_num);
-+ dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
-+
-+ /* Make sure host channel interrupts are enabled. */
-+ gintmsk.b.hcintr = 1;
-+ dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
-+
-+ /*
-+ * Program the HCCHARn register with the endpoint characteristics for
-+ * the current transfer.
-+ */
-+ hcchar.d32 = 0;
-+ hcchar.b.devaddr = hc->dev_addr;
-+ hcchar.b.epnum = hc->ep_num;
-+ hcchar.b.epdir = hc->ep_is_in;
-+ hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
-+ hcchar.b.eptype = hc->ep_type;
-+ hcchar.b.mps = hc->max_packet;
-+
-+ dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+ DWC_DEBUGPL(DBG_HCDV, " Dev Addr: %d\n", hcchar.b.devaddr);
-+ DWC_DEBUGPL(DBG_HCDV, " Ep Num: %d\n", hcchar.b.epnum);
-+ DWC_DEBUGPL(DBG_HCDV, " Is In: %d\n", hcchar.b.epdir);
-+ DWC_DEBUGPL(DBG_HCDV, " Is Low Speed: %d\n", hcchar.b.lspddev);
-+ DWC_DEBUGPL(DBG_HCDV, " Ep Type: %d\n", hcchar.b.eptype);
-+ DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps);
-+ DWC_DEBUGPL(DBG_HCDV, " Multi Cnt: %d\n", hcchar.b.multicnt);
-+
-+ /*
-+ * Program the HCSPLIT register for SPLITs
-+ */
-+ hcsplt.d32 = 0;
-+ if (hc->do_split) {
-+ DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", hc->hc_num,
-+ hc->complete_split ? "CSPLIT" : "SSPLIT");
-+ hcsplt.b.compsplt = hc->complete_split;
-+ hcsplt.b.xactpos = hc->xact_pos;
-+ hcsplt.b.hubaddr = hc->hub_addr;
-+ hcsplt.b.prtaddr = hc->port_addr;
-+ DWC_DEBUGPL(DBG_HCDV, " comp split %d\n", hc->complete_split);
-+ DWC_DEBUGPL(DBG_HCDV, " xact pos %d\n", hc->xact_pos);
-+ DWC_DEBUGPL(DBG_HCDV, " hub addr %d\n", hc->hub_addr);
-+ DWC_DEBUGPL(DBG_HCDV, " port addr %d\n", hc->port_addr);
-+ DWC_DEBUGPL(DBG_HCDV, " is_in %d\n", hc->ep_is_in);
-+ DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps);
-+ DWC_DEBUGPL(DBG_HCDV, " xferlen: %d\n", hc->xfer_len);
-+ }
-+ dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
-+
-+}
-+
-+/**
-+ * Attempts to halt a host channel. This function should only be called in
-+ * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
-+ * normal circumstances in DMA mode, the controller halts the channel when the
-+ * transfer is complete or a condition occurs that requires application
-+ * intervention.
-+ *
-+ * In slave mode, checks for a free request queue entry, then sets the Channel
-+ * Enable and Channel Disable bits of the Host Channel Characteristics
-+ * register of the specified channel to intiate the halt. If there is no free
-+ * request queue entry, sets only the Channel Disable bit of the HCCHARn
-+ * register to flush requests for this channel. In the latter case, sets a
-+ * flag to indicate that the host channel needs to be halted when a request
-+ * queue slot is open.
-+ *
-+ * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
-+ * HCCHARn register. The controller ensures there is space in the request
-+ * queue before submitting the halt request.
-+ *
-+ * Some time may elapse before the core flushes any posted requests for this
-+ * host channel and halts. The Channel Halted interrupt handler completes the
-+ * deactivation of the host channel.
-+ *
-+ * @param core_if Controller register interface.
-+ * @param hc Host channel to halt.
-+ * @param halt_status Reason for halting the channel.
-+ */
-+void dwc_otg_hc_halt(dwc_otg_core_if_t *core_if,
-+ dwc_hc_t *hc,
-+ dwc_otg_halt_status_e halt_status)
-+{
-+ gnptxsts_data_t nptxsts;
-+ hptxsts_data_t hptxsts;
-+ hcchar_data_t hcchar;
-+ dwc_otg_hc_regs_t *hc_regs;
-+ dwc_otg_core_global_regs_t *global_regs;
-+ dwc_otg_host_global_regs_t *host_global_regs;
-+
-+ hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+ global_regs = core_if->core_global_regs;
-+ host_global_regs = core_if->host_if->host_global_regs;
-+
-+ WARN_ON(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+
-+ if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
-+ halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
-+ /*
-+ * Disable all channel interrupts except Ch Halted. The QTD
-+ * and QH state associated with this transfer has been cleared
-+ * (in the case of URB_DEQUEUE), so the channel needs to be
-+ * shut down carefully to prevent crashes.
-+ */
-+ hcintmsk_data_t hcintmsk;
-+ hcintmsk.d32 = 0;
-+ hcintmsk.b.chhltd = 1;
-+ dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32);
-+
-+ /*
-+ * Make sure no other interrupts besides halt are currently
-+ * pending. Handling another interrupt could cause a crash due
-+ * to the QTD and QH state.
-+ */
-+ dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32);
-+
-+ /*
-+ * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
-+ * even if the channel was already halted for some other
-+ * reason.
-+ */
-+ hc->halt_status = halt_status;
-+
-+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
-+ if (hcchar.b.chen == 0) {
-+ /*
-+ * The channel is either already halted or it hasn't
-+ * started yet. In DMA mode, the transfer may halt if
-+ * it finishes normally or a condition occurs that
-+ * requires driver intervention. Don't want to halt
-+ * the channel again. In either Slave or DMA mode,
-+ * it's possible that the transfer has been assigned
-+ * to a channel, but not started yet when an URB is
-+ * dequeued. Don't want to halt a channel that hasn't
-+ * started yet.
-+ */
-+ return;
-+ }
-+ }
-+
-+ if (hc->halt_pending) {
-+ /*
-+ * A halt has already been issued for this channel. This might
-+ * happen when a transfer is aborted by a higher level in
-+ * the stack.
-+ */
-+#ifdef DEBUG
-+ DWC_PRINT("*** %s: Channel %d, _hc->halt_pending already set ***\n",
-+ __func__, hc->hc_num);
-+
-+/* dwc_otg_dump_global_registers(core_if); */
-+/* dwc_otg_dump_host_registers(core_if); */
-+#endif
-+ return;
-+ }
-+
-+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 1;
-+
-+ if (!core_if->dma_enable) {
-+ /* Check for space in the request queue to issue the halt. */
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
-+ nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts);
-+ if (nptxsts.b.nptxqspcavail == 0) {
-+ hcchar.b.chen = 0;
-+ }
-+ }
-+ else {
-+ hptxsts.d32 = dwc_read_reg32(&host_global_regs->hptxsts);
-+ if ((hptxsts.b.ptxqspcavail == 0) || (core_if->queuing_high_bandwidth)) {
-+ hcchar.b.chen = 0;
-+ }
-+ }
-+ }
-+
-+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
-+
-+ hc->halt_status = halt_status;
-+
-+ if (hcchar.b.chen) {
-+ hc->halt_pending = 1;
-+ hc->halt_on_queue = 0;
-+ }
-+ else {
-+ hc->halt_on_queue = 1;
-+ }
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+ DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32);
-+ DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending);
-+ DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue);
-+ DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status);
-+
-+ return;
-+}
-+
-+/**
-+ * Clears the transfer state for a host channel. This function is normally
-+ * called after a transfer is done and the host channel is being released.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param hc Identifies the host channel to clean up.
-+ */
-+void dwc_otg_hc_cleanup(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
-+{
-+ dwc_otg_hc_regs_t *hc_regs;
-+
-+ hc->xfer_started = 0;
-+
-+ /*
-+ * Clear channel interrupt enables and any unhandled channel interrupt
-+ * conditions.
-+ */
-+ hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+ dwc_write_reg32(&hc_regs->hcintmsk, 0);
-+ dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF);
-+
-+#ifdef DEBUG
-+ del_timer(&core_if->hc_xfer_timer[hc->hc_num]);
-+ {
-+ hcchar_data_t hcchar;
-+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
-+ if (hcchar.b.chdis) {
-+ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
-+ __func__, hc->hc_num, hcchar.d32);
-+ }
-+ }
-+#endif
-+}
-+
-+/**
-+ * Sets the channel property that indicates in which frame a periodic transfer
-+ * should occur. This is always set to the _next_ frame. This function has no
-+ * effect on non-periodic transfers.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param hc Identifies the host channel to set up and its properties.
-+ * @param hcchar Current value of the HCCHAR register for the specified host
-+ * channel.
-+ */
-+static inline void hc_set_even_odd_frame(dwc_otg_core_if_t *core_if,
-+ dwc_hc_t *hc,
-+ hcchar_data_t *hcchar)
-+{
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ hfnum_data_t hfnum;
-+ hfnum.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hfnum);
-+
-+ /* 1 if _next_ frame is odd, 0 if it's even */
-+ hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
-+#ifdef DEBUG
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split && !hc->complete_split) {
-+ switch (hfnum.b.frnum & 0x7) {
-+ case 7:
-+ core_if->hfnum_7_samples++;
-+ core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
-+ break;
-+ case 0:
-+ core_if->hfnum_0_samples++;
-+ core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
-+ break;
-+ default:
-+ core_if->hfnum_other_samples++;
-+ core_if->hfnum_other_frrem_accum += hfnum.b.frrem;
-+ break;
-+ }
-+ }
-+#endif
-+ }
-+}
-+
-+#ifdef DEBUG
-+static void hc_xfer_timeout(unsigned long ptr)
-+{
-+ hc_xfer_info_t *xfer_info = (hc_xfer_info_t *)ptr;
-+ int hc_num = xfer_info->hc->hc_num;
-+ DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
-+ DWC_WARN(" start_hcchar_val 0x%08x\n", xfer_info->core_if->start_hcchar_val[hc_num]);
-+}
-+#endif
-+
-+/*
-+ * This function does the setup for a data transfer for a host channel and
-+ * starts the transfer. May be called in either Slave mode or DMA mode. In
-+ * Slave mode, the caller must ensure that there is sufficient space in the
-+ * request queue and Tx Data FIFO.
-+ *
-+ * For an OUT transfer in Slave mode, it loads a data packet into the
-+ * appropriate FIFO. If necessary, additional data packets will be loaded in
-+ * the Host ISR.
-+ *
-+ * For an IN transfer in Slave mode, a data packet is requested. The data
-+ * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
-+ * additional data packets are requested in the Host ISR.
-+ *
-+ * For a PING transfer in Slave mode, the Do Ping bit is set in the egards,
-+ *
-+ * Steven
-+ *
-+ * register along with a packet count of 1 and the channel is enabled. This
-+ * causes a single PING transaction to occur. Other fields in HCTSIZ are
-+ * simply set to 0 since no data transfer occurs in this case.
-+ *
-+ * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
-+ * all the information required to perform the subsequent data transfer. In
-+ * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
-+ * controller performs the entire PING protocol, then starts the data
-+ * transfer.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param hc Information needed to initialize the host channel. The xfer_len
-+ * value may be reduced to accommodate the max widths of the XferSize and
-+ * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
-+ * to reflect the final xfer_len value.
-+ */
-+void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
-+{
-+ hcchar_data_t hcchar;
-+ hctsiz_data_t hctsiz;
-+ uint16_t num_packets;
-+ uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
-+ uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
-+ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+
-+ hctsiz.d32 = 0;
-+
-+ if (hc->do_ping) {
-+ if (!core_if->dma_enable) {
-+ dwc_otg_hc_do_ping(core_if, hc);
-+ hc->xfer_started = 1;
-+ return;
-+ }
-+ else {
-+ hctsiz.b.dopng = 1;
-+ }
-+ }
-+
-+ if (hc->do_split) {
-+ num_packets = 1;
-+
-+ if (hc->complete_split && !hc->ep_is_in) {
-+ /* For CSPLIT OUT Transfer, set the size to 0 so the
-+ * core doesn't expect any data written to the FIFO */
-+ hc->xfer_len = 0;
-+ }
-+ else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
-+ hc->xfer_len = hc->max_packet;
-+ }
-+ else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
-+ hc->xfer_len = 188;
-+ }
-+
-+ hctsiz.b.xfersize = hc->xfer_len;
-+ }
-+ else {
-+ /*
-+ * Ensure that the transfer length and packet count will fit
-+ * in the widths allocated for them in the HCTSIZn register.
-+ */
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ /*
-+ * Make sure the transfer size is no larger than one
-+ * (micro)frame's worth of data. (A check was done
-+ * when the periodic transfer was accepted to ensure
-+ * that a (micro)frame's worth of data can be
-+ * programmed into a channel.)
-+ */
-+ uint32_t max_periodic_len = hc->multi_count * hc->max_packet;
-+ if (hc->xfer_len > max_periodic_len) {
-+ hc->xfer_len = max_periodic_len;
-+ }
-+ else {
-+ }
-+
-+ }
-+ else if (hc->xfer_len > max_hc_xfer_size) {
-+ /* Make sure that xfer_len is a multiple of max packet size. */
-+ hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
-+ }
-+
-+ if (hc->xfer_len > 0) {
-+ num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
-+ if (num_packets > max_hc_pkt_count) {
-+ num_packets = max_hc_pkt_count;
-+ hc->xfer_len = num_packets * hc->max_packet;
-+ }
-+ }
-+ else {
-+ /* Need 1 packet for transfer length of 0. */
-+ num_packets = 1;
-+ }
-+
-+ if (hc->ep_is_in) {
-+ /* Always program an integral # of max packets for IN transfers. */
-+ hc->xfer_len = num_packets * hc->max_packet;
-+ }
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ /*
-+ * Make sure that the multi_count field matches the
-+ * actual transfer length.
-+ */
-+ hc->multi_count = num_packets;
-+ }
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ /* Set up the initial PID for the transfer. */
-+ if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
-+ if (hc->ep_is_in) {
-+ if (hc->multi_count == 1) {
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
-+ }
-+ else if (hc->multi_count == 2) {
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
-+ }
-+ else {
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
-+ }
-+ }
-+ else {
-+ if (hc->multi_count == 1) {
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
-+ }
-+ else {
-+ hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
-+ }
-+ }
-+ }
-+ else {
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
-+ }
-+ }
-+
-+ hctsiz.b.xfersize = hc->xfer_len;
-+ }
-+
-+ hc->start_pkt_count = num_packets;
-+ hctsiz.b.pktcnt = num_packets;
-+ hctsiz.b.pid = hc->data_pid_start;
-+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+ DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize);
-+ DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt);
-+ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
-+
-+ if (core_if->dma_enable) {
-+#if defined (CONFIG_DWC_OTG_HOST_ONLY)
-+ if ((uint32_t)hc->xfer_buff & 0x3) {
-+ /* non DWORD-aligned buffer case*/
-+ if(!hc->qh->dw_align_buf) {
-+ hc->qh->dw_align_buf =
-+ dma_alloc_coherent(NULL,
-+ core_if->core_params->max_transfer_size,
-+ &hc->qh->dw_align_buf_dma,
-+ GFP_ATOMIC | GFP_DMA);
-+ if (!hc->qh->dw_align_buf) {
-+
-+ DWC_ERROR("%s: Failed to allocate memory to handle "
-+ "non-dword aligned buffer case\n", __func__);
-+ return;
-+ }
-+
-+ }
-+ if (!hc->ep_is_in) {
-+ memcpy(hc->qh->dw_align_buf, phys_to_virt((uint32_t)hc->xfer_buff), hc->xfer_len);
-+ }
-+
-+ dwc_write_reg32(&hc_regs->hcdma, hc->qh->dw_align_buf_dma);
-+ }
-+ else
-+#endif
-+ dwc_write_reg32(&hc_regs->hcdma, (uint32_t)hc->xfer_buff);
-+ }
-+
-+ /* Start the split */
-+ if (hc->do_split) {
-+ hcsplt_data_t hcsplt;
-+ hcsplt.d32 = dwc_read_reg32 (&hc_regs->hcsplt);
-+ hcsplt.b.spltena = 1;
-+ dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32);
-+ }
-+
-+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
-+ hcchar.b.multicnt = hc->multi_count;
-+ hc_set_even_odd_frame(core_if, hc, &hcchar);
-+#ifdef DEBUG
-+ core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
-+ if (hcchar.b.chdis) {
-+ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
-+ __func__, hc->hc_num, hcchar.d32);
-+ }
-+#endif
-+
-+ /* Set host channel enable after all other setup is complete. */
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 0;
-+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
-+
-+ hc->xfer_started = 1;
-+ hc->requests++;
-+
-+ if (!core_if->dma_enable &&
-+ !hc->ep_is_in && hc->xfer_len > 0) {
-+ /* Load OUT packet into the appropriate Tx FIFO. */
-+ dwc_otg_hc_write_packet(core_if, hc);
-+ }
-+
-+#ifdef DEBUG
-+ /* Start a timer for this transfer. */
-+ core_if->hc_xfer_timer[hc->hc_num].function = hc_xfer_timeout;
-+ core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
-+ core_if->hc_xfer_info[hc->hc_num].hc = hc;
-+ core_if->hc_xfer_timer[hc->hc_num].data = (unsigned long)(&core_if->hc_xfer_info[hc->hc_num]);
-+ core_if->hc_xfer_timer[hc->hc_num].expires = jiffies + (HZ*10);
-+ add_timer(&core_if->hc_xfer_timer[hc->hc_num]);
-+#endif
-+}
-+
-+/**
-+ * This function continues a data transfer that was started by previous call
-+ * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
-+ * sufficient space in the request queue and Tx Data FIFO. This function
-+ * should only be called in Slave mode. In DMA mode, the controller acts
-+ * autonomously to complete transfers programmed to a host channel.
-+ *
-+ * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
-+ * if there is any data remaining to be queued. For an IN transfer, another
-+ * data packet is always requested. For the SETUP phase of a control transfer,
-+ * this function does nothing.
-+ *
-+ * @return 1 if a new request is queued, 0 if no more requests are required
-+ * for this transfer.
-+ */
-+int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
-+{
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+
-+ if (hc->do_split) {
-+ /* SPLITs always queue just once per channel */
-+ return 0;
-+ }
-+ else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
-+ /* SETUPs are queued only once since they can't be NAKed. */
-+ return 0;
-+ }
-+ else if (hc->ep_is_in) {
-+ /*
-+ * Always queue another request for other IN transfers. If
-+ * back-to-back INs are issued and NAKs are received for both,
-+ * the driver may still be processing the first NAK when the
-+ * second NAK is received. When the interrupt handler clears
-+ * the NAK interrupt for the first NAK, the second NAK will
-+ * not be seen. So we can't depend on the NAK interrupt
-+ * handler to requeue a NAKed request. Instead, IN requests
-+ * are issued each time this function is called. When the
-+ * transfer completes, the extra requests for the channel will
-+ * be flushed.
-+ */
-+ hcchar_data_t hcchar;
-+ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+
-+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
-+ hc_set_even_odd_frame(core_if, hc, &hcchar);
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 0;
-+ DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n", hcchar.d32);
-+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
-+ hc->requests++;
-+ return 1;
-+ }
-+ else {
-+ /* OUT transfers. */
-+ if (hc->xfer_count < hc->xfer_len) {
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ hcchar_data_t hcchar;
-+ dwc_otg_hc_regs_t *hc_regs;
-+ hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
-+ hc_set_even_odd_frame(core_if, hc, &hcchar);
-+ }
-+
-+ /* Load OUT packet into the appropriate Tx FIFO. */
-+ dwc_otg_hc_write_packet(core_if, hc);
-+ hc->requests++;
-+ return 1;
-+ }
-+ else {
-+ return 0;
-+ }
-+ }
-+}
-+
-+/**
-+ * Starts a PING transfer. This function should only be called in Slave mode.
-+ * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
-+ */
-+void dwc_otg_hc_do_ping(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
-+{
-+ hcchar_data_t hcchar;
-+ hctsiz_data_t hctsiz;
-+ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+
-+ hctsiz.d32 = 0;
-+ hctsiz.b.dopng = 1;
-+ hctsiz.b.pktcnt = 1;
-+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 0;
-+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
-+}
-+
-+/*
-+ * This function writes a packet into the Tx FIFO associated with the Host
-+ * Channel. For a channel associated with a non-periodic EP, the non-periodic
-+ * Tx FIFO is written. For a channel associated with a periodic EP, the
-+ * periodic Tx FIFO is written. This function should only be called in Slave
-+ * mode.
-+ *
-+ * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
-+ * then number of bytes written to the Tx FIFO.
-+ */
-+void dwc_otg_hc_write_packet(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
-+{
-+ uint32_t i;
-+ uint32_t remaining_count;
-+ uint32_t byte_count;
-+ uint32_t dword_count;
-+
-+ uint32_t *data_buff = (uint32_t *)(hc->xfer_buff);
-+ uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
-+
-+ remaining_count = hc->xfer_len - hc->xfer_count;
-+ if (remaining_count > hc->max_packet) {
-+ byte_count = hc->max_packet;
-+ }
-+ else {
-+ byte_count = remaining_count;
-+ }
-+
-+ dword_count = (byte_count + 3) / 4;
-+
-+ if ((((unsigned long)data_buff) & 0x3) == 0) {
-+ /* xfer_buff is DWORD aligned. */
-+ for (i = 0; i < dword_count; i++, data_buff++)
-+ {
-+ dwc_write_reg32(data_fifo, *data_buff);
-+ }
-+ }
-+ else {
-+ /* xfer_buff is not DWORD aligned. */
-+ for (i = 0; i < dword_count; i++, data_buff++)
-+ {
-+ dwc_write_reg32(data_fifo, get_unaligned(data_buff));
-+ }
-+ }
-+
-+ hc->xfer_count += byte_count;
-+ hc->xfer_buff += byte_count;
-+}
-+
-+/**
-+ * Gets the current USB frame number. This is the frame number from the last
-+ * SOF packet.
-+ */
-+uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *core_if)
-+{
-+ dsts_data_t dsts;
-+ dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
-+
-+ /* read current frame/microframe number from DSTS register */
-+ return dsts.b.soffn;
-+}
-+
-+/**
-+ * This function reads a setup packet from the Rx FIFO into the destination
-+ * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
-+ * Interrupt routine when a SETUP packet has been received in Slave mode.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dest Destination buffer for packet data.
-+ */
-+void dwc_otg_read_setup_packet(dwc_otg_core_if_t *core_if, uint32_t *dest)
-+{
-+ /* Get the 8 bytes of a setup transaction data */
-+
-+ /* Pop 2 DWORDS off the receive data FIFO into memory */
-+ dest[0] = dwc_read_reg32(core_if->data_fifo[0]);
-+ dest[1] = dwc_read_reg32(core_if->data_fifo[0]);
-+}
-+
-+
-+/**
-+ * This function enables EP0 OUT to receive SETUP packets and configures EP0
-+ * IN for transmitting packets. It is normally called when the
-+ * "Enumeration Done" interrupt occurs.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP0 data.
-+ */
-+void dwc_otg_ep0_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
-+{
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ dsts_data_t dsts;
-+ depctl_data_t diepctl;
-+ depctl_data_t doepctl;
-+ dctl_data_t dctl = { .d32 = 0 };
-+
-+ /* Read the Device Status and Endpoint 0 Control registers */
-+ dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts);
-+ diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl);
-+ doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl);
-+
-+ /* Set the MPS of the IN EP based on the enumeration speed */
-+ switch (dsts.b.enumspd) {
-+ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
-+ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
-+ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
-+ diepctl.b.mps = DWC_DEP0CTL_MPS_64;
-+ break;
-+ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
-+ diepctl.b.mps = DWC_DEP0CTL_MPS_8;
-+ break;
-+ }
-+
-+ dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
-+
-+ /* Enable OUT EP for receive */
-+ doepctl.b.epena = 1;
-+ dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
-+
-+#ifdef VERBOSE
-+ DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n",
-+ dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
-+ DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n",
-+ dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
-+#endif
-+ dctl.b.cgnpinnak = 1;
-+
-+ dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-+ DWC_DEBUGPL(DBG_PCDV,"dctl=%0x\n",
-+ dwc_read_reg32(&dev_if->dev_global_regs->dctl));
-+}
-+
-+/**
-+ * This function activates an EP. The Device EP control register for
-+ * the EP is configured as defined in the ep structure. Note: This
-+ * function is not used for EP0.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to activate.
-+ */
-+void dwc_otg_ep_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
-+{
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ depctl_data_t depctl;
-+ volatile uint32_t *addr;
-+ daint_data_t daintmsk = { .d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
-+ (ep->is_in?"IN":"OUT"));
-+
-+ /* Read DEPCTLn register */
-+ if (ep->is_in == 1) {
-+ addr = &dev_if->in_ep_regs[ep->num]->diepctl;
-+ daintmsk.ep.in = 1<<ep->num;
-+ }
-+ else {
-+ addr = &dev_if->out_ep_regs[ep->num]->doepctl;
-+ daintmsk.ep.out = 1<<ep->num;
-+ }
-+
-+ /* If the EP is already active don't change the EP Control
-+ * register. */
-+ depctl.d32 = dwc_read_reg32(addr);
-+ if (!depctl.b.usbactep) {
-+ depctl.b.mps = ep->maxpacket;
-+ depctl.b.eptype = ep->type;
-+ depctl.b.txfnum = ep->tx_fifo_num;
-+
-+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ depctl.b.setd0pid = 1; // ???
-+ }
-+ else {
-+ depctl.b.setd0pid = 1;
-+ }
-+ depctl.b.usbactep = 1;
-+
-+ dwc_write_reg32(addr, depctl.d32);
-+ DWC_DEBUGPL(DBG_PCDV,"DEPCTL=%08x\n", dwc_read_reg32(addr));
-+ }
-+
-+ /* Enable the Interrupt for this EP */
-+ if(core_if->multiproc_int_enable) {
-+ if (ep->is_in == 1) {
-+ diepmsk_data_t diepmsk = { .d32 = 0};
-+ diepmsk.b.xfercompl = 1;
-+ diepmsk.b.timeout = 1;
-+ diepmsk.b.epdisabled = 1;
-+ diepmsk.b.ahberr = 1;
-+ diepmsk.b.intknepmis = 1;
-+ diepmsk.b.txfifoundrn = 1; //?????
-+
-+
-+ if(core_if->dma_desc_enable) {
-+ diepmsk.b.bna = 1;
-+ }
-+/*
-+ if(core_if->dma_enable) {
-+ doepmsk.b.nak = 1;
-+ }
-+*/
-+ dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[ep->num], diepmsk.d32);
-+
-+ } else {
-+ doepmsk_data_t doepmsk = { .d32 = 0};
-+ doepmsk.b.xfercompl = 1;
-+ doepmsk.b.ahberr = 1;
-+ doepmsk.b.epdisabled = 1;
-+
-+
-+ if(core_if->dma_desc_enable) {
-+ doepmsk.b.bna = 1;
-+ }
-+/*
-+ doepmsk.b.babble = 1;
-+ doepmsk.b.nyet = 1;
-+ doepmsk.b.nak = 1;
-+*/
-+ dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[ep->num], doepmsk.d32);
-+ }
-+ dwc_modify_reg32(&dev_if->dev_global_regs->deachintmsk,
-+ 0, daintmsk.d32);
-+ } else {
-+ dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk,
-+ 0, daintmsk.d32);
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV,"DAINTMSK=%0x\n",
-+ dwc_read_reg32(&dev_if->dev_global_regs->daintmsk));
-+
-+ ep->stall_clear_flag = 0;
-+ return;
-+}
-+
-+/**
-+ * This function deactivates an EP. This is done by clearing the USB Active
-+ * EP bit in the Device EP control register. Note: This function is not used
-+ * for EP0. EP0 cannot be deactivated.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to deactivate.
-+ */
-+void dwc_otg_ep_deactivate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
-+{
-+ depctl_data_t depctl = { .d32 = 0 };
-+ volatile uint32_t *addr;
-+ daint_data_t daintmsk = { .d32 = 0};
-+
-+ /* Read DEPCTLn register */
-+ if (ep->is_in == 1) {
-+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
-+ daintmsk.ep.in = 1<<ep->num;
-+ }
-+ else {
-+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
-+ daintmsk.ep.out = 1<<ep->num;
-+ }
-+
-+ depctl.b.usbactep = 0;
-+
-+ if(core_if->dma_desc_enable)
-+ depctl.b.epdis = 1;
-+
-+ dwc_write_reg32(addr, depctl.d32);
-+
-+ /* Disable the Interrupt for this EP */
-+ if(core_if->multiproc_int_enable) {
-+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->deachintmsk,
-+ daintmsk.d32, 0);
-+
-+ if (ep->is_in == 1) {
-+ dwc_write_reg32(&core_if->dev_if->dev_global_regs->diepeachintmsk[ep->num], 0);
-+ } else {
-+ dwc_write_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[ep->num], 0);
-+ }
-+ } else {
-+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->daintmsk,
-+ daintmsk.d32, 0);
-+ }
-+}
-+
-+/**
-+ * This function does the setup for a data transfer for an EP and
-+ * starts the transfer. For an IN transfer, the packets will be
-+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
-+ * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ */
-+static void init_dma_desc_chain(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
-+{
-+ dwc_otg_dma_desc_t* dma_desc;
-+ uint32_t offset;
-+ uint32_t xfer_est;
-+ int i;
-+
-+ ep->desc_cnt = ( ep->total_len / ep->maxxfer) +
-+ ((ep->total_len % ep->maxxfer) ? 1 : 0);
-+ if(!ep->desc_cnt)
-+ ep->desc_cnt = 1;
-+
-+ dma_desc = ep->desc_addr;
-+ xfer_est = ep->total_len;
-+ offset = 0;
-+ for( i = 0; i < ep->desc_cnt; ++i) {
-+ /** DMA Descriptor Setup */
-+ if(xfer_est > ep->maxxfer) {
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ dma_desc->status.b.l = 0;
-+ dma_desc->status.b.ioc = 0;
-+ dma_desc->status.b.sp = 0;
-+ dma_desc->status.b.bytes = ep->maxxfer;
-+ dma_desc->buf = ep->dma_addr + offset;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ xfer_est -= ep->maxxfer;
-+ offset += ep->maxxfer;
-+ } else {
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ if(ep->is_in) {
-+ dma_desc->status.b.sp = (xfer_est % ep->maxpacket) ?
-+ 1 : ((ep->sent_zlp) ? 1 : 0);
-+ dma_desc->status.b.bytes = xfer_est;
-+ } else {
-+ dma_desc->status.b.bytes = xfer_est + ((4 - (xfer_est & 0x3)) & 0x3) ;
-+ }
-+
-+ dma_desc->buf = ep->dma_addr + offset;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+ }
-+ dma_desc ++;
-+ }
-+}
-+
-+/**
-+ * This function does the setup for a data transfer for an EP and
-+ * starts the transfer. For an IN transfer, the packets will be
-+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
-+ * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ */
-+
-+void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
-+{
-+ depctl_data_t depctl;
-+ deptsiz_data_t deptsiz;
-+ gintmsk_data_t intr_mask = { .d32 = 0};
-+
-+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
-+
-+ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
-+ "xfer_buff=%p start_xfer_buff=%p\n",
-+ ep->num, (ep->is_in?"IN":"OUT"), ep->xfer_len,
-+ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
-+
-+ /* IN endpoint */
-+ if (ep->is_in == 1) {
-+ dwc_otg_dev_in_ep_regs_t *in_regs =
-+ core_if->dev_if->in_ep_regs[ep->num];
-+
-+ gnptxsts_data_t gtxstatus;
-+
-+ gtxstatus.d32 =
-+ dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
-+
-+ if(core_if->en_multiple_tx_fifo == 0 && gtxstatus.b.nptxqspcavail == 0) {
-+#ifdef DEBUG
-+ DWC_PRINT("TX Queue Full (0x%0x)\n", gtxstatus.d32);
-+#endif
-+ return;
-+ }
-+
-+ depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
-+ deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
-+
-+ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
-+ ep->maxxfer : (ep->total_len - ep->xfer_len);
-+
-+ /* Zero Length Packet? */
-+ if ((ep->xfer_len - ep->xfer_count) == 0) {
-+ deptsiz.b.xfersize = 0;
-+ deptsiz.b.pktcnt = 1;
-+ }
-+ else {
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
-+ deptsiz.b.pktcnt =
-+ (ep->xfer_len - ep->xfer_count - 1 + ep->maxpacket) /
-+ ep->maxpacket;
-+ }
-+
-+
-+ /* Write the DMA register */
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable == 0) {
-+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
-+ dwc_write_reg32 (&(in_regs->diepdma),
-+ (uint32_t)ep->dma_addr);
-+ }
-+ else {
-+ init_dma_desc_chain(core_if, ep);
-+ /** DIEPDMAn Register write */
-+ dwc_write_reg32(&in_regs->diepdma, ep->dma_desc_addr);
-+ }
-+ }
-+ else {
-+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
-+ if(ep->type != DWC_OTG_EP_TYPE_ISOC) {
-+ /**
-+ * Enable the Non-Periodic Tx FIFO empty interrupt,
-+ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
-+ * the data will be written into the fifo by the ISR.
-+ */
-+ if(core_if->en_multiple_tx_fifo == 0) {
-+ intr_mask.b.nptxfempty = 1;
-+ dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
-+ intr_mask.d32, intr_mask.d32);
-+ }
-+ else {
-+ /* Enable the Tx FIFO Empty Interrupt for this EP */
-+ if(ep->xfer_len > 0) {
-+ uint32_t fifoemptymsk = 0;
-+ fifoemptymsk = 1 << ep->num;
-+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+ 0, fifoemptymsk);
-+
-+ }
-+ }
-+ }
-+ }
-+
-+ /* EP enable, IN data in FIFO */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ dwc_write_reg32(&in_regs->diepctl, depctl.d32);
-+
-+ depctl.d32 = dwc_read_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl);
-+ depctl.b.nextep = ep->num;
-+ dwc_write_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32);
-+
-+ }
-+ else {
-+ /* OUT endpoint */
-+ dwc_otg_dev_out_ep_regs_t *out_regs =
-+ core_if->dev_if->out_ep_regs[ep->num];
-+
-+ depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
-+ deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
-+
-+ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
-+ ep->maxxfer : (ep->total_len - ep->xfer_len);
-+
-+ /* Program the transfer size and packet count as follows:
-+ *
-+ * pktcnt = N
-+ * xfersize = N * maxpacket
-+ */
-+ if ((ep->xfer_len - ep->xfer_count) == 0) {
-+ /* Zero Length Packet */
-+ deptsiz.b.xfersize = ep->maxpacket;
-+ deptsiz.b.pktcnt = 1;
-+ }
-+ else {
-+ deptsiz.b.pktcnt =
-+ (ep->xfer_len - ep->xfer_count + (ep->maxpacket - 1)) /
-+ ep->maxpacket;
-+ ep->xfer_len = deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
-+ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
-+ ep->num,
-+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+
-+ if (core_if->dma_enable) {
-+ if (!core_if->dma_desc_enable) {
-+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
-+
-+ dwc_write_reg32 (&(out_regs->doepdma),
-+ (uint32_t)ep->dma_addr);
-+ }
-+ else {
-+ init_dma_desc_chain(core_if, ep);
-+
-+ /** DOEPDMAn Register write */
-+ dwc_write_reg32(&out_regs->doepdma, ep->dma_desc_addr);
-+ }
-+ }
-+ else {
-+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
-+ }
-+
-+ /* EP enable */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+
-+ dwc_write_reg32(&out_regs->doepctl, depctl.d32);
-+
-+ DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
-+ dwc_read_reg32(&out_regs->doepctl),
-+ dwc_read_reg32(&out_regs->doeptsiz));
-+ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
-+ dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk),
-+ dwc_read_reg32(&core_if->core_global_regs->gintmsk));
-+ }
-+}
-+
-+/**
-+ * This function setup a zero length transfer in Buffer DMA and
-+ * Slave modes for usb requests with zero field set
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
-+{
-+
-+ depctl_data_t depctl;
-+ deptsiz_data_t deptsiz;
-+ gintmsk_data_t intr_mask = { .d32 = 0};
-+
-+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
-+
-+ /* IN endpoint */
-+ if (ep->is_in == 1) {
-+ dwc_otg_dev_in_ep_regs_t *in_regs =
-+ core_if->dev_if->in_ep_regs[ep->num];
-+
-+ depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
-+ deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
-+
-+ deptsiz.b.xfersize = 0;
-+ deptsiz.b.pktcnt = 1;
-+
-+
-+ /* Write the DMA register */
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable == 0) {
-+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
-+ dwc_write_reg32 (&(in_regs->diepdma),
-+ (uint32_t)ep->dma_addr);
-+ }
-+ }
-+ else {
-+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
-+ /**
-+ * Enable the Non-Periodic Tx FIFO empty interrupt,
-+ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
-+ * the data will be written into the fifo by the ISR.
-+ */
-+ if(core_if->en_multiple_tx_fifo == 0) {
-+ intr_mask.b.nptxfempty = 1;
-+ dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
-+ intr_mask.d32, intr_mask.d32);
-+ }
-+ else {
-+ /* Enable the Tx FIFO Empty Interrupt for this EP */
-+ if(ep->xfer_len > 0) {
-+ uint32_t fifoemptymsk = 0;
-+ fifoemptymsk = 1 << ep->num;
-+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+ 0, fifoemptymsk);
-+ }
-+ }
-+ }
-+
-+ /* EP enable, IN data in FIFO */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ dwc_write_reg32(&in_regs->diepctl, depctl.d32);
-+
-+ depctl.d32 = dwc_read_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl);
-+ depctl.b.nextep = ep->num;
-+ dwc_write_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32);
-+
-+ }
-+ else {
-+ /* OUT endpoint */
-+ dwc_otg_dev_out_ep_regs_t *out_regs =
-+ core_if->dev_if->out_ep_regs[ep->num];
-+
-+ depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
-+ deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
-+
-+ /* Zero Length Packet */
-+ deptsiz.b.xfersize = ep->maxpacket;
-+ deptsiz.b.pktcnt = 1;
-+
-+ if (core_if->dma_enable) {
-+ if (!core_if->dma_desc_enable) {
-+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
-+
-+ dwc_write_reg32 (&(out_regs->doepdma),
-+ (uint32_t)ep->dma_addr);
-+ }
-+ }
-+ else {
-+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
-+ }
-+
-+ /* EP enable */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+
-+ dwc_write_reg32(&out_regs->doepctl, depctl.d32);
-+
-+ }
-+}
-+
-+/**
-+ * This function does the setup for a data transfer for EP0 and starts
-+ * the transfer. For an IN transfer, the packets will be loaded into
-+ * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
-+ * unloaded from the Rx FIFO in the ISR.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP0 data.
-+ */
-+void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
-+{
-+ depctl_data_t depctl;
-+ deptsiz0_data_t deptsiz;
-+ gintmsk_data_t intr_mask = { .d32 = 0};
-+ dwc_otg_dma_desc_t* dma_desc;
-+
-+ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
-+ "xfer_buff=%p start_xfer_buff=%p \n",
-+ ep->num, (ep->is_in?"IN":"OUT"), ep->xfer_len,
-+ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
-+
-+ ep->total_len = ep->xfer_len;
-+
-+ /* IN endpoint */
-+ if (ep->is_in == 1) {
-+ dwc_otg_dev_in_ep_regs_t *in_regs =
-+ core_if->dev_if->in_ep_regs[0];
-+
-+ gnptxsts_data_t gtxstatus;
-+
-+ gtxstatus.d32 =
-+ dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
-+
-+ if(core_if->en_multiple_tx_fifo == 0 && gtxstatus.b.nptxqspcavail == 0) {
-+#ifdef DEBUG
-+ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
-+ DWC_DEBUGPL(DBG_PCD,"DIEPCTL0=%0x\n",
-+ dwc_read_reg32(&in_regs->diepctl));
-+ DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
-+ deptsiz.d32,
-+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+ DWC_PRINT("TX Queue or FIFO Full (0x%0x)\n",
-+ gtxstatus.d32);
-+#endif
-+ return;
-+ }
-+
-+
-+ depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
-+ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
-+
-+ /* Zero Length Packet? */
-+ if (ep->xfer_len == 0) {
-+ deptsiz.b.xfersize = 0;
-+ deptsiz.b.pktcnt = 1;
-+ }
-+ else {
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+ if (ep->xfer_len > ep->maxpacket) {
-+ ep->xfer_len = ep->maxpacket;
-+ deptsiz.b.xfersize = ep->maxpacket;
-+ }
-+ else {
-+ deptsiz.b.xfersize = ep->xfer_len;
-+ }
-+ deptsiz.b.pktcnt = 1;
-+
-+ }
-+ DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
-+ ep->xfer_len,
-+ deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
-+
-+ /* Write the DMA register */
-+ if (core_if->dma_enable) {
-+ if(core_if->dma_desc_enable == 0) {
-+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
-+
-+ dwc_write_reg32 (&(in_regs->diepdma),
-+ (uint32_t)ep->dma_addr);
-+ }
-+ else {
-+ dma_desc = core_if->dev_if->in_desc_addr;
-+
-+ /** DMA Descriptor Setup */
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ dma_desc->status.b.sp = (ep->xfer_len == ep->maxpacket) ? 0 : 1;
-+ dma_desc->status.b.bytes = ep->xfer_len;
-+ dma_desc->buf = ep->dma_addr;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ /** DIEPDMA0 Register write */
-+ dwc_write_reg32(&in_regs->diepdma, core_if->dev_if->dma_in_desc_addr);
-+ }
-+ }
-+ else {
-+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
-+ }
-+
-+ /* EP enable, IN data in FIFO */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ dwc_write_reg32(&in_regs->diepctl, depctl.d32);
-+
-+ /**
-+ * Enable the Non-Periodic Tx FIFO empty interrupt, the
-+ * data will be written into the fifo by the ISR.
-+ */
-+ if (!core_if->dma_enable) {
-+ if(core_if->en_multiple_tx_fifo == 0) {
-+ intr_mask.b.nptxfempty = 1;
-+ dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
-+ intr_mask.d32, intr_mask.d32);
-+ }
-+ else {
-+ /* Enable the Tx FIFO Empty Interrupt for this EP */
-+ if(ep->xfer_len > 0) {
-+ uint32_t fifoemptymsk = 0;
-+ fifoemptymsk |= 1 << ep->num;
-+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+ 0, fifoemptymsk);
-+ }
-+ }
-+ }
-+ }
-+ else {
-+ /* OUT endpoint */
-+ dwc_otg_dev_out_ep_regs_t *out_regs =
-+ core_if->dev_if->out_ep_regs[0];
-+
-+ depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
-+ deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
-+
-+ /* Program the transfer size and packet count as follows:
-+ * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
-+ * pktcnt = N */
-+ /* Zero Length Packet */
-+ deptsiz.b.xfersize = ep->maxpacket;
-+ deptsiz.b.pktcnt = 1;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n",
-+ ep->xfer_len,
-+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+
-+ if (core_if->dma_enable) {
-+ if(!core_if->dma_desc_enable) {
-+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
-+
-+ dwc_write_reg32 (&(out_regs->doepdma),
-+ (uint32_t)ep->dma_addr);
-+ }
-+ else {
-+ dma_desc = core_if->dev_if->out_desc_addr;
-+
-+ /** DMA Descriptor Setup */
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ dma_desc->status.b.bytes = ep->maxpacket;
-+ dma_desc->buf = ep->dma_addr;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ /** DOEPDMA0 Register write */
-+ dwc_write_reg32(&out_regs->doepdma, core_if->dev_if->dma_out_desc_addr);
-+ }
-+ }
-+ else {
-+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
-+ }
-+
-+ /* EP enable */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ dwc_write_reg32 (&(out_regs->doepctl), depctl.d32);
-+ }
-+}
-+
-+/**
-+ * This function continues control IN transfers started by
-+ * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
-+ * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
-+ * bit for the packet count.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP0 data.
-+ */
-+void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
-+{
-+ depctl_data_t depctl;
-+ deptsiz0_data_t deptsiz;
-+ gintmsk_data_t intr_mask = { .d32 = 0};
-+ dwc_otg_dma_desc_t* dma_desc;
-+
-+ if (ep->is_in == 1) {
-+ dwc_otg_dev_in_ep_regs_t *in_regs =
-+ core_if->dev_if->in_ep_regs[0];
-+ gnptxsts_data_t tx_status = { .d32 = 0 };
-+
-+ tx_status.d32 = dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
-+ /** @todo Should there be check for room in the Tx
-+ * Status Queue. If not remove the code above this comment. */
-+
-+ depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
-+ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
-+
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+
-+
-+ if(core_if->dma_desc_enable == 0) {
-+ deptsiz.b.xfersize = (ep->total_len - ep->xfer_count) > ep->maxpacket ? ep->maxpacket :
-+ (ep->total_len - ep->xfer_count);
-+ deptsiz.b.pktcnt = 1;
-+ if(core_if->dma_enable == 0) {
-+ ep->xfer_len += deptsiz.b.xfersize;
-+ } else {
-+ ep->xfer_len = deptsiz.b.xfersize;
-+ }
-+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
-+ }
-+ else {
-+ ep->xfer_len = (ep->total_len - ep->xfer_count) > ep->maxpacket ? ep->maxpacket :
-+ (ep->total_len - ep->xfer_count);
-+
-+ dma_desc = core_if->dev_if->in_desc_addr;
-+
-+ /** DMA Descriptor Setup */
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ dma_desc->status.b.sp = (ep->xfer_len == ep->maxpacket) ? 0 : 1;
-+ dma_desc->status.b.bytes = ep->xfer_len;
-+ dma_desc->buf = ep->dma_addr;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ /** DIEPDMA0 Register write */
-+ dwc_write_reg32(&in_regs->diepdma, core_if->dev_if->dma_in_desc_addr);
-+ }
-+
-+
-+ DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
-+ ep->xfer_len,
-+ deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
-+
-+ /* Write the DMA register */
-+ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
-+ if(core_if->dma_desc_enable == 0)
-+ dwc_write_reg32 (&(in_regs->diepdma), (uint32_t)ep->dma_addr);
-+ }
-+
-+ /* EP enable, IN data in FIFO */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ dwc_write_reg32(&in_regs->diepctl, depctl.d32);
-+
-+ /**
-+ * Enable the Non-Periodic Tx FIFO empty interrupt, the
-+ * data will be written into the fifo by the ISR.
-+ */
-+ if (!core_if->dma_enable) {
-+ if(core_if->en_multiple_tx_fifo == 0) {
-+ /* First clear it from GINTSTS */
-+ intr_mask.b.nptxfempty = 1;
-+ dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
-+ intr_mask.d32, intr_mask.d32);
-+
-+ }
-+ else {
-+ /* Enable the Tx FIFO Empty Interrupt for this EP */
-+ if(ep->xfer_len > 0) {
-+ uint32_t fifoemptymsk = 0;
-+ fifoemptymsk |= 1 << ep->num;
-+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+ 0, fifoemptymsk);
-+ }
-+ }
-+ }
-+ }
-+ else {
-+ dwc_otg_dev_out_ep_regs_t *out_regs =
-+ core_if->dev_if->out_ep_regs[0];
-+
-+
-+ depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
-+ deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
-+
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+ deptsiz.b.xfersize = ep->maxpacket;
-+ deptsiz.b.pktcnt = 1;
-+
-+
-+ if(core_if->dma_desc_enable == 0) {
-+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
-+ }
-+ else {
-+ dma_desc = core_if->dev_if->out_desc_addr;
-+
-+ /** DMA Descriptor Setup */
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ dma_desc->status.b.bytes = ep->maxpacket;
-+ dma_desc->buf = ep->dma_addr;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ /** DOEPDMA0 Register write */
-+ dwc_write_reg32(&out_regs->doepdma, core_if->dev_if->dma_out_desc_addr);
-+ }
-+
-+
-+ DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
-+ ep->xfer_len,
-+ deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
-+
-+ /* Write the DMA register */
-+ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
-+ if(core_if->dma_desc_enable == 0)
-+ dwc_write_reg32 (&(out_regs->doepdma), (uint32_t)ep->dma_addr);
-+ }
-+
-+ /* EP enable, IN data in FIFO */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ dwc_write_reg32(&out_regs->doepctl, depctl.d32);
-+
-+ }
-+}
-+
-+#ifdef DEBUG
-+void dump_msg(const u8 *buf, unsigned int length)
-+{
-+ unsigned int start, num, i;
-+ char line[52], *p;
-+
-+ if (length >= 512)
-+ return;
-+ start = 0;
-+ while (length > 0) {
-+ num = min(length, 16u);
-+ p = line;
-+ for (i = 0; i < num; ++i)
-+ {
-+ if (i == 8)
-+ *p++ = ' ';
-+ sprintf(p, " %02x", buf[i]);
-+ p += 3;
-+ }
-+ *p = 0;
-+ DWC_PRINT("%6x: %s\n", start, line);
-+ buf += num;
-+ start += num;
-+ length -= num;
-+ }
-+}
-+#else
-+static inline void dump_msg(const u8 *buf, unsigned int length)
-+{
-+}
-+#endif
-+
-+/**
-+ * This function writes a packet into the Tx FIFO associated with the
-+ * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For
-+ * periodic EPs the periodic Tx FIFO associated with the EP is written
-+ * with all packets for the next micro-frame.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to write packet for.
-+ * @param dma Indicates if DMA is being used.
-+ */
-+void dwc_otg_ep_write_packet(dwc_otg_core_if_t *core_if, dwc_ep_t *ep, int dma)
-+{
-+ /**
-+ * The buffer is padded to DWORD on a per packet basis in
-+ * slave/dma mode if the MPS is not DWORD aligned. The last
-+ * packet, if short, is also padded to a multiple of DWORD.
-+ *
-+ * ep->xfer_buff always starts DWORD aligned in memory and is a
-+ * multiple of DWORD in length
-+ *
-+ * ep->xfer_len can be any number of bytes
-+ *
-+ * ep->xfer_count is a multiple of ep->maxpacket until the last
-+ * packet
-+ *
-+ * FIFO access is DWORD */
-+
-+ uint32_t i;
-+ uint32_t byte_count;
-+ uint32_t dword_count;
-+ uint32_t *fifo;
-+ uint32_t *data_buff = (uint32_t *)ep->xfer_buff;
-+
-+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if, ep);
-+ if (ep->xfer_count >= ep->xfer_len) {
-+ DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
-+ return;
-+ }
-+
-+ /* Find the byte length of the packet either short packet or MPS */
-+ if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
-+ byte_count = ep->xfer_len - ep->xfer_count;
-+ }
-+ else {
-+ byte_count = ep->maxpacket;
-+ }
-+
-+ /* Find the DWORD length, padded by extra bytes as neccessary if MPS
-+ * is not a multiple of DWORD */
-+ dword_count = (byte_count + 3) / 4;
-+
-+#ifdef VERBOSE
-+ dump_msg(ep->xfer_buff, byte_count);
-+#endif
-+
-+ /**@todo NGS Where are the Periodic Tx FIFO addresses
-+ * intialized? What should this be? */
-+
-+ fifo = core_if->data_fifo[ep->num];
-+
-+
-+ DWC_DEBUGPL((DBG_PCDV|DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n", fifo, data_buff, *data_buff, byte_count);
-+
-+ if (!dma) {
-+ for (i=0; i<dword_count; i++, data_buff++) {
-+ dwc_write_reg32(fifo, *data_buff);
-+ }
-+ }
-+
-+ ep->xfer_count += byte_count;
-+ ep->xfer_buff += byte_count;
-+ ep->dma_addr += byte_count;
-+}
-+
-+/**
-+ * Set the EP STALL.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to set the stall on.
-+ */
-+void dwc_otg_ep_set_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
-+{
-+ depctl_data_t depctl;
-+ volatile uint32_t *depctl_addr;
-+
-+ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
-+ (ep->is_in?"IN":"OUT"));
-+
-+ DWC_PRINT("%s ep%d-%s\n", __func__, ep->num,
-+ (ep->is_in?"in":"out"));
-+
-+ if (ep->is_in == 1) {
-+ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
-+ depctl.d32 = dwc_read_reg32(depctl_addr);
-+
-+ /* set the disable and stall bits */
-+ if (depctl.b.epena) {
-+ depctl.b.epdis = 1;
-+ }
-+ depctl.b.stall = 1;
-+ dwc_write_reg32(depctl_addr, depctl.d32);
-+ }
-+ else {
-+ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
-+ depctl.d32 = dwc_read_reg32(depctl_addr);
-+
-+ /* set the stall bit */
-+ depctl.b.stall = 1;
-+ dwc_write_reg32(depctl_addr, depctl.d32);
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr));
-+
-+ return;
-+}
-+
-+/**
-+ * Clear the EP STALL.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to clear stall from.
-+ */
-+void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
-+{
-+ depctl_data_t depctl;
-+ volatile uint32_t *depctl_addr;
-+
-+ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
-+ (ep->is_in?"IN":"OUT"));
-+
-+ if (ep->is_in == 1) {
-+ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
-+ }
-+ else {
-+ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
-+ }
-+
-+ depctl.d32 = dwc_read_reg32(depctl_addr);
-+
-+ /* clear the stall bits */
-+ depctl.b.stall = 0;
-+
-+ /*
-+ * USB Spec 9.4.5: For endpoints using data toggle, regardless
-+ * of whether an endpoint has the Halt feature set, a
-+ * ClearFeature(ENDPOINT_HALT) request always results in the
-+ * data toggle being reinitialized to DATA0.
-+ */
-+ if (ep->type == DWC_OTG_EP_TYPE_INTR ||
-+ ep->type == DWC_OTG_EP_TYPE_BULK) {
-+ depctl.b.setd0pid = 1; /* DATA0 */
-+ }
-+
-+ dwc_write_reg32(depctl_addr, depctl.d32);
-+ DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr));
-+ return;
-+}
-+
-+/**
-+ * This function reads a packet from the Rx FIFO into the destination
-+ * buffer. To read SETUP data use dwc_otg_read_setup_packet.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dest Destination buffer for the packet.
-+ * @param bytes Number of bytes to copy to the destination.
-+ */
-+void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
-+ uint8_t *dest,
-+ uint16_t bytes)
-+{
-+ int i;
-+ int word_count = (bytes + 3) / 4;
-+
-+ volatile uint32_t *fifo = core_if->data_fifo[0];
-+ uint32_t *data_buff = (uint32_t *)dest;
-+
-+ /**
-+ * @todo Account for the case where _dest is not dword aligned. This
-+ * requires reading data from the FIFO into a uint32_t temp buffer,
-+ * then moving it into the data buffer.
-+ */
-+
-+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
-+ core_if, dest, bytes);
-+
-+ for (i=0; i<word_count; i++, data_buff++)
-+ {
-+ *data_buff = dwc_read_reg32(fifo);
-+ }
-+
-+ return;
-+}
-+
-+
-+
-+/**
-+ * This functions reads the device registers and prints them
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *core_if)
-+{
-+ int i;
-+ volatile uint32_t *addr;
-+
-+ DWC_PRINT("Device Global Registers\n");
-+ addr=&core_if->dev_if->dev_global_regs->dcfg;
-+ DWC_PRINT("DCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->dev_global_regs->dctl;
-+ DWC_PRINT("DCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->dev_global_regs->dsts;
-+ DWC_PRINT("DSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->dev_global_regs->diepmsk;
-+ DWC_PRINT("DIEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->dev_global_regs->doepmsk;
-+ DWC_PRINT("DOEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->dev_global_regs->daint;
-+ DWC_PRINT("DAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->dev_global_regs->daintmsk;
-+ DWC_PRINT("DAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->dev_global_regs->dtknqr1;
-+ DWC_PRINT("DTKNQR1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
-+ addr=&core_if->dev_if->dev_global_regs->dtknqr2;
-+ DWC_PRINT("DTKNQR2 @0x%08X : 0x%08X\n",
-+ (uint32_t)addr,dwc_read_reg32(addr));
-+ }
-+
-+ addr=&core_if->dev_if->dev_global_regs->dvbusdis;
-+ DWC_PRINT("DVBUSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+
-+ addr=&core_if->dev_if->dev_global_regs->dvbuspulse;
-+ DWC_PRINT("DVBUSPULSE @0x%08X : 0x%08X\n",
-+ (uint32_t)addr,dwc_read_reg32(addr));
-+
-+ if (core_if->hwcfg2.b.dev_token_q_depth > 14) {
-+ addr=&core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
-+ DWC_PRINT("DTKNQR3_DTHRCTL @0x%08X : 0x%08X\n",
-+ (uint32_t)addr, dwc_read_reg32(addr));
-+ }
-+/*
-+ if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
-+ addr=&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
-+ DWC_PRINT("DTKNQR4 @0x%08X : 0x%08X\n",
-+ (uint32_t)addr, dwc_read_reg32(addr));
-+ }
-+*/
-+ addr=&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
-+ DWC_PRINT("FIFOEMPMSK @0x%08X : 0x%08X\n", (uint32_t)addr, dwc_read_reg32(addr));
-+
-+ addr=&core_if->dev_if->dev_global_regs->deachint;
-+ DWC_PRINT("DEACHINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->dev_global_regs->deachintmsk;
-+ DWC_PRINT("DEACHINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+
-+ for (i=0; i<= core_if->dev_if->num_in_eps; i++) {
-+ addr=&core_if->dev_if->dev_global_regs->diepeachintmsk[i];
-+ DWC_PRINT("DIEPEACHINTMSK[%d] @0x%08X : 0x%08X\n", i, (uint32_t)addr, dwc_read_reg32(addr));
-+ }
-+
-+
-+ for (i=0; i<= core_if->dev_if->num_out_eps; i++) {
-+ addr=&core_if->dev_if->dev_global_regs->doepeachintmsk[i];
-+ DWC_PRINT("DOEPEACHINTMSK[%d] @0x%08X : 0x%08X\n", i, (uint32_t)addr, dwc_read_reg32(addr));
-+ }
-+
-+ for (i=0; i<= core_if->dev_if->num_in_eps; i++) {
-+ DWC_PRINT("Device IN EP %d Registers\n", i);
-+ addr=&core_if->dev_if->in_ep_regs[i]->diepctl;
-+ DWC_PRINT("DIEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->in_ep_regs[i]->diepint;
-+ DWC_PRINT("DIEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->in_ep_regs[i]->dieptsiz;
-+ DWC_PRINT("DIETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->in_ep_regs[i]->diepdma;
-+ DWC_PRINT("DIEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->in_ep_regs[i]->dtxfsts;
-+ DWC_PRINT("DTXFSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->in_ep_regs[i]->diepdmab;
-+ DWC_PRINT("DIEPDMAB @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ }
-+
-+
-+ for (i=0; i<= core_if->dev_if->num_out_eps; i++) {
-+ DWC_PRINT("Device OUT EP %d Registers\n", i);
-+ addr=&core_if->dev_if->out_ep_regs[i]->doepctl;
-+ DWC_PRINT("DOEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->out_ep_regs[i]->doepfn;
-+ DWC_PRINT("DOEPFN @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->out_ep_regs[i]->doepint;
-+ DWC_PRINT("DOEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->out_ep_regs[i]->doeptsiz;
-+ DWC_PRINT("DOETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->out_ep_regs[i]->doepdma;
-+ DWC_PRINT("DOEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->dev_if->out_ep_regs[i]->doepdmab;
-+ DWC_PRINT("DOEPDMAB @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+
-+ }
-+
-+
-+
-+ return;
-+}
-+
-+/**
-+ * This functions reads the SPRAM and prints its content
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_dump_spram(dwc_otg_core_if_t *core_if)
-+{
-+ volatile uint8_t *addr, *start_addr, *end_addr;
-+
-+ DWC_PRINT("SPRAM Data:\n");
-+ start_addr = (void*)core_if->core_global_regs;
-+ DWC_PRINT("Base Address: 0x%8X\n", (uint32_t)start_addr);
-+ start_addr += 0x00028000;
-+ end_addr=(void*)core_if->core_global_regs;
-+ end_addr += 0x000280e0;
-+
-+ for(addr = start_addr; addr < end_addr; addr+=16)
-+ {
-+ DWC_PRINT("0x%8X:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n", (uint32_t)addr,
-+ addr[0],
-+ addr[1],
-+ addr[2],
-+ addr[3],
-+ addr[4],
-+ addr[5],
-+ addr[6],
-+ addr[7],
-+ addr[8],
-+ addr[9],
-+ addr[10],
-+ addr[11],
-+ addr[12],
-+ addr[13],
-+ addr[14],
-+ addr[15]
-+ );
-+ }
-+
-+ return;
-+}
-+/**
-+ * This function reads the host registers and prints them
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_dump_host_registers(dwc_otg_core_if_t *core_if)
-+{
-+ int i;
-+ volatile uint32_t *addr;
-+
-+ DWC_PRINT("Host Global Registers\n");
-+ addr=&core_if->host_if->host_global_regs->hcfg;
-+ DWC_PRINT("HCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->host_if->host_global_regs->hfir;
-+ DWC_PRINT("HFIR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->host_if->host_global_regs->hfnum;
-+ DWC_PRINT("HFNUM @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->host_if->host_global_regs->hptxsts;
-+ DWC_PRINT("HPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->host_if->host_global_regs->haint;
-+ DWC_PRINT("HAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->host_if->host_global_regs->haintmsk;
-+ DWC_PRINT("HAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=core_if->host_if->hprt0;
-+ DWC_PRINT("HPRT0 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+
-+ for (i=0; i<core_if->core_params->host_channels; i++)
-+ {
-+ DWC_PRINT("Host Channel %d Specific Registers\n", i);
-+ addr=&core_if->host_if->hc_regs[i]->hcchar;
-+ DWC_PRINT("HCCHAR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->host_if->hc_regs[i]->hcsplt;
-+ DWC_PRINT("HCSPLT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->host_if->hc_regs[i]->hcint;
-+ DWC_PRINT("HCINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->host_if->hc_regs[i]->hcintmsk;
-+ DWC_PRINT("HCINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->host_if->hc_regs[i]->hctsiz;
-+ DWC_PRINT("HCTSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->host_if->hc_regs[i]->hcdma;
-+ DWC_PRINT("HCDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ }
-+ return;
-+}
-+
-+/**
-+ * This function reads the core global registers and prints them
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_dump_global_registers(dwc_otg_core_if_t *core_if)
-+{
-+ int i;
-+ volatile uint32_t *addr;
-+
-+ DWC_PRINT("Core Global Registers\n");
-+ addr=&core_if->core_global_regs->gotgctl;
-+ DWC_PRINT("GOTGCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->gotgint;
-+ DWC_PRINT("GOTGINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->gahbcfg;
-+ DWC_PRINT("GAHBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->gusbcfg;
-+ DWC_PRINT("GUSBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->grstctl;
-+ DWC_PRINT("GRSTCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->gintsts;
-+ DWC_PRINT("GINTSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->gintmsk;
-+ DWC_PRINT("GINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->grxstsr;
-+ DWC_PRINT("GRXSTSR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ //addr=&core_if->core_global_regs->grxstsp;
-+ //DWC_PRINT("GRXSTSP @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->grxfsiz;
-+ DWC_PRINT("GRXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->gnptxfsiz;
-+ DWC_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->gnptxsts;
-+ DWC_PRINT("GNPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->gi2cctl;
-+ DWC_PRINT("GI2CCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->gpvndctl;
-+ DWC_PRINT("GPVNDCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->ggpio;
-+ DWC_PRINT("GGPIO @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->guid;
-+ DWC_PRINT("GUID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->gsnpsid;
-+ DWC_PRINT("GSNPSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->ghwcfg1;
-+ DWC_PRINT("GHWCFG1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->ghwcfg2;
-+ DWC_PRINT("GHWCFG2 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->ghwcfg3;
-+ DWC_PRINT("GHWCFG3 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->ghwcfg4;
-+ DWC_PRINT("GHWCFG4 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+ addr=&core_if->core_global_regs->hptxfsiz;
-+ DWC_PRINT("HPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
-+
-+ for (i=0; i<core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
-+ {
-+ addr=&core_if->core_global_regs->dptxfsiz_dieptxf[i];
-+ DWC_PRINT("DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,dwc_read_reg32(addr));
-+ }
-+}
-+
-+/**
-+ * Flush a Tx FIFO.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param num Tx FIFO to flush.
-+ */
-+void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t *core_if,
-+ const int num)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ volatile grstctl_t greset = { .d32 = 0};
-+ int count = 0;
-+
-+ DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", num);
-+
-+ greset.b.txfflsh = 1;
-+ greset.b.txfnum = num;
-+ dwc_write_reg32(&global_regs->grstctl, greset.d32);
-+
-+ do {
-+ greset.d32 = dwc_read_reg32(&global_regs->grstctl);
-+ if (++count > 10000) {
-+ DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
-+ __func__, greset.d32,
-+ dwc_read_reg32(&global_regs->gnptxsts));
-+ break;
-+ }
-+ }
-+ while (greset.b.txfflsh == 1);
-+
-+ /* Wait for 3 PHY Clocks*/
-+ UDELAY(1);
-+}
-+
-+/**
-+ * Flush Rx FIFO.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t *core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ volatile grstctl_t greset = { .d32 = 0};
-+ int count = 0;
-+
-+ DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__);
-+ /*
-+ *
-+ */
-+ greset.b.rxfflsh = 1;
-+ dwc_write_reg32(&global_regs->grstctl, greset.d32);
-+
-+ do {
-+ greset.d32 = dwc_read_reg32(&global_regs->grstctl);
-+ if (++count > 10000) {
-+ DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
-+ greset.d32);
-+ break;
-+ }
-+ }
-+ while (greset.b.rxfflsh == 1);
-+
-+ /* Wait for 3 PHY Clocks*/
-+ UDELAY(1);
-+}
-+
-+/**
-+ * Do core a soft reset of the core. Be careful with this because it
-+ * resets all the internal state machines of the core.
-+ */
-+void dwc_otg_core_reset(dwc_otg_core_if_t *core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ volatile grstctl_t greset = { .d32 = 0};
-+ int count = 0;
-+
-+ DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
-+ /* Wait for AHB master IDLE state. */
-+ do {
-+ UDELAY(10);
-+ greset.d32 = dwc_read_reg32(&global_regs->grstctl);
-+ if (++count > 100000) {
-+ DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
-+ greset.d32);
-+ return;
-+ }
-+ }
-+ while (greset.b.ahbidle == 0);
-+
-+ /* Core Soft Reset */
-+ count = 0;
-+ greset.b.csftrst = 1;
-+ dwc_write_reg32(&global_regs->grstctl, greset.d32);
-+ do {
-+ greset.d32 = dwc_read_reg32(&global_regs->grstctl);
-+ if (++count > 10000) {
-+ DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__,
-+ greset.d32);
-+ break;
-+ }
-+ }
-+ while (greset.b.csftrst == 1);
-+
-+ /* Wait for 3 PHY Clocks*/
-+ MDELAY(100);
-+}
-+
-+
-+
-+/**
-+ * Register HCD callbacks. The callbacks are used to start and stop
-+ * the HCD for interrupt processing.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param cb the HCD callback structure.
-+ * @param p pointer to be passed to callback function (usb_hcd*).
-+ */
-+void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t *core_if,
-+ dwc_otg_cil_callbacks_t *cb,
-+ void *p)
-+{
-+ core_if->hcd_cb = cb;
-+ cb->p = p;
-+}
-+
-+/**
-+ * Register PCD callbacks. The callbacks are used to start and stop
-+ * the PCD for interrupt processing.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param cb the PCD callback structure.
-+ * @param p pointer to be passed to callback function (pcd*).
-+ */
-+void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t *core_if,
-+ dwc_otg_cil_callbacks_t *cb,
-+ void *p)
-+{
-+ core_if->pcd_cb = cb;
-+ cb->p = p;
-+}
-+
-+#ifdef DWC_EN_ISOC
-+
-+/**
-+ * This function writes isoc data per 1 (micro)frame into tx fifo
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void write_isoc_frame_data(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
-+{
-+ dwc_otg_dev_in_ep_regs_t *ep_regs;
-+ dtxfsts_data_t txstatus = {.d32 = 0};
-+ uint32_t len = 0;
-+ uint32_t dwords;
-+
-+ ep->xfer_len = ep->data_per_frame;
-+ ep->xfer_count = 0;
-+
-+ ep_regs = core_if->dev_if->in_ep_regs[ep->num];
-+
-+ len = ep->xfer_len - ep->xfer_count;
-+
-+ if (len > ep->maxpacket) {
-+ len = ep->maxpacket;
-+ }
-+
-+ dwords = (len + 3)/4;
-+
-+ /* While there is space in the queue and space in the FIFO and
-+ * More data to tranfer, Write packets to the Tx FIFO */
-+ txstatus.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
-+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",ep->num,txstatus.d32);
-+
-+ while (txstatus.b.txfspcavail > dwords &&
-+ ep->xfer_count < ep->xfer_len &&
-+ ep->xfer_len != 0) {
-+ /* Write the FIFO */
-+ dwc_otg_ep_write_packet(core_if, ep, 0);
-+
-+ len = ep->xfer_len - ep->xfer_count;
-+ if (len > ep->maxpacket) {
-+ len = ep->maxpacket;
-+ }
-+
-+ dwords = (len + 3)/4;
-+ txstatus.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
-+ DWC_DEBUGPL(DBG_PCDV,"dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
-+ }
-+}
-+
-+
-+/**
-+ * This function initializes a descriptor chain for Isochronous transfer
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
-+{
-+ deptsiz_data_t deptsiz = { .d32 = 0 };
-+ depctl_data_t depctl = { .d32 = 0 };
-+ dsts_data_t dsts = { .d32 = 0 };
-+ volatile uint32_t *addr;
-+
-+ if(ep->is_in) {
-+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
-+ } else {
-+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
-+ }
-+
-+ ep->xfer_len = ep->data_per_frame;
-+ ep->xfer_count = 0;
-+ ep->xfer_buff = ep->cur_pkt_addr;
-+ ep->dma_addr = ep->cur_pkt_dma_addr;
-+
-+ if(ep->is_in) {
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+ deptsiz.b.xfersize = ep->xfer_len;
-+ deptsiz.b.pktcnt =
-+ (ep->xfer_len - 1 + ep->maxpacket) /
-+ ep->maxpacket;
-+ deptsiz.b.mc = deptsiz.b.pktcnt;
-+ dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, deptsiz.d32);
-+
-+ /* Write the DMA register */
-+ if (core_if->dma_enable) {
-+ dwc_write_reg32 (&(core_if->dev_if->in_ep_regs[ep->num]->diepdma), (uint32_t)ep->dma_addr);
-+ }
-+ } else {
-+ deptsiz.b.pktcnt =
-+ (ep->xfer_len + (ep->maxpacket - 1)) /
-+ ep->maxpacket;
-+ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
-+
-+ dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
-+
-+ if (core_if->dma_enable) {
-+ dwc_write_reg32 (&(core_if->dev_if->out_ep_regs[ep->num]->doepdma),
-+ (uint32_t)ep->dma_addr);
-+ }
-+ }
-+
-+
-+ /** Enable endpoint, clear nak */
-+
-+ depctl.d32 = 0;
-+ if(ep->bInterval == 1) {
-+ dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
-+ ep->next_frame = dsts.b.soffn + ep->bInterval;
-+
-+ if(ep->next_frame & 0x1) {
-+ depctl.b.setd1pid = 1;
-+ } else {
-+ depctl.b.setd0pid = 1;
-+ }
-+ } else {
-+ ep->next_frame += ep->bInterval;
-+
-+ if(ep->next_frame & 0x1) {
-+ depctl.b.setd1pid = 1;
-+ } else {
-+ depctl.b.setd0pid = 1;
-+ }
-+ }
-+ depctl.b.epena = 1;
-+ depctl.b.cnak = 1;
-+
-+ dwc_modify_reg32(addr, 0, depctl.d32);
-+ depctl.d32 = dwc_read_reg32(addr);
-+
-+ if(ep->is_in && core_if->dma_enable == 0) {
-+ write_isoc_frame_data(core_if, ep);
-+ }
-+
-+}
-+
-+#endif //DWC_EN_ISOC
---- /dev/null
-+++ b/drivers/usb/dwc_otg/dwc_otg_cil.h
-@@ -0,0 +1,1098 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
-+ * $Revision: 1.2 $
-+ * $Date: 2008-11-21 05:39:15 $
-+ * $Change: 1099526 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#if !defined(__DWC_CIL_H__)
-+#define __DWC_CIL_H__
-+
-+#include <linux/workqueue.h>
-+#include <linux/version.h>
-+#include <asm/param.h>
-+
-+#include "linux/dwc_otg_plat.h"
-+#include "dwc_otg_regs.h"
-+#ifdef DEBUG
-+#include "linux/timer.h"
-+#endif
-+
-+/**
-+ * @file
-+ * This file contains the interface to the Core Interface Layer.
-+ */
-+
-+
-+/** Macros defined for DWC OTG HW Release verison */
-+#define OTG_CORE_REV_2_00 0x4F542000
-+#define OTG_CORE_REV_2_60a 0x4F54260A
-+#define OTG_CORE_REV_2_71a 0x4F54271A
-+#define OTG_CORE_REV_2_72a 0x4F54272A
-+
-+/**
-+*/
-+typedef struct iso_pkt_info
-+{
-+ uint32_t offset;
-+ uint32_t length;
-+ int32_t status;
-+} iso_pkt_info_t;
-+/**
-+ * The <code>dwc_ep</code> structure represents the state of a single
-+ * endpoint when acting in device mode. It contains the data items
-+ * needed for an endpoint to be activated and transfer packets.
-+ */
-+typedef struct dwc_ep
-+{
-+ /** EP number used for register address lookup */
-+ uint8_t num;
-+ /** EP direction 0 = OUT */
-+ unsigned is_in : 1;
-+ /** EP active. */
-+ unsigned active : 1;
-+
-+ /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO
-+ If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/
-+ unsigned tx_fifo_num : 4;
-+ /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
-+ unsigned type : 2;
-+#define DWC_OTG_EP_TYPE_CONTROL 0
-+#define DWC_OTG_EP_TYPE_ISOC 1
-+#define DWC_OTG_EP_TYPE_BULK 2
-+#define DWC_OTG_EP_TYPE_INTR 3
-+
-+ /** DATA start PID for INTR and BULK EP */
-+ unsigned data_pid_start : 1;
-+ /** Frame (even/odd) for ISOC EP */
-+ unsigned even_odd_frame : 1;
-+ /** Max Packet bytes */
-+ unsigned maxpacket : 11;
-+
-+ /** Max Transfer size */
-+ unsigned maxxfer : 16;
-+
-+ /** @name Transfer state */
-+ /** @{ */
-+
-+ /**
-+ * Pointer to the beginning of the transfer buffer -- do not modify
-+ * during transfer.
-+ */
-+
-+ uint32_t dma_addr;
-+
-+ uint32_t dma_desc_addr;
-+ dwc_otg_dma_desc_t* desc_addr;
-+
-+
-+ uint8_t *start_xfer_buff;
-+ /** pointer to the transfer buffer */
-+ uint8_t *xfer_buff;
-+ /** Number of bytes to transfer */
-+ unsigned xfer_len : 19;
-+ /** Number of bytes transferred. */
-+ unsigned xfer_count : 19;
-+ /** Sent ZLP */
-+ unsigned sent_zlp : 1;
-+ /** Total len for control transfer */
-+ unsigned total_len : 19;
-+
-+ /** stall clear flag */
-+ unsigned stall_clear_flag : 1;
-+
-+ /** Allocated DMA Desc count */
-+ uint32_t desc_cnt;
-+
-+#ifdef DWC_EN_ISOC
-+ /**
-+ * Variables specific for ISOC EPs
-+ *
-+ */
-+ /** DMA addresses of ISOC buffers */
-+ uint32_t dma_addr0;
-+ uint32_t dma_addr1;
-+
-+ uint32_t iso_dma_desc_addr;
-+ dwc_otg_dma_desc_t* iso_desc_addr;
-+
-+ /** pointer to the transfer buffers */
-+ uint8_t *xfer_buff0;
-+ uint8_t *xfer_buff1;
-+
-+ /** number of ISOC Buffer is processing */
-+ uint32_t proc_buf_num;
-+ /** Interval of ISOC Buffer processing */
-+ uint32_t buf_proc_intrvl;
-+ /** Data size for regular frame */
-+ uint32_t data_per_frame;
-+
-+ /* todo - pattern data support is to be implemented in the future */
-+ /** Data size for pattern frame */
-+ uint32_t data_pattern_frame;
-+ /** Frame number of pattern data */
-+ uint32_t sync_frame;
-+
-+ /** bInterval */
-+ uint32_t bInterval;
-+ /** ISO Packet number per frame */
-+ uint32_t pkt_per_frm;
-+ /** Next frame num for which will be setup DMA Desc */
-+ uint32_t next_frame;
-+ /** Number of packets per buffer processing */
-+ uint32_t pkt_cnt;
-+ /** Info for all isoc packets */
-+ iso_pkt_info_t *pkt_info;
-+ /** current pkt number */
-+ uint32_t cur_pkt;
-+ /** current pkt number */
-+ uint8_t *cur_pkt_addr;
-+ /** current pkt number */
-+ uint32_t cur_pkt_dma_addr;
-+#endif //DWC_EN_ISOC
-+/** @} */
-+} dwc_ep_t;
-+
-+/*
-+ * Reasons for halting a host channel.
-+ */
-+typedef enum dwc_otg_halt_status
-+{
-+ DWC_OTG_HC_XFER_NO_HALT_STATUS,
-+ DWC_OTG_HC_XFER_COMPLETE,
-+ DWC_OTG_HC_XFER_URB_COMPLETE,
-+ DWC_OTG_HC_XFER_ACK,
-+ DWC_OTG_HC_XFER_NAK,
-+ DWC_OTG_HC_XFER_NYET,
-+ DWC_OTG_HC_XFER_STALL,
-+ DWC_OTG_HC_XFER_XACT_ERR,
-+ DWC_OTG_HC_XFER_FRAME_OVERRUN,
-+ DWC_OTG_HC_XFER_BABBLE_ERR,
-+ DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
-+ DWC_OTG_HC_XFER_AHB_ERR,
-+ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
-+ DWC_OTG_HC_XFER_URB_DEQUEUE
-+} dwc_otg_halt_status_e;
-+
-+/**
-+ * Host channel descriptor. This structure represents the state of a single
-+ * host channel when acting in host mode. It contains the data items needed to
-+ * transfer packets to an endpoint via a host channel.
-+ */
-+typedef struct dwc_hc
-+{
-+ /** Host channel number used for register address lookup */
-+ uint8_t hc_num;
-+
-+ /** Device to access */
-+ unsigned dev_addr : 7;
-+
-+ /** EP to access */
-+ unsigned ep_num : 4;
-+
-+ /** EP direction. 0: OUT, 1: IN */
-+ unsigned ep_is_in : 1;
-+
-+ /**
-+ * EP speed.
-+ * One of the following values:
-+ * - DWC_OTG_EP_SPEED_LOW
-+ * - DWC_OTG_EP_SPEED_FULL
-+ * - DWC_OTG_EP_SPEED_HIGH
-+ */
-+ unsigned speed : 2;
-+#define DWC_OTG_EP_SPEED_LOW 0
-+#define DWC_OTG_EP_SPEED_FULL 1
-+#define DWC_OTG_EP_SPEED_HIGH 2
-+
-+ /**
-+ * Endpoint type.
-+ * One of the following values:
-+ * - DWC_OTG_EP_TYPE_CONTROL: 0
-+ * - DWC_OTG_EP_TYPE_ISOC: 1
-+ * - DWC_OTG_EP_TYPE_BULK: 2
-+ * - DWC_OTG_EP_TYPE_INTR: 3
-+ */
-+ unsigned ep_type : 2;
-+
-+ /** Max packet size in bytes */
-+ unsigned max_packet : 11;
-+
-+ /**
-+ * PID for initial transaction.
-+ * 0: DATA0,<br>
-+ * 1: DATA2,<br>
-+ * 2: DATA1,<br>
-+ * 3: MDATA (non-Control EP),
-+ * SETUP (Control EP)
-+ */
-+ unsigned data_pid_start : 2;
-+#define DWC_OTG_HC_PID_DATA0 0
-+#define DWC_OTG_HC_PID_DATA2 1
-+#define DWC_OTG_HC_PID_DATA1 2
-+#define DWC_OTG_HC_PID_MDATA 3
-+#define DWC_OTG_HC_PID_SETUP 3
-+
-+ /** Number of periodic transactions per (micro)frame */
-+ unsigned multi_count: 2;
-+
-+ /** @name Transfer State */
-+ /** @{ */
-+
-+ /** Pointer to the current transfer buffer position. */
-+ uint8_t *xfer_buff;
-+ /** Total number of bytes to transfer. */
-+ uint32_t xfer_len;
-+ /** Number of bytes transferred so far. */
-+ uint32_t xfer_count;
-+ /** Packet count at start of transfer.*/
-+ uint16_t start_pkt_count;
-+
-+ /**
-+ * Flag to indicate whether the transfer has been started. Set to 1 if
-+ * it has been started, 0 otherwise.
-+ */
-+ uint8_t xfer_started;
-+
-+ /**
-+ * Set to 1 to indicate that a PING request should be issued on this
-+ * channel. If 0, process normally.
-+ */
-+ uint8_t do_ping;
-+
-+ /**
-+ * Set to 1 to indicate that the error count for this transaction is
-+ * non-zero. Set to 0 if the error count is 0.
-+ */
-+ uint8_t error_state;
-+
-+ /**
-+ * Set to 1 to indicate that this channel should be halted the next
-+ * time a request is queued for the channel. This is necessary in
-+ * slave mode if no request queue space is available when an attempt
-+ * is made to halt the channel.
-+ */
-+ uint8_t halt_on_queue;
-+
-+ /**
-+ * Set to 1 if the host channel has been halted, but the core is not
-+ * finished flushing queued requests. Otherwise 0.
-+ */
-+ uint8_t halt_pending;
-+
-+ /**
-+ * Reason for halting the host channel.
-+ */
-+ dwc_otg_halt_status_e halt_status;
-+
-+ /*
-+ * Split settings for the host channel
-+ */
-+ uint8_t do_split; /**< Enable split for the channel */
-+ uint8_t complete_split; /**< Enable complete split */
-+ uint8_t hub_addr; /**< Address of high speed hub */
-+
-+ uint8_t port_addr; /**< Port of the low/full speed device */
-+ /** Split transaction position
-+ * One of the following values:
-+ * - DWC_HCSPLIT_XACTPOS_MID
-+ * - DWC_HCSPLIT_XACTPOS_BEGIN
-+ * - DWC_HCSPLIT_XACTPOS_END
-+ * - DWC_HCSPLIT_XACTPOS_ALL */
-+ uint8_t xact_pos;
-+
-+ /** Set when the host channel does a short read. */
-+ uint8_t short_read;
-+
-+ /**
-+ * Number of requests issued for this channel since it was assigned to
-+ * the current transfer (not counting PINGs).
-+ */
-+ uint8_t requests;
-+
-+ /**
-+ * Queue Head for the transfer being processed by this channel.
-+ */
-+ struct dwc_otg_qh *qh;
-+
-+ /** @} */
-+
-+ /** Entry in list of host channels. */
-+ struct list_head hc_list_entry;
-+} dwc_hc_t;
-+
-+/**
-+ * The following parameters may be specified when starting the module. These
-+ * parameters define how the DWC_otg controller should be configured.
-+ * Parameter values are passed to the CIL initialization function
-+ * dwc_otg_cil_init.
-+ */
-+typedef struct dwc_otg_core_params
-+{
-+ int32_t opt;
-+#define dwc_param_opt_default 1
-+
-+ /**
-+ * Specifies the OTG capabilities. The driver will automatically
-+ * detect the value for this parameter if none is specified.
-+ * 0 - HNP and SRP capable (default)
-+ * 1 - SRP Only capable
-+ * 2 - No HNP/SRP capable
-+ */
-+ int32_t otg_cap;
-+#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
-+#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
-+#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
-+#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
-+
-+ /**
-+ * Specifies whether to use slave or DMA mode for accessing the data
-+ * FIFOs. The driver will automatically detect the value for this
-+ * parameter if none is specified.
-+ * 0 - Slave
-+ * 1 - DMA (default, if available)
-+ */
-+ int32_t dma_enable;
-+#define dwc_param_dma_enable_default 1
-+
-+ /**
-+ * When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data
-+ * FIFOs in device mode. The driver will automatically detect the value for this
-+ * parameter if none is specified.
-+ * 0 - address DMA
-+ * 1 - DMA Descriptor(default, if available)
-+ */
-+ int32_t dma_desc_enable;
-+#define dwc_param_dma_desc_enable_default 0
-+ /** The DMA Burst size (applicable only for External DMA
-+ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
-+ */
-+ int32_t dma_burst_size; /* Translate this to GAHBCFG values */
-+#define dwc_param_dma_burst_size_default 32
-+
-+ /**
-+ * Specifies the maximum speed of operation in host and device mode.
-+ * The actual speed depends on the speed of the attached device and
-+ * the value of phy_type. The actual speed depends on the speed of the
-+ * attached device.
-+ * 0 - High Speed (default)
-+ * 1 - Full Speed
-+ */
-+ int32_t speed;
-+#define dwc_param_speed_default 0
-+#define DWC_SPEED_PARAM_HIGH 0
-+#define DWC_SPEED_PARAM_FULL 1
-+
-+ /** Specifies whether low power mode is supported when attached
-+ * to a Full Speed or Low Speed device in host mode.
-+ * 0 - Don't support low power mode (default)
-+ * 1 - Support low power mode
-+ */
-+ int32_t host_support_fs_ls_low_power;
-+#define dwc_param_host_support_fs_ls_low_power_default 0
-+
-+ /** Specifies the PHY clock rate in low power mode when connected to a
-+ * Low Speed device in host mode. This parameter is applicable only if
-+ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
-+ * then defaults to 6 MHZ otherwise 48 MHZ.
-+ *
-+ * 0 - 48 MHz
-+ * 1 - 6 MHz
-+ */
-+ int32_t host_ls_low_power_phy_clk;
-+#define dwc_param_host_ls_low_power_phy_clk_default 0
-+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
-+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
-+
-+ /**
-+ * 0 - Use cC FIFO size parameters
-+ * 1 - Allow dynamic FIFO sizing (default)
-+ */
-+ int32_t enable_dynamic_fifo;
-+#define dwc_param_enable_dynamic_fifo_default 1
-+
-+ /** Total number of 4-byte words in the data FIFO memory. This
-+ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
-+ * Tx FIFOs.
-+ * 32 to 32768 (default 8192)
-+ * Note: The total FIFO memory depth in the FPGA configuration is 8192.
-+ */
-+ int32_t data_fifo_size;
-+#define dwc_param_data_fifo_size_default 8192
-+
-+ /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1064)
-+ */
-+ int32_t dev_rx_fifo_size;
-+#define dwc_param_dev_rx_fifo_size_default 1064
-+
-+ /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
-+ * when dynamic FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+ int32_t dev_nperio_tx_fifo_size;
-+#define dwc_param_dev_nperio_tx_fifo_size_default 1024
-+
-+ /** Number of 4-byte words in each of the periodic Tx FIFOs in device
-+ * mode when dynamic FIFO sizing is enabled.
-+ * 4 to 768 (default 256)
-+ */
-+ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
-+#define dwc_param_dev_perio_tx_fifo_size_default 256
-+
-+ /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+ int32_t host_rx_fifo_size;
-+#define dwc_param_host_rx_fifo_size_default 1024
-+
-+ /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
-+ * when Dynamic FIFO sizing is enabled in the core.
-+ * 16 to 32768 (default 1024)
-+ */
-+ int32_t host_nperio_tx_fifo_size;
-+#define dwc_param_host_nperio_tx_fifo_size_default 1024
-+
-+ /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+ int32_t host_perio_tx_fifo_size;
-+#define dwc_param_host_perio_tx_fifo_size_default 1024
-+
-+ /** The maximum transfer size supported in bytes.
-+ * 2047 to 65,535 (default 65,535)
-+ */
-+ int32_t max_transfer_size;
-+#define dwc_param_max_transfer_size_default 65535
-+
-+ /** The maximum number of packets in a transfer.
-+ * 15 to 511 (default 511)
-+ */
-+ int32_t max_packet_count;
-+#define dwc_param_max_packet_count_default 511
-+
-+ /** The number of host channel registers to use.
-+ * 1 to 16 (default 12)
-+ * Note: The FPGA configuration supports a maximum of 12 host channels.
-+ */
-+ int32_t host_channels;
-+#define dwc_param_host_channels_default 12
-+
-+ /** The number of endpoints in addition to EP0 available for device
-+ * mode operations.
-+ * 1 to 15 (default 6 IN and OUT)
-+ * Note: The FPGA configuration supports a maximum of 6 IN and OUT
-+ * endpoints in addition to EP0.
-+ */
-+ int32_t dev_endpoints;
-+#define dwc_param_dev_endpoints_default 6
-+
-+ /**
-+ * Specifies the type of PHY interface to use. By default, the driver
-+ * will automatically detect the phy_type.
-+ *
-+ * 0 - Full Speed PHY
-+ * 1 - UTMI+ (default)
-+ * 2 - ULPI
-+ */
-+ int32_t phy_type;
-+#define DWC_PHY_TYPE_PARAM_FS 0
-+#define DWC_PHY_TYPE_PARAM_UTMI 1
-+#define DWC_PHY_TYPE_PARAM_ULPI 2
-+#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
-+
-+ /**
-+ * Specifies the UTMI+ Data Width. This parameter is
-+ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
-+ * PHY_TYPE, this parameter indicates the data width between
-+ * the MAC and the ULPI Wrapper.) Also, this parameter is
-+ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
-+ * to "8 and 16 bits", meaning that the core has been
-+ * configured to work at either data path width.
-+ *
-+ * 8 or 16 bits (default 16)
-+ */
-+ int32_t phy_utmi_width;
-+#define dwc_param_phy_utmi_width_default 16
-+
-+ /**
-+ * Specifies whether the ULPI operates at double or single
-+ * data rate. This parameter is only applicable if PHY_TYPE is
-+ * ULPI.
-+ *
-+ * 0 - single data rate ULPI interface with 8 bit wide data
-+ * bus (default)
-+ * 1 - double data rate ULPI interface with 4 bit wide data
-+ * bus
-+ */
-+ int32_t phy_ulpi_ddr;
-+#define dwc_param_phy_ulpi_ddr_default 0
-+
-+ /**
-+ * Specifies whether to use the internal or external supply to
-+ * drive the vbus with a ULPI phy.
-+ */
-+ int32_t phy_ulpi_ext_vbus;
-+#define DWC_PHY_ULPI_INTERNAL_VBUS 0
-+#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
-+#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
-+
-+ /**
-+ * Specifies whether to use the I2Cinterface for full speed PHY. This
-+ * parameter is only applicable if PHY_TYPE is FS.
-+ * 0 - No (default)
-+ * 1 - Yes
-+ */
-+ int32_t i2c_enable;
-+#define dwc_param_i2c_enable_default 0
-+
-+ int32_t ulpi_fs_ls;
-+#define dwc_param_ulpi_fs_ls_default 0
-+
-+ int32_t ts_dline;
-+#define dwc_param_ts_dline_default 0
-+
-+ /**
-+ * Specifies whether dedicated transmit FIFOs are
-+ * enabled for non periodic IN endpoints in device mode
-+ * 0 - No
-+ * 1 - Yes
-+ */
-+ int32_t en_multiple_tx_fifo;
-+#define dwc_param_en_multiple_tx_fifo_default 1
-+
-+ /** Number of 4-byte words in each of the Tx FIFOs in device
-+ * mode when dynamic FIFO sizing is enabled.
-+ * 4 to 768 (default 256)
-+ */
-+ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
-+#define dwc_param_dev_tx_fifo_size_default 256
-+
-+ /** Thresholding enable flag-
-+ * bit 0 - enable non-ISO Tx thresholding
-+ * bit 1 - enable ISO Tx thresholding
-+ * bit 2 - enable Rx thresholding
-+ */
-+ uint32_t thr_ctl;
-+#define dwc_param_thr_ctl_default 0
-+
-+ /** Thresholding length for Tx
-+ * FIFOs in 32 bit DWORDs
-+ */
-+ uint32_t tx_thr_length;
-+#define dwc_param_tx_thr_length_default 64
-+
-+ /** Thresholding length for Rx
-+ * FIFOs in 32 bit DWORDs
-+ */
-+ uint32_t rx_thr_length;
-+#define dwc_param_rx_thr_length_default 64
-+
-+ /** Per Transfer Interrupt
-+ * mode enable flag
-+ * 1 - Enabled
-+ * 0 - Disabled
-+ */
-+ uint32_t pti_enable;
-+#define dwc_param_pti_enable_default 0
-+
-+ /** Molti Processor Interrupt
-+ * mode enable flag
-+ * 1 - Enabled
-+ * 0 - Disabled
-+ */
-+ uint32_t mpi_enable;
-+#define dwc_param_mpi_enable_default 0
-+
-+} dwc_otg_core_params_t;
-+
-+#ifdef DEBUG
-+struct dwc_otg_core_if;
-+typedef struct hc_xfer_info
-+{
-+ struct dwc_otg_core_if *core_if;
-+ dwc_hc_t *hc;
-+} hc_xfer_info_t;
-+#endif
-+
-+/**
-+ * The <code>dwc_otg_core_if</code> structure contains information needed to manage
-+ * the DWC_otg controller acting in either host or device mode. It
-+ * represents the programming view of the controller as a whole.
-+ */
-+typedef struct dwc_otg_core_if
-+{
-+ /** Parameters that define how the core should be configured.*/
-+ dwc_otg_core_params_t *core_params;
-+
-+ /** Core Global registers starting at offset 000h. */
-+ dwc_otg_core_global_regs_t *core_global_regs;
-+
-+ /** Device-specific information */
-+ dwc_otg_dev_if_t *dev_if;
-+ /** Host-specific information */
-+ dwc_otg_host_if_t *host_if;
-+
-+ /** Value from SNPSID register */
-+ uint32_t snpsid;
-+
-+ /*
-+ * Set to 1 if the core PHY interface bits in USBCFG have been
-+ * initialized.
-+ */
-+ uint8_t phy_init_done;
-+
-+ /*
-+ * SRP Success flag, set by srp success interrupt in FS I2C mode
-+ */
-+ uint8_t srp_success;
-+ uint8_t srp_timer_started;
-+
-+ /* Common configuration information */
-+ /** Power and Clock Gating Control Register */
-+ volatile uint32_t *pcgcctl;
-+#define DWC_OTG_PCGCCTL_OFFSET 0xE00
-+
-+ /** Push/pop addresses for endpoints or host channels.*/
-+ uint32_t *data_fifo[MAX_EPS_CHANNELS];
-+#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
-+#define DWC_OTG_DATA_FIFO_SIZE 0x1000
-+
-+ /** Total RAM for FIFOs (Bytes) */
-+ uint16_t total_fifo_size;
-+ /** Size of Rx FIFO (Bytes) */
-+ uint16_t rx_fifo_size;
-+ /** Size of Non-periodic Tx FIFO (Bytes) */
-+ uint16_t nperio_tx_fifo_size;
-+
-+
-+ /** 1 if DMA is enabled, 0 otherwise. */
-+ uint8_t dma_enable;
-+
-+ /** 1 if Descriptor DMA mode is enabled, 0 otherwise. */
-+ uint8_t dma_desc_enable;
-+
-+ /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
-+ uint8_t pti_enh_enable;
-+
-+ /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
-+ uint8_t multiproc_int_enable;
-+
-+ /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
-+ uint8_t en_multiple_tx_fifo;
-+
-+ /** Set to 1 if multiple packets of a high-bandwidth transfer is in
-+ * process of being queued */
-+ uint8_t queuing_high_bandwidth;
-+
-+ /** Hardware Configuration -- stored here for convenience.*/
-+ hwcfg1_data_t hwcfg1;
-+ hwcfg2_data_t hwcfg2;
-+ hwcfg3_data_t hwcfg3;
-+ hwcfg4_data_t hwcfg4;
-+
-+ /** Host and Device Configuration -- stored here for convenience.*/
-+ hcfg_data_t hcfg;
-+ dcfg_data_t dcfg;
-+
-+ /** The operational State, during transations
-+ * (a_host>>a_peripherial and b_device=>b_host) this may not
-+ * match the core but allows the software to determine
-+ * transitions.
-+ */
-+ uint8_t op_state;
-+
-+ /**
-+ * Set to 1 if the HCD needs to be restarted on a session request
-+ * interrupt. This is required if no connector ID status change has
-+ * occurred since the HCD was last disconnected.
-+ */
-+ uint8_t restart_hcd_on_session_req;
-+
-+ /** HCD callbacks */
-+ /** A-Device is a_host */
-+#define A_HOST (1)
-+ /** A-Device is a_suspend */
-+#define A_SUSPEND (2)
-+ /** A-Device is a_peripherial */
-+#define A_PERIPHERAL (3)
-+ /** B-Device is operating as a Peripheral. */
-+#define B_PERIPHERAL (4)
-+ /** B-Device is operating as a Host. */
-+#define B_HOST (5)
-+
-+ /** HCD callbacks */
-+ struct dwc_otg_cil_callbacks *hcd_cb;
-+ /** PCD callbacks */
-+ struct dwc_otg_cil_callbacks *pcd_cb;
-+
-+ /** Device mode Periodic Tx FIFO Mask */
-+ uint32_t p_tx_msk;
-+ /** Device mode Periodic Tx FIFO Mask */
-+ uint32_t tx_msk;
-+
-+ /** Workqueue object used for handling several interrupts */
-+ struct workqueue_struct *wq_otg;
-+
-+ /** Work object used for handling "Connector ID Status Change" Interrupt */
-+ struct work_struct w_conn_id;
-+
-+ /** Work object used for handling "Wakeup Detected" Interrupt */
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
-+ struct work_struct w_wkp;
-+#else
-+ struct delayed_work w_wkp;
-+#endif
-+
-+#ifdef DEBUG
-+ uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
-+
-+ hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
-+ struct timer_list hc_xfer_timer[MAX_EPS_CHANNELS];
-+
-+ uint32_t hfnum_7_samples;
-+ uint64_t hfnum_7_frrem_accum;
-+ uint32_t hfnum_0_samples;
-+ uint64_t hfnum_0_frrem_accum;
-+ uint32_t hfnum_other_samples;
-+ uint64_t hfnum_other_frrem_accum;
-+#endif
-+
-+
-+} dwc_otg_core_if_t;
-+
-+/*We must clear S3C24XX_EINTPEND external interrupt register
-+ * because after clearing in this register trigerred IRQ from
-+ * H/W core in kernel interrupt can be occured again before OTG
-+ * handlers clear all IRQ sources of Core registers because of
-+ * timing latencies and Low Level IRQ Type.
-+ */
-+
-+#ifdef CONFIG_MACH_IPMATE
-+#define S3C2410X_CLEAR_EINTPEND() \
-+do { \
-+ if (!dwc_otg_read_core_intr(core_if)) { \
-+ __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
-+ } \
-+} while (0)
-+#else
-+#define S3C2410X_CLEAR_EINTPEND() do { } while (0)
-+#endif
-+
-+/*
-+ * The following functions are functions for works
-+ * using during handling some interrupts
-+ */
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
-+
-+extern void w_conn_id_status_change(void *p);
-+extern void w_wakeup_detected(void *p);
-+
-+#else
-+
-+extern void w_conn_id_status_change(struct work_struct *p);
-+extern void w_wakeup_detected(struct work_struct *p);
-+
-+#endif
-+
-+
-+/*
-+ * The following functions support initialization of the CIL driver component
-+ * and the DWC_otg controller.
-+ */
-+extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr,
-+ dwc_otg_core_params_t *_core_params);
-+extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if);
-+extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if);
-+extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if);
-+extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if);
-+extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if );
-+extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if );
-+
-+/** @name Device CIL Functions
-+ * The following functions support managing the DWC_otg controller in device
-+ * mode.
-+ */
-+/**@{*/
-+extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if);
-+extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest);
-+extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if);
-+extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
-+extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
-+extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
-+extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
-+extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
-+extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
-+extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
-+extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma);
-+extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
-+extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
-+extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if);
-+extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if);
-+extern void dwc_otg_dump_spram(dwc_otg_core_if_t *_core_if);
-+#ifdef DWC_EN_ISOC
-+extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep);
-+extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep);
-+#endif //DWC_EN_ISOC
-+/**@}*/
-+
-+/** @name Host CIL Functions
-+ * The following functions support managing the DWC_otg controller in host
-+ * mode.
-+ */
-+/**@{*/
-+extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
-+extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
-+ dwc_hc_t *_hc,
-+ dwc_otg_halt_status_e _halt_status);
-+extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
-+extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
-+extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
-+extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
-+extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
-+extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if);
-+extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if);
-+
-+/**
-+ * This function Reads HPRT0 in preparation to modify. It keeps the
-+ * WC bits 0 so that if they are read as 1, they won't clear when you
-+ * write it back
-+ */
-+static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if)
-+{
-+ hprt0_data_t hprt0;
-+ hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
-+ hprt0.b.prtena = 0;
-+ hprt0.b.prtconndet = 0;
-+ hprt0.b.prtenchng = 0;
-+ hprt0.b.prtovrcurrchng = 0;
-+ return hprt0.d32;
-+}
-+
-+extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if);
-+/**@}*/
-+
-+/** @name Common CIL Functions
-+ * The following functions support managing the DWC_otg controller in either
-+ * device or host mode.
-+ */
-+/**@{*/
-+
-+extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
-+ uint8_t *dest,
-+ uint16_t bytes);
-+
-+extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if);
-+
-+extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if,
-+ const int _num );
-+extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if );
-+extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if );
-+
-+extern dwc_otg_dma_desc_t* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, uint32_t count);
-+extern void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t* desc_addr, uint32_t dma_desc_addr, uint32_t count);
-+
-+/**
-+ * This function returns the Core Interrupt register.
-+ */
-+static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if)
-+{
-+ return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) &
-+ dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
-+}
-+
-+/**
-+ * This function returns the OTG Interrupt register.
-+ */
-+static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if)
-+{
-+ return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint));
-+}
-+
-+/**
-+ * This function reads the Device All Endpoints Interrupt register and
-+ * returns the IN endpoint interrupt bits.
-+ */
-+static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *core_if)
-+{
-+ uint32_t v;
-+
-+ if(core_if->multiproc_int_enable) {
-+ v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) &
-+ dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk);
-+ } else {
-+ v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
-+ dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
-+ }
-+ return (v & 0xffff);
-+
-+}
-+
-+/**
-+ * This function reads the Device All Endpoints Interrupt register and
-+ * returns the OUT endpoint interrupt bits.
-+ */
-+static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *core_if)
-+{
-+ uint32_t v;
-+
-+ if(core_if->multiproc_int_enable) {
-+ v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) &
-+ dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk);
-+ } else {
-+ v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
-+ dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
-+ }
-+
-+ return ((v & 0xffff0000) >> 16);
-+}
-+
-+/**
-+ * This function returns the Device IN EP Interrupt register
-+ */
-+static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *core_if,
-+ dwc_ep_t *ep)
-+{
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ uint32_t v, msk, emp;
-+
-+ if(core_if->multiproc_int_enable) {
-+ msk = dwc_read_reg32(&dev_if->dev_global_regs->diepeachintmsk[ep->num]);
-+ emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
-+ msk |= ((emp >> ep->num) & 0x1) << 7;
-+ v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
-+ } else {
-+ msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
-+ emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
-+ msk |= ((emp >> ep->num) & 0x1) << 7;
-+ v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
-+ }
-+
-+
-+ return v;
-+}
-+/**
-+ * This function returns the Device OUT EP Interrupt register
-+ */
-+static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if,
-+ dwc_ep_t *_ep)
-+{
-+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
-+ uint32_t v;
-+ doepmsk_data_t msk = { .d32 = 0 };
-+
-+ if(_core_if->multiproc_int_enable) {
-+ msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepeachintmsk[_ep->num]);
-+ if(_core_if->pti_enh_enable) {
-+ msk.b.pktdrpsts = 1;
-+ }
-+ v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32;
-+ } else {
-+ msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
-+ if(_core_if->pti_enh_enable) {
-+ msk.b.pktdrpsts = 1;
-+ }
-+ v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32;
-+ }
-+ return v;
-+}
-+
-+/**
-+ * This function returns the Host All Channel Interrupt register
-+ */
-+static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
-+{
-+ return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint));
-+}
-+
-+static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
-+{
-+ return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
-+}
-+
-+
-+/**
-+ * This function returns the mode of the operation, host or device.
-+ *
-+ * @return 0 - Device Mode, 1 - Host Mode
-+ */
-+static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if)
-+{
-+ return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1);
-+}
-+
-+static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if)
-+{
-+ return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
-+}
-+static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if)
-+{
-+ return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
-+}
-+
-+extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if );
-+
-+
-+/**@}*/
-+
-+/**
-+ * DWC_otg CIL callback structure. This structure allows the HCD and
-+ * PCD to register functions used for starting and stopping the PCD
-+ * and HCD for role change on for a DRD.
-+ */
-+typedef struct dwc_otg_cil_callbacks
-+{
-+ /** Start function for role change */
-+ int (*start) (void *_p);
-+ /** Stop Function for role change */
-+ int (*stop) (void *_p);
-+ /** Disconnect Function for role change */
-+ int (*disconnect) (void *_p);
-+ /** Resume/Remote wakeup Function */
-+ int (*resume_wakeup) (void *_p);
-+ /** Suspend function */
-+ int (*suspend) (void *_p);
-+ /** Session Start (SRP) */
-+ int (*session_start) (void *_p);
-+ /** Pointer passed to start() and stop() */
-+ void *p;
-+} dwc_otg_cil_callbacks_t;
-+
-+extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if,
-+ dwc_otg_cil_callbacks_t *_cb,
-+ void *_p);
-+extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if,
-+ dwc_otg_cil_callbacks_t *_cb,
-+ void *_p);
-+
-+#endif
-+
---- /dev/null
-+++ b/drivers/usb/dwc_otg/dwc_otg_cil_intr.c
-@@ -0,0 +1,750 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
-+ * $Revision: 1.2 $
-+ * $Date: 2008-11-21 05:39:15 $
-+ * $Change: 1065567 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ *
-+ * The Core Interface Layer provides basic services for accessing and
-+ * managing the DWC_otg hardware. These services are used by both the
-+ * Host Controller Driver and the Peripheral Controller Driver.
-+ *
-+ * This file contains the Common Interrupt handlers.
-+ */
-+#include "linux/dwc_otg_plat.h"
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_cil.h"
-+
-+#ifdef DEBUG
-+inline const char *op_state_str(dwc_otg_core_if_t *core_if)
-+{
-+ return (core_if->op_state==A_HOST?"a_host":
-+ (core_if->op_state==A_SUSPEND?"a_suspend":
-+ (core_if->op_state==A_PERIPHERAL?"a_peripheral":
-+ (core_if->op_state==B_PERIPHERAL?"b_peripheral":
-+ (core_if->op_state==B_HOST?"b_host":
-+ "unknown")))));
-+}
-+#endif
-+
-+/** This function will log a debug message
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *core_if)
-+{
-+ gintsts_data_t gintsts;
-+ DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
-+ dwc_otg_mode(core_if) ? "Host" : "Device");
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.modemismatch = 1;
-+ dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
-+ return 1;
-+}
-+
-+/** Start the HCD. Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void hcd_start(dwc_otg_core_if_t *core_if)
-+{
-+ if (core_if->hcd_cb && core_if->hcd_cb->start) {
-+ core_if->hcd_cb->start(core_if->hcd_cb->p);
-+ }
-+}
-+/** Stop the HCD. Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void hcd_stop(dwc_otg_core_if_t *core_if)
-+{
-+ if (core_if->hcd_cb && core_if->hcd_cb->stop) {
-+ core_if->hcd_cb->stop(core_if->hcd_cb->p);
-+ }
-+}
-+/** Disconnect the HCD. Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void hcd_disconnect(dwc_otg_core_if_t *core_if)
-+{
-+ if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
-+ core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
-+ }
-+}
-+/** Inform the HCD the a New Session has begun. Helper function for
-+ * using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void hcd_session_start(dwc_otg_core_if_t *core_if)
-+{
-+ if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
-+ core_if->hcd_cb->session_start(core_if->hcd_cb->p);
-+ }
-+}
-+
-+/** Start the PCD. Helper function for using the PCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void pcd_start(dwc_otg_core_if_t *core_if)
-+{
-+ if (core_if->pcd_cb && core_if->pcd_cb->start) {
-+ core_if->pcd_cb->start(core_if->pcd_cb->p);
-+ }
-+}
-+/** Stop the PCD. Helper function for using the PCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void pcd_stop(dwc_otg_core_if_t *core_if)
-+{
-+ if (core_if->pcd_cb && core_if->pcd_cb->stop) {
-+ core_if->pcd_cb->stop(core_if->pcd_cb->p);
-+ }
-+}
-+/** Suspend the PCD. Helper function for using the PCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void pcd_suspend(dwc_otg_core_if_t *core_if)
-+{
-+ if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
-+ core_if->pcd_cb->suspend(core_if->pcd_cb->p);
-+ }
-+}
-+/** Resume the PCD. Helper function for using the PCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void pcd_resume(dwc_otg_core_if_t *core_if)
-+{
-+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
-+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
-+ }
-+}
-+
-+/**
-+ * This function handles the OTG Interrupts. It reads the OTG
-+ * Interrupt Register (GOTGINT) to determine what interrupt has
-+ * occurred.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs =
-+ core_if->core_global_regs;
-+ gotgint_data_t gotgint;
-+ gotgctl_data_t gotgctl;
-+ gintmsk_data_t gintmsk;
-+
-+ gotgint.d32 = dwc_read_reg32(&global_regs->gotgint);
-+ gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
-+ DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32);
-+
-+ if (gotgint.b.sesenddet) {
-+ DWC_DEBUGPL(DBG_ANY, "OTG Interrupt: "
-+ "Session End Detected++ (%s)\n",
-+ op_state_str(core_if));
-+ gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
-+
-+ if (core_if->op_state == B_HOST) {
-+ pcd_start(core_if);
-+ core_if->op_state = B_PERIPHERAL;
-+ } else {
-+ /* If not B_HOST and Device HNP still set. HNP
-+ * Did not succeed!*/
-+ if (gotgctl.b.devhnpen) {
-+ DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
-+ DWC_ERROR("Device Not Connected/Responding!\n");
-+ }
-+
-+ /* If Session End Detected the B-Cable has
-+ * been disconnected. */
-+ /* Reset PCD and Gadget driver to a
-+ * clean state. */
-+ pcd_stop(core_if);
-+ }
-+ gotgctl.d32 = 0;
-+ gotgctl.b.devhnpen = 1;
-+ dwc_modify_reg32(&global_regs->gotgctl,
-+ gotgctl.d32, 0);
-+ }
-+ if (gotgint.b.sesreqsucstschng) {
-+ DWC_DEBUGPL(DBG_ANY, " OTG Interrupt: "
-+ "Session Reqeust Success Status Change++\n");
-+ gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
-+ if (gotgctl.b.sesreqscs) {
-+ if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
-+ (core_if->core_params->i2c_enable)) {
-+ core_if->srp_success = 1;
-+ }
-+ else {
-+ pcd_resume(core_if);
-+ /* Clear Session Request */
-+ gotgctl.d32 = 0;
-+ gotgctl.b.sesreq = 1;
-+ dwc_modify_reg32(&global_regs->gotgctl,
-+ gotgctl.d32, 0);
-+ }
-+ }
-+ }
-+ if (gotgint.b.hstnegsucstschng) {
-+ /* Print statements during the HNP interrupt handling
-+ * can cause it to fail.*/
-+ gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
-+ if (gotgctl.b.hstnegscs) {
-+ if (dwc_otg_is_host_mode(core_if)) {
-+ core_if->op_state = B_HOST;
-+ /*
-+ * Need to disable SOF interrupt immediately.
-+ * When switching from device to host, the PCD
-+ * interrupt handler won't handle the
-+ * interrupt if host mode is already set. The
-+ * HCD interrupt handler won't get called if
-+ * the HCD state is HALT. This means that the
-+ * interrupt does not get handled and Linux
-+ * complains loudly.
-+ */
-+ gintmsk.d32 = 0;
-+ gintmsk.b.sofintr = 1;
-+ dwc_modify_reg32(&global_regs->gintmsk,
-+ gintmsk.d32, 0);
-+ pcd_stop(core_if);
-+ /*
-+ * Initialize the Core for Host mode.
-+ */
-+ hcd_start(core_if);
-+ core_if->op_state = B_HOST;
-+ }
-+ } else {
-+ gotgctl.d32 = 0;
-+ gotgctl.b.hnpreq = 1;
-+ gotgctl.b.devhnpen = 1;
-+ dwc_modify_reg32(&global_regs->gotgctl,
-+ gotgctl.d32, 0);
-+ DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
-+ DWC_ERROR("Device Not Connected/Responding\n");
-+ }
-+ }
-+ if (gotgint.b.hstnegdet) {
-+ /* The disconnect interrupt is set at the same time as
-+ * Host Negotiation Detected. During the mode
-+ * switch all interrupts are cleared so the disconnect
-+ * interrupt handler will not get executed.
-+ */
-+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
-+ "Host Negotiation Detected++ (%s)\n",
-+ (dwc_otg_is_host_mode(core_if)?"Host":"Device"));
-+ if (dwc_otg_is_device_mode(core_if)){
-+ DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n", core_if->op_state);
-+ hcd_disconnect(core_if);
-+ pcd_start(core_if);
-+ core_if->op_state = A_PERIPHERAL;
-+ } else {
-+ /*
-+ * Need to disable SOF interrupt immediately. When
-+ * switching from device to host, the PCD interrupt
-+ * handler won't handle the interrupt if host mode is
-+ * already set. The HCD interrupt handler won't get
-+ * called if the HCD state is HALT. This means that
-+ * the interrupt does not get handled and Linux
-+ * complains loudly.
-+ */
-+ gintmsk.d32 = 0;
-+ gintmsk.b.sofintr = 1;
-+ dwc_modify_reg32(&global_regs->gintmsk,
-+ gintmsk.d32, 0);
-+ pcd_stop(core_if);
-+ hcd_start(core_if);
-+ core_if->op_state = A_HOST;
-+ }
-+ }
-+ if (gotgint.b.adevtoutchng) {
-+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
-+ "A-Device Timeout Change++\n");
-+ }
-+ if (gotgint.b.debdone) {
-+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
-+ "Debounce Done++\n");
-+ }
-+
-+ /* Clear GOTGINT */
-+ dwc_write_reg32 (&core_if->core_global_regs->gotgint, gotgint.d32);
-+
-+ return 1;
-+}
-+
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
-+
-+void w_conn_id_status_change(void *p)
-+{
-+ dwc_otg_core_if_t *core_if = p;
-+
-+#else
-+
-+void w_conn_id_status_change(struct work_struct *p)
-+{
-+ dwc_otg_core_if_t *core_if = container_of(p, dwc_otg_core_if_t, w_conn_id);
-+
-+#endif
-+
-+
-+ uint32_t count = 0;
-+ gotgctl_data_t gotgctl = { .d32 = 0 };
-+
-+ gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
-+ DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
-+ DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
-+
-+ /* B-Device connector (Device Mode) */
-+ if (gotgctl.b.conidsts) {
-+ /* Wait for switch to device mode. */
-+ while (!dwc_otg_is_device_mode(core_if)){
-+ DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n",
-+ (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral"));
-+ MDELAY(100);
-+ if (++count > 10000) *(uint32_t*)NULL=0;
-+ }
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ pcd_start(core_if);
-+ } else {
-+ /* A-Device connector (Host Mode) */
-+ while (!dwc_otg_is_host_mode(core_if)) {
-+ DWC_PRINT("Waiting for Host Mode, Mode=%s\n",
-+ (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral"));
-+ MDELAY(100);
-+ if (++count > 10000) *(uint32_t*)NULL=0;
-+ }
-+ core_if->op_state = A_HOST;
-+ /*
-+ * Initialize the Core for Host mode.
-+ */
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ hcd_start(core_if);
-+ }
-+}
-+
-+
-+/**
-+ * This function handles the Connector ID Status Change Interrupt. It
-+ * reads the OTG Interrupt Register (GOTCTL) to determine whether this
-+ * is a Device to Host Mode transition or a Host Mode to Device
-+ * Transition.
-+ *
-+ * This only occurs when the cable is connected/removed from the PHY
-+ * connector.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *core_if)
-+{
-+
-+ /*
-+ * Need to disable SOF interrupt immediately. If switching from device
-+ * to host, the PCD interrupt handler won't handle the interrupt if
-+ * host mode is already set. The HCD interrupt handler won't get
-+ * called if the HCD state is HALT. This means that the interrupt does
-+ * not get handled and Linux complains loudly.
-+ */
-+ gintmsk_data_t gintmsk = { .d32 = 0 };
-+ gintsts_data_t gintsts = { .d32 = 0 };
-+
-+ gintmsk.b.sofintr = 1;
-+ dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
-+
-+ DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++ (%s)\n",
-+ (dwc_otg_is_host_mode(core_if)?"Host":"Device"));
-+
-+ /*
-+ * Need to schedule a work, as there are possible DELAY function calls
-+ */
-+ queue_work(core_if->wq_otg, &core_if->w_conn_id);
-+
-+ /* Set flag and clear interrupt */
-+ gintsts.b.conidstschng = 1;
-+ dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that a device is initiating the Session
-+ * Request Protocol to request the host to turn on bus power so a new
-+ * session can begin. The handler responds by turning on bus power. If
-+ * the DWC_otg controller is in low power mode, the handler brings the
-+ * controller out of low power mode before turning on bus power.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t *core_if)
-+{
-+ gintsts_data_t gintsts;
-+
-+#ifndef DWC_HOST_ONLY
-+ hprt0_data_t hprt0;
-+ DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
-+
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ DWC_PRINT("SRP: Device mode\n");
-+ } else {
-+ DWC_PRINT("SRP: Host mode\n");
-+
-+ /* Turn on the port power bit. */
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtpwr = 1;
-+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ /* Start the Connection timer. So a message can be displayed
-+ * if connect does not occur within 10 seconds. */
-+ hcd_session_start(core_if);
-+ }
-+#endif
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.sessreqintr = 1;
-+ dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
-+void w_wakeup_detected(void *p)
-+{
-+ dwc_otg_core_if_t* core_if = p;
-+
-+#else
-+
-+void w_wakeup_detected(struct work_struct *p)
-+{
-+ struct delayed_work *dw = container_of(p, struct delayed_work, work);
-+ dwc_otg_core_if_t *core_if = container_of(dw, dwc_otg_core_if_t, w_wkp);
-+
-+#endif
-+ /*
-+ * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
-+ * so that OPT tests pass with all PHYs).
-+ */
-+ hprt0_data_t hprt0 = {.d32=0};
-+#if 0
-+ pcgcctl_data_t pcgcctl = {.d32=0};
-+ /* Restart the Phy Clock */
-+ pcgcctl.b.stoppclk = 1;
-+ dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
-+ UDELAY(10);
-+#endif //0
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32);
-+// MDELAY(70);
-+ hprt0.b.prtres = 0; /* Resume */
-+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
-+ DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(core_if->host_if->hprt0));
-+}
-+/**
-+ * This interrupt indicates that the DWC_otg controller has detected a
-+ * resume or remote wakeup sequence. If the DWC_otg controller is in
-+ * low power mode, the handler must brings the controller out of low
-+ * power mode. The controller automatically begins resume
-+ * signaling. The handler schedules a time to stop resume signaling.
-+ */
-+int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t *core_if)
-+{
-+ gintsts_data_t gintsts;
-+
-+ DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n");
-+
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ dctl_data_t dctl = {.d32=0};
-+ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
-+ dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts));
-+#ifdef PARTIAL_POWER_DOWN
-+ if (core_if->hwcfg4.b.power_optimiz) {
-+ pcgcctl_data_t power = {.d32=0};
-+
-+ power.d32 = dwc_read_reg32(core_if->pcgcctl);
-+ DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32);
-+
-+ power.b.stoppclk = 0;
-+ dwc_write_reg32(core_if->pcgcctl, power.d32);
-+
-+ power.b.pwrclmp = 0;
-+ dwc_write_reg32(core_if->pcgcctl, power.d32);
-+
-+ power.b.rstpdwnmodule = 0;
-+ dwc_write_reg32(core_if->pcgcctl, power.d32);
-+ }
-+#endif
-+ /* Clear the Remote Wakeup Signalling */
-+ dctl.b.rmtwkupsig = 1;
-+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl,
-+ dctl.d32, 0);
-+
-+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
-+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
-+ }
-+
-+ } else {
-+ pcgcctl_data_t pcgcctl = {.d32=0};
-+
-+ /* Restart the Phy Clock */
-+ pcgcctl.b.stoppclk = 1;
-+ dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
-+
-+ queue_delayed_work(core_if->wq_otg, &core_if->w_wkp, ((70 * HZ / 1000) + 1));
-+ }
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.wkupintr = 1;
-+ dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that a device has been disconnected from
-+ * the root port.
-+ */
-+int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t *core_if)
-+{
-+ gintsts_data_t gintsts;
-+
-+ DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
-+ (dwc_otg_is_host_mode(core_if)?"Host":"Device"),
-+ op_state_str(core_if));
-+
-+/** @todo Consolidate this if statement. */
-+#ifndef DWC_HOST_ONLY
-+ if (core_if->op_state == B_HOST) {
-+ /* If in device mode Disconnect and stop the HCD, then
-+ * start the PCD. */
-+ hcd_disconnect(core_if);
-+ pcd_start(core_if);
-+ core_if->op_state = B_PERIPHERAL;
-+ } else if (dwc_otg_is_device_mode(core_if)) {
-+ gotgctl_data_t gotgctl = { .d32 = 0 };
-+ gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
-+ if (gotgctl.b.hstsethnpen==1) {
-+ /* Do nothing, if HNP in process the OTG
-+ * interrupt "Host Negotiation Detected"
-+ * interrupt will do the mode switch.
-+ */
-+ } else if (gotgctl.b.devhnpen == 0) {
-+ /* If in device mode Disconnect and stop the HCD, then
-+ * start the PCD. */
-+ hcd_disconnect(core_if);
-+ pcd_start(core_if);
-+ core_if->op_state = B_PERIPHERAL;
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n");
-+ }
-+ } else {
-+ if (core_if->op_state == A_HOST) {
-+ /* A-Cable still connected but device disconnected. */
-+ hcd_disconnect(core_if);
-+ }
-+ }
-+#endif
-+
-+ gintsts.d32 = 0;
-+ gintsts.b.disconnect = 1;
-+ dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
-+ return 1;
-+}
-+/**
-+ * This interrupt indicates that SUSPEND state has been detected on
-+ * the USB.
-+ *
-+ * For HNP the USB Suspend interrupt signals the change from
-+ * "a_peripheral" to "a_host".
-+ *
-+ * When power management is enabled the core will be put in low power
-+ * mode.
-+ */
-+int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *core_if)
-+{
-+ dsts_data_t dsts;
-+ gintsts_data_t gintsts;
-+
-+ DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n");
-+
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ /* Check the Device status register to determine if the Suspend
-+ * state is active. */
-+ dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
-+ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
-+ DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
-+ "HWCFG4.power Optimize=%d\n",
-+ dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
-+
-+
-+#ifdef PARTIAL_POWER_DOWN
-+/** @todo Add a module parameter for power management. */
-+
-+ if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
-+ pcgcctl_data_t power = {.d32=0};
-+ DWC_DEBUGPL(DBG_CIL, "suspend\n");
-+
-+ power.b.pwrclmp = 1;
-+ dwc_write_reg32(core_if->pcgcctl, power.d32);
-+
-+ power.b.rstpdwnmodule = 1;
-+ dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
-+
-+ power.b.stoppclk = 1;
-+ dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
-+
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY,"disconnect?\n");
-+ }
-+#endif
-+ /* PCD callback for suspend. */
-+ pcd_suspend(core_if);
-+ } else {
-+ if (core_if->op_state == A_PERIPHERAL) {
-+ DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n");
-+ /* Clear the a_peripheral flag, back to a_host. */
-+ pcd_stop(core_if);
-+ hcd_start(core_if);
-+ core_if->op_state = A_HOST;
-+ }
-+ }
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.usbsuspend = 1;
-+ dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+
-+/**
-+ * This function returns the Core Interrupt register.
-+ */
-+static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *core_if)
-+{
-+ gintsts_data_t gintsts;
-+ gintmsk_data_t gintmsk;
-+ gintmsk_data_t gintmsk_common = {.d32=0};
-+ gintmsk_common.b.wkupintr = 1;
-+ gintmsk_common.b.sessreqintr = 1;
-+ gintmsk_common.b.conidstschng = 1;
-+ gintmsk_common.b.otgintr = 1;
-+ gintmsk_common.b.modemismatch = 1;
-+ gintmsk_common.b.disconnect = 1;
-+ gintmsk_common.b.usbsuspend = 1;
-+ /** @todo: The port interrupt occurs while in device
-+ * mode. Added code to CIL to clear the interrupt for now!
-+ */
-+ gintmsk_common.b.portintr = 1;
-+
-+ gintsts.d32 = dwc_read_reg32(&core_if->core_global_regs->gintsts);
-+ gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
-+#ifdef DEBUG
-+ /* if any common interrupts set */
-+ if (gintsts.d32 & gintmsk_common.d32) {
-+ DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n",
-+ gintsts.d32, gintmsk.d32);
-+ }
-+#endif
-+
-+ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
-+
-+}
-+
-+/**
-+ * Common interrupt handler.
-+ *
-+ * The common interrupts are those that occur in both Host and Device mode.
-+ * This handler handles the following interrupts:
-+ * - Mode Mismatch Interrupt
-+ * - Disconnect Interrupt
-+ * - OTG Interrupt
-+ * - Connector ID Status Change Interrupt
-+ * - Session Request Interrupt.
-+ * - Resume / Remote Wakeup Detected Interrupt.
-+ *
-+ */
-+int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t *core_if)
-+{
-+ int retval = 0;
-+ gintsts_data_t gintsts;
-+
-+ gintsts.d32 = dwc_otg_read_common_intr(core_if);
-+
-+ if (gintsts.b.modemismatch) {
-+ retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
-+ }
-+ if (gintsts.b.otgintr) {
-+ retval |= dwc_otg_handle_otg_intr(core_if);
-+ }
-+ if (gintsts.b.conidstschng) {
-+ retval |= dwc_otg_handle_conn_id_status_change_intr(core_if);
-+ }
-+ if (gintsts.b.disconnect) {
-+ retval |= dwc_otg_handle_disconnect_intr(core_if);
-+ }
-+ if (gintsts.b.sessreqintr) {
-+ retval |= dwc_otg_handle_session_req_intr(core_if);
-+ }
-+ if (gintsts.b.wkupintr) {
-+ retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
-+ }
-+ if (gintsts.b.usbsuspend) {
-+ retval |= dwc_otg_handle_usb_suspend_intr(core_if);
-+ }
-+ if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
-+ /* The port interrupt occurs while in device mode with HPRT0
-+ * Port Enable/Disable.
-+ */
-+ gintsts.d32 = 0;
-+ gintsts.b.portintr = 1;
-+ dwc_write_reg32(&core_if->core_global_regs->gintsts,
-+ gintsts.d32);
-+ retval |= 1;
-+
-+ }
-+
-+ S3C2410X_CLEAR_EINTPEND();
-+
-+ return retval;
-+}
---- /dev/null
-+++ b/drivers/usb/dwc_otg/dwc_otg_driver.c
-@@ -0,0 +1,1273 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $
-+ * $Revision: 1.7 $
-+ * $Date: 2008-11-21 05:39:15 $
-+ * $Change: 791271 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ * The dwc_otg_driver module provides the initialization and cleanup entry
-+ * points for the DWC_otg driver. This module will be dynamically installed
-+ * after Linux is booted using the insmod command. When the module is
-+ * installed, the dwc_otg_driver_init function is called. When the module is
-+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
-+ *
-+ * This module also defines a data structure for the dwc_otg_driver, which is
-+ * used in conjunction with the standard ARM platform_device structure. These
-+ * structures allow the OTG driver to comply with the standard Linux driver
-+ * model in which devices and drivers are registered with a bus driver. This
-+ * has the benefit that Linux can expose attributes of the driver and device
-+ * in its special sysfs file system. Users can then read or write files in
-+ * this file system to perform diagnostics on the driver components or the
-+ * device.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/errno.h>
-+#include <linux/types.h>
-+#include <linux/stat.h> /* permission constants */
-+#include <linux/version.h>
-+#include <linux/platform_device.h>
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+# include <linux/irq.h>
-+#endif
-+
-+#include <asm/io.h>
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
-+# include <asm/irq.h>
-+#endif
-+
-+#include "linux/dwc_otg_plat.h"
-+#include "dwc_otg_attr.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_cil.h"
-+#include "dwc_otg_pcd.h"
-+#include "dwc_otg_hcd.h"
-+
-+#define DWC_DRIVER_VERSION "2.72a 24-JUN-2008"
-+#define DWC_DRIVER_DESC "HS OTG USB Controller driver"
-+
-+static const char dwc_driver_name[] = "dwc_otg";
-+
-+/*-------------------------------------------------------------------------*/
-+/* Encapsulate the module parameter settings */
-+
-+static dwc_otg_core_params_t dwc_otg_module_params = {
-+ .opt = -1,
-+ .otg_cap = -1,
-+ .dma_enable = -1,
-+ .dma_desc_enable = -1,
-+ .dma_burst_size = -1,
-+ .speed = -1,
-+ .host_support_fs_ls_low_power = -1,
-+ .host_ls_low_power_phy_clk = -1,
-+ .enable_dynamic_fifo = -1,
-+ .data_fifo_size = -1,
-+ .dev_rx_fifo_size = -1,
-+ .dev_nperio_tx_fifo_size = -1,
-+ .dev_perio_tx_fifo_size = {
-+ /* dev_perio_tx_fifo_size_1 */
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1
-+ /* 15 */
-+ },
-+ .host_rx_fifo_size = -1,
-+ .host_nperio_tx_fifo_size = -1,
-+ .host_perio_tx_fifo_size = -1,
-+ .max_transfer_size = -1,
-+ .max_packet_count = -1,
-+ .host_channels = -1,
-+ .dev_endpoints = -1,
-+ .phy_type = -1,
-+ .phy_utmi_width = -1,
-+ .phy_ulpi_ddr = -1,
-+ .phy_ulpi_ext_vbus = -1,
-+ .i2c_enable = -1,
-+ .ulpi_fs_ls = -1,
-+ .ts_dline = -1,
-+ .en_multiple_tx_fifo = -1,
-+ .dev_tx_fifo_size = {
-+ /* dev_tx_fifo_size */
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1
-+ /* 15 */
-+ },
-+ .thr_ctl = -1,
-+ .tx_thr_length = -1,
-+ .rx_thr_length = -1,
-+ .pti_enable = -1,
-+ .mpi_enable = -1,
-+};
-+
-+/**
-+ * This function shows the Driver Version.
-+ */
-+static ssize_t version_show(struct device_driver *dev, char *buf)
-+{
-+ return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2, "%s\n",
-+ DWC_DRIVER_VERSION);
-+}
-+static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
-+
-+/**
-+ * Global Debug Level Mask.
-+ */
-+uint32_t g_dbg_lvl = 0; /* OFF */
-+
-+/**
-+ * This function shows the driver Debug Level.
-+ */
-+static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
-+{
-+ return sprintf(buf, "0x%0x\n", g_dbg_lvl);
-+}
-+
-+/**
-+ * This function stores the driver Debug Level.
-+ */
-+static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
-+ size_t count)
-+{
-+ g_dbg_lvl = simple_strtoul(buf, NULL, 16);
-+ return count;
-+}
-+static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store);
-+
-+/**
-+ * This function is called during module intialization to verify that
-+ * the module parameters are in a valid state.
-+ */
-+static int check_parameters(dwc_otg_core_if_t *core_if)
-+{
-+ int i;
-+ int retval = 0;
-+
-+/* Checks if the parameter is outside of its valid range of values */
-+#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
-+ ((dwc_otg_module_params._param_ < (_low_)) || \
-+ (dwc_otg_module_params._param_ > (_high_)))
-+
-+/* If the parameter has been set by the user, check that the parameter value is
-+ * within the value range of values. If not, report a module error. */
-+#define DWC_OTG_PARAM_ERR(_param_, _low_, _high_, _string_) \
-+ do { \
-+ if (dwc_otg_module_params._param_ != -1) { \
-+ if (DWC_OTG_PARAM_TEST(_param_, (_low_), (_high_))) { \
-+ DWC_ERROR("`%d' invalid for parameter `%s'\n", \
-+ dwc_otg_module_params._param_, _string_); \
-+ dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
-+ retval++; \
-+ } \
-+ } \
-+ } while (0)
-+
-+ DWC_OTG_PARAM_ERR(opt,0,1,"opt");
-+ DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap");
-+ DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable");
-+ DWC_OTG_PARAM_ERR(dma_desc_enable,0,1,"dma_desc_enable");
-+ DWC_OTG_PARAM_ERR(speed,0,1,"speed");
-+ DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power");
-+ DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk");
-+ DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo");
-+ DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size");
-+ DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size");
-+ DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size");
-+ DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size");
-+ DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size");
-+ DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size");
-+ DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size");
-+ DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count");
-+ DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels");
-+ DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints");
-+ DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type");
-+ DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr");
-+ DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus");
-+ DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable");
-+ DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls");
-+ DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline");
-+
-+ if (dwc_otg_module_params.dma_burst_size != -1) {
-+ if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) &&
-+ DWC_OTG_PARAM_TEST(dma_burst_size,4,4) &&
-+ DWC_OTG_PARAM_TEST(dma_burst_size,8,8) &&
-+ DWC_OTG_PARAM_TEST(dma_burst_size,16,16) &&
-+ DWC_OTG_PARAM_TEST(dma_burst_size,32,32) &&
-+ DWC_OTG_PARAM_TEST(dma_burst_size,64,64) &&
-+ DWC_OTG_PARAM_TEST(dma_burst_size,128,128) &&
-+ DWC_OTG_PARAM_TEST(dma_burst_size,256,256)) {
-+ DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
-+ dwc_otg_module_params.dma_burst_size);
-+ dwc_otg_module_params.dma_burst_size = 32;
-+ retval++;
-+ }
-+
-+ {
-+ uint8_t brst_sz = 0;
-+ while(dwc_otg_module_params.dma_burst_size > 1) {
-+ brst_sz ++;
-+ dwc_otg_module_params.dma_burst_size >>= 1;
-+ }
-+ dwc_otg_module_params.dma_burst_size = brst_sz;
-+ }
-+ }
-+
-+ if (dwc_otg_module_params.phy_utmi_width != -1) {
-+ if (DWC_OTG_PARAM_TEST(phy_utmi_width, 8, 8) &&
projects / openwrt / openwrt.git / commitdiff