ralink: fix rcu_sched stalls on mt7621
authorJohn Crispin <john@phrozen.org>
Tue, 25 Jul 2017 12:46:01 +0000 (14:46 +0200)
committerJohn Crispin <john@phrozen.org>
Wed, 26 Jul 2017 07:14:20 +0000 (09:14 +0200)
there were 2 bugs
*) core1 came up with a bad bogo mips, looks like the clock needed time to stabilize
*) HPT frequency was not set making r4k timers not come up properly

Signed-off-by: John Crispin <john@phrozen.org>
target/linux/ramips/dts/mt7621.dtsi
target/linux/ramips/patches-4.9/101-mt7621-timer.patch [new file with mode: 0644]

index 6b95c54..7662518 100644 (file)
@@ -42,6 +42,8 @@
                clock-frequency = <50000000>;
        };
 
+
+
        palmbus: palmbus@1E000000 {
                compatible = "palmbus";
                reg = <0x1E000000 0x100000>;
                        status = "disabled";
                };
 
+               systick: systick@d00 {
+                       compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
+                       reg = <0xd00 0x10>;
+
+                       resets = <&rstctrl 28>;
+                       reset-names = "intc";
+
+                       interrupt-parent = <&gic>;
+                       interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
                memc: memc@5000 {
                        compatible = "mtk,mt7621-memc";
                        reg = <0x300 0x100>;
diff --git a/target/linux/ramips/patches-4.9/101-mt7621-timer.patch b/target/linux/ramips/patches-4.9/101-mt7621-timer.patch
new file mode 100644 (file)
index 0000000..ca90f5d
--- /dev/null
@@ -0,0 +1,119 @@
+Index: linux-4.9.37/arch/mips/kernel/smp-cmp.c
+===================================================================
+--- linux-4.9.37.orig/arch/mips/kernel/smp-cmp.c
++++ linux-4.9.37/arch/mips/kernel/smp-cmp.c
+@@ -43,6 +43,10 @@ static void cmp_init_secondary(void)
+ {
+       struct cpuinfo_mips *c __maybe_unused = &current_cpu_data;
++      printk("%s:%s[%d]%x\n", __FILE__, __func__, __LINE__, c->core);
++      c->core = (read_c0_ebase() & 0x3ff) >> (fls(smp_num_siblings)-1);
++      printk("%s:%s[%d]%x\n", __FILE__, __func__, __LINE__, c->core);
++
+       /* Assume GIC is present */
+       change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
+                                STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
+Index: linux-4.9.37/arch/mips/ralink/mt7621.c
+===================================================================
+--- linux-4.9.37.orig/arch/mips/ralink/mt7621.c
++++ linux-4.9.37/arch/mips/ralink/mt7621.c
+@@ -18,6 +18,7 @@
+ #include <asm/mach-ralink/ralink_regs.h>
+ #include <asm/mach-ralink/mt7621.h>
+ #include <asm/mips-boards/launch.h>
++#include <asm/delay.h>
+ #include <pinmux.h>
+@@ -179,6 +180,58 @@ bool plat_cpu_core_present(int core)
+       return true;
+ }
++#define LPS_PREC 8
++/*
++*  Re-calibration lpj(loop-per-jiffy).
++*  (derived from kernel/calibrate.c)
++*/
++static int udelay_recal(void)
++{
++      unsigned int i, lpj = 0;
++      unsigned long ticks, loopbit;
++      int lps_precision = LPS_PREC;
++
++      lpj = (1<<12);
++
++      while ((lpj <<= 1) != 0) {
++              /* wait for "start of" clock tick */
++              ticks = jiffies;
++              while (ticks == jiffies)
++                      /* nothing */;
++
++              /* Go .. */
++              ticks = jiffies;
++              __delay(lpj);
++              ticks = jiffies - ticks;
++              if (ticks)
++                      break;
++      }
++
++      /*
++       * Do a binary approximation to get lpj set to
++       * equal one clock (up to lps_precision bits)
++       */
++      lpj >>= 1;
++      loopbit = lpj;
++      while (lps_precision-- && (loopbit >>= 1)) {
++              lpj |= loopbit;
++              ticks = jiffies;
++              while (ticks == jiffies)
++                      /* nothing */;
++              ticks = jiffies;
++              __delay(lpj);
++              if (jiffies != ticks)   /* longer than 1 tick */
++                      lpj &= ~loopbit;
++      }
++      printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj);
++
++      for(i=0; i< NR_CPUS; i++)
++              cpu_data[i].udelay_val = lpj;
++
++      return 0;
++}
++device_initcall(udelay_recal);
++
+ void prom_soc_init(struct ralink_soc_info *soc_info)
+ {
+       void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
+Index: linux-4.9.37/arch/mips/ralink/Kconfig
+===================================================================
+--- linux-4.9.37.orig/arch/mips/ralink/Kconfig
++++ linux-4.9.37/arch/mips/ralink/Kconfig
+@@ -56,6 +56,7 @@ choice
+               select COMMON_CLK
+               select CLKSRC_MIPS_GIC
+               select HW_HAS_PCI
++              select GENERIC_CLOCKEVENTS_BROADCAST
+ endchoice
+ choice
+Index: linux-4.9.37/arch/mips/ralink/timer-gic.c
+===================================================================
+--- linux-4.9.37.orig/arch/mips/ralink/timer-gic.c
++++ linux-4.9.37/arch/mips/ralink/timer-gic.c
+@@ -12,6 +12,7 @@
+ #include <linux/of.h>
+ #include <linux/clk-provider.h>
+ #include <linux/clocksource.h>
++#include <asm/time.h>
+ #include "common.h"
+@@ -19,6 +20,8 @@ void __init plat_time_init(void)
+ {
+       ralink_of_remap();
++      mips_hpt_frequency = 880000000 / 2;
++
+       of_clk_init(NULL);
+       clocksource_probe();
+ }