ar71xx: add kernel support for dir-825-c1
authorGabor Juhos <juhosg@openwrt.org>
Tue, 29 Jan 2013 22:50:50 +0000 (22:50 +0000)
committerGabor Juhos <juhosg@openwrt.org>
Tue, 29 Jan 2013 22:50:50 +0000 (22:50 +0000)
[juhosg:
 - remove unused GPIO stuff
 - use a separate kernel patch for machine integration]

Signed-off-by: Alexander Stadler <sa.maillists@univie.ac.at>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 35401

target/linux/ar71xx/config-3.7
target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-c1.c [new file with mode: 0644]
target/linux/ar71xx/patches-3.7/612-MIPS-ath79-add-DIR-825-C1-support.patch [new file with mode: 0644]

index e396dfb..11498c5 100644 (file)
@@ -39,6 +39,7 @@ CONFIG_ATH79_MACH_DB120=y
 CONFIG_ATH79_MACH_DIR_600_A1=y
 CONFIG_ATH79_MACH_DIR_615_C1=y
 CONFIG_ATH79_MACH_DIR_825_B1=y
+CONFIG_ATH79_MACH_DIR_825_C1=y
 CONFIG_ATH79_MACH_EAP7660D=y
 CONFIG_ATH79_MACH_EW_DORIN=y
 CONFIG_ATH79_MACH_HORNET_UB=y
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-c1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-c1.c
new file mode 100644 (file)
index 0000000..4d140bb
--- /dev/null
@@ -0,0 +1,189 @@
+/*
+ *  D-Link DIR-825 rev. C1 board support
+ *
+ *  Copyright (C) 2013 Alexander Stadler
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+#include <linux/phy.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/ath9k_platform.h>
+#include <linux/ar8216_platform.h>
+
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+#include "common.h"
+#include "dev-ap9x-pci.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-spi.h"
+#include "dev-usb.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define DIR825C1_GPIO_LED_BLUE_USB             11
+#define DIR825C1_GPIO_LED_ORANGE_POWER         15
+#define DIR825C1_GPIO_LED_BLUE_POWER           14
+#define DIR825C1_GPIO_LED_ORANGE_PLANET                19
+#define DIR825C1_GPIO_LED_BLUE_PLANET          18
+
+#define DIR825C1_GPIO_BTN_RESET                        17
+#define DIR825C1_GPIO_BTN_WPS                  16
+
+
+#define DIR825C1_KEYS_POLL_INTERVAL    20      /* msecs */
+#define DIR825C1_KEYS_DEBOUNCE_INTERVAL        (3 * DIR825C1_KEYS_POLL_INTERVAL)
+
+#define DIR825C1_MAC0_OFFSET             0x4
+#define DIR825C1_MAC1_OFFSET             0x18
+#define DIR825C1_WMAC_CALDATA_OFFSET     0x1000
+#define DIR825C1_PCIE_CALDATA_OFFSET     0x5000
+
+static struct gpio_led dir825c1_leds_gpio[] __initdata = {
+       {
+               .name           = "d-link:blue:usb",
+               .gpio           = DIR825C1_GPIO_LED_BLUE_USB,
+               .active_low     = 1,
+       }, {
+               .name           = "d-link:orange:power",
+               .gpio           = DIR825C1_GPIO_LED_ORANGE_POWER,
+               .active_low     = 1,
+       }, {
+               .name           = "d-link:blue:power",
+               .gpio           = DIR825C1_GPIO_LED_BLUE_POWER,
+               .active_low     = 1,
+       }, {
+               .name           = "d-link:orange:planet",
+               .gpio           = DIR825C1_GPIO_LED_ORANGE_PLANET,
+               .active_low     = 1,
+       }, {
+               .name           = "d-link:blue:planet",
+               .gpio           = DIR825C1_GPIO_LED_BLUE_PLANET,
+               .active_low     = 1,
+       }
+};
+
+static struct gpio_keys_button dir825c1_gpio_keys[] __initdata = {
+       {
+               .desc           = "reset",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = DIR825C1_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = DIR825C1_GPIO_BTN_RESET,
+               .active_low     = 1,
+       }, {
+               .desc           = "wps",
+               .type           = EV_KEY,
+               .code           = KEY_WPS_BUTTON,
+               .debounce_interval = DIR825C1_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = DIR825C1_GPIO_BTN_WPS,
+               .active_low     = 1,
+       }
+};
+
+static struct ar8327_pad_cfg dir825c1_ar8327_pad0_cfg = {
+       .mode = AR8327_PAD_MAC_RGMII,
+       .txclk_delay_en = true,
+       .rxclk_delay_en = true,
+       .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
+       .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
+};
+
+static struct ar8327_led_cfg dir825c1_ar8327_led_cfg = {
+       .led_ctrl0 = 0xc737c737,
+       .led_ctrl1 = 0x00000000,
+       .led_ctrl2 = 0x00000000,
+       .led_ctrl3 = 0x0030c300,
+       .open_drain = false,
+};
+
+static struct ar8327_platform_data dir825c1_ar8327_data = {
+       .pad0_cfg = &dir825c1_ar8327_pad0_cfg,
+       .port0_cfg = {
+               .force_link = 1,
+               .speed = AR8327_PORT_SPEED_1000,
+               .duplex = 1,
+               .txpause = 1,
+               .rxpause = 1,
+       },
+       .led_cfg = &dir825c1_ar8327_led_cfg,
+};
+
+static struct mdio_board_info dir825c1_mdio0_info[] = {
+       {
+               .bus_id = "ag71xx-mdio.0",
+               .phy_addr = 0,
+               .platform_data = &dir825c1_ar8327_data,
+       },
+};
+
+static void dir825c1_read_ascii_mac(u8 *dest, u8 *src)
+{
+       int ret;
+
+       ret = sscanf(src, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+                    &dest[0], &dest[1], &dest[2],
+                    &dest[3], &dest[4], &dest[5]);
+
+       if (ret != ETH_ALEN)
+               memset(dest, 0, ETH_ALEN);
+}
+
+static void __init dir825c1_setup(void)
+{
+       u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000);
+       u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+       u8 tmpmac[ETH_ALEN];
+       u8 mac1[ETH_ALEN], mac2[ETH_ALEN];
+
+       dir825c1_read_ascii_mac(mac1, mac + DIR825C1_MAC0_OFFSET);
+       dir825c1_read_ascii_mac(mac2, mac + DIR825C1_MAC1_OFFSET);
+
+       ath79_gpio_output_select(DIR825C1_GPIO_LED_BLUE_USB, AR934X_GPIO_OUT_GPIO);
+
+       ath79_register_m25p80(NULL);
+
+       ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825c1_leds_gpio),
+                                dir825c1_leds_gpio);
+       ath79_register_gpio_keys_polled(-1, DIR825C1_KEYS_POLL_INTERVAL,
+                                       ARRAY_SIZE(dir825c1_gpio_keys),
+                                       dir825c1_gpio_keys);
+
+       ap9x_pci_setup_wmac_led_pin(0, 13);
+       ap9x_pci_setup_wmac_led_pin(1, 32);
+
+       ath79_init_mac(tmpmac, mac1, 0);
+       ath79_register_wmac(art + DIR825C1_WMAC_CALDATA_OFFSET, tmpmac);
+
+       ath79_init_mac(tmpmac, mac2, 0);
+       ap91_pci_init(art + DIR825C1_PCIE_CALDATA_OFFSET, tmpmac);
+
+       ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
+
+       mdiobus_register_board_info(dir825c1_mdio0_info,
+                                   ARRAY_SIZE(dir825c1_mdio0_info));
+
+       ath79_register_mdio(0, 0x0);
+
+       ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
+
+       /* GMAC0 is connected to an AR8327N switch */
+       ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+       ath79_eth0_data.phy_mask = BIT(0);
+       ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
+       ath79_eth0_pll_data.pll_1000 = 0x06000000;
+       ath79_register_eth(0);
+
+       ath79_register_usb();
+}
+
+MIPS_MACHINE(ATH79_MACH_DIR_825_C1, "DIR-825-C1",
+            "D-Link DIR-825 rev. C1",
+            dir825c1_setup);
diff --git a/target/linux/ar71xx/patches-3.7/612-MIPS-ath79-add-DIR-825-C1-support.patch b/target/linux/ar71xx/patches-3.7/612-MIPS-ath79-add-DIR-825-C1-support.patch
new file mode 100644 (file)
index 0000000..3e6d17f
--- /dev/null
@@ -0,0 +1,40 @@
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -39,6 +39,7 @@ enum ath79_mach_type {
+       ATH79_MACH_DIR_615_C1,          /* D-Link DIR-615 rev. C1 */
+       ATH79_MACH_DIR_615_E4,          /* D-Link DIR-615 rev. E4 */
+       ATH79_MACH_DIR_825_B1,          /* D-Link DIR-825 rev. B1 */
++      ATH79_MACH_DIR_825_C1,          /* D-Link DIR-825 rev. C1 */
+       ATH79_MACH_EW_DORIN,            /* embedded wireless Dorin Platform */
+       ATH79_MACH_EW_DORIN_ROUTER,     /* embedded wireless Dorin Router Platform */
+       ATH79_MACH_EAP7660D,            /* Senao EAP7660D */
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -283,6 +283,17 @@ config ATH79_MACH_DIR_825_B1
+       select ATH79_DEV_M25P80
+       select ATH79_DEV_USB
++config ATH79_MACH_DIR_825_C1
++        bool "D-Link DIR-825 rev. C1 board support"
++        select SOC_AR934X
++        select ATH79_DEV_AP9X_PCI if PCI
++        select ATH79_DEV_ETH
++        select ATH79_DEV_GPIO_BUTTONS
++        select ATH79_DEV_LEDS_GPIO
++        select ATH79_DEV_M25P80
++        select ATH79_DEV_USB
++        select ATH79_DEV_WMAC
++
+ config ATH79_MACH_EW_DORIN
+       bool "embedded wireless Dorin Platform support"
+       select SOC_AR933X
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -55,6 +55,7 @@ obj-$(CONFIG_ATH79_MACH_DB120)               += mach-
+ obj-$(CONFIG_ATH79_MACH_DIR_600_A1)   += mach-dir-600-a1.o
+ obj-$(CONFIG_ATH79_MACH_DIR_615_C1)   += mach-dir-615-c1.o
+ obj-$(CONFIG_ATH79_MACH_DIR_825_B1)   += mach-dir-825-b1.o
++obj-$(CONFIG_ATH79_MACH_DIR_825_C1)   += mach-dir-825-c1.o
+ obj-$(CONFIG_ATH79_MACH_EW_DORIN)     += mach-ew-dorin.o
+ obj-$(CONFIG_ATH79_MACH_EAP7660D)     += mach-eap7660d.o
+ obj-$(CONFIG_ATH79_MACH_JA76PF)               += mach-ja76pf.o