ar8216: rework/fix AR8337 MAC swap handling
authorFelix Fietkau <nbd@openwrt.org>
Sun, 20 Dec 2015 14:25:45 +0000 (14:25 +0000)
committerFelix Fietkau <nbd@openwrt.org>
Sun, 20 Dec 2015 14:25:45 +0000 (14:25 +0000)
In r45970 the MAC swap handling was made opt-in, however some boards
have been forgotten during the conversion. Since the reference design
uses this MAC swapping, and pretty much all known boards using this chip
seem to do so too, enabling the swapping is a more reasonable default
than leaving it disabled.

Change the code to still allow boards to opt-out of this.

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 47956

target/linux/ar71xx/files/arch/mips/ath79/mach-epg5000.c
target/linux/ar71xx/files/arch/mips/ath79/mach-esr1750.c
target/linux/ar71xx/files/arch/mips/ath79/mach-f9k1115v2.c
target/linux/ar71xx/files/arch/mips/ath79/mach-nbg6716.c
target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c
target/linux/generic/files/drivers/net/phy/ar8327.c
target/linux/generic/files/include/linux/ar8216_platform.h

index b049f5d692c6df41ff6abbdb80e67db951513571..3d60afc4083acc7c74a1102fb9346af4f43b0378 100644 (file)
@@ -98,7 +98,6 @@ static struct ar8327_pad_cfg epg5000_ar8327_pad0_cfg = {
        .rxclk_delay_en = true,
        .txclk_delay_sel = AR8327_CLK_DELAY_SEL2,
        .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
-       .mac06_exchange_en = true,
 };
 
 static struct ar8327_platform_data epg5000_ar8327_data = {
index d2bc177d73d3f60d719f26376c57d6b25ff2899e..2a34b3a2e9ee966a0170aaa04f08e6bc971e2416 100644 (file)
@@ -97,7 +97,6 @@ static struct ar8327_pad_cfg esr1750_ar8327_pad0_cfg = {
        .rxclk_delay_en = true,
        .txclk_delay_sel = AR8327_CLK_DELAY_SEL2,
        .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
-       .mac06_exchange_en = true,
 };
 
 static struct ar8327_platform_data esr1750_ar8327_data = {
index 9e86e9ab3b8c2fbf6f4686b8a5410131b9d84811..69d005d795a43ae18a1bb68736f84c7898d51b1e 100644 (file)
@@ -98,7 +98,6 @@ static struct ar8327_pad_cfg f9k1115v2_ar8327_pad0_cfg = {
        .rxclk_delay_en = true,
        .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
        .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
-       .mac06_exchange_en = true,
 };
 
 static struct ar8327_pad_cfg f9k1115v2_ar8327_pad6_cfg = {
index 73e11f194585f8d7cef77c76950ea20b22bdbee2..c28a8a511875a51a3bac1914f8ec39007e4e4311 100644 (file)
@@ -320,7 +320,6 @@ static void __init nbg6716_010_setup(void)
        nbg6716_ar8327_pad0_cfg.rxclk_delay_en = true;
        nbg6716_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
        nbg6716_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
-       nbg6716_ar8327_pad0_cfg.mac06_exchange_en = true;
 
        /* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */
        nbg6716_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
index 6a90c6ecb3f882d8f8d2c7dcd29455f5866a3c3e..88022e7533f12e89c05d0db0f4cafef78a700947 100644 (file)
@@ -186,7 +186,6 @@ static void __init wlr8100_010_setup(void)
        wlr8100_ar8327_pad0_cfg.rxclk_delay_en = true;
        wlr8100_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
        wlr8100_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
-       wlr8100_ar8327_pad0_cfg.mac06_exchange_en = true;
 
        /* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */
        wlr8100_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
index 1802b9ead7e8e16bfb37e0d24491f9ea5ceed7e4..90ee4115c02e337d067ad0d4292a03cab122e999 100644 (file)
@@ -124,9 +124,6 @@ ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
                break;
        }
 
-       if (cfg->mac06_exchange_en)
-               t |= AR8337_PAD_MAC06_EXCHANGE_EN;
-
        return t;
 }
 
@@ -511,7 +508,10 @@ ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
        data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
 
        t = ar8327_get_pad_cfg(pdata->pad0_cfg);
+       if (chip_is_ar8337(priv) && !pdata->pad0_cfg->mac06_exchange_dis)
+           t |= AR8337_PAD_MAC06_EXCHANGE_EN;
        ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);
+
        t = ar8327_get_pad_cfg(pdata->pad5_cfg);
        ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t);
        t = ar8327_get_pad_cfg(pdata->pad6_cfg);
index d70f11a843aa6014601426eb3a013865175871ac..24bc442a26d0ced7a5b686846dfc53f14f7ded37 100644 (file)
@@ -47,7 +47,7 @@ struct ar8327_pad_cfg {
        bool sgmii_delay_en;
        enum ar8327_clk_delay_sel txclk_delay_sel;
        enum ar8327_clk_delay_sel rxclk_delay_sel;
-       bool mac06_exchange_en;
+       bool mac06_exchange_dis;
 };
 
 enum ar8327_port_speed {