ipq806x: force 2nd pci slot into gen1 mode
authorPavel Kubelun <be.dissent@gmail.com>
Thu, 6 Jul 2017 14:20:18 +0000 (17:20 +0300)
committerFelix Fietkau <nbd@nbd.name>
Wed, 17 Jan 2018 10:02:05 +0000 (11:02 +0100)
According to QSDK and OEM tarballs (checked c2600, r7500v2, r7800) 2nd pci slot (pci1, 2,4 GHz card)) on ap148 based boards should operate in gen1 mode.
EA8500 is an exception and according to GPL pcie0 should operate in gen1 mode.

In previous commit we've added the support for this option, so enable it in DT for affected devices.

QSDK ref:
https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/commit/?h=release/endive_preview_cc&id=f3b07fe309027c52fc163149500cedddd707c506

While at it move the phy transmit termination offset value into dtsi file as it's platform specific.

Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-c2600.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064.dtsi
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-r7800.dts

index fa4f05b..39a0d96 100644 (file)
 
                pcie0: pci@1b500000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
                };
 
                pcie1: pci@1b700000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
+                       force_gen1 = <1>;
                };
 
                nand@1ac00000 {
index 80bc5df..a4fd134 100644 (file)
 
                pcie0: pci@1b500000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
                };
 
                pcie1: pci@1b700000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
+                       force_gen1 = <1>;
                };
 
                mdio0: mdio {
index c1a4c82..b7c49cc 100644 (file)
                        reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
                        pinctrl-0 = <&pcie1_pins>;
                        pinctrl-names = "default";
+                       force_gen1 = <1>;
                };
 
                nand@1ac00000 {
index 761fa43..a8628ff 100644 (file)
 
                pcie0: pci@1b500000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
+                       force_gen1 = <1>;
                };
 
                pcie1: pci@1b700000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
                };
-               
+
                pcie2: pci@1b900000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
                };
-               
+
                nand@1ac00000 {
                        status = "ok";
 
index 2ea856d..3445a79 100644 (file)
 
                pcie1: pci@1b700000 {
                        status = "ok";
+                       force_gen1 = <1>;
                };
 
                nand@1ac00000 {
index a21cf18..c4b0c4b 100644 (file)
                        reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
                        pinctrl-0 = <&pcie1_pins>;
                        pinctrl-names = "default";
+                       force_gen1 = <1>;
                };
 
                nand@1ac00000 {
index b55a98d..561c49a 100644 (file)
 
                pcie0: pci@1b500000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
                };
 
                pcie1: pci@1b700000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
+                       force_gen1 = <1>;
                };
 
                mdio0: mdio {
index 9996bd7..4b93fea 100644 (file)
 
                        perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
 
+                       phy-tx0-term-offset = <7>;
+
                        status = "disabled";
                };
 
 
                        perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
 
+                       phy-tx0-term-offset = <7>;
+
                        status = "disabled";
                };
 
 
                        perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
 
+                       phy-tx0-term-offset = <7>;
+
                        status = "disabled";
                };
 
index 15165b9..987ee85 100644 (file)
                        reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
                        pinctrl-0 = <&pcie1_pins>;
                        pinctrl-names = "default";
+                       force_gen1 = <1>;
                };
 
                mdio0: mdio {
index 403054c..4c89dcf 100644 (file)
 
                pcie0: pci@1b500000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
                };
 
                pcie1: pci@1b700000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
+                       force_gen1 = <1>;
                };
 
                nand@1ac00000 {