ipq806x: fix pcie tx termination offset

According to GPL tarballs and QSDK related branch tx termination
offset for ipq8064 SoC version >= 2.0 should be equal to 0 and
not 7.

https://github.com/paul-chambers/netgear-r7800/blob/master/git_home/linux.git/sourcecode/arch/arm/mach-msm/board-ipq806x.c#L1682-L1685

Fix this.

Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
[slh: rebase for kernel v4.14 as well]
Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
(cherry picked from commit fbedc2213c19023bb4ec4ed7bd71908501aaf6d1)

diff --git a/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
index 5a40b03eefdea869683d65e2a2ee77b248c87f4d..8c522a897d42573eaeb2cdd424a7f1a0f39dc9b2 100644 (file)
--- a/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
+++ b/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
@@ -14,5 +14,17 @@
                        tx_deamp_3_5db = <32>;
                        mpll = <0xa0>;
                };
                        tx_deamp_3_5db = <32>;
                        mpll = <0xa0>;
                };

+
+               pcie0: pci@1b500000 {
+                       phy-tx0-term-offset = <0>;
+               };
+
+               pcie1: pci@1b700000 {
+                       phy-tx0-term-offset = <0>;
+               };
+
+               pcie2: pci@1b900000 {
+                       phy-tx0-term-offset = <0>;
+               };

        };
 };
        };
 };

diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
index 5a40b03eefdea869683d65e2a2ee77b248c87f4d..8c522a897d42573eaeb2cdd424a7f1a0f39dc9b2 100644 (file)
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
+++ b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
@@ -14,5 +14,17 @@
                        tx_deamp_3_5db = <32>;
                        mpll = <0xa0>;
                };
                        tx_deamp_3_5db = <32>;
                        mpll = <0xa0>;
                };

+
+               pcie0: pci@1b500000 {
+                       phy-tx0-term-offset = <0>;
+               };
+
+               pcie1: pci@1b700000 {
+                       phy-tx0-term-offset = <0>;
+               };
+
+               pcie2: pci@1b900000 {
+                       phy-tx0-term-offset = <0>;
+               };

        };
 };
        };
 };