ar71xx: add more registers to ar71x_regs.h
authorJulien Dusser <julien.dusser@free.fr>
Wed, 20 Dec 2017 14:29:42 +0000 (15:29 +0100)
committerJohn Crispin <john@phrozen.org>
Tue, 13 Feb 2018 10:20:58 +0000 (11:20 +0100)
Add more registers and flags to ar71x_regs.h for QCA955x and QCA956x
SoCs. Values come from Qualcomm Atheros u-boot code.

Patches can be merged into
622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch

Signed-off-by: Julien Dusser <julien.dusser@free.fr>
target/linux/ar71xx/files/arch/mips/ath79/mach-mr18.c
target/linux/ar71xx/patches-4.4/921-MIPS-ath79-add-even-more-register-defines-for-QCA956x-SoC.patch [new file with mode: 0644]
target/linux/ar71xx/patches-4.9/921-MIPS-ath79-add-even-more-register-defines-for-QCA956x-SoC.patch [new file with mode: 0644]

index a24cb3f..2d2fb6e 100644 (file)
@@ -168,17 +168,6 @@ static int mr18_extract_sgmii_res_cal(void)
        return reversed_sgmii_value;
 }
 
-#define QCA955X_PLL_ETH_SGMII_SERDES_REG               0x004c
-#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT       BIT(2)
-#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK                BIT(1)
-#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL            BIT(0)
-
-#define QCA955X_GMAC_REG_SGMII_SERDES                  0x0018
-#define QCA955X_SGMII_SERDES_RES_CALIBRATION           BIT(23)
-#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK      0xf
-#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT     23
-#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS                BIT(15)
-
 static void mr18_setup_qca955x_eth_serdes_cal(unsigned int sgmii_value)
 {
        void __iomem *ethbase, *pllbase;
diff --git a/target/linux/ar71xx/patches-4.4/921-MIPS-ath79-add-even-more-register-defines-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.4/921-MIPS-ath79-add-even-more-register-defines-for-QCA956x-SoC.patch
new file mode 100644 (file)
index 0000000..a4608ea
--- /dev/null
@@ -0,0 +1,194 @@
+Add more registers for QCA955x and QCA956x.
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -175,6 +175,35 @@
+ /*
+  * Hidden Registers
+  */
++#define QCA956X_MAC_CFG_BASE          0xb9000000
++#define QCA956X_MAC_CFG_SIZE          0x64
++
++#define QCA956X_MAC_CFG1_REG          0x00
++#define QCA956X_MAC_CFG1_SOFT_RST     BIT(31)
++#define QCA956X_MAC_CFG1_RX_RST               BIT(19)
++#define QCA956X_MAC_CFG1_TX_RST               BIT(18)
++#define QCA956X_MAC_CFG1_LOOPBACK     BIT(8)
++#define QCA956X_MAC_CFG1_RX_EN                BIT(2)
++#define QCA956X_MAC_CFG1_TX_EN                BIT(0)
++
++#define QCA956X_MAC_CFG2_REG          0x04
++#define QCA956X_MAC_CFG2_IF_1000      BIT(9)
++#define QCA956X_MAC_CFG2_IF_10_100    BIT(8)
++#define QCA956X_MAC_CFG2_HUGE_FRAME_EN        BIT(5)
++#define QCA956X_MAC_CFG2_LEN_CHECK    BIT(4)
++#define QCA956X_MAC_CFG2_PAD_CRC_EN   BIT(2)
++#define QCA956X_MAC_CFG2_FDX          BIT(0)
++
++#define QCA956X_MAC_MII_MGMT_CFG_REG  0x20
++#define QCA956X_MGMT_CFG_CLK_DIV_20   0x07
++
++#define QCA956X_MAC_FIFO_CFG0_REG     0x48
++#define QCA956X_MAC_FIFO_CFG1_REG     0x4c
++#define QCA956X_MAC_FIFO_CFG2_REG     0x50
++#define QCA956X_MAC_FIFO_CFG3_REG     0x54
++#define QCA956X_MAC_FIFO_CFG4_REG     0x58
++#define QCA956X_MAC_FIFO_CFG5_REG     0x5c
++
+ #define QCA956X_DAM_RESET_OFFSET      0xb90001bc
+ #define QCA956X_DAM_RESET_SIZE                0x4
+ #define QCA956X_INLINE_CHKSUM_ENG     BIT(27)
+@@ -384,6 +413,7 @@
+ #define QCA955X_PLL_CLK_CTRL_REG              0x08
+ #define QCA955X_PLL_ETH_XMII_CONTROL_REG      0x28
+ #define QCA955X_PLL_ETH_SGMII_CONTROL_REG     0x48
++#define QCA955X_PLL_ETH_SGMII_SERDES_REG      0x4c
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT    0
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK     0x3f
+@@ -416,12 +446,18 @@
+ #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL               BIT(21)
+ #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL               BIT(24)
++#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT      BIT(2)
++#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK               BIT(1)
++#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL           BIT(0)
++
+ #define QCA956X_PLL_CPU_CONFIG_REG                    0x00
+ #define QCA956X_PLL_CPU_CONFIG1_REG                   0x04
+ #define QCA956X_PLL_DDR_CONFIG_REG                    0x08
+ #define QCA956X_PLL_DDR_CONFIG1_REG                   0x0c
+ #define QCA956X_PLL_CLK_CTRL_REG                      0x10
++#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG          0x28
+ #define QCA956X_PLL_ETH_XMII_CONTROL_REG              0x30
++#define QCA956X_PLL_ETH_SGMII_SERDES_REG              0x4c
+ #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT           12
+ #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK            0x1f
+@@ -460,6 +496,31 @@
+ #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL   BIT(21)
+ #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL               BIT(24)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB           BIT(5)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1                BIT(6)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL          BIT(7)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SHIFT 8
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK        0xf
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP             BIT(12)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2                BIT(13)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1                BIT(14)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2                BIT(15)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE   BIT(16)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE             BIT(17)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL                BIT(18)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL          BIT(19)
++
++#define QCA956X_PLL_ETH_XMII_TX_INVERT                        BIT(1)
++#define QCA956X_PLL_ETH_XMII_GIGE                     BIT(25)
++#define QCA956X_PLL_ETH_XMII_RX_DELAY_SHIFT           28
++#define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK            0x3
++#define QCA956X_PLL_ETH_XMII_TX_DELAY_SHIFT           26
++#define QCA956X_PLL_ETH_XMII_TX_DELAY_MASK            3
++
++#define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT              BIT(2)
++#define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK                       BIT(1)
++#define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL                   BIT(0)
++
+ /*
+  * USB_CONFIG block
+  */
+@@ -657,6 +718,25 @@
+ #define QCA955X_RESET_MBOX            BIT(1)
+ #define QCA955X_RESET_I2S             BIT(0)
++#define QCA956X_RESET_EXTERNAL                BIT(28)
++#define QCA956X_RESET_FULL_CHIP               BIT(24)
++#define QCA956X_RESET_GE1_MDIO                BIT(23)
++#define QCA956X_RESET_GE0_MDIO                BIT(22)
++#define QCA956X_RESET_CPU_NMI         BIT(21)
++#define QCA956X_RESET_CPU_COLD                BIT(20)
++#define QCA956X_RESET_DMA             BIT(19)
++#define QCA956X_RESET_DDR             BIT(16)
++#define QCA956X_RESET_GE1_MAC         BIT(13)
++#define QCA956X_RESET_SGMII_ANALOG    BIT(12)
++#define QCA956X_RESET_USB_PHY_ANALOG  BIT(11)
++#define QCA956X_RESET_GE0_MAC         BIT(9)
++#define QCA956X_RESET_SGMII           BIT(8)
++#define QCA956X_RESET_USB_HOST                BIT(5)
++#define QCA956X_RESET_USB_PHY         BIT(4)
++#define QCA956X_RESET_USBSUS_OVERRIDE BIT(3)
++#define QCA956X_RESET_SWITCH_ANALOG   BIT(2)
++#define QCA956X_RESET_SWITCH          BIT(0)
++
+ #define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
+ #define AR933X_BOOTSTRAP_EEPBUSY      BIT(4)
+ #define AR933X_BOOTSTRAP_USB_MODE_HOST        BIT(3)
+@@ -1189,6 +1269,7 @@
+  */
+ #define QCA955X_GMAC_REG_ETH_CFG      0x00
++#define QCA955X_GMAC_REG_SGMII_SERDES 0x18
+ #define QCA955X_ETH_CFG_RGMII_EN      BIT(0)
+ #define QCA955X_ETH_CFG_MII_GE0               BIT(1)
+@@ -1210,16 +1291,58 @@
+ #define QCA955X_ETH_CFG_TXE_DELAY_MASK        0x3
+ #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT       20
++#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS       BIT(15)
++#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
++#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
+ /*
+  * QCA956X GMAC Interface
+  */
+-#define QCA956X_GMAC_REG_ETH_CFG              0x00
++#define QCA956X_GMAC_REG_ETH_CFG      0x00
++#define QCA956X_GMAC_REG_SGMII_RESET  0x14
++#define QCA956X_GMAC_REG_SGMII_SERDES 0x18
++#define QCA956X_GMAC_REG_MR_AN_CONTROL        0x1c
++#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34
++#define QCA956X_GMAC_REG_SGMII_DEBUG  0x58
++#define QCA956X_ETH_CFG_RGMII_EN              BIT(0)
++#define QCA956X_ETH_CFG_GE0_SGMII             BIT(6)
+ #define QCA956X_ETH_CFG_SW_ONLY_MODE          BIT(7)
+-#define QCA956X_ETH_CFG_SW_PHY_SWAP               BIT(8)
++#define QCA956X_ETH_CFG_SW_PHY_SWAP           BIT(8)
+ #define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP      BIT(9)
+ #define QCA956X_ETH_CFG_SW_APB_ACCESS         BIT(10)
+ #define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST      BIT(13)
++#define QCA956X_ETH_CFG_RXD_DELAY_MASK                0x3
++#define QCA956X_ETH_CFG_RXD_DELAY_SHIFT               14
++#define QCA956X_ETH_CFG_RDV_DELAY_MASK                0x3
++#define QCA956X_ETH_CFG_RDV_DELAY_SHIFT               16
++
++#define QCA956X_SGMII_RESET_RX_CLK_N_RESET    0x0
++#define QCA956X_SGMII_RESET_RX_CLK_N          BIT(0)
++#define QCA956X_SGMII_RESET_TX_CLK_N          BIT(1)
++#define QCA956X_SGMII_RESET_RX_125M_N         BIT(2)
++#define QCA956X_SGMII_RESET_TX_125M_N         BIT(3)
++#define QCA956X_SGMII_RESET_HW_RX_125M_N      BIT(4)
++
++#define QCA956X_SGMII_SERDES_CDR_BW_MASK      0x3
++#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT     1
++#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK  0x7
++#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4
++#define QCA956X_SGMII_SERDES_PLL_BW           BIT(8)
++#define QCA956X_SGMII_SERDES_VCO_FAST         BIT(9)
++#define QCA956X_SGMII_SERDES_VCO_SLOW         BIT(10)
++#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS       BIT(15)
++#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16)
++#define QCA956X_SGMII_SERDES_FIBER_SDO                BIT(17)
++#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
++#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
++#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT    27
++#define QCA956X_SGMII_SERDES_VCO_REG_MASK     0xf
++
++#define QCA956X_MR_AN_CONTROL_AN_ENABLE               BIT(12)
++#define QCA956X_MR_AN_CONTROL_PHY_RESET               BIT(15)
++
++#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT  0
++#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK   0x7
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/target/linux/ar71xx/patches-4.9/921-MIPS-ath79-add-even-more-register-defines-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.9/921-MIPS-ath79-add-even-more-register-defines-for-QCA956x-SoC.patch
new file mode 100644 (file)
index 0000000..a4608ea
--- /dev/null
@@ -0,0 +1,194 @@
+Add more registers for QCA955x and QCA956x.
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -175,6 +175,35 @@
+ /*
+  * Hidden Registers
+  */
++#define QCA956X_MAC_CFG_BASE          0xb9000000
++#define QCA956X_MAC_CFG_SIZE          0x64
++
++#define QCA956X_MAC_CFG1_REG          0x00
++#define QCA956X_MAC_CFG1_SOFT_RST     BIT(31)
++#define QCA956X_MAC_CFG1_RX_RST               BIT(19)
++#define QCA956X_MAC_CFG1_TX_RST               BIT(18)
++#define QCA956X_MAC_CFG1_LOOPBACK     BIT(8)
++#define QCA956X_MAC_CFG1_RX_EN                BIT(2)
++#define QCA956X_MAC_CFG1_TX_EN                BIT(0)
++
++#define QCA956X_MAC_CFG2_REG          0x04
++#define QCA956X_MAC_CFG2_IF_1000      BIT(9)
++#define QCA956X_MAC_CFG2_IF_10_100    BIT(8)
++#define QCA956X_MAC_CFG2_HUGE_FRAME_EN        BIT(5)
++#define QCA956X_MAC_CFG2_LEN_CHECK    BIT(4)
++#define QCA956X_MAC_CFG2_PAD_CRC_EN   BIT(2)
++#define QCA956X_MAC_CFG2_FDX          BIT(0)
++
++#define QCA956X_MAC_MII_MGMT_CFG_REG  0x20
++#define QCA956X_MGMT_CFG_CLK_DIV_20   0x07
++
++#define QCA956X_MAC_FIFO_CFG0_REG     0x48
++#define QCA956X_MAC_FIFO_CFG1_REG     0x4c
++#define QCA956X_MAC_FIFO_CFG2_REG     0x50
++#define QCA956X_MAC_FIFO_CFG3_REG     0x54
++#define QCA956X_MAC_FIFO_CFG4_REG     0x58
++#define QCA956X_MAC_FIFO_CFG5_REG     0x5c
++
+ #define QCA956X_DAM_RESET_OFFSET      0xb90001bc
+ #define QCA956X_DAM_RESET_SIZE                0x4
+ #define QCA956X_INLINE_CHKSUM_ENG     BIT(27)
+@@ -384,6 +413,7 @@
+ #define QCA955X_PLL_CLK_CTRL_REG              0x08
+ #define QCA955X_PLL_ETH_XMII_CONTROL_REG      0x28
+ #define QCA955X_PLL_ETH_SGMII_CONTROL_REG     0x48
++#define QCA955X_PLL_ETH_SGMII_SERDES_REG      0x4c
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT    0
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK     0x3f
+@@ -416,12 +446,18 @@
+ #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL               BIT(21)
+ #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL               BIT(24)
++#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT      BIT(2)
++#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK               BIT(1)
++#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL           BIT(0)
++
+ #define QCA956X_PLL_CPU_CONFIG_REG                    0x00
+ #define QCA956X_PLL_CPU_CONFIG1_REG                   0x04
+ #define QCA956X_PLL_DDR_CONFIG_REG                    0x08
+ #define QCA956X_PLL_DDR_CONFIG1_REG                   0x0c
+ #define QCA956X_PLL_CLK_CTRL_REG                      0x10
++#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG          0x28
+ #define QCA956X_PLL_ETH_XMII_CONTROL_REG              0x30
++#define QCA956X_PLL_ETH_SGMII_SERDES_REG              0x4c
+ #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT           12
+ #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK            0x1f
+@@ -460,6 +496,31 @@
+ #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL   BIT(21)
+ #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL               BIT(24)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB           BIT(5)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1                BIT(6)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL          BIT(7)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SHIFT 8
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK        0xf
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP             BIT(12)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2                BIT(13)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1                BIT(14)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2                BIT(15)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE   BIT(16)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE             BIT(17)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL                BIT(18)
++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL          BIT(19)
++
++#define QCA956X_PLL_ETH_XMII_TX_INVERT                        BIT(1)
++#define QCA956X_PLL_ETH_XMII_GIGE                     BIT(25)
++#define QCA956X_PLL_ETH_XMII_RX_DELAY_SHIFT           28
++#define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK            0x3
++#define QCA956X_PLL_ETH_XMII_TX_DELAY_SHIFT           26
++#define QCA956X_PLL_ETH_XMII_TX_DELAY_MASK            3
++
++#define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT              BIT(2)
++#define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK                       BIT(1)
++#define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL                   BIT(0)
++
+ /*
+  * USB_CONFIG block
+  */
+@@ -657,6 +718,25 @@
+ #define QCA955X_RESET_MBOX            BIT(1)
+ #define QCA955X_RESET_I2S             BIT(0)
++#define QCA956X_RESET_EXTERNAL                BIT(28)
++#define QCA956X_RESET_FULL_CHIP               BIT(24)
++#define QCA956X_RESET_GE1_MDIO                BIT(23)
++#define QCA956X_RESET_GE0_MDIO                BIT(22)
++#define QCA956X_RESET_CPU_NMI         BIT(21)
++#define QCA956X_RESET_CPU_COLD                BIT(20)
++#define QCA956X_RESET_DMA             BIT(19)
++#define QCA956X_RESET_DDR             BIT(16)
++#define QCA956X_RESET_GE1_MAC         BIT(13)
++#define QCA956X_RESET_SGMII_ANALOG    BIT(12)
++#define QCA956X_RESET_USB_PHY_ANALOG  BIT(11)
++#define QCA956X_RESET_GE0_MAC         BIT(9)
++#define QCA956X_RESET_SGMII           BIT(8)
++#define QCA956X_RESET_USB_HOST                BIT(5)
++#define QCA956X_RESET_USB_PHY         BIT(4)
++#define QCA956X_RESET_USBSUS_OVERRIDE BIT(3)
++#define QCA956X_RESET_SWITCH_ANALOG   BIT(2)
++#define QCA956X_RESET_SWITCH          BIT(0)
++
+ #define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
+ #define AR933X_BOOTSTRAP_EEPBUSY      BIT(4)
+ #define AR933X_BOOTSTRAP_USB_MODE_HOST        BIT(3)
+@@ -1189,6 +1269,7 @@
+  */
+ #define QCA955X_GMAC_REG_ETH_CFG      0x00
++#define QCA955X_GMAC_REG_SGMII_SERDES 0x18
+ #define QCA955X_ETH_CFG_RGMII_EN      BIT(0)
+ #define QCA955X_ETH_CFG_MII_GE0               BIT(1)
+@@ -1210,16 +1291,58 @@
+ #define QCA955X_ETH_CFG_TXE_DELAY_MASK        0x3
+ #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT       20
++#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS       BIT(15)
++#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
++#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
+ /*
+  * QCA956X GMAC Interface
+  */
+-#define QCA956X_GMAC_REG_ETH_CFG              0x00
++#define QCA956X_GMAC_REG_ETH_CFG      0x00
++#define QCA956X_GMAC_REG_SGMII_RESET  0x14
++#define QCA956X_GMAC_REG_SGMII_SERDES 0x18
++#define QCA956X_GMAC_REG_MR_AN_CONTROL        0x1c
++#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34
++#define QCA956X_GMAC_REG_SGMII_DEBUG  0x58
++#define QCA956X_ETH_CFG_RGMII_EN              BIT(0)
++#define QCA956X_ETH_CFG_GE0_SGMII             BIT(6)
+ #define QCA956X_ETH_CFG_SW_ONLY_MODE          BIT(7)
+-#define QCA956X_ETH_CFG_SW_PHY_SWAP               BIT(8)
++#define QCA956X_ETH_CFG_SW_PHY_SWAP           BIT(8)
+ #define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP      BIT(9)
+ #define QCA956X_ETH_CFG_SW_APB_ACCESS         BIT(10)
+ #define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST      BIT(13)
++#define QCA956X_ETH_CFG_RXD_DELAY_MASK                0x3
++#define QCA956X_ETH_CFG_RXD_DELAY_SHIFT               14
++#define QCA956X_ETH_CFG_RDV_DELAY_MASK                0x3
++#define QCA956X_ETH_CFG_RDV_DELAY_SHIFT               16
++
++#define QCA956X_SGMII_RESET_RX_CLK_N_RESET    0x0
++#define QCA956X_SGMII_RESET_RX_CLK_N          BIT(0)
++#define QCA956X_SGMII_RESET_TX_CLK_N          BIT(1)
++#define QCA956X_SGMII_RESET_RX_125M_N         BIT(2)
++#define QCA956X_SGMII_RESET_TX_125M_N         BIT(3)
++#define QCA956X_SGMII_RESET_HW_RX_125M_N      BIT(4)
++
++#define QCA956X_SGMII_SERDES_CDR_BW_MASK      0x3
++#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT     1
++#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK  0x7
++#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4
++#define QCA956X_SGMII_SERDES_PLL_BW           BIT(8)
++#define QCA956X_SGMII_SERDES_VCO_FAST         BIT(9)
++#define QCA956X_SGMII_SERDES_VCO_SLOW         BIT(10)
++#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS       BIT(15)
++#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16)
++#define QCA956X_SGMII_SERDES_FIBER_SDO                BIT(17)
++#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
++#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
++#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT    27
++#define QCA956X_SGMII_SERDES_VCO_REG_MASK     0xf
++
++#define QCA956X_MR_AN_CONTROL_AN_ENABLE               BIT(12)
++#define QCA956X_MR_AN_CONTROL_PHY_RESET               BIT(15)
++
++#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT  0
++#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK   0x7
+ #endif /* __ASM_MACH_AR71XX_REGS_H */