include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=ath9k
-PKG_VERSION:=20080731
+PKG_VERSION:=20080803
PKG_RELEASE:=1
include $(INCLUDE_DIR)/package.mk
#endif
struct ath_tx_status {
- u_int32_t ts_tstamp;
- u_int16_t ts_seqnum;
- u_int8_t ts_status;
- u_int8_t ts_ratecode;
- u_int8_t ts_rateindex;
+ u32 ts_tstamp;
+ u16 ts_seqnum;
+ u8 ts_status;
+ u8 ts_ratecode;
+ u8 ts_rateindex;
int8_t ts_rssi;
- u_int8_t ts_shortretry;
- u_int8_t ts_longretry;
- u_int8_t ts_virtcol;
- u_int8_t ts_antenna;
- u_int8_t ts_flags;
+ u8 ts_shortretry;
+ u8 ts_longretry;
+ u8 ts_virtcol;
+ u8 ts_antenna;
+ u8 ts_flags;
int8_t ts_rssi_ctl0;
int8_t ts_rssi_ctl1;
int8_t ts_rssi_ctl2;
int8_t ts_rssi_ext0;
int8_t ts_rssi_ext1;
int8_t ts_rssi_ext2;
- u_int8_t pad[3];
- u_int32_t ba_low;
- u_int32_t ba_high;
- u_int32_t evm0;
- u_int32_t evm1;
- u_int32_t evm2;
+ u8 pad[3];
+ u32 ba_low;
+ u32 ba_high;
+ u32 evm0;
+ u32 evm1;
+ u32 evm2;
};
struct ath_rx_status {
- u_int32_t rs_tstamp;
- u_int16_t rs_datalen;
- u_int8_t rs_status;
- u_int8_t rs_phyerr;
+ u32 rs_tstamp;
+ u16 rs_datalen;
+ u8 rs_status;
+ u8 rs_phyerr;
int8_t rs_rssi;
- u_int8_t rs_keyix;
- u_int8_t rs_rate;
- u_int8_t rs_antenna;
- u_int8_t rs_more;
+ u8 rs_keyix;
+ u8 rs_rate;
+ u8 rs_antenna;
+ u8 rs_more;
int8_t rs_rssi_ctl0;
int8_t rs_rssi_ctl1;
int8_t rs_rssi_ctl2;
int8_t rs_rssi_ext0;
int8_t rs_rssi_ext1;
int8_t rs_rssi_ext2;
- u_int8_t rs_isaggr;
- u_int8_t rs_moreaggr;
- u_int8_t rs_num_delims;
- u_int8_t rs_flags;
- u_int32_t evm0;
- u_int32_t evm1;
- u_int32_t evm2;
+ u8 rs_isaggr;
+ u8 rs_moreaggr;
+ u8 rs_num_delims;
+ u8 rs_flags;
+ u32 evm0;
+ u32 evm1;
+ u32 evm2;
};
#define ATH9K_RXERR_CRC 0x01
#define ATH9K_RX_DELIM_CRC_POST 0x20
#define ATH9K_RX_DECRYPT_BUSY 0x40
-#define HAL_RXKEYIX_INVALID ((u_int8_t)-1)
-#define HAL_TXKEYIX_INVALID ((u_int)-1)
+#define ATH9K_RXKEYIX_INVALID ((u8)-1)
+#define ATH9K_TXKEYIX_INVALID ((u32)-1)
struct ath_desc {
- u_int32_t ds_link;
- u_int32_t ds_data;
- u_int32_t ds_ctl0;
- u_int32_t ds_ctl1;
- u_int32_t ds_hw[20];
+ u32 ds_link;
+ u32 ds_data;
+ u32 ds_ctl0;
+ u32 ds_ctl1;
+ u32 ds_hw[20];
union {
struct ath_tx_status tx;
struct ath_rx_status rx;
#define ds_rxstat ds_us.rx
#define ds_stat ds_us.stats
-#define HAL_TXDESC_CLRDMASK 0x0001
-#define HAL_TXDESC_NOACK 0x0002
-#define HAL_TXDESC_RTSENA 0x0004
-#define HAL_TXDESC_CTSENA 0x0008
-#define HAL_TXDESC_INTREQ 0x0010
-#define HAL_TXDESC_VEOL 0x0020
-#define HAL_TXDESC_EXT_ONLY 0x0040
-#define HAL_TXDESC_EXT_AND_CTL 0x0080
-#define HAL_TXDESC_VMF 0x0100
-#define HAL_TXDESC_FRAG_IS_ON 0x0200
+#define ATH9K_TXDESC_CLRDMASK 0x0001
+#define ATH9K_TXDESC_NOACK 0x0002
+#define ATH9K_TXDESC_RTSENA 0x0004
+#define ATH9K_TXDESC_CTSENA 0x0008
+#define ATH9K_TXDESC_INTREQ 0x0010
+#define ATH9K_TXDESC_VEOL 0x0020
+#define ATH9K_TXDESC_EXT_ONLY 0x0040
+#define ATH9K_TXDESC_EXT_AND_CTL 0x0080
+#define ATH9K_TXDESC_VMF 0x0100
+#define ATH9K_TXDESC_FRAG_IS_ON 0x0200
-#define HAL_RXDESC_INTREQ 0x0020
+#define ATH9K_RXDESC_INTREQ 0x0020
enum hal_capability_type {
HAL_CAP_CIPHER = 0,
};
struct hal_capabilities {
- u_int halChanSpreadSupport:1,
+ u32 halChanSpreadSupport:1,
halChapTuningSupport:1,
halMicAesCcmSupport:1,
halMicCkipSupport:1,
halAutoSleepSupport:1,
hal4kbSplitTransSupport:1,
halWowMatchPatternExact:1;
- u_int32_t halWirelessModes;
- u_int16_t halTotalQueues;
- u_int16_t halKeyCacheSize;
- u_int16_t halLow5GhzChan, halHigh5GhzChan;
- u_int16_t halLow2GhzChan, halHigh2GhzChan;
- u_int16_t halNumMRRetries;
- u_int16_t halRtsAggrLimit;
- u_int8_t halTxChainMask;
- u_int8_t halRxChainMask;
- u_int16_t halTxTrigLevelMax;
- u_int16_t halRegCap;
- u_int8_t halNumGpioPins;
- u_int8_t halNumAntCfg2GHz;
- u_int8_t halNumAntCfg5GHz;
+ u32 halWirelessModes;
+ u16 halTotalQueues;
+ u16 halKeyCacheSize;
+ u16 halLow5GhzChan, halHigh5GhzChan;
+ u16 halLow2GhzChan, halHigh2GhzChan;
+ u16 halNumMRRetries;
+ u16 halRtsAggrLimit;
+ u8 halTxChainMask;
+ u8 halRxChainMask;
+ u16 halTxTrigLevelMax;
+ u16 halRegCap;
+ u8 halNumGpioPins;
+ u8 halNumAntCfg2GHz;
+ u8 halNumAntCfg5GHz;
};
struct hal_ops_config {
int ath_hal_additional_swba_backoff;
int ath_hal_6mb_ack;
int ath_hal_cwmIgnoreExtCCA;
- u_int8_t ath_hal_pciePowerSaveEnable;
- u_int8_t ath_hal_pcieL1SKPEnable;
- u_int8_t ath_hal_pcieClockReq;
- u_int32_t ath_hal_pcieWaen;
+ u8 ath_hal_pciePowerSaveEnable;
+ u8 ath_hal_pcieL1SKPEnable;
+ u8 ath_hal_pcieClockReq;
+ u32 ath_hal_pcieWaen;
int ath_hal_pciePowerReset;
- u_int8_t ath_hal_pcieRestore;
- u_int8_t ath_hal_analogShiftReg;
- u_int8_t ath_hal_htEnable;
- u_int32_t ath_hal_ofdmTrigLow;
- u_int32_t ath_hal_ofdmTrigHigh;
- u_int32_t ath_hal_cckTrigHigh;
- u_int32_t ath_hal_cckTrigLow;
- u_int32_t ath_hal_enableANI;
- u_int8_t ath_hal_noiseImmunityLvl;
- u_int32_t ath_hal_ofdmWeakSigDet;
- u_int32_t ath_hal_cckWeakSigThr;
- u_int8_t ath_hal_spurImmunityLvl;
- u_int8_t ath_hal_firStepLvl;
+ u8 ath_hal_pcieRestore;
+ u8 ath_hal_analogShiftReg;
+ u8 ath_hal_htEnable;
+ u32 ath_hal_ofdmTrigLow;
+ u32 ath_hal_ofdmTrigHigh;
+ u32 ath_hal_cckTrigHigh;
+ u32 ath_hal_cckTrigLow;
+ u32 ath_hal_enableANI;
+ u8 ath_hal_noiseImmunityLvl;
+ u32 ath_hal_ofdmWeakSigDet;
+ u32 ath_hal_cckWeakSigThr;
+ u8 ath_hal_spurImmunityLvl;
+ u8 ath_hal_firStepLvl;
int8_t ath_hal_rssiThrHigh;
int8_t ath_hal_rssiThrLow;
- u_int16_t ath_hal_diversityControl;
- u_int16_t ath_hal_antennaSwitchSwap;
+ u16 ath_hal_diversityControl;
+ u16 ath_hal_antennaSwitchSwap;
int ath_hal_serializeRegMode;
int ath_hal_intrMitigation;
#define SPUR_DISABLE 0
#define AR_SPUR_FEEQ_BOUND_HT40 19
#define AR_SPUR_FEEQ_BOUND_HT20 10
int ath_hal_spurMode;
- u_int16_t ath_hal_spurChans[AR_EEPROM_MODAL_SPURS][2];
+ u16 ath_hal_spurChans[AR_EEPROM_MODAL_SPURS][2];
};
-enum hal_tx_queue {
- HAL_TX_QUEUE_INACTIVE = 0,
- HAL_TX_QUEUE_DATA,
- HAL_TX_QUEUE_BEACON,
- HAL_TX_QUEUE_CAB,
- HAL_TX_QUEUE_UAPSD,
- HAL_TX_QUEUE_PSPOLL
+enum ath9k_tx_queue {
+ ATH9K_TX_QUEUE_INACTIVE = 0,
+ ATH9K_TX_QUEUE_DATA,
+ ATH9K_TX_QUEUE_BEACON,
+ ATH9K_TX_QUEUE_CAB,
+ ATH9K_TX_QUEUE_UAPSD,
+ ATH9K_TX_QUEUE_PSPOLL
};
-#define HAL_NUM_TX_QUEUES 10
+#define ATH9K_NUM_TX_QUEUES 10
-enum hal_tx_queue_subtype {
- HAL_WME_AC_BK = 0,
- HAL_WME_AC_BE,
- HAL_WME_AC_VI,
- HAL_WME_AC_VO,
- HAL_WME_UPSD
+enum ath9k_tx_queue_subtype {
+ ATH9K_WME_AC_BK = 0,
+ ATH9K_WME_AC_BE,
+ ATH9K_WME_AC_VI,
+ ATH9K_WME_AC_VO,
+ ATH9K_WME_UPSD
};
-enum hal_tx_queue_flags {
+enum ath9k_tx_queue_flags {
TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
};
-struct hal_txq_info {
- u_int32_t tqi_ver;
- enum hal_tx_queue_subtype tqi_subtype;
- enum hal_tx_queue_flags tqi_qflags;
- u_int32_t tqi_priority;
- u_int32_t tqi_aifs;
- u_int32_t tqi_cwmin;
- u_int32_t tqi_cwmax;
- u_int16_t tqi_shretry;
- u_int16_t tqi_lgretry;
- u_int32_t tqi_cbrPeriod;
- u_int32_t tqi_cbrOverflowLimit;
- u_int32_t tqi_burstTime;
- u_int32_t tqi_readyTime;
- u_int32_t tqi_compBuf;
+struct ath9k_txq_info {
+ u32 tqi_ver;
+ enum ath9k_tx_queue_subtype tqi_subtype;
+ enum ath9k_tx_queue_flags tqi_qflags;
+ u32 tqi_priority;
+ u32 tqi_aifs;
+ u32 tqi_cwmin;
+ u32 tqi_cwmax;
+ u16 tqi_shretry;
+ u16 tqi_lgretry;
+ u32 tqi_cbrPeriod;
+ u32 tqi_cbrOverflowLimit;
+ u32 tqi_burstTime;
+ u32 tqi_readyTime;
+ u32 tqi_compBuf;
};
-#define HAL_TQI_NONVAL 0xffff
+#define ATH9K_TXQ_USEDEFAULT ((u32) -1)
-#define HAL_TXQ_USEDEFAULT ((u_int32_t) -1)
+#define ATH9K_DECOMP_MASK_SIZE 128
+#define ATH9K_READY_TIME_LO_BOUND 50
+#define ATH9K_READY_TIME_HI_BOUND 96
-#define HAL_COMP_BUF_MAX_SIZE 9216
-#define HAL_COMP_BUF_ALIGN_SIZE 512
-#define HAL_DECOMP_MASK_SIZE 128
-
-#define HAL_READY_TIME_LO_BOUND 50
-#define HAL_READY_TIME_HI_BOUND 96
-
-enum hal_pkt_type {
- HAL_PKT_TYPE_NORMAL = 0,
- HAL_PKT_TYPE_ATIM,
- HAL_PKT_TYPE_PSPOLL,
- HAL_PKT_TYPE_BEACON,
- HAL_PKT_TYPE_PROBE_RESP,
- HAL_PKT_TYPE_CHIRP,
- HAL_PKT_TYPE_GRP_POLL,
+enum ath9k_pkt_type {
+ ATH9K_PKT_TYPE_NORMAL = 0,
+ ATH9K_PKT_TYPE_ATIM,
+ ATH9K_PKT_TYPE_PSPOLL,
+ ATH9K_PKT_TYPE_BEACON,
+ ATH9K_PKT_TYPE_PROBE_RESP,
+ ATH9K_PKT_TYPE_CHIRP,
+ ATH9K_PKT_TYPE_GRP_POLL,
};
-struct hal_tx_queue_info {
- u_int32_t tqi_ver;
- enum hal_tx_queue tqi_type;
- enum hal_tx_queue_subtype tqi_subtype;
- enum hal_tx_queue_flags tqi_qflags;
- u_int32_t tqi_priority;
- u_int32_t tqi_aifs;
- u_int32_t tqi_cwmin;
- u_int32_t tqi_cwmax;
- u_int16_t tqi_shretry;
- u_int16_t tqi_lgretry;
- u_int32_t tqi_cbrPeriod;
- u_int32_t tqi_cbrOverflowLimit;
- u_int32_t tqi_burstTime;
- u_int32_t tqi_readyTime;
- u_int32_t tqi_physCompBuf;
- u_int32_t tqi_intFlags;
+struct ath9k_tx_queue_info {
+ u32 tqi_ver;
+ enum ath9k_tx_queue tqi_type;
+ enum ath9k_tx_queue_subtype tqi_subtype;
+ enum ath9k_tx_queue_flags tqi_qflags;
+ u32 tqi_priority;
+ u32 tqi_aifs;
+ u32 tqi_cwmin;
+ u32 tqi_cwmax;
+ u16 tqi_shretry;
+ u16 tqi_lgretry;
+ u32 tqi_cbrPeriod;
+ u32 tqi_cbrOverflowLimit;
+ u32 tqi_burstTime;
+ u32 tqi_readyTime;
+ u32 tqi_physCompBuf;
+ u32 tqi_intFlags;
};
-enum hal_rx_filter {
- HAL_RX_FILTER_UCAST = 0x00000001,
- HAL_RX_FILTER_MCAST = 0x00000002,
- HAL_RX_FILTER_BCAST = 0x00000004,
- HAL_RX_FILTER_CONTROL = 0x00000008,
- HAL_RX_FILTER_BEACON = 0x00000010,
- HAL_RX_FILTER_PROM = 0x00000020,
- HAL_RX_FILTER_PROBEREQ = 0x00000080,
- HAL_RX_FILTER_PSPOLL = 0x00004000,
- HAL_RX_FILTER_PHYERR = 0x00000100,
- HAL_RX_FILTER_PHYRADAR = 0x00002000,
+enum ath9k_rx_filter {
+ ATH9K_RX_FILTER_UCAST = 0x00000001,
+ ATH9K_RX_FILTER_MCAST = 0x00000002,
+ ATH9K_RX_FILTER_BCAST = 0x00000004,
+ ATH9K_RX_FILTER_CONTROL = 0x00000008,
+ ATH9K_RX_FILTER_BEACON = 0x00000010,
+ ATH9K_RX_FILTER_PROM = 0x00000020,
+ ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
+ ATH9K_RX_FILTER_PSPOLL = 0x00004000,
+ ATH9K_RX_FILTER_PHYERR = 0x00000100,
+ ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
};
-enum hal_int {
- HAL_INT_RX = 0x00000001,
- HAL_INT_RXDESC = 0x00000002,
- HAL_INT_RXNOFRM = 0x00000008,
- HAL_INT_RXEOL = 0x00000010,
- HAL_INT_RXORN = 0x00000020,
- HAL_INT_TX = 0x00000040,
- HAL_INT_TXDESC = 0x00000080,
- HAL_INT_TIM_TIMER = 0x00000100,
- HAL_INT_TXURN = 0x00000800,
- HAL_INT_MIB = 0x00001000,
- HAL_INT_RXPHY = 0x00004000,
- HAL_INT_RXKCM = 0x00008000,
- HAL_INT_SWBA = 0x00010000,
- HAL_INT_BMISS = 0x00040000,
- HAL_INT_BNR = 0x00100000,
- HAL_INT_TIM = 0x00200000,
- HAL_INT_DTIM = 0x00400000,
- HAL_INT_DTIMSYNC = 0x00800000,
- HAL_INT_GPIO = 0x01000000,
- HAL_INT_CABEND = 0x02000000,
- HAL_INT_CST = 0x10000000,
- HAL_INT_GTT = 0x20000000,
- HAL_INT_FATAL = 0x40000000,
- HAL_INT_GLOBAL = 0x80000000,
- HAL_INT_BMISC = HAL_INT_TIM
- | HAL_INT_DTIM | HAL_INT_DTIMSYNC | HAL_INT_CABEND,
- HAL_INT_COMMON = HAL_INT_RXNOFRM
- | HAL_INT_RXDESC
- | HAL_INT_RXEOL
- | HAL_INT_RXORN
- | HAL_INT_TXURN
- | HAL_INT_TXDESC
- | HAL_INT_MIB
- | HAL_INT_RXPHY
- | HAL_INT_RXKCM | HAL_INT_SWBA | HAL_INT_BMISS | HAL_INT_GPIO,
- HAL_INT_NOCARD = 0xffffffff
+enum ath9k_int {
+ ATH9K_INT_RX = 0x00000001,
+ ATH9K_INT_RXDESC = 0x00000002,
+ ATH9K_INT_RXNOFRM = 0x00000008,
+ ATH9K_INT_RXEOL = 0x00000010,
+ ATH9K_INT_RXORN = 0x00000020,
+ ATH9K_INT_TX = 0x00000040,
+ ATH9K_INT_TXDESC = 0x00000080,
+ ATH9K_INT_TIM_TIMER = 0x00000100,
+ ATH9K_INT_TXURN = 0x00000800,
+ ATH9K_INT_MIB = 0x00001000,
+ ATH9K_INT_RXPHY = 0x00004000,
+ ATH9K_INT_RXKCM = 0x00008000,
+ ATH9K_INT_SWBA = 0x00010000,
+ ATH9K_INT_BMISS = 0x00040000,
+ ATH9K_INT_BNR = 0x00100000,
+ ATH9K_INT_TIM = 0x00200000,
+ ATH9K_INT_DTIM = 0x00400000,
+ ATH9K_INT_DTIMSYNC = 0x00800000,
+ ATH9K_INT_GPIO = 0x01000000,
+ ATH9K_INT_CABEND = 0x02000000,
+ ATH9K_INT_CST = 0x10000000,
+ ATH9K_INT_GTT = 0x20000000,
+ ATH9K_INT_FATAL = 0x40000000,
+ ATH9K_INT_GLOBAL = 0x80000000,
+ ATH9K_INT_BMISC = ATH9K_INT_TIM |
+ ATH9K_INT_DTIM |
+ ATH9K_INT_DTIMSYNC |
+ ATH9K_INT_CABEND,
+ ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
+ ATH9K_INT_RXDESC |
+ ATH9K_INT_RXEOL |
+ ATH9K_INT_RXORN |
+ ATH9K_INT_TXURN |
+ ATH9K_INT_TXDESC |
+ ATH9K_INT_MIB |
+ ATH9K_INT_RXPHY |
+ ATH9K_INT_RXKCM |
+ ATH9K_INT_SWBA |
+ ATH9K_INT_BMISS |
+ ATH9K_INT_GPIO,
+ ATH9K_INT_NOCARD = 0xffffffff
};
-struct hal_rate_table {
+struct ath9k_rate_table {
int rateCount;
- u_int8_t rateCodeToIndex[256];
+ u8 rateCodeToIndex[256];
struct {
- u_int8_t valid;
- u_int8_t phy;
- u_int32_t rateKbps;
- u_int8_t rateCode;
- u_int8_t shortPreamble;
- u_int8_t dot11Rate;
- u_int8_t controlRate;
- u_int16_t lpAckDuration;
- u_int16_t spAckDuration;
+ u8 valid;
+ u8 phy;
+ u32 rateKbps;
+ u8 rateCode;
+ u8 shortPreamble;
+ u8 dot11Rate;
+ u8 controlRate;
+ u16 lpAckDuration;
+ u16 spAckDuration;
} info[32];
};
-#define HAL_RATESERIES_RTS_CTS 0x0001
-#define HAL_RATESERIES_2040 0x0002
-#define HAL_RATESERIES_HALFGI 0x0004
-
-struct hal_11n_rate_series {
- u_int Tries;
- u_int Rate;
- u_int PktDuration;
- u_int ChSel;
- u_int RateFlags;
-};
+#define ATH9K_RATESERIES_RTS_CTS 0x0001
+#define ATH9K_RATESERIES_2040 0x0002
+#define ATH9K_RATESERIES_HALFGI 0x0004
-struct hal_channel {
- u_int16_t channel;
- u_int32_t channelFlags;
- u_int8_t privFlags;
- int8_t maxRegTxPower;
- int8_t maxTxPower;
- int8_t minTxPower;
+struct ath9k_11n_rate_series {
+ u32 Tries;
+ u32 Rate;
+ u32 PktDuration;
+ u32 ChSel;
+ u32 RateFlags;
};
#define CHANNEL_CW_INT 0x00002
#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
-#define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM)
#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
CHANNEL_HT40PLUS | \
CHANNEL_HT40MINUS)
-struct hal_channel_internal {
- u_int16_t channel;
- u_int32_t channelFlags;
- u_int8_t privFlags;
+struct ath9k_channel {
+ u16 channel;
+ u32 channelFlags;
+ u8 privFlags;
int8_t maxRegTxPower;
int8_t maxTxPower;
int8_t minTxPower;
- bool bssSendHere;
- u_int8_t gainI;
- bool iqCalValid;
+ u32 chanmode;
int32_t CalValid;
bool oneTimeCalsDone;
int8_t iCoff;
int8_t qCoff;
int16_t rawNoiseFloor;
- int16_t noiseFloorAdjust;
int8_t antennaMax;
- u_int32_t regDmnFlags;
- u_int32_t conformanceTestLimit;
- u_int64_t ah_tsf_last;
- u_int64_t ah_channel_time;
- u_int16_t mainSpur;
- u_int64_t dfsTsf;
+ u32 regDmnFlags;
+ u32 conformanceTestLimit[3]; /* 0:11a, 1: 11b, 2:11g */
#ifdef ATH_NF_PER_CHAN
- struct hal_nfcal_hist nfCalHist[NUM_NF_READINGS];
+ struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
#endif
};
-#define HAL_SPUR_VAL_MASK 0x3FFF
-#define HAL_SPUR_CHAN_WIDTH 87
-#define HAL_BIN_WIDTH_BASE_100HZ 3125
-#define HAL_MAX_BINS_ALLOWED 28
-
#define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
(((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
(((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
(((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
(((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
(((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
-#define IS_CHAN_PUREG(_c) \
- (((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG)
#define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
#define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
-#define IS_CHAN_HT20(_c) (((_c)->channelFlags & CHANNEL_HT20) != 0)
-#define IS_CHAN_HT40(_c) ((((_c)->channelFlags & CHANNEL_HT40PLUS) != 0) \
- || (((_c)->channelFlags & CHANNEL_HT40MINUS) != 0))
+
+/* These macros check chanmode and not channelFlags */
+#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
+ ((_c)->chanmode == CHANNEL_G_HT20))
+#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
+ ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
+ ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
+ ((_c)->chanmode == CHANNEL_G_HT40MINUS))
#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
+
#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
-#define IS_CHAN_A_5MHZ_SPACED(_c) \
- ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
- (((_c)->channel % 20) != 0) && \
- (((_c)->channel % 10) != 0))
-
-struct hal_keyval {
- u_int8_t kv_type;
- u_int8_t kv_pad;
- u_int16_t kv_len;
- u_int8_t kv_val[16];
- u_int8_t kv_mic[8];
- u_int8_t kv_txmic[8];
+#define IS_CHAN_A_5MHZ_SPACED(_c) \
+ ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
+ (((_c)->channel % 20) != 0) && \
+ (((_c)->channel % 10) != 0))
+
+struct ath9k_keyval {
+ u8 kv_type;
+ u8 kv_pad;
+ u16 kv_len;
+ u8 kv_val[16];
+ u8 kv_mic[8];
+ u8 kv_txmic[8];
};
-enum hal_key_type {
- HAL_KEY_TYPE_CLEAR,
- HAL_KEY_TYPE_WEP,
- HAL_KEY_TYPE_AES,
- HAL_KEY_TYPE_TKIP,
+enum ath9k_key_type {
+ ATH9K_KEY_TYPE_CLEAR,
+ ATH9K_KEY_TYPE_WEP,
+ ATH9K_KEY_TYPE_AES,
+ ATH9K_KEY_TYPE_TKIP,
};
-enum hal_cipher {
- HAL_CIPHER_WEP = 0,
- HAL_CIPHER_AES_OCB = 1,
- HAL_CIPHER_AES_CCM = 2,
- HAL_CIPHER_CKIP = 3,
- HAL_CIPHER_TKIP = 4,
- HAL_CIPHER_CLR = 5,
- HAL_CIPHER_MIC = 127
+enum ath9k_cipher {
+ ATH9K_CIPHER_WEP = 0,
+ ATH9K_CIPHER_AES_OCB = 1,
+ ATH9K_CIPHER_AES_CCM = 2,
+ ATH9K_CIPHER_CKIP = 3,
+ ATH9K_CIPHER_TKIP = 4,
+ ATH9K_CIPHER_CLR = 5,
+ ATH9K_CIPHER_MIC = 127
};
#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
#define AR_EEPROM_RFSILENT_POLARITY 0x0002
#define AR_EEPROM_RFSILENT_POLARITY_S 1
-enum {
- CTRY_DEBUG = 0x1ff,
- CTRY_DEFAULT = 0
-};
+#define CTRY_DEBUG 0x1ff
+#define CTRY_DEFAULT 0
enum reg_ext_bitmap {
REG_EXT_JAPAN_MIDBAND = 1,
REG_EXT_JAPAN_DFS_HT40 = 4
};
-struct hal_country_entry {
- u_int16_t countryCode;
- u_int16_t regDmnEnum;
- u_int16_t regDmn5G;
- u_int16_t regDmn2G;
- u_int8_t isMultidomain;
- u_int8_t iso[3];
+struct ath9k_country_entry {
+ u16 countryCode;
+ u16 regDmnEnum;
+ u16 regDmn5G;
+ u16 regDmn2G;
+ u8 isMultidomain;
+ u8 iso[3];
};
#define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
#define REG_CLR_BIT(_a, _r, _f) \
REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
-#define HAL_COMP_BUF_MAX_SIZE 9216
-#define HAL_COMP_BUF_ALIGN_SIZE 512
+#define ATH9K_COMP_BUF_MAX_SIZE 9216
+#define ATH9K_COMP_BUF_ALIGN_SIZE 512
-#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
+#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
#define INIT_AIFS 2
#define INIT_CWMIN 15
#define MAX_RATE_POWER 63
#define LE_READ_2(p) \
- ((u_int16_t) \
- ((((const u_int8_t *)(p))[0]) | \
- (((const u_int8_t *)(p))[1] << 8)))
+ ((u16) \
+ ((((const u8 *)(p))[0]) | \
+ (((const u8 *)(p))[1] << 8)))
#define LE_READ_4(p) \
- ((u_int32_t) \
- ((((const u_int8_t *)(p))[0]) | \
- (((const u_int8_t *)(p))[1] << 8) | \
- (((const u_int8_t *)(p))[2] << 16) | \
- (((const u_int8_t *)(p))[3] << 24)))
-
-enum hal_status {
- HAL_OK = 0,
- HAL_ENXIO,
- HAL_ENOMEM,
- HAL_EIO,
- HAL_EEMAGIC,
- HAL_EEVERSION,
- HAL_EELOCKED,
- HAL_EEBADSUM,
- HAL_EEREAD,
- HAL_EEBADMAC,
- HAL_EESIZE,
- HAL_EEWRITE,
- HAL_EINVAL,
- HAL_ENOTSUPP,
- HAL_ESELFTEST,
- HAL_EINPROGRESS
-};
-
-enum hal_power_mode {
- HAL_PM_AWAKE = 0,
- HAL_PM_FULL_SLEEP,
- HAL_PM_NETWORK_SLEEP,
- HAL_PM_UNDEFINED
-};
-
-enum hal_rfgain {
- HAL_RFGAIN_INACTIVE = 0,
- HAL_RFGAIN_READ_REQUESTED,
- HAL_RFGAIN_NEED_CHANGE
+ ((u32) \
+ ((((const u8 *)(p))[0]) | \
+ (((const u8 *)(p))[1] << 8) | \
+ (((const u8 *)(p))[2] << 16) | \
+ (((const u8 *)(p))[3] << 24)))
+
+enum ath9k_power_mode {
+ ATH9K_PM_AWAKE = 0,
+ ATH9K_PM_FULL_SLEEP,
+ ATH9K_PM_NETWORK_SLEEP,
+ ATH9K_PM_UNDEFINED
};
#define HAL_ANTENNA_MIN_MODE 0
#define HAL_ANTENNA_FIXED_B 2
#define HAL_ANTENNA_MAX_MODE 3
-struct hal_mib_stats {
- u_int32_t ackrcv_bad;
- u_int32_t rts_bad;
- u_int32_t rts_good;
- u_int32_t fcs_bad;
- u_int32_t beacons;
-};
-
-enum hal_ant_setting {
- HAL_ANT_VARIABLE = 0,
- HAL_ANT_FIXED_A,
- HAL_ANT_FIXED_B
+struct ath9k_mib_stats {
+ u32 ackrcv_bad;
+ u32 rts_bad;
+ u32 rts_good;
+ u32 fcs_bad;
+ u32 beacons;
};
-enum hal_opmode {
- HAL_M_STA = 1,
- HAL_M_IBSS = 0,
- HAL_M_HOSTAP = 6,
- HAL_M_MONITOR = 8
+enum ath9k_ant_setting {
+ ATH9K_ANT_VARIABLE = 0,
+ ATH9K_ANT_FIXED_A,
+ ATH9K_ANT_FIXED_B
};
-enum {
- HAL_SLOT_TIME_6 = 6,
- HAL_SLOT_TIME_9 = 9,
- HAL_SLOT_TIME_20 = 20,
+enum ath9k_opmode {
+ ATH9K_M_STA = 1,
+ ATH9K_M_IBSS = 0,
+ ATH9K_M_HOSTAP = 6,
+ ATH9K_M_MONITOR = 8
};
+#define ATH9K_SLOT_TIME_6 6
+#define ATH9K_SLOT_TIME_9 9
+#define ATH9K_SLOT_TIME_20 20
-enum hal_ht_macmode {
- HAL_HT_MACMODE_20 = 0,
- HAL_HT_MACMODE_2040 = 1,
+enum ath9k_ht_macmode {
+ ATH9K_HT_MACMODE_20 = 0,
+ ATH9K_HT_MACMODE_2040 = 1,
};
-enum hal_ht_extprotspacing {
- HAL_HT_EXTPROTSPACING_20 = 0,
- HAL_HT_EXTPROTSPACING_25 = 1,
+enum ath9k_ht_extprotspacing {
+ ATH9K_HT_EXTPROTSPACING_20 = 0,
+ ATH9K_HT_EXTPROTSPACING_25 = 1,
};
-struct hal_ht_cwm {
- enum hal_ht_macmode ht_macmode;
- enum hal_ht_extprotspacing ht_extprotspacing;
+struct ath9k_ht_cwm {
+ enum ath9k_ht_macmode ht_macmode;
+ enum ath9k_ht_extprotspacing ht_extprotspacing;
};
enum hal_freq_band {
HAL_FREQ_BAND_2GHZ = 1,
};
-enum {
- HAL_TRUE_CHIP = 1
-};
-
-enum hal_bus_type {
- HAL_BUS_TYPE_PCI,
- HAL_BUS_TYPE_AHB
-};
-
-enum hal_ani_cmd {
- HAL_ANI_PRESENT = 0x1,
- HAL_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
- HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
- HAL_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
- HAL_ANI_FIRSTEP_LEVEL = 0x10,
- HAL_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
- HAL_ANI_MODE = 0x40,
- HAL_ANI_PHYERR_RESET = 0x80,
- HAL_ANI_ALL = 0xff
+enum ath9k_ani_cmd {
+ ATH9K_ANI_PRESENT = 0x1,
+ ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
+ ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
+ ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
+ ATH9K_ANI_FIRSTEP_LEVEL = 0x10,
+ ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
+ ATH9K_ANI_MODE = 0x40,
+ ATH9K_ANI_PHYERR_RESET = 0x80,
+ ATH9K_ANI_ALL = 0xff
};
enum phytype {
START_ADHOC_IN_11B,
};
-enum hal_tp_scale {
- HAL_TP_SCALE_MAX = 0,
- HAL_TP_SCALE_50,
- HAL_TP_SCALE_25,
- HAL_TP_SCALE_12,
- HAL_TP_SCALE_MIN
+enum ath9k_tp_scale {
+ ATH9K_TP_SCALE_MAX = 0,
+ ATH9K_TP_SCALE_50,
+ ATH9K_TP_SCALE_25,
+ ATH9K_TP_SCALE_12,
+ ATH9K_TP_SCALE_MIN
};
enum ser_reg_mode {
#define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3
#define AR_PHY_CCA_FILTERWINDOW_LENGTH 5
-#define HAL_NF_CAL_HIST_MAX 5
+#define ATH9K_NF_CAL_HIST_MAX 5
#define NUM_NF_READINGS 6
-struct hal_nfcal_hist {
- int16_t nfCalBuffer[HAL_NF_CAL_HIST_MAX];
- u_int8_t currIndex;
+struct ath9k_nfcal_hist {
+ int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX];
+ u8 currIndex;
int16_t privNF;
- u_int8_t invalidNFcount;
+ u8 invalidNFcount;
};
-struct hal_beacon_state {
- u_int32_t bs_nexttbtt;
- u_int32_t bs_nextdtim;
- u_int32_t bs_intval;
-#define HAL_BEACON_PERIOD 0x0000ffff
-#define HAL_BEACON_ENA 0x00800000
-#define HAL_BEACON_RESET_TSF 0x01000000
- u_int32_t bs_dtimperiod;
- u_int16_t bs_cfpperiod;
- u_int16_t bs_cfpmaxduration;
- u_int32_t bs_cfpnext;
- u_int16_t bs_timoffset;
- u_int16_t bs_bmissthreshold;
- u_int32_t bs_sleepduration;
+struct ath9k_beacon_state {
+ u32 bs_nexttbtt;
+ u32 bs_nextdtim;
+ u32 bs_intval;
+#define ATH9K_BEACON_PERIOD 0x0000ffff
+#define ATH9K_BEACON_ENA 0x00800000
+#define ATH9K_BEACON_RESET_TSF 0x01000000
+ u32 bs_dtimperiod;
+ u16 bs_cfpperiod;
+ u16 bs_cfpmaxduration;
+ u32 bs_cfpnext;
+ u16 bs_timoffset;
+ u16 bs_bmissthreshold;
+ u32 bs_sleepduration;
};
-struct hal_node_stats {
- u_int32_t ns_avgbrssi;
- u_int32_t ns_avgrssi;
- u_int32_t ns_avgtxrssi;
- u_int32_t ns_avgtxrate;
+struct ath9k_node_stats {
+ u32 ns_avgbrssi;
+ u32 ns_avgrssi;
+ u32 ns_avgtxrssi;
+ u32 ns_avgtxrate;
};
-#define HAL_RSSI_EP_MULTIPLIER (1<<7)
-#define HAL_RATE_EP_MULTIPLIER (1<<7)
+#define ATH9K_RSSI_EP_MULTIPLIER (1<<7)
-enum hal_gpio_output_mux_type {
- HAL_GPIO_OUTPUT_MUX_AS_OUTPUT,
- HAL_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,
- HAL_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,
- HAL_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,
- HAL_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,
- HAL_GPIO_OUTPUT_MUX_NUM_ENTRIES
+enum ath9k_gpio_output_mux_type {
+ ATH9K_GPIO_OUTPUT_MUX_AS_OUTPUT,
+ ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,
+ ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,
+ ATH9K_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,
+ ATH9K_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,
+ ATH9K_GPIO_OUTPUT_MUX_NUM_ENTRIES
};
enum {
- HAL_RESET_POWER_ON,
- HAL_RESET_WARM,
- HAL_RESET_COLD,
+ ATH9K_RESET_POWER_ON,
+ ATH9K_RESET_WARM,
+ ATH9K_RESET_COLD,
};
#define AH_USE_EEPROM 0x1
-#define AH_IS_HB63 0x2
struct ath_hal {
- u_int32_t ah_magic;
- u_int16_t ah_devid;
- u_int16_t ah_subvendorid;
+ u32 ah_magic;
+ u16 ah_devid;
+ u16 ah_subvendorid;
struct ath_softc *ah_sc;
void __iomem *ah_sh;
- u_int16_t ah_countryCode;
- u_int32_t ah_macVersion;
- u_int16_t ah_macRev;
- u_int16_t ah_phyRev;
- u_int16_t ah_analog5GhzRev;
- u_int16_t ah_analog2GhzRev;
- u_int8_t ah_decompMask[HAL_DECOMP_MASK_SIZE];
- u_int32_t ah_flags;
- enum hal_opmode ah_opmode;
+ u16 ah_countryCode;
+ u32 ah_macVersion;
+ u16 ah_macRev;
+ u16 ah_phyRev;
+ u16 ah_analog5GhzRev;
+ u16 ah_analog2GhzRev;
+ u8 ah_decompMask[ATH9K_DECOMP_MASK_SIZE];
+ u32 ah_flags;
+ enum ath9k_opmode ah_opmode;
struct hal_ops_config ah_config;
struct hal_capabilities ah_caps;
int16_t ah_powerLimit;
- u_int16_t ah_maxPowerLevel;
- u_int ah_tpScale;
- u_int16_t ah_currentRD;
- u_int16_t ah_currentRDExt;
- u_int16_t ah_currentRDInUse;
- u_int16_t ah_currentRD5G;
- u_int16_t ah_currentRD2G;
+ u16 ah_maxPowerLevel;
+ u32 ah_tpScale;
+ u16 ah_currentRD;
+ u16 ah_currentRDExt;
+ u16 ah_currentRDInUse;
+ u16 ah_currentRD5G;
+ u16 ah_currentRD2G;
char ah_iso[4];
enum start_adhoc_option ah_adHocMode;
bool ah_commonMode;
- struct hal_channel_internal ah_channels[150];
- u_int ah_nchan;
- struct hal_channel_internal *ah_curchan;
- u_int16_t ah_rfsilent;
+ struct ath9k_channel ah_channels[150];
+ u32 ah_nchan;
+ struct ath9k_channel *ah_curchan;
+ u16 ah_rfsilent;
bool ah_rfkillEnabled;
bool ah_isPciExpress;
- u_int16_t ah_txTrigLevel;
+ u16 ah_txTrigLevel;
#ifndef ATH_NF_PER_CHAN
- struct hal_nfcal_hist nfCalHist[NUM_NF_READINGS];
+ struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
#endif
};
};
struct chan_centers {
- u_int16_t synth_center;
- u_int16_t ctl_center;
- u_int16_t ext_center;
+ u16 synth_center;
+ u16 ctl_center;
+ u16 ext_center;
};
-enum hal_status ath_hal_getcapability(struct ath_hal *ah,
- enum hal_capability_type type,
- u_int32_t capability,
- u_int32_t *result);
-const struct hal_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
- u_int mode);
+int ath_hal_getcapability(struct ath_hal *ah,
+ enum hal_capability_type type,
+ u32 capability,
+ u32 *result);
+const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
+ u32 mode);
void ath9k_hw_detach(struct ath_hal *ah);
-struct ath_hal *ath9k_hw_attach(u_int16_t devid,
+struct ath_hal *ath9k_hw_attach(u16 devid,
struct ath_softc *sc,
void __iomem *mem,
- enum hal_status *error);
+ int *error);
bool ath9k_regd_init_channels(struct ath_hal *ah,
- struct hal_channel *chans,
- u_int maxchans, u_int *nchans,
- u_int8_t *regclassids,
- u_int maxregids, u_int *nregids,
- u_int16_t cc, u_int32_t modeSelect,
+ u32 maxchans, u32 *nchans,
+ u8 *regclassids,
+ u32 maxregids, u32 *nregids,
+ u16 cc, u32 modeSelect,
bool enableOutdoor,
bool enableExtendedChannels);
-u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags);
-enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah,
- enum hal_int ints);
-bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
- struct hal_channel *chan,
- enum hal_ht_macmode macmode,
- u_int8_t txchainmask, u_int8_t rxchainmask,
- enum hal_ht_extprotspacing extprotspacing,
+u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
+enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah,
+ enum ath9k_int ints);
+bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode,
+ struct ath9k_channel *chan,
+ enum ath9k_ht_macmode macmode,
+ u8 txchainmask, u8 rxchainmask,
+ enum ath9k_ht_extprotspacing extprotspacing,
bool bChannelChange,
- enum hal_status *status);
+ int *status);
bool ath9k_hw_phy_disable(struct ath_hal *ah);
-void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct hal_channel *chan,
+void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
bool *isCalDone);
void ath9k_hw_ani_monitor(struct ath_hal *ah,
- const struct hal_node_stats *stats,
- struct hal_channel *chan);
+ const struct ath9k_node_stats *stats,
+ struct ath9k_channel *chan);
bool ath9k_hw_calibrate(struct ath_hal *ah,
- struct hal_channel *chan,
- u_int8_t rxchainmask,
+ struct ath9k_channel *chan,
+ u8 rxchainmask,
bool longcal,
bool *isCalDone);
int16_t ath9k_hw_getchan_noise(struct ath_hal *ah,
- struct hal_channel *chan);
-void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
- u_int16_t assocId);
-void ath9k_hw_setrxfilter(struct ath_hal *ah, u_int32_t bits);
-void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
- u_int16_t assocId);
-bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q);
+ struct ath9k_channel *chan);
+void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
+ u16 assocId);
+void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
+void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
+ u16 assocId);
+bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
void ath9k_hw_reset_tsf(struct ath_hal *ah);
-bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry);
-bool ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
- const u_int8_t *mac);
+bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
+bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
+ const u8 *mac);
bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
- u_int16_t entry,
- const struct hal_keyval *k,
- const u_int8_t *mac,
+ u16 entry,
+ const struct ath9k_keyval *k,
+ const u8 *mac,
int xorKey);
bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
- u_int32_t setting);
+ u32 setting);
void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
bool ath9k_hw_intrpend(struct ath_hal *ah);
-bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked);
+bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
bool bIncTrigLevel);
void ath9k_hw_procmibevent(struct ath_hal *ah,
- const struct hal_node_stats *stats);
+ const struct ath9k_node_stats *stats);
bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
-void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum hal_ht_macmode mode);
+void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
bool ath9k_hw_phycounters(struct ath_hal *ah);
-bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry);
+bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
bool ath9k_hw_getcapability(struct ath_hal *ah,
enum hal_capability_type type,
- u_int32_t capability,
- u_int32_t *result);
+ u32 capability,
+ u32 *result);
bool ath9k_hw_setcapability(struct ath_hal *ah,
enum hal_capability_type type,
- u_int32_t capability,
- u_int32_t setting,
- enum hal_status *status);
-u_int ath9k_hw_getdefantenna(struct ath_hal *ah);
-void ath9k_hw_getmac(struct ath_hal *ah, u_int8_t *mac);
-void ath9k_hw_getbssidmask(struct ath_hal *ah, u_int8_t *mask);
+ u32 capability,
+ u32 setting,
+ int *status);
+u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
+void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
+void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
bool ath9k_hw_setbssidmask(struct ath_hal *ah,
- const u_int8_t *mask);
+ const u8 *mask);
bool ath9k_hw_setpower(struct ath_hal *ah,
- enum hal_power_mode mode);
-enum hal_int ath9k_hw_intrget(struct ath_hal *ah);
-u_int64_t ath9k_hw_gettsf64(struct ath_hal *ah);
-u_int ath9k_hw_getdefantenna(struct ath_hal *ah);
-bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us);
+ enum ath9k_power_mode mode);
+enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah);
+u64 ath9k_hw_gettsf64(struct ath_hal *ah);
+u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
+bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us);
bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
- enum hal_ant_setting settings,
- struct hal_channel *chan,
- u_int8_t *tx_chainmask,
- u_int8_t *rx_chainmask,
- u_int8_t *antenna_cfgd);
-void ath9k_hw_setantenna(struct ath_hal *ah, u_int antenna);
-enum hal_status ath9k_hw_select_antconfig(struct ath_hal *ah,
- u_int32_t cfg);
-bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
- u_int32_t txdp);
-bool ath9k_hw_txstart(struct ath_hal *ah, u_int q);
-u_int16_t ath9k_hw_computetxtime(struct ath_hal *ah,
- const struct hal_rate_table *rates,
- u_int32_t frameLen, u_int16_t rateix,
+ enum ath9k_ant_setting settings,
+ struct ath9k_channel *chan,
+ u8 *tx_chainmask,
+ u8 *rx_chainmask,
+ u8 *antenna_cfgd);
+void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna);
+int ath9k_hw_select_antconfig(struct ath_hal *ah,
+ u32 cfg);
+bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q,
+ u32 txdp);
+bool ath9k_hw_txstart(struct ath_hal *ah, u32 q);
+u16 ath9k_hw_computetxtime(struct ath_hal *ah,
+ const struct ath9k_rate_table *rates,
+ u32 frameLen, u16 rateix,
bool shortPreamble);
void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
struct ath_desc *lastds,
- u_int durUpdateEn, u_int rtsctsRate,
- u_int rtsctsDuration,
- struct hal_11n_rate_series series[],
- u_int nseries, u_int flags);
+ u32 durUpdateEn, u32 rtsctsRate,
+ u32 rtsctsDuration,
+ struct ath9k_11n_rate_series series[],
+ u32 nseries, u32 flags);
void ath9k_hw_set11n_burstduration(struct ath_hal *ah,
struct ath_desc *ds,
- u_int burstDuration);
+ u32 burstDuration);
void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
-u_int32_t ath9k_hw_reverse_bits(u_int32_t val, u_int32_t n);
-bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q);
-u_int ath9k_regd_get_ctl(struct ath_hal *ah, struct hal_channel *chan);
-u_int ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
- struct hal_channel *chan);
-u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags);
+u32 ath9k_hw_reverse_bits(u32 val, u32 n);
+bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q);
+u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
+u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
+ struct ath9k_channel *chan);
+u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
bool ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
- struct hal_txq_info *qInfo);
+ struct ath9k_txq_info *qInfo);
bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
- const struct hal_txq_info *qInfo);
-struct hal_channel_internal *ath9k_regd_check_channel(struct ath_hal *ah,
- const struct hal_channel *c);
+ const struct ath9k_txq_info *qInfo);
+struct ath9k_channel *ath9k_regd_check_channel(struct ath_hal *ah,
+ const struct ath9k_channel *c);
void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
- u_int pktLen, enum hal_pkt_type type,
- u_int txPower, u_int keyIx,
- enum hal_key_type keyType, u_int flags);
+ u32 pktLen, enum ath9k_pkt_type type,
+ u32 txPower, u32 keyIx,
+ enum ath9k_key_type keyType, u32 flags);
bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
- u_int segLen, bool firstSeg,
+ u32 segLen, bool firstSeg,
bool lastSeg,
const struct ath_desc *ds0);
-u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
- u_int32_t *rxc_pcnt,
- u_int32_t *rxf_pcnt,
- u_int32_t *txf_pcnt);
+u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
+ u32 *rxc_pcnt,
+ u32 *rxf_pcnt,
+ u32 *txf_pcnt);
void ath9k_hw_dmaRegDump(struct ath_hal *ah);
void ath9k_hw_beaconinit(struct ath_hal *ah,
- u_int32_t next_beacon, u_int32_t beacon_period);
+ u32 next_beacon, u32 beacon_period);
void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
- const struct hal_beacon_state *bs);
+ const struct ath9k_beacon_state *bs);
bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
- u_int32_t size, u_int flags);
-void ath9k_hw_putrxbuf(struct ath_hal *ah, u_int32_t rxdp);
+ u32 size, u32 flags);
+void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp);
void ath9k_hw_rxena(struct ath_hal *ah);
void ath9k_hw_setopmode(struct ath_hal *ah);
-bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac);
-void ath9k_hw_setmcastfilter(struct ath_hal *ah, u_int32_t filter0,
- u_int32_t filter1);
-u_int32_t ath9k_hw_getrxfilter(struct ath_hal *ah);
+bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
+void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0,
+ u32 filter1);
+u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
void ath9k_hw_startpcureceive(struct ath_hal *ah);
void ath9k_hw_stoppcurecv(struct ath_hal *ah);
bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
-enum hal_status ath9k_hw_rxprocdesc(struct ath_hal *ah,
- struct ath_desc *ds, u_int32_t pa,
- struct ath_desc *nds, u_int64_t tsf);
-u_int32_t ath9k_hw_gettxbuf(struct ath_hal *ah, u_int q);
-enum hal_status ath9k_hw_txprocdesc(struct ath_hal *ah,
- struct ath_desc *ds);
+int ath9k_hw_rxprocdesc(struct ath_hal *ah,
+ struct ath_desc *ds, u32 pa,
+ struct ath_desc *nds, u64 tsf);
+u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
+int ath9k_hw_txprocdesc(struct ath_hal *ah,
+ struct ath_desc *ds);
void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
- u_int numDelims);
+ u32 numDelims);
void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
- u_int aggrLen);
+ u32 aggrLen);
void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
-bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q);
-void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u_int32_t *txqs);
+bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
+void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
- struct ath_desc *ds, u_int vmf);
-bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit);
+ struct ath_desc *ds, u32 vmf);
+bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
-int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
- const struct hal_txq_info *qInfo);
-u_int32_t ath9k_hw_numtxpending(struct ath_hal *ah, u_int q);
-const char *ath9k_hw_probe(u_int16_t vendorid, u_int16_t devid);
+int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
+ const struct ath9k_txq_info *qInfo);
+u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
+const char *ath9k_hw_probe(u16 vendorid, u16 devid);
bool ath9k_hw_disable(struct ath_hal *ah);
void ath9k_hw_rfdetach(struct ath_hal *ah);
void ath9k_hw_get_channel_centers(struct ath_hal *ah,
- struct hal_channel_internal *chan,
+ struct ath9k_channel *chan,
struct chan_centers *centers);
bool ath9k_get_channel_edges(struct ath_hal *ah,
- u_int16_t flags, u_int16_t *low,
- u_int16_t *high);
-bool ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
- struct hal_channel *chans,
- u_int32_t nchans);
+ u16 flags, u16 *low,
+ u16 *high);
#endif
static int ath_beaconq_config(struct ath_softc *sc)
{
struct ath_hal *ah = sc->sc_ah;
- struct hal_txq_info qi;
+ struct ath9k_txq_info qi;
ath9k_hw_gettxqueueprops(ah, sc->sc_bhalq, &qi);
- if (sc->sc_opmode == HAL_M_HOSTAP) {
+ if (sc->sc_opmode == ATH9K_M_HOSTAP) {
/* Always burst out beacon and CAB traffic. */
qi.tqi_aifs = 1;
qi.tqi_cwmin = 0;
struct ath_hal *ah = sc->sc_ah;
struct ath_desc *ds;
int flags, antenna;
- const struct hal_rate_table *rt;
- u_int8_t rix, rate;
+ const struct ath9k_rate_table *rt;
+ u8 rix, rate;
int ctsrate = 0;
int ctsduration = 0;
- struct hal_11n_rate_series series[4];
+ struct ath9k_11n_rate_series series[4];
DPRINTF(sc, ATH_DBG_BEACON, "%s: m %p len %u\n",
__func__, skb, skb->len);
/* setup descriptors */
ds = bf->bf_desc;
- flags = HAL_TXDESC_NOACK;
+ flags = ATH9K_TXDESC_NOACK;
- if (sc->sc_opmode == HAL_M_IBSS && ah->ah_caps.halVEOLSupport) {
+ if (sc->sc_opmode == ATH9K_M_IBSS && ah->ah_caps.halVEOLSupport) {
ds->ds_link = bf->bf_daddr; /* self-linked */
- flags |= HAL_TXDESC_VEOL;
+ flags |= ATH9K_TXDESC_VEOL;
/* Let hardware handle antenna switching. */
antenna = 0;
} else {
ath9k_hw_set11n_txdesc(ah, ds
, skb->len + FCS_LEN /* frame length */
- , HAL_PKT_TYPE_BEACON /* Atheros packet type */
+ , ATH9K_PKT_TYPE_BEACON /* Atheros packet type */
, avp->av_btxctl.txpower /* txpower XXX */
- , HAL_TXKEYIX_INVALID /* no encryption */
- , HAL_KEY_TYPE_CLEAR /* no encryption */
+ , ATH9K_TXKEYIX_INVALID /* no encryption */
+ , ATH9K_KEY_TYPE_CLEAR /* no encryption */
, flags /* no ack, veol for beacons */
);
, ds /* first descriptor */
);
- memzero(series, sizeof(struct hal_11n_rate_series) * 4);
+ memzero(series, sizeof(struct ath9k_11n_rate_series) * 4);
series[0].Tries = 1;
series[0].Rate = rate;
series[0].ChSel = sc->sc_tx_chainmask;
- series[0].RateFlags = (ctsrate) ? HAL_RATESERIES_RTS_CTS : 0;
+ series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0;
ath9k_hw_set11n_ratescenario(ah, ds, ds, 0,
ctsrate, ctsduration, series, 4, 0);
}
/*
* Setup a h/w transmit queue for beacons.
*
- * This function allocates an information structure (struct hal_txq_info)
+ * This function allocates an information structure (struct ath9k_txq_info)
* on the stack, sets some specific parameters (zero out channel width
* min/max, and enable aifs). The info structure does not need to be
* persistant.
int ath_beaconq_setup(struct ath_hal *ah)
{
- struct hal_txq_info qi;
+ struct ath9k_txq_info qi;
memzero(&qi, sizeof(qi));
qi.tqi_aifs = 1;
qi.tqi_cwmin = 0;
qi.tqi_cwmax = 0;
/* NB: don't enable any interrupts */
- return ath9k_hw_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
+ return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
}
struct ath_buf, list);
list_del(&avp->av_bcbuf->list);
- if (sc->sc_opmode == HAL_M_HOSTAP ||
+ if (sc->sc_opmode == ATH9K_M_HOSTAP ||
!sc->sc_ah->ah_caps.halVEOLSupport) {
int slot;
/*
* following the header.
*/
if (avp->av_bslot > 0) {
- u_int64_t tsfadjust;
+ u64 tsfadjust;
__le64 val;
int intval;
void ath9k_beacon_tasklet(unsigned long data)
{
#define TSF_TO_TU(_h,_l) \
- ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
+ ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
struct ath_softc *sc = (struct ath_softc *)data;
struct ath_hal *ah = sc->sc_ah;
struct ath_buf *bf = NULL;
int slot, if_id;
- u_int32_t bfaddr;
- u_int32_t rx_clear = 0, rx_frame = 0, tx_frame = 0;
- u_int32_t show_cycles = 0;
- u_int32_t bc = 0; /* beacon count */
- u_int64_t tsf;
- u_int32_t tsftu;
- u_int16_t intval;
+ u32 bfaddr;
+ u32 rx_clear = 0, rx_frame = 0, tx_frame = 0;
+ u32 show_cycles = 0;
+ u32 bc = 0; /* beacon count */
+ u64 tsf;
+ u32 tsftu;
+ u16 intval;
if (sc->sc_noreset) {
show_cycles = ath9k_hw_GetMibCycleCountsPct(ah,
void ath_beacon_config(struct ath_softc *sc, int if_id)
{
#define TSF_TO_TU(_h,_l) \
- ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
+ ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
struct ath_hal *ah = sc->sc_ah;
- u_int32_t nexttbtt, intval;
+ u32 nexttbtt, intval;
struct ath_beacon_config conf;
- enum hal_opmode av_opmode;
+ enum ath9k_opmode av_opmode;
if (if_id != ATH_IF_ID_ANY)
av_opmode = sc->sc_vaps[if_id]->av_opmode;
nexttbtt = TSF_TO_TU(LE_READ_4(conf.u.last_tstamp + 4),
LE_READ_4(conf.u.last_tstamp));
/* XXX conditionalize multi-bss support? */
- if (sc->sc_opmode == HAL_M_HOSTAP) {
+ if (sc->sc_opmode == ATH9K_M_HOSTAP) {
/*
* For multi-bss ap support beacons are either staggered
* evenly over N slots or burst together. For the former
* Slots that are not occupied will generate nothing.
*/
/* NB: the beacon interval is kept internally in TU's */
- intval = conf.beacon_interval & HAL_BEACON_PERIOD;
+ intval = conf.beacon_interval & ATH9K_BEACON_PERIOD;
intval /= ATH_BCBUF; /* for staggered beacons */
} else {
- intval = conf.beacon_interval & HAL_BEACON_PERIOD;
+ intval = conf.beacon_interval & ATH9K_BEACON_PERIOD;
}
if (nexttbtt == 0) /* e.g. for ap mode */
nexttbtt = roundup(nexttbtt, intval);
DPRINTF(sc, ATH_DBG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
__func__, nexttbtt, intval, conf.beacon_interval);
- /* Check for HAL_M_HOSTAP and sc_nostabeacons for WDS client */
- if (sc->sc_opmode == HAL_M_STA) {
- struct hal_beacon_state bs;
- u_int64_t tsf;
- u_int32_t tsftu;
+ /* Check for ATH9K_M_HOSTAP and sc_nostabeacons for WDS client */
+ if (sc->sc_opmode == ATH9K_M_STA) {
+ struct ath9k_beacon_state bs;
+ u64 tsf;
+ u32 tsftu;
int dtimperiod, dtimcount, sleepduration;
int cfpperiod, cfpcount;
ath9k_hw_set_interrupts(ah, 0);
ath9k_hw_set_sta_beacon_timers(ah, &bs);
- sc->sc_imask |= HAL_INT_BMISS;
+ sc->sc_imask |= ATH9K_INT_BMISS;
ath9k_hw_set_interrupts(ah, sc->sc_imask);
} else {
- u_int64_t tsf;
- u_int32_t tsftu;
+ u64 tsf;
+ u32 tsftu;
ath9k_hw_set_interrupts(ah, 0);
if (nexttbtt == intval)
- intval |= HAL_BEACON_RESET_TSF;
- if (sc->sc_opmode == HAL_M_IBSS) {
+ intval |= ATH9K_BEACON_RESET_TSF;
+ if (sc->sc_opmode == ATH9K_M_IBSS) {
/*
* Pull nexttbtt forward to reflect the current
* TSF .
*/
#define FUDGE 2
- if (!(intval & HAL_BEACON_RESET_TSF)) {
+ if (!(intval & ATH9K_BEACON_RESET_TSF)) {
tsf = ath9k_hw_gettsf64(ah);
- tsftu = TSF_TO_TU((u_int32_t)(tsf>>32),
- (u_int32_t)tsf) + FUDGE;
+ tsftu = TSF_TO_TU((u32)(tsf>>32),
+ (u32)tsf) + FUDGE;
do {
nexttbtt += intval;
} while (nexttbtt < tsftu);
DPRINTF(sc, ATH_DBG_BEACON,
"%s: IBSS nexttbtt %u intval %u (%u)\n",
__func__, nexttbtt,
- intval & ~HAL_BEACON_RESET_TSF,
+ intval & ~ATH9K_BEACON_RESET_TSF,
conf.beacon_interval);
/*
* self-linked tx descriptor and let the hardware
* deal with things.
*/
- intval |= HAL_BEACON_ENA;
+ intval |= ATH9K_BEACON_ENA;
if (!ah->ah_caps.halVEOLSupport)
- sc->sc_imask |= HAL_INT_SWBA;
+ sc->sc_imask |= ATH9K_INT_SWBA;
ath_beaconq_config(sc);
- } else if (sc->sc_opmode == HAL_M_HOSTAP) {
+ } else if (sc->sc_opmode == ATH9K_M_HOSTAP) {
/*
* In AP mode we enable the beacon timers and
* SWBA interrupts to prepare beacon frames.
*/
- intval |= HAL_BEACON_ENA;
- sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
+ intval |= ATH9K_BEACON_ENA;
+ sc->sc_imask |= ATH9K_INT_SWBA; /* beacon prepare */
ath_beaconq_config(sc);
}
ath9k_hw_beaconinit(ah, nexttbtt, intval);
* When using a self-linked beacon descriptor in
* ibss mode load it once here.
*/
- if (sc->sc_opmode == HAL_M_IBSS && ah->ah_caps.halVEOLSupport)
+ if (sc->sc_opmode == ATH9K_M_IBSS && ah->ah_caps.halVEOLSupport)
ath_beacon_start_adhoc(sc, 0);
}
#undef TSF_TO_TU
static int ath_outdoor; /* enable outdoor use */
-static const u_int8_t ath_bcast_mac[ETH_ALEN] =
+static const u8 ath_bcast_mac[ETH_ALEN] =
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
-static u_int32_t ath_chainmask_sel_up_rssi_thres =
+static u32 ath_chainmask_sel_up_rssi_thres =
ATH_CHAINMASK_SEL_UP_RSSI_THRES;
-static u_int32_t ath_chainmask_sel_down_rssi_thres =
+static u32 ath_chainmask_sel_down_rssi_thres =
ATH_CHAINMASK_SEL_DOWN_RSSI_THRES;
-static u_int32_t ath_chainmask_sel_period =
+static u32 ath_chainmask_sel_period =
ATH_CHAINMASK_SEL_TIMEOUT;
/* return bus cachesize in 4B word units */
static void bus_read_cachesize(struct ath_softc *sc, int *csz)
{
- u_int8_t u8tmp;
+ u8 u8tmp;
- pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u_int8_t *)&u8tmp);
+ pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
*csz = (int)u8tmp;
/*
static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
{
- const struct hal_rate_table *rt;
+ const struct ath9k_rate_table *rt;
int i;
memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
BUG_ON(!rt);
for (i = 0; i < rt->rateCount; i++)
- sc->sc_rixmap[rt->info[i].rateCode] = (u_int8_t) i;
+ sc->sc_rixmap[rt->info[i].rateCode] = (u8) i;
memzero(sc->sc_hwmap, sizeof(sc->sc_hwmap));
for (i = 0; i < 256; i++) {
- u_int8_t ix = rt->rateCodeToIndex[i];
+ u8 ix = rt->rateCodeToIndex[i];
if (ix == 0xff)
continue;
static int ath_rate_setup(struct ath_softc *sc, enum wireless_mode mode)
{
struct ath_hal *ah = sc->sc_ah;
- const struct hal_rate_table *rt;
+ const struct ath9k_rate_table *rt;
switch (mode) {
case WIRELESS_MODE_11a:
/*
* Set up channel list
- *
- * Determines the proper set of channelflags based on the selected mode,
- * allocates a channel array, and passes it to the HAL for initialization.
- * If successful, the list is passed to the upper layer, then de-allocated.
-*/
-
-static int ath_getchannels(struct ath_softc *sc,
- u_int cc,
- bool outDoor,
- bool xchanMode)
+ */
+static int ath_setup_channels(struct ath_softc *sc)
{
struct ath_hal *ah = sc->sc_ah;
- struct hal_channel *chans;
- int nchan;
- u_int8_t regclassids[ATH_REGCLASSIDS_MAX];
- u_int nregclass = 0;
-
- chans = kmalloc(ATH_CHAN_MAX * sizeof(struct hal_channel), GFP_KERNEL);
- if (chans == NULL) {
- DPRINTF(sc, ATH_DBG_FATAL,
- "%s: unable to allocate channel table\n", __func__);
- return -ENOMEM;
- }
-
+ int nchan, i, a = 0, b = 0;
+ u8 regclassids[ATH_REGCLASSIDS_MAX];
+ u32 nregclass = 0;
+ struct ieee80211_supported_band *band_2ghz;
+ struct ieee80211_supported_band *band_5ghz;
+ struct ieee80211_channel *chan_2ghz;
+ struct ieee80211_channel *chan_5ghz;
+ struct ath9k_channel *c;
+
+ /* Fill in ah->ah_channels */
if (!ath9k_regd_init_channels(ah,
- chans,
ATH_CHAN_MAX,
- (u_int *)&nchan,
+ (u32 *)&nchan,
regclassids,
ATH_REGCLASSIDS_MAX,
&nregclass,
- cc,
+ CTRY_DEFAULT,
ATH9K_MODE_SEL_ALL,
- outDoor,
- xchanMode)) {
- u_int32_t rd = ah->ah_currentRD;
+ false,
+ 1)) {
+ u32 rd = ah->ah_currentRD;
DPRINTF(sc, ATH_DBG_FATAL,
- "%s: unable to collect channel list from hal; "
+ "%s: unable to collect channel list; "
"regdomain likely %u country code %u\n",
- __func__, rd, cc);
- kfree(chans);
+ __func__, rd, CTRY_DEFAULT);
return -EINVAL;
}
- ath_setup_channel_list(sc,
- CLIST_UPDATE,
- chans,
- nchan,
- regclassids,
- nregclass,
- CTRY_DEFAULT);
+ band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
+ band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
+ chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
+ chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
+
+ for (i = 0; i < nchan; i++) {
+ c = &ah->ah_channels[i];
+ if (IS_CHAN_2GHZ(c)) {
+ chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
+ chan_2ghz[a].center_freq = c->channel;
+ chan_2ghz[a].max_power = c->maxTxPower;
+
+ if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
+ chan_2ghz[a].flags |=
+ IEEE80211_CHAN_NO_IBSS;
+ if (c->channelFlags & CHANNEL_PASSIVE)
+ chan_2ghz[a].flags |=
+ IEEE80211_CHAN_PASSIVE_SCAN;
+
+ band_2ghz->n_channels = ++a;
+
+ DPRINTF(sc, ATH_DBG_CONFIG,
+ "%s: 2MHz channel: %d, "
+ "channelFlags: 0x%x\n",
+ __func__,
+ c->channel,
+ c->channelFlags);
+ } else if (IS_CHAN_5GHZ(c)) {
+ chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
+ chan_5ghz[b].center_freq = c->channel;
+ chan_5ghz[b].max_power = c->maxTxPower;
+
+ if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
+ chan_5ghz[b].flags |=
+ IEEE80211_CHAN_NO_IBSS;
+ if (c->channelFlags & CHANNEL_PASSIVE)
+ chan_5ghz[b].flags |=
+ IEEE80211_CHAN_PASSIVE_SCAN;
+
+ band_5ghz->n_channels = ++b;
+
+ DPRINTF(sc, ATH_DBG_CONFIG,
+ "%s: 5MHz channel: %d, "
+ "channelFlags: 0x%x\n",
+ __func__,
+ c->channel,
+ c->channelFlags);
+ }
+ }
- kfree(chans);
return 0;
}
* exist, the lowest mode (11b) is selected.
*/
-static enum wireless_mode ath_chan2mode(struct hal_channel *chan)
+static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
{
- if ((chan->channelFlags & CHANNEL_A) == CHANNEL_A)
+ if (chan->chanmode == CHANNEL_A)
return WIRELESS_MODE_11a;
- else if ((chan->channelFlags & CHANNEL_G) == CHANNEL_G)
+ else if (chan->chanmode == CHANNEL_G)
return WIRELESS_MODE_11g;
- else if ((chan->channelFlags & CHANNEL_B) == CHANNEL_B)
+ else if (chan->chanmode == CHANNEL_B)
return WIRELESS_MODE_11b;
- else if ((chan->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20)
+ else if (chan->chanmode == CHANNEL_A_HT20)
return WIRELESS_MODE_11NA_HT20;
- else if ((chan->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20)
+ else if (chan->chanmode == CHANNEL_G_HT20)
return WIRELESS_MODE_11NG_HT20;
- else if ((chan->channelFlags & CHANNEL_A_HT40PLUS) ==
- CHANNEL_A_HT40PLUS)
+ else if (chan->chanmode == CHANNEL_A_HT40PLUS)
return WIRELESS_MODE_11NA_HT40PLUS;
- else if ((chan->channelFlags & CHANNEL_A_HT40MINUS) ==
- CHANNEL_A_HT40MINUS)
+ else if (chan->chanmode == CHANNEL_A_HT40MINUS)
return WIRELESS_MODE_11NA_HT40MINUS;
- else if ((chan->channelFlags & CHANNEL_G_HT40PLUS) ==
- CHANNEL_G_HT40PLUS)
+ else if (chan->chanmode == CHANNEL_G_HT40PLUS)
return WIRELESS_MODE_11NG_HT40PLUS;
- else if ((chan->channelFlags & CHANNEL_G_HT40MINUS) ==
- CHANNEL_G_HT40MINUS)
+ else if (chan->chanmode == CHANNEL_G_HT40MINUS)
return WIRELESS_MODE_11NG_HT40MINUS;
/* NB: should not get here */
* the current operating mode for the new channel.
*/
-static void ath_chan_change(struct ath_softc *sc, struct hal_channel *chan)
+static void ath_chan_change(struct ath_softc *sc, struct ath9k_channel *chan)
{
enum wireless_mode mode;
void ath_scan_start(struct ath_softc *sc)
{
struct ath_hal *ah = sc->sc_ah;
- u_int32_t rfilt;
- u_int32_t now = (u_int32_t) jiffies_to_msecs(get_timestamp());
+ u32 rfilt;
+ u32 now = (u32) jiffies_to_msecs(get_timestamp());
sc->sc_scanning = 1;
rfilt = ath_calcrxfilter(sc);
void ath_scan_end(struct ath_softc *sc)
{
struct ath_hal *ah = sc->sc_ah;
- u_int32_t rfilt;
- u_int32_t now = (u_int32_t) jiffies_to_msecs(get_timestamp());
+ u32 rfilt;
+ u32 now = (u32) jiffies_to_msecs(get_timestamp());
sc->sc_scanning = 0;
/* Request for a full reset due to rx packet filter changes */
* by reseting the chip. To accomplish this we must first cleanup any pending
* DMA, then restart stuff after a la ath_init.
*/
-int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
+int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
{
struct ath_hal *ah = sc->sc_ah;
bool fastcc = true, stopped;
- enum hal_ht_macmode ht_macmode;
+ enum ath9k_ht_macmode ht_macmode;
if (sc->sc_invalid) /* if the device is invalid or removed */
return -EIO;
if (hchan->channel != sc->sc_curchan.channel ||
hchan->channelFlags != sc->sc_curchan.channelFlags ||
sc->sc_update_chainmask || sc->sc_full_reset) {
- enum hal_status status;
+ int status;
/*
* This is only performed if the channel settings have
* actually changed.
{
struct ath_hal *ah = sc->sc_ah;
struct ath_vap *avp;
- u_int32_t rfilt = 0;
+ u32 rfilt = 0;
DECLARE_MAC_BUF(mac);
avp = sc->sc_vaps[if_id];
#endif
/* update ratectrl about the new state */
- ath_rate_newstate(sc, avp, 0);
+ ath_rate_newstate(sc, avp);
rfilt = ath_calcrxfilter(sc);
ath9k_hw_setrxfilter(ah, rfilt);
- if (sc->sc_opmode == HAL_M_STA || sc->sc_opmode == HAL_M_IBSS) {
+ if (sc->sc_opmode == ATH9K_M_STA || sc->sc_opmode == ATH9K_M_IBSS) {
memcpy(sc->sc_curbssid, ath_bcast_mac, ETH_ALEN);
ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
} else
* Disable BMISS interrupt when we're not associated
*/
ath9k_hw_set_interrupts(ah,
- sc->sc_imask & ~(HAL_INT_SWBA | HAL_INT_BMISS));
- sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
+ sc->sc_imask & ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
+ sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
/* need to reconfigure the beacons when it moves to RUN */
sc->sc_beacons = 0;
int ath_vap_attach(struct ath_softc *sc,
int if_id,
struct ieee80211_vif *if_data,
- enum hal_opmode opmode)
+ enum ath9k_opmode opmode)
{
struct ath_vap *avp;
}
switch (opmode) {
- case HAL_M_STA:
- case HAL_M_IBSS:
- case HAL_M_MONITOR:
+ case ATH9K_M_STA:
+ case ATH9K_M_IBSS:
+ case ATH9K_M_MONITOR:
break;
- case HAL_M_HOSTAP:
+ case ATH9K_M_HOSTAP:
/* XXX not right, beacon buffer is allocated on RUN trans */
if (list_empty(&sc->sc_bbuf))
return -ENOMEM;
/* Core */
/********/
-int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
+int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan)
{
struct ath_hal *ah = sc->sc_ah;
- enum hal_status status;
+ int status;
int error = 0;
- enum hal_ht_macmode ht_macmode = ath_cwm_macmode(sc);
+ enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
DPRINTF(sc, ATH_DBG_CONFIG, "%s: mode %d\n", __func__, sc->sc_opmode);
goto done;
}
/* Setup our intr mask. */
- sc->sc_imask = HAL_INT_RX | HAL_INT_TX
- | HAL_INT_RXEOL | HAL_INT_RXORN
- | HAL_INT_FATAL | HAL_INT_GLOBAL;
+ sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
+ | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
+ | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
if (ah->ah_caps.halGTTSupport)
- sc->sc_imask |= HAL_INT_GTT;
+ sc->sc_imask |= ATH9K_INT_GTT;
if (ah->ah_caps.halHTSupport)
- sc->sc_imask |= HAL_INT_CST;
+ sc->sc_imask |= ATH9K_INT_CST;
/*
* Enable MIB interrupts when there are hardware phy counters.
* Note we only do this (at the moment) for station mode.
*/
if (ath9k_hw_phycounters(ah) &&
- ((sc->sc_opmode == HAL_M_STA) || (sc->sc_opmode == HAL_M_IBSS)))
- sc->sc_imask |= HAL_INT_MIB;
+ ((sc->sc_opmode == ATH9K_M_STA) || (sc->sc_opmode == ATH9K_M_IBSS)))
+ sc->sc_imask |= ATH9K_INT_MIB;
/*
* Some hardware processes the TIM IE and fires an
* interrupt when the TIM bit is set. For hardware
* that does, if not overridden by configuration,
* enable the TIM interrupt when operating as station.
*/
- if (ah->ah_caps.halEnhancedPmSupport && sc->sc_opmode == HAL_M_STA &&
+ if (ah->ah_caps.halEnhancedPmSupport && sc->sc_opmode == ATH9K_M_STA &&
!sc->sc_config.swBeaconProcess)
- sc->sc_imask |= HAL_INT_TIM;
+ sc->sc_imask |= ATH9K_INT_TIM;
/*
* Don't enable interrupts here as we've not yet built our
* vap and node data structures, which will be needed as soon
* and to reset the hardware when rf gain settings must be reset.
*/
-static int ath_reset_start(struct ath_softc *sc, u_int32_t flag)
+static int ath_reset_start(struct ath_softc *sc, u32 flag)
{
struct ath_hal *ah = sc->sc_ah;
return 0;
}
-static int ath_reset_end(struct ath_softc *sc, u_int32_t flag)
+static int ath_reset_end(struct ath_softc *sc, u32 flag)
{
struct ath_hal *ah = sc->sc_ah;
/* Restart the txq */
if (flag & RESET_RETRY_TXQ) {
int i;
- for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
+ for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
if (ATH_TXQ_SETUP(sc, i)) {
spin_lock_bh(&sc->sc_txq[i].axq_lock);
ath_txq_schedule(sc, &sc->sc_txq[i]);
int ath_reset(struct ath_softc *sc)
{
struct ath_hal *ah = sc->sc_ah;
- enum hal_status status;
+ int status;
int error = 0;
- enum hal_ht_macmode ht_macmode = ath_cwm_macmode(sc);
+ enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
/* NB: indicate channel change so we do a full reset */
spin_lock_bh(&sc->sc_resetlock);
{
struct ath_softc *sc = dev;
struct ath_hal *ah = sc->sc_ah;
- enum hal_int status;
+ enum ath9k_int status;
bool sched = false;
do {
sc->sc_intrstatus = status;
- if (status & HAL_INT_FATAL) {
+ if (status & ATH9K_INT_FATAL) {
/* need a chip reset */
sched = true;
- } else if (status & HAL_INT_RXORN) {
+ } else if (status & ATH9K_INT_RXORN) {
/* need a chip reset */
sched = true;
} else {
- if (status & HAL_INT_SWBA) {
+ if (status & ATH9K_INT_SWBA) {
/* schedule a tasklet for beacon handling */
tasklet_schedule(&sc->bcon_tasklet);
}
- if (status & HAL_INT_RXEOL) {
+ if (status & ATH9K_INT_RXEOL) {
/*
* NB: the hardware should re-read the link when
* RXE bit is written, but it doesn't work
sched = true;
}
- if (status & HAL_INT_TXURN)
+ if (status & ATH9K_INT_TXURN)
/* bump tx trigger level */
ath9k_hw_updatetxtriglevel(ah, true);
/* XXX: optimize this */
- if (status & HAL_INT_RX)
+ if (status & ATH9K_INT_RX)
sched = true;
- if (status & HAL_INT_TX)
+ if (status & ATH9K_INT_TX)
sched = true;
- if (status & HAL_INT_BMISS)
+ if (status & ATH9K_INT_BMISS)
sched = true;
/* carrier sense timeout */
- if (status & HAL_INT_CST)
+ if (status & ATH9K_INT_CST)
sched = true;
- if (status & HAL_INT_MIB) {
+ if (status & ATH9K_INT_MIB) {
/*
* Disable interrupts until we service the MIB
* interrupt; otherwise it will continue to
ath9k_hw_procmibevent(ah, &sc->sc_halstats);
ath9k_hw_set_interrupts(ah, sc->sc_imask);
}
- if (status & HAL_INT_TIM_TIMER) {
+ if (status & ATH9K_INT_TIM_TIMER) {
if (!ah->ah_caps.halAutoSleepSupport) {
/* Clear RxAbort bit so that we can
* receive frames */
if (sched) {
/* turn off every interrupt except SWBA */
- ath9k_hw_set_interrupts(ah, (sc->sc_imask & HAL_INT_SWBA));
+ ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
tasklet_schedule(&sc->intr_tq);
}
static void ath9k_tasklet(unsigned long data)
{
struct ath_softc *sc = (struct ath_softc *)data;
- u_int32_t status = sc->sc_intrstatus;
+ u32 status = sc->sc_intrstatus;
- if (status & HAL_INT_FATAL) {
+ if (status & ATH9K_INT_FATAL) {
/* need a chip reset */
ath_internal_reset(sc);
return;
} else {
- if (status & (HAL_INT_RX | HAL_INT_RXEOL | HAL_INT_RXORN)) {
+ if (status &
+ (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
/* XXX: fill me in */
/*
- if (status & HAL_INT_RXORN) {
+ if (status & ATH9K_INT_RXORN) {
}
- if (status & HAL_INT_RXEOL) {
+ if (status & ATH9K_INT_RXEOL) {
}
*/
spin_lock_bh(&sc->sc_rxflushlock);
spin_unlock_bh(&sc->sc_rxflushlock);
}
/* XXX: optimize this */
- if (status & HAL_INT_TX)
+ if (status & ATH9K_INT_TX)
ath_tx_tasklet(sc);
/* XXX: fill me in */
/*
- if (status & HAL_INT_BMISS) {
+ if (status & ATH9K_INT_BMISS) {
}
- if (status & (HAL_INT_TIM | HAL_INT_DTIMSYNC)) {
- if (status & HAL_INT_TIM) {
+ if (status & (ATH9K_INT_TIM | ATH9K_INT_DTIMSYNC)) {
+ if (status & ATH9K_INT_TIM) {
}
- if (status & HAL_INT_DTIMSYNC) {
+ if (status & ATH9K_INT_DTIMSYNC) {
}
}
*/
ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
}
-int ath_init(u_int16_t devid, struct ath_softc *sc)
+int ath_init(u16 devid, struct ath_softc *sc)
{
struct ath_hal *ah = NULL;
- enum hal_status status;
+ int status;
int error = 0, i;
int csz = 0;
- u_int32_t rd;
+ u32 rd;
/* XXX: hardware will not be ready until ath_open() being called */
sc->sc_invalid = 1;
* reset the contents on initial power up.
*/
for (i = 0; i < sc->sc_keymax; i++)
- ath9k_hw_keyreset(ah, (u_int16_t) i);
+ ath9k_hw_keyreset(ah, (u16) i);
/*
* Mark key cache slots associated with global keys
* as in use. If we knew TKIP was not to be used we
*/
rd = ah->ah_currentRD;
- error = ath_getchannels(sc,
- CTRY_DEFAULT,
- ath_outdoor,
- 1);
+ error = ath_setup_channels(sc);
if (error)
goto bad;
/* default to STA mode */
- sc->sc_opmode = HAL_M_MONITOR;
+ sc->sc_opmode = ATH9K_M_MONITOR;
/* Setup rate tables for all potential media types. */
/* 11g encompasses b,g */
error = -EIO;
goto bad2;
}
- sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
+ sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
if (sc->sc_cabq == NULL) {
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to setup CAB xmit queue\n", __func__);
/* Setup data queues */
/* NB: ensure BK queue is the lowest priority h/w queue */
- if (!ath_tx_setup(sc, HAL_WME_AC_BK)) {
+ if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to setup xmit queue for BK traffic\n",
__func__);
goto bad2;
}
- if (!ath_tx_setup(sc, HAL_WME_AC_BE)) {
+ if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to setup xmit queue for BE traffic\n",
__func__);
error = -EIO;
goto bad2;
}
- if (!ath_tx_setup(sc, HAL_WME_AC_VI)) {
+ if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to setup xmit queue for VI traffic\n",
__func__);
error = -EIO;
goto bad2;
}
- if (!ath_tx_setup(sc, HAL_WME_AC_VO)) {
+ if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
DPRINTF(sc, ATH_DBG_FATAL,
"%s: unable to setup xmit queue for VO traffic\n",
__func__);
goto bad2;
}
- if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER, HAL_CIPHER_TKIP, NULL)) {
+ if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
+ ATH9K_CIPHER_TKIP, NULL)) {
/*
* Whether we should enable h/w TKIP MIC.
* XXX: if we don't support WME TKIP MIC, then we wouldn't
* With split mic keys the number of stations is limited
* to 27 otherwise 59.
*/
- if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER, HAL_CIPHER_TKIP, NULL)
- && ath9k_hw_getcapability(ah, HAL_CAP_CIPHER, HAL_CIPHER_MIC, NULL)
- && ath9k_hw_getcapability(ah, HAL_CAP_TKIP_SPLIT, 0, NULL))
+ if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
+ ATH9K_CIPHER_TKIP, NULL)
+ && ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
+ ATH9K_CIPHER_MIC, NULL)
+ && ath9k_hw_getcapability(ah, HAL_CAP_TKIP_SPLIT,
+ 0, NULL))
sc->sc_splitmic = 1;
/* turn on mcast key search if possible */
- if (ath9k_hw_getcapability(ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL)
- == HAL_OK)
+ if (!ath9k_hw_getcapability(ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL))
(void)ath9k_hw_setcapability(ah, HAL_CAP_MCAST_KEYSRCH, 1,
1, NULL);
ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
}
- sc->sc_slottime = HAL_SLOT_TIME_9; /* default to short slot time */
+ sc->sc_slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
/* initialize beacon slots */
for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
return 0;
bad2:
/* cleanup tx queues */
- for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
+ for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
if (ATH_TXQ_SETUP(sc, i))
ath_tx_cleanupq(sc, &sc->sc_txq[i]);
bad:
ath_stop(sc);
if (!sc->sc_invalid)
- ath9k_hw_setpower(sc->sc_ah, HAL_PM_AWAKE);
+ ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
ath_rate_detach(sc->sc_rc);
/* cleanup tx queues */
- for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
+ for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
if (ATH_TXQ_SETUP(sc, i))
ath_tx_cleanupq(sc, &sc->sc_txq[i]);
ath9k_hw_detach(ah);
/* Encryption */
/**************/
-void ath_key_reset(struct ath_softc *sc, u_int16_t keyix, int freeslot)
+void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
{
ath9k_hw_keyreset(sc->sc_ah, keyix);
if (freeslot)
}
int ath_keyset(struct ath_softc *sc,
- u_int16_t keyix,
- struct hal_keyval *hk,
- const u_int8_t mac[ETH_ALEN])
+ u16 keyix,
+ struct ath9k_keyval *hk,
+ const u8 mac[ETH_ALEN])
{
bool status;
void ath_update_txpow(struct ath_softc *sc)
{
struct ath_hal *ah = sc->sc_ah;
- u_int32_t txpow;
+ u32 txpow;
if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
/* Return the current country and domain information */
void ath_get_currentCountry(struct ath_softc *sc,
- struct hal_country_entry *ctry)
+ struct ath9k_country_entry *ctry)
{
ath9k_regd_get_current_country(sc->sc_ah, ctry);
}
void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
- u_int8_t num_antcfg,
- const u_int8_t *bssid)
+ u8 num_antcfg,
+ const u8 *bssid)
{
antdiv->antdiv_num_antcfg =
num_antcfg < ATH_ANT_DIV_MAX_CFG ?
}
static int32_t ath_find_max_val(int32_t *val,
- u_int8_t num_val, u_int8_t *max_index)
+ u8 num_val, u8 *max_index)
{
- u_int32_t MaxVal = *val++;
- u_int32_t cur_index = 0;
+ u32 MaxVal = *val++;
+ u32 cur_index = 0;
*max_index = 0;
while (++cur_index < num_val) {
{
struct ath_softc *sc = antdiv->antdiv_sc;
struct ath_hal *ah = sc->sc_ah;
- u_int64_t curtsf = 0;
- u_int8_t bestcfg, curcfg = antdiv->antdiv_curcfg;
+ u64 curtsf = 0;
+ u8 bestcfg, curcfg = antdiv->antdiv_curcfg;
__le16 fc = hdr->frame_control;
if (antdiv->antdiv_start && ieee80211_is_beacon(fc)
if (curcfg == antdiv->antdiv_num_antcfg)
curcfg = 0;
- if (HAL_OK == ath9k_hw_select_antconfig(ah, curcfg)) {
+ if (!ath9k_hw_select_antconfig(ah, curcfg)) {
antdiv->antdiv_bestcfg = antdiv->antdiv_curcfg;
antdiv->antdiv_curcfg = curcfg;
antdiv->antdiv_laststatetsf = curtsf;
if (curcfg == antdiv->antdiv_bestcfg) {
ath_find_max_val(antdiv->antdiv_lastbrssi,
antdiv->antdiv_num_antcfg, &bestcfg);
- if (HAL_OK == ath9k_hw_select_antconfig(ah, bestcfg)) {
+ if (!ath9k_hw_select_antconfig(ah, bestcfg)) {
antdiv->antdiv_bestcfg = bestcfg;
antdiv->antdiv_curcfg = bestcfg;
antdiv->antdiv_laststatetsf = curtsf;
antdiv->antdiv_state = ATH_ANT_DIV_IDLE;
}
} else {
- if (HAL_OK == ath9k_hw_select_antconfig(ah, curcfg)) {
+ if (!ath9k_hw_select_antconfig(ah, curcfg)) {
antdiv->antdiv_curcfg = curcfg;
antdiv->antdiv_laststatetsf = curtsf;
antdiv->antdiv_state = ATH_ANT_DIV_SCAN;
* one skipped descriptor per 4K page.
*/
if (!(sc->sc_ah->ah_caps.hal4kbSplitTransSupport)) {
- u_int32_t ndesc_skipped =
+ u32 ndesc_skipped =
ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
- u_int32_t dma_len;
+ u32 dma_len;
while (ndesc_skipped) {
dma_len = ndesc_skipped * sizeof(struct ath_desc);
}
ds = dd->dd_desc;
DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
- __func__, dd->dd_name, ds, (u_int32_t) dd->dd_desc_len,
- ito64(dd->dd_desc_paddr), /*XXX*/(u_int32_t) dd->dd_desc_len);
+ __func__, dd->dd_name, ds, (u32) dd->dd_desc_len,
+ ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
/* allocate buffers */
bsize = sizeof(struct ath_buf) * nbuf;
switch (queue) {
case 0:
- qnum = sc->sc_haltype2q[HAL_WME_AC_VO];
+ qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO];
break;
case 1:
- qnum = sc->sc_haltype2q[HAL_WME_AC_VI];
+ qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI];
break;
case 2:
- qnum = sc->sc_haltype2q[HAL_WME_AC_BE];
+ qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
break;
case 3:
- qnum = sc->sc_haltype2q[HAL_WME_AC_BK];
+ qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK];
break;
default:
- qnum = sc->sc_haltype2q[HAL_WME_AC_BE];
+ qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
break;
}
return qnum;
}
-int ath_get_mac80211_qnum(u_int queue, struct ath_softc *sc)
+int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
{
int qnum;
switch (queue) {
- case HAL_WME_AC_VO:
+ case ATH9K_WME_AC_VO:
qnum = 0;
break;
- case HAL_WME_AC_VI:
+ case ATH9K_WME_AC_VI:
qnum = 1;
break;
- case HAL_WME_AC_BE:
+ case ATH9K_WME_AC_BE:
qnum = 2;
break;
- case HAL_WME_AC_BK:
+ case ATH9K_WME_AC_BK:
qnum = 3;
break;
default:
* a full 64-bit TSF using the current h/w TSF.
*/
-u_int64_t ath_extend_tsf(struct ath_softc *sc, u_int32_t rstamp)
+u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp)
{
- u_int64_t tsf;
+ u64 tsf;
tsf = ath9k_hw_gettsf64(sc->sc_ah);
if ((tsf & 0x7fff) < rstamp)
* MIMO technology.
*/
-void ath_setdefantenna(void *context, u_int antenna)
+void ath_setdefantenna(void *context, u32 antenna)
{
struct ath_softc *sc = (struct ath_softc *)context;
struct ath_hal *ah = sc->sc_ah;
/* Per-instance load-time (note: NOT run-time) configurations
* for Atheros Device */
struct ath_config {
- u_int32_t ath_aggr_prot;
- u_int16_t txpowlimit;
- u_int16_t txpowlimit_override;
- u_int8_t cabqReadytime; /* Cabq Readytime % */
- u_int8_t swBeaconProcess; /* Process received beacons
+ u32 ath_aggr_prot;
+ u16 txpowlimit;
+ u16 txpowlimit_override;
+ u8 cabqReadytime; /* Cabq Readytime % */
+ u8 swBeaconProcess; /* Process received beacons
in SW (vs HW) */
};
struct ath_buf_state {
int bfs_nframes; /* # frames in aggregate */
- u_int16_t bfs_al; /* length of aggregate */
- u_int16_t bfs_frmlen; /* length of frame */
+ u16 bfs_al; /* length of aggregate */
+ u16 bfs_frmlen; /* length of frame */
int bfs_seqno; /* sequence number */
int bfs_tidno; /* tid of this frame */
int bfs_retries; /* current retries */
when set for tx frame */
int bfs_rifsburst_elem; /* RIFS burst/bar */
int bfs_nrifsubframes; /* # of elements in burst */
- enum hal_key_type bfs_keytype; /* key type use to encrypt this frame */
+ /* key type use to encrypt this frame */
+ enum ath9k_key_type bfs_keytype;
};
#define bf_nframes bf_state.bfs_nframes
struct ath_desc *bf_desc; /* virtual addr of desc */
dma_addr_t bf_daddr; /* physical addr of desc */
dma_addr_t bf_buf_addr; /* physical addr of data buffer */
- u_int32_t bf_status;
- u_int16_t bf_flags; /* tx descriptor flags */
+ u32 bf_status;
+ u16 bf_flags; /* tx descriptor flags */
struct ath_buf_state bf_state; /* buffer state */
dma_addr_t bf_dmacontext;
};
const char *dd_name;
struct ath_desc *dd_desc; /* descriptors */
dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
- u_int32_t dd_desc_len; /* size of dd_desc */
+ u32 dd_desc_len; /* size of dd_desc */
struct ath_buf *dd_bufptr; /* associated buffers */
dma_addr_t dd_dmacontext;
};
/* per frame rx status block */
struct ath_recv_status {
- u_int64_t tsf; /* mac tsf */
+ u64 tsf; /* mac tsf */
int8_t rssi; /* RSSI (noise floor ajusted) */
int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
int8_t abs_rssi; /* absolute RSSI */
- u_int8_t rateieee; /* data rate received (IEEE rate code) */
- u_int8_t ratecode; /* phy rate code */
+ u8 rateieee; /* data rate received (IEEE rate code) */
+ u8 ratecode; /* phy rate code */
int rateKbps; /* data rate received (Kbps) */
int antenna; /* rx antenna */
int flags; /* status of associated skb */
int baw_tail; /* tail of block-ack window */
int seq_reset; /* need to reset start sequence */
int addba_exchangecomplete;
- u_int16_t seq_next; /* next expected sequence */
- u_int16_t baw_size; /* block-ack window size */
+ u16 seq_next; /* next expected sequence */
+ u16 baw_size; /* block-ack window size */
};
/* Per-node receiver aggregate state */
int ath_startrecv(struct ath_softc *sc);
bool ath_stoprecv(struct ath_softc *sc);
void ath_flushrecv(struct ath_softc *sc);
-u_int32_t ath_calcrxfilter(struct ath_softc *sc);
+u32 ath_calcrxfilter(struct ath_softc *sc);
void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an);
void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
int ath__rx_indicate(struct ath_softc *sc,
struct sk_buff *skb,
struct ath_recv_status *status,
- u_int16_t keyix);
+ u16 keyix);
int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
struct ath_recv_status *status);
* hardware queue).
*/
struct ath_txq {
- u_int axq_qnum; /* hardware q number */
- u_int32_t *axq_link; /* link ptr in last TX desc */
+ u32 axq_qnum; /* hardware q number */
+ u32 *axq_link; /* link ptr in last TX desc */
struct list_head axq_q; /* transmit queue */
spinlock_t axq_lock; /* lock on q and link */
unsigned long axq_lockflags; /* intr state when must cli */
- u_int axq_depth; /* queue depth */
- u_int8_t axq_aggr_depth; /* aggregates queued */
- u_int32_t axq_totalqueued;/* total ever queued */
- u_int axq_intrcnt; /* count to determine
+ u32 axq_depth; /* queue depth */
+ u8 axq_aggr_depth; /* aggregates queued */
+ u32 axq_totalqueued;/* total ever queued */
+ u32 axq_intrcnt; /* count to determine
if descriptor should generate
int on this txq. */
bool stopped; /* Is mac80211 queue
struct ath_node *an; /* parent node structure */
struct ath_atx_ac *ac; /* parent access category */
struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];/* active tx frames */
- u_int16_t seq_start; /* starting seq of BA window */
- u_int16_t seq_next; /* next seq to be used */
- u_int16_t baw_size; /* BA window size */
+ u16 seq_start; /* starting seq of BA window */
+ u16 seq_next; /* next seq to be used */
+ u16 baw_size; /* BA window size */
int tidno; /* TID number */
int baw_head; /* first un-acked tx buffer */
int baw_tail; /* next unused tx buffer slot */
int paused; /* TID is paused */
int cleanup_inprogress; /* aggr of this TID is
being teared down */
- u_int32_t addba_exchangecomplete:1; /* ADDBA state */
+ u32 addba_exchangecomplete:1; /* ADDBA state */
int32_t addba_exchangeinprogress;
int addba_exchangeattempts;
};
struct ath_node *an; /* destination to sent to */
int if_id; /* only valid for cab traffic */
int qnum; /* h/w queue number */
- u_int ht:1; /* if it can be transmitted using HT */
- u_int ps:1; /* if one or more stations are in PS mode */
- u_int use_minrate:1; /* if this frame should transmitted using
+ u32 ht:1; /* if it can be transmitted using HT */
+ u32 ps:1; /* if one or more stations are in PS mode */
+ u32 use_minrate:1; /* if this frame should transmitted using
minimum rate */
- enum hal_pkt_type atype; /* Atheros packet type */
- enum hal_key_type keytype; /* key type */
- u_int flags; /* HAL flags */
- u_int16_t seqno; /* sequence number */
- u_int16_t tidno; /* tid number */
- u_int16_t txpower; /* transmit power */
- u_int16_t frmlen; /* frame length */
- u_int32_t keyix; /* key index */
+ enum ath9k_pkt_type atype; /* Atheros packet type */
+ enum ath9k_key_type keytype; /* key type */
+ u32 flags; /* HAL flags */
+ u16 seqno; /* sequence number */
+ u16 tidno; /* tid number */
+ u16 txpower; /* transmit power */
+ u16 frmlen; /* frame length */
+ u32 keyix; /* key index */
int min_rate; /* minimum rate */
int mcast_rate; /* multicast rate */
- u_int16_t nextfraglen; /* next fragment length */
+ u16 nextfraglen; /* next fragment length */
/* below is set only by ath_dev */
struct ath_softc *dev; /* device handle */
dma_addr_t dmacontext;
#define ATH_TX_CHAIN_RSSI_VALID 0x01
/* if extn chain rssis are valid */
#define ATH_TX_RSSI_EXTN_VALID 0x02
- u_int32_t airtime; /* time on air per final tx rate */
+ u32 airtime; /* time on air per final tx rate */
};
struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
int ath_tx_init(struct ath_softc *sc, int nbufs);
int ath_tx_cleanup(struct ath_softc *sc);
int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
-int ath_txq_update(struct ath_softc *sc, int qnum, struct hal_txq_info *q);
+int ath_txq_update(struct ath_softc *sc, int qnum, struct ath9k_txq_info *q);
int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb);
void ath_tx_tasklet(struct ath_softc *sc);
-u_int32_t ath_txq_depth(struct ath_softc *sc, int qnum);
-u_int32_t ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
-void ath_notify_txq_status(struct ath_softc *sc, u_int16_t queue_depth);
+u32 ath_txq_depth(struct ath_softc *sc, int qnum);
+u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
+void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
struct ath_xmit_status *tx_status, struct ath_node *an);
atomic_t an_refcnt;
struct ath_chainmask_sel an_chainmask_sel;
struct ath_node_aggr an_aggr; /* A-MPDU aggregation state */
- u_int8_t an_smmode; /* SM Power save mode */
- u_int8_t an_flags;
+ u8 an_smmode; /* SM Power save mode */
+ u8 an_flags;
u8 an_addr[ETH_ALEN];
};
enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
struct ath_node *an, u8 tidno);
void ath_tx_aggr_teardown(struct ath_softc *sc,
- struct ath_node *an, u_int8_t tidno);
+ struct ath_node *an, u8 tidno);
void ath_rx_aggr_teardown(struct ath_softc *sc,
- struct ath_node *an, u_int8_t tidno);
+ struct ath_node *an, u8 tidno);
int ath_rx_aggr_start(struct ath_softc *sc,
const u8 *addr,
u16 tid,
void ath_newassoc(struct ath_softc *sc,
struct ath_node *node, int isnew, int isuapsd);
struct ath_node *ath_node_attach(struct ath_softc *sc,
- u_int8_t addr[ETH_ALEN], int if_id);
+ u8 addr[ETH_ALEN], int if_id);
void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
-struct ath_node *ath_node_get(struct ath_softc *sc, u_int8_t addr[ETH_ALEN]);
+struct ath_node *ath_node_get(struct ath_softc *sc, u8 addr[ETH_ALEN]);
void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
-struct ath_node *ath_node_find(struct ath_softc *sc, u_int8_t *addr);
+struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr);
/*******************/
/* Beacon Handling */
/* beacon configuration */
struct ath_beacon_config {
- u_int16_t beacon_interval;
- u_int16_t listen_interval;
- u_int16_t dtim_period;
- u_int16_t bmiss_timeout;
- u_int8_t dtim_count;
- u_int8_t tim_offset;
+ u16 beacon_interval;
+ u16 listen_interval;
+ u16 dtim_period;
+ u16 bmiss_timeout;
+ u8 dtim_count;
+ u8 tim_offset;
union {
- u_int64_t last_tsf;
- u_int8_t last_tstamp[8];
+ u64 last_tsf;
+ u8 last_tstamp[8];
} u; /* last received beacon/probe response timestamp of this BSS. */
};
/* offsets in a beacon frame for
* quick acess of beacon content by low-level driver */
struct ath_beacon_offset {
- u_int8_t *bo_tim; /* start of atim/dtim */
+ u8 *bo_tim; /* start of atim/dtim */
};
void ath9k_beacon_tasklet(unsigned long data);
/* VAP configuration (from protocol layer) */
struct ath_vap_config {
- u_int32_t av_fixed_rateset;
- u_int32_t av_fixed_retryset;
+ u32 av_fixed_rateset;
+ u32 av_fixed_retryset;
};
/* driver-specific vap state */
struct ath_vap {
struct ieee80211_vif *av_if_data; /* interface(vap)
instance from 802.11 protocal layer */
- enum hal_opmode av_opmode; /* VAP operational mode */
+ enum ath9k_opmode av_opmode; /* VAP operational mode */
struct ath_buf *av_bcbuf; /* beacon buffer */
struct ath_beacon_offset av_boff; /* dynamic update state */
struct ath_tx_control av_btxctl; /* tx control information
transmit queue */
struct ath_vap_config av_config; /* vap configuration
parameters from 802.11 protocol layer*/
+ struct ath_rate_node *rc_node;
};
int ath_vap_attach(struct ath_softc *sc,
int if_id,
struct ieee80211_vif *if_data,
- enum hal_opmode opmode);
+ enum ath9k_opmode opmode);
int ath_vap_detach(struct ath_softc *sc, int if_id);
int ath_vap_config(struct ath_softc *sc,
int if_id, struct ath_vap_config *if_config);
struct ath_antdiv {
struct ath_softc *antdiv_sc;
- u_int8_t antdiv_start;
+ u8 antdiv_start;
enum ATH_ANT_DIV_STATE antdiv_state;
- u_int8_t antdiv_num_antcfg;
- u_int8_t antdiv_curcfg;
- u_int8_t antdiv_bestcfg;
+ u8 antdiv_num_antcfg;
+ u8 antdiv_curcfg;
+ u8 antdiv_bestcfg;
int32_t antdivf_rssitrig;
int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
- u_int64_t antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
- u_int64_t antdiv_laststatetsf;
- u_int8_t antdiv_bssid[ETH_ALEN];
+ u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
+ u64 antdiv_laststatetsf;
+ u8 antdiv_bssid[ETH_ALEN];
};
void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
struct ath_softc *sc, int32_t rssitrig);
void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
- u_int8_t num_antcfg,
- const u_int8_t *bssid);
+ u8 num_antcfg,
+ const u8 *bssid);
void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
void ath_slow_ant_div(struct ath_antdiv *antdiv,
struct ieee80211_hdr *wh,
struct ath_rx_status *rx_stats);
-void ath_setdefantenna(void *sc, u_int antenna);
+void ath_setdefantenna(void *sc, u32 antenna);
/********************/
/* Main driver core */
* up to ATH_KEYMAX entries (could dynamically allocate state).
*/
#define ATH_KEYMAX 128 /* max key cache size we handle */
-#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */
#define RESET_RETRY_TXQ 0x00000001
#define ATH_IF_ID_ANY 0xff
PROT_M_CTSONLY
};
-enum ieee80211_clist_cmd {
- CLIST_UPDATE,
- CLIST_DFS_UPDATE,
- CLIST_NEW_COUNTRY
-};
-
enum RATE_TYPE {
NORMAL_RATE = 0,
HALF_RATE,
};
struct ath_ht_info {
- enum hal_ht_macmode tx_chan_width;
- u_int16_t maxampdu;
- u_int8_t mpdudensity;
- u_int8_t ext_chan_offset;
+ enum ath9k_ht_macmode tx_chan_width;
+ u16 maxampdu;
+ u8 mpdudensity;
+ u8 ext_chan_offset;
};
struct ath_softc {
int sc_debug; /* Debug masks */
struct ath_hal *sc_ah; /* HAL Instance */
struct ath_rate_softc *sc_rc; /* tx rate control support */
- u_int32_t sc_intrstatus; /* HAL_STATUS */
- enum hal_opmode sc_opmode; /* current operating mode */
+ u32 sc_intrstatus; /* HAL_STATUS */
+ enum ath9k_opmode sc_opmode; /* current operating mode */
/* Properties, Config */
- u_int8_t sc_invalid; /* being detached */
- u_int8_t sc_beacons; /* beacons running */
- u_int8_t sc_scanning; /* scanning active */
- u_int8_t sc_txaggr; /* enable 11n tx aggregation */
- u_int8_t sc_rxaggr; /* enable 11n rx aggregation */
- u_int8_t sc_update_chainmask; /* change chain mask */
- u_int8_t sc_full_reset; /* force full reset */
+ u8 sc_invalid; /* being detached */
+ u8 sc_beacons; /* beacons running */
+ u8 sc_scanning; /* scanning active */
+ u8 sc_txaggr; /* enable 11n tx aggregation */
+ u8 sc_rxaggr; /* enable 11n rx aggregation */
+ u8 sc_update_chainmask; /* change chain mask */
+ u8 sc_full_reset; /* force full reset */
enum wireless_mode sc_curmode; /* current phy mode */
- u_int16_t sc_curtxpow; /* current tx power limit */
- u_int16_t sc_curaid; /* current association id */
- u_int8_t sc_curbssid[ETH_ALEN];
- u_int8_t sc_myaddr[ETH_ALEN];
+ u16 sc_curtxpow; /* current tx power limit */
+ u16 sc_curaid; /* current association id */
+ u8 sc_curbssid[ETH_ALEN];
+ u8 sc_myaddr[ETH_ALEN];
enum PROT_MODE sc_protmode; /* protection mode */
- u_int8_t sc_mcastantenna;/* Multicast antenna number */
- u_int8_t sc_txantenna; /* data tx antenna
+ u8 sc_mcastantenna;/* Multicast antenna number */
+ u8 sc_txantenna; /* data tx antenna
(fixed or auto) */
- u_int8_t sc_nbcnvaps; /* # of vaps sending beacons */
- u_int16_t sc_nvaps; /* # of active virtual ap's */
+ u8 sc_nbcnvaps; /* # of vaps sending beacons */
+ u16 sc_nvaps; /* # of active virtual ap's */
struct ath_vap *sc_vaps[ATH_BCBUF]; /* interface id
to avp map */
- enum hal_int sc_imask; /* interrupt mask copy */
- u_int8_t sc_bssidmask[ETH_ALEN];
- u_int8_t sc_defant; /* current default antenna */
- u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
- u_int16_t sc_cachelsz; /* cache line size */
+ enum ath9k_int sc_imask; /* interrupt mask copy */
+ u8 sc_bssidmask[ETH_ALEN];
+ u8 sc_defant; /* current default antenna */
+ u8 sc_rxotherant; /* rx's on non-default antenna*/
+ u16 sc_cachelsz; /* cache line size */
int sc_slotupdate; /* slot to next advance fsm */
int sc_slottime; /* slot time */
- u_int8_t sc_noreset;
+ u8 sc_noreset;
int sc_bslot[ATH_BCBUF];/* beacon xmit slots */
- struct hal_node_stats sc_halstats; /* station-mode rssi stats */
+ struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */
struct list_head node_list;
struct ath_ht_info sc_ht_info;
int16_t sc_noise_floor; /* signal noise floor in dBm */
- enum hal_ht_extprotspacing sc_ht_extprotspacing;
- u_int8_t sc_tx_chainmask;
- u_int8_t sc_rx_chainmask;
- u_int8_t sc_rxchaindetect_ref;
- u_int8_t sc_rxchaindetect_thresh5GHz;
- u_int8_t sc_rxchaindetect_thresh2GHz;
- u_int8_t sc_rxchaindetect_delta5GHz;
- u_int8_t sc_rxchaindetect_delta2GHz;
- u_int32_t sc_rtsaggrlimit; /* Chipset specific
+ enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
+ u8 sc_tx_chainmask;
+ u8 sc_rx_chainmask;
+ u8 sc_rxchaindetect_ref;
+ u8 sc_rxchaindetect_thresh5GHz;
+ u8 sc_rxchaindetect_thresh2GHz;
+ u8 sc_rxchaindetect_delta5GHz;
+ u8 sc_rxchaindetect_delta2GHz;
+ u32 sc_rtsaggrlimit; /* Chipset specific
aggr limit */
u32 sc_flags;
#ifdef CONFIG_SLOW_ANT_DIV
} sc_updateslot; /* slot time update fsm */
/* Crypto */
- u_int sc_keymax; /* size of key cache */
- DECLARE_BITMAP (sc_keymap, ATH_KEYBYTES);/* key use bit map */
- u_int8_t sc_splitmic; /* split TKIP MIC keys */
+ u32 sc_keymax; /* size of key cache */
+ DECLARE_BITMAP (sc_keymap, ATH_KEYMAX);/* key use bit map */
+ u8 sc_splitmic; /* split TKIP MIC keys */
int sc_keytype; /* type of the key being used */
/* RX */
struct list_head sc_rxbuf; /* receive buffer */
struct ath_descdma sc_rxdma; /* RX descriptors */
int sc_rxbufsize; /* rx size based on mtu */
- u_int32_t *sc_rxlink; /* link ptr in last RX desc */
- u_int32_t sc_rxflush; /* rx flush in progress */
- u_int64_t sc_lastrx; /* tsf of last rx'd frame */
+ u32 *sc_rxlink; /* link ptr in last RX desc */
+ u32 sc_rxflush; /* rx flush in progress */
+ u64 sc_lastrx; /* tsf of last rx'd frame */
/* TX */
struct list_head sc_txbuf; /* transmit buffer */
- struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
+ struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
struct ath_descdma sc_txdma; /* TX descriptors */
- u_int sc_txqsetup; /* h/w queues setup */
- u_int sc_txintrperiod;/* tx interrupt batching */
- int sc_haltype2q[HAL_WME_AC_VO+1]; /* HAL WME
+ u32 sc_txqsetup; /* h/w queues setup */
+ u32 sc_txintrperiod;/* tx interrupt batching */
+ int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME
AC -> h/w qnum */
- u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
+ u32 sc_ant_tx[8]; /* recent tx frames/antenna */
/* Beacon */
- struct hal_txq_info sc_beacon_qi; /* adhoc only: beacon
+ struct ath9k_txq_info sc_beacon_qi; /* adhoc only: beacon
queue parameters */
struct ath_descdma sc_bdma; /* beacon descriptors */
struct ath_txq *sc_cabq; /* tx q for cab frames */
struct list_head sc_bbuf; /* beacon buffers */
- u_int sc_bhalq; /* HAL q for outgoing beacons */
- u_int sc_bmisscount; /* missed beacon transmits */
- u_int32_t ast_be_xmit; /* beacons transmitted */
+ u32 sc_bhalq; /* HAL q for outgoing beacons */
+ u32 sc_bmisscount; /* missed beacon transmits */
+ u32 ast_be_xmit; /* beacons transmitted */
/* Rate */
struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
- const struct hal_rate_table *sc_rates[WIRELESS_MODE_MAX];
- const struct hal_rate_table *sc_currates; /* current rate table */
- u_int8_t sc_rixmap[256]; /* IEEE to h/w
+ const struct ath9k_rate_table *sc_rates[WIRELESS_MODE_MAX];
+ const struct ath9k_rate_table *sc_currates; /* current rate table */
+ u8 sc_rixmap[256]; /* IEEE to h/w
rate table ix */
- u_int8_t sc_minrateix; /* min h/w rate index */
- u_int8_t sc_protrix; /* protection rate index */
+ u8 sc_minrateix; /* min h/w rate index */
+ u8 sc_protrix; /* protection rate index */
struct {
- u_int32_t rateKbps; /* transfer rate in kbs */
- u_int8_t ieeerate; /* IEEE rate */
+ u32 rateKbps; /* transfer rate in kbs */
+ u8 ieeerate; /* IEEE rate */
} sc_hwmap[256]; /* h/w rate ix mappings */
/* Channel, Band */
struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
- struct hal_channel sc_curchan; /* current h/w channel */
+ struct ath9k_channel sc_curchan; /* current h/w channel */
/* Locks */
spinlock_t sc_rxflushlock; /* lock of RX flush */
spinlock_t node_lock;
};
-int ath_init(u_int16_t devid, struct ath_softc *sc);
+int ath_init(u16 devid, struct ath_softc *sc);
void ath_deinit(struct ath_softc *sc);
-int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan);
+int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan);
int ath_suspend(struct ath_softc *sc);
irqreturn_t ath_isr(int irq, void *dev);
int ath_reset(struct ath_softc *sc);
void ath_scan_start(struct ath_softc *sc);
void ath_scan_end(struct ath_softc *sc);
-int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan);
-void ath_setup_channel_list(struct ath_softc *sc,
- enum ieee80211_clist_cmd cmd,
- const struct hal_channel *chans,
- int nchan,
- const u_int8_t *regclassids,
- u_int nregclass,
- int countrycode);
+int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan);
void ath_setup_rate(struct ath_softc *sc,
enum wireless_mode wMode,
enum RATE_TYPE type,
- const struct hal_rate_table *rt);
+ const struct ath9k_rate_table *rt);
/*********************/
/* Utility Functions */
/*********************/
-void ath_key_reset(struct ath_softc *sc, u_int16_t keyix, int freeslot);
+void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot);
int ath_keyset(struct ath_softc *sc,
- u_int16_t keyix,
- struct hal_keyval *hk,
- const u_int8_t mac[ETH_ALEN]);
+ u16 keyix,
+ struct ath9k_keyval *hk,
+ const u8 mac[ETH_ALEN]);
int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
-int ath_get_mac80211_qnum(u_int queue, struct ath_softc *sc);
+int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
void ath_setslottime(struct ath_softc *sc);
void ath_update_txpow(struct ath_softc *sc);
int ath_cabq_update(struct ath_softc *);
void ath_get_currentCountry(struct ath_softc *sc,
- struct hal_country_entry *ctry);
-u_int64_t ath_extend_tsf(struct ath_softc *sc, u_int32_t rstamp);
+ struct ath9k_country_entry *ctry);
+u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp);
void ath_internal_reset(struct ath_softc *sc);
-u_int32_t ath_chan2flags(struct ieee80211_channel *chan, struct ath_softc *sc);
+u32 ath_chan2flags(struct ieee80211_channel *chan, struct ath_softc *sc);
dma_addr_t ath_skb_map_single(struct ath_softc *sc,
struct sk_buff *skb,
int direction,
struct sk_buff *skb,
int direction,
dma_addr_t *pa);
-void ath_mcast_merge(struct ath_softc *sc, u_int32_t mfilt[2]);
-enum hal_ht_macmode ath_cwm_macmode(struct ath_softc *sc);
+void ath_mcast_merge(struct ath_softc *sc, u32 mfilt[2]);
+enum ath9k_ht_macmode ath_cwm_macmode(struct ath_softc *sc);
#endif /* CORE_H */
#include "initvals.h"
static void ath9k_hw_iqcal_collect(struct ath_hal *ah);
-static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains);
+static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains);
static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah);
static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah,
- u_int8_t numChains);
+ u8 numChains);
static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah);
static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah,
- u_int8_t numChains);
+ u8 numChains);
-static const u_int8_t CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
+static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 };
static const struct hal_percal_data iq_cal_multi_sample = {
},
};
-static struct hal_rate_table ar5416_11a_table = {
+static struct ath9k_rate_table ar5416_11a_table = {
8,
{0},
{
},
};
-static struct hal_rate_table ar5416_11b_table = {
+static struct ath9k_rate_table ar5416_11b_table = {
4,
{0},
{
},
};
-static struct hal_rate_table ar5416_11g_table = {
+static struct ath9k_rate_table ar5416_11g_table = {
12,
{0},
{
},
};
-static struct hal_rate_table ar5416_11ng_table = {
+static struct ath9k_rate_table ar5416_11ng_table = {
28,
{0},
{
},
};
-static struct hal_rate_table ar5416_11na_table = {
+static struct ath9k_rate_table ar5416_11na_table = {
24,
{0},
{
};
static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
- const struct hal_channel *chan)
+ const struct ath9k_channel *chan)
{
if (IS_CHAN_CCK(chan))
return WIRELESS_MODE_11b;
}
static bool ath9k_hw_wait(struct ath_hal *ah,
- u_int reg,
- u_int32_t mask,
- u_int32_t val)
+ u32 reg,
+ u32 mask,
+ u32 val)
{
int i;
return false;
}
-static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u_int off,
- u_int16_t *data)
+static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u32 off,
+ u16 *data)
{
(void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
return true;
}
-static enum hal_status ath9k_hw_flash_map(struct ath_hal *ah)
+static int ath9k_hw_flash_map(struct ath_hal *ah)
{
struct ath_hal_5416 *ahp = AH5416(ah);
if (!ahp->ah_cal_mem) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"%s: cannot remap eeprom region \n", __func__);
- return HAL_EIO;
+ return -EIO;
}
- return HAL_OK;
+ return 0;
}
-static bool ath9k_hw_flash_read(struct ath_hal *ah, u_int off,
- u_int16_t *data)
+static bool ath9k_hw_flash_read(struct ath_hal *ah, u32 off,
+ u16 *data)
{
struct ath_hal_5416 *ahp = AH5416(ah);
static void ath9k_hw_read_revisions(struct ath_hal *ah)
{
- u_int32_t val;
+ u32 val;
val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
}
}
-u_int32_t ath9k_hw_reverse_bits(u_int32_t val, u_int32_t n)
+u32 ath9k_hw_reverse_bits(u32 val, u32 n)
{
- u_int32_t retval;
+ u32 retval;
int i;
for (i = 0, retval = 0; i < n; i++) {
}
static inline void ath9k_hw_override_ini(struct ath_hal *ah,
- struct hal_channel *chan)
+ struct ath9k_channel *chan)
{
if (!AR_SREV_5416_V20_OR_LATER(ah)
|| AR_SREV_9280_10_OR_LATER(ah))
}
static inline void ath9k_hw_init_bb(struct ath_hal *ah,
- struct hal_channel *chan)
+ struct ath9k_channel *chan)
{
- u_int32_t synthDelay;
+ u32 synthDelay;
synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
if (IS_CHAN_CCK(chan))
}
static inline void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
- enum hal_opmode opmode)
+ enum ath9k_opmode opmode)
{
struct ath_hal_5416 *ahp = AH5416(ah);
ahp->ah_maskReg |= AR_IMR_TXOK;
- if (opmode == HAL_M_HOSTAP)
+ if (opmode == ATH9K_M_HOSTAP)
ahp->ah_maskReg |= AR_IMR_MIB;
REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
}
static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
- u_int reg,
- u_int32_t mask,
- u_int32_t shift,
- u_int32_t val)
+ u32 reg,
+ u32 mask,
+ u32 shift,
+ u32 val)
{
- u_int32_t regVal;
+ u32 regVal;
regVal = REG_READ(ah, reg) & ~mask;
regVal |= (val << shift) & mask;
return;
}
-static u_int8_t ath9k_hw_get_num_ant_config(struct ath_hal_5416 *ahp,
+static u8 ath9k_hw_get_num_ant_config(struct ath_hal_5416 *ahp,
enum hal_freq_band freq_band)
{
struct ar5416_eeprom *eep = &ahp->ah_eeprom;
struct modal_eep_header *pModal =
&(eep->modalHeader[HAL_FREQ_BAND_2GHZ == freq_band]);
struct base_eep_header *pBase = &eep->baseEepHeader;
- u_int8_t num_ant_config;
+ u8 num_ant_config;
num_ant_config = 1;
return num_ant_config;
}
-static enum hal_status
+static int
ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp,
- struct hal_channel_internal *chan,
- u_int8_t index,
- u_int16_t *config)
+ struct ath9k_channel *chan,
+ u8 index,
+ u16 *config)
{
struct ar5416_eeprom *eep = &ahp->ah_eeprom;
struct modal_eep_header *pModal =
switch (index) {
case 0:
*config = pModal->antCtrlCommon & 0xFFFF;
- return HAL_OK;
+ return 0;
case 1:
if (pBase->version >= 0x0E0D) {
if (pModal->useAnt1) {
*config =
((pModal->antCtrlCommon & 0xFFFF0000) >> 16);
- return HAL_OK;
+ return 0;
}
}
break;
break;
}
- return HAL_EINVAL;
+ return -EINVAL;
}
static inline bool ath9k_hw_nvram_read(struct ath_hal *ah,
- u_int off,
- u_int16_t *data)
+ u32 off,
+ u16 *data)
{
if (ath9k_hw_use_flash(ah))
return ath9k_hw_flash_read(ah, off, data);
{
struct ath_hal_5416 *ahp = AH5416(ah);
struct ar5416_eeprom *eep = &ahp->ah_eeprom;
- u_int16_t *eep_data;
+ u16 *eep_data;
int addr, ar5416_eep_start_loc = 0;
if (!ath9k_hw_use_flash(ah)) {
if (AR_SREV_9100(ah))
ar5416_eep_start_loc = 256;
- eep_data = (u_int16_t *) eep;
+ eep_data = (u16 *) eep;
for (addr = 0;
- addr < sizeof(struct ar5416_eeprom) / sizeof(u_int16_t);
+ addr < sizeof(struct ar5416_eeprom) / sizeof(u16);
addr++) {
if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
eep_data)) {
/* XXX: Clean me up, make me more legible */
static bool
ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
- struct hal_channel_internal *chan)
+ struct ath9k_channel *chan)
{
struct modal_eep_header *pModal;
int i, regChainOffset;
struct ath_hal_5416 *ahp = AH5416(ah);
struct ar5416_eeprom *eep = &ahp->ah_eeprom;
- u_int8_t txRxAttenLocal;
- u_int16_t ant_config;
+ u8 txRxAttenLocal;
+ u16 ant_config;
pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
return true;
}
-static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
+static inline int ath9k_hw_check_eeprom(struct ath_hal *ah)
{
- u_int32_t sum = 0, el;
- u_int16_t *eepdata;
+ u32 sum = 0, el;
+ u16 *eepdata;
int i;
struct ath_hal_5416 *ahp = AH5416(ah);
bool need_swap = false;
(struct ar5416_eeprom *) &ahp->ah_eeprom;
if (!ath9k_hw_use_flash(ah)) {
- u_int16_t magic, magic2;
+ u16 magic, magic2;
int addr;
if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
if (magic2 == AR5416_EEPROM_MAGIC) {
need_swap = true;
- eepdata = (u_int16_t *) (&ahp->ah_eeprom);
+ eepdata = (u16 *) (&ahp->ah_eeprom);
for (addr = 0;
addr <
sizeof(struct ar5416_eeprom) /
- sizeof(u_int16_t); addr++) {
- u_int16_t temp;
+ sizeof(u16); addr++) {
+ u16 temp;
temp = swab16(*eepdata);
*eepdata = temp;
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"Invalid EEPROM Magic. "
"endianness missmatch.\n");
- return HAL_EEBADSUM;
+ return -EINVAL;
}
}
}
el = ahp->ah_eeprom.baseEepHeader.length;
if (el > sizeof(struct ar5416_eeprom))
- el = sizeof(struct ar5416_eeprom) / sizeof(u_int16_t);
+ el = sizeof(struct ar5416_eeprom) / sizeof(u16);
else
- el = el / sizeof(u_int16_t);
+ el = el / sizeof(u16);
- eepdata = (u_int16_t *) (&ahp->ah_eeprom);
+ eepdata = (u16 *) (&ahp->ah_eeprom);
for (i = 0; i < el; i++)
sum ^= *eepdata++;
if (need_swap) {
- u_int32_t integer, j;
- u_int16_t word;
+ u32 integer, j;
+ u16 word;
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"EEPROM Endianness is not native.. Changing \n");
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"Bad EEPROM checksum 0x%x or revision 0x%04x\n",
sum, ar5416_get_eep_ver(ahp));
- return HAL_EEBADSUM;
+ return -EINVAL;
}
- return HAL_OK;
+ return 0;
}
static bool ath9k_hw_chip_test(struct ath_hal *ah)
{
- u_int32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
- u_int32_t regHold[2];
- u_int32_t patternData[4] = { 0x55555555,
+ u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
+ u32 regHold[2];
+ u32 patternData[4] = { 0x55555555,
0xaaaaaaaa,
0x66666666,
0x99999999 };
int i, j;
for (i = 0; i < 2; i++) {
- u_int32_t addr = regAddr[i];
- u_int32_t wrData, rdData;
+ u32 addr = regAddr[i];
+ u32 wrData, rdData;
regHold[i] = REG_READ(ah, addr);
for (j = 0; j < 0x100; j++) {
return true;
}
-u_int32_t ath9k_hw_getrxfilter(struct ath_hal *ah)
+u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
{
- u_int32_t bits = REG_READ(ah, AR_RX_FILTER);
- u_int32_t phybits = REG_READ(ah, AR_PHY_ERR);
+ u32 bits = REG_READ(ah, AR_RX_FILTER);
+ u32 phybits = REG_READ(ah, AR_PHY_ERR);
if (phybits & AR_PHY_ERR_RADAR)
- bits |= HAL_RX_FILTER_PHYRADAR;
+ bits |= ATH9K_RX_FILTER_PHYRADAR;
if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
- bits |= HAL_RX_FILTER_PHYERR;
+ bits |= ATH9K_RX_FILTER_PHYERR;
return bits;
}
-void ath9k_hw_setrxfilter(struct ath_hal *ah, u_int32_t bits)
+void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
{
- u_int32_t phybits;
+ u32 phybits;
REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
phybits = 0;
- if (bits & HAL_RX_FILTER_PHYRADAR)
+ if (bits & ATH9K_RX_FILTER_PHYRADAR)
phybits |= AR_PHY_ERR_RADAR;
- if (bits & HAL_RX_FILTER_PHYERR)
+ if (bits & ATH9K_RX_FILTER_PHYERR)
phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
REG_WRITE(ah, AR_PHY_ERR, phybits);
bool ath9k_hw_setcapability(struct ath_hal *ah,
enum hal_capability_type type,
- u_int32_t capability,
- u_int32_t setting,
- enum hal_status *status)
+ u32 capability,
+ u32 setting,
+ int *status)
{
struct ath_hal_5416 *ahp = AH5416(ah);
- u_int32_t v;
+ u32 v;
switch (type) {
case HAL_CAP_TKIP_MIC:
void ath9k_hw_dmaRegDump(struct ath_hal *ah)
{
- u_int32_t val[ATH9K_NUM_DMA_DEBUG_REGS];
+ u32 val[ATH9K_NUM_DMA_DEBUG_REGS];
int qcuOffset = 0, dcuOffset = 0;
- u_int32_t *qcuBase = &val[0], *dcuBase = &val[4];
+ u32 *qcuBase = &val[0], *dcuBase = &val[4];
int i;
REG_WRITE(ah, AR_MACMISC,
if (i % 4 == 0)
DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
- val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t)));
+ val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32)));
DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "%d: %08x ", i, val[i]);
}
"AR_CR 0x%x \n", REG_READ(ah, AR_CR));
}
-u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
- u_int32_t *rxc_pcnt,
- u_int32_t *rxf_pcnt,
- u_int32_t *txf_pcnt)
+u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
+ u32 *rxc_pcnt,
+ u32 *rxf_pcnt,
+ u32 *txf_pcnt)
{
- static u_int32_t cycles, rx_clear, rx_frame, tx_frame;
- u_int32_t good = 1;
+ static u32 cycles, rx_clear, rx_frame, tx_frame;
+ u32 good = 1;
- u_int32_t rc = REG_READ(ah, AR_RCCNT);
- u_int32_t rf = REG_READ(ah, AR_RFCNT);
- u_int32_t tf = REG_READ(ah, AR_TFCNT);
- u_int32_t cc = REG_READ(ah, AR_CCCNT);
+ u32 rc = REG_READ(ah, AR_RCCNT);
+ u32 rf = REG_READ(ah, AR_RFCNT);
+ u32 tf = REG_READ(ah, AR_TFCNT);
+ u32 cc = REG_READ(ah, AR_CCCNT);
if (cycles == 0 || cycles > cc) {
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
__func__);
good = 0;
} else {
- u_int32_t cc_d = cc - cycles;
- u_int32_t rc_d = rc - rx_clear;
- u_int32_t rf_d = rf - rx_frame;
- u_int32_t tf_d = tf - tx_frame;
+ u32 cc_d = cc - cycles;
+ u32 rc_d = rc - rx_clear;
+ u32 rf_d = rf - rx_frame;
+ u32 tf_d = tf - tx_frame;
if (cc_d != 0) {
*rxc_pcnt = rc_d * 100 / cc_d;
return good;
}
-void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum hal_ht_macmode mode)
+void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
{
- u_int32_t macmode;
+ u32 macmode;
- if (mode == HAL_HT_MACMODE_2040 &&
+ if (mode == ATH9K_HT_MACMODE_2040 &&
!ah->ah_config.ath_hal_cwmIgnoreExtCCA)
macmode = AR_2040_JOINED_RX_CLEAR;
else
}
-static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid,
+static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
struct ath_softc *sc,
void __iomem *mem,
- enum hal_status *status)
+ int *status)
{
- static const u_int8_t defbssidmask[ETH_ALEN] =
+ static const u8 defbssidmask[ETH_ALEN] =
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
struct ath_hal_5416 *ahp;
struct ath_hal *ah;
DPRINTF(sc, ATH_DBG_FATAL,
"%s: cannot allocate memory for state block\n",
__func__);
- *status = HAL_ENOMEM;
+ *status = -ENOMEM;
return NULL;
}
ah->ah_flags = AH_USE_EEPROM;
ah->ah_powerLimit = MAX_RATE_POWER;
- ah->ah_tpScale = HAL_TP_SCALE_MAX;
+ ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
ahp->ah_atimWindow = 0;
ahp->ah_diversityControl = ah->ah_config.ath_hal_diversityControl;
ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
ahp->ah_beaconInterval = 100;
ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
- ahp->ah_slottime = (u_int) -1;
- ahp->ah_acktimeout = (u_int) -1;
- ahp->ah_ctstimeout = (u_int) -1;
- ahp->ah_globaltxtimeout = (u_int) -1;
+ ahp->ah_slottime = (u32) -1;
+ ahp->ah_acktimeout = (u32) -1;
+ ahp->ah_ctstimeout = (u32) -1;
+ ahp->ah_globaltxtimeout = (u32) -1;
memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
ahp->ah_gBeaconRate = 0;
return ahp;
}
-static enum hal_status ath9k_hw_eeprom_attach(struct ath_hal *ah)
+static int ath9k_hw_eeprom_attach(struct ath_hal *ah)
{
- enum hal_status status;
+ int status;
if (ath9k_hw_use_flash(ah))
ath9k_hw_flash_map(ah);
if (!ath9k_hw_fill_eeprom(ah))
- return HAL_EIO;
+ return -EIO;
status = ath9k_hw_check_eeprom(ah);
return status;
}
-u_int32_t ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
+u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
enum eeprom_param param)
{
struct ar5416_eeprom *eep = &ahp->ah_eeprom;
static inline int ath9k_hw_get_radiorev(struct ath_hal *ah)
{
- u_int32_t val;
+ u32 val;
int i;
REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
return ath9k_hw_reverse_bits(val, 8);
}
-static inline enum hal_status ath9k_hw_init_macaddr(struct ath_hal *ah)
+static inline int ath9k_hw_init_macaddr(struct ath_hal *ah)
{
- u_int32_t sum;
+ u32 sum;
int i;
- u_int16_t eeval;
+ u16 eeval;
struct ath_hal_5416 *ahp = AH5416(ah);
DECLARE_MAC_BUF(mac);
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"%s: mac address read failed: %s\n", __func__,
print_mac(mac, ahp->ah_macaddr));
- return HAL_EEBADMAC;
+ return -EADDRNOTAVAIL;
}
- return HAL_OK;
+ return 0;
}
-static inline int16_t ath9k_hw_interpolate(u_int16_t target,
- u_int16_t srcLeft,
- u_int16_t srcRight,
+static inline int16_t ath9k_hw_interpolate(u16 target,
+ u16 srcLeft,
+ u16 srcRight,
int16_t targetLeft,
int16_t targetRight)
{
return rv;
}
-static inline u_int16_t ath9k_hw_fbin2freq(u_int8_t fbin,
+static inline u16 ath9k_hw_fbin2freq(u8 fbin,
bool is2GHz)
{
if (fbin == AR5416_BCHAN_UNUSED)
return fbin;
- return (u_int16_t) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
+ return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
}
-static u_int16_t ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
- u_int16_t i,
+static u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
+ u16 i,
bool is2GHz)
{
struct ath_hal_5416 *ahp = AH5416(ah);
struct ar5416_eeprom *eep =
(struct ar5416_eeprom *) &ahp->ah_eeprom;
- u_int16_t spur_val = AR_NO_SPUR;
+ u16 spur_val = AR_NO_SPUR;
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"Getting spur idx %d is2Ghz. %d val %x\n",
return spur_val;
}
-static inline enum hal_status ath9k_hw_rfattach(struct ath_hal *ah)
+static inline int ath9k_hw_rfattach(struct ath_hal *ah)
{
bool rfStatus = false;
- enum hal_status ecode = HAL_OK;
+ int ecode = 0;
rfStatus = ath9k_hw_init_rf(ah, &ecode);
if (!rfStatus) {
return ecode;
}
- return HAL_OK;
+ return 0;
}
-static enum hal_status ath9k_hw_rf_claim(struct ath_hal *ah)
+static int ath9k_hw_rf_claim(struct ath_hal *ah)
{
- u_int32_t val;
+ u32 val;
REG_WRITE(ah, AR_PHY(0), 0x00000007);
"%s: 5G Radio Chip Rev 0x%02X is not "
"supported by this driver\n",
__func__, ah->ah_analog5GhzRev);
- return HAL_ENOTSUPP;
+ return -EOPNOTSUPP;
}
ah->ah_analog5GhzRev = val;
- return HAL_OK;
+ return 0;
}
static inline void ath9k_hw_init_pll(struct ath_hal *ah,
- struct hal_channel *chan)
+ struct ath9k_channel *chan)
{
- u_int32_t pll;
+ u32 pll;
if (AR_SREV_9100(ah)) {
if (chan && IS_CHAN_5GHZ(chan))
pll |= SM(0xb, AR_RTC_PLL_DIV);
}
}
- REG_WRITE(ah, (u_int16_t) (AR_RTC_PLL_CONTROL), pll);
+ REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
udelay(RTC_PLL_SETTLE_DELAY);
REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
}
-static void ath9k_hw_set_regs(struct ath_hal *ah, struct hal_channel *chan,
- enum hal_ht_macmode macmode)
+static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
+ enum ath9k_ht_macmode macmode)
{
- u_int32_t phymode;
+ u32 phymode;
struct ath_hal_5416 *ahp = AH5416(ah);
phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
if (IS_CHAN_HT40(chan)) {
phymode |= AR_PHY_FC_DYN2040_EN;
- if (chan->channelFlags & CHANNEL_HT40PLUS)
+ if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
+ (chan->chanmode == CHANNEL_G_HT40PLUS))
phymode |= AR_PHY_FC_DYN2040_PRI_CH;
- if (ahp->ah_extprotspacing == HAL_HT_EXTPROTSPACING_25)
+ if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
phymode |= AR_PHY_FC_DYN2040_EXT_CH;
}
REG_WRITE(ah, AR_PHY_TURBO, phymode);
static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
{
- u_int32_t val;
+ u32 val;
val = REG_READ(ah, AR_STA_ID1);
val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
switch (opmode) {
- case HAL_M_HOSTAP:
+ case ATH9K_M_HOSTAP:
REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
| AR_STA_ID1_KSRCH_MODE);
REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
break;
- case HAL_M_IBSS:
+ case ATH9K_M_IBSS:
REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
| AR_STA_ID1_KSRCH_MODE);
REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
break;
- case HAL_M_STA:
- case HAL_M_MONITOR:
+ case ATH9K_M_STA:
+ case ATH9K_M_MONITOR:
REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
break;
}
}
static inline void
-ath9k_hw_set_rfmode(struct ath_hal *ah, struct hal_channel *chan)
+ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
{
- u_int32_t rfMode = 0;
+ u32 rfMode = 0;
if (chan == NULL)
return;
static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
{
- u_int32_t rst_flags;
- u_int32_t tmpReg;
+ u32 rst_flags;
+ u32 tmpReg;
REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
AR_RTC_FORCE_WAKE_ON_INT);
}
rst_flags = AR_RTC_RC_MAC_WARM;
- if (type == HAL_RESET_COLD)
+ if (type == ATH9K_RESET_COLD)
rst_flags |= AR_RTC_RC_MAC_COLD;
}
- REG_WRITE(ah, (u_int16_t) (AR_RTC_RC), rst_flags);
+ REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
udelay(50);
- REG_WRITE(ah, (u_int16_t) (AR_RTC_RC), 0);
- if (!ath9k_hw_wait(ah, (u_int16_t) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
+ REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
+ if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET,
"%s: RTC stuck in MAC reset\n",
__func__);
REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
AR_RTC_FORCE_WAKE_ON_INT);
- REG_WRITE(ah, (u_int16_t) (AR_RTC_RESET), 0);
- REG_WRITE(ah, (u_int16_t) (AR_RTC_RESET), 1);
+ REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
+ REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
if (!ath9k_hw_wait(ah,
AR_RTC_STATUS,
ath9k_hw_read_revisions(ah);
- return ath9k_hw_set_reset(ah, HAL_RESET_WARM);
+ return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
}
static bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
- u_int32_t type)
+ u32 type)
{
REG_WRITE(ah, AR_RTC_FORCE_WAKE,
AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
switch (type) {
- case HAL_RESET_POWER_ON:
+ case ATH9K_RESET_POWER_ON:
return ath9k_hw_set_reset_power_on(ah);
break;
- case HAL_RESET_WARM:
- case HAL_RESET_COLD:
+ case ATH9K_RESET_WARM:
+ case ATH9K_RESET_COLD:
return ath9k_hw_set_reset(ah, type);
break;
default:
}
}
-static inline struct hal_channel_internal *ath9k_hw_check_chan(
- struct ath_hal *ah, struct hal_channel *chan)
+static inline
+struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
+ struct ath9k_channel *chan)
{
- if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan, CHANNEL_5GHZ)) == 0) {
+ if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
"%s: invalid channel %u/0x%x; not marked as "
"2GHz or 5GHz\n", __func__, chan->channel,
return NULL;
}
- if ((IS(chan, CHANNEL_OFDM)
- ^ IS(chan, CHANNEL_CCK)
- ^ IS(chan, CHANNEL_HT20)
- ^ IS(chan, CHANNEL_HT40PLUS)
- ^ IS(chan, CHANNEL_HT40MINUS)) == 0) {
+ if (!IS_CHAN_OFDM(chan) &&
+ !IS_CHAN_CCK(chan) &&
+ !IS_CHAN_HT20(chan) &&
+ !IS_CHAN_HT40(chan)) {
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
- "%s: invalid channel %u/0x%x; not marked as "
- "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
- __func__, chan->channel, chan->channelFlags);
+ "%s: invalid channel %u/0x%x; not marked as "
+ "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
+ __func__, chan->channel, chan->channelFlags);
return NULL;
}
}
static inline bool
-ath9k_hw_get_lower_upper_index(u_int8_t target,
- u_int8_t *pList,
- u_int16_t listSize,
- u_int16_t *indexL,
- u_int16_t *indexR)
+ath9k_hw_get_lower_upper_index(u8 target,
+ u8 *pList,
+ u16 listSize,
+ u16 *indexL,
+ u16 *indexR)
{
- u_int16_t i;
+ u16 i;
if (target <= pList[0]) {
*indexL = *indexR = 0;
return true;
}
if (target >= pList[listSize - 1]) {
- *indexL = *indexR = (u_int16_t) (listSize - 1);
+ *indexL = *indexR = (u16) (listSize - 1);
return true;
}
}
if (target < pList[i + 1]) {
*indexL = i;
- *indexR = (u_int16_t) (i + 1);
+ *indexR = (u16) (i + 1);
return false;
}
}
static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
{
int16_t nfval;
- int16_t sort[HAL_NF_CAL_HIST_MAX];
+ int16_t sort[ATH9K_NF_CAL_HIST_MAX];
int i, j;
- for (i = 0; i < HAL_NF_CAL_HIST_MAX; i++)
+ for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
sort[i] = nfCalBuffer[i];
- for (i = 0; i < HAL_NF_CAL_HIST_MAX - 1; i++) {
- for (j = 1; j < HAL_NF_CAL_HIST_MAX - i; j++) {
+ for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
+ for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
if (sort[j] > sort[j - 1]) {
nfval = sort[j];
sort[j] = sort[j - 1];
}
}
}
- nfval = sort[(HAL_NF_CAL_HIST_MAX - 1) >> 1];
+ nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
return nfval;
}
-static void ath9k_hw_update_nfcal_hist_buffer(struct hal_nfcal_hist *h,
+static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
int16_t *nfarray)
{
int i;
for (i = 0; i < NUM_NF_READINGS; i++) {
h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
- if (++h[i].currIndex >= HAL_NF_CAL_HIST_MAX)
+ if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
h[i].currIndex = 0;
if (h[i].invalidNFcount > 0) {
if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE
|| nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
- h[i].invalidNFcount = HAL_NF_CAL_HIST_MAX;
+ h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
} else {
h[i].invalidNFcount--;
h[i].privNF = nfarray[i];
static bool
getNoiseFloorThresh(struct ath_hal *ah,
- const struct hal_channel_internal *chan,
+ const struct ath9k_channel *chan,
int16_t *nft)
{
struct ath_hal_5416 *ahp = AH5416(ah);
- switch (chan->channelFlags & CHANNEL_ALL) {
+ switch (chan->chanmode) {
case CHANNEL_A:
case CHANNEL_A_HT20:
case CHANNEL_A_HT40PLUS:
}
static void
-ath9k_hw_loadnf(struct ath_hal *ah, struct hal_channel_internal *chan)
+ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
{
- struct hal_nfcal_hist *h;
+ struct ath9k_nfcal_hist *h;
int i, j;
int32_t val;
- const u_int32_t ar5416_cca_regs[6] = {
+ const u32 ar5416_cca_regs[6] = {
AR_PHY_CCA,
AR_PHY_CH1_CCA,
AR_PHY_CH2_CCA,
AR_PHY_CH1_EXT_CCA,
AR_PHY_CH2_EXT_CCA
};
- u_int8_t chainmask;
+ u8 chainmask;
if (AR_SREV_9280(ah))
chainmask = 0x1B;
if (chainmask & (1 << i)) {
val = REG_READ(ah, ar5416_cca_regs[i]);
val &= 0xFFFFFE00;
- val |= (((u_int32_t) (h[i].privNF) << 1) & 0x1ff);
+ val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
REG_WRITE(ah, ar5416_cca_regs[i], val);
}
}
if (chainmask & (1 << i)) {
val = REG_READ(ah, ar5416_cca_regs[i]);
val &= 0xFFFFFE00;
- val |= (((u_int32_t) (-50) << 1) & 0x1ff);
+ val |= (((u32) (-50) << 1) & 0x1ff);
REG_WRITE(ah, ar5416_cca_regs[i], val);
}
}
}
static int16_t ath9k_hw_getnf(struct ath_hal *ah,
- struct hal_channel_internal *chan)
+ struct ath9k_channel *chan)
{
int16_t nf, nfThresh;
int16_t nfarray[NUM_NF_READINGS] = { 0 };
- struct hal_nfcal_hist *h;
- u_int8_t chainmask;
+ struct ath9k_nfcal_hist *h;
+ u8 chainmask;
if (AR_SREV_9280(ah))
chainmask = 0x1B;
}
static void ath9k_hw_update_mibstats(struct ath_hal *ah,
- struct hal_mib_stats *stats)
+ struct ath9k_mib_stats *stats)
{
stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
}
static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
- struct hal_channel_internal *chan)
+ struct ath9k_channel *chan)
{
struct ath_hal_5416 *ahp = AH5416(ah);
int i;
memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani));
for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
- ahp->ah_ani[i].ofdmTrigHigh = HAL_ANI_OFDM_TRIG_HIGH;
- ahp->ah_ani[i].ofdmTrigLow = HAL_ANI_OFDM_TRIG_LOW;
- ahp->ah_ani[i].cckTrigHigh = HAL_ANI_CCK_TRIG_HIGH;
- ahp->ah_ani[i].cckTrigLow = HAL_ANI_CCK_TRIG_LOW;
- ahp->ah_ani[i].rssiThrHigh = HAL_ANI_RSSI_THR_HIGH;
- ahp->ah_ani[i].rssiThrLow = HAL_ANI_RSSI_THR_LOW;
+ ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
+ ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
+ ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
+ ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
+ ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
+ ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
ahp->ah_ani[i].ofdmWeakSigDetectOff =
- !HAL_ANI_USE_OFDM_WEAK_SIG;
+ !ATH9K_ANI_USE_OFDM_WEAK_SIG;
ahp->ah_ani[i].cckWeakSigThreshold =
- HAL_ANI_CCK_WEAK_SIG_THR;
- ahp->ah_ani[i].spurImmunityLevel = HAL_ANI_SPUR_IMMUNE_LVL;
- ahp->ah_ani[i].firstepLevel = HAL_ANI_FIRSTEP_LVL;
+ ATH9K_ANI_CCK_WEAK_SIG_THR;
+ ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
+ ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
if (ahp->ah_hasHwPhyCounters) {
ahp->ah_ani[i].ofdmPhyErrBase =
- AR_PHY_COUNTMAX - HAL_ANI_OFDM_TRIG_HIGH;
+ AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
ahp->ah_ani[i].cckPhyErrBase =
- AR_PHY_COUNTMAX - HAL_ANI_CCK_TRIG_HIGH;
+ AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
}
}
if (ahp->ah_hasHwPhyCounters) {
REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
ath9k_enable_mib_counters(ah);
}
- ahp->ah_aniPeriod = HAL_ANI_PERIOD;
+ ahp->ah_aniPeriod = ATH9K_ANI_PERIOD;
if (ah->ah_config.ath_hal_enableANI)
ahp->ah_procPhyErr |= HAL_PROCESS_ANI;
}
static bool ath9k_hw_ani_control(struct ath_hal *ah,
- enum hal_ani_cmd cmd, int param)
+ enum ath9k_ani_cmd cmd, int param)
{
struct ath_hal_5416 *ahp = AH5416(ah);
struct ar5416AniState *aniState = ahp->ah_curani;
switch (cmd & ahp->ah_ani_function) {
- case HAL_ANI_NOISE_IMMUNITY_LEVEL:{
- u_int level = param;
+ case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
+ u32 level = param;
if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
aniState->noiseImmunityLevel = level;
break;
}
- case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
+ case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
const int m1ThreshLow[] = { 127, 50 };
const int m2ThreshLow[] = { 127, 40 };
const int m1Thresh[] = { 127, 0x4d };
const int m2Thresh[] = { 127, 0x40 };
const int m2CountThr[] = { 31, 16 };
const int m2CountThrLow[] = { 63, 48 };
- u_int on = param ? 1 : 0;
+ u32 on = param ? 1 : 0;
REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
}
break;
}
- case HAL_ANI_CCK_WEAK_SIGNAL_THR:{
+ case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
const int weakSigThrCck[] = { 8, 6 };
- u_int high = param ? 1 : 0;
+ u32 high = param ? 1 : 0;
REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
}
break;
}
- case HAL_ANI_FIRSTEP_LEVEL:{
+ case ATH9K_ANI_FIRSTEP_LEVEL:{
const int firstep[] = { 0, 4, 8 };
- u_int level = param;
+ u32 level = param;
if (level >= ARRAY_SIZE(firstep)) {
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
aniState->firstepLevel = level;
break;
}
- case HAL_ANI_SPUR_IMMUNITY_LEVEL:{
+ case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
const int cycpwrThr1[] =
{ 2, 4, 6, 8, 10, 12, 14, 16 };
- u_int level = param;
+ u32 level = param;
if (level >= ARRAY_SIZE(cycpwrThr1)) {
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
aniState->spurImmunityLevel = level;
break;
}
- case HAL_ANI_PRESENT:
+ case ATH9K_ANI_PRESENT:
break;
default:
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
{
struct ath_hal_5416 *ahp = AH5416(ah);
- struct hal_channel_internal *chan = ah->ah_curchan;
+ struct ath9k_channel *chan = ah->ah_curchan;
struct ar5416AniState *aniState;
enum wireless_mode mode;
int32_t rssi;
aniState = ahp->ah_curani;
if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
- if (ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
+ if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
aniState->noiseImmunityLevel + 1)) {
return;
}
}
if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
- if (ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
+ if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
aniState->spurImmunityLevel + 1)) {
return;
}
}
- if (ah->ah_opmode == HAL_M_HOSTAP) {
+ if (ah->ah_opmode == ATH9K_M_HOSTAP) {
if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
- ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
+ ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
aniState->firstepLevel + 1);
}
return;
if (rssi > aniState->rssiThrHigh) {
if (!aniState->ofdmWeakSigDetectOff) {
if (ath9k_hw_ani_control(ah,
- HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+ ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
false)) {
ath9k_hw_ani_control(ah,
- HAL_ANI_SPUR_IMMUNITY_LEVEL,
+ ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
0);
return;
}
}
if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
- ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
+ ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
aniState->firstepLevel + 1);
return;
}
} else if (rssi > aniState->rssiThrLow) {
if (aniState->ofdmWeakSigDetectOff)
ath9k_hw_ani_control(ah,
- HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
- true);
+ ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+ true);
if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
- ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
+ ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
aniState->firstepLevel + 1);
return;
} else {
- mode = ath9k_hw_chan2wmode(ah, (struct hal_channel *) chan);
+ mode = ath9k_hw_chan2wmode(ah, chan);
if (mode == WIRELESS_MODE_11g || mode == WIRELESS_MODE_11b) {
if (!aniState->ofdmWeakSigDetectOff)
ath9k_hw_ani_control(ah,
- HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
- false);
+ ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+ false);
if (aniState->firstepLevel > 0)
ath9k_hw_ani_control(ah,
- HAL_ANI_FIRSTEP_LEVEL,
+ ATH9K_ANI_FIRSTEP_LEVEL,
0);
return;
}
static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
{
struct ath_hal_5416 *ahp = AH5416(ah);
- struct hal_channel_internal *chan = ah->ah_curchan;
+ struct ath9k_channel *chan = ah->ah_curchan;
struct ar5416AniState *aniState;
enum wireless_mode mode;
int32_t rssi;
aniState = ahp->ah_curani;
if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
- if (ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
+ if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
aniState->noiseImmunityLevel + 1)) {
return;
}
}
- if (ah->ah_opmode == HAL_M_HOSTAP) {
+ if (ah->ah_opmode == ATH9K_M_HOSTAP) {
if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
- ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
+ ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
aniState->firstepLevel + 1);
}
return;
rssi = BEACON_RSSI(ahp);
if (rssi > aniState->rssiThrLow) {
if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
- ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
+ ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
aniState->firstepLevel + 1);
} else {
- mode = ath9k_hw_chan2wmode(ah, (struct hal_channel *) chan);
+ mode = ath9k_hw_chan2wmode(ah, chan);
if (mode == WIRELESS_MODE_11g || mode == WIRELESS_MODE_11b) {
if (aniState->firstepLevel > 0)
ath9k_hw_ani_control(ah,
- HAL_ANI_FIRSTEP_LEVEL,
+ ATH9K_ANI_FIRSTEP_LEVEL,
0);
}
}
{
struct ath_hal_5416 *ahp = AH5416(ah);
struct ar5416AniState *aniState;
- struct hal_channel_internal *chan = ah->ah_curchan;
+ struct ath9k_channel *chan = ah->ah_curchan;
int index;
if (!DO_ANI(ah))
aniState = &ahp->ah_ani[index];
ahp->ah_curani = aniState;
- if (DO_ANI(ah) && ah->ah_opmode != HAL_M_STA
- && ah->ah_opmode != HAL_M_IBSS) {
+ if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA
+ && ah->ah_opmode != ATH9K_M_IBSS) {
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"%s: Reset ANI state opmode %u\n", __func__,
ah->ah_opmode);
ahp->ah_stats.ast_ani_reset++;
- ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);
- ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
- ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL, 0);
+ ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
+ ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
+ ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
ath9k_hw_ani_control(ah,
- HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
- !HAL_ANI_USE_OFDM_WEAK_SIG);
- ath9k_hw_ani_control(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
- HAL_ANI_CCK_WEAK_SIG_THR);
+ ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+ !ATH9K_ANI_USE_OFDM_WEAK_SIG);
+ ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
+ ATH9K_ANI_CCK_WEAK_SIG_THR);
ath9k_hw_setrxfilter(ah,
ath9k_hw_getrxfilter(ah) |
- HAL_RX_FILTER_PHYERR);
- if (ah->ah_opmode == HAL_M_HOSTAP) {
+ ATH9K_RX_FILTER_PHYERR);
+ if (ah->ah_opmode == ATH9K_M_HOSTAP) {
ahp->ah_curani->ofdmTrigHigh =
ah->ah_config.ath_hal_ofdmTrigHigh;
ahp->ah_curani->ofdmTrigLow =
}
if (aniState->noiseImmunityLevel != 0)
- ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
+ ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
aniState->noiseImmunityLevel);
if (aniState->spurImmunityLevel != 0)
- ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
+ ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
aniState->spurImmunityLevel);
if (aniState->ofdmWeakSigDetectOff)
ath9k_hw_ani_control(ah,
- HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+ ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
!aniState->ofdmWeakSigDetectOff);
if (aniState->cckWeakSigThreshold)
- ath9k_hw_ani_control(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
+ ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
aniState->cckWeakSigThreshold);
if (aniState->firstepLevel != 0)
- ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
+ ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
aniState->firstepLevel);
if (ahp->ah_hasHwPhyCounters) {
ath9k_hw_setrxfilter(ah,
ath9k_hw_getrxfilter(ah) &
- ~HAL_RX_FILTER_PHYERR);
+ ~ATH9K_RX_FILTER_PHYERR);
ath9k_ani_restart(ah);
REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
ath9k_ani_restart(ah);
ath9k_hw_setrxfilter(ah,
ath9k_hw_getrxfilter(ah) |
- HAL_RX_FILTER_PHYERR);
+ ATH9K_RX_FILTER_PHYERR);
}
}
void ath9k_hw_procmibevent(struct ath_hal *ah,
- const struct hal_node_stats *stats)
+ const struct ath9k_node_stats *stats)
{
struct ath_hal_5416 *ahp = AH5416(ah);
- u_int32_t phyCnt1, phyCnt2;
+ u32 phyCnt1, phyCnt2;
DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Processing Mib Intr\n");
if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
struct ar5416AniState *aniState = ahp->ah_curani;
- u_int32_t ofdmPhyErrCnt, cckPhyErrCnt;
+ u32 ofdmPhyErrCnt, cckPhyErrCnt;
ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
ahp->ah_stats.ast_ani_ofdmerrs +=
aniState = ahp->ah_curani;
- if (ah->ah_opmode == HAL_M_HOSTAP) {
+ if (ah->ah_opmode == ATH9K_M_HOSTAP) {
if (aniState->firstepLevel > 0) {
- if (ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
+ if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
aniState->firstepLevel - 1)) {
return;
}
} else if (rssi > aniState->rssiThrLow) {
if (aniState->ofdmWeakSigDetectOff) {
if (ath9k_hw_ani_control(ah,
- HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+ ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
true) ==
true) {
return;
}
if (aniState->firstepLevel > 0) {
if (ath9k_hw_ani_control
- (ah, HAL_ANI_FIRSTEP_LEVEL,
+ (ah, ATH9K_ANI_FIRSTEP_LEVEL,
aniState->firstepLevel - 1) ==
true) {
return;
} else {
if (aniState->firstepLevel > 0) {
if (ath9k_hw_ani_control
- (ah, HAL_ANI_FIRSTEP_LEVEL,
+ (ah, ATH9K_ANI_FIRSTEP_LEVEL,
aniState->firstepLevel - 1) ==
true) {
return;
}
if (aniState->spurImmunityLevel > 0) {
- if (ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
+ if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
aniState->spurImmunityLevel - 1)) {
return;
}
}
if (aniState->noiseImmunityLevel > 0) {
- ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
+ ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
aniState->noiseImmunityLevel - 1);
return;
}
{
struct ath_hal_5416 *ahp = AH5416(ah);
struct ar5416AniState *aniState;
- u_int32_t txFrameCount, rxFrameCount, cycleCount;
+ u32 txFrameCount, rxFrameCount, cycleCount;
int32_t listenTime;
txFrameCount = REG_READ(ah, AR_TFCNT);
}
void ath9k_hw_ani_monitor(struct ath_hal *ah,
- const struct hal_node_stats *stats,
- struct hal_channel *chan)
+ const struct ath9k_node_stats *stats,
+ struct ath9k_channel *chan)
{
struct ath_hal_5416 *ahp = AH5416(ah);
struct ar5416AniState *aniState;
aniState->listenTime += listenTime;
if (ahp->ah_hasHwPhyCounters) {
- u_int32_t phyCnt1, phyCnt2;
- u_int32_t ofdmPhyErrCnt, cckPhyErrCnt;
+ u32 phyCnt1, phyCnt2;
+ u32 ofdmPhyErrCnt, cckPhyErrCnt;
ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE;
ah->nfCalHist[i].invalidNFcount =
AR_PHY_CCA_FILTERWINDOW_LENGTH;
- for (j = 0; j < HAL_NF_CAL_HIST_MAX; j++) {
+ for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
ah->nfCalHist[i].nfCalBuffer[j] =
AR_PHY_CCA_MAX_GOOD_VALUE;
}
#endif
static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
- u_int32_t gpio, u_int32_t type)
+ u32 gpio, u32 type)
{
int addr;
- u_int32_t gpio_shift, tmp;
+ u32 gpio_shift, tmp;
if (gpio > 11)
addr = AR_GPIO_OUTPUT_MUX3;
}
}
-static bool ath9k_hw_cfg_output(struct ath_hal *ah, u_int32_t gpio,
- enum hal_gpio_output_mux_type
+static bool ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
+ enum ath9k_gpio_output_mux_type
halSignalType)
{
- u_int32_t ah_signal_type;
- u_int32_t gpio_shift;
+ u32 ah_signal_type;
+ u32 gpio_shift;
- static u_int32_t MuxSignalConversionTable[] = {
+ static u32 MuxSignalConversionTable[] = {
AR_GPIO_OUTPUT_MUX_AS_OUTPUT,
return true;
}
-static bool ath9k_hw_set_gpio(struct ath_hal *ah, u_int32_t gpio,
- u_int32_t val)
+static bool ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio,
+ u32 val)
{
REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
AR_GPIO_BIT(gpio));
return true;
}
-static u_int32_t ath9k_hw_gpio_get(struct ath_hal *ah, u_int32_t gpio)
+static u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
{
if (gpio >= ah->ah_caps.halNumGpioPins)
return 0xffffffff;
}
}
-static inline enum hal_status ath9k_hw_post_attach(struct ath_hal *ah)
+static inline int ath9k_hw_post_attach(struct ath_hal *ah)
{
- enum hal_status ecode;
+ int ecode;
if (!ath9k_hw_chip_test(ah)) {
DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
"%s: hardware self-test failed\n", __func__);
- return HAL_ESELFTEST;
+ return -ENODEV;
}
ecode = ath9k_hw_rf_claim(ah);
- if (ecode != HAL_OK)
+ if (ecode != 0)
return ecode;
ecode = ath9k_hw_eeprom_attach(ah);
- if (ecode != HAL_OK)
+ if (ecode != 0)
return ecode;
ecode = ath9k_hw_rfattach(ah);
- if (ecode != HAL_OK)
+ if (ecode != 0)
return ecode;
if (!AR_SREV_9100(ah)) {
ath9k_hw_ani_setup(ah);
ath9k_hw_ani_attach(ah);
}
- return HAL_OK;
+ return 0;
}
-static u_int32_t ath9k_hw_ini_fixup(struct ath_hal *ah,
+static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
struct ar5416_eeprom *pEepData,
- u_int32_t reg, u_int32_t value)
+ u32 reg, u32 value)
{
struct base_eep_header *pBase = &(pEepData->baseEepHeader);
{
struct ath_hal_5416 *ahp = AH5416(ah);
struct hal_capabilities *pCap = &ah->ah_caps;
- u_int16_t capField = 0, eeval;
+ u16 capField = 0, eeval;
eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_0);
capField = ath9k_hw_get_eeprom(ahp, EEP_OP_CAP);
- if (ah->ah_opmode != HAL_M_HOSTAP &&
+ if (ah->ah_opmode != ATH9K_M_HOSTAP &&
ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
ah->ah_currentRD += 5;
pCap->halTotalQueues =
MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
else
- pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
+ pCap->halTotalQueues = ATH9K_NUM_TX_QUEUES;
if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
pCap->halKeyCacheSize =
if (!AR_SREV_9100(ah))
REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
- REG_CLR_BIT(ah, (u_int16_t) (AR_RTC_RESET),
+ REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
AR_RTC_RESET_EN);
}
}
static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
int setChip)
{
- u_int32_t val;
+ u32 val;
int i;
if (setChip) {
if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
AR_RTC_STATUS_SHUTDOWN) {
- if (ath9k_hw_set_reset_reg(ah, HAL_RESET_POWER_ON)
+ if (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)
!= true) {
return false;
}
}
bool ath9k_hw_setpower(struct ath_hal *ah,
- enum hal_power_mode mode)
+ enum ath9k_power_mode mode)
{
struct ath_hal_5416 *ahp = AH5416(ah);
static const char *modes[] = {
setChip ? "set chip " : "");
switch (mode) {
- case HAL_PM_AWAKE:
+ case ATH9K_PM_AWAKE:
status = ath9k_hw_set_power_awake(ah, setChip);
break;
- case HAL_PM_FULL_SLEEP:
+ case ATH9K_PM_FULL_SLEEP:
ath9k_set_power_sleep(ah, setChip);
ahp->ah_chipFullSleep = true;
break;
- case HAL_PM_NETWORK_SLEEP:
+ case ATH9K_PM_NETWORK_SLEEP:
ath9k_set_power_network_sleep(ah, setChip);
break;
default:
return status;
}
-static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid,
+static struct ath_hal *ath9k_hw_do_attach(u16 devid,
struct ath_softc *sc,
void __iomem *mem,
- enum hal_status *status)
+ int *status)
{
struct ath_hal_5416 *ahp;
struct ath_hal *ah;
- enum hal_status ecode;
+ int ecode;
#ifndef CONFIG_SLOW_ANT_DIV
- u_int32_t i;
- u_int32_t j;
+ u32 i;
+ u32 j;
#endif
ahp = ath9k_hw_newstate(devid, sc, mem, status);
if (ah->ah_config.ath_hal_intrMitigation != 0)
ahp->ah_intrMitigation = true;
- if (!ath9k_hw_set_reset_reg(ah, HAL_RESET_POWER_ON)) {
+ if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n",
__func__);
- ecode = HAL_EIO;
+ ecode = -EIO;
goto bad;
}
- if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE)) {
+ if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n",
__func__);
- ecode = HAL_EIO;
+ ecode = -EIO;
goto bad;
}
"%s: Mac Chip Rev 0x%02x.%x is not supported by "
"this driver\n", __func__,
ah->ah_macVersion, ah->ah_macRev);
- ecode = HAL_ENOTSUPP;
+ ecode = -EOPNOTSUPP;
goto bad;
}
if (AR_SREV_9160(ah)) {
ah->ah_config.ath_hal_enableANI = 1;
- ahp->ah_ani_function = (HAL_ANI_SPUR_IMMUNITY_LEVEL |
- HAL_ANI_FIRSTEP_LEVEL);
+ ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
+ ATH9K_ANI_FIRSTEP_LEVEL);
} else {
- ahp->ah_ani_function = HAL_ANI_ALL;
+ ahp->ah_ani_function = ATH9K_ANI_ALL;
if (AR_SREV_9280_10_OR_LATER(ah)) {
ahp->ah_ani_function &=
- ~HAL_ANI_NOISE_IMMUNITY_LEVEL;
+ ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
}
}
ar5416DisablePciePhy(ah);
ecode = ath9k_hw_post_attach(ah);
- if (ecode != HAL_OK)
+ if (ecode != 0)
goto bad;
#ifndef CONFIG_SLOW_ANT_DIV
if (ah->ah_devid == AR9280_DEVID_PCI) {
for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
- u_int32_t reg = INI_RA(&ahp->ah_iniModes, i, 0);
+ u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
- u_int32_t val = INI_RA(&ahp->ah_iniModes, i, j);
+ u32 val = INI_RA(&ahp->ah_iniModes, i, j);
INI_RA(&ahp->ah_iniModes, i, j) =
ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,
if (!ath9k_hw_fill_cap_info(ah)) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET,
"%s:failed ath9k_hw_fill_cap_info\n", __func__);
- ecode = HAL_EEREAD;
+ ecode = -EINVAL;
goto bad;
}
ecode = ath9k_hw_init_macaddr(ah);
- if (ecode != HAL_OK) {
+ if (ecode != 0) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET,
"%s: failed initializing mac address\n",
__func__);
ath9k_hw_ani_detach(ah);
ath9k_hw_rfdetach(ah);
- ath9k_hw_setpower(ah, HAL_PM_FULL_SLEEP);
+ ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
kfree(ah);
}
bool ath9k_get_channel_edges(struct ath_hal *ah,
- u_int16_t flags, u_int16_t *low,
- u_int16_t *high)
+ u16 flags, u16 *low,
+ u16 *high)
{
struct hal_capabilities *pCap = &ah->ah_caps;
return false;
}
-static inline bool ath9k_hw_fill_vpd_table(u_int8_t pwrMin,
- u_int8_t pwrMax,
- u_int8_t *pPwrList,
- u_int8_t *pVpdList,
- u_int16_t
+static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin,
+ u8 pwrMax,
+ u8 *pPwrList,
+ u8 *pVpdList,
+ u16
numIntercepts,
- u_int8_t *pRetVpdList)
+ u8 *pRetVpdList)
{
- u_int16_t i, k;
- u_int8_t currPwr = pwrMin;
- u_int16_t idxL = 0, idxR = 0;
+ u16 i, k;
+ u8 currPwr = pwrMin;
+ u16 idxL = 0, idxR = 0;
for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
if (idxR < 1)
idxR = 1;
if (idxL == numIntercepts - 1)
- idxL = (u_int16_t) (numIntercepts - 2);
+ idxL = (u16) (numIntercepts - 2);
if (pPwrList[idxL] == pPwrList[idxR])
k = pVpdList[idxL];
else
- k = (u_int16_t) (((currPwr -
+ k = (u16) (((currPwr -
pPwrList[idxL]) *
pVpdList[idxR] +
(pPwrList[idxR] -
currPwr) * pVpdList[idxL]) /
(pPwrList[idxR] -
pPwrList[idxL]));
- pRetVpdList[i] = (u_int8_t) k;
+ pRetVpdList[i] = (u8) k;
currPwr += 2;
}
static inline void
ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
- struct hal_channel_internal *chan,
+ struct ath9k_channel *chan,
struct cal_data_per_freq *pRawDataSet,
- u_int8_t *bChans,
- u_int16_t availPiers,
- u_int16_t tPdGainOverlap,
+ u8 *bChans,
+ u16 availPiers,
+ u16 tPdGainOverlap,
int16_t *pMinCalPower,
- u_int16_t *pPdGainBoundaries,
- u_int8_t *pPDADCValues,
- u_int16_t numXpdGains)
+ u16 *pPdGainBoundaries,
+ u8 *pPDADCValues,
+ u16 numXpdGains)
{
int i, j, k;
int16_t ss;
- u_int16_t idxL = 0, idxR = 0, numPiers;
- static u_int8_t vpdTableL[AR5416_NUM_PD_GAINS]
+ u16 idxL = 0, idxR = 0, numPiers;
+ static u8 vpdTableL[AR5416_NUM_PD_GAINS]
[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
- static u_int8_t vpdTableR[AR5416_NUM_PD_GAINS]
+ static u8 vpdTableR[AR5416_NUM_PD_GAINS]
[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
- static u_int8_t vpdTableI[AR5416_NUM_PD_GAINS]
+ static u8 vpdTableI[AR5416_NUM_PD_GAINS]
[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
- u_int8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR;
- u_int8_t minPwrT4[AR5416_NUM_PD_GAINS];
- u_int8_t maxPwrT4[AR5416_NUM_PD_GAINS];
+ u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
+ u8 minPwrT4[AR5416_NUM_PD_GAINS];
+ u8 maxPwrT4[AR5416_NUM_PD_GAINS];
int16_t vpdStep;
int16_t tmpVal;
- u_int16_t sizeCurrVpdTable, maxIndex, tgtIndex;
+ u16 sizeCurrVpdTable, maxIndex, tgtIndex;
bool match;
int16_t minDelta = 0;
struct chan_centers centers;
break;
}
- match = ath9k_hw_get_lower_upper_index((u_int8_t)
+ match = ath9k_hw_get_lower_upper_index((u8)
FREQ2FBIN(centers.
synth_center,
IS_CHAN_2GHZ
for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
vpdTableI[i][j] =
- (u_int8_t) (ath9k_hw_interpolate
- ((u_int16_t)
+ (u8) (ath9k_hw_interpolate
+ ((u16)
FREQ2FBIN(centers.
synth_center,
IS_CHAN_2GHZ
for (i = 0; i < numXpdGains; i++) {
if (i == (numXpdGains - 1))
pPdGainBoundaries[i] =
- (u_int16_t) (maxPwrT4[i] / 2);
+ (u16) (maxPwrT4[i] / 2);
else
pPdGainBoundaries[i] =
- (u_int16_t) ((maxPwrT4[i] +
+ (u16) ((maxPwrT4[i] +
minPwrT4[i + 1]) / 4);
pPdGainBoundaries[i] =
- min((u_int16_t) AR5416_MAX_RATE_POWER,
+ min((u16) AR5416_MAX_RATE_POWER,
pPdGainBoundaries[i]);
if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
tmpVal = (int16_t) (vpdTableI[i][0] + ss * vpdStep);
pPDADCValues[k++] =
- (u_int8_t) ((tmpVal < 0) ? 0 : tmpVal);
+ (u8) ((tmpVal < 0) ? 0 : tmpVal);
ss++;
}
sizeCurrVpdTable =
- (u_int8_t) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
- tgtIndex = (u_int8_t) (pPdGainBoundaries[i] + tPdGainOverlap -
+ (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
+ tgtIndex = (u8) (pPdGainBoundaries[i] + tPdGainOverlap -
(minPwrT4[i] / 2));
maxIndex = (tgtIndex <
sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
[sizeCurrVpdTable -
1] + (ss - maxIndex +
1) * vpdStep));
- pPDADCValues[k++] = (u_int8_t) ((tmpVal >
+ pPDADCValues[k++] = (u8) ((tmpVal >
255) ? 255 : tmpVal);
ss++;
}
static inline bool
ath9k_hw_set_power_cal_table(struct ath_hal *ah,
struct ar5416_eeprom *pEepData,
- struct hal_channel_internal *chan,
+ struct ath9k_channel *chan,
int16_t *pTxPowerIndexOffset)
{
struct cal_data_per_freq *pRawDataset;
- u_int8_t *pCalBChans = NULL;
- u_int16_t pdGainOverlap_t2;
- static u_int8_t pdadcValues[AR5416_NUM_PDADC_VALUES];
- u_int16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK];
- u_int16_t numPiers, i, j;
+ u8 *pCalBChans = NULL;
+ u16 pdGainOverlap_t2;
+ static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
+ u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
+ u16 numPiers, i, j;
int16_t tMinCalPower;
- u_int16_t numXpdGain, xpdMask;
- u_int16_t xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
- u_int32_t reg32, regOffset, regChainOffset;
+ u16 numXpdGain, xpdMask;
+ u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
+ u32 reg32, regOffset, regChainOffset;
int16_t modalIdx;
struct ath_hal_5416 *ahp = AH5416(ah);
pEepData->modalHeader[modalIdx].pdGainOverlap;
} else {
pdGainOverlap_t2 =
- (u_int16_t) (MS
+ (u16) (MS
(REG_READ(ah, AR_PHY_TPCRG5),
AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
}
if (numXpdGain >= AR5416_NUM_PD_GAINS)
break;
xpdGainValues[numXpdGain] =
- (u_int16_t) (AR5416_PD_GAINS_IN_MASK - i);
+ (u16) (AR5416_PD_GAINS_IN_MASK - i);
numXpdGain++;
}
}
void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
{
struct ath_hal_5416 *ahp = AH5416(ah);
- u_int8_t i;
+ u8 i;
if (ah->ah_isPciExpress != true)
return;
static inline void
ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
- struct hal_channel_internal *chan,
+ struct ath9k_channel *chan,
struct cal_target_power_leg *powInfo,
- u_int16_t numChannels,
+ u16 numChannels,
struct cal_target_power_leg *pNewPower,
- u_int16_t numRates,
+ u16 numRates,
bool isExtTarget)
{
- u_int16_t clo, chi;
+ u16 clo, chi;
int i;
int matchIndex = -1, lowIndex = -1;
- u_int16_t freq;
+ u16 freq;
struct chan_centers centers;
ath9k_hw_get_channel_centers(ah, chan, ¢ers);
for (i = 0; i < numRates; i++) {
pNewPower->tPow2x[i] =
- (u_int8_t) ath9k_hw_interpolate(freq, clo, chi,
+ (u8) ath9k_hw_interpolate(freq, clo, chi,
powInfo
[lowIndex].
tPow2x[i],
static inline void
ath9k_hw_get_target_powers(struct ath_hal *ah,
- struct hal_channel_internal *chan,
+ struct ath9k_channel *chan,
struct cal_target_power_ht *powInfo,
- u_int16_t numChannels,
+ u16 numChannels,
struct cal_target_power_ht *pNewPower,
- u_int16_t numRates,
+ u16 numRates,
bool isHt40Target)
{
- u_int16_t clo, chi;
+ u16 clo, chi;
int i;
int matchIndex = -1, lowIndex = -1;
- u_int16_t freq;
+ u16 freq;
struct chan_centers centers;
ath9k_hw_get_channel_centers(ah, chan, ¢ers);
for (i = 0; i < numRates; i++) {
pNewPower->tPow2x[i] =
- (u_int8_t) ath9k_hw_interpolate(freq, clo, chi,
+ (u8) ath9k_hw_interpolate(freq, clo, chi,
powInfo
[lowIndex].
tPow2x[i],
}
}
-static inline u_int16_t
-ath9k_hw_get_max_edge_power(u_int16_t freq,
+static inline u16
+ath9k_hw_get_max_edge_power(u16 freq,
struct cal_ctl_edges *pRdEdgesPower,
bool is2GHz)
{
- u_int16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+ u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
int i;
for (i = 0; (i < AR5416_NUM_BAND_EDGES)
static inline bool
ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
struct ar5416_eeprom *pEepData,
- struct hal_channel_internal *chan,
+ struct ath9k_channel *chan,
int16_t *ratesArray,
- u_int16_t cfgCtl,
- u_int8_t AntennaReduction,
- u_int8_t twiceMaxRegulatoryPower,
- u_int8_t powerLimit)
+ u16 cfgCtl,
+ u8 AntennaReduction,
+ u8 twiceMaxRegulatoryPower,
+ u8 powerLimit)
{
- u_int8_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
- static const u_int16_t tpScaleReductionTable[5] =
+ u8 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+ static const u16 tpScaleReductionTable[5] =
{ 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
int i;
struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
0, {0, 0, 0, 0}
};
- u_int8_t scaledPower = 0, minCtlPower, maxRegAllowedPower;
- u_int16_t ctlModesFor11a[] =
+ u8 scaledPower = 0, minCtlPower, maxRegAllowedPower;
+ u16 ctlModesFor11a[] =
{ CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
- u_int16_t ctlModesFor11g[] =
+ u16 ctlModesFor11g[] =
{ CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
CTL_2GHT40
};
- u_int16_t numCtlModes, *pCtlMode, ctlMode, freq;
+ u16 numCtlModes, *pCtlMode, ctlMode, freq;
struct chan_centers centers;
int tx_chainmask;
- u_int8_t twiceMinEdgePower;
+ u8 twiceMinEdgePower;
struct ath_hal_5416 *ahp = AH5416(ah);
tx_chainmask = ahp->ah_txchainmask;
pEepData->modalHeader
[IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
- twiceLargestAntenna = max((u_int8_t) twiceLargestAntenna,
+ twiceLargestAntenna = max((u8) twiceLargestAntenna,
pEepData->modalHeader
[IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
- if (ah->ah_tpScale != HAL_TP_SCALE_MAX) {
+ if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) {
maxRegAllowedPower -=
(tpScaleReductionTable[(ah->ah_tpScale)] * 2);
}
for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i];
i++) {
DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
- " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
+ " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
"pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
- "chan %d chanctl 0x%x\n",
- i, cfgCtl, pCtlMode[ctlMode],
- pEepData->ctlIndex[i], chan->channel,
- chan->conformanceTestLimit);
+ "chan %d\n",
+ i, cfgCtl, pCtlMode[ctlMode],
+ pEepData->ctlIndex[i], chan->channel);
if ((((cfgCtl & ~CTL_MODE_M) |
(pCtlMode[ctlMode] & CTL_MODE_M)) ==
return true;
}
-static enum hal_status
+static int
ath9k_hw_set_txpower(struct ath_hal *ah,
struct ar5416_eeprom *pEepData,
- struct hal_channel_internal *chan,
- u_int16_t cfgCtl,
- u_int8_t twiceAntennaReduction,
- u_int8_t twiceMaxRegulatoryPower,
- u_int8_t powerLimit)
+ struct ath9k_channel *chan,
+ u16 cfgCtl,
+ u8 twiceAntennaReduction,
+ u8 twiceMaxRegulatoryPower,
+ u8 powerLimit)
{
struct modal_eep_header *pModal =
&(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
int16_t ratesArray[Ar5416RateSize];
int16_t txPowerIndexOffset = 0;
- u_int8_t ht40PowerIncForPdadc = 2;
+ u8 ht40PowerIncForPdadc = 2;
int i;
memset(ratesArray, 0, sizeof(ratesArray));
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"ath9k_hw_set_txpower: unable to set "
"tx power per rate table\n");
- return HAL_EIO;
+ return -EIO;
}
if (!ath9k_hw_set_power_cal_table
(ah, pEepData, chan, &txPowerIndexOffset)) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"ath9k_hw_set_txpower: unable to set power table\n");
- return HAL_EIO;
+ return -EIO;
}
for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
else
ah->ah_maxPowerLevel = ratesArray[i];
- return HAL_OK;
+ return 0;
}
static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
- u_int32_t coef_scaled,
- u_int32_t *coef_mantissa,
- u_int32_t *coef_exponent)
+ u32 coef_scaled,
+ u32 *coef_mantissa,
+ u32 *coef_exponent)
{
- u_int32_t coef_exp, coef_man;
+ u32 coef_exp, coef_man;
for (coef_exp = 31; coef_exp > 0; coef_exp--)
if ((coef_scaled >> coef_exp) & 0x1)
static void
ath9k_hw_set_delta_slope(struct ath_hal *ah,
- struct hal_channel_internal *chan)
+ struct ath9k_channel *chan)
{
- u_int32_t coef_scaled, ds_coef_exp, ds_coef_man;
- u_int32_t clockMhzScaled = 0x64000000;
+ u32 coef_scaled, ds_coef_exp, ds_coef_man;
+ u32 clockMhzScaled = 0x64000000;
struct chan_centers centers;
if (IS_CHAN_HALF_RATE(chan))
}
static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
- struct hal_channel *chan,
- struct hal_channel_internal *ichan)
+ struct ath9k_channel *chan)
{
int bb_spur = AR_NO_SPUR;
int freq;
memset(&mask_m, 0, sizeof(int8_t) * 123);
memset(&mask_p, 0, sizeof(int8_t) * 123);
- ath9k_hw_get_channel_centers(ah, ichan, ¢ers);
+ ath9k_hw_get_channel_centers(ah, chan, ¢ers);
freq = centers.synth_center;
ah->ah_config.ath_hal_spurMode = SPUR_ENABLE_EEPROM;
}
static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
- struct hal_channel *chan)
+ struct ath9k_channel *chan)
{
int bb_spur = AR_NO_SPUR;
int bin, cur_bin;
}
static void ath9k_hw_set_addac(struct ath_hal *ah,
- struct hal_channel_internal *chan)
+ struct ath9k_channel *chan)
{
struct modal_eep_header *pModal;
struct ath_hal_5416 *ahp = AH5416(ah);
struct ar5416_eeprom *eep = &ahp->ah_eeprom;
- u_int8_t biaslevel;
+ u8 biaslevel;
if (ah->ah_macVersion != AR_SREV_VERSION_9160)
return;
biaslevel = pModal->xpaBiasLvl;
} else {
- u_int16_t resetFreqBin, freqBin, freqCount = 0;
+ u16 resetFreqBin, freqBin, freqCount = 0;
struct chan_centers centers;
ath9k_hw_get_channel_centers(ah, chan, ¢ers);
resetFreqBin =
FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan));
freqBin = pModal->xpaBiasLvlFreq[0] & 0xff;
- biaslevel = (u_int8_t) (pModal->xpaBiasLvlFreq[0] >> 14);
+ biaslevel = (u8) (pModal->xpaBiasLvlFreq[0] >> 14);
freqCount++;
freqBin = pModal->xpaBiasLvlFreq[freqCount] & 0xff;
if (resetFreqBin >= freqBin) {
biaslevel =
- (u_int8_t) (pModal->
+ (u8) (pModal->
xpaBiasLvlFreq[freqCount]
>> 14);
} else {
}
}
-static u_int ath9k_hw_mac_usec(struct ath_hal *ah, u_int clks)
+static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
{
- const struct hal_channel *c =
- (const struct hal_channel *) ah->ah_curchan;
-
- if (c != NULL)
- return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, c)];
+ if (ah->ah_curchan != NULL)
+ return clks /
+ CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
else
return clks / CLOCK_RATE[WIRELESS_MODE_11b];
}
-static u_int ath9k_hw_mac_to_usec(struct ath_hal *ah, u_int clks)
+static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
{
- struct hal_channel_internal *chan = ah->ah_curchan;
+ struct ath9k_channel *chan = ah->ah_curchan;
if (chan && IS_CHAN_HT40(chan))
return ath9k_hw_mac_usec(ah, clks) / 2;
return ath9k_hw_mac_usec(ah, clks);
}
-static u_int ath9k_hw_mac_clks(struct ath_hal *ah, u_int usecs)
+static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
{
- const struct hal_channel *c =
- (const struct hal_channel *) ah->ah_curchan;
-
- if (c != NULL)
- return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah, c)];
+ if (ah->ah_curchan != NULL)
+ return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
+ ah->ah_curchan)];
else
return usecs * CLOCK_RATE[WIRELESS_MODE_11b];
}
-static u_int ath9k_hw_mac_to_clks(struct ath_hal *ah, u_int usecs)
+static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
{
- struct hal_channel_internal *chan = ah->ah_curchan;
+ struct ath9k_channel *chan = ah->ah_curchan;
if (chan && IS_CHAN_HT40(chan))
return ath9k_hw_mac_clks(ah, usecs) * 2;
return ath9k_hw_mac_clks(ah, usecs);
}
-static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u_int us)
+static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
{
struct ath_hal_5416 *ahp = AH5416(ah);
if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n",
__func__, us);
- ahp->ah_acktimeout = (u_int) -1;
+ ahp->ah_acktimeout = (u32) -1;
return false;
} else {
REG_RMW_FIELD(ah, AR_TIME_OUT,
}
}
-static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u_int us)
+static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
{
struct ath_hal_5416 *ahp = AH5416(ah);
if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n",
__func__, us);
- ahp->ah_ctstimeout = (u_int) -1;
+ ahp->ah_ctstimeout = (u32) -1;
return false;
} else {
REG_RMW_FIELD(ah, AR_TIME_OUT,
}
}
static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah,
- u_int tu)
+ u32 tu)
{
struct ath_hal_5416 *ahp = AH5416(ah);
if (tu > 0xFFFF) {
DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
"%s: bad global tx timeout %u\n", __func__, tu);
- ahp->ah_globaltxtimeout = (u_int) -1;
+ ahp->ah_globaltxtimeout = (u32) -1;
return false;
} else {
REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
}
}
-bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us)
+bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
{
struct ath_hal_5416 *ahp = AH5416(ah);
- if (us < HAL_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
+ if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n",
__func__, us);
- ahp->ah_slottime = (u_int) -1;
+ ahp->ah_slottime = (u32) -1;
return false;
} else {
REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
if (ahp->ah_miscMode != 0)
REG_WRITE(ah, AR_PCU_MISC,
REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
- if (ahp->ah_slottime != (u_int) -1)
+ if (ahp->ah_slottime != (u32) -1)
ath9k_hw_setslottime(ah, ahp->ah_slottime);
- if (ahp->ah_acktimeout != (u_int) -1)
+ if (ahp->ah_acktimeout != (u32) -1)
ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
- if (ahp->ah_ctstimeout != (u_int) -1)
+ if (ahp->ah_ctstimeout != (u32) -1)
ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
- if (ahp->ah_globaltxtimeout != (u_int) -1)
+ if (ahp->ah_globaltxtimeout != (u32) -1)
ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
}
-static inline enum hal_status
+static inline int
ath9k_hw_process_ini(struct ath_hal *ah,
- struct hal_channel *chan,
- struct hal_channel_internal *ichan,
- enum hal_ht_macmode macmode)
+ struct ath9k_channel *chan,
+ enum ath9k_ht_macmode macmode)
{
int i, regWrites = 0;
struct ath_hal_5416 *ahp = AH5416(ah);
- u_int modesIndex, freqIndex;
- enum hal_status status;
+ u32 modesIndex, freqIndex;
+ int status;
- switch (chan->channelFlags & CHANNEL_ALL) {
+ switch (chan->chanmode) {
case CHANNEL_A:
case CHANNEL_A_HT20:
modesIndex = 1;
modesIndex = 2;
freqIndex = 1;
break;
- case CHANNEL_PUREG:
+ case CHANNEL_G:
case CHANNEL_G_HT20:
case CHANNEL_B:
modesIndex = 4;
break;
default:
- return HAL_EINVAL;
+ return -EINVAL;
}
REG_WRITE(ah, AR_PHY(0), 0x00000007);
REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
- ath9k_hw_set_addac(ah, ichan);
+ ath9k_hw_set_addac(ah, chan);
if (AR_SREV_5416_V22_OR_LATER(ah)) {
REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
} else {
struct ar5416IniArray temp;
- u_int32_t addacSize =
- sizeof(u_int32_t) * ahp->ah_iniAddac.ia_rows *
+ u32 addacSize =
+ sizeof(u32) * ahp->ah_iniAddac.ia_rows *
ahp->ah_iniAddac.ia_columns;
memcpy(ahp->ah_addac5416_21,
REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
- u_int32_t reg = INI_RA(&ahp->ah_iniModes, i, 0);
- u_int32_t val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
+ u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
+ u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
#ifdef CONFIG_SLOW_ANT_DIV
if (ah->ah_devid == AR9280_DEVID_PCI)
}
for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
- u_int32_t reg = INI_RA(&ahp->ah_iniCommon, i, 0);
- u_int32_t val = INI_RA(&ahp->ah_iniCommon, i, 1);
+ u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
+ u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
REG_WRITE(ah, reg, val);
ath9k_hw_set_regs(ah, chan, macmode);
ath9k_hw_init_chain_masks(ah);
- status = ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, ichan,
+ status = ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
ath9k_regd_get_ctl(ah, chan),
ath9k_regd_get_antenna_allowed(ah,
chan),
- ichan->maxRegTxPower * 2,
- min((u_int32_t) MAX_RATE_POWER,
- (u_int32_t) ah->ah_powerLimit));
- if (status != HAL_OK) {
+ chan->maxRegTxPower * 2,
+ min((u32) MAX_RATE_POWER,
+ (u32) ah->ah_powerLimit));
+ if (status != 0) {
DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
"%s: error init'ing transmit power\n", __func__);
- return HAL_EIO;
+ return -EIO;
}
- if (!ath9k_hw_set_rf_regs(ah, ichan, freqIndex)) {
+ if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
"%s: ar5416SetRfRegs failed\n", __func__);
- return HAL_EIO;
+ return -EIO;
}
- return HAL_OK;
+ return 0;
}
static inline void ath9k_hw_setup_calibration(struct ath_hal *ah,
static inline void
ath9k_hw_per_calibration(struct ath_hal *ah,
- struct hal_channel_internal *ichan,
- u_int8_t rxchainmask,
+ struct ath9k_channel *ichan,
+ u8 rxchainmask,
struct hal_cal_list *currCal,
bool *isCalDone)
{
int init_cal_count)
{
struct ath_hal_5416 *ahp = AH5416(ah);
- struct hal_channel_internal ichan;
+ struct ath9k_channel ichan;
bool isCalDone;
struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
const struct hal_percal_data *calData = currCal->calData;
static inline bool
ath9k_hw_channel_change(struct ath_hal *ah,
- struct hal_channel *chan,
- struct hal_channel_internal *ichan,
- enum hal_ht_macmode macmode)
+ struct ath9k_channel *chan,
+ enum ath9k_ht_macmode macmode)
{
- u_int32_t synthDelay, qnum;
+ u32 synthDelay, qnum;
struct ath_hal_5416 *ahp = AH5416(ah);
for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
ath9k_hw_set_regs(ah, chan, macmode);
if (AR_SREV_9280_10_OR_LATER(ah)) {
- if (!(ath9k_hw_ar9280_set_channel(ah, ichan))) {
+ if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
"%s: failed to set channel\n", __func__);
return false;
}
} else {
- if (!(ath9k_hw_set_channel(ah, ichan))) {
+ if (!(ath9k_hw_set_channel(ah, chan))) {
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
"%s: failed to set channel\n", __func__);
return false;
}
}
- if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, ichan,
+ if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
ath9k_regd_get_ctl(ah, chan),
ath9k_regd_get_antenna_allowed(ah, chan),
- ichan->maxRegTxPower * 2,
- min((u_int32_t) MAX_RATE_POWER,
- (u_int32_t) ah->ah_powerLimit))
- != HAL_OK) {
+ chan->maxRegTxPower * 2,
+ min((u32) MAX_RATE_POWER,
+ (u32) ah->ah_powerLimit)) != 0) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"%s: error init'ing transmit power\n", __func__);
return false;
REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
- ath9k_hw_set_delta_slope(ah, ichan);
+ ath9k_hw_set_delta_slope(ah, chan);
if (AR_SREV_9280_10_OR_LATER(ah))
- ath9k_hw_9280_spur_mitigate(ah, chan, ichan);
+ ath9k_hw_9280_spur_mitigate(ah, chan);
else
ath9k_hw_spur_mitigate(ah, chan);
- if (!ichan->oneTimeCalsDone)
- ichan->oneTimeCalsDone = true;
+ if (!chan->oneTimeCalsDone)
+ chan->oneTimeCalsDone = true;
return true;
}
static bool ath9k_hw_chip_reset(struct ath_hal *ah,
- struct hal_channel *chan)
+ struct ath9k_channel *chan)
{
struct ath_hal_5416 *ahp = AH5416(ah);
- if (!ath9k_hw_set_reset_reg(ah, HAL_RESET_WARM))
+ if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
return false;
- if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE))
+ if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
return false;
ahp->ah_chipFullSleep = false;
static inline void ath9k_hw_set_dma(struct ath_hal *ah)
{
- u_int32_t regval;
+ u32 regval;
regval = REG_READ(ah, AR_AHB_MODE);
REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
}
static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
- struct hal_channel *chan,
+ struct ath9k_channel *chan,
enum hal_cal_types calType)
{
struct ath_hal_5416 *ahp = AH5416(ah);
}
static inline bool ath9k_hw_init_cal(struct ath_hal *ah,
- struct hal_channel *chan)
+ struct ath9k_channel *chan)
{
struct ath_hal_5416 *ahp = AH5416(ah);
- struct hal_channel_internal *ichan =
+ &
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