There are only 2 options in the driver
for the function of mt7620 internal switch port 4:
EPHY mode (RJ-45, internal PHY)
GMAC mode (RGMII, external PHY)
Let the DTS property be boolean instead of string
where EPHY mode is the default.
Fix how the properties are written
for all DTS that use them,
and add missing nodes where applicable,
and remove useless nodes,
and minor DTS formatting.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit
953bfe2eb3b7236a72fa41ab2204fdaa9fd09f65)
status = "okay";
};
-&gsw {
- mediatek,port4 = "ephy";
-};
-
&ohci {
status = "okay";
};
status = "okay";
};
-&gsw {
- mediatek,port4 = "ephy";
-};
-
&i2c {
status = "okay";
};
status = "okay";
};
-&gsw {
- mediatek,port4 = "ephy";
-};
-
&ohci {
status = "okay";
};
};
};
-&gsw {
- mediatek,port4 = "ephy";
+ðernet {
pinctrl-names = "default";
pinctrl-0 = <&ephy_pins>;
};
};
};
-&gsw {
- mediatek,port4 = "ephy";
-};
-
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};
mediatek,portmap = "llllw";
};
-&gsw {
- mediatek,port4 = "ephy";
-};
-
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
pinctrl-names = "default";
mediatek,portmap = "llllw";
};
-&gsw {
- mediatek,port4 = "ephy";
-};
-
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};
mediatek,portmap = "llllw";
};
-&gsw {
- mediatek,port4 = "ephy";
-};
-
&gpio2 {
status = "okay";
};
mtd-mac-address = <&factory 0x4>;
};
-&gsw {
- ralink,port4 = "ephy";
-};
-
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
pinctrl-names = "default";
};
};
-&gsw {
- mediatek,port4 = "ephy";
-};
-
&state_default {
default {
groups = "i2c", "uartf";
};
&gsw {
- mediatek,port4 = "gmac";
+ mediatek,port4-gmac;
};
};
&gsw {
- mediatek,port4 = "gmac";
+ mediatek,port4-gmac;
mediatek,ephy-base-address = /bits/ 16 < 2 >;
};
};
&gsw {
- mediatek,port4 = "gmac";
+ mediatek,port4-gmac;
};
&pcie {
};
};
-&gsw {
- mediatek,port4 = "gmac";
-};
-
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};
};
};
-&gsw {
- mediatek,port4 = "gmac";
-};
-
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};
};
};
-&gsw {
- mediatek,port5 = "gmac";
-};
-
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};
0x7c 0x0000007e /* PORT0 STATUS */
0x0c 0x05600000 /* PORT6 PAD MODE CTRL */
0x94 0x0000007e /* PORT6 STATUS */
- >;
+ >;
};
};
};
};
&gsw {
- mediatek,port4 = "gmac";
+ mediatek,port4-gmac;
};
&wmac {
};
};
+&gsw {
+ mediatek,port4-gmac;
+};
+
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};
};
&gsw {
- mediatek,port4 = "gmac";
+ mediatek,port4-gmac;
};
};
};
-&gsw {
- mediatek,port4 = "gmac";
-};
-
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};
mediatek,portmap = "llllw";
};
-&gsw {
- mediatek,port4 = "ephy";
-};
-
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};
mediatek,portmap = "llllw";
};
-&gsw {
- ralink,port4 = "ephy";
-};
-
&sdhci {
status = "okay";
};
mediatek,portmap = "llllw";
};
-&gsw {
- mediatek,port4 = "ephy";
-};
-
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};
mediatek,portmap = "llllw";
};
-&gsw {
- mediatek,port4 = "ephy";
-};
-
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};
};
&gsw {
- mediatek,port4 = "gmac";
+ mediatek,port4-gmac;
};
&sdhci {
};
};
-&gsw {
- mediatek,port4 = "gmac";
-};
-
&pcie {
status = "okay";
};
mediatek,portmap = "llllw";
};
-&gsw {
- mediatek,port4 = "ephy";
-};
-
&sdhci {
status = "okay";
};
};
&gsw {
- mediatek,port4 = "gmac";
+ mediatek,port4-gmac;
};
&pcie {
};
&gsw {
- mediatek,port4 = "gmac";
+ mediatek,port4-gmac;
};
&ehci {
status = "okay";
};
-&gsw {
- mediatek,port4 = "ephy";
-};
-
&wmac {
ralink,mtd-eeprom = <&radio 0x0>;
};
status = "okay";
};
-&gsw {
- mediatek,port4 = "ephy";
-};
-
&wmac {
ralink,mtd-eeprom = <&radio 0x0>;
};
};
&gsw {
- mediatek,port4 = "gmac";
+ mediatek,port4-gmac;
};
ðernet {
};
&gsw {
- mediatek,port4 = "gmac";
+ mediatek,port4-gmac;
};
&wmac {
mediatek,portmap = "llllw";
};
-&gsw {
- ralink,port4 = "ephy";
-};
-
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};
&ohci {
status = "okay";
};
-
-&gsw {
- mediatek,port4 = "ephy";
-};
};
&gsw {
- mediatek,port4 = "gmac";
+ mediatek,port4-gmac;
};
&wmac {
interrupt-parent = <&intc>;
interrupts = <17>;
- mediatek,port4 = "ephy";
};
ehci: ehci@101c0000 {
struct fe_priv *priv = (struct fe_priv *)_priv;
struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
u32 status;
- int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
+ int i, max = (gsw->port4_ephy) ? (4) : (3);
status = mtk_switch_r32(gsw, GSW_REG_ISR);
if (status & PORT_IRQ_ST_CHG)
mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
/* setup port 4 */
- if (gsw->port4 == PORT4_EPHY) {
- u32 val = rt_sysc_r32(SYSC_REG_CFG1);
+ if (gsw->port4_ephy) {
+ val = rt_sysc_r32(SYSC_REG_CFG1);
val |= 3 << 14;
rt_sysc_w32(val, SYSC_REG_CFG1);
static int mt7620_gsw_probe(struct platform_device *pdev)
{
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- const char *port4 = NULL;
struct mt7620_gsw *gsw;
struct device_node *np = pdev->dev.of_node;
u16 val;
gsw->dev = &pdev->dev;
- of_property_read_string(np, "mediatek,port4", &port4);
- if (port4 && !strcmp(port4, "ephy"))
- gsw->port4 = PORT4_EPHY;
- else if (port4 && !strcmp(port4, "gmac"))
- gsw->port4 = PORT4_EXT;
- else
- gsw->port4 = PORT4_EPHY;
+ gsw->port4_ephy = !of_property_read_bool(np, "mediatek,port4-gmac");
if (of_property_read_u16(np, "mediatek,ephy-base-address", &val) == 0)
gsw->ephy_base = val;
GSW_ATTR_PORT_UNTAG,
};
-enum {
- PORT4_EPHY = 0,
- PORT4_EXT,
-};
-
struct mt7620_gsw {
struct device *dev;
void __iomem *base;
int irq;
- int port4;
+ bool port4_ephy;
unsigned long int autopoll;
u16 ephy_base;
};
u32 val, mask = 0;
u32 val_delay = 0;
u32 mask_delay = GSW_REG_GPCx_TXDELAY | GSW_REG_GPCx_RXDELAY;
- int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
+ int min = (gsw->port4_ephy) ? (5) : (4);
if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
if (_id)
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