ipq806x: drop ipq40xx support
authorJohn Crispin <john@phrozen.org>
Wed, 21 Feb 2018 15:17:10 +0000 (16:17 +0100)
committerMathias Kresin <dev@kresin.me>
Wed, 14 Mar 2018 18:04:50 +0000 (19:04 +0100)
Signed-off-by: John Crispin <john@phrozen.org>
48 files changed:
target/linux/ipq806x/base-files/etc/board.d/01_leds
target/linux/ipq806x/base-files/etc/board.d/02_network
target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
target/linux/ipq806x/base-files/lib/upgrade/openmesh.sh [deleted file]
target/linux/ipq806x/base-files/lib/upgrade/platform.sh
target/linux/ipq806x/config-4.9
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-a42.dts [deleted file]
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-bus.dtsi [deleted file]
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-fritz4040.dts [deleted file]
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-gl-b1300.dts [deleted file]
target/linux/ipq806x/image/Makefile
target/linux/ipq806x/patches-4.9/0015-cpufreq-dt-qcom-ipq4019-Add-compat-for-qcom-ipq4019.patch [deleted file]
target/linux/ipq806x/patches-4.9/0016-clk-ipq4019-report-accurate-fixed-clock-rates.patch [deleted file]
target/linux/ipq806x/patches-4.9/0017-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch [deleted file]
target/linux/ipq806x/patches-4.9/0018-qcom-ipq4019-turn-on-DMA-for-i2c.patch [deleted file]
target/linux/ipq806x/patches-4.9/0019-qcom-ipq4019-use-correct-clock-for-i2c-bus-0.patch [deleted file]
target/linux/ipq806x/patches-4.9/0020-qcom-ipq4019-enable-DMA-for-spi.patch [deleted file]
target/linux/ipq806x/patches-4.9/0026-dts-ipq4019-Add-support-for-IPQ4019-DK04-board.patch [deleted file]
target/linux/ipq806x/patches-4.9/0069-arm-boot-add-dts-files.patch
target/linux/ipq806x/patches-4.9/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch [deleted file]
target/linux/ipq806x/patches-4.9/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch [deleted file]
target/linux/ipq806x/patches-4.9/307-ARM-qcom-Add-IPQ4019-SoC-support.patch [deleted file]
target/linux/ipq806x/patches-4.9/308-dts-ipq4019-add-both-IPQ4019-wifi-block-definitions.patch [deleted file]
target/linux/ipq806x/patches-4.9/309-dts-ipq4019-add-pseudo-random-number-generator.patch [deleted file]
target/linux/ipq806x/patches-4.9/605-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch [deleted file]
target/linux/ipq806x/patches-4.9/700-net-add-qualcomm-mdio-and-phy.patch [deleted file]
target/linux/ipq806x/patches-4.9/701-dts-ipq4019-add-mdio-node.patch [deleted file]
target/linux/ipq806x/patches-4.9/702-dts-ipq4019-add-PHY-switch-nodes.patch [deleted file]
target/linux/ipq806x/patches-4.9/710-net-add-qualcomm-essedma-ethernet-driver.patch [deleted file]
target/linux/ipq806x/patches-4.9/711-dts-ipq4019-add-ethernet-essedma-node.patch [deleted file]
target/linux/ipq806x/patches-4.9/820-qcom-ipq4019-Add-IPQ4019-USB-HS-SS-PHY-drivers.patch [deleted file]
target/linux/ipq806x/patches-4.9/830-usb-dwc3-register-qca-ipq4019-dwc3-in-dwc3-of-simple.patch [deleted file]
target/linux/ipq806x/patches-4.9/852-ipq4019-pinctrl-Updated-various-Pin-definitions.patch [deleted file]
target/linux/ipq806x/patches-4.9/859-msm-pinctrl-Add-support-to-configure-ipq40xx-GPIO_PU.patch [deleted file]
target/linux/ipq806x/patches-4.9/860-qcom-mtd-nand-Add-bam_dma-support-in-qcom_nand-drive.patch [deleted file]
target/linux/ipq806x/patches-4.9/861-qcom-mtd-nand-Added-bam-transaction-and-support-addi.patch [deleted file]
target/linux/ipq806x/patches-4.9/862-dmaengine-qcom-bam_dma-Add-custom-data-mapping.patch [deleted file]
target/linux/ipq806x/patches-4.9/863-dts-ipq4019-add-nand-and-qpic-bam-dma-node.patch [deleted file]
target/linux/ipq806x/patches-4.9/864-00-v3-1-2-dts-ipq4019-Fix-pinctrl-node-name.patch [deleted file]
target/linux/ipq806x/patches-4.9/864-00-v3-2-2-dts-ipq4019-Move-xo-and-timer-nodes-to-SoC-dtsi.patch [deleted file]
target/linux/ipq806x/patches-4.9/864-01-dts-ipq4019-ap-dk04-fix-pinctrl-node-name.patch [deleted file]
target/linux/ipq806x/patches-4.9/864-02-dts-ipq4019-ap-dk04-remove-xo-and-timer-nodes.patch [deleted file]
target/linux/ipq806x/patches-4.9/864-03-dts-ipq4019-ap-dk01-add-tcsr-config-to-dtsi.patch [deleted file]
target/linux/ipq806x/patches-4.9/864-04-dts-ipq4019-ap-dk01-add-network-nodes-to-dtsi.patch [deleted file]
target/linux/ipq806x/patches-4.9/864-05-dts-ipq4019-ap-dk01-remove-spi-chip-node-from-dtsi.patch [deleted file]
target/linux/ipq806x/patches-4.9/864-06-dts-ipq4019-fix-max-cpu-speed.patch [deleted file]
target/linux/ipq806x/patches-4.9/864-07-dts-ipq4019-ap-dk01.1-c1-add-spi-and-ram-nodes.patch [deleted file]
target/linux/ipq806x/patches-4.9/864-08-dts-ipq4019-ap-dk01.1-c1-add-compatible-string.patch [deleted file]

index ea8b781..98aac70 100755 (executable)
@@ -11,14 +11,6 @@ board=$(board_name)
 boardname="${board##*,}"
 
 case "$board" in
-avm,fritzbox-4040)
-       ucidef_set_led_wlan "wlan" "WLAN" "fritz4040:green:wlan" "phy0tpt" "phy1tpt"
-       ucidef_set_led_netdev "wan" "WAN" "fritz4040:green:wan" "eth1"
-       ucidef_set_led_switch "lan" "LAN" "fritz4040:green:lan" "switch0" "0x1e"
-       ;;
-glinet,gl-b1300)
-       ucidef_set_led_wlan "wlan" "WLAN" "${boardname}:green:wlan" "phy0tpt"
-       ;;
 netgear,d7800 |\
 netgear,r7500 |\
 netgear,r7500v2 |\
index 74223e5..e279cdd 100755 (executable)
@@ -12,11 +12,6 @@ board_config_update
 board=$(board_name)
 
 case "$board" in
-avm,fritzbox-4040)
-       ucidef_set_interfaces_lan_wan "eth0" "eth1"
-       ucidef_add_switch "switch0" \
-               "0u@eth0" "1:lan" "2:lan" "3:lan" "4:lan"
-       ;;
 linksys,ea8500)
        hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)
        ucidef_add_switch "switch0" \
@@ -33,10 +28,6 @@ tplink,vr2600v)
        ucidef_add_switch "switch0" \
                "1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0"
        ;;
-glinet,gl-b1300 |\
-openmesh,a42)
-       ucidef_set_interfaces_lan_wan "eth1" "eth0"
-       ;;
 qcom,ipq8064-db149)
        ucidef_set_interface_lan "eth1 eth2 eth3"
        ucidef_add_switch "switch0" \
index fa8eb11..ed99bd5 100644 (file)
@@ -45,35 +45,6 @@ board=$(board_name)
 
 
 case "$FIRMWARE" in
-"ath10k/pre-cal-ahb-a000000.wifi.bin")
-       case "$board" in
-       avm,fritzbox-4040)
-               /usr/bin/fritz_cal_extract -i 1 -s 0x400 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader_config")
-               ;;
-       openmesh,a42)
-               ath10kcal_extract "0:ART" 4096 12064
-               ;;
-       glinet,gl-b1300 |\
-       qcom,ap-dk01.1-c1)
-               ath10kcal_extract "ART" 4096 12064
-               ;;
-       esac
-       ;;
-"ath10k/pre-cal-ahb-a800000.wifi.bin")
-       case "$board" in
-       avm,fritzbox-4040)
-               /usr/bin/fritz_cal_extract -i 1 -s 0x400 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader_config")
-               ;;
-       openmesh,a42)
-               ath10kcal_extract "0:ART" 20480 12064
-               ;;
-       glinet,gl-b1300 |\
-       qcom,ap-dk01.1-c1)
-               ath10kcal_extract "ART" 20480 12064
-               ;;
-       esac
-       ;;
-
 "ath10k/pre-cal-pci-0000:01:00.0.bin")
        case $board in
        linksys,ea8500)
diff --git a/target/linux/ipq806x/base-files/lib/upgrade/openmesh.sh b/target/linux/ipq806x/base-files/lib/upgrade/openmesh.sh
deleted file mode 100644 (file)
index a2c79d9..0000000
+++ /dev/null
@@ -1,110 +0,0 @@
-# The U-Boot loader of the OpenMesh devices requires image sizes and
-# checksums to be provided in the U-Boot environment.
-# The OpenMesh devices come with 2 main partitions - while one is active
-# sysupgrade will flash the other. The boot order is changed to boot the
-# newly flashed partition. If the new partition can't be booted due to
-# upgrade failures the previously used partition is loaded.
-
-platform_do_upgrade_openmesh() {
-       local tar_file="$1"
-       local restore_backup
-       local primary_kernel_mtd
-
-       local setenv_script="/tmp/fw_env_upgrade"
-
-       local kernel_mtd="$(find_mtd_index $PART_NAME)"
-       local kernel_offset="$(cat /sys/class/mtd/mtd${kernel_mtd}/offset)"
-       local total_size="$(cat /sys/class/mtd/mtd${kernel_mtd}/size)"
-
-       # detect to which flash region the new image is written to.
-       #
-       # 1. check what is the mtd index for the first flash region on this
-       #    device
-       # 2. check if the target partition ("inactive") has the mtd index of
-       #    the first flash region
-       #
-       #    - when it is: the new bootseq will be 1,2 and the first region is
-       #      modified
-       #    - when it isnt: bootseq will be 2,1 and the second region is
-       #      modified
-       #
-       # The detection has to be done via the hardcoded mtd partition because
-       # the current boot might be done with the fallback region. Let us
-       # assume that the current bootseq is 1,2. The bootloader detected that
-       # the image in flash region 1 is corrupt and thus switches to flash
-       # region 2. The bootseq in the u-boot-env is now still the same and
-       # the sysupgrade code can now only rely on the actual mtd indexes and
-       # not the bootseq variable to detect the currently booted flash
-       # region/image.
-       #
-       # In the above example, an implementation which uses bootseq ("1,2") to
-       # detect the currently booted image would assume that region 1 is booted
-       # and then overwrite the variables for the wrong flash region (aka the
-       # one which isn't modified). This could result in a device which doesn't
-       # boot anymore to Linux until it was reflashed with ap51-flash.
-       local next_boot_part="1"
-       case "$(board_name)" in
-       openmesh,a42)
-               primary_kernel_mtd=8
-               ;;
-       *)
-               echo "failed to detect primary kernel mtd partition for board"
-               return 1
-               ;;
-       esac
-       [ "$kernel_mtd" = "$primary_kernel_mtd" ] || next_boot_part="2"
-
-       local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
-       board_dir=${board_dir%/}
-
-       local kernel_length=$(tar xf $tar_file ${board_dir}/kernel -O | wc -c)
-       local rootfs_length=$(tar xf $tar_file ${board_dir}/root -O | wc -c)
-       # rootfs without EOF marker
-       rootfs_length=$((rootfs_length-4))
-
-       local kernel_md5=$(tar xf $tar_file ${board_dir}/kernel -O | md5sum); kernel_md5="${kernel_md5%% *}"
-       # md5 checksum of rootfs with EOF marker
-       local rootfs_md5=$(tar xf $tar_file ${board_dir}/root -O | dd bs=1 count=$rootfs_length | md5sum); rootfs_md5="${rootfs_md5%% *}"
-
-       #
-       # add tar support to get_image() to use default_do_upgrade() instead?
-       #
-
-       # take care of restoring a saved config
-       [ "$SAVE_CONFIG" -eq 1 ] && restore_backup="${MTD_CONFIG_ARGS} -j ${CONF_TAR}"
-
-       # write concatinated kernel + rootfs to flash
-       tar xf $tar_file ${board_dir}/kernel ${board_dir}/root -O | \
-               mtd $restore_backup write - $PART_NAME
-
-       # prepare new u-boot env
-       if [ "$next_boot_part" = "1" ]; then
-               echo "bootseq 1,2" > $setenv_script
-       else
-               echo "bootseq 2,1" > $setenv_script
-       fi
-
-       printf "kernel_size_%i 0x%08x\n" $next_boot_part $kernel_length >> $setenv_script
-       printf "vmlinux_start_addr 0x%08x\n" ${kernel_offset} >> $setenv_script
-       printf "vmlinux_size 0x%08x\n" ${kernel_length} >> $setenv_script
-       printf "vmlinux_checksum %s\n" ${kernel_md5} >> $setenv_script
-
-       printf "rootfs_size_%i 0x%08x\n" $next_boot_part $((total_size-kernel_length)) >> $setenv_script
-       printf "rootfs_start_addr 0x%08x\n" $((kernel_offset+kernel_length)) >> $setenv_script
-       printf "rootfs_size 0x%08x\n" ${rootfs_length} >> $setenv_script
-       printf "rootfs_checksum %s\n" ${rootfs_md5} >> $setenv_script
-
-       # store u-boot env changes
-       fw_setenv -s $setenv_script || {
-               echo "failed to update U-Boot environment"
-               return 1
-       }
-}
-
-# create /var/lock for the lock "fw_setenv.lock" of fw_setenv
-# the rest is copied using ipq806x's RAMFS_COPY_BIN and RAMFS_COPY_DATA
-platform_add_ramfs_ubootenv()
-{
-        mkdir -p $RAM_ROOT/var/lock
-}
-append sysupgrade_pre_upgrade platform_add_ramfs_ubootenv
index 5561dd5..c0deeda 100644 (file)
@@ -17,15 +17,10 @@ platform_do_upgrade() {
        netgear,r7500 |\
        netgear,r7500v2 |\
        netgear,r7800 |\
-       qcom,ap-dk04.1-c1 |\
        qcom,ipq8064-ap148 |\
        zyxel,nbg6817)
                nand_do_upgrade "$ARGV"
                ;;
-       openmesh,a42)
-               PART_NAME="inactive"
-               platform_do_upgrade_openmesh "$ARGV"
-               ;;
        tplink,c2600)
                PART_NAME="os-image:rootfs"
                MTD_CONFIG_ARGS="-s 0x200000"
index a71b1b8..6bc3daf 100644 (file)
@@ -2,7 +2,6 @@ CONFIG_ALIGNMENT_TRAP=y
 # CONFIG_AMBA_PL08X is not set
 CONFIG_APQ_GCC_8084=y
 CONFIG_APQ_MMCC_8084=y
-CONFIG_AR40XX_PHY=y
 CONFIG_AR8216_PHY=y
 CONFIG_ARCH_CLOCKSOURCE_DATA=y
 CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
@@ -11,7 +10,6 @@ CONFIG_ARCH_HAS_SG_CHAIN=y
 CONFIG_ARCH_HAS_TICK_BROADCAST=y
 CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_IPQ40XX=y
 # CONFIG_ARCH_MDM9615 is not set
 CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
 CONFIG_ARCH_MSM8960=y
@@ -60,7 +58,6 @@ CONFIG_ARM_THUMB=y
 # CONFIG_ARM_THUMBEE is not set
 CONFIG_ARM_UNWIND=y
 CONFIG_ARM_VIRT_EXT=y
-CONFIG_AT803X_PHY=y
 # CONFIG_BINFMT_FLAT is not set
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_MQ_PCI=y
@@ -164,7 +161,6 @@ CONFIG_DYNAMIC_DEBUG=y
 CONFIG_EARLY_PRINTK=y
 CONFIG_EDAC_ATOMIC_SCRUB=y
 CONFIG_EDAC_SUPPORT=y
-CONFIG_ESSEDMA=y
 CONFIG_ETHERNET_PACKET_MANGLE=y
 CONFIG_FIXED_PHY=y
 CONFIG_FIX_EARLYCON_MEM=y
@@ -190,8 +186,6 @@ CONFIG_GENERIC_TIME_VSYSCALL=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIOLIB_IRQCHIP=y
 CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WATCHDOG=y
-# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
 CONFIG_HANDLE_DOMAIN_IRQ=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_HAS_DMA=y
@@ -257,7 +251,7 @@ CONFIG_IOMMU_HELPER=y
 # CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
 # CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
 CONFIG_IOMMU_SUPPORT=y
-CONFIG_IPQ_GCC_4019=y
+# CONFIG_IPQ_GCC_4019 is not set
 CONFIG_IPQ_GCC_806X=y
 # CONFIG_IPQ_LCC_806X is not set
 CONFIG_IRQCHIP=y
@@ -277,7 +271,6 @@ CONFIG_LZO_DECOMPRESS=y
 CONFIG_MDIO_BITBANG=y
 CONFIG_MDIO_BOARDINFO=y
 CONFIG_MDIO_GPIO=y
-CONFIG_MDIO_IPQ40XX=y
 # CONFIG_MDM_GCC_9615 is not set
 # CONFIG_MDM_LCC_9615 is not set
 # CONFIG_MFD_MAX77620 is not set
@@ -378,7 +371,7 @@ CONFIG_PHY_QCOM_IPQ806X_SATA=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_APQ8064=y
 # CONFIG_PINCTRL_APQ8084 is not set
-CONFIG_PINCTRL_IPQ4019=y
+# CONFIG_PINCTRL_IPQ4019 is not set
 CONFIG_PINCTRL_IPQ8064=y
 # CONFIG_PINCTRL_MDM9615 is not set
 CONFIG_PINCTRL_MSM=y
@@ -444,7 +437,6 @@ CONFIG_RWSEM_XCHGADD_ALGORITHM=y
 # CONFIG_SCHED_INFO is not set
 # CONFIG_SCSI_DMA is not set
 CONFIG_SERIAL_8250_FSL=y
-# CONFIG_SERIAL_AMBA_PL010 is not set
 # CONFIG_SERIAL_AMBA_PL011 is not set
 CONFIG_SERIAL_MSM=y
 CONFIG_SERIAL_MSM_CONSOLE=y
@@ -483,7 +475,6 @@ CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
 CONFIG_USB=y
 CONFIG_USB_COMMON=y
 # CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_IPQ4019_PHY=y
 CONFIG_USB_SUPPORT=y
 # CONFIG_USB_UHCI_HCD is not set
 CONFIG_USE_OF=y
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-a42.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-a42.dts
deleted file mode 100644 (file)
index 887be99..0000000
+++ /dev/null
@@ -1,244 +0,0 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2017, Sven Eckelmann <sven.eckelmann@openmesh.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include "qcom-ipq4019-bus.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-       model = "OpenMesh A42";
-       compatible = "openmesh,a42", "qcom,ipq4019";
-
-       reserved-memory {
-               #address-cells = <0x1>;
-               #size-cells = <0x1>;
-               ranges;
-
-               rsvd1@87000000 {
-                       reg = <0x87000000 0x500000>;
-                       no-map;
-               };
-
-               wifi_dump@87500000 {
-                       reg = <0x87500000 0x600000>;
-                       no-map;
-               };
-
-               rsvd2@87B00000 {
-                       reg = <0x87b00000 0x500000>;
-                       no-map;
-               };
-       };
-
-       soc {
-               tcsr@194b000 {
-                       /* select hostmode */
-                       compatible = "qcom,tcsr";
-                       reg = <0x194b000 0x100>;
-                       qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-                       status = "ok";
-               };
-
-               ess_tcsr@1953000 {
-                       compatible = "qcom,tcsr";
-                       reg = <0x1953000 0x1000>;
-                       qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-               };
-
-               tcsr@1949000 {
-                       compatible = "qcom,tcsr";
-                       reg = <0x1949000 0x100>;
-                       qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-               };
-
-               tcsr@1957000 {
-                       compatible = "qcom,tcsr";
-                       reg = <0x1957000 0x100>;
-                       qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-               };
-
-               pinctrl@1000000 {
-                       serial_pins: serial_pinmux {
-                               mux {
-                                       pins = "gpio60", "gpio61";
-                                       function = "blsp_uart0";
-                                       bias-disable;
-                               };
-                       };
-
-                       spi_0_pins: spi_0_pinmux {
-                               pinmux {
-                                       function = "blsp_spi0";
-                                       pins = "gpio55", "gpio56", "gpio57";
-                               };
-                               pinmux_cs {
-                                       function = "gpio";
-                                       pins = "gpio54";
-                               };
-                               pinconf {
-                                       pins = "gpio55", "gpio56", "gpio57";
-                                       drive-strength = <12>;
-                                       bias-disable;
-                               };
-                               pinconf_cs {
-                                       pins = "gpio54";
-                                       drive-strength = <2>;
-                                       bias-disable;
-                                       output-high;
-                               };
-                       };
-               };
-
-               blsp_dma: dma@7884000 {
-                       status = "ok";
-               };
-
-               spi_0: spi@78b5000 {
-                       pinctrl-0 = <&spi_0_pins>;
-                       pinctrl-names = "default";
-                       status = "ok";
-                       cs-gpios = <&tlmm 54 0>;
-
-                       m25p80@0 {
-                               #address-cells = <1>;
-                               #size-cells = <1>;
-                               compatible = "jedec,spi-nor";
-                               reg = <0>;
-                               spi-max-frequency = <24000000>;
-
-                               /* partitions are passed via bootloader */
-                       };
-               };
-
-               serial@78af000 {
-                       pinctrl-0 = <&serial_pins>;
-                       pinctrl-names = "default";
-                       status = "ok";
-               };
-
-               cryptobam: dma@8e04000 {
-                       status = "ok";
-               };
-
-               crypto@8e3a000 {
-                       status = "ok";
-               };
-
-               watchdog@b017000 {
-                       status = "ok";
-               };
-
-               usb2_hs_phy: hsphy@a8000 {
-                       status = "ok";
-               };
-
-               usb2: usb2@60f8800 {
-                       status = "ok";
-               };
-
-               mdio@90000 {
-                       status = "okay";
-               };
-
-               ess-switch@c000000 {
-                       status = "okay";
-               };
-
-               ess-psgmii@98000 {
-                       status = "okay";
-               };
-
-               edma@c080000 {
-                       status = "okay";
-               };
-
-               wifi@a000000 {
-                       status = "okay";
-                       qcom,ath10k-calibration-variant = "OM-A42";
-               };
-
-               wifi@a800000 {
-                       status = "okay";
-                       qcom,ath10k-calibration-variant = "OM-A42";
-               };
-       };
-
-       gpio-keys {
-               compatible = "gpio-keys";
-
-               reset {
-                       label = "reset";
-                       gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
-                       linux,code = <KEY_RESTART>;
-               };
-       };
-
-       aliases {
-               led-boot = &power;
-               led-failsafe = &power;
-               led-running = &power;
-               led-upgrade = &power;
-       };
-
-       gpio-leds {
-               compatible = "gpio-leds";
-
-               red {
-                       label = "a42:red:status";
-                       gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-                       linux,default-trigger = "default-off";
-               };
-
-               power: green {
-                       label = "a42:green:status";
-                       gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-               };
-
-               blue {
-                       label = "a42:blue:status";
-                       gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-                       linux,default-trigger = "default-off";
-               };
-       };
-
-       watchdog {
-               compatible = "linux,wdt-gpio";
-               gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-               hw_algo = "toggle";
-               /* hw_margin_ms is actually 300s but driver limits it to 60s */
-               hw_margin_ms = <60000>;
-               always-running;
-       };
-};
-
-&gmac0 {
-       qcom,phy_mdio_addr = <4>;
-       qcom,poll_required = <1>;
-       qcom,forced_speed = <1000>;
-       qcom,forced_duplex = <1>;
-       vlan_tag = <2 0x20>;
-};
-
-&gmac1 {
-       qcom,phy_mdio_addr = <3>;
-       qcom,poll_required = <1>;
-       qcom,forced_speed = <1000>;
-       qcom,forced_duplex = <1>;
-       vlan_tag = <1 0x10>;
-};
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-bus.dtsi b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-bus.dtsi
deleted file mode 100644 (file)
index 1695059..0000000
+++ /dev/null
@@ -1,1142 +0,0 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include <dt-bindings/msm/msm-bus-ids.h>
-
-/ {
-
-soc {
-       ad_hoc_bus: ad-hoc-bus {
-               compatible = "qcom,msm-bus-device";
-               reg = <0x580000 0x14000>,
-                       <0x500000 0x11000>;
-               reg-names = "snoc-base", "pcnoc-base";
-
-               /*Buses*/
-
-               fab_pcnoc: fab-pcnoc {
-                       cell-id = <MSM_BUS_FAB_PERIPH_NOC>;
-                       label = "fab-pcnoc";
-                       qcom,fab-dev;
-                       qcom,base-name = "pcnoc-base";
-                       qcom,bypass-qos-prg;
-                       qcom,bus-type = <1>;
-                       qcom,qos-off = <0x1000>;
-                       qcom,base-offset = <0x0>;
-                       clocks = <>;
-               };
-
-               fab_snoc: fab-snoc {
-                       cell-id = <MSM_BUS_FAB_SYS_NOC>;
-                       label = "fab-snoc";
-                       qcom,fab-dev;
-                       qcom,base-name = "snoc-base";
-                       qcom,bypass-qos-prg;
-                       qcom,bus-type = <1>;
-                       qcom,qos-off = <0x80>;
-                       qcom,base-offset = <0x0>;
-                       clocks = <>;
-               };
-
-               /*Masters*/
-
-               mas_blsp_bam: mas-blsp-bam {
-                       cell-id = <MSM_BUS_MASTER_BLSP_BAM>;
-                       label = "mas-blsp-bam";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = <&pcnoc_m_0>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_BLSP_BAM>;
-                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-                                &slv_srif &slv_prng &slv_qdss_cfg
-                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-                                &slv_boot_rom &slv_security &slv_spdm
-                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-                                &slv_sdcc_cfg &slv_snoc_cfg>;
-               };
-
-               mas_usb2_bam: mas-usb2-bam {
-                       cell-id = <MSM_BUS_MASTER_USB2_BAM>;
-                       label = "mas-usb2-bam";
-                       qcom,buswidth = <8>;
-                       qcom,ap-owned;
-                       qcom,qport = <15>;
-                       qcom,qos-mode = "fixed";
-                       qcom,connections = <&slv_pcnoc_snoc>;
-                       qcom,prio1 = <1>;
-                       qcom,prio0 = <1>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_USB2_BAM>;
-                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-                                &slv_srif &slv_prng &slv_qdss_cfg
-                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-                                &slv_boot_rom &slv_security &slv_spdm
-                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-                                &slv_sdcc_cfg &slv_snoc_cfg>;
-               };
-
-               mas_adss_dma0: mas-adss-dma0 {
-                       cell-id = <MSM_BUS_MASTER_ADDS_DMA0>;
-                       label = "mas-adss-dma0";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = <&pcnoc_m_1>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_ADSS_DMA0>;
-                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-                                &slv_srif &slv_prng &slv_qdss_cfg
-                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-                                &slv_boot_rom &slv_security &slv_spdm
-                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-                                &slv_sdcc_cfg &slv_snoc_cfg>;
-               };
-
-               mas_adss_dma1: mas-adss-dma1 {
-                       cell-id = <MSM_BUS_MASTER_ADDS_DMA1>;
-                       label = "mas-adss-dma1";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = <&pcnoc_m_1>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_ADSS_DMA1>;
-                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-                                &slv_srif &slv_prng &slv_qdss_cfg
-                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-                                &slv_boot_rom &slv_security &slv_spdm
-                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-                                &slv_sdcc_cfg &slv_snoc_cfg>;
-               };
-
-               mas_adss_dma2: mas-adss-dma2 {
-                       cell-id = <MSM_BUS_MASTER_ADDS_DMA2>;
-                       label = "mas-adss-dma2";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = <&pcnoc_m_1>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_ADSS_DMA2>;
-                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-                                &slv_srif &slv_prng &slv_qdss_cfg
-                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-                                &slv_boot_rom &slv_security &slv_spdm
-                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-                                &slv_sdcc_cfg &slv_snoc_cfg>;
-               };
-
-               mas_adss_dma3: mas-adss-dma3 {
-                       cell-id = <MSM_BUS_MASTER_ADDS_DMA3>;
-                       label = "mas-adss-dma3";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = <&pcnoc_m_1>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_ADSS_DMA3>;
-                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-                                &slv_srif &slv_prng &slv_qdss_cfg
-                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-                                &slv_boot_rom &slv_security &slv_spdm
-                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-                                &slv_sdcc_cfg &slv_snoc_cfg>;
-               };
-
-               mas_qpic_bam: mas-qpic-bam {
-                       cell-id = <MSM_BUS_MASTER_QPIC_BAM>;
-                       label = "mas-qpic-bam";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = <&pcnoc_m_0>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_QPIC_BAM>;
-                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-                                &slv_srif &slv_prng &slv_qdss_cfg
-                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-                                &slv_boot_rom &slv_security &slv_spdm
-                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-                                &slv_sdcc_cfg &slv_snoc_cfg>;
-               };
-
-               mas_spdm: mas-spdm {
-                       cell-id = <MSM_BUS_MASTER_SPDM>;
-                       label = "mas-spdm";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = <&pcnoc_m_0>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_SPDM>;
-                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-                                &slv_srif &slv_prng &slv_qdss_cfg
-                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-                                &slv_boot_rom &slv_security &slv_spdm
-                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-                                &slv_sdcc_cfg &slv_snoc_cfg>;
-               };
-
-               mas_pcnoc_cfg: mas-pcnoc-cfg {
-                       cell-id = <MSM_BUS_MASTER_PNOC_CFG>;
-                       label = "mas-pcnoc-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = <&slv_srvc_pcnoc>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_CFG>;
-               };
-
-               mas_tic: mas-tic {
-                       cell-id = <MSM_BUS_MASTER_TIC>;
-                       label = "mas-tic";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = <&pcnoc_int_0 &slv_pcnoc_snoc>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_TIC>;
-               };
-
-               mas_sdcc_bam: mas-sdcc-bam {
-                       cell-id = <MSM_BUS_MASTER_SDCC_BAM>;
-                       label = "mas-sdcc-bam";
-                       qcom,buswidth = <8>;
-                       qcom,ap-owned;
-                       qcom,qport = <14>;
-                       qcom,qos-mode = "fixed";
-                       qcom,connections = <&slv_pcnoc_snoc>;
-                       qcom,prio1 = <0>;
-                       qcom,prio0 = <0>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_SDCC_BAM>;
-                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-                                &slv_srif &slv_prng &slv_qdss_cfg
-                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-                                &slv_boot_rom &slv_security &slv_spdm
-                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-                                &slv_sdcc_cfg &slv_snoc_cfg>;
-               };
-
-               mas_snoc_pcnoc: mas-snoc-pcnoc {
-                       cell-id = <MSM_BUS_SNOC_PNOC_MAS>;
-                       label = "mas-snoc-pcnoc";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,qport = <16>;
-                       qcom,qos-mode = "fixed";
-                       qcom,connections = <&pcnoc_int_0>;
-                       qcom,prio1 = <0>;
-                       qcom,prio0 = <0>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_SNOC_PCNOC>;
-               };
-
-               mas_qdss_dap: mas-qdss-dap {
-                       cell-id = <MSM_BUS_MASTER_QDSS_DAP>;
-                       label = "mas-qdss-dap";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = <&pcnoc_int_0 &slv_pcnoc_snoc>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_QDSS_DAP>;
-               };
-
-               mas_ddrc_snoc: mas-ddrc-snoc {
-                       cell-id = <MSM_BUS_MASTER_DDRC_SNOC>;
-                       label = "mas-ddrc-snoc";
-                       qcom,buswidth = <16>;
-                       qcom,ap-owned;
-                       qcom,connections = <&snoc_int_0 &snoc_int_1
-                                &slv_pcie>;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_DDRC_SNOC>;
-                       qcom,blacklist = <&slv_snoc_ddrc_m1 &slv_srvc_snoc>;
-               };
-
-               mas_wss_0: mas-wss-0 {
-                       cell-id = <MSM_BUS_MASTER_WSS_0>;
-                       label = "mas-wss-0";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,qport = <26>;
-                       qcom,qos-mode = "fixed";
-                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
-                       qcom,prio1 = <0>;
-                       qcom,prio0 = <0>;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_WSS_0>;
-                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_pcie
-                                &slv_wss1_cfg &slv_wss0_cfg &slv_crypto_cfg
-                                &slv_srvc_snoc>;
-               };
-
-               mas_wss_1: mas-wss-1 {
-                       cell-id = <MSM_BUS_MASTER_WSS_1>;
-                       label = "mas-wss-1";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,qport = <27>;
-                       qcom,qos-mode = "fixed";
-                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
-                       qcom,prio1 = <0>;
-                       qcom,prio0 = <0>;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_WSS_1>;
-                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_pcie
-                                &slv_wss1_cfg &slv_wss0_cfg &slv_crypto_cfg
-                                &slv_srvc_snoc>;
-               };
-
-               mas_crypto: mas-crypto {
-                       cell-id = <MSM_BUS_MASTER_CRYPTO>;
-                       label = "mas-crypto";
-                       qcom,buswidth = <8>;
-                       qcom,ap-owned;
-                       qcom,qport = <5>;
-                       qcom,qos-mode = "fixed";
-                       qcom,connections = <&snoc_int_0 &snoc_int_1
-                                &slv_snoc_ddrc_m1>;
-                       qcom,prio1 = <0>;
-                       qcom,prio0 = <0>;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO>;
-                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
-                                &slv_pcie &slv_qdss_stm &slv_crypto_cfg
-                                &slv_srvc_snoc>;
-               };
-
-               mas_ess: mas-ess {
-                       cell-id = <MSM_BUS_MASTER_ESS>;
-                       label = "mas-ess";
-                       qcom,buswidth = <8>;
-                       qcom,ap-owned;
-                       qcom,qport = <44>;
-                       qcom,qos-mode = "fixed";
-                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
-                       qcom,prio1 = <0>;
-                       qcom,prio0 = <0>;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_ESS>;
-                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
-                                &slv_pcie &slv_qdss_stm &slv_wss1_cfg
-                                &slv_wss0_cfg &slv_crypto_cfg &slv_srvc_snoc>;
-               };
-
-               mas_pcie: mas-pcie {
-                       cell-id = <MSM_BUS_MASTER_PCIE>;
-                       label = "mas-pcie";
-                       qcom,buswidth = <8>;
-                       qcom,ap-owned;
-                       qcom,qport = <6>;
-                       qcom,qos-mode = "fixed";
-                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
-                       qcom,prio1 = <0>;
-                       qcom,prio0 = <0>;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_PCIE>;
-                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_pcie
-                                &slv_qdss_stm &slv_wss1_cfg &slv_wss0_cfg
-                                &slv_crypto_cfg &slv_srvc_snoc>;
-               };
-
-               mas_usb3: mas-usb3 {
-                       cell-id = <MSM_BUS_MASTER_USB3>;
-                       label = "mas-usb3";
-                       qcom,buswidth = <8>;
-                       qcom,ap-owned;
-                       qcom,qport = <7>;
-                       qcom,qos-mode = "fixed";
-                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
-                       qcom,prio1 = <0>;
-                       qcom,prio0 = <0>;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_USB3>;
-                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
-                                &slv_pcie &slv_qdss_stm &slv_wss1_cfg
-                                &slv_wss0_cfg &slv_crypto_cfg &slv_srvc_snoc>;
-               };
-
-               mas_qdss_etr: mas-qdss-etr {
-                       cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
-                       label = "mas-qdss-etr";
-                       qcom,buswidth = <8>;
-                       qcom,ap-owned;
-                       qcom,qport = <544>;
-                       qcom,qos-mode = "fixed";
-                       qcom,connections = <&qdss_int>;
-                       qcom,prio1 = <0>;
-                       qcom,prio0 = <0>;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>;
-                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
-                                &slv_pcie &slv_qdss_stm &slv_wss1_cfg
-                                &slv_wss0_cfg &slv_crypto_cfg &slv_srvc_snoc>;
-               };
-
-               mas_qdss_bamndp: mas-qdss-bamndp {
-                       cell-id = <MSM_BUS_MASTER_QDSS_BAMNDP>;
-                       label = "mas-qdss-bamndp";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,qport = <576>;
-                       qcom,qos-mode = "fixed";
-                       qcom,connections = <&qdss_int>;
-                       qcom,prio1 = <0>;
-                       qcom,prio0 = <0>;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAMNDP>;
-                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
-                                &slv_pcie &slv_qdss_stm &slv_wss1_cfg
-                                &slv_wss0_cfg &slv_crypto_cfg &slv_srvc_snoc>;
-               };
-
-               mas_pcnoc_snoc: mas-pcnoc-snoc {
-                       cell-id = <MSM_BUS_PNOC_SNOC_MAS>;
-                       label = "mas-pcnoc-snoc";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,qport = <384>;
-                       qcom,qos-mode = "fixed";
-                       qcom,connections = <&snoc_int_0 &snoc_int_1
-                                &slv_snoc_ddrc_m1>;
-                       qcom,prio1 = <0>;
-                       qcom,prio0 = <0>;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_PNOC_SNOC>;
-                       qcom,blacklist = <&slv_srvc_snoc>;
-               };
-
-               mas_snoc_cfg: mas-snoc-cfg {
-                       cell-id = <MSM_BUS_MASTER_QDSS_SNOC_CFG>;
-                       label = "mas-snoc-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = <&slv_srvc_snoc>;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_QDSS_SNOC_CFG>;
-               };
-
-               /*Internal nodes*/
-
-
-               pcnoc_m_0: pcnoc-m-0 {
-                       cell-id = <MSM_BUS_PNOC_M_0>;
-                       label = "pcnoc-m-0";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,qport = <12>;
-                       qcom,qos-mode = "fixed";
-                       qcom,connections = <&slv_pcnoc_snoc>;
-                       qcom,prio1 = <1>;
-                       qcom,prio0 = <1>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_0>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_0>;
-               };
-
-               pcnoc_m_1: pcnoc-m-1 {
-                       cell-id = <MSM_BUS_PNOC_M_1>;
-                       label = "pcnoc-m-1";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,qport = <13>;
-                       qcom,qos-mode = "fixed";
-                       qcom,connections = <&slv_pcnoc_snoc>;
-                       qcom,prio1 = <1>;
-                       qcom,prio0 = <1>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_1>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_1>;
-               };
-
-               pcnoc_int_0: pcnoc-int-0 {
-                       cell-id = <MSM_BUS_PNOC_INT_0>;
-                       label = "pcnoc-int-0";
-                       qcom,buswidth = <8>;
-                       qcom,ap-owned;
-                       qcom,connections = < &pcnoc_s_1 &pcnoc_s_2 &pcnoc_s_0
-                                &pcnoc_s_4 &pcnoc_s_5
-                                &pcnoc_s_6 &pcnoc_s_7
-                                &pcnoc_s_8 &pcnoc_s_9
-                                &pcnoc_s_3>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_0>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_0>;
-               };
-
-               pcnoc_s_0: pcnoc-s-0 {
-                       cell-id = <MSM_BUS_PNOC_SLV_0>;
-                       label = "pcnoc-s-0";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = <&slv_clk_ctl &slv_tcsr &slv_security
-                                &slv_tlmm>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_0>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_0>;
-               };
-
-               pcnoc_s_1: pcnoc-s-1 {
-                       cell-id = <MSM_BUS_PNOC_SLV_1>;
-                       label = "pcnoc-s-1";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = < &slv_prng_apu_cfg &slv_prng&slv_imem_cfg>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_1>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_1>;
-               };
-
-               pcnoc_s_2: pcnoc-s-2 {
-                       cell-id = <MSM_BUS_PNOC_SLV_2>;
-                       label = "pcnoc-s-2";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = < &slv_spdm &slv_pcnoc_mpu_cfg &slv_pcnoc_cfg
-                               &slv_boot_rom>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_2>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_2>;
-               };
-
-               pcnoc_s_3: pcnoc-s-3 {
-                       cell-id = <MSM_BUS_PNOC_SLV_3>;
-                       label = "pcnoc-s-3";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = < &slv_qdss_cfg&slv_gcnt &slv_snoc_cfg
-                                &slv_snoc_mpu_cfg>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_3>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_3>;
-               };
-
-               pcnoc_s_4: pcnoc-s-4 {
-                       cell-id = <MSM_BUS_PNOC_SLV_4>;
-                       label = "pcnoc-s-4";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = <&slv_adss_cfg &slv_adss_vmidmt_cfg &slv_adss_apu>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_4>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_4>;
-               };
-
-               pcnoc_s_5: pcnoc-s-5 {
-                       cell-id = <MSM_BUS_PNOC_SLV_5>;
-                       label = "pcnoc-s-5";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = <&slv_qhss_apu_cfg &slv_fephy_cfg &slv_mdio
-                                &slv_srif>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_5>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_5>;
-               };
-
-               pcnoc_s_6: pcnoc-s-6 {
-                       cell-id = <MSM_BUS_PNOC_SLV_6>;
-                       label = "pcnoc-s-6";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = < &slv_ddrc_mpu0_cfg &slv_ddrc_apu_cfg &slv_ddrc_mpu2_cfg
-                               &slv_ddrc_cfg &slv_ddrc_mpu1_cfg>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_6>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_6>;
-               };
-
-               pcnoc_s_7: pcnoc-s-7 {
-                       cell-id = <MSM_BUS_PNOC_SLV_7>;
-                       label = "pcnoc-s-7";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = < &slv_ess_apu_cfg &slv_usb2_cfg&slv_ess_vmidmt_cfg>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_7>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_7>;
-               };
-
-               pcnoc_s_8: pcnoc-s-8 {
-                       cell-id = <MSM_BUS_PNOC_SLV_8>;
-                       label = "pcnoc-s-8";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = < &slv_sdcc_cfg &slv_qpic_cfg&slv_blsp_cfg>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_8>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_8>;
-               };
-
-               pcnoc_s_9: pcnoc-s-9 {
-                       cell-id = <MSM_BUS_PNOC_SLV_9>;
-                       label = "pcnoc-s-9";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,connections = < &slv_wss1_apu_cfg &slv_wss1_vmidmt_cfg&slv_wss0_vmidmt_cfg
-                                &slv_wss0_apu_cfg>;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_9>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_9>;
-               };
-
-               snoc_int_0: snoc-int-0 {
-                       cell-id = <MSM_BUS_SNOC_INT_0>;
-                       label = "snoc-int-0";
-                       qcom,buswidth = <8>;
-                       qcom,ap-owned;
-                       qcom,connections = < &slv_ocimem&slv_qdss_stm>;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_0>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_0>;
-               };
-
-               snoc_int_1: snoc-int-1 {
-                       cell-id = <MSM_BUS_SNOC_INT_1>;
-                       label = "snoc-int-1";
-                       qcom,buswidth = <8>;
-                       qcom,ap-owned;
-                       qcom,connections = < &slv_crypto_cfg &slv_a7ss &slv_ess_cfg
-                                &slv_usb3_cfg &slv_wss1_cfg
-                               &slv_wss0_cfg>;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_1>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_1>;
-               };
-
-               qdss_int: qdss-int {
-                       cell-id = <MSM_BUS_SNOC_QDSS_INT>;
-                       label = "qdss-int";
-                       qcom,buswidth = <8>;
-                       qcom,ap-owned;
-                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,mas-rpm-id = <ICBID_MASTER_QDSS_INT>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_INT>;
-               };
-               /*Slaves*/
-
-               slv_clk_ctl:slv-clk-ctl {
-                       cell-id = <MSM_BUS_SLAVE_CLK_CTL>;
-                       label = "slv-clk-ctl";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_CLK_CTL>;
-               };
-
-               slv_security:slv-security {
-                       cell-id = <MSM_BUS_SLAVE_SECURITY>;
-                       label = "slv-security";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_SECURITY>;
-               };
-
-               slv_tcsr:slv-tcsr {
-                       cell-id = <MSM_BUS_SLAVE_TCSR>;
-                       label = "slv-tcsr";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>;
-               };
-
-               slv_tlmm:slv-tlmm {
-                       cell-id = <MSM_BUS_SLAVE_TLMM>;
-                       label = "slv-tlmm";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_TLMM>;
-               };
-
-               slv_imem_cfg:slv-imem-cfg {
-                       cell-id = <MSM_BUS_SLAVE_IMEM_CFG>;
-                       label = "slv-imem-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_IMEM_CFG>;
-               };
-
-               slv_prng:slv-prng {
-                       cell-id = <MSM_BUS_SLAVE_PRNG>;
-                       label = "slv-prng";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>;
-               };
-
-               slv_prng_apu_cfg:slv-prng-apu-cfg {
-                       cell-id = <MSM_BUS_SLAVE_PRNG_APU_CFG>;
-                       label = "slv-prng-apu-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PRNG_APU_CFG>;
-               };
-
-               slv_boot_rom:slv-boot-rom {
-                       cell-id = <MSM_BUS_SLAVE_BOOT_ROM>;
-                       label = "slv-boot-rom";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_BOOT_ROM>;
-               };
-
-               slv_spdm:slv-spdm {
-                       cell-id = <MSM_BUS_SLAVE_SPDM_WRAPPER>;
-                       label = "slv-spdm";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_SPDM_WRAPPER>;
-               };
-
-               slv_pcnoc_cfg:slv-pcnoc-cfg {
-                       cell-id = <MSM_BUS_SLAVE_PNOC_CFG>;
-                       label = "slv-pcnoc-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PNOC_CFG>;
-               };
-
-               slv_pcnoc_mpu_cfg:slv-pcnoc-mpu-cfg {
-                       cell-id = <MSM_BUS_SLAVE_PERIPH_MPU_CFG>;
-                       label = "slv-pcnoc-mpu-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PERIPH_MPU_CFG>;
-               };
-
-               slv_gcnt:slv-gcnt {
-                       cell-id = <MSM_BUS_SLAVE_GCNT>;
-                       label = "slv-gcnt";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_GCNT>;
-               };
-
-               slv_qdss_cfg:slv-qdss-cfg {
-                       cell-id = <MSM_BUS_SLAVE_QDSS_CFG>;
-                       label = "slv-qdss-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_CFG>;
-               };
-
-               slv_snoc_cfg:slv-snoc-cfg {
-                       cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
-                       label = "slv-snoc-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CFG>;
-               };
-
-               slv_snoc_mpu_cfg:slv-snoc-mpu-cfg {
-                       cell-id = <MSM_BUS_SLAVE_SNOC_MPU_CFG>;
-                       label = "slv-snoc-mpu-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_MPU_CFG>;
-               };
-
-               slv_adss_cfg:slv-adss-cfg {
-                       cell-id = <MSM_BUS_SLAVE_ADSS_CFG>;
-                       label = "slv-adss-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_ADSS_CFG>;
-               };
-
-               slv_adss_apu:slv-adss-apu {
-                       cell-id = <MSM_BUS_SLAVE_ADSS_VMIDMT_CFG>;
-                       label = "slv-adss-apu";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_ADSS_APU>;
-               };
-
-               slv_adss_vmidmt_cfg:slv-adss-vmidmt-cfg {
-                       cell-id = <MSM_BUS_SLAVE_ADSS_VMIDMT_CFG>;
-                       label = "slv-adss-vmidmt-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_ADSS_VMIDMT_CFG>;
-               };
-
-               slv_qhss_apu_cfg:slv-qhss-apu-cfg {
-                       cell-id = <MSM_BUS_SLAVE_QHSS_APU_CFG>;
-                       label = "slv-qhss-apu-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_QHSS_APU_CFG>;
-               };
-
-               slv_mdio:slv-mdio {
-                       cell-id = <MSM_BUS_SLAVE_MDIO>;
-                       label = "slv-mdio";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_MDIO>;
-               };
-
-               slv_fephy_cfg:slv-fephy-cfg {
-                       cell-id = <MSM_BUS_SLAVE_FEPHY_CFG>;
-                       label = "slv-fephy-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_FEPHY_CFG>;
-               };
-
-               slv_srif:slv-srif {
-                       cell-id = <MSM_BUS_SLAVE_SRIF>;
-                       label = "slv-srif";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_SRIF>;
-               };
-
-               slv_ddrc_cfg:slv-ddrc-cfg {
-                       cell-id = <MSM_BUS_SLAVE_DDRC_CFG>;
-                       label = "slv-ddrc-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_CFG>;
-               };
-
-               slv_ddrc_apu_cfg:slv-ddrc-apu-cfg {
-                       cell-id = <MSM_BUS_SLAVE_DDRC_APU_CFG>;
-                       label = "slv-ddrc-apu-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_APU_CFG>;
-               };
-
-               slv_ddrc_mpu0_cfg:slv-ddrc-mpu0-cfg {
-                       cell-id = <MSM_BUS_SLAVE_MPU0_CFG>;
-                       label = "slv-ddrc-mpu0-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_MPU0_CFG>;
-               };
-
-               slv_ddrc_mpu1_cfg:slv-ddrc-mpu1-cfg {
-                       cell-id = <MSM_BUS_SLAVE_MPU1_CFG>;
-                       label = "slv-ddrc-mpu1-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_MPU1_CFG>;
-               };
-
-               slv_ddrc_mpu2_cfg:slv-ddrc-mpu2-cfg {
-                       cell-id = <MSM_BUS_SLAVE_MPU2_CFG>;
-                       label = "slv-ddrc-mpu2-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_MPU2_CFG>;
-               };
-
-               slv_ess_vmidmt_cfg:slv-ess-vmidmt-cfg {
-                       cell-id = <MSM_BUS_SLAVE_ESS_VMIDMT_CFG>;
-                       label = "slv-ess-vmidmt-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_ESS_VMIDMT_CFG>;
-               };
-
-               slv_ess_apu_cfg:slv-ess-apu-cfg {
-                       cell-id = <MSM_BUS_SLAVE_ESS_APU_CFG>;
-                       label = "slv-ess-apu-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_ESS_APU_CFG>;
-               };
-
-               slv_usb2_cfg:slv-usb2-cfg {
-                       cell-id = <MSM_BUS_SLAVE_USB2_CFG>;
-                       label = "slv-usb2-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_USB2_CFG>;
-               };
-
-               slv_blsp_cfg:slv-blsp-cfg {
-                       cell-id = <MSM_BUS_SLAVE_BLSP_CFG>;
-                       label = "slv-blsp-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_CFG>;
-               };
-
-               slv_qpic_cfg:slv-qpic-cfg {
-                       cell-id = <MSM_BUS_SLAVE_QPIC_CFG>;
-                       label = "slv-qpic-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_QPIC_CFG>;
-               };
-
-               slv_sdcc_cfg:slv-sdcc-cfg {
-                       cell-id = <MSM_BUS_SLAVE_SDCC_CFG>;
-                       label = "slv-sdcc-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_CFG>;
-               };
-
-               slv_wss0_vmidmt_cfg:slv-wss0-vmidmt-cfg {
-                       cell-id = <MSM_BUS_SLAVE_WSS0_VMIDMT_CFG>;
-                       label = "slv-wss0-vmidmt-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS0_VMIDMT_CFG>;
-               };
-
-               slv_wss0_apu_cfg:slv-wss0-apu-cfg {
-                       cell-id = <MSM_BUS_SLAVE_WSS0_APU_CFG>;
-                       label = "slv-wss0-apu-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS0_APU_CFG>;
-               };
-
-               slv_wss1_vmidmt_cfg:slv-wss1-vmidmt-cfg {
-                       cell-id = <MSM_BUS_SLAVE_WSS1_VMIDMT_CFG>;
-                       label = "slv-wss1-vmidmt-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS1_VMIDMT_CFG>;
-               };
-
-               slv_wss1_apu_cfg:slv-wss1-apu-cfg {
-                       cell-id = <MSM_BUS_SLAVE_WSS1_APU_CFG>;
-                       label = "slv-wss1-apu-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS1_APU_CFG>;
-               };
-
-               slv_pcnoc_snoc:slv-pcnoc-snoc {
-                       cell-id = <MSM_BUS_PNOC_SNOC_SLV>;
-                       label = "slv-pcnoc-snoc";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_SNOC>;
-               };
-
-               slv_srvc_pcnoc:slv-srvc-pcnoc {
-                       cell-id = <MSM_BUS_SLAVE_SRVC_PCNOC>;
-                       label = "slv-srvc-pcnoc";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_pcnoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_SRVC_PCNOC>;
-               };
-
-               slv_snoc_ddrc_m1:slv-snoc-ddrc-m1 {
-                       cell-id = <MSM_BUS_SLAVE_SNOC_DDRC>;
-                       label = "slv-snoc-ddrc-m1";
-                       qcom,buswidth = <8>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_DDRC>;
-               };
-
-               slv_a7ss:slv-a7ss {
-                       cell-id = <MSM_BUS_SLAVE_A7SS>;
-                       label = "slv-a7ss";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_A7SS>;
-               };
-
-               slv_ocimem:slv-ocimem {
-                       cell-id = <MSM_BUS_SLAVE_OCIMEM>;
-                       label = "slv-ocimem";
-                       qcom,buswidth = <8>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_OCIMEM>;
-               };
-
-               slv_wss0_cfg:slv-wss0-cfg {
-                       cell-id = <MSM_BUS_SLAVE_WSS0_CFG>;
-                       label = "slv-wss0-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS0_CFG>;
-               };
-
-               slv_wss1_cfg:slv-wss1-cfg {
-                       cell-id = <MSM_BUS_SLAVE_WSS1_CFG>;
-                       label = "slv-wss1-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS1_CFG>;
-               };
-
-               slv_pcie:slv-pcie {
-                       cell-id = <MSM_BUS_SLAVE_PCIE>;
-                       label = "slv-pcie";
-                       qcom,buswidth = <8>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_PCIE>;
-               };
-
-               slv_usb3_cfg:slv-usb3-cfg {
-                       cell-id = <MSM_BUS_SLAVE_USB3_CFG>;
-                       label = "slv-usb3-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_USB3_CFG>;
-               };
-
-               slv_crypto_cfg:slv-crypto-cfg {
-                       cell-id = <MSM_BUS_SLAVE_CRYPTO_CFG>;
-                       label = "slv-crypto-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_CRYPTO_CFG>;
-               };
-
-               slv_ess_cfg:slv-ess-cfg {
-                       cell-id = <MSM_BUS_SLAVE_ESS_CFG>;
-                       label = "slv-ess-cfg";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_ESS_CFG>;
-               };
-
-               slv_qdss_stm:slv-qdss-stm {
-                       cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
-                       label = "slv-qdss-stm";
-                       qcom,buswidth = <4>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>;
-               };
-
-               slv_srvc_snoc:slv-srvc-snoc {
-                       cell-id = <MSM_BUS_SLAVE_SRVC_SNOC>;
-                       label = "slv-srvc-snoc";
-                       qcom,buswidth = <8>;
-                       qcom,ap-owned;
-                       qcom,bus-dev = <&fab_snoc>;
-                       qcom,slv-rpm-id = <ICBID_SLAVE_SRVC_SNOC>;
-               };
-       };
-};
-
-};
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-fritz4040.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-fritz4040.dts
deleted file mode 100644 (file)
index f5ca3d5..0000000
+++ /dev/null
@@ -1,322 +0,0 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include "qcom-ipq4019-bus.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-       model = "AVM FRITZ!Box 4040";
-       compatible = "avm,fritzbox-4040", "qcom,ipq4019";
-
-       aliases {
-               led-boot = &power;
-               led-failsafe = &flash;
-               led-running = &power;
-               led-upgrade = &flash;
-       };
-
-       reserved-memory {
-               #address-cells = <0x1>;
-               #size-cells = <0x1>;
-               ranges;
-
-               tz_apps@87b80000 {
-                       reg = <0x87b80000 0x280000>;
-                       reusable;
-               };
-
-               smem@87e00000 {
-                       reg = <0x87e00000 0x080000>;
-                       no-map;
-               };
-
-               tz@87e80000 {
-                       reg = <0x87e80000 0x180000>;
-                       no-map;
-               };
-       };
-
-       soc {
-               mdio@90000 {
-                       status = "okay";
-               };
-
-               ess-psgmii@98000 {
-                       status = "okay";
-               };
-
-               tcsr@1949000 {
-                       compatible = "qcom,tcsr";
-                       reg = <0x1949000 0x100>;
-                       qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-               };
-
-               tcsr@194b000 {
-                       compatible = "qcom,tcsr";
-                       reg = <0x194b000 0x100>;
-                       qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-               };
-
-               ess_tcsr@1953000 {
-                       compatible = "qcom,tcsr";
-                       reg = <0x1953000 0x1000>;
-                       qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-               };
-
-               tcsr@1957000 {
-                       compatible = "qcom,tcsr";
-                       reg = <0x1957000 0x100>;
-                       qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-               };
-
-               usb2@60f8800 {
-                       status = "ok";
-               };
-
-               serial@78af000 {
-                       pinctrl-0 = <&serial_pins>;
-                       pinctrl-names = "default";
-                       status = "ok";
-               };
-
-               usb3@8af8800 {
-                       status = "ok";
-               };
-
-               crypto@8e3a000 {
-                       status = "ok";
-               };
-
-               wifi@a000000 {
-                       status = "okay";
-               };
-
-               wifi@a800000 {
-                       status = "okay";
-               };
-
-               watchdog@b017000 {
-                       status = "ok";
-               };
-
-               qca8075: ess-switch@c000000 {
-                       status = "okay";
-
-                       #gpio-cells = <2>;
-                       gpio-controller;
-
-                       enable-usb-power {
-                               gpio-hog;
-                               line-name = "enable USB3 power";
-                               gpios = <7 GPIO_ACTIVE_HIGH>;
-                               output-high;
-                       };
-               };
-
-               edma@c080000 {
-                       status = "okay";
-               };
-       };
-
-       gpio-keys {
-               compatible = "gpio-keys";
-
-               wlan {
-                       label = "wlan";
-                       gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
-                       linux,code = <KEY_RFKILL>;
-               };
-
-               wps {
-                       label = "wps";
-                       gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-                       linux,code = <KEY_WPS_BUTTON>;
-               };
-       };
-
-       gpio-leds {
-               compatible = "gpio-leds";
-
-               wlan {
-                       label = "fritz4040:green:wlan";
-                       gpios = <&qca8075 1 GPIO_ACTIVE_HIGH>;
-               };
-
-               panic: info_red {
-                       label = "fritz4040:red:info";
-                       gpios = <&qca8075 3 GPIO_ACTIVE_HIGH>;
-                       panic-indicator;
-               };
-
-               wan {
-                       label = "fritz4040:green:wan";
-                       gpios = <&qca8075 5 GPIO_ACTIVE_HIGH>;
-               };
-
-               power: power {
-                       label = "fritz4040:green:power";
-                       gpios = <&qca8075 11 GPIO_ACTIVE_HIGH>;
-               };
-
-               lan {
-                       label = "fritz4040:green:lan";
-                       gpios = <&qca8075 13 GPIO_ACTIVE_HIGH>;
-               };
-
-               flash: info_amber {
-                       label = "fritz4040:amber:info";
-                       gpios = <&qca8075 15 GPIO_ACTIVE_HIGH>;
-               };
-       };
-};
-
-&tlmm {
-       serial_pins: serial_pinmux {
-               mux {
-                       pins = "gpio60", "gpio61";
-                       function = "blsp_uart0";
-                       bias-disable;
-               };
-       };
-
-       spi_0_pins: spi_0_pinmux {
-               mux {
-                       function = "blsp_spi0";
-                       pins = "gpio55", "gpio56", "gpio57";
-                       drive-strength = <12>;
-                       bias-disable;
-               };
-
-               mux_cs {
-                       function = "gpio";
-                       pins = "gpio54";
-                       drive-strength = <2>;
-                       bias-disable;
-                       output-high;
-               };
-       };
-};
-
-&cryptobam {
-       status = "ok";
-};
-
-&blsp_dma {
-       status = "ok";
-};
-
-&spi_0 { /* BLSP1 QUP1 */
-       pinctrl-0 = <&spi_0_pins>;
-       pinctrl-names = "default";
-       status = "ok";
-       cs-gpios = <&tlmm 54 0>;
-
-       mx25l25635f@0 {
-               compatible = "jedec,spi-nor";
-               #address-cells = <1>;
-               #size-cells = <0>;
-               reg = <0>;
-               spi-max-frequency = <24000000>;
-               status = "ok";
-               m25p,fast-read;
-
-               partitions {
-                       compatible = "fixed-partitions";
-                       #address-cells = <1>;
-                       #size-cells = <1>;
-
-                       partition0@0 {
-                               label = "SBL1";
-                               reg = <0x00000000 0x00040000>;
-                               read-only;
-                       };
-                       partition1@40000 {
-                               label = "MIBIB";
-                               reg = <0x00040000 0x00020000>;
-                               read-only;
-                       };
-                       partition2@60000 {
-                               label = "QSEE";
-                               reg = <0x00060000 0x00060000>;
-                               read-only;
-                       };
-                       partition3@c0000 {
-                               label = "CDT";
-                               reg = <0x000c0000 0x00010000>;
-                               read-only;
-                       };
-                       partition4@d0000 {
-                               label = "DDRPARAMS";
-                               reg = <0x000d0000 0x00010000>;
-                               read-only;
-                       };
-                       partition5@e0000 {
-                               label = "APPSBLENV"; /* uboot env - empty */
-                               reg = <0x000e0000 0x00010000>;
-                               read-only;
-                       };
-                       partition6@f0000 {
-                               label = "urlader"; /* APPSBL */
-                               reg = <0x000f0000 0x0002dc000>;
-                               read-only;
-                       };
-                       partition7@11dc00 {
-                               /* make a backup of this partition! */
-                               label = "urlader_config";
-                               reg = <0x0011dc00 0x00002400>;
-                               read-only;
-                       };
-                       partition8@120000 {
-                               label = "tffs1";
-                               reg = <0x00120000 0x00080000>;
-                               read-only;
-                       };
-                       partition9@1a0000 {
-                               label = "tffs2";
-                               reg = <0x001a0000 0x00080000>;
-                               read-only;
-                       };
-                       partition10@220000 {
-                               label = "uboot";
-                               reg = <0x00220000 0x00080000>;
-                               read-only;
-                       };
-                       partition11@2A0000 {
-                               label = "firmware";
-                               reg = <0x002a0000 0x01c60000>;
-                       };
-                       partition12@1f00000 {
-                               label = "jffs2";
-                               reg = <0x01f00000 0x00100000>;
-                       };
-               };
-       };
-};
-
-&usb3_ss_phy {
-       status = "ok";
-};
-
-&usb3_hs_phy {
-       status = "ok";
-};
-
-&usb2_hs_phy {
-       status = "ok";
-};
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-gl-b1300.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-gl-b1300.dts
deleted file mode 100644 (file)
index 53824e3..0000000
+++ /dev/null
@@ -1,316 +0,0 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-       model = "GL.iNet GL-B1300";
-       compatible = "glinet,gl-b1300", "qcom,ipq4019";
-
-       memory {
-               device_type = "memory";
-               reg = <0x80000000 0x10000000>;
-       };
-
-       reserved-memory {
-               #address-cells = <0x1>;
-               #size-cells = <0x1>;
-               ranges;
-
-               apps_bl@87000000 {
-                       reg = <0x87000000 0x400000>;
-                       no-map;
-               };
-
-               sbl@87400000 {
-                       reg = <0x87400000 0x100000>;
-                       no-map;
-               };
-
-               cnss_debug@87500000 {
-                       reg = <0x87500000 0x600000>;
-                       no-map;
-               };
-
-               cpu_context_dump@87b00000 {
-                       reg = <0x87b00000 0x080000>;
-                       no-map;
-               };
-
-               tz_apps@87b80000 {
-                       reg = <0x87b80000 0x280000>;
-                       no-map;
-               };
-
-               smem@87e00000 {
-                       reg = <0x87e00000 0x080000>;
-                       no-map;
-               };
-
-               tz@87e80000 {
-                       reg = <0x87e80000 0x180000>;
-                       no-map;
-               };
-       };
-
-       soc {
-               tcsr@194b000 {
-                       /* select hostmode */
-                       compatible = "qcom,tcsr";
-                       reg = <0x194b000 0x100>;
-                       qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-                       status = "ok";
-               };
-
-               ess_tcsr@1953000 {
-                       compatible = "qcom,tcsr";
-                       reg = <0x1953000 0x1000>;
-                       qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-               };
-
-               tcsr@1949000 {
-                       compatible = "qcom,tcsr";
-                       reg = <0x1949000 0x100>;
-                       qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-               };
-
-               tcsr@1957000 {
-                       compatible = "qcom,tcsr";
-                       reg = <0x1957000 0x100>;
-                       qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-               };
-
-               pinctrl@1000000 {
-                       serial_pins: serial_pinmux {
-                               mux {
-                                       pins = "gpio60", "gpio61";
-                                       function = "blsp_uart0";
-                                       bias-disable;
-                               };
-                       };
-
-                       spi_0_pins: spi_0_pinmux {
-                               pinmux {
-                                       function = "blsp_spi0";
-                                       pins = "gpio55", "gpio56", "gpio57";
-                               };
-                               pinmux_cs {
-                                       function = "gpio";
-                                       pins = "gpio54";
-                               };
-                               pinconf {
-                                       pins = "gpio55", "gpio56", "gpio57";
-                                       drive-strength = <12>;
-                                       bias-disable;
-                               };
-                               pinconf_cs {
-                                       pins = "gpio54";
-                                       drive-strength = <2>;
-                                       bias-disable;
-                                       output-high;
-                               };
-                       };
-               };
-
-               blsp_dma: dma@7884000 {
-                       status = "ok";
-               };
-
-               spi_0: spi@78b5000 {
-                       pinctrl-0 = <&spi_0_pins>;
-                       pinctrl-names = "default";
-                       status = "ok";
-                       cs-gpios = <&tlmm 54 0>;
-               };
-
-               serial@78af000 {
-                       pinctrl-0 = <&serial_pins>;
-                       pinctrl-names = "default";
-                       status = "ok";
-               };
-
-               cryptobam: dma@8e04000 {
-                       status = "ok";
-               };
-
-               crypto@8e3a000 {
-                       status = "ok";
-               };
-
-               watchdog@b017000 {
-                       status = "ok";
-               };
-
-               usb3_ss_phy: ssphy@9a000 {
-                       status = "ok";
-               };
-
-               usb3_hs_phy: hsphy@a6000 {
-                       status = "ok";
-               };
-
-               usb3: usb3@8af8800 {
-                       status = "ok";
-               };
-
-               usb2_hs_phy: hsphy@a8000 {
-                       status = "ok";
-               };
-
-               usb2: usb2@60f8800 {
-                       status = "ok";
-               };
-
-               mdio@90000 {
-                       status = "okay";
-               };
-
-               ess-switch@c000000 {
-                       status = "okay";
-               };
-
-               ess-psgmii@98000 {
-                       status = "okay";
-               };
-
-               edma@c080000 {
-                       status = "okay";
-               };
-
-               wifi@a000000 {
-                       status = "okay";
-               };
-
-               wifi@a800000 {
-                       status = "okay";
-               };
-       };
-
-       gpio-keys {
-               compatible = "gpio-keys";
-
-               wps {
-                       label = "wps";
-                       gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-                       linux,code = <KEY_WPS_BUTTON>;
-               };
-               reset {
-                       label = "reset";
-                       gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-                       linux,code = <KEY_RESTART>;
-               };
-       };
-
-       gpio-leds {
-               compatible = "gpio-leds";
-
-               power {
-                       label = "gl-b1300:green:power";
-                       gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
-                       default-state = "on";
-               };
-               mesh {
-                       label = "gl-b1300:green:mesh";
-                       gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-               };
-               wlan {
-                       label = "gl-b1300:green:wlan";
-                       gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-               };
-       };
-};
-
-&spi_0 {
-       mx25l25635f@0 {
-               compatible = "mx25l25635f", "jedec,spi-nor";
-               #address-cells = <1>;
-               #size-cells = <1>;
-               reg = <0>;
-               spi-max-frequency = <24000000>;
-
-               SBL1@0 {
-                       label = "SBL1";
-                       reg = <0x0 0x40000>;
-                       read-only;
-               };
-               MIBIB@40000 {
-                       label = "MIBIB";
-                       reg = <0x40000 0x20000>;
-                       read-only;
-               };
-               QSEE@60000 {
-                       label = "QSEE";
-                       reg = <0x60000 0x60000>;
-                       read-only;
-               };
-               CDT@c0000 {
-                       label = "CDT";
-                       reg = <0xc0000 0x10000>;
-                       read-only;
-               };
-               DDRPARAMS@d0000 {
-                       label = "DDRPARAMS";
-                       reg = <0xd0000 0x10000>;
-                       read-only;
-               };
-               APPSBLENV@e0000 {
-                       label = "APPSBLENV";
-                       reg = <0xe0000 0x10000>;
-                       read-only;
-               };
-               APPSBL@f0000 {
-                       label = "APPSBL";
-                       reg = <0xf0000 0x80000>;
-                       read-only;
-               };
-               ART@170000 {
-                       label = "ART";
-                       reg = <0x170000 0x10000>;
-                       read-only;
-               };
-               kernel@180000 {
-                       label = "kernel";
-                       reg = <0x180000 0x400000>;
-               };
-               rootfs@580000 {
-                       label = "rootfs";
-                       reg = <0x580000 0x1a80000>;
-               };
-               firmware@180000 {
-                       label = "firmware";
-                       reg = <0x180000 0x1e80000>;
-               };
-       };
-};
-
-&gmac0 {
-       qcom,phy_mdio_addr = <4>;
-       qcom,poll_required = <1>;
-       qcom,forced_speed = <1000>;
-       qcom,forced_duplex = <1>;
-       vlan_tag = <2 0x20>;
-};
-
-&gmac1 {
-       qcom,phy_mdio_addr = <3>;
-       qcom,poll_required = <1>;
-       qcom,forced_speed = <1000>;
-       qcom,forced_duplex = <1>;
-       vlan_tag = <1 0x10>;
-};
\ No newline at end of file
index c2d7255..d41679f 100644 (file)
@@ -73,21 +73,6 @@ define Device/ZyXELImage
        IMAGE/mmcblk0p4-kernel.bin := append-kernel
 endef
 
-define Device/avm_fritzbox-4040
-       $(call Device/FitImageLzma)
-       DEVICE_DTS := qcom-ipq4019-fritz4040
-       KERNEL_LOADADDR := 0x80208000
-       BLOCKSIZE := 4k
-       PAGESIZE := 256
-       BOARD_NAME := fritz4040
-       DEVICE_TITLE := AVM Fritz!Box 4040
-       IMAGE_SIZE := 29753344
-       IMAGES = sysupgrade.bin
-       IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
-       DEVICE_PACKAGES := ipq-wifi-avm_fritzbox-4040 fritz-tffs fritz-caldata u-boot-fritz4040
-endef
-TARGET_DEVICES += avm_fritzbox-4040
-
 define Device/linksys_ea8500
        $(call Device/LegacyImage)
        DEVICE_DTS := qcom-ipq8064-ea8500
@@ -165,66 +150,6 @@ define Device/netgear_r7800
 endef
 TARGET_DEVICES += netgear_r7800
 
-define Device/glinet_gl-b1300
-       DEVICE_TITLE := GL.iNet GL-B1300
-       BOARD_NAME := gl-b1300
-       DEVICE_DTS := qcom-ipq4019-gl-b1300
-       KERNEL_LOADADDR := 0x80208000
-       KERNEL_INSTALL := 1
-       KERNEL_SIZE := 4096k
-       IMAGE_SIZE := 26624k
-       $(call Device/FitImage)
-       IMAGES := sysupgrade.bin
-       IMAGE/sysupgrade.bin := append-kernel | pad-to $$$${KERNEL_SIZE} | append-rootfs | pad-rootfs | append-metadata
-       DEVICE_PACKAGES := ipq-wifi-glinet_gl-b1300
-endef
-TARGET_DEVICES += glinet_gl-b1300
-
-define Device/openmesh_a42
-       $(call Device/FitImageLzma)
-       DEVICE_DTS := qcom-ipq4019-a42
-       KERNEL_LOADADDR := 0x80208000
-       BLOCKSIZE := 64k
-       SUPPORTED_DEVICES := openmesh,a42
-       DEVICE_TITLE := OpenMesh A42
-       KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE)
-       IMAGE_SIZE := 15616k
-       IMAGES = factory.bin sysupgrade.bin
-       IMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=A42
-       IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata
-       DEVICE_PACKAGES := ath10k-firmware-qca4019 uboot-envtools
-endef
-TARGET_DEVICES += openmesh_a42
-
-define Device/qcom_ap-dk01.1-c1
-       DEVICE_TITLE := QCA AP-DK01.1-C1
-       BOARD_NAME := ap-dk01.1-c1
-       DEVICE_DTS := qcom-ipq4019-ap.dk01.1-c1
-       KERNEL_LOADADDR := 0x80208000
-       KERNEL_INSTALL := 1
-       KERNEL_SIZE := 4096k
-       IMAGE_SIZE := 26624k
-       $(call Device/FitImage)
-       IMAGES := sysupgrade.bin
-       IMAGE/sysupgrade.bin := append-kernel | pad-to $$$${KERNEL_SIZE} | append-rootfs | pad-rootfs | append-metadata
-       DEVICE_PACKAGES := ath10k-firmware-qca4019
-endef
-TARGET_DEVICES += qcom_ap-dk01.1-c1
-
-define Device/qcom_ap-dk04.1-c1
-       $(call Device/FitImage)
-       $(call Device/UbiFit)
-       DEVICE_DTS := qcom-ipq4019-ap.dk04.1-c1
-       KERNEL_LOADADDR := 0x80208000
-       KERNEL_INSTALL := 1
-       KERNEL_SIZE := 4048k
-       BLOCKSIZE := 128k
-       PAGESIZE := 2048
-       BOARD_NAME := ap-dk04.1-c1
-       DEVICE_TITLE := QCA AP-DK04.1-C1
-endef
-TARGET_DEVICES += qcom_ap-dk04.1-c1
-
 define Device/qcom_ipq8064-ap148
        $(call Device/FitImage)
        $(call Device/UbiFit)
diff --git a/target/linux/ipq806x/patches-4.9/0015-cpufreq-dt-qcom-ipq4019-Add-compat-for-qcom-ipq4019.patch b/target/linux/ipq806x/patches-4.9/0015-cpufreq-dt-qcom-ipq4019-Add-compat-for-qcom-ipq4019.patch
deleted file mode 100644 (file)
index 06b61a0..0000000
+++ /dev/null
@@ -1,27 +0,0 @@
-From 5543e93f51d5e23f9b3a7fe11a722c91fc410485 Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Wed, 13 Apr 2016 14:03:14 -0500
-Subject: [PATCH 15/69] cpufreq: dt: qcom: ipq4019: Add compat for qcom ipq4019
-
-Instantiate  cpufreq-dt-platdev driver for ipq4019 to support changing
-CPU frequencies.
-
-This depends on Viresh Kumar's patches in this series:
-http://comments.gmane.org/gmane.linux.power-management.general/73887
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
----
- drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/cpufreq/cpufreq-dt-platdev.c
-+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
-@@ -35,6 +35,8 @@ static const struct of_device_id machine
-       { .compatible = "marvell,berlin", },
-+      { .compatible = "qcom,ipq4019", },
-+
-       { .compatible = "samsung,exynos3250", },
-       { .compatible = "samsung,exynos4210", },
-       { .compatible = "samsung,exynos4212", },
diff --git a/target/linux/ipq806x/patches-4.9/0016-clk-ipq4019-report-accurate-fixed-clock-rates.patch b/target/linux/ipq806x/patches-4.9/0016-clk-ipq4019-report-accurate-fixed-clock-rates.patch
deleted file mode 100644 (file)
index be9c4eb..0000000
+++ /dev/null
@@ -1,33 +0,0 @@
-From 5e2df5f44e35d79fff2ab8bbb8a726ad5de78a3e Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@qca.qualcomm.com>
-Date: Thu, 28 Apr 2016 12:55:08 -0500
-Subject: [PATCH 16/69] clk: ipq4019: report accurate fixed clock rates
-
-This looks like a copy-and-paste gone wrong, but update all
-the fixed clock rates to report the correct values.
-
-Signed-off-by: Matthew McClintock <mmcclint@qca.qualcomm.com>
----
- drivers/clk/qcom/gcc-ipq4019.c | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq4019.c
-+++ b/drivers/clk/qcom/gcc-ipq4019.c
-@@ -1327,12 +1327,12 @@ static int gcc_ipq4019_probe(struct plat
- {
-       struct device *dev = &pdev->dev;
--      clk_register_fixed_rate(dev, "fepll125", "xo", 0, 200000000);
--      clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 200000000);
--      clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 200000000);
--      clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 200000000);
-+      clk_register_fixed_rate(dev, "fepll125", "xo", 0, 125000000);
-+      clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 125000000);
-+      clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 250000000);
-+      clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 250000000);
-       clk_register_fixed_rate(dev, "fepll200", "xo", 0, 200000000);
--      clk_register_fixed_rate(dev, "fepll500", "xo", 0, 200000000);
-+      clk_register_fixed_rate(dev, "fepll500", "xo", 0, 500000000);
-       clk_register_fixed_rate(dev, "ddrpllapss", "xo", 0, 666000000);
-       return qcom_cc_probe(pdev, &gcc_ipq4019_desc);
diff --git a/target/linux/ipq806x/patches-4.9/0017-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch b/target/linux/ipq806x/patches-4.9/0017-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch
deleted file mode 100644 (file)
index 7cbd6a4..0000000
+++ /dev/null
@@ -1,77 +0,0 @@
-From 18c3b42575a154343831aec0637aab00e19440e1 Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Thu, 17 Mar 2016 15:01:09 -0500
-Subject: [PATCH 17/69] qcom: ipq4019: add cpu operating points for cpufreq
- support
-
-This adds some operating points for cpu frequeny scaling
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
- 1 file changed, 26 insertions(+), 8 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -40,14 +40,7 @@
-                       reg = <0x0>;
-                       clocks = <&gcc GCC_APPS_CLK_SRC>;
-                       clock-frequency = <0>;
--                      operating-points = <
--                              /* kHz  uV (fixed) */
--                              48000   1100000
--                              200000  1100000
--                              500000  1100000
--                              666000  1100000
--                      >;
--                      clock-latency = <256000>;
-+                      operating-points-v2 = <&cpu0_opp_table>;
-               };
-               cpu@1 {
-@@ -59,6 +52,7 @@
-                       reg = <0x1>;
-                       clocks = <&gcc GCC_APPS_CLK_SRC>;
-                       clock-frequency = <0>;
-+                      operating-points-v2 = <&cpu0_opp_table>;
-               };
-               cpu@2 {
-@@ -70,6 +64,7 @@
-                       reg = <0x2>;
-                       clocks = <&gcc GCC_APPS_CLK_SRC>;
-                       clock-frequency = <0>;
-+                      operating-points-v2 = <&cpu0_opp_table>;
-               };
-               cpu@3 {
-@@ -81,6 +76,29 @@
-                       reg = <0x3>;
-                       clocks = <&gcc GCC_APPS_CLK_SRC>;
-                       clock-frequency = <0>;
-+                      operating-points-v2 = <&cpu0_opp_table>;
-+              };
-+      };
-+
-+      cpu0_opp_table: opp_table0 {
-+              compatible = "operating-points-v2";
-+              opp-shared;
-+
-+              opp@48000000 {
-+                      opp-hz = /bits/ 64 <48000000>;
-+                      clock-latency-ns = <256000>;
-+              };
-+              opp@200000000 {
-+                      opp-hz = /bits/ 64 <200000000>;
-+                      clock-latency-ns = <256000>;
-+              };
-+              opp@500000000 {
-+                      opp-hz = /bits/ 64 <500000000>;
-+                      clock-latency-ns = <256000>;
-+              };
-+              opp@666000000 {
-+                      opp-hz = /bits/ 64 <666000000>;
-+                      clock-latency-ns = <256000>;
-               };
-       };
diff --git a/target/linux/ipq806x/patches-4.9/0018-qcom-ipq4019-turn-on-DMA-for-i2c.patch b/target/linux/ipq806x/patches-4.9/0018-qcom-ipq4019-turn-on-DMA-for-i2c.patch
deleted file mode 100644 (file)
index 42bb4a6..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-From 71f82049dca86bc89b9da07e051e4ed492820233 Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Mon, 28 Mar 2016 11:16:51 -0500
-Subject: [PATCH 18/69] qcom: ipq4019: turn on DMA for i2c
-
-These are the required nodes for i2c-qup to use DMA
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -179,6 +179,8 @@
-                       clock-names = "iface", "core";
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-+                      dmas = <&blsp_dma 9>, <&blsp_dma 8>;
-+                      dma-names = "rx", "tx";
-                       status = "disabled";
-               };
diff --git a/target/linux/ipq806x/patches-4.9/0019-qcom-ipq4019-use-correct-clock-for-i2c-bus-0.patch b/target/linux/ipq806x/patches-4.9/0019-qcom-ipq4019-use-correct-clock-for-i2c-bus-0.patch
deleted file mode 100644 (file)
index 54ee571..0000000
+++ /dev/null
@@ -1,28 +0,0 @@
-From 7292bf171cdf2fb48607058f12ddd0d812a87428 Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@qca.qualcomm.com>
-Date: Fri, 29 Apr 2016 12:48:02 -0500
-Subject: [PATCH 19/69] qcom: ipq4019: use correct clock for i2c bus 0
-
-For the record the mapping is as follows:
-
-QUP0 = SPI QUP1
-QUP1 = SPI QUP2
-QUP2 = I2C QUP1
-QUP3 = I2C QUP2
-
-Signed-off-by: Matthew McClintock <mmcclint@qca.qualcomm.com>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -175,7 +175,7 @@
-                       reg = <0x78b7000 0x6000>;
-                       interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&gcc GCC_BLSP1_AHB_CLK>,
--                               <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
-+                               <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
-                       clock-names = "iface", "core";
-                       #address-cells = <1>;
-                       #size-cells = <0>;
diff --git a/target/linux/ipq806x/patches-4.9/0020-qcom-ipq4019-enable-DMA-for-spi.patch b/target/linux/ipq806x/patches-4.9/0020-qcom-ipq4019-enable-DMA-for-spi.patch
deleted file mode 100644 (file)
index c1fa5c7..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-From 4593e768393b9589f0a8987eaf57316c214865fe Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Mon, 11 Apr 2016 14:49:12 -0500
-Subject: [PATCH 20/69] qcom: ipq4019: enable DMA for spi
-
-These are the required nodes for spi-qup to use DMA
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -167,6 +167,8 @@
-                       clock-names = "core", "iface";
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-+                      dmas = <&blsp_dma 5>, <&blsp_dma 4>;
-+                      dma-names = "rx", "tx";
-                       status = "disabled";
-               };
diff --git a/target/linux/ipq806x/patches-4.9/0026-dts-ipq4019-Add-support-for-IPQ4019-DK04-board.patch b/target/linux/ipq806x/patches-4.9/0026-dts-ipq4019-Add-support-for-IPQ4019-DK04-board.patch
deleted file mode 100644 (file)
index 8cd3e20..0000000
+++ /dev/null
@@ -1,225 +0,0 @@
-From ec3e465ecf3f7dd26f2e22170e4c5f4b9979df5d Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Mon, 21 Mar 2016 15:55:21 -0500
-Subject: [PATCH 26/69] dts: ipq4019: Add support for IPQ4019 DK04 board
-
-This is pretty similiar to a DK01 but has a bit more IO. Some notable
-differences are listed below however they are not in the device tree yet
-as we continue adding more support
-
-- second serial port
-- PCIe
-- NAND
-- SD/EMMC
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
----
- arch/arm/boot/dts/Makefile                      |   1 +
- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi   |  12 +-
- arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts |  21 +++
- arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi   | 163 ++++++++++++++++++++++++
- 4 files changed, 189 insertions(+), 8 deletions(-)
- create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
- create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
-
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -617,6 +617,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
-       qcom-apq8084-ifc6540.dtb \
-       qcom-apq8084-mtp.dtb \
-       qcom-ipq4019-ap.dk01.1-c1.dtb \
-+      qcom-ipq4019-ap.dk04.1-c1.dtb \
-       qcom-ipq8064-ap148.dtb \
-       qcom-msm8660-surf.dtb \
-       qcom-msm8960-cdp.dtb \
---- /dev/null
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
-@@ -0,0 +1,22 @@
-+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for any
-+ * purpose with or without fee is hereby granted, provided that the above
-+ * copyright notice and this permission notice appear in all copies.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ *
-+ */
-+
-+#include "qcom-ipq4019-ap.dk04.1.dtsi"
-+
-+/ {
-+      model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK04.1-C1";
-+      compatible = "qcom,ap-dk04.1-c1", "qcom,ipq4019";
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
-@@ -0,0 +1,163 @@
-+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for any
-+ * purpose with or without fee is hereby granted, provided that the above
-+ * copyright notice and this permission notice appear in all copies.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ *
-+ */
-+
-+#include "qcom-ipq4019.dtsi"
-+
-+/ {
-+      model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
-+      compatible = "qcom,ipq4019";
-+
-+      clocks {
-+                xo: xo {
-+                        compatible = "fixed-clock";
-+                        clock-frequency = <48000000>;
-+                        #clock-cells = <0>;
-+                };
-+      };
-+
-+      soc {
-+              timer {
-+                      compatible = "arm,armv7-timer";
-+                      interrupts = <1 2 0xf08>,
-+                                   <1 3 0xf08>,
-+                                   <1 4 0xf08>,
-+                                   <1 1 0xf08>;
-+                      clock-frequency = <48000000>;
-+              };
-+
-+              pinctrl@0x01000000 {
-+                      serial_0_pins: serial_pinmux {
-+                              mux {
-+                                      pins = "gpio16", "gpio17";
-+                                      function = "blsp_uart0";
-+                                      bias-disable;
-+                              };
-+                      };
-+
-+                       serial_1_pins: serial1_pinmux {
-+                              mux {
-+                                      pins = "gpio8", "gpio9";
-+                                      function = "blsp_uart1";
-+                                      bias-disable;
-+                              };
-+                      };
-+
-+                      spi_0_pins: spi_0_pinmux {
-+                              pinmux {
-+                                      function = "blsp_spi0";
-+                                      pins = "gpio13", "gpio14", "gpio15";
-+                              };
-+                              pinmux_cs {
-+                                      function = "gpio";
-+                                      pins = "gpio12";
-+                              };
-+                              pinconf {
-+                                      pins = "gpio13", "gpio14", "gpio15";
-+                                      drive-strength = <12>;
-+                                      bias-disable;
-+                              };
-+                              pinconf_cs {
-+                                      pins = "gpio12";
-+                                      drive-strength = <2>;
-+                                      bias-disable;
-+                                      output-high;
-+                              };
-+                      };
-+
-+                      i2c_0_pins: i2c_0_pinmux {
-+                              pinmux {
-+                                      function = "blsp_i2c0";
-+                                      pins = "gpio10", "gpio11";
-+                              };
-+                              pinconf {
-+                                      pins = "gpio10", "gpio11";
-+                                      drive-strength = <16>;
-+                                      bias-disable;
-+                              };
-+                      };
-+              };
-+
-+              blsp_dma: dma@7884000 {
-+                      status = "ok";
-+              };
-+
-+              spi_0: spi@78b5000 {
-+                      pinctrl-0 = <&spi_0_pins>;
-+                      pinctrl-names = "default";
-+                      status = "ok";
-+                      cs-gpios = <&tlmm 12 0>;
-+
-+                      mx25l25635e@0 {
-+                              #address-cells = <1>;
-+                              #size-cells = <1>;
-+                              reg = <0>;
-+                              compatible = "mx25l25635e";
-+                              spi-max-frequency = <24000000>;
-+                      };
-+              };
-+
-+              i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
-+                      pinctrl-0 = <&i2c_0_pins>;
-+                      pinctrl-names = "default";
-+
-+                      status = "ok";
-+              };
-+
-+              serial@78af000 {
-+                      pinctrl-0 = <&serial_0_pins>;
-+                      pinctrl-names = "default";
-+                      status = "ok";
-+              };
-+
-+              serial@78b0000 {
-+                      pinctrl-0 = <&serial_1_pins>;
-+                      pinctrl-names = "default";
-+                      status = "ok";
-+              };
-+
-+              usb3_ss_phy: ssphy@9a000 {
-+                      status = "ok";
-+              };
-+
-+              usb3_hs_phy: hsphy@a6000 {
-+                      status = "ok";
-+              };
-+
-+              usb3: usb3@8af8800 {
-+                      status = "ok";
-+              };
-+
-+              usb2_hs_phy: hsphy@a8000 {
-+                      status = "ok";
-+              };
-+
-+              usb2: usb2@60f8800 {
-+                      status = "ok";
-+              };
-+
-+              cryptobam: dma@8e04000 {
-+                      status = "ok";
-+              };
-+
-+              crypto@8e3a000 {
-+                      status = "ok";
-+              };
-+
-+              watchdog@b017000 {
-+                      status = "ok";
-+              };
-+      };
-+};
index 0f3b20e..bac7c6d 100644 (file)
@@ -10,15 +10,9 @@ Signed-off-by: John Crispin <john@phrozen.org>
 
 --- a/arch/arm/boot/dts/Makefile
 +++ b/arch/arm/boot/dts/Makefile
-@@ -616,9 +616,20 @@ dtb-$(CONFIG_ARCH_QCOM) += \
-       qcom-apq8074-dragonboard.dtb \
-       qcom-apq8084-ifc6540.dtb \
+@@ -618,6 +618,14 @@ dtb-$(CONFIG_ARCH_QCOM) += \
        qcom-apq8084-mtp.dtb \
-+      qcom-ipq4019-a42.dtb \
-+      qcom-ipq4019-gl-b1300.dtb \
        qcom-ipq4019-ap.dk01.1-c1.dtb \
-       qcom-ipq4019-ap.dk04.1-c1.dtb \
-+      qcom-ipq4019-fritz4040.dtb \
        qcom-ipq8064-ap148.dtb \
 +      qcom-ipq8064-c2600.dtb \
 +      qcom-ipq8064-d7800.dtb \
diff --git a/target/linux/ipq806x/patches-4.9/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch b/target/linux/ipq806x/patches-4.9/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch
deleted file mode 100644 (file)
index 40f5e40..0000000
+++ /dev/null
@@ -1,109 +0,0 @@
-From 6a6c067b7ce2b3de4efbafddc134afbea3ddc1a3 Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Fri, 8 Apr 2016 15:26:10 -0500
-Subject: [PATCH] qcom: ipq4019: use v2 of the kpss bringup mechanism
-
-v1 was the incorrect choice here and sometimes the board
-would not come up properly.
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
-Changes:
-       - moved L2-Cache to be a subnode of cpu0
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 32 ++++++++++++++++++++++++--------
- 1 file changed, 24 insertions(+), 8 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -34,19 +34,27 @@
-               cpu@0 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a7";
--                      enable-method = "qcom,kpss-acc-v1";
-+                      enable-method = "qcom,kpss-acc-v2";
-+                      next-level-cache = <&L2>;
-                       qcom,acc = <&acc0>;
-                       qcom,saw = <&saw0>;
-                       reg = <0x0>;
-                       clocks = <&gcc GCC_APPS_CLK_SRC>;
-                       clock-frequency = <0>;
-                       operating-points-v2 = <&cpu0_opp_table>;
-+
-+                      L2: l2-cache {
-+                              compatible = "qcom,arch-cache";
-+                              cache-level = <2>;
-+                              qcom,saw = <&saw_l2>;
-+                      };
-               };
-               cpu@1 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a7";
--                      enable-method = "qcom,kpss-acc-v1";
-+                      enable-method = "qcom,kpss-acc-v2";
-+                      next-level-cache = <&L2>;
-                       qcom,acc = <&acc1>;
-                       qcom,saw = <&saw1>;
-                       reg = <0x1>;
-@@ -58,7 +66,8 @@
-               cpu@2 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a7";
--                      enable-method = "qcom,kpss-acc-v1";
-+                      enable-method = "qcom,kpss-acc-v2";
-+                      next-level-cache = <&L2>;
-                       qcom,acc = <&acc2>;
-                       qcom,saw = <&saw2>;
-                       reg = <0x2>;
-@@ -70,7 +79,8 @@
-               cpu@3 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a7";
--                      enable-method = "qcom,kpss-acc-v1";
-+                      enable-method = "qcom,kpss-acc-v2";
-+                      next-level-cache = <&L2>;
-                       qcom,acc = <&acc3>;
-                       qcom,saw = <&saw3>;
-                       reg = <0x3>;
-@@ -212,22 +222,22 @@
-               };
-                 acc0: clock-controller@b088000 {
--                        compatible = "qcom,kpss-acc-v1";
-+                        compatible = "qcom,kpss-acc-v2";
-                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
-                 };
-                 acc1: clock-controller@b098000 {
--                        compatible = "qcom,kpss-acc-v1";
-+                        compatible = "qcom,kpss-acc-v2";
-                         reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
-                 };
-                 acc2: clock-controller@b0a8000 {
--                        compatible = "qcom,kpss-acc-v1";
-+                        compatible = "qcom,kpss-acc-v2";
-                         reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
-                 };
-                 acc3: clock-controller@b0b8000 {
--                        compatible = "qcom,kpss-acc-v1";
-+                        compatible = "qcom,kpss-acc-v2";
-                         reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
-                 };
-@@ -255,6 +265,12 @@
-                         regulator;
-                 };
-+              saw_l2: regulator@b012000 {
-+                      compatible = "qcom,saw2";
-+                      reg = <0xb012000 0x1000>;
-+                      regulator;
-+              };
-+
-               serial@78af000 {
-                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-                       reg = <0x78af000 0x200>;
diff --git a/target/linux/ipq806x/patches-4.9/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch b/target/linux/ipq806x/patches-4.9/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch
deleted file mode 100644 (file)
index 3c3fc98..0000000
+++ /dev/null
@@ -1,130 +0,0 @@
-From ea5f4d6f4716f3a0bb4fc3614b7a0e8c0df1cb81 Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Thu, 17 Mar 2016 16:22:28 -0500
-Subject: [PATCH] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree
-
-This adds the SoC nodes to the ipq4019 device tree and
-enable it for the DK01.1 board.
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
-Changes:
-       - replaced space with tab
-       - added sleep and mock_utmi clocks
-       - added registers for usb2 and usb3 parent node
-       - changed compatible to qca,ipa4019-dwc3
-       - updated usb2 and usb3 names
-         (included the reg - in case they become necessary later)
----
- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
- arch/arm/boot/dts/qcom-ipq4019.dtsi           | 71 +++++++++++++++++++++++++++
- 2 files changed, 91 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-@@ -108,5 +108,25 @@
-               watchdog@b017000 {
-                       status = "ok";
-               };
-+
-+              usb3_ss_phy: ssphy@9a000 {
-+                      status = "ok";
-+              };
-+
-+              usb3_hs_phy: hsphy@a6000 {
-+                      status = "ok";
-+              };
-+
-+              usb3: usb3@8af8800 {
-+                      status = "ok";
-+              };
-+
-+              usb2_hs_phy: hsphy@a8000 {
-+                      status = "ok";
-+              };
-+
-+              usb2: usb2@60f8800 {
-+                      status = "ok";
-+              };
-       };
- };
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -307,5 +307,76 @@
-                       compatible = "qcom,pshold";
-                       reg = <0x4ab000 0x4>;
-               };
-+
-+              usb3_ss_phy: ssphy@9a000 {
-+                      compatible = "qca,uni-ssphy";
-+                      reg = <0x9a000 0x800>;
-+                      reg-names = "phy_base";
-+                      resets = <&gcc USB3_UNIPHY_PHY_ARES>;
-+                      reset-names = "por_rst";
-+                      status = "disabled";
-+              };
-+
-+              usb3_hs_phy: hsphy@a6000 {
-+                      compatible = "qca,baldur-usb3-hsphy";
-+                      reg = <0xa6000 0x40>;
-+                      reg-names = "phy_base";
-+                      resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
-+                      reset-names = "por_rst", "srif_rst";
-+                      status = "disabled";
-+              };
-+
-+              usb3@8af8800 {
-+                      compatible = "qca,ipq4019-dwc3";
-+                      reg = <0x8af8800 0x100>;
-+                      #address-cells = <1>;
-+                      #size-cells = <1>;
-+                      clocks = <&gcc GCC_USB3_MASTER_CLK>,
-+                               <&gcc GCC_USB3_SLEEP_CLK>,
-+                               <&gcc GCC_USB3_MOCK_UTMI_CLK>;
-+                      clock-names = "master", "sleep", "mock_utmi";
-+                      ranges;
-+                      status = "disabled";
-+
-+                      dwc3@8a00000 {
-+                              compatible = "snps,dwc3";
-+                              reg = <0x8a00000 0xf8000>;
-+                              interrupts = <0 132 0>;
-+                              usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
-+                              phy-names = "usb2-phy", "usb3-phy";
-+                              dr_mode = "host";
-+                      };
-+              };
-+
-+              usb2_hs_phy: hsphy@a8000 {
-+                      compatible = "qca,baldur-usb2-hsphy";
-+                      reg = <0xa8000 0x40>;
-+                      reg-names = "phy_base";
-+                      resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
-+                      reset-names = "por_rst", "srif_rst";
-+                      status = "disabled";
-+              };
-+
-+              usb2@60f8800 {
-+                      compatible = "qca,ipq4019-dwc3";
-+                      reg = <0x60f8800 0x100>;
-+                      #address-cells = <1>;
-+                      #size-cells = <1>;
-+                      clocks = <&gcc GCC_USB2_MASTER_CLK>,
-+                               <&gcc GCC_USB2_SLEEP_CLK>,
-+                               <&gcc GCC_USB2_MOCK_UTMI_CLK>;
-+                      clock-names = "master", "sleep", "mock_utmi";
-+                      ranges;
-+                      status = "disabled";
-+
-+                      dwc3@6000000 {
-+                              compatible = "snps,dwc3";
-+                              reg = <0x6000000 0xf8000>;
-+                              interrupts = <0 136 0>;
-+                              usb-phy = <&usb2_hs_phy>;
-+                              phy-names = "usb2-phy";
-+                              dr_mode = "host";
-+                      };
-+              };
-       };
- };
diff --git a/target/linux/ipq806x/patches-4.9/307-ARM-qcom-Add-IPQ4019-SoC-support.patch b/target/linux/ipq806x/patches-4.9/307-ARM-qcom-Add-IPQ4019-SoC-support.patch
deleted file mode 100644 (file)
index 4cbcc0a..0000000
+++ /dev/null
@@ -1,35 +0,0 @@
-From e7748d641ae37081e2034869491f1629461ae13c Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sat, 19 Nov 2016 00:58:18 +0100
-Subject: [PATCH] ARM: qcom: Add IPQ4019 SoC support
-
-Add support for the Qualcomm Atheros IPQ4019 SoC.
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
- arch/arm/Makefile          | 1 +
- arch/arm/mach-qcom/Kconfig | 5 +++++
- 2 files changed, 6 insertions(+)
-
---- a/arch/arm/Makefile
-+++ b/arch/arm/Makefile
-@@ -147,6 +147,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
- endif
- textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
- textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
-+textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
- textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
- # Machine directory name.  This list is sorted alphanumerically
---- a/arch/arm/mach-qcom/Kconfig
-+++ b/arch/arm/mach-qcom/Kconfig
-@@ -28,4 +28,9 @@ config ARCH_MDM9615
-       bool "Enable support for MDM9615"
-       select CLKSRC_QCOM
-+config ARCH_IPQ40XX
-+      bool "Enable support for IPQ40XX"
-+      select CLKSRC_QCOM
-+      select HAVE_ARM_ARCH_TIMER
-+
- endif
diff --git a/target/linux/ipq806x/patches-4.9/308-dts-ipq4019-add-both-IPQ4019-wifi-block-definitions.patch b/target/linux/ipq806x/patches-4.9/308-dts-ipq4019-add-both-IPQ4019-wifi-block-definitions.patch
deleted file mode 100644 (file)
index d12ca4b..0000000
+++ /dev/null
@@ -1,105 +0,0 @@
-From 6091a49b0b06bf838fed80498c4f5f40d0fbd447 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sat, 19 Nov 2016 01:22:46 +0100
-Subject: [PATCH] dts: ipq4019: add both IPQ4019 wifi block definitions
-
-The IPQ4019 has two ath10k blocks on the AHB. Both wifi's
-are already supported by ath10k.
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 84 +++++++++++++++++++++++++++++++++++++
- 1 file changed, 84 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -378,5 +378,89 @@
-                               dr_mode = "host";
-                       };
-               };
-+
-+              wifi0: wifi@a000000 {
-+                      compatible = "qcom,ipq4019-wifi";
-+                      reg = <0xa000000 0x200000>;
-+                      resets = <&gcc WIFI0_CPU_INIT_RESET
-+                                &gcc WIFI0_RADIO_SRIF_RESET
-+                                &gcc WIFI0_RADIO_WARM_RESET
-+                                &gcc WIFI0_RADIO_COLD_RESET
-+                                &gcc WIFI0_CORE_WARM_RESET
-+                                &gcc WIFI0_CORE_COLD_RESET>;
-+                      reset-names = "wifi_cpu_init", "wifi_radio_srif",
-+                                    "wifi_radio_warm", "wifi_radio_cold",
-+                                    "wifi_core_warm", "wifi_core_cold";
-+                      clocks = <&gcc GCC_WCSS2G_CLK
-+                                &gcc GCC_WCSS2G_REF_CLK
-+                                &gcc GCC_WCSS2G_RTC_CLK>;
-+                      clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
-+                                    "wifi_wcss_rtc";
-+                      interrupts = <0 32 IRQ_TYPE_EDGE_RISING
-+                                    0 33 IRQ_TYPE_EDGE_RISING
-+                                    0 34 IRQ_TYPE_EDGE_RISING
-+                                    0 35 IRQ_TYPE_EDGE_RISING
-+                                    0 36 IRQ_TYPE_EDGE_RISING
-+                                    0 37 IRQ_TYPE_EDGE_RISING
-+                                    0 38 IRQ_TYPE_EDGE_RISING
-+                                    0 39 IRQ_TYPE_EDGE_RISING
-+                                    0 40 IRQ_TYPE_EDGE_RISING
-+                                    0 41 IRQ_TYPE_EDGE_RISING
-+                                    0 42 IRQ_TYPE_EDGE_RISING
-+                                    0 43 IRQ_TYPE_EDGE_RISING
-+                                    0 44 IRQ_TYPE_EDGE_RISING
-+                                    0 45 IRQ_TYPE_EDGE_RISING
-+                                    0 46 IRQ_TYPE_EDGE_RISING
-+                                    0 47 IRQ_TYPE_EDGE_RISING
-+                                    0 168 IRQ_TYPE_NONE>;
-+                      interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
-+                                         "msi4",  "msi5",  "msi6",  "msi7",
-+                                         "msi8",  "msi9", "msi10", "msi11",
-+                                        "msi12", "msi13", "msi14", "msi15",
-+                                        "legacy";
-+                      status = "disabled";
-+              };
-+
-+              wifi1: wifi@a800000 {
-+                      compatible = "qcom,ipq4019-wifi";
-+                      reg = <0xa800000 0x200000>;
-+                      resets = <&gcc WIFI1_CPU_INIT_RESET
-+                                &gcc WIFI1_RADIO_SRIF_RESET
-+                                &gcc WIFI1_RADIO_WARM_RESET
-+                                &gcc WIFI1_RADIO_COLD_RESET
-+                                &gcc WIFI1_CORE_WARM_RESET
-+                                &gcc WIFI1_CORE_COLD_RESET>;
-+                      reset-names = "wifi_cpu_init", "wifi_radio_srif",
-+                                    "wifi_radio_warm", "wifi_radio_cold",
-+                                    "wifi_core_warm", "wifi_core_cold";
-+                      clocks = <&gcc GCC_WCSS5G_CLK
-+                                &gcc GCC_WCSS5G_REF_CLK
-+                                &gcc GCC_WCSS5G_RTC_CLK>;
-+                      clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
-+                                    "wifi_wcss_rtc";
-+                      interrupts = <0 48 IRQ_TYPE_EDGE_RISING
-+                                    0 49 IRQ_TYPE_EDGE_RISING
-+                                    0 50 IRQ_TYPE_EDGE_RISING
-+                                    0 51 IRQ_TYPE_EDGE_RISING
-+                                    0 52 IRQ_TYPE_EDGE_RISING
-+                                    0 53 IRQ_TYPE_EDGE_RISING
-+                                    0 54 IRQ_TYPE_EDGE_RISING
-+                                    0 55 IRQ_TYPE_EDGE_RISING
-+                                    0 56 IRQ_TYPE_EDGE_RISING
-+                                    0 57 IRQ_TYPE_EDGE_RISING
-+                                    0 58 IRQ_TYPE_EDGE_RISING
-+                                    0 59 IRQ_TYPE_EDGE_RISING
-+                                    0 60 IRQ_TYPE_EDGE_RISING
-+                                    0 61 IRQ_TYPE_EDGE_RISING
-+                                    0 62 IRQ_TYPE_EDGE_RISING
-+                                    0 63 IRQ_TYPE_EDGE_RISING
-+                                    0 169 IRQ_TYPE_NONE>;
-+                      interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
-+                                         "msi4",  "msi5",  "msi6",  "msi7",
-+                                         "msi8",  "msi9", "msi10", "msi11",
-+                                        "msi12", "msi13", "msi14", "msi15",
-+                                        "legacy";
-+                      status = "disabled";
-+              };
-       };
- };
diff --git a/target/linux/ipq806x/patches-4.9/309-dts-ipq4019-add-pseudo-random-number-generator.patch b/target/linux/ipq806x/patches-4.9/309-dts-ipq4019-add-pseudo-random-number-generator.patch
deleted file mode 100644 (file)
index abcbb6e..0000000
+++ /dev/null
@@ -1,29 +0,0 @@
-From 26fa6fdc627b523277c7a79907233596b2f8a3ef Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sat, 19 Nov 2016 03:29:04 +0100
-Subject: [PATCH] dts: ipq4019: add pseudo random number generator
-
-This architecture has a pseudo random number generator
-supported by the existing "qcom,prng" binding.
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -271,6 +271,13 @@
-                       regulator;
-               };
-+              rng@22000 {
-+                      compatible = "qcom,prng";
-+                      reg = <0x22000 0x140>;
-+                      clocks = <&gcc GCC_PRNG_AHB_CLK>;
-+                      clock-names = "core";
-+              };
-+
-               serial@78af000 {
-                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-                       reg = <0x78af000 0x200>;
diff --git a/target/linux/ipq806x/patches-4.9/605-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch b/target/linux/ipq806x/patches-4.9/605-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch
deleted file mode 100644 (file)
index d272187..0000000
+++ /dev/null
@@ -1,53 +0,0 @@
-From 7c129254adb1093d10a62ed7bf7b956fcc6ffe34 Mon Sep 17 00:00:00 2001
-From: Rakesh Nair <ranair@codeaurora.org>
-Date: Wed, 20 Jul 2016 15:02:01 +0530
-Subject: [PATCH] net: IPQ4019 needs rfs/vlan_tag callbacks in
- netdev_ops
-
-Add callback support to get default vlan tag and register
-receive flow steering filter.
-
-Used by IPQ4019 ess-edma driver.
-
-BUG=chrome-os-partner:33096
-TEST=none
-
-Change-Id: I266070e4a0fbe4a0d9966fe79a71e50ec4f26c75
-Signed-off-by: Rakesh Nair <ranair@codeaurora.org>
-Reviewed-on: https://chromium-review.googlesource.com/362203
-Commit-Ready: Grant Grundler <grundler@chromium.org>
-Tested-by: Grant Grundler <grundler@chromium.org>
-Reviewed-by: Grant Grundler <grundler@chromium.org>
----
- include/linux/netdevice.h | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/include/linux/netdevice.h
-+++ b/include/linux/netdevice.h
-@@ -725,6 +725,16 @@ struct xps_map {
- #define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \
-        - sizeof(struct xps_map)) / sizeof(u16))
-+#ifdef CONFIG_RFS_ACCEL
-+typedef int (*set_rfs_filter_callback_t)(struct net_device *dev,
-+                                     __be32 src,
-+                                     __be32 dst,
-+                                     __be16 sport,
-+                                     __be16 dport,
-+                                     u8 proto,
-+                                     u16 rxq_index,
-+                                     u32 action);
-+#endif
- /*
-  * This structure holds all XPS maps for device.  Maps are indexed by CPU.
-  */
-@@ -1251,6 +1261,9 @@ struct net_device_ops {
-                                                    const struct sk_buff *skb,
-                                                    u16 rxq_index,
-                                                    u32 flow_id);
-+        int                     (*ndo_register_rfs_filter)(struct net_device *dev,
-+                                                              set_rfs_filter_callback_t set_filter);
-+        int                     (*ndo_get_default_vlan_tag)(struct net_device *net);
- #endif
-       int                     (*ndo_add_slave)(struct net_device *dev,
-                                                struct net_device *slave_dev);
diff --git a/target/linux/ipq806x/patches-4.9/700-net-add-qualcomm-mdio-and-phy.patch b/target/linux/ipq806x/patches-4.9/700-net-add-qualcomm-mdio-and-phy.patch
deleted file mode 100644 (file)
index 0035243..0000000
+++ /dev/null
@@ -1,2690 +0,0 @@
-From 5a71a2005a2e1e6bbe36f00386c495ad6626beb2 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@googlemail.com>
-Date: Thu, 19 Jan 2017 01:59:43 +0100
-Subject: [PATCH 30/38] NET: add qualcomm mdio and PHY
-
----
- drivers/net/phy/Kconfig  | 14 ++++++++++++++
- drivers/net/phy/Makefile |  2 ++
- 2 files changed, 16 insertions(+)
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -408,6 +408,20 @@ config XILINX_GMII2RGMII
-          the Reduced Gigabit Media Independent Interface(RGMII) between
-          Ethernet physical media devices and the Gigabit Ethernet controller.
-+config MDIO_IPQ40XX
-+      tristate "Qualcomm Atheros ipq40xx MDIO interface"
-+      depends on HAS_IOMEM && OF
-+      ---help---
-+        This driver supports the MDIO interface found in Qualcomm
-+        Atheros ipq40xx Soc chip.
-+
-+config AR40XX_PHY
-+      tristate "Driver for Qualcomm Atheros IPQ40XX switches"
-+      depends on HAS_IOMEM && OF
-+      select SWCONFIG
-+      ---help---
-+         This is the driver for Qualcomm Atheros IPQ40XX ESS switches.
-+
- endif # PHYLIB
- config MICREL_KS8995MA
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -32,6 +32,7 @@ obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += md
- obj-$(CONFIG_MDIO_CAVIUM)     += mdio-cavium.o
- obj-$(CONFIG_MDIO_GPIO)               += mdio-gpio.o
- obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
-+obj-$(CONFIG_MDIO_IPQ40XX)    += mdio-ipq40xx.o
- obj-$(CONFIG_MDIO_MOXART)     += mdio-moxart.o
- obj-$(CONFIG_MDIO_OCTEON)     += mdio-octeon.o
- obj-$(CONFIG_MDIO_SUN4I)      += mdio-sun4i.o
-@@ -40,6 +41,7 @@ obj-$(CONFIG_MDIO_XGENE)     += mdio-xgene.o
- obj-$(CONFIG_AMD_PHY)         += amd.o
- obj-$(CONFIG_AQUANTIA_PHY)    += aquantia.o
-+obj-$(CONFIG_AR40XX_PHY)      += ar40xx.o
- obj-$(CONFIG_AT803X_PHY)      += at803x.o
- obj-$(CONFIG_BCM63XX_PHY)     += bcm63xx.o
- obj-$(CONFIG_BCM7XXX_PHY)     += bcm7xxx.o
---- /dev/null
-+++ b/drivers/net/phy/ar40xx.c
-@@ -0,0 +1,2090 @@
-+/*
-+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for
-+ * any purpose with or without fee is hereby granted, provided that the
-+ * above copyright notice and this permission notice appear in all copies.
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
-+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/list.h>
-+#include <linux/bitops.h>
-+#include <linux/switch.h>
-+#include <linux/delay.h>
-+#include <linux/phy.h>
-+#include <linux/clk.h>
-+#include <linux/reset.h>
-+#include <linux/lockdep.h>
-+#include <linux/workqueue.h>
-+#include <linux/of_device.h>
-+#include <linux/of_address.h>
-+#include <linux/mdio.h>
-+#include <linux/gpio.h>
-+
-+#include "ar40xx.h"
-+
-+static struct ar40xx_priv *ar40xx_priv;
-+
-+#define MIB_DESC(_s , _o, _n) \
-+      {                       \
-+              .size = (_s),   \
-+              .offset = (_o), \
-+              .name = (_n),   \
-+      }
-+
-+static const struct ar40xx_mib_desc ar40xx_mibs[] = {
-+      MIB_DESC(1, AR40XX_STATS_RXBROAD, "RxBroad"),
-+      MIB_DESC(1, AR40XX_STATS_RXPAUSE, "RxPause"),
-+      MIB_DESC(1, AR40XX_STATS_RXMULTI, "RxMulti"),
-+      MIB_DESC(1, AR40XX_STATS_RXFCSERR, "RxFcsErr"),
-+      MIB_DESC(1, AR40XX_STATS_RXALIGNERR, "RxAlignErr"),
-+      MIB_DESC(1, AR40XX_STATS_RXRUNT, "RxRunt"),
-+      MIB_DESC(1, AR40XX_STATS_RXFRAGMENT, "RxFragment"),
-+      MIB_DESC(1, AR40XX_STATS_RX64BYTE, "Rx64Byte"),
-+      MIB_DESC(1, AR40XX_STATS_RX128BYTE, "Rx128Byte"),
-+      MIB_DESC(1, AR40XX_STATS_RX256BYTE, "Rx256Byte"),
-+      MIB_DESC(1, AR40XX_STATS_RX512BYTE, "Rx512Byte"),
-+      MIB_DESC(1, AR40XX_STATS_RX1024BYTE, "Rx1024Byte"),
-+      MIB_DESC(1, AR40XX_STATS_RX1518BYTE, "Rx1518Byte"),
-+      MIB_DESC(1, AR40XX_STATS_RXMAXBYTE, "RxMaxByte"),
-+      MIB_DESC(1, AR40XX_STATS_RXTOOLONG, "RxTooLong"),
-+      MIB_DESC(2, AR40XX_STATS_RXGOODBYTE, "RxGoodByte"),
-+      MIB_DESC(2, AR40XX_STATS_RXBADBYTE, "RxBadByte"),
-+      MIB_DESC(1, AR40XX_STATS_RXOVERFLOW, "RxOverFlow"),
-+      MIB_DESC(1, AR40XX_STATS_FILTERED, "Filtered"),
-+      MIB_DESC(1, AR40XX_STATS_TXBROAD, "TxBroad"),
-+      MIB_DESC(1, AR40XX_STATS_TXPAUSE, "TxPause"),
-+      MIB_DESC(1, AR40XX_STATS_TXMULTI, "TxMulti"),
-+      MIB_DESC(1, AR40XX_STATS_TXUNDERRUN, "TxUnderRun"),
-+      MIB_DESC(1, AR40XX_STATS_TX64BYTE, "Tx64Byte"),
-+      MIB_DESC(1, AR40XX_STATS_TX128BYTE, "Tx128Byte"),
-+      MIB_DESC(1, AR40XX_STATS_TX256BYTE, "Tx256Byte"),
-+      MIB_DESC(1, AR40XX_STATS_TX512BYTE, "Tx512Byte"),
-+      MIB_DESC(1, AR40XX_STATS_TX1024BYTE, "Tx1024Byte"),
-+      MIB_DESC(1, AR40XX_STATS_TX1518BYTE, "Tx1518Byte"),
-+      MIB_DESC(1, AR40XX_STATS_TXMAXBYTE, "TxMaxByte"),
-+      MIB_DESC(1, AR40XX_STATS_TXOVERSIZE, "TxOverSize"),
-+      MIB_DESC(2, AR40XX_STATS_TXBYTE, "TxByte"),
-+      MIB_DESC(1, AR40XX_STATS_TXCOLLISION, "TxCollision"),
-+      MIB_DESC(1, AR40XX_STATS_TXABORTCOL, "TxAbortCol"),
-+      MIB_DESC(1, AR40XX_STATS_TXMULTICOL, "TxMultiCol"),
-+      MIB_DESC(1, AR40XX_STATS_TXSINGLECOL, "TxSingleCol"),
-+      MIB_DESC(1, AR40XX_STATS_TXEXCDEFER, "TxExcDefer"),
-+      MIB_DESC(1, AR40XX_STATS_TXDEFER, "TxDefer"),
-+      MIB_DESC(1, AR40XX_STATS_TXLATECOL, "TxLateCol"),
-+};
-+
-+static u32
-+ar40xx_read(struct ar40xx_priv *priv, int reg)
-+{
-+      return readl(priv->hw_addr + reg);
-+}
-+
-+static u32
-+ar40xx_psgmii_read(struct ar40xx_priv *priv, int reg)
-+{
-+      return readl(priv->psgmii_hw_addr + reg);
-+}
-+
-+static void
-+ar40xx_write(struct ar40xx_priv *priv, int reg, u32 val)
-+{
-+      writel(val, priv->hw_addr + reg);
-+}
-+
-+static u32
-+ar40xx_rmw(struct ar40xx_priv *priv, int reg, u32 mask, u32 val)
-+{
-+      u32 ret;
-+
-+      ret = ar40xx_read(priv, reg);
-+      ret &= ~mask;
-+      ret |= val;
-+      ar40xx_write(priv, reg, ret);
-+      return ret;
-+}
-+
-+static void
-+ar40xx_psgmii_write(struct ar40xx_priv *priv, int reg, u32 val)
-+{
-+      writel(val, priv->psgmii_hw_addr + reg);
-+}
-+
-+static void
-+ar40xx_phy_dbg_write(struct ar40xx_priv *priv, int phy_addr,
-+                   u16 dbg_addr, u16 dbg_data)
-+{
-+      struct mii_bus *bus = priv->mii_bus;
-+
-+      mutex_lock(&bus->mdio_lock);
-+      bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_ADDR, dbg_addr);
-+      bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_DATA, dbg_data);
-+      mutex_unlock(&bus->mdio_lock);
-+}
-+
-+static void
-+ar40xx_phy_dbg_read(struct ar40xx_priv *priv, int phy_addr,
-+                  u16 dbg_addr, u16 *dbg_data)
-+{
-+      struct mii_bus *bus = priv->mii_bus;
-+
-+      mutex_lock(&bus->mdio_lock);
-+      bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_ADDR, dbg_addr);
-+      *dbg_data = bus->read(bus, phy_addr, AR40XX_MII_ATH_DBG_DATA);
-+      mutex_unlock(&bus->mdio_lock);
-+}
-+
-+static void
-+ar40xx_phy_mmd_write(struct ar40xx_priv *priv, u32 phy_id,
-+                   u16 mmd_num, u16 reg_id, u16 reg_val)
-+{
-+      struct mii_bus *bus = priv->mii_bus;
-+
-+      mutex_lock(&bus->mdio_lock);
-+      bus->write(bus, phy_id,
-+                      AR40XX_MII_ATH_MMD_ADDR, mmd_num);
-+      bus->write(bus, phy_id,
-+                      AR40XX_MII_ATH_MMD_DATA, reg_id);
-+      bus->write(bus, phy_id,
-+                      AR40XX_MII_ATH_MMD_ADDR,
-+                      0x4000 | mmd_num);
-+      bus->write(bus, phy_id,
-+              AR40XX_MII_ATH_MMD_DATA, reg_val);
-+      mutex_unlock(&bus->mdio_lock);
-+}
-+
-+static u16
-+ar40xx_phy_mmd_read(struct ar40xx_priv *priv, u32 phy_id,
-+                  u16 mmd_num, u16 reg_id)
-+{
-+      u16 value;
-+      struct mii_bus *bus = priv->mii_bus;
-+
-+      mutex_lock(&bus->mdio_lock);
-+      bus->write(bus, phy_id,
-+                      AR40XX_MII_ATH_MMD_ADDR, mmd_num);
-+      bus->write(bus, phy_id,
-+                      AR40XX_MII_ATH_MMD_DATA, reg_id);
-+      bus->write(bus, phy_id,
-+                      AR40XX_MII_ATH_MMD_ADDR,
-+                      0x4000 | mmd_num);
-+      value = bus->read(bus, phy_id, AR40XX_MII_ATH_MMD_DATA);
-+      mutex_unlock(&bus->mdio_lock);
-+      return value;
-+}
-+
-+/* Start of swconfig support */
-+
-+static void
-+ar40xx_phy_poll_reset(struct ar40xx_priv *priv)
-+{
-+      u32 i, in_reset, retries = 500;
-+      struct mii_bus *bus = priv->mii_bus;
-+
-+      /* Assume RESET was recently issued to some or all of the phys */
-+      in_reset = GENMASK(AR40XX_NUM_PHYS - 1, 0);
-+
-+      while (retries--) {
-+              /* 1ms should be plenty of time.
-+               * 802.3 spec allows for a max wait time of 500ms
-+               */
-+              usleep_range(1000, 2000);
-+
-+              for (i = 0; i < AR40XX_NUM_PHYS; i++) {
-+                      int val;
-+
-+                      /* skip devices which have completed reset */
-+                      if (!(in_reset & BIT(i)))
-+                              continue;
-+
-+                      val = mdiobus_read(bus, i, MII_BMCR);
-+                      if (val < 0)
-+                              continue;
-+
-+                      /* mark when phy is no longer in reset state */
-+                      if (!(val & BMCR_RESET))
-+                              in_reset &= ~BIT(i);
-+              }
-+
-+              if (!in_reset)
-+                      return;
-+      }
-+
-+      dev_warn(&bus->dev, "Failed to reset all phys! (in_reset: 0x%x)\n",
-+               in_reset);
-+}
-+
-+static void
-+ar40xx_phy_init(struct ar40xx_priv *priv)
-+{
-+      int i;
-+      struct mii_bus *bus;
-+      u16 val;
-+
-+      bus = priv->mii_bus;
-+      for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {
-+              ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_0, &val);
-+              val &= ~AR40XX_PHY_MANU_CTRL_EN;
-+              ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_0, val);
-+              mdiobus_write(bus, i,
-+                            MII_ADVERTISE, ADVERTISE_ALL |
-+                            ADVERTISE_PAUSE_CAP |
-+                            ADVERTISE_PAUSE_ASYM);
-+              mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
-+              mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
-+      }
-+
-+      ar40xx_phy_poll_reset(priv);
-+}
-+
-+static void
-+ar40xx_port_phy_linkdown(struct ar40xx_priv *priv)
-+{
-+      struct mii_bus *bus;
-+      int i;
-+      u16 val;
-+
-+      bus = priv->mii_bus;
-+      for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {
-+              mdiobus_write(bus, i, MII_CTRL1000, 0);
-+              mdiobus_write(bus, i, MII_ADVERTISE, 0);
-+              mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
-+              ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_0, &val);
-+              val |= AR40XX_PHY_MANU_CTRL_EN;
-+              ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_0, val);
-+              /* disable transmit */
-+              ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_2, &val);
-+              val &= 0xf00f;
-+              ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_2, val);
-+      }
-+}
-+
-+static void
-+ar40xx_set_mirror_regs(struct ar40xx_priv *priv)
-+{
-+      int port;
-+
-+      /* reset all mirror registers */
-+      ar40xx_rmw(priv, AR40XX_REG_FWD_CTRL0,
-+                 AR40XX_FWD_CTRL0_MIRROR_PORT,
-+                 (0xF << AR40XX_FWD_CTRL0_MIRROR_PORT_S));
-+      for (port = 0; port < AR40XX_NUM_PORTS; port++) {
-+              ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(port),
-+                         AR40XX_PORT_LOOKUP_ING_MIRROR_EN, 0);
-+
-+              ar40xx_rmw(priv, AR40XX_REG_PORT_HOL_CTRL1(port),
-+                         AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN, 0);
-+      }
-+
-+      /* now enable mirroring if necessary */
-+      if (priv->source_port >= AR40XX_NUM_PORTS ||
-+          priv->monitor_port >= AR40XX_NUM_PORTS ||
-+          priv->source_port == priv->monitor_port) {
-+              return;
-+      }
-+
-+      ar40xx_rmw(priv, AR40XX_REG_FWD_CTRL0,
-+                 AR40XX_FWD_CTRL0_MIRROR_PORT,
-+                 (priv->monitor_port << AR40XX_FWD_CTRL0_MIRROR_PORT_S));
-+
-+      if (priv->mirror_rx)
-+              ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(priv->source_port), 0,
-+                         AR40XX_PORT_LOOKUP_ING_MIRROR_EN);
-+
-+      if (priv->mirror_tx)
-+              ar40xx_rmw(priv, AR40XX_REG_PORT_HOL_CTRL1(priv->source_port),
-+                         0, AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN);
-+}
-+
-+static int
-+ar40xx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+      u8 ports = priv->vlan_table[val->port_vlan];
-+      int i;
-+
-+      val->len = 0;
-+      for (i = 0; i < dev->ports; i++) {
-+              struct switch_port *p;
-+
-+              if (!(ports & BIT(i)))
-+                      continue;
-+
-+              p = &val->value.ports[val->len++];
-+              p->id = i;
-+              if ((priv->vlan_tagged & BIT(i)) ||
-+                  (priv->pvid[i] != val->port_vlan))
-+                      p->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
-+              else
-+                      p->flags = 0;
-+      }
-+      return 0;
-+}
-+
-+static int
-+ar40xx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+      u8 *vt = &priv->vlan_table[val->port_vlan];
-+      int i;
-+
-+      *vt = 0;
-+      for (i = 0; i < val->len; i++) {
-+              struct switch_port *p = &val->value.ports[i];
-+
-+              if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) {
-+                      if (val->port_vlan == priv->pvid[p->id])
-+                              priv->vlan_tagged |= BIT(p->id);
-+              } else {
-+                      priv->vlan_tagged &= ~BIT(p->id);
-+                      priv->pvid[p->id] = val->port_vlan;
-+              }
-+
-+              *vt |= BIT(p->id);
-+      }
-+      return 0;
-+}
-+
-+static int
-+ar40xx_reg_wait(struct ar40xx_priv *priv, u32 reg, u32 mask, u32 val,
-+              unsigned timeout)
-+{
-+      int i;
-+
-+      for (i = 0; i < timeout; i++) {
-+              u32 t;
-+
-+              t = ar40xx_read(priv, reg);
-+              if ((t & mask) == val)
-+                      return 0;
-+
-+              usleep_range(1000, 2000);
-+      }
-+
-+      return -ETIMEDOUT;
-+}
-+
-+static int
-+ar40xx_mib_op(struct ar40xx_priv *priv, u32 op)
-+{
-+      int ret;
-+
-+      lockdep_assert_held(&priv->mib_lock);
-+
-+      /* Capture the hardware statistics for all ports */
-+      ar40xx_rmw(priv, AR40XX_REG_MIB_FUNC,
-+                 AR40XX_MIB_FUNC, (op << AR40XX_MIB_FUNC_S));
-+
-+      /* Wait for the capturing to complete. */
-+      ret = ar40xx_reg_wait(priv, AR40XX_REG_MIB_FUNC,
-+                            AR40XX_MIB_BUSY, 0, 10);
-+
-+      return ret;
-+}
-+
-+static void
-+ar40xx_mib_fetch_port_stat(struct ar40xx_priv *priv, int port, bool flush)
-+{
-+      unsigned int base;
-+      u64 *mib_stats;
-+      int i;
-+      u32 num_mibs = ARRAY_SIZE(ar40xx_mibs);
-+
-+      WARN_ON(port >= priv->dev.ports);
-+
-+      lockdep_assert_held(&priv->mib_lock);
-+
-+      base = AR40XX_REG_PORT_STATS_START +
-+             AR40XX_REG_PORT_STATS_LEN * port;
-+
-+      mib_stats = &priv->mib_stats[port * num_mibs];
-+      if (flush) {
-+              u32 len;
-+
-+              len = num_mibs * sizeof(*mib_stats);
-+              memset(mib_stats, 0, len);
-+              return;
-+      }
-+      for (i = 0; i < num_mibs; i++) {
-+              const struct ar40xx_mib_desc *mib;
-+              u64 t;
-+
-+              mib = &ar40xx_mibs[i];
-+              t = ar40xx_read(priv, base + mib->offset);
-+              if (mib->size == 2) {
-+                      u64 hi;
-+
-+                      hi = ar40xx_read(priv, base + mib->offset + 4);
-+                      t |= hi << 32;
-+              }
-+
-+              mib_stats[i] += t;
-+      }
-+}
-+
-+static int
-+ar40xx_mib_capture(struct ar40xx_priv *priv)
-+{
-+      return ar40xx_mib_op(priv, AR40XX_MIB_FUNC_CAPTURE);
-+}
-+
-+static int
-+ar40xx_mib_flush(struct ar40xx_priv *priv)
-+{
-+      return ar40xx_mib_op(priv, AR40XX_MIB_FUNC_FLUSH);
-+}
-+
-+static int
-+ar40xx_sw_set_reset_mibs(struct switch_dev *dev,
-+                       const struct switch_attr *attr,
-+                       struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+      unsigned int len;
-+      int ret;
-+      u32 num_mibs = ARRAY_SIZE(ar40xx_mibs);
-+
-+      mutex_lock(&priv->mib_lock);
-+
-+      len = priv->dev.ports * num_mibs * sizeof(*priv->mib_stats);
-+      memset(priv->mib_stats, 0, len);
-+      ret = ar40xx_mib_flush(priv);
-+
-+      mutex_unlock(&priv->mib_lock);
-+      return ret;
-+}
-+
-+static int
-+ar40xx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
-+                 struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+      priv->vlan = !!val->value.i;
-+      return 0;
-+}
-+
-+static int
-+ar40xx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
-+                 struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+      val->value.i = priv->vlan;
-+      return 0;
-+}
-+
-+static int
-+ar40xx_sw_set_mirror_rx_enable(struct switch_dev *dev,
-+                             const struct switch_attr *attr,
-+                             struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+      mutex_lock(&priv->reg_mutex);
-+      priv->mirror_rx = !!val->value.i;
-+      ar40xx_set_mirror_regs(priv);
-+      mutex_unlock(&priv->reg_mutex);
-+
-+      return 0;
-+}
-+
-+static int
-+ar40xx_sw_get_mirror_rx_enable(struct switch_dev *dev,
-+                             const struct switch_attr *attr,
-+                             struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+      mutex_lock(&priv->reg_mutex);
-+      val->value.i = priv->mirror_rx;
-+      mutex_unlock(&priv->reg_mutex);
-+      return 0;
-+}
-+
-+static int
-+ar40xx_sw_set_mirror_tx_enable(struct switch_dev *dev,
-+                             const struct switch_attr *attr,
-+                             struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+      mutex_lock(&priv->reg_mutex);
-+      priv->mirror_tx = !!val->value.i;
-+      ar40xx_set_mirror_regs(priv);
-+      mutex_unlock(&priv->reg_mutex);
-+
-+      return 0;
-+}
-+
-+static int
-+ar40xx_sw_get_mirror_tx_enable(struct switch_dev *dev,
-+                             const struct switch_attr *attr,
-+                             struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+      mutex_lock(&priv->reg_mutex);
-+      val->value.i = priv->mirror_tx;
-+      mutex_unlock(&priv->reg_mutex);
-+      return 0;
-+}
-+
-+static int
-+ar40xx_sw_set_mirror_monitor_port(struct switch_dev *dev,
-+                                const struct switch_attr *attr,
-+                                struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+      mutex_lock(&priv->reg_mutex);
-+      priv->monitor_port = val->value.i;
-+      ar40xx_set_mirror_regs(priv);
-+      mutex_unlock(&priv->reg_mutex);
-+
-+      return 0;
-+}
-+
-+static int
-+ar40xx_sw_get_mirror_monitor_port(struct switch_dev *dev,
-+                                const struct switch_attr *attr,
-+                                struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+      mutex_lock(&priv->reg_mutex);
-+      val->value.i = priv->monitor_port;
-+      mutex_unlock(&priv->reg_mutex);
-+      return 0;
-+}
-+
-+static int
-+ar40xx_sw_set_mirror_source_port(struct switch_dev *dev,
-+                               const struct switch_attr *attr,
-+                               struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+      mutex_lock(&priv->reg_mutex);
-+      priv->source_port = val->value.i;
-+      ar40xx_set_mirror_regs(priv);
-+      mutex_unlock(&priv->reg_mutex);
-+
-+      return 0;
-+}
-+
-+static int
-+ar40xx_sw_get_mirror_source_port(struct switch_dev *dev,
-+                               const struct switch_attr *attr,
-+                               struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+      mutex_lock(&priv->reg_mutex);
-+      val->value.i = priv->source_port;
-+      mutex_unlock(&priv->reg_mutex);
-+      return 0;
-+}
-+
-+static int
-+ar40xx_sw_set_linkdown(struct switch_dev *dev,
-+                     const struct switch_attr *attr,
-+                     struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+      if (val->value.i == 1)
-+              ar40xx_port_phy_linkdown(priv);
-+      else
-+              ar40xx_phy_init(priv);
-+
-+      return 0;
-+}
-+
-+static int
-+ar40xx_sw_set_port_reset_mib(struct switch_dev *dev,
-+                           const struct switch_attr *attr,
-+                           struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+      int port;
-+      int ret;
-+
-+      port = val->port_vlan;
-+      if (port >= dev->ports)
-+              return -EINVAL;
-+
-+      mutex_lock(&priv->mib_lock);
-+      ret = ar40xx_mib_capture(priv);
-+      if (ret)
-+              goto unlock;
-+
-+      ar40xx_mib_fetch_port_stat(priv, port, true);
-+
-+unlock:
-+      mutex_unlock(&priv->mib_lock);
-+      return ret;
-+}
-+
-+static int
-+ar40xx_sw_get_port_mib(struct switch_dev *dev,
-+                     const struct switch_attr *attr,
-+                     struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+      u64 *mib_stats;
-+      int port;
-+      int ret;
-+      char *buf = priv->buf;
-+      int i, len = 0;
-+      u32 num_mibs = ARRAY_SIZE(ar40xx_mibs);
-+
-+      port = val->port_vlan;
-+      if (port >= dev->ports)
-+              return -EINVAL;
-+
-+      mutex_lock(&priv->mib_lock);
-+      ret = ar40xx_mib_capture(priv);
-+      if (ret)
-+              goto unlock;
-+
-+      ar40xx_mib_fetch_port_stat(priv, port, false);
-+
-+      len += snprintf(buf + len, sizeof(priv->buf) - len,
-+                      "Port %d MIB counters\n",
-+                      port);
-+
-+      mib_stats = &priv->mib_stats[port * num_mibs];
-+      for (i = 0; i < num_mibs; i++)
-+              len += snprintf(buf + len, sizeof(priv->buf) - len,
-+                              "%-12s: %llu\n",
-+                              ar40xx_mibs[i].name,
-+                              mib_stats[i]);
-+
-+      val->value.s = buf;
-+      val->len = len;
-+
-+unlock:
-+      mutex_unlock(&priv->mib_lock);
-+      return ret;
-+}
-+
-+static int
-+ar40xx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
-+                struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+      priv->vlan_id[val->port_vlan] = val->value.i;
-+      return 0;
-+}
-+
-+static int
-+ar40xx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
-+                struct switch_val *val)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+      val->value.i = priv->vlan_id[val->port_vlan];
-+      return 0;
-+}
-+
-+static int
-+ar40xx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+      *vlan = priv->pvid[port];
-+      return 0;
-+}
-+
-+static int
-+ar40xx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+      /* make sure no invalid PVIDs get set */
-+      if (vlan >= dev->vlans)
-+              return -EINVAL;
-+
-+      priv->pvid[port] = vlan;
-+      return 0;
-+}
-+
-+static void
-+ar40xx_read_port_link(struct ar40xx_priv *priv, int port,
-+                    struct switch_port_link *link)
-+{
-+      u32 status;
-+      u32 speed;
-+
-+      memset(link, 0, sizeof(*link));
-+
-+      status = ar40xx_read(priv, AR40XX_REG_PORT_STATUS(port));
-+
-+      link->aneg = !!(status & AR40XX_PORT_AUTO_LINK_EN);
-+      if (link->aneg || (port != AR40XX_PORT_CPU))
-+              link->link = !!(status & AR40XX_PORT_STATUS_LINK_UP);
-+      else
-+              link->link = true;
-+
-+      if (!link->link)
-+              return;
-+
-+      link->duplex = !!(status & AR40XX_PORT_DUPLEX);
-+      link->tx_flow = !!(status & AR40XX_PORT_STATUS_TXFLOW);
-+      link->rx_flow = !!(status & AR40XX_PORT_STATUS_RXFLOW);
-+
-+      speed = (status & AR40XX_PORT_SPEED) >>
-+               AR40XX_PORT_STATUS_SPEED_S;
-+
-+      switch (speed) {
-+      case AR40XX_PORT_SPEED_10M:
-+              link->speed = SWITCH_PORT_SPEED_10;
-+              break;
-+      case AR40XX_PORT_SPEED_100M:
-+              link->speed = SWITCH_PORT_SPEED_100;
-+              break;
-+      case AR40XX_PORT_SPEED_1000M:
-+              link->speed = SWITCH_PORT_SPEED_1000;
-+              break;
-+      default:
-+              link->speed = SWITCH_PORT_SPEED_UNKNOWN;
-+              break;
-+      }
-+}
-+
-+static int
-+ar40xx_sw_get_port_link(struct switch_dev *dev, int port,
-+                      struct switch_port_link *link)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+      ar40xx_read_port_link(priv, port, link);
-+      return 0;
-+}
-+
-+static const struct switch_attr ar40xx_sw_attr_globals[] = {
-+      {
-+              .type = SWITCH_TYPE_INT,
-+              .name = "enable_vlan",
-+              .description = "Enable VLAN mode",
-+              .set = ar40xx_sw_set_vlan,
-+              .get = ar40xx_sw_get_vlan,
-+              .max = 1
-+      },
-+      {
-+              .type = SWITCH_TYPE_NOVAL,
-+              .name = "reset_mibs",
-+              .description = "Reset all MIB counters",
-+              .set = ar40xx_sw_set_reset_mibs,
-+      },
-+      {
-+              .type = SWITCH_TYPE_INT,
-+              .name = "enable_mirror_rx",
-+              .description = "Enable mirroring of RX packets",
-+              .set = ar40xx_sw_set_mirror_rx_enable,
-+              .get = ar40xx_sw_get_mirror_rx_enable,
-+              .max = 1
-+      },
-+      {
-+              .type = SWITCH_TYPE_INT,
-+              .name = "enable_mirror_tx",
-+              .description = "Enable mirroring of TX packets",
-+              .set = ar40xx_sw_set_mirror_tx_enable,
-+              .get = ar40xx_sw_get_mirror_tx_enable,
-+              .max = 1
-+      },
-+      {
-+              .type = SWITCH_TYPE_INT,
-+              .name = "mirror_monitor_port",
-+              .description = "Mirror monitor port",
-+              .set = ar40xx_sw_set_mirror_monitor_port,
-+              .get = ar40xx_sw_get_mirror_monitor_port,
-+              .max = AR40XX_NUM_PORTS - 1
-+      },
-+      {
-+              .type = SWITCH_TYPE_INT,
-+              .name = "mirror_source_port",
-+              .description = "Mirror source port",
-+              .set = ar40xx_sw_set_mirror_source_port,
-+              .get = ar40xx_sw_get_mirror_source_port,
-+              .max = AR40XX_NUM_PORTS - 1
-+      },
-+      {
-+              .type = SWITCH_TYPE_INT,
-+              .name = "linkdown",
-+              .description = "Link down all the PHYs",
-+              .set = ar40xx_sw_set_linkdown,
-+              .max = 1
-+      },
-+};
-+
-+static const struct switch_attr ar40xx_sw_attr_port[] = {
-+      {
-+              .type = SWITCH_TYPE_NOVAL,
-+              .name = "reset_mib",
-+              .description = "Reset single port MIB counters",
-+              .set = ar40xx_sw_set_port_reset_mib,
-+      },
-+      {
-+              .type = SWITCH_TYPE_STRING,
-+              .name = "mib",
-+              .description = "Get port's MIB counters",
-+              .set = NULL,
-+              .get = ar40xx_sw_get_port_mib,
-+      },
-+};
-+
-+const struct switch_attr ar40xx_sw_attr_vlan[] = {
-+      {
-+              .type = SWITCH_TYPE_INT,
-+              .name = "vid",
-+              .description = "VLAN ID (0-4094)",
-+              .set = ar40xx_sw_set_vid,
-+              .get = ar40xx_sw_get_vid,
-+              .max = 4094,
-+      },
-+};
-+
-+/* End of swconfig support */
-+
-+static int
-+ar40xx_wait_bit(struct ar40xx_priv *priv, int reg, u32 mask, u32 val)
-+{
-+      int timeout = 20;
-+      u32 t;
-+
-+      while (1) {
-+              t = ar40xx_read(priv, reg);
-+              if ((t & mask) == val)
-+                      return 0;
-+
-+              if (timeout-- <= 0)
-+                      break;
-+
-+              usleep_range(10, 20);
-+      }
-+
-+      pr_err("ar40xx: timeout for reg %08x: %08x & %08x != %08x\n",
-+             (unsigned int)reg, t, mask, val);
-+      return -ETIMEDOUT;
-+}
-+
-+static int
-+ar40xx_atu_flush(struct ar40xx_priv *priv)
-+{
-+      int ret;
-+
-+      ret = ar40xx_wait_bit(priv, AR40XX_REG_ATU_FUNC,
-+                            AR40XX_ATU_FUNC_BUSY, 0);
-+      if (!ret)
-+              ar40xx_write(priv, AR40XX_REG_ATU_FUNC,
-+                           AR40XX_ATU_FUNC_OP_FLUSH |
-+                           AR40XX_ATU_FUNC_BUSY);
-+
-+      return ret;
-+}
-+
-+static void
-+ar40xx_ess_reset(struct ar40xx_priv *priv)
-+{
-+      reset_control_assert(priv->ess_rst);
-+      mdelay(10);
-+      reset_control_deassert(priv->ess_rst);
-+      /* Waiting for all inner tables init done.
-+        * It cost 5~10ms.
-+        */
-+      mdelay(10);
-+
-+      pr_info("ESS reset ok!\n");
-+}
-+
-+/* Start of psgmii self test */
-+
-+static void
-+ar40xx_malibu_psgmii_ess_reset(struct ar40xx_priv *priv)
-+{
-+      u32 n;
-+      struct mii_bus *bus = priv->mii_bus;
-+      /* reset phy psgmii */
-+      /* fix phy psgmii RX 20bit */
-+      mdiobus_write(bus, 5, 0x0, 0x005b);
-+      /* reset phy psgmii */
-+      mdiobus_write(bus, 5, 0x0, 0x001b);
-+      /* release reset phy psgmii */
-+      mdiobus_write(bus, 5, 0x0, 0x005b);
-+
-+      for (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) {
-+              u16 status;
-+
-+              status = ar40xx_phy_mmd_read(priv, 5, 1, 0x28);
-+              if (status & BIT(0))
-+                      break;
-+              /* Polling interval to check PSGMII PLL in malibu is ready
-+                * the worst time is 8.67ms
-+                * for 25MHz reference clock
-+                * [512+(128+2048)*49]*80ns+100us
-+                */
-+              mdelay(2);
-+      }
-+
-+      /*check malibu psgmii calibration done end..*/
-+
-+      /*freeze phy psgmii RX CDR*/
-+      mdiobus_write(bus, 5, 0x1a, 0x2230);
-+
-+      ar40xx_ess_reset(priv);
-+
-+      /*check psgmii calibration done start*/
-+      for (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) {
-+              u32 status;
-+
-+              status = ar40xx_psgmii_read(priv, 0xa0);
-+              if (status & BIT(0))
-+                      break;
-+              /* Polling interval to check PSGMII PLL in ESS is ready */
-+              mdelay(2);
-+      }
-+
-+      /* check dakota psgmii calibration done end..*/
-+
-+      /* relesae phy psgmii RX CDR */
-+      mdiobus_write(bus, 5, 0x1a, 0x3230);
-+      /* release phy psgmii RX 20bit */
-+      mdiobus_write(bus, 5, 0x0, 0x005f);
-+}
-+
-+static void
-+ar40xx_psgmii_single_phy_testing(struct ar40xx_priv *priv, int phy)
-+{
-+      int j;
-+      u32 tx_ok, tx_error;
-+      u32 rx_ok, rx_error;
-+      u32 tx_ok_high16;
-+      u32 rx_ok_high16;
-+      u32 tx_all_ok, rx_all_ok;
-+      struct mii_bus *bus = priv->mii_bus;
-+
-+      mdiobus_write(bus, phy, 0x0, 0x9000);
-+      mdiobus_write(bus, phy, 0x0, 0x4140);
-+
-+      for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {
-+              u16 status;
-+
-+              status = mdiobus_read(bus, phy, 0x11);
-+              if (status & AR40XX_PHY_SPEC_STATUS_LINK)
-+                      break;
-+              /* the polling interval to check if the PHY link up or not
-+                * maxwait_timer: 750 ms +/-10 ms
-+                * minwait_timer : 1 us +/- 0.1us
-+                * time resides in minwait_timer ~ maxwait_timer
-+                * see IEEE 802.3 section 40.4.5.2
-+                */
-+              mdelay(8);
-+      }
-+
-+      /* enable check */
-+      ar40xx_phy_mmd_write(priv, phy, 7, 0x8029, 0x0000);
-+      ar40xx_phy_mmd_write(priv, phy, 7, 0x8029, 0x0003);
-+
-+      /* start traffic */
-+      ar40xx_phy_mmd_write(priv, phy, 7, 0x8020, 0xa000);
-+      /* wait for all traffic end
-+        * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms
-+        */
-+      mdelay(50);
-+
-+      /* check counter */
-+      tx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802e);
-+      tx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802d);
-+      tx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802f);
-+      rx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802b);
-+      rx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802a);
-+      rx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802c);
-+      tx_all_ok = tx_ok + (tx_ok_high16 << 16);
-+      rx_all_ok = rx_ok + (rx_ok_high16 << 16);
-+      if (tx_all_ok == 0x1000 && tx_error == 0) {
-+              /* success */
-+              priv->phy_t_status &= (~BIT(phy));
-+      } else {
-+              pr_info("PHY %d single test PSGMII issue happen!\n", phy);
-+              priv->phy_t_status |= BIT(phy);
-+      }
-+
-+      mdiobus_write(bus, phy, 0x0, 0x1840);
-+}
-+
-+static void
-+ar40xx_psgmii_all_phy_testing(struct ar40xx_priv *priv)
-+{
-+      int phy, j;
-+      struct mii_bus *bus = priv->mii_bus;
-+
-+      mdiobus_write(bus, 0x1f, 0x0, 0x9000);
-+      mdiobus_write(bus, 0x1f, 0x0, 0x4140);
-+
-+      for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {
-+              for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
-+                      u16 status;
-+
-+                      status = mdiobus_read(bus, phy, 0x11);
-+                      if (!(status & BIT(10)))
-+                              break;
-+              }
-+
-+              if (phy >= (AR40XX_NUM_PORTS - 1))
-+                      break;
-+              /* The polling interva to check if the PHY link up or not */
-+              mdelay(8);
-+      }
-+      /* enable check */
-+      ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0000);
-+      ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0003);
-+
-+      /* start traffic */
-+      ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0xa000);
-+      /* wait for all traffic end
-+        * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms
-+        */
-+      mdelay(50);
-+
-+      for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
-+              u32 tx_ok, tx_error;
-+              u32 rx_ok, rx_error;
-+              u32 tx_ok_high16;
-+              u32 rx_ok_high16;
-+              u32 tx_all_ok, rx_all_ok;
-+
-+              /* check counter */
-+              tx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802e);
-+              tx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802d);
-+              tx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802f);
-+              rx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802b);
-+              rx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802a);
-+              rx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802c);
-+              tx_all_ok = tx_ok + (tx_ok_high16<<16);
-+              rx_all_ok = rx_ok + (rx_ok_high16<<16);
-+              if (tx_all_ok == 0x1000 && tx_error == 0) {
-+                      /* success */
-+                      priv->phy_t_status &= ~BIT(phy + 8);
-+              } else {
-+                      pr_info("PHY%d test see issue!\n", phy);
-+                      priv->phy_t_status |= BIT(phy + 8);
-+              }
-+      }
-+
-+      pr_debug("PHY all test 0x%x \r\n", priv->phy_t_status);
-+}
-+
-+void
-+ar40xx_psgmii_self_test(struct ar40xx_priv *priv)
-+{
-+      u32 i, phy;
-+      struct mii_bus *bus = priv->mii_bus;
-+
-+      ar40xx_malibu_psgmii_ess_reset(priv);
-+
-+      /* switch to access MII reg for copper */
-+      mdiobus_write(bus, 4, 0x1f, 0x8500);
-+      for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
-+              /*enable phy mdio broadcast write*/
-+              ar40xx_phy_mmd_write(priv, phy, 7, 0x8028, 0x801f);
-+      }
-+      /* force no link by power down */
-+      mdiobus_write(bus, 0x1f, 0x0, 0x1840);
-+      /*packet number*/
-+      ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x1000);
-+      ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8062, 0x05e0);
-+
-+      /*fix mdi status */
-+      mdiobus_write(bus, 0x1f, 0x10, 0x6800);
-+      for (i = 0; i < AR40XX_PSGMII_CALB_NUM; i++) {
-+              priv->phy_t_status = 0;
-+
-+              for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
-+                      ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1),
-+                              AR40XX_PORT_LOOKUP_LOOPBACK,
-+                              AR40XX_PORT_LOOKUP_LOOPBACK);
-+              }
-+
-+              for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++)
-+                      ar40xx_psgmii_single_phy_testing(priv, phy);
-+
-+              ar40xx_psgmii_all_phy_testing(priv);
-+
-+              if (priv->phy_t_status)
-+                      ar40xx_malibu_psgmii_ess_reset(priv);
-+              else
-+                      break;
-+      }
-+
-+      if (i >= AR40XX_PSGMII_CALB_NUM)
-+              pr_info("PSGMII cannot recover\n");
-+      else
-+              pr_debug("PSGMII recovered after %d times reset\n", i);
-+
-+      /* configuration recover */
-+      /* packet number */
-+      ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x0);
-+      /* disable check */
-+      ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0);
-+      /* disable traffic */
-+      ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0x0);
-+}
-+
-+void
-+ar40xx_psgmii_self_test_clean(struct ar40xx_priv *priv)
-+{
-+      int phy;
-+      struct mii_bus *bus = priv->mii_bus;
-+
-+      /* disable phy internal loopback */
-+      mdiobus_write(bus, 0x1f, 0x10, 0x6860);
-+      mdiobus_write(bus, 0x1f, 0x0, 0x9040);
-+
-+      for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
-+              /* disable mac loop back */
-+              ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1),
-+                              AR40XX_PORT_LOOKUP_LOOPBACK, 0);
-+              /* disable phy mdio broadcast write */
-+              ar40xx_phy_mmd_write(priv, phy, 7, 0x8028, 0x001f);
-+      }
-+
-+      /* clear fdb entry */
-+      ar40xx_atu_flush(priv);
-+}
-+
-+/* End of psgmii self test */
-+
-+static void
-+ar40xx_mac_mode_init(struct ar40xx_priv *priv, u32 mode)
-+{
-+      if (mode == PORT_WRAPPER_PSGMII) {
-+              ar40xx_psgmii_write(priv, AR40XX_PSGMII_MODE_CONTROL, 0x2200);
-+              ar40xx_psgmii_write(priv, AR40XX_PSGMIIPHY_TX_CONTROL, 0x8380);
-+      }
-+}
-+
-+static
-+int ar40xx_cpuport_setup(struct ar40xx_priv *priv)
-+{
-+      u32 t;
-+
-+      t = AR40XX_PORT_STATUS_TXFLOW |
-+           AR40XX_PORT_STATUS_RXFLOW |
-+           AR40XX_PORT_TXHALF_FLOW |
-+           AR40XX_PORT_DUPLEX |
-+           AR40XX_PORT_SPEED_1000M;
-+      ar40xx_write(priv, AR40XX_REG_PORT_STATUS(0), t);
-+      usleep_range(10, 20);
-+
-+      t |= AR40XX_PORT_TX_EN |
-+             AR40XX_PORT_RX_EN;
-+      ar40xx_write(priv, AR40XX_REG_PORT_STATUS(0), t);
-+
-+      return 0;
-+}
-+
-+static void
-+ar40xx_init_port(struct ar40xx_priv *priv, int port)
-+{
-+      u32 t;
-+
-+      ar40xx_rmw(priv, AR40XX_REG_PORT_STATUS(port),
-+                      AR40XX_PORT_AUTO_LINK_EN, 0);
-+
-+      ar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0);
-+
-+      ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), 0);
-+
-+      t = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH << AR40XX_PORT_VLAN1_OUT_MODE_S;
-+      ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t);
-+
-+      t = AR40XX_PORT_LOOKUP_LEARN;
-+      t |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;
-+      ar40xx_write(priv, AR40XX_REG_PORT_LOOKUP(port), t);
-+}
-+
-+void
-+ar40xx_init_globals(struct ar40xx_priv *priv)
-+{
-+      u32 t;
-+
-+      /* enable CPU port and disable mirror port */
-+      t = AR40XX_FWD_CTRL0_CPU_PORT_EN |
-+          AR40XX_FWD_CTRL0_MIRROR_PORT;
-+      ar40xx_write(priv, AR40XX_REG_FWD_CTRL0, t);
-+
-+      /* forward multicast and broadcast frames to CPU */
-+      t = (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_UC_FLOOD_S) |
-+          (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_MC_FLOOD_S) |
-+          (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_BC_FLOOD_S);
-+      ar40xx_write(priv, AR40XX_REG_FWD_CTRL1, t);
-+
-+      /* enable jumbo frames */
-+      ar40xx_rmw(priv, AR40XX_REG_MAX_FRAME_SIZE,
-+                 AR40XX_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
-+
-+      /* Enable MIB counters */
-+      ar40xx_rmw(priv, AR40XX_REG_MODULE_EN, 0,
-+                 AR40XX_MODULE_EN_MIB);
-+
-+      /* Disable AZ */
-+      ar40xx_write(priv, AR40XX_REG_EEE_CTRL, 0);
-+
-+      /* set flowctrl thershold for cpu port */
-+      t = (AR40XX_PORT0_FC_THRESH_ON_DFLT << 16) |
-+            AR40XX_PORT0_FC_THRESH_OFF_DFLT;
-+      ar40xx_write(priv, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), t);
-+}
-+
-+static void
-+ar40xx_malibu_init(struct ar40xx_priv *priv)
-+{
-+      int i;
-+      struct mii_bus *bus;
-+      u16 val;
-+
-+      bus = priv->mii_bus;
-+
-+      /* war to enable AZ transmitting ability */
-+      ar40xx_phy_mmd_write(priv, AR40XX_PSGMII_ID, 1,
-+                           AR40XX_MALIBU_PSGMII_MODE_CTRL,
-+                           AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL);
-+      for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {
-+              /* change malibu control_dac */
-+              val = ar40xx_phy_mmd_read(priv, i, 7,
-+                                        AR40XX_MALIBU_PHY_MMD7_DAC_CTRL);
-+              val &= ~AR40XX_MALIBU_DAC_CTRL_MASK;
-+              val |= AR40XX_MALIBU_DAC_CTRL_VALUE;
-+              ar40xx_phy_mmd_write(priv, i, 7,
-+                                   AR40XX_MALIBU_PHY_MMD7_DAC_CTRL, val);
-+              if (i == AR40XX_MALIBU_PHY_LAST_ADDR) {
-+                      /* to avoid goes into hibernation */
-+                      val = ar40xx_phy_mmd_read(priv, i, 3,
-+                                                AR40XX_MALIBU_PHY_RLP_CTRL);
-+                      val &= (~(1<<1));
-+                      ar40xx_phy_mmd_write(priv, i, 3,
-+                                           AR40XX_MALIBU_PHY_RLP_CTRL, val);
-+              }
-+      }
-+
-+      /* adjust psgmii serdes tx amp */
-+      mdiobus_write(bus, AR40XX_PSGMII_ID, AR40XX_PSGMII_TX_DRIVER_1_CTRL,
-+                    AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP);
-+}
-+
-+static int
-+ar40xx_hw_init(struct ar40xx_priv *priv)
-+{
-+      u32 i;
-+
-+      ar40xx_ess_reset(priv);
-+
-+      if (priv->mii_bus)
-+              ar40xx_malibu_init(priv);
-+      else
-+              return -1;
-+
-+      ar40xx_psgmii_self_test(priv);
-+      ar40xx_psgmii_self_test_clean(priv);
-+
-+      ar40xx_mac_mode_init(priv, priv->mac_mode);
-+
-+      for (i = 0; i < priv->dev.ports; i++)
-+              ar40xx_init_port(priv, i);
-+
-+      ar40xx_init_globals(priv);
-+
-+      return 0;
-+}
-+
-+/* Start of qm error WAR */
-+
-+static
-+int ar40xx_force_1g_full(struct ar40xx_priv *priv, u32 port_id)
-+{
-+      u32 reg;
-+
-+      if (port_id < 0 || port_id > 6)
-+              return -1;
-+
-+      reg = AR40XX_REG_PORT_STATUS(port_id);
-+      return ar40xx_rmw(priv, reg, AR40XX_PORT_SPEED,
-+                      (AR40XX_PORT_SPEED_1000M | AR40XX_PORT_DUPLEX));
-+}
-+
-+static
-+int ar40xx_get_qm_status(struct ar40xx_priv *priv,
-+                       u32 port_id, u32 *qm_buffer_err)
-+{
-+      u32 reg;
-+      u32 qm_val;
-+
-+      if (port_id < 1 || port_id > 5) {
-+              *qm_buffer_err = 0;
-+              return -1;
-+      }
-+
-+      if (port_id < 4) {
-+              reg = AR40XX_REG_QM_PORT0_3_QNUM;
-+              ar40xx_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg);
-+              qm_val = ar40xx_read(priv, AR40XX_REG_QM_DEBUG_VALUE);
-+              /* every 8 bits for each port */
-+              *qm_buffer_err = (qm_val >> (port_id * 8)) & 0xFF;
-+      } else {
-+              reg = AR40XX_REG_QM_PORT4_6_QNUM;
-+              ar40xx_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg);
-+              qm_val = ar40xx_read(priv, AR40XX_REG_QM_DEBUG_VALUE);
-+              /* every 8 bits for each port */
-+              *qm_buffer_err = (qm_val >> ((port_id-4) * 8)) & 0xFF;
-+      }
-+
-+      return 0;
-+}
-+
-+static void
-+ar40xx_sw_mac_polling_task(struct ar40xx_priv *priv)
-+{
-+      static int task_count;
-+      u32 i;
-+      u32 reg, value;
-+      u32 link, speed, duplex;
-+      u32 qm_buffer_err;
-+      u16 port_phy_status[AR40XX_NUM_PORTS];
-+      static u32 qm_err_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0};
-+      static u32 link_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0};
-+      struct mii_bus *bus = NULL;
-+
-+      if (!priv || !priv->mii_bus)
-+              return;
-+
-+      bus = priv->mii_bus;
-+
-+      ++task_count;
-+
-+      for (i = 1; i < AR40XX_NUM_PORTS; ++i) {
-+              port_phy_status[i] =
-+                      mdiobus_read(bus, i-1, AR40XX_PHY_SPEC_STATUS);
-+              speed = link = duplex = port_phy_status[i];
-+              speed &= AR40XX_PHY_SPEC_STATUS_SPEED;
-+              speed >>= 14;
-+              link &= AR40XX_PHY_SPEC_STATUS_LINK;
-+              link >>= 10;
-+              duplex &= AR40XX_PHY_SPEC_STATUS_DUPLEX;
-+              duplex >>= 13;
-+
-+              if (link != priv->ar40xx_port_old_link[i]) {
-+                      ++link_cnt[i];
-+                      /* Up --> Down */
-+                      if ((priv->ar40xx_port_old_link[i] ==
-+                                      AR40XX_PORT_LINK_UP) &&
-+                          (link == AR40XX_PORT_LINK_DOWN)) {
-+                              /* LINK_EN disable(MAC force mode)*/
-+                              reg = AR40XX_REG_PORT_STATUS(i);
-+                              ar40xx_rmw(priv, reg,
-+                                              AR40XX_PORT_AUTO_LINK_EN, 0);
-+
-+                              /* Check queue buffer */
-+                              qm_err_cnt[i] = 0;
-+                              ar40xx_get_qm_status(priv, i, &qm_buffer_err);
-+                              if (qm_buffer_err) {
-+                                      priv->ar40xx_port_qm_buf[i] =
-+                                              AR40XX_QM_NOT_EMPTY;
-+                              } else {
-+                                      u16 phy_val = 0;
-+
-+                                      priv->ar40xx_port_qm_buf[i] =
-+                                              AR40XX_QM_EMPTY;
-+                                      ar40xx_force_1g_full(priv, i);
-+                                      /* Ref:QCA8337 Datasheet,Clearing
-+                                       * MENU_CTRL_EN prevents phy to
-+                                       * stuck in 100BT mode when
-+                                       * bringing up the link
-+                                       */
-+                                      ar40xx_phy_dbg_read(priv, i-1,
-+                                                          AR40XX_PHY_DEBUG_0,
-+                                                          &phy_val);
-+                                      phy_val &= (~AR40XX_PHY_MANU_CTRL_EN);
-+                                      ar40xx_phy_dbg_write(priv, i-1,
-+                                                           AR40XX_PHY_DEBUG_0,
-+                                                           phy_val);
-+                              }
-+                              priv->ar40xx_port_old_link[i] = link;
-+                      } else if ((priv->ar40xx_port_old_link[i] ==
-+                                              AR40XX_PORT_LINK_DOWN) &&
-+                                      (link == AR40XX_PORT_LINK_UP)) {
-+                              /* Down --> Up */
-+                              if (priv->port_link_up[i] < 1) {
-+                                      ++priv->port_link_up[i];
-+                              } else {
-+                                      /* Change port status */
-+                                      reg = AR40XX_REG_PORT_STATUS(i);
-+                                      value = ar40xx_read(priv, reg);
-+                                      priv->port_link_up[i] = 0;
-+
-+                                      value &= ~(AR40XX_PORT_DUPLEX |
-+                                                 AR40XX_PORT_SPEED);
-+                                      value |= speed | (duplex ? BIT(6) : 0);
-+                                      ar40xx_write(priv, reg, value);
-+                                      /* clock switch need such time
-+                                       * to avoid glitch
-+                                       */
-+                                      usleep_range(100, 200);
-+
-+                                      value |= AR40XX_PORT_AUTO_LINK_EN;
-+                                      ar40xx_write(priv, reg, value);
-+                                      /* HW need such time to make sure link
-+                                       * stable before enable MAC
-+                                       */
-+                                      usleep_range(100, 200);
-+
-+                                      if (speed == AR40XX_PORT_SPEED_100M) {
-+                                              u16 phy_val = 0;
-+                                              /* Enable @100M, if down to 10M
-+                                               * clock will change smoothly
-+                                               */
-+                                              ar40xx_phy_dbg_read(priv, i-1,
-+                                                                  0,
-+                                                                  &phy_val);
-+                                              phy_val |=
-+                                                      AR40XX_PHY_MANU_CTRL_EN;
-+                                              ar40xx_phy_dbg_write(priv, i-1,
-+                                                                   0,
-+                                                                   phy_val);
-+                                      }
-+                                      priv->ar40xx_port_old_link[i] = link;
-+                              }
-+                      }
-+              }
-+
-+              if (priv->ar40xx_port_qm_buf[i] == AR40XX_QM_NOT_EMPTY) {
-+                      /* Check QM */
-+                      ar40xx_get_qm_status(priv, i, &qm_buffer_err);
-+                      if (qm_buffer_err) {
-+                              ++qm_err_cnt[i];
-+                      } else {
-+                              priv->ar40xx_port_qm_buf[i] =
-+                                              AR40XX_QM_EMPTY;
-+                              qm_err_cnt[i] = 0;
-+                              ar40xx_force_1g_full(priv, i);
-+                      }
-+              }
-+      }
-+}
-+
-+static void
-+ar40xx_qm_err_check_work_task(struct work_struct *work)
-+{
-+      struct ar40xx_priv *priv = container_of(work, struct ar40xx_priv,
-+                                      qm_dwork.work);
-+
-+      mutex_lock(&priv->qm_lock);
-+
-+      ar40xx_sw_mac_polling_task(priv);
-+
-+      mutex_unlock(&priv->qm_lock);
-+
-+      schedule_delayed_work(&priv->qm_dwork,
-+                            msecs_to_jiffies(AR40XX_QM_WORK_DELAY));
-+}
-+
-+static int
-+ar40xx_qm_err_check_work_start(struct ar40xx_priv *priv)
-+{
-+      mutex_init(&priv->qm_lock);
-+
-+      INIT_DELAYED_WORK(&priv->qm_dwork, ar40xx_qm_err_check_work_task);
-+
-+      schedule_delayed_work(&priv->qm_dwork,
-+                            msecs_to_jiffies(AR40XX_QM_WORK_DELAY));
-+
-+      return 0;
-+}
-+
-+/* End of qm error WAR */
-+
-+static int
-+ar40xx_vlan_init(struct ar40xx_priv *priv)
-+{
-+      int port;
-+      unsigned long bmp;
-+
-+      /* By default Enable VLAN */
-+      priv->vlan = 1;
-+      priv->vlan_table[AR40XX_LAN_VLAN] = priv->cpu_bmp | priv->lan_bmp;
-+      priv->vlan_table[AR40XX_WAN_VLAN] = priv->cpu_bmp | priv->wan_bmp;
-+      priv->vlan_tagged = priv->cpu_bmp;
-+      bmp = priv->lan_bmp;
-+      for_each_set_bit(port, &bmp, AR40XX_NUM_PORTS)
-+                      priv->pvid[port] = AR40XX_LAN_VLAN;
-+
-+      bmp = priv->wan_bmp;
-+      for_each_set_bit(port, &bmp, AR40XX_NUM_PORTS)
-+                      priv->pvid[port] = AR40XX_WAN_VLAN;
-+
-+      return 0;
-+}
-+
-+static void
-+ar40xx_mib_work_func(struct work_struct *work)
-+{
-+      struct ar40xx_priv *priv;
-+      int err;
-+
-+      priv = container_of(work, struct ar40xx_priv, mib_work.work);
-+
-+      mutex_lock(&priv->mib_lock);
-+
-+      err = ar40xx_mib_capture(priv);
-+      if (err)
-+              goto next_port;
-+
-+      ar40xx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
-+
-+next_port:
-+      priv->mib_next_port++;
-+      if (priv->mib_next_port >= priv->dev.ports)
-+              priv->mib_next_port = 0;
-+
-+      mutex_unlock(&priv->mib_lock);
-+
-+      schedule_delayed_work(&priv->mib_work,
-+                            msecs_to_jiffies(AR40XX_MIB_WORK_DELAY));
-+}
-+
-+static void
-+ar40xx_setup_port(struct ar40xx_priv *priv, int port, u32 members)
-+{
-+      u32 t;
-+      u32 egress, ingress;
-+      u32 pvid = priv->vlan_id[priv->pvid[port]];
-+
-+      if (priv->vlan) {
-+              egress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD;
-+              ingress = AR40XX_IN_SECURE;
-+      } else {
-+              egress = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH;
-+              ingress = AR40XX_IN_PORT_ONLY;
-+      }
-+
-+      t = pvid << AR40XX_PORT_VLAN0_DEF_SVID_S;
-+      t |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S;
-+      ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), t);
-+
-+      t = AR40XX_PORT_VLAN1_PORT_VLAN_PROP;
-+      t |= egress << AR40XX_PORT_VLAN1_OUT_MODE_S;
-+      ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t);
-+
-+      t = members;
-+      t |= AR40XX_PORT_LOOKUP_LEARN;
-+      t |= ingress << AR40XX_PORT_LOOKUP_IN_MODE_S;
-+      t |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;
-+      ar40xx_write(priv, AR40XX_REG_PORT_LOOKUP(port), t);
-+}
-+
-+static void
-+ar40xx_vtu_op(struct ar40xx_priv *priv, u32 op, u32 val)
-+{
-+      if (ar40xx_wait_bit(priv, AR40XX_REG_VTU_FUNC1,
-+                          AR40XX_VTU_FUNC1_BUSY, 0))
-+              return;
-+
-+      if ((op & AR40XX_VTU_FUNC1_OP) == AR40XX_VTU_FUNC1_OP_LOAD)
-+              ar40xx_write(priv, AR40XX_REG_VTU_FUNC0, val);
-+
-+      op |= AR40XX_VTU_FUNC1_BUSY;
-+      ar40xx_write(priv, AR40XX_REG_VTU_FUNC1, op);
-+}
-+
-+static void
-+ar40xx_vtu_load_vlan(struct ar40xx_priv *priv, u32 vid, u32 port_mask)
-+{
-+      u32 op;
-+      u32 val;
-+      int i;
-+
-+      op = AR40XX_VTU_FUNC1_OP_LOAD | (vid << AR40XX_VTU_FUNC1_VID_S);
-+      val = AR40XX_VTU_FUNC0_VALID | AR40XX_VTU_FUNC0_IVL;
-+      for (i = 0; i < AR40XX_NUM_PORTS; i++) {
-+              u32 mode;
-+
-+              if ((port_mask & BIT(i)) == 0)
-+                      mode = AR40XX_VTU_FUNC0_EG_MODE_NOT;
-+              else if (priv->vlan == 0)
-+                      mode = AR40XX_VTU_FUNC0_EG_MODE_KEEP;
-+              else if ((priv->vlan_tagged & BIT(i)) ||
-+                       (priv->vlan_id[priv->pvid[i]] != vid))
-+                      mode = AR40XX_VTU_FUNC0_EG_MODE_TAG;
-+              else
-+                      mode = AR40XX_VTU_FUNC0_EG_MODE_UNTAG;
-+
-+              val |= mode << AR40XX_VTU_FUNC0_EG_MODE_S(i);
-+      }
-+      ar40xx_vtu_op(priv, op, val);
-+}
-+
-+static void
-+ar40xx_vtu_flush(struct ar40xx_priv *priv)
-+{
-+      ar40xx_vtu_op(priv, AR40XX_VTU_FUNC1_OP_FLUSH, 0);
-+}
-+
-+static int
-+ar40xx_sw_hw_apply(struct switch_dev *dev)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+      u8 portmask[AR40XX_NUM_PORTS];
-+      int i, j;
-+
-+      mutex_lock(&priv->reg_mutex);
-+      /* flush all vlan entries */
-+      ar40xx_vtu_flush(priv);
-+
-+      memset(portmask, 0, sizeof(portmask));
-+      if (priv->vlan) {
-+              for (j = 0; j < AR40XX_MAX_VLANS; j++) {
-+                      u8 vp = priv->vlan_table[j];
-+
-+                      if (!vp)
-+                              continue;
-+
-+                      for (i = 0; i < dev->ports; i++) {
-+                              u8 mask = BIT(i);
-+
-+                              if (vp & mask)
-+                                      portmask[i] |= vp & ~mask;
-+                      }
-+
-+                      ar40xx_vtu_load_vlan(priv, priv->vlan_id[j],
-+                                           priv->vlan_table[j]);
-+              }
-+      } else {
-+              /* 8021q vlan disabled */
-+              for (i = 0; i < dev->ports; i++) {
-+                      if (i == AR40XX_PORT_CPU)
-+                              continue;
-+
-+                      portmask[i] = BIT(AR40XX_PORT_CPU);
-+                      portmask[AR40XX_PORT_CPU] |= BIT(i);
-+              }
-+      }
-+
-+      /* update the port destination mask registers and tag settings */
-+      for (i = 0; i < dev->ports; i++)
-+              ar40xx_setup_port(priv, i, portmask[i]);
-+
-+      ar40xx_set_mirror_regs(priv);
-+
-+      mutex_unlock(&priv->reg_mutex);
-+      return 0;
-+}
-+
-+static int
-+ar40xx_sw_reset_switch(struct switch_dev *dev)
-+{
-+      struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+      int i, rv;
-+
-+      mutex_lock(&priv->reg_mutex);
-+      memset(&priv->vlan, 0, sizeof(struct ar40xx_priv) -
-+              offsetof(struct ar40xx_priv, vlan));
-+
-+      for (i = 0; i < AR40XX_MAX_VLANS; i++)
-+              priv->vlan_id[i] = i;
-+
-+      ar40xx_vlan_init(priv);
-+
-+      priv->mirror_rx = false;
-+      priv->mirror_tx = false;
-+      priv->source_port = 0;
-+      priv->monitor_port = 0;
-+
-+      mutex_unlock(&priv->reg_mutex);
-+
-+      rv = ar40xx_sw_hw_apply(dev);
-+      return rv;
-+}
-+
-+static int
-+ar40xx_start(struct ar40xx_priv *priv)
-+{
-+      int ret;
-+
-+      ret = ar40xx_hw_init(priv);
-+      if (ret)
-+              return ret;
-+
-+      ret = ar40xx_sw_reset_switch(&priv->dev);
-+      if (ret)
-+              return ret;
-+
-+      /* at last, setup cpu port */
-+      ret = ar40xx_cpuport_setup(priv);
-+      if (ret)
-+              return ret;
-+
-+      schedule_delayed_work(&priv->mib_work,
-+                            msecs_to_jiffies(AR40XX_MIB_WORK_DELAY));
-+
-+      ar40xx_qm_err_check_work_start(priv);
-+
-+      return 0;
-+}
-+
-+static const struct switch_dev_ops ar40xx_sw_ops = {
-+      .attr_global = {
-+              .attr = ar40xx_sw_attr_globals,
-+              .n_attr = ARRAY_SIZE(ar40xx_sw_attr_globals),
-+      },
-+      .attr_port = {
-+              .attr = ar40xx_sw_attr_port,
-+              .n_attr = ARRAY_SIZE(ar40xx_sw_attr_port),
-+      },
-+      .attr_vlan = {
-+              .attr = ar40xx_sw_attr_vlan,
-+              .n_attr = ARRAY_SIZE(ar40xx_sw_attr_vlan),
-+      },
-+      .get_port_pvid = ar40xx_sw_get_pvid,
-+      .set_port_pvid = ar40xx_sw_set_pvid,
-+      .get_vlan_ports = ar40xx_sw_get_ports,
-+      .set_vlan_ports = ar40xx_sw_set_ports,
-+      .apply_config = ar40xx_sw_hw_apply,
-+      .reset_switch = ar40xx_sw_reset_switch,
-+      .get_port_link = ar40xx_sw_get_port_link,
-+};
-+
-+/* Start of phy driver support */
-+
-+static const u32 ar40xx_phy_ids[] = {
-+      0x004dd0b1,
-+      0x004dd0b2, /* AR40xx */
-+};
-+
-+static bool
-+ar40xx_phy_match(u32 phy_id)
-+{
-+      int i;
-+
-+      for (i = 0; i < ARRAY_SIZE(ar40xx_phy_ids); i++)
-+              if (phy_id == ar40xx_phy_ids[i])
-+                      return true;
-+
-+      return false;
-+}
-+
-+static bool
-+is_ar40xx_phy(struct mii_bus *bus)
-+{
-+      unsigned i;
-+
-+      for (i = 0; i < 4; i++) {
-+              u32 phy_id;
-+
-+              phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
-+              phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
-+              if (!ar40xx_phy_match(phy_id))
-+                      return false;
-+      }
-+
-+      return true;
-+}
-+
-+static int
-+ar40xx_phy_probe(struct phy_device *phydev)
-+{
-+      if (!is_ar40xx_phy(phydev->mdio.bus))
-+              return -ENODEV;
-+
-+      ar40xx_priv->mii_bus = phydev->mdio.bus;
-+      phydev->priv = ar40xx_priv;
-+      if (phydev->mdio.addr == 0)
-+              ar40xx_priv->phy = phydev;
-+
-+      phydev->supported |= SUPPORTED_1000baseT_Full;
-+      phydev->advertising |= ADVERTISED_1000baseT_Full;
-+      return 0;
-+}
-+
-+static void
-+ar40xx_phy_remove(struct phy_device *phydev)
-+{
-+      ar40xx_priv->mii_bus = NULL;
-+      phydev->priv = NULL;
-+}
-+
-+static int
-+ar40xx_phy_config_init(struct phy_device *phydev)
-+{
-+      return 0;
-+}
-+
-+static int
-+ar40xx_phy_read_status(struct phy_device *phydev)
-+{
-+      if (phydev->mdio.addr != 0)
-+              return genphy_read_status(phydev);
-+
-+      return 0;
-+}
-+
-+static int
-+ar40xx_phy_config_aneg(struct phy_device *phydev)
-+{
-+      if (phydev->mdio.addr == 0)
-+              return 0;
-+
-+      return genphy_config_aneg(phydev);
-+}
-+
-+static struct phy_driver ar40xx_phy_driver = {
-+      .phy_id         = 0x004d0000,
-+      .name           = "QCA Malibu",
-+      .phy_id_mask    = 0xffff0000,
-+      .features       = PHY_BASIC_FEATURES,
-+      .probe          = ar40xx_phy_probe,
-+      .remove         = ar40xx_phy_remove,
-+      .config_init    = ar40xx_phy_config_init,
-+      .config_aneg    = ar40xx_phy_config_aneg,
-+      .read_status    = ar40xx_phy_read_status,
-+};
-+
-+static uint16_t ar40xx_gpio_get_phy(unsigned int offset)
-+{
-+      return offset / 4;
-+}
-+
-+static uint16_t ar40xx_gpio_get_reg(unsigned int offset)
-+{
-+      return 0x8074 + offset % 4;
-+}
-+
-+static void ar40xx_gpio_set(struct gpio_chip *gc, unsigned int offset,
-+                          int value)
-+{
-+      struct ar40xx_priv *priv = gpiochip_get_data(gc);
-+
-+      ar40xx_phy_mmd_write(priv, ar40xx_gpio_get_phy(offset), 0x7,
-+                           ar40xx_gpio_get_reg(offset),
-+                           value ? 0xA000 : 0x8000);
-+}
-+
-+static int ar40xx_gpio_get(struct gpio_chip *gc, unsigned offset)
-+{
-+      struct ar40xx_priv *priv = gpiochip_get_data(gc);
-+
-+      return ar40xx_phy_mmd_read(priv, ar40xx_gpio_get_phy(offset), 0x7,
-+                                 ar40xx_gpio_get_reg(offset)) == 0xA000;
-+}
-+
-+static int ar40xx_gpio_get_dir(struct gpio_chip *gc, unsigned offset)
-+{
-+      return 0; /* only out direction */
-+}
-+
-+static int ar40xx_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
-+                             int value)
-+{
-+      /*
-+       * the direction out value is used to set the initial value.
-+       * support of this function is required by leds-gpio.c
-+       */
-+      ar40xx_gpio_set(gc, offset, value);
-+      return 0;
-+}
-+
-+static void ar40xx_register_gpio(struct device *pdev,
-+                               struct ar40xx_priv *priv,
-+                               struct device_node *switch_node)
-+{
-+      struct gpio_chip *gc;
-+      int err;
-+
-+      gc = devm_kzalloc(pdev, sizeof(*gc), GFP_KERNEL);
-+      if (!gc)
-+              return;
-+
-+      gc->label = "ar40xx_gpio",
-+      gc->base = -1,
-+      gc->ngpio = 5 /* mmd 0 - 4 */ * 4 /* 0x8074 - 0x8077 */,
-+      gc->parent = pdev;
-+      gc->owner = THIS_MODULE;
-+
-+      gc->get_direction = ar40xx_gpio_get_dir;
-+      gc->direction_output = ar40xx_gpio_dir_out;
-+      gc->get = ar40xx_gpio_get;
-+      gc->set = ar40xx_gpio_set;
-+      gc->can_sleep = true;
-+      gc->label = priv->dev.name;
-+      gc->of_node = switch_node;
-+
-+      err = devm_gpiochip_add_data(pdev, gc, priv);
-+      if (err != 0)
-+              dev_err(pdev, "Failed to register gpio %d.\n", err);
-+}
-+
-+/* End of phy driver support */
-+
-+/* Platform driver probe function */
-+
-+static int ar40xx_probe(struct platform_device *pdev)
-+{
-+      struct device_node *switch_node;
-+      struct device_node *psgmii_node;
-+      const __be32 *mac_mode;
-+      struct clk *ess_clk;
-+      struct switch_dev *swdev;
-+      struct ar40xx_priv *priv;
-+      u32 len;
-+      u32 num_mibs;
-+      struct resource psgmii_base = {0};
-+      struct resource switch_base = {0};
-+      int ret;
-+
-+      priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-+      if (!priv)
-+              return -ENOMEM;
-+
-+      platform_set_drvdata(pdev, priv);
-+      ar40xx_priv = priv;
-+
-+      switch_node = of_node_get(pdev->dev.of_node);
-+      if (of_address_to_resource(switch_node, 0, &switch_base) != 0)
-+              return -EIO;
-+
-+      priv->hw_addr = devm_ioremap_resource(&pdev->dev, &switch_base);
-+      if (IS_ERR(priv->hw_addr)) {
-+              dev_err(&pdev->dev, "Failed to ioremap switch_base!\n");
-+              return PTR_ERR(priv->hw_addr);
-+      }
-+
-+      /*psgmii dts get*/
-+      psgmii_node = of_find_node_by_name(NULL, "ess-psgmii");
-+      if (!psgmii_node) {
-+              dev_err(&pdev->dev, "Failed to find ess-psgmii node!\n");
-+              return -EINVAL;
-+      }
-+
-+      if (of_address_to_resource(psgmii_node, 0, &psgmii_base) != 0)
-+              return -EIO;
-+
-+      priv->psgmii_hw_addr = devm_ioremap_resource(&pdev->dev, &psgmii_base);
-+      if (IS_ERR(priv->psgmii_hw_addr)) {
-+              dev_err(&pdev->dev, "psgmii ioremap fail!\n");
-+              return PTR_ERR(priv->psgmii_hw_addr);
-+      }
-+
-+      mac_mode = of_get_property(switch_node, "switch_mac_mode", &len);
-+      if (!mac_mode) {
-+              dev_err(&pdev->dev, "Failed to read switch_mac_mode\n");
-+              return -EINVAL;
-+      }
-+      priv->mac_mode = be32_to_cpup(mac_mode);
-+
-+      ess_clk = of_clk_get_by_name(switch_node, "ess_clk");
-+      if (ess_clk)
-+              clk_prepare_enable(ess_clk);
-+
-+      priv->ess_rst = devm_reset_control_get(&pdev->dev, "ess_rst");
-+      if (IS_ERR(priv->ess_rst)) {
-+              dev_err(&pdev->dev, "Failed to get ess_rst control!\n");
-+              return PTR_ERR(priv->ess_rst);
-+      }
-+
-+      if (of_property_read_u32(switch_node, "switch_cpu_bmp",
-+                               &priv->cpu_bmp) ||
-+          of_property_read_u32(switch_node, "switch_lan_bmp",
-+                               &priv->lan_bmp) ||
-+          of_property_read_u32(switch_node, "switch_wan_bmp",
-+                               &priv->wan_bmp)) {
-+              dev_err(&pdev->dev, "Failed to read port properties\n");
-+              return -EIO;
-+      }
-+
-+      ret = phy_driver_register(&ar40xx_phy_driver, THIS_MODULE);
-+      if (ret) {
-+              dev_err(&pdev->dev, "Failed to register ar40xx phy driver!\n");
-+              return -EIO;
-+      }
-+
-+      mutex_init(&priv->reg_mutex);
-+      mutex_init(&priv->mib_lock);
-+      INIT_DELAYED_WORK(&priv->mib_work, ar40xx_mib_work_func);
-+
-+      /* register switch */
-+      swdev = &priv->dev;
-+
-+      swdev->alias = dev_name(&priv->mii_bus->dev);
-+
-+      swdev->cpu_port = AR40XX_PORT_CPU;
-+      swdev->name = "QCA AR40xx";
-+      swdev->vlans = AR40XX_MAX_VLANS;
-+      swdev->ports = AR40XX_NUM_PORTS;
-+      swdev->ops = &ar40xx_sw_ops;
-+      ret = register_switch(swdev, NULL);
-+      if (ret)
-+              goto err_unregister_phy;
-+
-+      num_mibs = ARRAY_SIZE(ar40xx_mibs);
-+      len = priv->dev.ports * num_mibs *
-+            sizeof(*priv->mib_stats);
-+      priv->mib_stats = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
-+      if (!priv->mib_stats) {
-+              ret = -ENOMEM;
-+              goto err_unregister_switch;
-+      }
-+
-+      ar40xx_start(priv);
-+
-+      if (of_property_read_bool(switch_node, "gpio-controller"))
-+              ar40xx_register_gpio(&pdev->dev, ar40xx_priv, switch_node);
-+
-+      return 0;
-+
-+err_unregister_switch:
-+      unregister_switch(&priv->dev);
-+err_unregister_phy:
-+      phy_driver_unregister(&ar40xx_phy_driver);
-+      platform_set_drvdata(pdev, NULL);
-+      return ret;
-+}
-+
-+static int ar40xx_remove(struct platform_device *pdev)
-+{
-+      struct ar40xx_priv *priv = platform_get_drvdata(pdev);
-+
-+      cancel_delayed_work_sync(&priv->qm_dwork);
-+      cancel_delayed_work_sync(&priv->mib_work);
-+
-+      unregister_switch(&priv->dev);
-+
-+      phy_driver_unregister(&ar40xx_phy_driver);
-+
-+      return 0;
-+}
-+
-+static const struct of_device_id ar40xx_of_mtable[] = {
-+      {.compatible = "qcom,ess-switch" },
-+      {}
-+};
-+
-+struct platform_driver ar40xx_drv = {
-+      .probe = ar40xx_probe,
-+      .remove = ar40xx_remove,
-+      .driver = {
-+              .name    = "ar40xx",
-+              .of_match_table = ar40xx_of_mtable,
-+      },
-+};
-+
-+module_platform_driver(ar40xx_drv);
-+
-+MODULE_DESCRIPTION("IPQ40XX ESS driver");
-+MODULE_LICENSE("Dual BSD/GPL");
---- /dev/null
-+++ b/drivers/net/phy/ar40xx.h
-@@ -0,0 +1,337 @@
-+/*
-+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for
-+ * any purpose with or without fee is hereby granted, provided that the
-+ * above copyright notice and this permission notice appear in all copies.
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
-+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+ #ifndef __AR40XX_H
-+#define __AR40XX_H
-+
-+#define AR40XX_MAX_VLANS      128
-+#define AR40XX_NUM_PORTS      6
-+#define AR40XX_NUM_PHYS       5
-+
-+#define BITS(_s, _n)  (((1UL << (_n)) - 1) << _s)
-+
-+struct ar40xx_priv {
-+      struct switch_dev dev;
-+
-+      u8  __iomem      *hw_addr;
-+      u8  __iomem      *psgmii_hw_addr;
-+      u32 mac_mode;
-+      struct reset_control *ess_rst;
-+      u32 cpu_bmp;
-+      u32 lan_bmp;
-+      u32 wan_bmp;
-+
-+      struct mii_bus *mii_bus;
-+      struct phy_device *phy;
-+
-+      /* mutex for qm task */
-+      struct mutex qm_lock;
-+      struct delayed_work qm_dwork;
-+      u32 port_link_up[AR40XX_NUM_PORTS];
-+      u32 ar40xx_port_old_link[AR40XX_NUM_PORTS];
-+      u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS];
-+
-+      u32 phy_t_status;
-+
-+      /* mutex for switch reg access */
-+      struct mutex reg_mutex;
-+
-+      /* mutex for mib task */
-+      struct mutex mib_lock;
-+      struct delayed_work mib_work;
-+      int mib_next_port;
-+      u64 *mib_stats;
-+
-+      char buf[2048];
-+
-+      /* all fields below will be cleared on reset */
-+      bool vlan;
-+      u16 vlan_id[AR40XX_MAX_VLANS];
-+      u8 vlan_table[AR40XX_MAX_VLANS];
-+      u8 vlan_tagged;
-+      u16 pvid[AR40XX_NUM_PORTS];
-+
-+      /* mirror */
-+      bool mirror_rx;
-+      bool mirror_tx;
-+      int source_port;
-+      int monitor_port;
-+};
-+
-+#define AR40XX_PORT_LINK_UP 1
-+#define AR40XX_PORT_LINK_DOWN 0
-+#define AR40XX_QM_NOT_EMPTY  1
-+#define AR40XX_QM_EMPTY  0
-+
-+#define AR40XX_LAN_VLAN       1
-+#define AR40XX_WAN_VLAN       2
-+
-+enum ar40xx_port_wrapper_cfg {
-+      PORT_WRAPPER_PSGMII = 0,
-+};
-+
-+struct ar40xx_mib_desc {
-+      u32 size;
-+      u32 offset;
-+      const char *name;
-+};
-+
-+#define AR40XX_PORT_CPU       0
-+
-+#define AR40XX_PSGMII_MODE_CONTROL    0x1b4
-+#define   AR40XX_PSGMII_ATHR_CSCO_MODE_25M    BIT(0)
-+
-+#define AR40XX_PSGMIIPHY_TX_CONTROL    0x288
-+
-+#define AR40XX_MII_ATH_MMD_ADDR               0x0d
-+#define AR40XX_MII_ATH_MMD_DATA               0x0e
-+#define AR40XX_MII_ATH_DBG_ADDR               0x1d
-+#define AR40XX_MII_ATH_DBG_DATA               0x1e
-+
-+#define AR40XX_STATS_RXBROAD          0x00
-+#define AR40XX_STATS_RXPAUSE          0x04
-+#define AR40XX_STATS_RXMULTI          0x08
-+#define AR40XX_STATS_RXFCSERR         0x0c
-+#define AR40XX_STATS_RXALIGNERR               0x10
-+#define AR40XX_STATS_RXRUNT           0x14
-+#define AR40XX_STATS_RXFRAGMENT               0x18
-+#define AR40XX_STATS_RX64BYTE         0x1c
-+#define AR40XX_STATS_RX128BYTE                0x20
-+#define AR40XX_STATS_RX256BYTE                0x24
-+#define AR40XX_STATS_RX512BYTE                0x28
-+#define AR40XX_STATS_RX1024BYTE               0x2c
-+#define AR40XX_STATS_RX1518BYTE               0x30
-+#define AR40XX_STATS_RXMAXBYTE                0x34
-+#define AR40XX_STATS_RXTOOLONG                0x38
-+#define AR40XX_STATS_RXGOODBYTE               0x3c
-+#define AR40XX_STATS_RXBADBYTE                0x44
-+#define AR40XX_STATS_RXOVERFLOW               0x4c
-+#define AR40XX_STATS_FILTERED         0x50
-+#define AR40XX_STATS_TXBROAD          0x54
-+#define AR40XX_STATS_TXPAUSE          0x58
-+#define AR40XX_STATS_TXMULTI          0x5c
-+#define AR40XX_STATS_TXUNDERRUN               0x60
-+#define AR40XX_STATS_TX64BYTE         0x64
-+#define AR40XX_STATS_TX128BYTE                0x68
-+#define AR40XX_STATS_TX256BYTE                0x6c
-+#define AR40XX_STATS_TX512BYTE                0x70
-+#define AR40XX_STATS_TX1024BYTE               0x74
-+#define AR40XX_STATS_TX1518BYTE               0x78
-+#define AR40XX_STATS_TXMAXBYTE                0x7c
-+#define AR40XX_STATS_TXOVERSIZE               0x80
-+#define AR40XX_STATS_TXBYTE           0x84
-+#define AR40XX_STATS_TXCOLLISION      0x8c
-+#define AR40XX_STATS_TXABORTCOL               0x90
-+#define AR40XX_STATS_TXMULTICOL               0x94
-+#define AR40XX_STATS_TXSINGLECOL      0x98
-+#define AR40XX_STATS_TXEXCDEFER               0x9c
-+#define AR40XX_STATS_TXDEFER          0xa0
-+#define AR40XX_STATS_TXLATECOL                0xa4
-+
-+#define AR40XX_REG_MODULE_EN                  0x030
-+#define   AR40XX_MODULE_EN_MIB                        BIT(0)
-+
-+#define AR40XX_REG_MIB_FUNC                   0x034
-+#define   AR40XX_MIB_BUSY             BIT(17)
-+#define   AR40XX_MIB_CPU_KEEP                 BIT(20)
-+#define   AR40XX_MIB_FUNC             BITS(24, 3)
-+#define   AR40XX_MIB_FUNC_S           24
-+#define   AR40XX_MIB_FUNC_NO_OP               0x0
-+#define   AR40XX_MIB_FUNC_FLUSH               0x1
-+
-+#define AR40XX_REG_PORT_STATUS(_i)            (0x07c + (_i) * 4)
-+#define   AR40XX_PORT_SPEED                   BITS(0, 2)
-+#define   AR40XX_PORT_STATUS_SPEED_S  0
-+#define   AR40XX_PORT_TX_EN                   BIT(2)
-+#define   AR40XX_PORT_RX_EN                   BIT(3)
-+#define   AR40XX_PORT_STATUS_TXFLOW   BIT(4)
-+#define   AR40XX_PORT_STATUS_RXFLOW   BIT(5)
-+#define   AR40XX_PORT_DUPLEX                  BIT(6)
-+#define   AR40XX_PORT_TXHALF_FLOW             BIT(7)
-+#define   AR40XX_PORT_STATUS_LINK_UP  BIT(8)
-+#define   AR40XX_PORT_AUTO_LINK_EN            BIT(9)
-+#define   AR40XX_PORT_STATUS_FLOW_CONTROL  BIT(12)
-+
-+#define AR40XX_REG_MAX_FRAME_SIZE             0x078
-+#define   AR40XX_MAX_FRAME_SIZE_MTU           BITS(0, 14)
-+
-+#define AR40XX_REG_PORT_HEADER(_i)            (0x09c + (_i) * 4)
-+
-+#define AR40XX_REG_EEE_CTRL                   0x100
-+#define   AR40XX_EEE_CTRL_DISABLE_PHY(_i)     BIT(4 + (_i) * 2)
-+
-+#define AR40XX_REG_PORT_VLAN0(_i)             (0x420 + (_i) * 0x8)
-+#define   AR40XX_PORT_VLAN0_DEF_SVID          BITS(0, 12)
-+#define   AR40XX_PORT_VLAN0_DEF_SVID_S                0
-+#define   AR40XX_PORT_VLAN0_DEF_CVID          BITS(16, 12)
-+#define   AR40XX_PORT_VLAN0_DEF_CVID_S                16
-+
-+#define AR40XX_REG_PORT_VLAN1(_i)             (0x424 + (_i) * 0x8)
-+#define   AR40XX_PORT_VLAN1_PORT_VLAN_PROP    BIT(6)
-+#define   AR40XX_PORT_VLAN1_OUT_MODE          BITS(12, 2)
-+#define   AR40XX_PORT_VLAN1_OUT_MODE_S                12
-+#define   AR40XX_PORT_VLAN1_OUT_MODE_UNMOD    0
-+#define   AR40XX_PORT_VLAN1_OUT_MODE_UNTAG    1
-+#define   AR40XX_PORT_VLAN1_OUT_MODE_TAG              2
-+#define   AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH  3
-+
-+#define AR40XX_REG_VTU_FUNC0                  0x0610
-+#define   AR40XX_VTU_FUNC0_EG_MODE            BITS(4, 14)
-+#define   AR40XX_VTU_FUNC0_EG_MODE_S(_i)      (4 + (_i) * 2)
-+#define   AR40XX_VTU_FUNC0_EG_MODE_KEEP               0
-+#define   AR40XX_VTU_FUNC0_EG_MODE_UNTAG      1
-+#define   AR40XX_VTU_FUNC0_EG_MODE_TAG                2
-+#define   AR40XX_VTU_FUNC0_EG_MODE_NOT                3
-+#define   AR40XX_VTU_FUNC0_IVL                        BIT(19)
-+#define   AR40XX_VTU_FUNC0_VALID              BIT(20)
-+
-+#define AR40XX_REG_VTU_FUNC1                  0x0614
-+#define   AR40XX_VTU_FUNC1_OP                 BITS(0, 3)
-+#define   AR40XX_VTU_FUNC1_OP_NOOP            0
-+#define   AR40XX_VTU_FUNC1_OP_FLUSH           1
-+#define   AR40XX_VTU_FUNC1_OP_LOAD            2
-+#define   AR40XX_VTU_FUNC1_OP_PURGE           3
-+#define   AR40XX_VTU_FUNC1_OP_REMOVE_PORT     4
-+#define   AR40XX_VTU_FUNC1_OP_GET_NEXT                5
-+#define   AR40XX7_VTU_FUNC1_OP_GET_ONE                6
-+#define   AR40XX_VTU_FUNC1_FULL                       BIT(4)
-+#define   AR40XX_VTU_FUNC1_PORT                       BIT(8, 4)
-+#define   AR40XX_VTU_FUNC1_PORT_S             8
-+#define   AR40XX_VTU_FUNC1_VID                        BIT(16, 12)
-+#define   AR40XX_VTU_FUNC1_VID_S              16
-+#define   AR40XX_VTU_FUNC1_BUSY                       BIT(31)
-+
-+#define AR40XX_REG_FWD_CTRL0                  0x620
-+#define   AR40XX_FWD_CTRL0_CPU_PORT_EN                BIT(10)
-+#define   AR40XX_FWD_CTRL0_MIRROR_PORT                BITS(4, 4)
-+#define   AR40XX_FWD_CTRL0_MIRROR_PORT_S      4
-+
-+#define AR40XX_REG_FWD_CTRL1                  0x624
-+#define   AR40XX_FWD_CTRL1_UC_FLOOD           BITS(0, 7)
-+#define   AR40XX_FWD_CTRL1_UC_FLOOD_S         0
-+#define   AR40XX_FWD_CTRL1_MC_FLOOD           BITS(8, 7)
-+#define   AR40XX_FWD_CTRL1_MC_FLOOD_S         8
-+#define   AR40XX_FWD_CTRL1_BC_FLOOD           BITS(16, 7)
-+#define   AR40XX_FWD_CTRL1_BC_FLOOD_S         16
-+#define   AR40XX_FWD_CTRL1_IGMP                       BITS(24, 7)
-+#define   AR40XX_FWD_CTRL1_IGMP_S             24
-+
-+#define AR40XX_REG_PORT_LOOKUP(_i)            (0x660 + (_i) * 0xc)
-+#define   AR40XX_PORT_LOOKUP_MEMBER           BITS(0, 7)
-+#define   AR40XX_PORT_LOOKUP_IN_MODE          BITS(8, 2)
-+#define   AR40XX_PORT_LOOKUP_IN_MODE_S                8
-+#define   AR40XX_PORT_LOOKUP_STATE            BITS(16, 3)
-+#define   AR40XX_PORT_LOOKUP_STATE_S          16
-+#define   AR40XX_PORT_LOOKUP_LEARN            BIT(20)
-+#define   AR40XX_PORT_LOOKUP_LOOPBACK         BIT(21)
-+#define   AR40XX_PORT_LOOKUP_ING_MIRROR_EN    BIT(25)
-+
-+#define AR40XX_REG_ATU_FUNC                   0x60c
-+#define   AR40XX_ATU_FUNC_OP                  BITS(0, 4)
-+#define   AR40XX_ATU_FUNC_OP_NOOP             0x0
-+#define   AR40XX_ATU_FUNC_OP_FLUSH            0x1
-+#define   AR40XX_ATU_FUNC_OP_LOAD             0x2
-+#define   AR40XX_ATU_FUNC_OP_PURGE            0x3
-+#define   AR40XX_ATU_FUNC_OP_FLUSH_LOCKED     0x4
-+#define   AR40XX_ATU_FUNC_OP_FLUSH_UNICAST    0x5
-+#define   AR40XX_ATU_FUNC_OP_GET_NEXT         0x6
-+#define   AR40XX_ATU_FUNC_OP_SEARCH_MAC               0x7
-+#define   AR40XX_ATU_FUNC_OP_CHANGE_TRUNK     0x8
-+#define   AR40XX_ATU_FUNC_BUSY                        BIT(31)
-+
-+#define AR40XX_REG_QM_DEBUG_ADDR              0x820
-+#define AR40XX_REG_QM_DEBUG_VALUE             0x824
-+#define   AR40XX_REG_QM_PORT0_3_QNUM          0x1d
-+#define   AR40XX_REG_QM_PORT4_6_QNUM          0x1e
-+
-+#define AR40XX_REG_PORT_HOL_CTRL1(_i)         (0x974 + (_i) * 0x8)
-+#define   AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN  BIT(16)
-+
-+#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i)   (0x9b0 + (_i) * 0x4)
-+#define   AR40XX_PORT0_FC_THRESH_ON_DFLT      0x60
-+#define   AR40XX_PORT0_FC_THRESH_OFF_DFLT     0x90
-+
-+#define AR40XX_PHY_DEBUG_0   0
-+#define AR40XX_PHY_MANU_CTRL_EN  BIT(12)
-+
-+#define AR40XX_PHY_DEBUG_2   2
-+
-+#define AR40XX_PHY_SPEC_STATUS 0x11
-+#define   AR40XX_PHY_SPEC_STATUS_LINK         BIT(10)
-+#define   AR40XX_PHY_SPEC_STATUS_DUPLEX               BIT(13)
-+#define   AR40XX_PHY_SPEC_STATUS_SPEED                BITS(14, 2)
-+
-+/* port forwarding state */
-+enum {
-+      AR40XX_PORT_STATE_DISABLED = 0,
-+      AR40XX_PORT_STATE_BLOCK = 1,
-+      AR40XX_PORT_STATE_LISTEN = 2,
-+      AR40XX_PORT_STATE_LEARN = 3,
-+      AR40XX_PORT_STATE_FORWARD = 4
-+};
-+
-+/* ingress 802.1q mode */
-+enum {
-+      AR40XX_IN_PORT_ONLY = 0,
-+      AR40XX_IN_PORT_FALLBACK = 1,
-+      AR40XX_IN_VLAN_ONLY = 2,
-+      AR40XX_IN_SECURE = 3
-+};
-+
-+/* egress 802.1q mode */
-+enum {
-+      AR40XX_OUT_KEEP = 0,
-+      AR40XX_OUT_STRIP_VLAN = 1,
-+      AR40XX_OUT_ADD_VLAN = 2
-+};
-+
-+/* port speed */
-+enum {
-+      AR40XX_PORT_SPEED_10M = 0,
-+      AR40XX_PORT_SPEED_100M = 1,
-+      AR40XX_PORT_SPEED_1000M = 2,
-+      AR40XX_PORT_SPEED_ERR = 3,
-+};
-+
-+#define AR40XX_MIB_WORK_DELAY 2000 /* msecs */
-+
-+#define AR40XX_QM_WORK_DELAY    100
-+
-+#define   AR40XX_MIB_FUNC_CAPTURE     0x3
-+
-+#define AR40XX_REG_PORT_STATS_START   0x1000
-+#define AR40XX_REG_PORT_STATS_LEN             0x100
-+
-+#define AR40XX_PORTS_ALL      0x3f
-+
-+#define AR40XX_PSGMII_ID      5
-+#define AR40XX_PSGMII_CALB_NUM        100
-+#define AR40XX_MALIBU_PSGMII_MODE_CTRL        0x6d
-+#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c
-+#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL       0x801a
-+#define AR40XX_MALIBU_DAC_CTRL_MASK   0x380
-+#define AR40XX_MALIBU_DAC_CTRL_VALUE  0x280
-+#define AR40XX_MALIBU_PHY_RLP_CTRL       0x805a
-+#define AR40XX_PSGMII_TX_DRIVER_1_CTRL        0xb
-+#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a
-+#define AR40XX_MALIBU_PHY_LAST_ADDR   4
-+
-+static inline struct ar40xx_priv *
-+swdev_to_ar40xx(struct switch_dev *swdev)
-+{
-+      return container_of(swdev, struct ar40xx_priv, dev);
-+}
-+
-+#endif
---- /dev/null
-+++ b/drivers/net/phy/mdio-ipq40xx.c
-@@ -0,0 +1,203 @@
-+/*
-+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for
-+ * any purpose with or without fee is hereby granted, provided that the
-+ * above copyright notice and this permission notice appear in all copies.
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
-+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/mutex.h>
-+#include <linux/io.h>
-+#include <linux/of_address.h>
-+#include <linux/of_mdio.h>
-+#include <linux/phy.h>
-+#include <linux/platform_device.h>
-+
-+#define MDIO_CTRL_0_REG               0x40
-+#define MDIO_CTRL_1_REG               0x44
-+#define MDIO_CTRL_2_REG               0x48
-+#define MDIO_CTRL_3_REG               0x4c
-+#define MDIO_CTRL_4_REG               0x50
-+#define MDIO_CTRL_4_ACCESS_BUSY               BIT(16)
-+#define MDIO_CTRL_4_ACCESS_START              BIT(8)
-+#define MDIO_CTRL_4_ACCESS_CODE_READ          0
-+#define MDIO_CTRL_4_ACCESS_CODE_WRITE 1
-+#define CTRL_0_REG_DEFAULT_VALUE      0x150FF
-+
-+#define IPQ40XX_MDIO_RETRY    1000
-+#define IPQ40XX_MDIO_DELAY    10
-+
-+struct ipq40xx_mdio_data {
-+      struct mii_bus  *mii_bus;
-+      void __iomem    *membase;
-+      int             phy_irq[PHY_MAX_ADDR];
-+      struct device   *dev;
-+};
-+
-+static int ipq40xx_mdio_wait_busy(struct ipq40xx_mdio_data *am)
-+{
-+      int i;
-+
-+      for (i = 0; i < IPQ40XX_MDIO_RETRY; i++) {
-+              unsigned int busy;
-+
-+              busy = readl(am->membase + MDIO_CTRL_4_REG) &
-+                      MDIO_CTRL_4_ACCESS_BUSY;
-+              if (!busy)
-+                      return 0;
-+
-+              /* BUSY might take to be cleard by 15~20 times of loop */
-+              udelay(IPQ40XX_MDIO_DELAY);
-+      }
-+
-+      dev_err(am->dev, "%s: MDIO operation timed out\n", am->mii_bus->name);
-+
-+      return -ETIMEDOUT;
-+}
-+
-+static int ipq40xx_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
-+{
-+      struct ipq40xx_mdio_data *am = bus->priv;
-+      int value = 0;
-+      unsigned int cmd = 0;
-+
-+      lockdep_assert_held(&bus->mdio_lock);
-+
-+      if (ipq40xx_mdio_wait_busy(am))
-+              return -ETIMEDOUT;
-+
-+      /* issue the phy address and reg */
-+      writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG);
-+
-+      cmd = MDIO_CTRL_4_ACCESS_START|MDIO_CTRL_4_ACCESS_CODE_READ;
-+
-+      /* issue read command */
-+      writel(cmd, am->membase + MDIO_CTRL_4_REG);
-+
-+      /* Wait read complete */
-+      if (ipq40xx_mdio_wait_busy(am))
-+              return -ETIMEDOUT;
-+
-+      /* Read data */
-+      value = readl(am->membase + MDIO_CTRL_3_REG);
-+
-+      return value;
-+}
-+
-+static int ipq40xx_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
-+                          u16 value)
-+{
-+      struct ipq40xx_mdio_data *am = bus->priv;
-+      unsigned int cmd = 0;
-+
-+      lockdep_assert_held(&bus->mdio_lock);
-+
-+      if (ipq40xx_mdio_wait_busy(am))
-+              return -ETIMEDOUT;
-+
-+      /* issue the phy address and reg */
-+      writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG);
-+
-+      /* issue write data */
-+      writel(value, am->membase + MDIO_CTRL_2_REG);
-+
-+      cmd = MDIO_CTRL_4_ACCESS_START|MDIO_CTRL_4_ACCESS_CODE_WRITE;
-+      /* issue write command */
-+      writel(cmd, am->membase + MDIO_CTRL_4_REG);
-+
-+      /* Wait write complete */
-+      if (ipq40xx_mdio_wait_busy(am))
-+              return -ETIMEDOUT;
-+
-+      return 0;
-+}
-+
-+static int ipq40xx_mdio_probe(struct platform_device *pdev)
-+{
-+      struct ipq40xx_mdio_data *am;
-+      struct resource *res;
-+      int i;
-+
-+      am = devm_kzalloc(&pdev->dev, sizeof(*am), GFP_KERNEL);
-+      if (!am)
-+              return -ENOMEM;
-+
-+      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+      if (!res) {
-+              dev_err(&pdev->dev, "no iomem resource found\n");
-+              return -ENXIO;
-+      }
-+
-+      am->membase = devm_ioremap_resource(&pdev->dev, res);
-+      if (IS_ERR(am->membase)) {
-+              dev_err(&pdev->dev, "unable to ioremap registers\n");
-+              return PTR_ERR(am->membase);
-+      }
-+
-+      am->mii_bus = devm_mdiobus_alloc(&pdev->dev);
-+      if (!am->mii_bus)
-+              return  -ENOMEM;
-+
-+      writel(CTRL_0_REG_DEFAULT_VALUE, am->membase + MDIO_CTRL_0_REG);
-+
-+      am->mii_bus->name = "ipq40xx_mdio";
-+      am->mii_bus->read = ipq40xx_mdio_read;
-+      am->mii_bus->write = ipq40xx_mdio_write;
-+      memcpy(am->mii_bus->irq, am->phy_irq, sizeof(am->phy_irq));
-+      am->mii_bus->priv = am;
-+      am->mii_bus->parent = &pdev->dev;
-+      snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev));
-+
-+      for (i = 0; i < PHY_MAX_ADDR; i++)
-+              am->phy_irq[i] = PHY_POLL;
-+
-+      am->dev = &pdev->dev;
-+      platform_set_drvdata(pdev, am);
-+
-+      /* edma_axi_probe() use "am" drvdata.
-+       * ipq40xx_mdio_probe() must be called first.
-+       */
-+      return of_mdiobus_register(am->mii_bus, pdev->dev.of_node);
-+}
-+
-+static int ipq40xx_mdio_remove(struct platform_device *pdev)
-+{
-+      struct ipq40xx_mdio_data *am = platform_get_drvdata(pdev);
-+
-+      mdiobus_unregister(am->mii_bus);
-+      return 0;
-+}
-+
-+static const struct of_device_id ipq40xx_mdio_dt_ids[] = {
-+      { .compatible = "qcom,ipq4019-mdio" },
-+      { }
-+};
-+MODULE_DEVICE_TABLE(of, ipq40xx_mdio_dt_ids);
-+
-+static struct platform_driver ipq40xx_mdio_driver = {
-+      .probe = ipq40xx_mdio_probe,
-+      .remove = ipq40xx_mdio_remove,
-+      .driver = {
-+              .name = "ipq40xx-mdio",
-+              .of_match_table = ipq40xx_mdio_dt_ids,
-+      },
-+};
-+
-+module_platform_driver(ipq40xx_mdio_driver);
-+
-+#define DRV_VERSION     "1.0"
-+
-+MODULE_DESCRIPTION("IPQ40XX MDIO interface driver");
-+MODULE_AUTHOR("Qualcomm Atheros");
-+MODULE_VERSION(DRV_VERSION);
-+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/target/linux/ipq806x/patches-4.9/701-dts-ipq4019-add-mdio-node.patch b/target/linux/ipq806x/patches-4.9/701-dts-ipq4019-add-mdio-node.patch
deleted file mode 100644 (file)
index 676da72..0000000
+++ /dev/null
@@ -1,52 +0,0 @@
-From 09ed737593f71bcca08a537a6c15264a1a6add08 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sun, 20 Nov 2016 01:10:33 +0100
-Subject: [PATCH] dts: ipq4019: add mdio node for ethernet
-
-This patch adds the mdio device-tree node.
-This is where the switch is connected to, so it's needed
-for the ethernet interfaces.
-
-Note: The driver isn't anywhere close to be upstream,
-so the info might change.
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 28 ++++++++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -315,6 +315,34 @@
-                       reg = <0x4ab000 0x4>;
-               };
-+              mdio@90000 {
-+                      #address-cells = <1>;
-+                      #size-cells = <0>;
-+                      compatible = "qcom,ipq4019-mdio";
-+                      reg = <0x90000 0x64>;
-+                      status = "disabled";
-+
-+                      ethernet-phy@0 {
-+                              reg = <0>;
-+                      };
-+
-+                      ethernet-phy@1 {
-+                              reg = <1>;
-+                      };
-+
-+                      ethernet-phy@2 {
-+                              reg = <2>;
-+                      };
-+
-+                      ethernet-phy@3 {
-+                              reg = <3>;
-+                      };
-+
-+                      ethernet-phy@4 {
-+                              reg = <4>;
-+                      };
-+              };
-+
-               usb3_ss_phy: ssphy@9a000 {
-                       compatible = "qca,uni-ssphy";
-                       reg = <0x9a000 0x800>;
diff --git a/target/linux/ipq806x/patches-4.9/702-dts-ipq4019-add-PHY-switch-nodes.patch b/target/linux/ipq806x/patches-4.9/702-dts-ipq4019-add-PHY-switch-nodes.patch
deleted file mode 100644 (file)
index 79031d3..0000000
+++ /dev/null
@@ -1,46 +0,0 @@
-From 9deeec35dd3b628b95624e41d4e04acf728991ba Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sun, 20 Nov 2016 02:20:54 +0100
-Subject: [PATCH] dts: ipq4019: add PHY/switch nodes
-
-This patch adds both the "qcom,ess-switch" and "qcom,ess-psgmii"
-nodes which are needed for the ar40xx.c driver to initialize the
-switch.
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -343,6 +343,29 @@
-                       };
-               };
-+              ess-switch@c000000 {
-+                      compatible = "qcom,ess-switch";
-+                      reg = <0xc000000 0x80000>;
-+                      switch_access_mode = "local bus";
-+                      resets = <&gcc ESS_RESET>;
-+                      reset-names = "ess_rst";
-+                      clocks = <&gcc GCC_ESS_CLK>;
-+                      clock-names = "ess_clk";
-+                      switch_cpu_bmp = <0x1>;
-+                      switch_lan_bmp = <0x1e>;
-+                      switch_wan_bmp = <0x20>;
-+                      switch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */
-+                      switch_initvlas = <0x7c 0x54>;
-+                      status = "disabled";
-+              };
-+
-+              ess-psgmii@98000 {
-+                      compatible = "qcom,ess-psgmii";
-+                      reg = <0x98000 0x800>;
-+                      psgmii_access_mode = "local bus";
-+                      status = "disabled";
-+              };
-+
-               usb3_ss_phy: ssphy@9a000 {
-                       compatible = "qca,uni-ssphy";
-                       reg = <0x9a000 0x800>;
diff --git a/target/linux/ipq806x/patches-4.9/710-net-add-qualcomm-essedma-ethernet-driver.patch b/target/linux/ipq806x/patches-4.9/710-net-add-qualcomm-essedma-ethernet-driver.patch
deleted file mode 100644 (file)
index eb84124..0000000
+++ /dev/null
@@ -1,4602 +0,0 @@
-From 12e9319da1adacac92930c899c99f0e1970cac11 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@googlemail.com>
-Date: Thu, 19 Jan 2017 02:01:31 +0100
-Subject: [PATCH 33/38] NET: add qualcomm essedma ethernet driver
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
- drivers/net/ethernet/qualcomm/Kconfig  | 9 +++++++++
- drivers/net/ethernet/qualcomm/Makefile | 1 +
- 2 files changed, 10 insertions(+)
-
---- a/drivers/net/ethernet/qualcomm/Kconfig
-+++ b/drivers/net/ethernet/qualcomm/Kconfig
-@@ -37,4 +37,13 @@ config QCOM_EMAC
-         low power, Receive-Side Scaling (RSS), and IEEE 1588-2008
-         Precision Clock Synchronization Protocol.
-+config ESSEDMA
-+      tristate "Qualcomm Atheros ESS Edma support"
-+      ---help---
-+        This driver supports ethernet edma adapter.
-+        Say Y to build this driver.
-+
-+        To compile this driver as a module, choose M here. The module
-+        will be called essedma.ko.
-+
- endif # NET_VENDOR_QUALCOMM
---- a/drivers/net/ethernet/qualcomm/Makefile
-+++ b/drivers/net/ethernet/qualcomm/Makefile
-@@ -6,3 +6,4 @@ obj-$(CONFIG_QCA7000) += qcaspi.o
- qcaspi-objs := qca_spi.o qca_framing.o qca_7k.o qca_debug.o
- obj-y += emac/
-+obj-$(CONFIG_ESSEDMA) += essedma/
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/essedma/Makefile
-@@ -0,0 +1,9 @@
-+#
-+## Makefile for the Qualcomm Atheros ethernet edma driver
-+#
-+
-+
-+obj-$(CONFIG_ESSEDMA) += essedma.o
-+
-+essedma-objs := edma_axi.o edma.o edma_ethtool.o
-+
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/essedma/edma.c
-@@ -0,0 +1,2168 @@
-+/*
-+ * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for
-+ * any purpose with or without fee is hereby granted, provided that the
-+ * above copyright notice and this permission notice appear in all copies.
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
-+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+#include <linux/platform_device.h>
-+#include <linux/if_vlan.h>
-+#include "ess_edma.h"
-+#include "edma.h"
-+
-+extern struct net_device *edma_netdev[EDMA_MAX_PORTID_SUPPORTED];
-+bool edma_stp_rstp;
-+u16 edma_ath_eth_type;
-+
-+/* edma_skb_priority_offset()
-+ *    get edma skb priority
-+ */
-+static unsigned int edma_skb_priority_offset(struct sk_buff *skb)
-+{
-+      return (skb->priority >> 2) & 1;
-+}
-+
-+/* edma_alloc_tx_ring()
-+ *    Allocate Tx descriptors ring
-+ */
-+static int edma_alloc_tx_ring(struct edma_common_info *edma_cinfo,
-+                            struct edma_tx_desc_ring *etdr)
-+{
-+      struct platform_device *pdev = edma_cinfo->pdev;
-+
-+      /* Initialize ring */
-+      etdr->size = sizeof(struct edma_sw_desc) * etdr->count;
-+      etdr->sw_next_to_fill = 0;
-+      etdr->sw_next_to_clean = 0;
-+
-+      /* Allocate SW descriptors */
-+      etdr->sw_desc = vzalloc(etdr->size);
-+      if (!etdr->sw_desc) {
-+              dev_err(&pdev->dev, "buffer alloc of tx ring failed=%p", etdr);
-+              return -ENOMEM;
-+      }
-+
-+      /* Allocate HW descriptors */
-+      etdr->hw_desc = dma_alloc_coherent(&pdev->dev, etdr->size, &etdr->dma,
-+                                        GFP_KERNEL);
-+      if (!etdr->hw_desc) {
-+              dev_err(&pdev->dev, "descriptor allocation for tx ring failed");
-+              vfree(etdr->sw_desc);
-+              return -ENOMEM;
-+      }
-+
-+      return 0;
-+}
-+
-+/* edma_free_tx_ring()
-+ *    Free tx rings allocated by edma_alloc_tx_rings
-+ */
-+static void edma_free_tx_ring(struct edma_common_info *edma_cinfo,
-+                            struct edma_tx_desc_ring *etdr)
-+{
-+      struct platform_device *pdev = edma_cinfo->pdev;
-+
-+      if (likely(etdr->dma))
-+              dma_free_coherent(&pdev->dev, etdr->size, etdr->hw_desc,
-+                               etdr->dma);
-+
-+      vfree(etdr->sw_desc);
-+      etdr->sw_desc = NULL;
-+}
-+
-+/* edma_alloc_rx_ring()
-+ *    allocate rx descriptor ring
-+ */
-+static int edma_alloc_rx_ring(struct edma_common_info *edma_cinfo,
-+                           struct edma_rfd_desc_ring *erxd)
-+{
-+      struct platform_device *pdev = edma_cinfo->pdev;
-+
-+      erxd->size = sizeof(struct edma_sw_desc) * erxd->count;
-+      erxd->sw_next_to_fill = 0;
-+      erxd->sw_next_to_clean = 0;
-+
-+      /* Allocate SW descriptors */
-+      erxd->sw_desc = vzalloc(erxd->size);
-+      if (!erxd->sw_desc)
-+              return -ENOMEM;
-+
-+      /* Alloc HW descriptors */
-+      erxd->hw_desc = dma_alloc_coherent(&pdev->dev, erxd->size, &erxd->dma,
-+                      GFP_KERNEL);
-+      if (!erxd->hw_desc) {
-+              vfree(erxd->sw_desc);
-+              return -ENOMEM;
-+      }
-+
-+      return 0;
-+}
-+
-+/* edma_free_rx_ring()
-+ *    Free rx ring allocated by alloc_rx_ring
-+ */
-+static void edma_free_rx_ring(struct edma_common_info *edma_cinfo,
-+                           struct edma_rfd_desc_ring *rxdr)
-+{
-+      struct platform_device *pdev = edma_cinfo->pdev;
-+
-+      if (likely(rxdr->dma))
-+              dma_free_coherent(&pdev->dev, rxdr->size, rxdr->hw_desc,
-+                               rxdr->dma);
-+
-+      vfree(rxdr->sw_desc);
-+      rxdr->sw_desc = NULL;
-+}
-+
-+/* edma_configure_tx()
-+ *    Configure transmission control data
-+ */
-+static void edma_configure_tx(struct edma_common_info *edma_cinfo)
-+{
-+      u32 txq_ctrl_data;
-+
-+      txq_ctrl_data = (EDMA_TPD_BURST << EDMA_TXQ_NUM_TPD_BURST_SHIFT);
-+      txq_ctrl_data |= EDMA_TXQ_CTRL_TPD_BURST_EN;
-+      txq_ctrl_data |= (EDMA_TXF_BURST << EDMA_TXQ_TXF_BURST_NUM_SHIFT);
-+      edma_write_reg(EDMA_REG_TXQ_CTRL, txq_ctrl_data);
-+}
-+
-+
-+/* edma_configure_rx()
-+ *    configure reception control data
-+ */
-+static void edma_configure_rx(struct edma_common_info *edma_cinfo)
-+{
-+      struct edma_hw *hw = &edma_cinfo->hw;
-+      u32 rss_type, rx_desc1, rxq_ctrl_data;
-+
-+      /* Set RSS type */
-+      rss_type = hw->rss_type;
-+      edma_write_reg(EDMA_REG_RSS_TYPE, rss_type);
-+
-+      /* Set RFD burst number */
-+      rx_desc1 = (EDMA_RFD_BURST << EDMA_RXQ_RFD_BURST_NUM_SHIFT);
-+
-+      /* Set RFD prefetch threshold */
-+      rx_desc1 |= (EDMA_RFD_THR << EDMA_RXQ_RFD_PF_THRESH_SHIFT);
-+
-+      /* Set RFD in host ring low threshold to generte interrupt */
-+      rx_desc1 |= (EDMA_RFD_LTHR << EDMA_RXQ_RFD_LOW_THRESH_SHIFT);
-+      edma_write_reg(EDMA_REG_RX_DESC1, rx_desc1);
-+
-+      /* Set Rx FIFO threshold to start to DMA data to host */
-+      rxq_ctrl_data = EDMA_FIFO_THRESH_128_BYTE;
-+
-+      /* Set RX remove vlan bit */
-+      rxq_ctrl_data |= EDMA_RXQ_CTRL_RMV_VLAN;
-+
-+      edma_write_reg(EDMA_REG_RXQ_CTRL, rxq_ctrl_data);
-+}
-+
-+/* edma_alloc_rx_buf()
-+ *    does skb allocation for the received packets.
-+ */
-+static int edma_alloc_rx_buf(struct edma_common_info
-+                           *edma_cinfo,
-+                           struct edma_rfd_desc_ring *erdr,
-+                           int cleaned_count, int queue_id)
-+{
-+      struct platform_device *pdev = edma_cinfo->pdev;
-+      struct edma_rx_free_desc *rx_desc;
-+      struct edma_sw_desc *sw_desc;
-+      struct sk_buff *skb;
-+      unsigned int i;
-+      u16 prod_idx, length;
-+      u32 reg_data;
-+
-+      if (cleaned_count > erdr->count) {
-+              dev_err(&pdev->dev, "Incorrect cleaned_count %d",
-+                     cleaned_count);
-+              return -1;
-+      }
-+
-+      i = erdr->sw_next_to_fill;
-+
-+      while (cleaned_count) {
-+              sw_desc = &erdr->sw_desc[i];
-+              length = edma_cinfo->rx_head_buffer_len;
-+
-+              if (sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_REUSE) {
-+                      skb = sw_desc->skb;
-+              } else {
-+                      /* alloc skb */
-+                      skb = netdev_alloc_skb(edma_netdev[0], length);
-+                      if (!skb) {
-+                              /* Better luck next round */
-+                              break;
-+                      }
-+              }
-+
-+              if (edma_cinfo->page_mode) {
-+                      struct page *pg = alloc_page(GFP_ATOMIC);
-+
-+                      if (!pg) {
-+                              dev_kfree_skb_any(skb);
-+                              break;
-+                      }
-+
-+                      sw_desc->dma = dma_map_page(&pdev->dev, pg, 0,
-+                                                 edma_cinfo->rx_page_buffer_len,
-+                                                 DMA_FROM_DEVICE);
-+                      if (dma_mapping_error(&pdev->dev,
-+                                  sw_desc->dma)) {
-+                              __free_page(pg);
-+                              dev_kfree_skb_any(skb);
-+                              break;
-+                      }
-+
-+                      skb_fill_page_desc(skb, 0, pg, 0,
-+                                         edma_cinfo->rx_page_buffer_len);
-+                      sw_desc->flags = EDMA_SW_DESC_FLAG_SKB_FRAG;
-+                      sw_desc->length = edma_cinfo->rx_page_buffer_len;
-+              } else {
-+                      sw_desc->dma = dma_map_single(&pdev->dev, skb->data,
-+                                                   length, DMA_FROM_DEVICE);
-+                      if (dma_mapping_error(&pdev->dev,
-+                         sw_desc->dma)) {
-+                              dev_kfree_skb_any(skb);
-+                              break;
-+                      }
-+
-+                      sw_desc->flags = EDMA_SW_DESC_FLAG_SKB_HEAD;
-+                      sw_desc->length = length;
-+              }
-+
-+              /* Update the buffer info */
-+              sw_desc->skb = skb;
-+              rx_desc = (&((struct edma_rx_free_desc *)(erdr->hw_desc))[i]);
-+              rx_desc->buffer_addr = cpu_to_le64(sw_desc->dma);
-+              if (++i == erdr->count)
-+                      i = 0;
-+              cleaned_count--;
-+      }
-+
-+      erdr->sw_next_to_fill = i;
-+
-+      if (i == 0)
-+              prod_idx = erdr->count - 1;
-+      else
-+              prod_idx = i - 1;
-+
-+      /* Update the producer index */
-+      edma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), &reg_data);
-+      reg_data &= ~EDMA_RFD_PROD_IDX_BITS;
-+      reg_data |= prod_idx;
-+      edma_write_reg(EDMA_REG_RFD_IDX_Q(queue_id), reg_data);
-+      return cleaned_count;
-+}
-+
-+/* edma_init_desc()
-+ *    update descriptor ring size, buffer and producer/consumer index
-+ */
-+static void edma_init_desc(struct edma_common_info *edma_cinfo)
-+{
-+      struct edma_rfd_desc_ring *rfd_ring;
-+      struct edma_tx_desc_ring *etdr;
-+      int i = 0, j = 0;
-+      u32 data = 0;
-+      u16 hw_cons_idx = 0;
-+
-+      /* Set the base address of every TPD ring. */
-+      for (i = 0; i < edma_cinfo->num_tx_queues; i++) {
-+              etdr = edma_cinfo->tpd_ring[i];
-+
-+              /* Update descriptor ring base address */
-+              edma_write_reg(EDMA_REG_TPD_BASE_ADDR_Q(i), (u32)etdr->dma);
-+              edma_read_reg(EDMA_REG_TPD_IDX_Q(i), &data);
-+
-+              /* Calculate hardware consumer index */
-+              hw_cons_idx = (data >> EDMA_TPD_CONS_IDX_SHIFT) & 0xffff;
-+              etdr->sw_next_to_fill = hw_cons_idx;
-+              etdr->sw_next_to_clean = hw_cons_idx;
-+              data &= ~(EDMA_TPD_PROD_IDX_MASK << EDMA_TPD_PROD_IDX_SHIFT);
-+              data |= hw_cons_idx;
-+
-+              /* update producer index */
-+              edma_write_reg(EDMA_REG_TPD_IDX_Q(i), data);
-+
-+              /* update SW consumer index register */
-+              edma_write_reg(EDMA_REG_TX_SW_CONS_IDX_Q(i), hw_cons_idx);
-+
-+              /* Set TPD ring size */
-+              edma_write_reg(EDMA_REG_TPD_RING_SIZE,
-+                             edma_cinfo->tx_ring_count &
-+                                  EDMA_TPD_RING_SIZE_MASK);
-+      }
-+
-+      for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {
-+              rfd_ring = edma_cinfo->rfd_ring[j];
-+              /* Update Receive Free descriptor ring base address */
-+              edma_write_reg(EDMA_REG_RFD_BASE_ADDR_Q(j),
-+                      (u32)(rfd_ring->dma));
-+              j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
-+      }
-+
-+      data = edma_cinfo->rx_head_buffer_len;
-+      if (edma_cinfo->page_mode)
-+              data = edma_cinfo->rx_page_buffer_len;
-+
-+      data &= EDMA_RX_BUF_SIZE_MASK;
-+      data <<= EDMA_RX_BUF_SIZE_SHIFT;
-+
-+      /* Update RFD ring size and RX buffer size */
-+      data |= (edma_cinfo->rx_ring_count & EDMA_RFD_RING_SIZE_MASK)
-+              << EDMA_RFD_RING_SIZE_SHIFT;
-+
-+      edma_write_reg(EDMA_REG_RX_DESC0, data);
-+
-+      /* Disable TX FIFO low watermark and high watermark */
-+      edma_write_reg(EDMA_REG_TXF_WATER_MARK, 0);
-+
-+      /* Load all of base address above */
-+      edma_read_reg(EDMA_REG_TX_SRAM_PART, &data);
-+      data |= 1 << EDMA_LOAD_PTR_SHIFT;
-+      edma_write_reg(EDMA_REG_TX_SRAM_PART, data);
-+}
-+
-+/* edma_receive_checksum
-+ *    Api to check checksum on receive packets
-+ */
-+static void edma_receive_checksum(struct edma_rx_return_desc *rd,
-+                                               struct sk_buff *skb)
-+{
-+      skb_checksum_none_assert(skb);
-+
-+      /* check the RRD IP/L4 checksum bit to see if
-+       * its set, which in turn indicates checksum
-+       * failure.
-+       */
-+      if (rd->rrd6 & EDMA_RRD_CSUM_FAIL_MASK)
-+              return;
-+
-+      skb->ip_summed = CHECKSUM_UNNECESSARY;
-+}
-+
-+/* edma_clean_rfd()
-+ *    clean up rx resourcers on error
-+ */
-+static void edma_clean_rfd(struct edma_rfd_desc_ring *erdr, u16 index)
-+{
-+      struct edma_rx_free_desc *rx_desc;
-+      struct edma_sw_desc *sw_desc;
-+
-+      rx_desc = (&((struct edma_rx_free_desc *)(erdr->hw_desc))[index]);
-+      sw_desc = &erdr->sw_desc[index];
-+      if (sw_desc->skb) {
-+              dev_kfree_skb_any(sw_desc->skb);
-+              sw_desc->skb = NULL;
-+      }
-+
-+      memset(rx_desc, 0, sizeof(struct edma_rx_free_desc));
-+}
-+
-+/* edma_rx_complete_fraglist()
-+ *    Complete Rx processing for fraglist skbs
-+ */
-+static void edma_rx_complete_stp_rstp(struct sk_buff *skb, int port_id, struct edma_rx_return_desc *rd)
-+{
-+      int i;
-+      u32 priority;
-+      u16 port_type;
-+      u8 mac_addr[EDMA_ETH_HDR_LEN];
-+
-+      port_type = (rd->rrd1 >> EDMA_RRD_PORT_TYPE_SHIFT)
-+                              & EDMA_RRD_PORT_TYPE_MASK;
-+      /* if port type is 0x4, then only proceed with
-+       * other stp/rstp calculation
-+       */
-+      if (port_type == EDMA_RX_ATH_HDR_RSTP_PORT_TYPE) {
-+              u8 bpdu_mac[6] = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x00};
-+
-+              /* calculate the frame priority */
-+              priority = (rd->rrd1 >> EDMA_RRD_PRIORITY_SHIFT)
-+                      & EDMA_RRD_PRIORITY_MASK;
-+
-+              for (i = 0; i < EDMA_ETH_HDR_LEN; i++)
-+                      mac_addr[i] = skb->data[i];
-+
-+              /* Check if destination mac addr is bpdu addr */
-+              if (!memcmp(mac_addr, bpdu_mac, 6)) {
-+                      /* destination mac address is BPDU
-+                       * destination mac address, then add
-+                       * atheros header to the packet.
-+                       */
-+                      u16 athr_hdr = (EDMA_RX_ATH_HDR_VERSION << EDMA_RX_ATH_HDR_VERSION_SHIFT) |
-+                              (priority << EDMA_RX_ATH_HDR_PRIORITY_SHIFT) |
-+                              (EDMA_RX_ATH_HDR_RSTP_PORT_TYPE << EDMA_RX_ATH_PORT_TYPE_SHIFT) | port_id;
-+                      skb_push(skb, 4);
-+                      memcpy(skb->data, mac_addr, EDMA_ETH_HDR_LEN);
-+                      *(uint16_t *)&skb->data[12] = htons(edma_ath_eth_type);
-+                      *(uint16_t *)&skb->data[14] = htons(athr_hdr);
-+              }
-+      }
-+}
-+
-+/*
-+ * edma_rx_complete_fraglist()
-+ *    Complete Rx processing for fraglist skbs
-+ */
-+static int edma_rx_complete_fraglist(struct sk_buff *skb, u16 num_rfds, u16 length, u32 sw_next_to_clean,
-+                                      u16 *cleaned_count, struct edma_rfd_desc_ring *erdr, struct edma_common_info *edma_cinfo)
-+{
-+      struct platform_device *pdev = edma_cinfo->pdev;
-+      struct edma_hw *hw = &edma_cinfo->hw;
-+      struct sk_buff *skb_temp;
-+      struct edma_sw_desc *sw_desc;
-+      int i;
-+      u16 size_remaining;
-+
-+      skb->data_len = 0;
-+      skb->tail += (hw->rx_head_buff_size - 16);
-+      skb->len = skb->truesize = length;
-+      size_remaining = length - (hw->rx_head_buff_size - 16);
-+
-+      /* clean-up all related sw_descs */
-+      for (i = 1; i < num_rfds; i++) {
-+              struct sk_buff *skb_prev;
-+              sw_desc = &erdr->sw_desc[sw_next_to_clean];
-+              skb_temp = sw_desc->skb;
-+
-+              dma_unmap_single(&pdev->dev, sw_desc->dma,
-+                      sw_desc->length, DMA_FROM_DEVICE);
-+
-+              if (size_remaining < hw->rx_head_buff_size)
-+                      skb_put(skb_temp, size_remaining);
-+              else
-+                      skb_put(skb_temp, hw->rx_head_buff_size);
-+
-+              /*
-+               * If we are processing the first rfd, we link
-+               * skb->frag_list to the skb corresponding to the
-+               * first RFD
-+               */
-+              if (i == 1)
-+                      skb_shinfo(skb)->frag_list = skb_temp;
-+              else
-+                      skb_prev->next = skb_temp;
-+              skb_prev = skb_temp;
-+              skb_temp->next = NULL;
-+
-+              skb->data_len += skb_temp->len;
-+              size_remaining -= skb_temp->len;
-+
-+              /* Increment SW index */
-+              sw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1);
-+              (*cleaned_count)++;
-+      }
-+
-+      return sw_next_to_clean;
-+}
-+
-+/* edma_rx_complete_paged()
-+ *    Complete Rx processing for paged skbs
-+ */
-+static int edma_rx_complete_paged(struct sk_buff *skb, u16 num_rfds, u16 length, u32 sw_next_to_clean,
-+                                      u16 *cleaned_count, struct edma_rfd_desc_ring *erdr, struct edma_common_info *edma_cinfo)
-+{
-+      struct platform_device *pdev = edma_cinfo->pdev;
-+      struct sk_buff *skb_temp;
-+      struct edma_sw_desc *sw_desc;
-+      int i;
-+      u16 size_remaining;
-+
-+      skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
-+
-+      /* Setup skbuff fields */
-+      skb->len = length;
-+
-+      if (likely(num_rfds <= 1)) {
-+              skb->data_len = length;
-+              skb->truesize += edma_cinfo->rx_page_buffer_len;
-+              skb_fill_page_desc(skb, 0, skb_frag_page(frag),
-+                              16, length);
-+      } else {
-+              frag->size -= 16;
-+              skb->data_len = frag->size;
-+              skb->truesize += edma_cinfo->rx_page_buffer_len;
-+              size_remaining = length - frag->size;
-+
-+              skb_fill_page_desc(skb, 0, skb_frag_page(frag),
-+                              16, frag->size);
-+
-+              /* clean-up all related sw_descs */
-+              for (i = 1; i < num_rfds; i++) {
-+                      sw_desc = &erdr->sw_desc[sw_next_to_clean];
-+                      skb_temp = sw_desc->skb;
-+                      frag = &skb_shinfo(skb_temp)->frags[0];
-+                      dma_unmap_page(&pdev->dev, sw_desc->dma,
-+                              sw_desc->length, DMA_FROM_DEVICE);
-+
-+                      if (size_remaining < edma_cinfo->rx_page_buffer_len)
-+                              frag->size = size_remaining;
-+
-+                      skb_fill_page_desc(skb, i, skb_frag_page(frag),
-+                                      0, frag->size);
-+
-+                      skb_shinfo(skb_temp)->nr_frags = 0;
-+                      dev_kfree_skb_any(skb_temp);
-+
-+                      skb->data_len += frag->size;
-+                      skb->truesize += edma_cinfo->rx_page_buffer_len;
-+                      size_remaining -= frag->size;
-+
-+                      /* Increment SW index */
-+                      sw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1);
-+                      (*cleaned_count)++;
-+              }
-+      }
-+
-+      return sw_next_to_clean;
-+}
-+
-+/*
-+ * edma_rx_complete()
-+ *    Main api called from the poll function to process rx packets.
-+ */
-+static void edma_rx_complete(struct edma_common_info *edma_cinfo,
-+                          int *work_done, int work_to_do, int queue_id,
-+                          struct napi_struct *napi)
-+{
-+      struct platform_device *pdev = edma_cinfo->pdev;
-+      struct edma_rfd_desc_ring *erdr = edma_cinfo->rfd_ring[queue_id];
-+      struct net_device *netdev;
-+      struct edma_adapter *adapter;
-+      struct edma_sw_desc *sw_desc;
-+      struct sk_buff *skb;
-+      struct edma_rx_return_desc *rd;
-+      u16 hash_type, rrd[8], cleaned_count = 0, length = 0, num_rfds = 1,
-+          sw_next_to_clean, hw_next_to_clean = 0, vlan = 0, ret_count = 0;
-+      u32 data = 0;
-+      u8 *vaddr;
-+      int port_id, i, drop_count = 0;
-+      u32 priority;
-+      u16 count = erdr->count, rfd_avail;
-+      u8 queue_to_rxid[8] = {0, 0, 1, 1, 2, 2, 3, 3};
-+
-+      sw_next_to_clean = erdr->sw_next_to_clean;
-+
-+      edma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), &data);
-+      hw_next_to_clean = (data >> EDMA_RFD_CONS_IDX_SHIFT) &
-+                         EDMA_RFD_CONS_IDX_MASK;
-+
-+      do {
-+              while (sw_next_to_clean != hw_next_to_clean) {
-+                      if (!work_to_do)
-+                              break;
-+
-+                      sw_desc = &erdr->sw_desc[sw_next_to_clean];
-+                      skb = sw_desc->skb;
-+
-+                      /* Unmap the allocated buffer */
-+                      if (likely(sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_HEAD))
-+                              dma_unmap_single(&pdev->dev, sw_desc->dma,
-+                                              sw_desc->length, DMA_FROM_DEVICE);
-+                      else
-+                              dma_unmap_page(&pdev->dev, sw_desc->dma,
-+                                            sw_desc->length, DMA_FROM_DEVICE);
-+
-+                      /* Get RRD */
-+                      if (edma_cinfo->page_mode) {
-+                              vaddr = kmap_atomic(skb_frag_page(&skb_shinfo(skb)->frags[0]));
-+                              memcpy((uint8_t *)&rrd[0], vaddr, 16);
-+                              rd = (struct edma_rx_return_desc *)rrd;
-+                              kunmap_atomic(vaddr);
-+                      } else {
-+                              rd = (struct edma_rx_return_desc *)skb->data;
-+                      }
-+
-+                      /* Check if RRD is valid */
-+                      if (!(rd->rrd7 & EDMA_RRD_DESC_VALID)) {
-+                              edma_clean_rfd(erdr, sw_next_to_clean);
-+                              sw_next_to_clean = (sw_next_to_clean + 1) &
-+                                                 (erdr->count - 1);
-+                              cleaned_count++;
-+                              continue;
-+                      }
-+
-+                      /* Get the number of RFDs from RRD */
-+                      num_rfds = rd->rrd1 & EDMA_RRD_NUM_RFD_MASK;
-+
-+                      /* Get Rx port ID from switch */
-+                      port_id = (rd->rrd1 >> EDMA_PORT_ID_SHIFT) & EDMA_PORT_ID_MASK;
-+                      if ((!port_id) || (port_id > EDMA_MAX_PORTID_SUPPORTED)) {
-+                              dev_err(&pdev->dev, "Invalid RRD source port bit set");
-+                              for (i = 0; i < num_rfds; i++) {
-+                                      edma_clean_rfd(erdr, sw_next_to_clean);
-+                                      sw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1);
-+                                      cleaned_count++;
-+                              }
-+                              continue;
-+                      }
-+
-+                      /* check if we have a sink for the data we receive.
-+                       * If the interface isn't setup, we have to drop the
-+                       * incoming data for now.
-+                       */
-+                      netdev = edma_cinfo->portid_netdev_lookup_tbl[port_id];
-+                      if (!netdev) {
-+                              edma_clean_rfd(erdr, sw_next_to_clean);
-+                              sw_next_to_clean = (sw_next_to_clean + 1) &
-+                                                 (erdr->count - 1);
-+                              cleaned_count++;
-+                              continue;
-+                      }
-+                      adapter = netdev_priv(netdev);
-+
-+                      /* This code is added to handle a usecase where high
-+                       * priority stream and a low priority stream are
-+                       * received simultaneously on DUT. The problem occurs
-+                       * if one of the  Rx rings is full and the corresponding
-+                       * core is busy with other stuff. This causes ESS CPU
-+                       * port to backpressure all incoming traffic including
-+                       * high priority one. We monitor free descriptor count
-+                       * on each CPU and whenever it reaches threshold (< 80),
-+                       * we drop all low priority traffic and let only high
-+                       * priotiy traffic pass through. We can hence avoid
-+                       * ESS CPU port to send backpressure on high priroity
-+                       * stream.
-+                       */
-+                      priority = (rd->rrd1 >> EDMA_RRD_PRIORITY_SHIFT)
-+                              & EDMA_RRD_PRIORITY_MASK;
-+                      if (likely(!priority && !edma_cinfo->page_mode && (num_rfds <= 1))) {
-+                              rfd_avail = (count + sw_next_to_clean - hw_next_to_clean - 1) & (count - 1);
-+                              if (rfd_avail < EDMA_RFD_AVAIL_THR) {
-+                                      sw_desc->flags = EDMA_SW_DESC_FLAG_SKB_REUSE;
-+                                      sw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1);
-+                                      adapter->stats.rx_dropped++;
-+                                      cleaned_count++;
-+                                      drop_count++;
-+                                      if (drop_count == 3) {
-+                                              work_to_do--;
-+                                              (*work_done)++;
-+                                              drop_count = 0;
-+                                      }
-+                                      if (cleaned_count == EDMA_RX_BUFFER_WRITE) {
-+                                              /* If buffer clean count reaches 16, we replenish HW buffers. */
-+                                              ret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id);
-+                                              edma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id),
-+                                                            sw_next_to_clean);
-+                                              cleaned_count = ret_count;
-+                                      }
-+                                      continue;
-+                              }
-+                      }
-+
-+                      work_to_do--;
-+                      (*work_done)++;
-+
-+                      /* Increment SW index */
-+                      sw_next_to_clean = (sw_next_to_clean + 1) &
-+                                         (erdr->count - 1);
-+
-+                      cleaned_count++;
-+
-+                      /* Get the packet size and allocate buffer */
-+                      length = rd->rrd6 & EDMA_RRD_PKT_SIZE_MASK;
-+
-+                      if (edma_cinfo->page_mode) {
-+                              /* paged skb */
-+                              sw_next_to_clean = edma_rx_complete_paged(skb, num_rfds, length, sw_next_to_clean, &cleaned_count, erdr, edma_cinfo);
-+                              if (!pskb_may_pull(skb, ETH_HLEN)) {
-+                                      dev_kfree_skb_any(skb);
-+                                      continue;
-+                              }
-+                      } else {
-+                              /* single or fraglist skb */
-+
-+                              /* Addition of 16 bytes is required, as in the packet
-+                               * first 16 bytes are rrd descriptors, so actual data
-+                               * starts from an offset of 16.
-+                               */
-+                              skb_reserve(skb, 16);
-+                              if (likely((num_rfds <= 1) || !edma_cinfo->fraglist_mode)) {
-+                                      skb_put(skb, length);
-+                              } else {
-+                                      sw_next_to_clean = edma_rx_complete_fraglist(skb, num_rfds, length, sw_next_to_clean, &cleaned_count, erdr, edma_cinfo);
-+                              }
-+                      }
-+
-+                      if (edma_stp_rstp) {
-+                              edma_rx_complete_stp_rstp(skb, port_id, rd);
-+                      }
-+
-+                      skb->protocol = eth_type_trans(skb, netdev);
-+
-+                      /* Record Rx queue for RFS/RPS and fill flow hash from HW */
-+                      skb_record_rx_queue(skb, queue_to_rxid[queue_id]);
-+                      if (netdev->features & NETIF_F_RXHASH) {
-+                              hash_type = (rd->rrd5 >> EDMA_HASH_TYPE_SHIFT);
-+                              if ((hash_type > EDMA_HASH_TYPE_START) && (hash_type < EDMA_HASH_TYPE_END))
-+                                      skb_set_hash(skb, rd->rrd2, PKT_HASH_TYPE_L4);
-+                      }
-+
-+#ifdef CONFIG_NF_FLOW_COOKIE
-+                      skb->flow_cookie = rd->rrd3 & EDMA_RRD_FLOW_COOKIE_MASK;
-+#endif
-+                      edma_receive_checksum(rd, skb);
-+
-+                      /* Process VLAN HW acceleration indication provided by HW */
-+                      if (unlikely(adapter->default_vlan_tag != rd->rrd4)) {
-+                              vlan = rd->rrd4;
-+                              if (likely(rd->rrd7 & EDMA_RRD_CVLAN))
-+                                      __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan);
-+                              else if (rd->rrd1 & EDMA_RRD_SVLAN)
-+                                      __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), vlan);
-+                      }
-+
-+                      /* Update rx statistics */
-+                      adapter->stats.rx_packets++;
-+                      adapter->stats.rx_bytes += length;
-+
-+                      /* Check if we reached refill threshold */
-+                      if (cleaned_count == EDMA_RX_BUFFER_WRITE) {
-+                              ret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id);
-+                              edma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id),
-+                                            sw_next_to_clean);
-+                              cleaned_count = ret_count;
-+                      }
-+
-+                      /* At this point skb should go to stack */
-+                      napi_gro_receive(napi, skb);
-+              }
-+
-+              /* Check if we still have NAPI budget */
-+              if (!work_to_do)
-+                      break;
-+
-+              /* Read index once again since we still have NAPI budget */
-+              edma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), &data);
-+              hw_next_to_clean = (data >> EDMA_RFD_CONS_IDX_SHIFT) &
-+                      EDMA_RFD_CONS_IDX_MASK;
-+      } while (hw_next_to_clean != sw_next_to_clean);
-+
-+      erdr->sw_next_to_clean = sw_next_to_clean;
-+
-+      /* Refill here in case refill threshold wasn't reached */
-+      if (likely(cleaned_count)) {
-+              ret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id);
-+              if (ret_count)
-+                      dev_dbg(&pdev->dev, "Not all buffers was reallocated");
-+              edma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id),
-+                            erdr->sw_next_to_clean);
-+      }
-+}
-+
-+/* edma_delete_rfs_filter()
-+ *    Remove RFS filter from switch
-+ */
-+static int edma_delete_rfs_filter(struct edma_adapter *adapter,
-+                               struct edma_rfs_filter_node *filter_node)
-+{
-+      int res = -1;
-+
-+      struct flow_keys *keys = &filter_node->keys;
-+
-+      if (likely(adapter->set_rfs_rule))
-+              res = (*adapter->set_rfs_rule)(adapter->netdev,
-+                      flow_get_u32_src(keys), flow_get_u32_dst(keys),
-+                      keys->ports.src, keys->ports.dst,
-+                      keys->basic.ip_proto, filter_node->rq_id, 0);
-+
-+      return res;
-+}
-+
-+/* edma_add_rfs_filter()
-+ *    Add RFS filter to switch
-+ */
-+static int edma_add_rfs_filter(struct edma_adapter *adapter,
-+                             struct flow_keys *keys, u16 rq,
-+                             struct edma_rfs_filter_node *filter_node)
-+{
-+      int res = -1;
-+
-+      struct flow_keys *dest_keys = &filter_node->keys;
-+
-+      memcpy(dest_keys, &filter_node->keys, sizeof(*dest_keys));
-+/*
-+      dest_keys->control = keys->control;
-+      dest_keys->basic = keys->basic;
-+      dest_keys->addrs = keys->addrs;
-+      dest_keys->ports = keys->ports;
-+      dest_keys.ip_proto = keys->ip_proto;
-+*/
-+      /* Call callback registered by ESS driver */
-+      if (likely(adapter->set_rfs_rule))
-+              res = (*adapter->set_rfs_rule)(adapter->netdev, flow_get_u32_src(keys),
-+                    flow_get_u32_dst(keys), keys->ports.src, keys->ports.dst,
-+                    keys->basic.ip_proto, rq, 1);
-+
-+      return res;
-+}
-+
-+/* edma_rfs_key_search()
-+ *    Look for&