move danube folder to ifxmips, to allow future integration of the other chips
authorJohn Crispin <john@openwrt.org>
Thu, 20 Dec 2007 22:29:45 +0000 (22:29 +0000)
committerJohn Crispin <john@openwrt.org>
Thu, 20 Dec 2007 22:29:45 +0000 (22:29 +0000)
SVN-Revision: 9815

39 files changed:
target/linux/ifxmips/Makefile [new file with mode: 0644]
target/linux/ifxmips/base-files/etc/config/network [new file with mode: 0644]
target/linux/ifxmips/config-2.6.23 [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/danube/Kconfig [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/danube/Makefile [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/danube/dma-core.c [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/danube/interrupt.c [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/danube/pci.c [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/danube/pmu.c [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/danube/prom.c [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/danube/reset.c [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/danube/setup.c [new file with mode: 0644]
target/linux/ifxmips/files/drivers/char/danube_eeprom.c [new file with mode: 0644]
target/linux/ifxmips/files/drivers/char/danube_gpio.c [new file with mode: 0644]
target/linux/ifxmips/files/drivers/char/danube_led.c [new file with mode: 0644]
target/linux/ifxmips/files/drivers/char/danube_ssc.c [new file with mode: 0644]
target/linux/ifxmips/files/drivers/char/watchdog/danube_wdt.c [new file with mode: 0644]
target/linux/ifxmips/files/drivers/mtd/maps/danube.c [new file with mode: 0644]
target/linux/ifxmips/files/drivers/net/danube_mii0.c [new file with mode: 0644]
target/linux/ifxmips/files/drivers/serial/danube_asc.c [new file with mode: 0644]
target/linux/ifxmips/files/include/asm-mips/danube/danube.h [new file with mode: 0644]
target/linux/ifxmips/files/include/asm-mips/danube/danube_dma.h [new file with mode: 0644]
target/linux/ifxmips/files/include/asm-mips/danube/danube_gpio.h [new file with mode: 0644]
target/linux/ifxmips/files/include/asm-mips/danube/danube_ioctl.h [new file with mode: 0644]
target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h [new file with mode: 0644]
target/linux/ifxmips/files/include/asm-mips/danube/danube_mii0.h [new file with mode: 0644]
target/linux/ifxmips/files/include/asm-mips/danube/danube_orig.h [new file with mode: 0644]
target/linux/ifxmips/files/include/asm-mips/danube/danube_pmu.h [new file with mode: 0644]
target/linux/ifxmips/files/include/asm-mips/danube/danube_serial.h [new file with mode: 0644]
target/linux/ifxmips/files/include/asm-mips/danube/danube_wdt.h [new file with mode: 0644]
target/linux/ifxmips/files/include/asm-mips/danube/ifx_peripheral_definitions.h [new file with mode: 0644]
target/linux/ifxmips/files/include/asm-mips/danube/ifx_ssc.h [new file with mode: 0644]
target/linux/ifxmips/files/include/asm-mips/danube/ifx_ssc_defines.h [new file with mode: 0644]
target/linux/ifxmips/files/include/asm-mips/mach-danube/irq.h [new file with mode: 0644]
target/linux/ifxmips/image/Makefile [new file with mode: 0644]
target/linux/ifxmips/patches/100-board.patch [new file with mode: 0644]
target/linux/ifxmips/patches/110-drivers.patch [new file with mode: 0644]
target/linux/ifxmips/patches/160-cfi-swap.patch [new file with mode: 0644]
target/linux/ifxmips/series [new file with mode: 0644]

diff --git a/target/linux/ifxmips/Makefile b/target/linux/ifxmips/Makefile
new file mode 100644 (file)
index 0000000..1818e6b
--- /dev/null
@@ -0,0 +1,21 @@
+# 
+# Copyright (C) 2007 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+include $(TOPDIR)/rules.mk
+
+ARCH:=mips
+BOARD:=ifxmips
+BOARDNAME:=Infineon Mips
+FEATURES:=squashfs jffs2 broken
+LINUX_VERSION:=2.6.23
+
+include $(INCLUDE_DIR)/target.mk
+
+define Target/Description
+       Build firmware images for Infineon Mips Controllers
+endef
+
+$(eval $(call BuildTarget))
diff --git a/target/linux/ifxmips/base-files/etc/config/network b/target/linux/ifxmips/base-files/etc/config/network
new file mode 100644 (file)
index 0000000..eb01cdd
--- /dev/null
@@ -0,0 +1,14 @@
+# Copyright (C) 2006 OpenWrt.org
+
+config interface loopback
+       option ifname   lo
+       option proto    static
+       option ipaddr   127.0.0.1
+       option netmask  255.0.0.0
+
+config interface lan
+       option ifname   eth0
+       #option type            bridge
+       option proto    static
+       option ipaddr   192.168.45.110
+       option netmask  255.255.255.0
diff --git a/target/linux/ifxmips/config-2.6.23 b/target/linux/ifxmips/config-2.6.23
new file mode 100644 (file)
index 0000000..8875193
--- /dev/null
@@ -0,0 +1,190 @@
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+# CONFIG_8139TOO is not set
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_ATM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_BITREVERSE=y
+# CONFIG_BT is not set
+CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2 init=/etc/preinit"
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+# CONFIG_CPU_LOONGSON2 is not set
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+CONFIG_CPU_MIPSR1=y
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CRYPTO_HW is not set
+CONFIG_DANUBE=y
+CONFIG_DANUBE_ASC_UART=y
+CONFIG_DANUBE_EEPROM=y
+CONFIG_DANUBE_GPIO=y
+CONFIG_DANUBE_LED=y
+CONFIG_DANUBE_MII0=y
+CONFIG_DANUBE_MII1=y
+CONFIG_DANUBE_SSC=y
+CONFIG_DANUBE_WDT=y
+CONFIG_DEVPORT=y
+# CONFIG_DM9000 is not set
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+# CONFIG_HOSTAP is not set
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=y
+# CONFIG_I2C is not set
+# CONFIG_IDE is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQ_CPU=y
+CONFIG_KALLSYMS=y
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_VR41XX is not set
+CONFIG_MIPS=y
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_COBALT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MALTA is not set
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+CONFIG_MTD=y
+# CONFIG_MTD_ABSENT is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK2MTD is not set
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_CHAR=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_DANUBE=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_JEDECPROBE is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_ONENAND is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_PHRAM is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_BANKWIDTH=0
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_START=0x0
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_RTC is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_SCSI_WAIT_SCAN=m
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_DANUBE=y
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_PTSWARM is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+# CONFIG_TC35815 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+CONFIG_TRAD_SIGNALS=y
+# CONFIG_USBPCWATCHDOG is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USER_NS is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIA_RHINE is not set
+CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/ifxmips/files/arch/mips/danube/Kconfig b/target/linux/ifxmips/files/arch/mips/danube/Kconfig
new file mode 100644 (file)
index 0000000..1c5ad72
--- /dev/null
@@ -0,0 +1,36 @@
+# copyright 2007 john crispin <blogic@openwrt.org>
+
+menu "Danube built-in"
+
+config DANUBE_ASC_UART
+       bool "Danube asc uart"
+       select SERIAL_CORE
+       select SERIAL_CORE_CONSOLE
+       default y
+
+config MTD_DANUBE
+       bool "Danube flash map"
+       default y
+
+config DANUBE_WDT
+       bool "Danube watchdog"
+       default y
+
+config DANUBE_LED
+       bool "Danube led"
+       default y
+
+config DANUBE_GPIO
+       bool "Danube gpio"
+       default y
+
+config DANUBE_SSC
+       bool "Danube ssc"
+       default y
+
+config DANUBE_EEPROM
+       bool "Danube eeprom"
+       default y
+
+endmenu
+
diff --git a/target/linux/ifxmips/files/arch/mips/danube/Makefile b/target/linux/ifxmips/files/arch/mips/danube/Makefile
new file mode 100644 (file)
index 0000000..fed8f2f
--- /dev/null
@@ -0,0 +1,10 @@
+#
+#  Copyright 2007 openwrt.org
+#       John Crispin <blogic@openwrt.org>
+#
+# Makefile for Infineon Danube
+#
+obj-y := reset.o prom.o setup.o interrupt.o dma-core.o
+
+obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_KGDB) += kgdb_serial.o
diff --git a/target/linux/ifxmips/files/arch/mips/danube/dma-core.c b/target/linux/ifxmips/files/arch/mips/danube/dma-core.c
new file mode 100644 (file)
index 0000000..7d29dbd
--- /dev/null
@@ -0,0 +1,758 @@
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/fs.h>
+#include <linux/errno.h>
+#include <linux/stat.h>
+#include <linux/mm.h>
+#include <linux/tty.h>
+#include <linux/selection.h>
+#include <linux/kmod.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <asm/uaccess.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+
+#include <asm/danube/danube.h>
+#include <asm/danube/danube_irq.h>
+#include <asm/danube/danube_dma.h>
+#include <asm/danube/danube_pmu.h>
+
+/*25 descriptors for each dma channel,4096/8/20=25.xx*/
+#define DANUBE_DMA_DESCRIPTOR_OFFSET 25
+
+#define MAX_DMA_DEVICE_NUM  6  /*max ports connecting to dma */
+#define MAX_DMA_CHANNEL_NUM 20 /*max dma channels */
+#define DMA_INT_BUDGET      100        /*budget for interrupt handling */
+#define DMA_POLL_COUNTER    4  /*fix me, set the correct counter value here! */
+
+extern void mask_and_ack_danube_irq (unsigned int irq_nr);
+extern void enable_danube_irq (unsigned int irq_nr);
+extern void disable_danube_irq (unsigned int irq_nr);
+
+u64 *g_desc_list;
+_dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
+_dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM];
+
+char global_device_name[MAX_DMA_DEVICE_NUM][20] =
+       { {"PPE"}, {"DEU"}, {"SPI"}, {"SDIO"}, {"MCTRL0"}, {"MCTRL1"} };
+
+_dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
+       {"PPE", DANUBE_DMA_RX, 0, DANUBE_DMA_CH0_INT, 0},
+       {"PPE", DANUBE_DMA_TX, 0, DANUBE_DMA_CH1_INT, 0},
+       {"PPE", DANUBE_DMA_RX, 1, DANUBE_DMA_CH2_INT, 1},
+       {"PPE", DANUBE_DMA_TX, 1, DANUBE_DMA_CH3_INT, 1},
+       {"PPE", DANUBE_DMA_RX, 2, DANUBE_DMA_CH4_INT, 2},
+       {"PPE", DANUBE_DMA_TX, 2, DANUBE_DMA_CH5_INT, 2},
+       {"PPE", DANUBE_DMA_RX, 3, DANUBE_DMA_CH6_INT, 3},
+       {"PPE", DANUBE_DMA_TX, 3, DANUBE_DMA_CH7_INT, 3},
+       {"DEU", DANUBE_DMA_RX, 0, DANUBE_DMA_CH8_INT, 0},
+       {"DEU", DANUBE_DMA_TX, 0, DANUBE_DMA_CH9_INT, 0},
+       {"DEU", DANUBE_DMA_RX, 1, DANUBE_DMA_CH10_INT, 1},
+       {"DEU", DANUBE_DMA_TX, 1, DANUBE_DMA_CH11_INT, 1},
+       {"SPI", DANUBE_DMA_RX, 0, DANUBE_DMA_CH12_INT, 0},
+       {"SPI", DANUBE_DMA_TX, 0, DANUBE_DMA_CH13_INT, 0},
+       {"SDIO", DANUBE_DMA_RX, 0, DANUBE_DMA_CH14_INT, 0},
+       {"SDIO", DANUBE_DMA_TX, 0, DANUBE_DMA_CH15_INT, 0},
+       {"MCTRL0", DANUBE_DMA_RX, 0, DANUBE_DMA_CH16_INT, 0},
+       {"MCTRL0", DANUBE_DMA_TX, 0, DANUBE_DMA_CH17_INT, 0},
+       {"MCTRL1", DANUBE_DMA_RX, 1, DANUBE_DMA_CH18_INT, 1},
+       {"MCTRL1", DANUBE_DMA_TX, 1, DANUBE_DMA_CH19_INT, 1}
+};
+
+_dma_chan_map *chan_map = default_dma_map;
+volatile u32 g_danube_dma_int_status = 0;
+volatile int g_danube_dma_in_process = 0;/*0=not in process,1=in process*/
+
+void do_dma_tasklet (unsigned long);
+DECLARE_TASKLET (dma_tasklet, do_dma_tasklet, 0);
+
+u8*
+common_buffer_alloc (int len, int *byte_offset, void **opt)
+{
+       u8 *buffer = (u8 *) kmalloc (len * sizeof (u8), GFP_KERNEL);
+
+       *byte_offset = 0;
+
+       return buffer;
+}
+
+void
+common_buffer_free (u8 *dataptr, void *opt)
+{
+       if (dataptr)
+               kfree(dataptr);
+}
+
+void
+enable_ch_irq (_dma_channel_info *pCh)
+{
+       int chan_no = (int)(pCh - dma_chan);
+       int flag;
+
+       local_irq_save(flag);
+       writel(chan_no, DANUBE_DMA_CS);
+       writel(0x4a, DANUBE_DMA_CIE);
+       writel(readl(DANUBE_DMA_IRNEN) | (1 << chan_no), DANUBE_DMA_IRNEN);
+       local_irq_restore(flag);
+       enable_danube_irq(pCh->irq);
+}
+
+void
+disable_ch_irq (_dma_channel_info *pCh)
+{
+       int flag;
+       int chan_no = (int) (pCh - dma_chan);
+
+       local_irq_save(flag);
+       g_danube_dma_int_status &= ~(1 << chan_no);
+       writel(chan_no, DANUBE_DMA_CS);
+       writel(0, DANUBE_DMA_CIE);
+       writel(readl(DANUBE_DMA_IRNEN) & ~(1 << chan_no), DANUBE_DMA_IRNEN);
+       local_irq_restore(flag);
+       mask_and_ack_danube_irq(pCh->irq);
+}
+
+void
+open_chan (_dma_channel_info *pCh)
+{
+       int flag;
+       int chan_no = (int)(pCh - dma_chan);
+
+       local_irq_save(flag);
+       writel(chan_no, DANUBE_DMA_CS);
+       writel(readl(DANUBE_DMA_CCTRL) | 1, DANUBE_DMA_CCTRL);
+       if(pCh->dir == DANUBE_DMA_RX)
+               enable_ch_irq(pCh);
+       local_irq_restore(flag);
+}
+
+void
+close_chan(_dma_channel_info *pCh)
+{
+       int flag;
+       int chan_no = (int) (pCh - dma_chan);
+
+       local_irq_save(flag);
+       writel(chan_no, DANUBE_DMA_CS);
+       writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
+       disable_ch_irq(pCh);
+       local_irq_restore(flag);
+}
+
+void
+reset_chan (_dma_channel_info *pCh)
+{
+       int chan_no = (int) (pCh - dma_chan);
+
+       writel(chan_no, DANUBE_DMA_CS);
+       writel(readl(DANUBE_DMA_CCTRL) | 2, DANUBE_DMA_CCTRL);
+}
+
+void
+rx_chan_intr_handler (int chan_no)
+{
+       _dma_device_info *pDev = (_dma_device_info *)dma_chan[chan_no].dma_dev;
+       _dma_channel_info *pCh = &dma_chan[chan_no];
+       struct rx_desc *rx_desc_p;
+       int tmp;
+       int flag;
+
+       /*handle command complete interrupt */
+       rx_desc_p = (struct rx_desc*)pCh->desc_base + pCh->curr_desc;
+       if (rx_desc_p->status.field.OWN == CPU_OWN
+           && rx_desc_p->status.field.C
+           && rx_desc_p->status.field.data_length < 1536){
+               /*Every thing is correct, then we inform the upper layer */
+               pDev->current_rx_chan = pCh->rel_chan_no;
+               if(pDev->intr_handler)
+                       pDev->intr_handler(pDev, RCV_INT);
+               pCh->weight--;
+       } else {
+               local_irq_save(flag);
+               tmp = readl(DANUBE_DMA_CS);
+               writel(chan_no, DANUBE_DMA_CS);
+               writel(readl(DANUBE_DMA_CIS) | 0x7e, DANUBE_DMA_CIS);
+               writel(tmp, DANUBE_DMA_CS);
+               g_danube_dma_int_status &= ~(1 << chan_no);
+               local_irq_restore(flag);
+               enable_danube_irq(dma_chan[chan_no].irq);
+       }
+}
+
+inline void
+tx_chan_intr_handler (int chan_no)
+{
+       _dma_device_info *pDev = (_dma_device_info*)dma_chan[chan_no].dma_dev;
+       _dma_channel_info *pCh = &dma_chan[chan_no];
+    int tmp;
+    int flag;
+
+    local_irq_save(flag);
+    tmp = readl(DANUBE_DMA_CS);
+    writel(chan_no, DANUBE_DMA_CS);
+    writel(readl(DANUBE_DMA_CIS) | 0x7e, DANUBE_DMA_CIS);
+    writel(tmp, DANUBE_DMA_CS);
+    g_danube_dma_int_status &= ~(1 << chan_no);
+    local_irq_restore(flag);
+       pDev->current_tx_chan = pCh->rel_chan_no;
+       if (pDev->intr_handler)
+               pDev->intr_handler(pDev, TRANSMIT_CPT_INT);
+}
+
+void
+do_dma_tasklet (unsigned long unused)
+{
+       int i;
+       int chan_no = 0;
+       int budget = DMA_INT_BUDGET;
+       int weight = 0;
+    int flag;
+
+       while (g_danube_dma_int_status)
+       {
+               if (budget-- < 0)
+               {
+                       tasklet_schedule(&dma_tasklet);
+                       return;
+               }
+               chan_no = -1;
+               weight = 0;
+               for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
+               {
+                       if ((g_danube_dma_int_status & (1 << i)) && dma_chan[i].weight > 0)
+                       {
+                               if (dma_chan[i].weight > weight)
+                               {
+                                       chan_no = i;
+                    weight = dma_chan[chan_no].weight;
+                }
+                       }
+               }
+
+               if (chan_no >= 0)
+               {
+                       if (chan_map[chan_no].dir == DANUBE_DMA_RX)
+                               rx_chan_intr_handler(chan_no);
+                       else
+                               tx_chan_intr_handler(chan_no);
+               } else {
+                       for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
+                       {
+                               dma_chan[i].weight = dma_chan[i].default_weight;
+                       }
+               }
+       }
+
+    local_irq_save(flag);
+       g_danube_dma_in_process = 0;
+    if (g_danube_dma_int_status)
+       {
+        g_danube_dma_in_process = 1;
+        tasklet_schedule(&dma_tasklet);
+    }
+    local_irq_restore(flag);
+}
+
+irqreturn_t
+dma_interrupt (int irq, void *dev_id)
+{
+       _dma_channel_info *pCh;
+       int chan_no = 0;
+       int tmp;
+
+       pCh = (_dma_channel_info*)dev_id;
+       chan_no = (int)(pCh - dma_chan);
+       if (chan_no < 0 || chan_no > 19)
+               BUG();
+
+       tmp = readl(DANUBE_DMA_IRNEN);
+       writel(0, DANUBE_DMA_IRNEN);
+       g_danube_dma_int_status |= 1 << chan_no;
+       writel(tmp, DANUBE_DMA_IRNEN);
+       mask_and_ack_danube_irq(irq);
+
+    if (!g_danube_dma_in_process)
+       {
+        g_danube_dma_in_process = 1;
+        tasklet_schedule(&dma_tasklet);
+    }
+
+       return IRQ_HANDLED;
+}
+
+_dma_device_info*
+dma_device_reserve (char *dev_name)
+{
+       int i;
+
+       for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
+       {
+               if (strcmp(dev_name, dma_devs[i].device_name) == 0)
+               {
+                       if (dma_devs[i].reserved)
+                               return NULL;
+                       dma_devs[i].reserved = 1;
+                       break;
+               }
+       }
+
+       return &dma_devs[i];
+}
+
+void
+dma_device_release (_dma_device_info *dev)
+{
+       dev->reserved = 0;
+}
+
+void
+dma_device_register(_dma_device_info *dev)
+{
+       int i, j;
+       int chan_no = 0;
+       u8 *buffer;
+       int byte_offset;
+       int flag;
+       _dma_device_info *pDev;
+       _dma_channel_info *pCh;
+       struct rx_desc *rx_desc_p;
+       struct tx_desc *tx_desc_p;
+
+       for (i = 0; i < dev->max_tx_chan_num; i++)
+       {
+               pCh = dev->tx_chan[i];
+               if (pCh->control == DANUBE_DMA_CH_ON)
+               {
+                       chan_no = (int)(pCh - dma_chan);
+                       for (j = 0; j < pCh->desc_len; j++)
+                       {
+                               tx_desc_p = (struct tx_desc*)pCh->desc_base + j;
+                               memset(tx_desc_p, 0, sizeof(struct tx_desc));
+                       }
+                       local_irq_save(flag);
+                       writel(chan_no, DANUBE_DMA_CS);
+                       /*check if the descriptor length is changed */
+                       if (readl(DANUBE_DMA_CDLEN) != pCh->desc_len)
+                               writel(pCh->desc_len, DANUBE_DMA_CDLEN);
+
+                       writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
+                       writel(readl(DANUBE_DMA_CCTRL) | 2, DANUBE_DMA_CCTRL);
+                       while (readl(DANUBE_DMA_CCTRL) & 2){};
+                       writel(readl(DANUBE_DMA_IRNEN) | (1 << chan_no), DANUBE_DMA_IRNEN);
+                       writel(0x30100, DANUBE_DMA_CCTRL);      /*reset and enable channel,enable channel later */
+                       local_irq_restore(flag);
+               }
+       }
+
+       for (i = 0; i < dev->max_rx_chan_num; i++)
+       {
+               pCh = dev->rx_chan[i];
+               if (pCh->control == DANUBE_DMA_CH_ON)
+               {
+                       chan_no = (int)(pCh - dma_chan);
+
+                       for (j = 0; j < pCh->desc_len; j++)
+                       {
+                               rx_desc_p = (struct rx_desc*)pCh->desc_base + j;
+                               pDev = (_dma_device_info*)(pCh->dma_dev);
+                               buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void*)&(pCh->opt[j]));
+                               if (!buffer)
+                                       break;
+
+                               dma_cache_inv((unsigned long) buffer, pCh->packet_size);
+
+                               rx_desc_p->Data_Pointer = (u32)CPHYSADDR((u32)buffer);
+                               rx_desc_p->status.word = 0;
+                               rx_desc_p->status.field.byte_offset = byte_offset;
+                               rx_desc_p->status.field.OWN = DMA_OWN;
+                               rx_desc_p->status.field.data_length = pCh->packet_size;
+                       }
+
+                       local_irq_save(flag);
+                       writel(chan_no, DANUBE_DMA_CS);
+                       /*check if the descriptor length is changed */
+                       if (readl(DANUBE_DMA_CDLEN) != pCh->desc_len)
+                               writel(pCh->desc_len, DANUBE_DMA_CDLEN);
+                       writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
+                       writel(readl(DANUBE_DMA_CCTRL) | 2, DANUBE_DMA_CCTRL);
+                       while (readl(DANUBE_DMA_CCTRL) & 2){};
+                       writel(0x0a, DANUBE_DMA_CIE);   /*fix me, should enable all the interrupts here? */
+                       writel(readl(DANUBE_DMA_IRNEN) | (1 << chan_no), DANUBE_DMA_IRNEN);
+                       writel(0x30000, DANUBE_DMA_CCTRL);
+                       local_irq_restore(flag);
+                       enable_danube_irq(dma_chan[chan_no].irq);
+               }
+       }
+}
+
+void
+dma_device_unregister (_dma_device_info *dev)
+{
+       int i, j;
+       int chan_no;
+       _dma_channel_info *pCh;
+       struct rx_desc *rx_desc_p;
+       struct tx_desc *tx_desc_p;
+       int flag;
+
+       for (i = 0; i < dev->max_tx_chan_num; i++)
+       {
+               pCh = dev->tx_chan[i];
+               if (pCh->control == DANUBE_DMA_CH_ON)
+               {
+                       chan_no = (int)(dev->tx_chan[i] - dma_chan);
+                       local_irq_save (flag);
+                       writel(chan_no, DANUBE_DMA_CS);
+                       pCh->curr_desc = 0;
+                       pCh->prev_desc = 0;
+                       pCh->control = DANUBE_DMA_CH_OFF;
+                       writel(0, DANUBE_DMA_CIE);      /*fix me, should disable all the interrupts here? */
+                       writel(readl(DANUBE_DMA_IRNEN) & ~(1 << chan_no), DANUBE_DMA_IRNEN);    /*disable interrupts */
+                       writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
+                       while (readl(DANUBE_DMA_CCTRL) & 1) {};
+                       local_irq_restore (flag);
+
+                       for (j = 0; j < pCh->desc_len; j++)
+                       {
+                               tx_desc_p = (struct tx_desc*)pCh->desc_base + j;
+                               if ((tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C)
+                                               || (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0))
+                               {
+                                       dev->buffer_free ((u8 *) __va (tx_desc_p->Data_Pointer), (void*)pCh->opt[j]);
+                               }
+                               tx_desc_p->status.field.OWN = CPU_OWN;
+                               memset (tx_desc_p, 0, sizeof (struct tx_desc));
+                       }
+                       //TODO should free buffer that is not transferred by dma
+               }
+       }
+
+       for (i = 0; i < dev->max_rx_chan_num; i++)
+       {
+               pCh = dev->rx_chan[i];
+               chan_no = (int)(dev->rx_chan[i] - dma_chan);
+               disable_danube_irq(pCh->irq);
+
+               local_irq_save(flag);
+               g_danube_dma_int_status &= ~(1 << chan_no);
+               pCh->curr_desc = 0;
+               pCh->prev_desc = 0;
+               pCh->control = DANUBE_DMA_CH_OFF;
+
+               writel(chan_no, DANUBE_DMA_CS);
+               writel(0, DANUBE_DMA_CIE); /*fix me, should disable all the interrupts here? */
+               writel(readl(DANUBE_DMA_IRNEN) & ~(1 << chan_no), DANUBE_DMA_IRNEN);    /*disable interrupts */
+               writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
+               while (readl(DANUBE_DMA_CCTRL) & 1) {};
+
+               local_irq_restore (flag);
+               for (j = 0; j < pCh->desc_len; j++)
+               {
+                       rx_desc_p = (struct rx_desc *) pCh->desc_base + j;
+                       if ((rx_desc_p->status.field.OWN == CPU_OWN 
+                            && rx_desc_p->status.field.C)
+                           || (rx_desc_p->status.field.OWN == DMA_OWN
+                               && rx_desc_p->status.field.data_length > 0)) {
+                               dev->buffer_free ((u8 *)
+                                                 __va (rx_desc_p->
+                                                       Data_Pointer),
+                                                 (void *) pCh->opt[j]);
+                       }
+               }
+       }
+}
+
+int
+dma_device_read (struct dma_device_info *dma_dev, u8 ** dataptr, void **opt)
+{
+       u8 *buf;
+       int len;
+       int byte_offset = 0;
+       void *p = NULL;
+       _dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan];
+       struct rx_desc *rx_desc_p;
+
+       /*get the rx data first */
+       rx_desc_p = (struct rx_desc *) pCh->desc_base + pCh->curr_desc;
+       if (!(rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C))
+       {
+               return 0;
+       }
+
+       buf = (u8 *) __va (rx_desc_p->Data_Pointer);
+       *(u32*)dataptr = (u32)buf;
+       len = rx_desc_p->status.field.data_length;
+
+       if (opt)
+       {
+               *(int*)opt = (int)pCh->opt[pCh->curr_desc];
+       }
+
+       /*replace with a new allocated buffer */
+       buf = dma_dev->buffer_alloc(pCh->packet_size, &byte_offset, &p);
+
+       if (buf)
+       {
+               dma_cache_inv ((unsigned long) buf,
+               pCh->packet_size);
+               pCh->opt[pCh->curr_desc] = p;
+               wmb ();
+
+               rx_desc_p->Data_Pointer = (u32) CPHYSADDR ((u32) buf);
+               rx_desc_p->status.word = (DMA_OWN << 31) | ((byte_offset) << 23) | pCh->packet_size;
+               wmb ();
+       } else {
+               *(u32 *) dataptr = 0;
+               if (opt)
+                       *(int *) opt = 0;
+               len = 0;
+       }
+
+       /*increase the curr_desc pointer */
+       pCh->curr_desc++;
+       if (pCh->curr_desc == pCh->desc_len)
+               pCh->curr_desc = 0;
+
+       return len;
+}
+
+int
+dma_device_write (struct dma_device_info *dma_dev, u8 * dataptr, int len, void *opt)
+{
+       int flag;
+       u32 tmp, byte_offset;
+       _dma_channel_info *pCh;
+       int chan_no;
+       struct tx_desc *tx_desc_p;
+       local_irq_save (flag);
+
+       pCh = dma_dev->tx_chan[dma_dev->current_tx_chan];
+       chan_no = (int)(pCh - (_dma_channel_info *) dma_chan);
+
+       tx_desc_p = (struct tx_desc*)pCh->desc_base + pCh->prev_desc;
+       while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C)
+       {
+               dma_dev->buffer_free((u8 *) __va (tx_desc_p->Data_Pointer), pCh->opt[pCh->prev_desc]);
+               memset(tx_desc_p, 0, sizeof (struct tx_desc));
+               pCh->prev_desc = (pCh->prev_desc + 1) % (pCh->desc_len);
+               tx_desc_p = (struct tx_desc*)pCh->desc_base + pCh->prev_desc;
+       }
+       tx_desc_p = (struct tx_desc*)pCh->desc_base + pCh->curr_desc;
+       /*Check whether this descriptor is available */
+       if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C)
+       {
+               /*if not , the tell the upper layer device */
+               dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
+               local_irq_restore(flag);
+               printk (KERN_INFO "%s %d: failed to write!\n", __func__, __LINE__);
+
+               return 0;
+       }
+       pCh->opt[pCh->curr_desc] = opt;
+       /*byte offset----to adjust the starting address of the data buffer, should be multiple of the burst length. */
+       byte_offset = ((u32) CPHYSADDR ((u32) dataptr)) % ((dma_dev->tx_burst_len) * 4);
+       dma_cache_wback ((unsigned long) dataptr, len);
+       wmb ();
+       tx_desc_p->Data_Pointer = (u32) CPHYSADDR ((u32) dataptr) - byte_offset;
+       wmb ();
+       tx_desc_p->status.word = (DMA_OWN << 31) | DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | ((byte_offset) << 23) | len;
+       wmb ();
+
+       pCh->curr_desc++;
+       if (pCh->curr_desc == pCh->desc_len)
+               pCh->curr_desc = 0;
+
+       /*Check whether this descriptor is available */
+       tx_desc_p = (struct tx_desc *) pCh->desc_base + pCh->curr_desc;
+       if (tx_desc_p->status.field.OWN == DMA_OWN)
+       {
+               /*if not , the tell the upper layer device */
+               dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
+       }
+
+       writel(chan_no, DANUBE_DMA_CS);
+       tmp = readl(DANUBE_DMA_CCTRL);
+
+       if (!(tmp & 1))
+               pCh->open (pCh);
+
+       local_irq_restore (flag);
+
+       return len;
+}
+
+int
+map_dma_chan(_dma_chan_map *map)
+{
+       int i, j;
+       int result;
+
+       for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
+       {
+               strcpy(dma_devs[i].device_name, global_device_name[i]);
+       }
+
+       for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
+       {
+               dma_chan[i].irq = map[i].irq;
+               result = request_irq(dma_chan[i].irq, dma_interrupt, SA_INTERRUPT, "dma-core", (void*)&dma_chan[i]);
+               if (result)
+               {
+                       printk("error, cannot get dma_irq!\n");
+                       free_irq(dma_chan[i].irq, (void *) &dma_interrupt);
+
+                       return -EFAULT;
+               }
+       }
+
+       for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
+       {
+               dma_devs[i].num_tx_chan = 0;    /*set default tx channel number to be one */
+               dma_devs[i].num_rx_chan = 0;    /*set default rx channel number to be one */
+               dma_devs[i].max_rx_chan_num = 0;
+               dma_devs[i].max_tx_chan_num = 0;
+               dma_devs[i].buffer_alloc = &common_buffer_alloc;
+               dma_devs[i].buffer_free = &common_buffer_free;
+               dma_devs[i].intr_handler = NULL;
+               dma_devs[i].tx_burst_len = 4;
+               dma_devs[i].rx_burst_len = 4;
+               if (i == 0)
+               {
+                       writel(0, DANUBE_DMA_PS);
+                       writel(readl(DANUBE_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), DANUBE_DMA_PCTRL);    /*enable dma drop */
+               }
+
+               if (i == 1)
+               {
+                       writel(1, DANUBE_DMA_PS);
+                       writel(0x14, DANUBE_DMA_PCTRL); /*deu port setting */
+               }
+
+               for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++)
+               {
+                       dma_chan[j].byte_offset = 0;
+                       dma_chan[j].open = &open_chan;
+                       dma_chan[j].close = &close_chan;
+                       dma_chan[j].reset = &reset_chan;
+                       dma_chan[j].enable_irq = &enable_ch_irq;
+                       dma_chan[j].disable_irq = &disable_ch_irq;
+                       dma_chan[j].rel_chan_no = map[j].rel_chan_no;
+                       dma_chan[j].control = DANUBE_DMA_CH_OFF;
+                       dma_chan[j].default_weight = DANUBE_DMA_CH_DEFAULT_WEIGHT;
+                       dma_chan[j].weight = dma_chan[j].default_weight;
+                       dma_chan[j].curr_desc = 0;
+                       dma_chan[j].prev_desc = 0;
+               }
+
+               for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++)
+               {
+                       if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0)
+                       {
+                               if (map[j].dir == DANUBE_DMA_RX)
+                               {
+                                       dma_chan[j].dir = DANUBE_DMA_RX;
+                                       dma_devs[i].max_rx_chan_num++;
+                                       dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j];
+                                       dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri;
+                                       dma_chan[j].dma_dev = (void*)&dma_devs[i];
+                               } else if(map[j].dir == DANUBE_DMA_TX)
+                               { /*TX direction */
+                                       dma_chan[j].dir = DANUBE_DMA_TX;
+                                       dma_devs[i].max_tx_chan_num++;
+                                       dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j];
+                                       dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri;
+                                       dma_chan[j].dma_dev = (void*)&dma_devs[i];
+                               } else {
+                                       printk ("WRONG DMA MAP!\n");
+                               }
+                       }
+               }
+       }
+
+       return 0;
+}
+
+void
+dma_chip_init(void)
+{
+       int i;
+
+       // enable DMA from PMU
+       danube_pmu_enable(DANUBE_PMU_PWDCR_DMA);
+
+       // reset DMA
+       writel(readl(DANUBE_DMA_CTRL) | 1, DANUBE_DMA_CTRL);
+
+       // diable all interrupts
+       writel(0, DANUBE_DMA_IRNEN);
+
+       for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
+       {
+               writel(i, DANUBE_DMA_CS);
+               writel(0x2, DANUBE_DMA_CCTRL);
+               writel(0x80000040, DANUBE_DMA_CPOLL);
+               writel(readl(DANUBE_DMA_CCTRL) & ~0x1, DANUBE_DMA_CCTRL);
+
+       }
+}
+
+int
+danube_dma_init (void)
+{
+       int i;
+
+       dma_chip_init();
+       if (map_dma_chan(default_dma_map))
+               BUG();
+
+       g_desc_list = (u64*)KSEG1ADDR(__get_free_page(GFP_DMA));
+
+       if (g_desc_list == NULL)
+       {
+               printk("no memory for desriptor\n");
+               return -ENOMEM;
+       }
+
+       memset(g_desc_list, 0, PAGE_SIZE);
+
+       for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
+       {
+               dma_chan[i].desc_base = (u32)g_desc_list + i * DANUBE_DMA_DESCRIPTOR_OFFSET * 8;
+               dma_chan[i].curr_desc = 0;
+               dma_chan[i].desc_len = DANUBE_DMA_DESCRIPTOR_OFFSET;
+
+               writel(i, DANUBE_DMA_CS);
+               writel((u32)CPHYSADDR(dma_chan[i].desc_base), DANUBE_DMA_CDBA);
+               writel(dma_chan[i].desc_len, DANUBE_DMA_CDLEN);
+       }
+
+       return 0;
+}
+
+arch_initcall(danube_dma_init);
+
+void
+dma_cleanup(void)
+{
+       int i;
+
+       free_page(KSEG0ADDR((unsigned long) g_desc_list));
+       for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
+               free_irq(dma_chan[i].irq, (void*)&dma_interrupt);
+}
+
+EXPORT_SYMBOL (dma_device_reserve);
+EXPORT_SYMBOL (dma_device_release);
+EXPORT_SYMBOL (dma_device_register);
+EXPORT_SYMBOL (dma_device_unregister);
+EXPORT_SYMBOL (dma_device_read);
+EXPORT_SYMBOL (dma_device_write);
+
+MODULE_LICENSE ("GPL");
diff --git a/target/linux/ifxmips/files/arch/mips/danube/interrupt.c b/target/linux/ifxmips/files/arch/mips/danube/interrupt.c
new file mode 100644 (file)
index 0000000..c266608
--- /dev/null
@@ -0,0 +1,219 @@
+/*
+ *   arch/mips/danube/interrupt.c
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2005 Wu Qi Ming infineon
+ *
+ *   Rewrite of Infineon Danube code, thanks to infineon for the support,
+ *   software and hardware
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/danube/danube.h>
+#include <asm/danube/danube_irq.h>
+#include <asm/irq_cpu.h>
+
+
+void
+disable_danube_irq (unsigned int irq_nr)
+{
+       int i;
+       u32 *danube_ier = DANUBE_ICU_IM0_IER;
+
+       irq_nr -= INT_NUM_IRQ0;
+       for (i = 0; i <= 4; i++)
+       {
+               if (irq_nr < INT_NUM_IM_OFFSET){
+                       writel(readl(danube_ier) & ~(1 << irq_nr ), danube_ier);
+                       return;
+               }
+               danube_ier += DANUBE_ICU_OFFSET;
+               irq_nr -= INT_NUM_IM_OFFSET;
+       }
+}
+EXPORT_SYMBOL (disable_danube_irq);
+
+void
+mask_and_ack_danube_irq (unsigned int irq_nr)
+{
+       int i;
+       u32 *danube_ier = DANUBE_ICU_IM0_IER;
+       u32 *danube_isr = DANUBE_ICU_IM0_ISR;
+
+       irq_nr -= INT_NUM_IRQ0;
+       for (i = 0; i <= 4; i++)
+       {
+               if (irq_nr < INT_NUM_IM_OFFSET)
+               {
+                       writel(readl(danube_ier) & ~(1 << irq_nr ), danube_ier);
+                       writel((1 << irq_nr ), danube_isr);
+                       return;
+               }
+               danube_ier += DANUBE_ICU_OFFSET;
+               danube_isr += DANUBE_ICU_OFFSET;
+               irq_nr -= INT_NUM_IM_OFFSET;
+       }
+}
+EXPORT_SYMBOL (mask_and_ack_danube_irq);
+
+void
+enable_danube_irq (unsigned int irq_nr)
+{
+       int i;
+       u32 *danube_ier = DANUBE_ICU_IM0_IER;
+
+       irq_nr -= INT_NUM_IRQ0;
+       for (i = 0; i <= 4; i++)
+       {
+               if (irq_nr < INT_NUM_IM_OFFSET)
+               {
+                       writel(readl(danube_ier) | (1 << irq_nr ), danube_ier);
+                       return;
+               }
+               danube_ier += DANUBE_ICU_OFFSET;
+               irq_nr -= INT_NUM_IM_OFFSET;
+       }
+}
+EXPORT_SYMBOL (enable_danube_irq);
+
+static unsigned int
+startup_danube_irq (unsigned int irq)
+{
+       enable_danube_irq (irq);
+       return 0;
+}
+
+static void
+end_danube_irq (unsigned int irq)
+{
+       if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+               enable_danube_irq (irq);
+}
+
+static struct hw_interrupt_type danube_irq_type = {
+       "DANUBE",
+       .startup = startup_danube_irq,
+       .enable = enable_danube_irq,
+       .disable = disable_danube_irq,
+       .unmask = enable_danube_irq,
+       .ack = end_danube_irq,
+       .mask = disable_danube_irq,
+       .mask_ack = mask_and_ack_danube_irq,
+       .end = end_danube_irq,
+};
+
+static inline int
+ls1bit32(unsigned long x)
+{
+       __asm__ (
+               "       .set    push                                    \n"
+               "       .set    mips32                                  \n"
+               "       clz     %0, %1                                  \n"
+               "       .set    pop                                     \n"
+               : "=r" (x)
+               : "r" (x));
+
+               return 31 - x;
+}
+
+void
+danube_hw_irqdispatch (int module)
+{
+       u32 irq;
+
+       irq = readl(DANUBE_ICU_IM0_IOSR + (module * DANUBE_ICU_OFFSET));
+       if (irq == 0)
+               return;
+
+       irq = ls1bit32 (irq);
+       do_IRQ ((int) irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
+
+       if ((irq == 22) && (module == 0)){
+               writel(readl(DANUBE_EBU_PCC_ISTAT) | 0x10, DANUBE_EBU_PCC_ISTAT);
+       }
+}
+
+asmlinkage void
+plat_irq_dispatch (void)
+{
+       unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
+       unsigned int i;
+
+       if (pending & CAUSEF_IP7){
+               do_IRQ(MIPS_CPU_TIMER_IRQ);
+               goto out;
+       } else {
+               for (i = 0; i < 5; i++)
+               {
+                       if (pending & (CAUSEF_IP2 << i))
+                       {
+                               danube_hw_irqdispatch(i);
+                               goto out;
+                       }
+               }
+       }
+       printk("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
+
+out:
+       return;
+}
+
+static struct irqaction cascade = {
+       .handler = no_action,
+       .flags = IRQF_DISABLED,
+       .name = "cascade",
+};
+
+void __init
+arch_init_irq(void)
+{
+       int i;
+
+       for (i = 0; i < 5; i++)
+       {
+               writel(0, DANUBE_ICU_IM0_IER + (i * DANUBE_ICU_OFFSET));
+       }
+
+       mips_cpu_irq_init();
+
+       for (i = 2; i <= 6; i++)
+       {
+               setup_irq(i, &cascade);
+       }
+
+       for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
+       {
+#if 0
+               irq_desc[i].status = IRQ_DISABLED;
+               irq_desc[i].action = NULL;
+               irq_desc[i].depth = 1;
+#endif
+               set_irq_chip_and_handler(i, &danube_irq_type, handle_level_irq);
+       }
+
+       set_c0_status (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
+}
diff --git a/target/linux/ifxmips/files/arch/mips/danube/pci.c b/target/linux/ifxmips/files/arch/mips/danube/pci.c
new file mode 100644 (file)
index 0000000..1896336
--- /dev/null
@@ -0,0 +1,319 @@
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/mm.h>
+#include <asm/danube/danube.h>
+#include <asm/danube/danube_irq.h>
+#include <asm/addrspace.h>
+#include <linux/vmalloc.h>
+
+#define DANUBE_PCI_MEM_BASE    0x18000000
+#define DANUBE_PCI_MEM_SIZE    0x02000000
+#define DANUBE_PCI_IO_BASE     0x1AE00000
+#define DANUBE_PCI_IO_SIZE     0x00200000
+
+#define DANUBE_PCI_CFG_BUSNUM_SHF 16
+#define DANUBE_PCI_CFG_DEVNUM_SHF 11
+#define DANUBE_PCI_CFG_FUNNUM_SHF 8
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+static int danube_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
+static int danube_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
+
+struct pci_ops danube_pci_ops = {
+       .read = danube_pci_read_config_dword,
+       .write = danube_pci_write_config_dword
+};
+
+static struct resource pci_io_resource = {
+       .name = "io pci IO space",
+       .start = DANUBE_PCI_IO_BASE,
+       .end = DANUBE_PCI_IO_BASE + DANUBE_PCI_IO_SIZE - 1,
+       .flags = IORESOURCE_IO
+};
+
+static struct resource pci_mem_resource = {
+       .name = "ext pci memory space",
+       .start = DANUBE_PCI_MEM_BASE,
+       .end = DANUBE_PCI_MEM_BASE + DANUBE_PCI_MEM_SIZE - 1,
+       .flags = IORESOURCE_MEM
+};
+
+static struct pci_controller danube_pci_controller = {
+       .pci_ops = &danube_pci_ops,
+       .mem_resource = &pci_mem_resource,
+       .mem_offset     = 0x00000000UL,
+       .io_resource = &pci_io_resource,
+       .io_offset      = 0x00000000UL,
+};
+
+static u32 danube_pci_mapped_cfg;
+
+static int
+danube_pci_config_access(unsigned char access_type,
+               struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
+{
+       unsigned long cfg_base;
+       unsigned long flags;
+
+       u32 temp;
+
+       /* Danube support slot from 0 to 15 */
+       /* dev_fn 0&0x68 (AD29) is danube itself */
+       if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
+                       || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
+               return 1;
+
+       local_irq_save(flags);
+
+       cfg_base = danube_pci_mapped_cfg;
+       cfg_base |= (bus->number << DANUBE_PCI_CFG_BUSNUM_SHF) | (devfn <<
+                       DANUBE_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
+
+       /* Perform access */
+       if (access_type == PCI_ACCESS_WRITE)
+       {
+#ifdef CONFIG_DANUBE_PCI_HW_SWAP
+               writel(swab32(*data), ((u32*)cfg_base));
+#else
+               writel(*data, ((u32*)cfg_base));
+#endif
+       } else {
+               *data = readl(((u32*)(cfg_base)));
+#ifdef CONFIG_DANUBE_PCI_HW_SWAP
+               *data = swab32(*data);
+#endif
+       }
+       wmb();
+
+       /* clean possible Master abort */
+       cfg_base = (danube_pci_mapped_cfg | (0x0 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4;
+       temp = readl(((u32*)(cfg_base)));
+#ifdef CONFIG_DANUBE_PCI_HW_SWAP
+       temp = swab32 (temp);
+#endif
+       cfg_base = (danube_pci_mapped_cfg | (0x68 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4;
+       writel(temp, ((u32*)cfg_base));
+
+       local_irq_restore(flags);
+
+       if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
+               return 1;
+
+       return 0;
+}
+
+static int danube_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
+               int where, int size, u32 * val)
+{
+       u32 data = 0;
+
+       if (danube_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+               return PCIBIOS_DEVICE_NOT_FOUND;
+
+       if (size == 1)
+               *val = (data >> ((where & 3) << 3)) & 0xff;
+       else if (size == 2)
+               *val = (data >> ((where & 3) << 3)) & 0xffff;
+       else
+               *val = data;
+
+       return PCIBIOS_SUCCESSFUL;
+}
+
+static int danube_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
+               int where, int size, u32 val)
+{
+       u32 data = 0;
+
+       if (size == 4)
+       {
+               data = val;
+       } else {
+               if (danube_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+                       return PCIBIOS_DEVICE_NOT_FOUND;
+
+               if (size == 1)
+                       data = (data & ~(0xff << ((where & 3) << 3))) |
+                               (val << ((where & 3) << 3));
+               else if (size == 2)
+                       data = (data & ~(0xffff << ((where & 3) << 3))) |
+                               (val << ((where & 3) << 3));
+       }
+
+       if (danube_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+               return PCIBIOS_DEVICE_NOT_FOUND;
+
+       return PCIBIOS_SUCCESSFUL;
+}
+
+
+int pcibios_plat_dev_init(struct pci_dev *dev){
+       u8 pin;
+
+       pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+
+       switch(pin) {
+               case 0:
+                       break;
+               case 1:
+                       //falling edge level triggered:0x4, low level:0xc, rising edge:0x2
+                       printk("%s:%s[%d] %08X \n", __FILE__, __func__, __LINE__, dev->irq);
+                       writel(readl(DANUBE_EBU_PCC_CON) | 0xc, DANUBE_EBU_PCC_CON);
+                       writel(readl(DANUBE_EBU_PCC_IEN) | 0x10, DANUBE_EBU_PCC_IEN);
+                       break;
+               case 2:
+               case 3:
+               case 4:
+                       printk ("WARNING: interrupt pin %d not supported yet!\n", pin);
+               default:
+                       printk ("WARNING: invalid interrupt pin %d\n", pin);
+                       return 1;
+       }
+
+       return 0;
+}
+
+static void __init danube_pci_startup (void){
+       /*initialize the first PCI device--danube itself */
+       u32 temp_buffer;
+       /*TODO: trigger reset */
+       writel(readl(DANUBE_CGU_IFCCR) & ~0xf00000, DANUBE_CGU_IFCCR);
+       writel(readl(DANUBE_CGU_IFCCR) | 0x800000, DANUBE_CGU_IFCCR);
+       /* PCIS of IF_CLK of CGU   : 1 =>PCI Clock output
+          0 =>clock input
+          PADsel of PCI_CR of CGU : 1 =>From CGU
+          : 0 =>From pad
+        */
+       writel(readl(DANUBE_CGU_IFCCR) | (1 << 16), DANUBE_CGU_IFCCR);
+       writel((1 << 31) | (1 << 30), DANUBE_CGU_PCICR);
+
+       /* prepare GPIO */
+       /* PCI_RST: P1.5 ALT 01 */
+       //pliu20060613: start
+       writel(readl(DANUBE_GPIO_P1_OUT) | (1 << 5), DANUBE_GPIO_P1_OUT);
+       writel(readl(DANUBE_GPIO_P1_OD) | (1 << 5), DANUBE_GPIO_P1_OD);
+       writel(readl(DANUBE_GPIO_P1_DIR) | (1 << 5), DANUBE_GPIO_P1_DIR);
+       writel(readl(DANUBE_GPIO_P1_ALTSEL1) & ~(1 << 5), DANUBE_GPIO_P1_ALTSEL1);
+       writel(readl(DANUBE_GPIO_P1_ALTSEL0) & ~(1 << 5), DANUBE_GPIO_P1_ALTSEL0);
+       //pliu20060613: end
+       /* PCI_REQ1: P1.13 ALT 01 */
+       /* PCI_GNT1: P1.14 ALT 01 */
+       writel(readl(DANUBE_GPIO_P1_DIR) & ~0x2000, DANUBE_GPIO_P1_DIR);
+       writel(readl(DANUBE_GPIO_P1_DIR) | 0x4000, DANUBE_GPIO_P1_DIR);
+       writel(readl(DANUBE_GPIO_P1_ALTSEL1) & ~0x6000, DANUBE_GPIO_P1_ALTSEL1);
+       writel(readl(DANUBE_GPIO_P1_ALTSEL0) | 0x6000, DANUBE_GPIO_P1_ALTSEL0);
+       /* PCI_REQ2: P1.15 ALT 10 */
+       /* PCI_GNT2: P1.7 ALT 10 */
+
+
+       /* enable auto-switching between PCI and EBU */
+       writel(0xa, PCI_CR_CLK_CTRL);
+       /* busy, i.e. configuration is not done, PCI access has to be retried */
+       writel(readl(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
+       wmb ();
+       /* BUS Master/IO/MEM access */
+       writel(readl(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
+
+       temp_buffer = readl(PCI_CR_PC_ARB);
+       /* enable external 2 PCI masters */
+       temp_buffer &= (~(0xf << 16));
+       /* enable internal arbiter */
+       temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
+       /* enable internal PCI master reqest */
+       temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
+
+       /* enable EBU reqest */
+       temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
+
+       /* enable all external masters request */
+       temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
+       writel(temp_buffer, PCI_CR_PC_ARB);
+
+       wmb ();
+
+       /* FPI ==> PCI MEM address mapping */
+       /* base: 0xb8000000 == > 0x18000000 */
+       /* size: 8x4M = 32M */
+       writel(0x18000000, PCI_CR_FCI_ADDR_MAP0);
+       writel(0x18400000, PCI_CR_FCI_ADDR_MAP1);
+       writel(0x18800000, PCI_CR_FCI_ADDR_MAP2);
+       writel(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
+       writel(0x19000000, PCI_CR_FCI_ADDR_MAP4);
+       writel(0x19400000, PCI_CR_FCI_ADDR_MAP5);
+       writel(0x19800000, PCI_CR_FCI_ADDR_MAP6);
+       writel(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
+
+       /* FPI ==> PCI IO address mapping */
+       /* base: 0xbAE00000 == > 0xbAE00000 */
+       /* size: 2M */
+       writel(0xbae00000, PCI_CR_FCI_ADDR_MAP11hg);
+
+       /* PCI ==> FPI address mapping */
+       /* base: 0x0 ==> 0x0 */
+       /* size: 32M */
+       /* BAR1 32M map to SDR address */
+       writel(0x0e000008, PCI_CR_BAR11MASK);
+       writel(0, PCI_CR_PCI_ADDR_MAP11);
+       writel(0, PCI_CS_BASE_ADDR1);
+#ifdef CONFIG_DANUBE_PCI_HW_SWAP
+       /* both TX and RX endian swap are enabled */
+       DANUBE_PCI_REG32 (PCI_CR_PCI_EOI_REG) |= 3;
+       wmb ();
+#endif
+       /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
+       writel(readl(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
+       writel(readl(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
+       /*use 8 dw burse length */
+       writel(0x303, PCI_CR_FCI_BURST_LENGTH);
+
+       writel(readl(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
+       wmb();
+       writel(readl(DANUBE_GPIO_P1_OUT) & ~(1 << 5), DANUBE_GPIO_P1_OUT);
+       wmb();
+       mdelay (1);
+       writel(readl(DANUBE_GPIO_P1_OUT) | (1 << 5), DANUBE_GPIO_P1_OUT);
+}
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
+       printk("\n\n\n%s:%s[%d] %d %d\n", __FILE__, __func__, __LINE__, slot, pin);
+       switch (slot) {
+               case 13:
+                       /* IDSEL = AD29 --> USB Host Controller */
+                       return (INT_NUM_IM1_IRL0 + 17);
+               case 14:
+                       /* IDSEL = AD30 --> mini PCI connector */
+                       //return (INT_NUM_IM1_IRL0 + 14);
+                       return (INT_NUM_IM0_IRL0 + 22);
+               default:
+                       printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin);
+                       return 0;
+       }
+}
+
+int pcibios_init(void){
+       extern int pci_probe_only;
+
+       pci_probe_only = 0;
+       printk ("PCI: Probing PCI hardware on host bus 0.\n");
+
+       danube_pci_startup ();
+
+       //      DANUBE_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
+       danube_pci_mapped_cfg = ioremap_nocache(0x17000000, 0x800 * 16);
+       printk("Danube PCI mapped to 0x%08X\n", (unsigned long)danube_pci_mapped_cfg);
+
+       danube_pci_controller.io_map_base = (unsigned long)ioremap(DANUBE_PCI_IO_BASE, DANUBE_PCI_IO_SIZE - 1);
+
+       printk("Danube PCI I/O mapped to 0x%08X\n", (unsigned long)danube_pci_controller.io_map_base);
+
+       register_pci_controller(&danube_pci_controller);
+
+       return 0;
+}
+
+arch_initcall(pcibios_init);
diff --git a/target/linux/ifxmips/files/arch/mips/danube/pmu.c b/target/linux/ifxmips/files/arch/mips/danube/pmu.c
new file mode 100644 (file)
index 0000000..5bb66db
--- /dev/null
@@ -0,0 +1,45 @@
+/*
+ *   arch/mips/danube/pmu.c
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <asm/danube/danube.h>
+
+void
+danube_pmu_enable (unsigned int module)
+{
+       int err = 1000000;
+
+       writel(readl(DANUBE_PMU_PWDCR) & ~module, DANUBE_PMU_PWDCR);
+       while (--err && (readl(DANUBE_PMU_PWDSR) & module)) {}
+
+       if (!err)
+               panic("activating PMU module failed!");
+}
+EXPORT_SYMBOL(danube_pmu_enable);
+
+void
+danube_pmu_disable (unsigned int module)
+{
+       writel(readl(DANUBE_PMU_PWDCR) | module, DANUBE_PMU_PWDCR);
+}
+EXPORT_SYMBOL(danube_pmu_disable);
diff --git a/target/linux/ifxmips/files/arch/mips/danube/prom.c b/target/linux/ifxmips/files/arch/mips/danube/prom.c
new file mode 100644 (file)
index 0000000..efb0612
--- /dev/null
@@ -0,0 +1,81 @@
+/*
+ *   arch/mips/danube/prom.c
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2005 Wu Qi Ming infineon
+ *
+ *   Rewrite of Infineon Danube code, thanks to infineon for the support,
+ *   software and hardware
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/bootmem.h>
+#include <asm/bootinfo.h>
+#include <asm/danube/danube.h>
+
+static char buf[1024];
+
+void
+prom_free_prom_memory (void)
+{
+}
+
+const char *
+get_system_type (void)
+{
+       return BOARD_SYSTEM_TYPE;
+}
+
+void
+prom_putchar (char c)
+{
+       while ((readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
+
+       if (c == '\n')
+               writel('\r', DANUBE_ASC1_TBUF);
+       writel(c, DANUBE_ASC1_TBUF);
+}
+
+void
+prom_printf (const char * fmt, ...)
+{
+       va_list args;
+       int l;
+       char *p, *buf_end;
+
+       va_start(args, fmt);
+       l = vsprintf(buf, fmt, args);
+       va_end(args);
+       buf_end = buf + l;
+
+       for (p = buf; p < buf_end; p++)
+       {
+               prom_putchar(*p);
+       }
+}
+
+void __init
+prom_init(void)
+{
+       mips_machgroup = MACH_GROUP_DANUBE;
+       mips_machtype = MACH_INFINEON_DANUBE;
+
+       strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
+       add_memory_region (0x00000000, 0x2000000, BOOT_MEM_RAM);
+}
diff --git a/target/linux/ifxmips/files/arch/mips/danube/reset.c b/target/linux/ifxmips/files/arch/mips/danube/reset.c
new file mode 100644 (file)
index 0000000..cb1793c
--- /dev/null
@@ -0,0 +1,66 @@
+/*
+ *   arch/mips/danube/prom.c
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2005 infineon
+ *
+ *   Rewrite of Infineon Danube code, thanks to infineon for the support,
+ *   software and hardware
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/pm.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/danube/danube.h>
+
+static void
+danube_machine_restart (char *command)
+{
+       printk (KERN_NOTICE "System restart\n");
+       local_irq_disable ();
+
+       writel(readl(DANUBE_RCU_REQ) | DANUBE_RST_ALL, DANUBE_RCU_REQ);
+       for (;;);
+}
+
+static void
+danube_machine_halt (void)
+{
+       printk (KERN_NOTICE "System halted.\n");
+       local_irq_disable ();
+       for (;;);
+}
+
+static void
+danube_machine_power_off (void)
+{
+       printk (KERN_NOTICE "Please turn off the power now.\n");
+       local_irq_disable ();
+       for (;;);
+}
+
+void
+danube_reboot_setup (void)
+{
+       _machine_restart = danube_machine_restart;
+       _machine_halt = danube_machine_halt;
+       pm_power_off = danube_machine_power_off;
+}
diff --git a/target/linux/ifxmips/files/arch/mips/danube/setup.c b/target/linux/ifxmips/files/arch/mips/danube/setup.c
new file mode 100644 (file)
index 0000000..60b0ce2
--- /dev/null
@@ -0,0 +1,177 @@
+/*
+ *   arch/mips/danube/setup.c
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2004 peng.liu@infineon.com 
+ *
+ *   Rewrite of Infineon Danube code, thanks to infineon for the support,
+ *   software and hardware
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+
+#include <linux/init.h>
+
+#include <asm/time.h>
+#include <asm/traps.h>
+#include <asm/cpu.h>
+#include <asm/irq.h>
+#include <asm/danube/danube.h>
+#include <asm/danube/danube_irq.h>
+#include <asm/danube/danube_pmu.h>
+
+static unsigned int r4k_offset; /* Amount to increment compare reg each time */
+static unsigned int r4k_cur;    /* What counter should be at next timer irq */
+
+extern void danube_reboot_setup (void);
+void prom_printf (const char * fmt, ...);
+
+void
+__init bus_error_init (void)
+{
+               /* nothing yet */
+}
+
+unsigned int
+danube_get_ddr_hz (void)
+{
+       switch (readl(DANUBE_CGU_SYS) & 0x3)
+       {
+       case 0:
+               return CLOCK_167M;
+       case 1:
+               return CLOCK_133M;
+       case 2:
+               return CLOCK_111M;
+       }
+       return CLOCK_83M;
+}
+EXPORT_SYMBOL(danube_get_ddr_hz);
+
+unsigned int
+danube_get_cpu_hz (void)
+{
+       unsigned int ddr_clock = danube_get_ddr_hz();
+       switch (readl(DANUBE_CGU_SYS) & 0xc)
+       {
+       case 0:
+               return CLOCK_333M;
+       case 4:
+               return ddr_clock;
+       }
+       return ddr_clock << 1;
+}
+EXPORT_SYMBOL(danube_get_cpu_hz);
+
+unsigned int
+danube_get_fpi_hz (void)
+{
+       unsigned int ddr_clock = danube_get_ddr_hz();
+       if (readl(DANUBE_CGU_SYS) & 0x40)
+       {
+               return ddr_clock >> 1;
+       }
+       return ddr_clock;
+}
+EXPORT_SYMBOL(danube_get_fpi_hz);
+
+unsigned int
+danube_get_cpu_ver (void)
+{
+       return readl(DANUBE_MCD_CHIPID) & 0xFFFFF000;
+}
+EXPORT_SYMBOL(danube_get_cpu_ver);
+
+void
+danube_time_init (void)
+{
+       mips_hpt_frequency = danube_get_cpu_hz() / 2;
+       r4k_offset = mips_hpt_frequency / HZ;
+       printk("mips_hpt_frequency:%d\n", mips_hpt_frequency);
+       printk("r4k_offset: %08x(%d)\n", r4k_offset, r4k_offset);
+}
+
+int
+danube_be_handler(struct pt_regs *regs, int is_fixup)
+{
+       /*TODO*/
+       printk(KERN_ERR "TODO: BUS error\n");
+
+       return MIPS_BE_FATAL;
+}
+
+/* ISR GPTU Timer 6 for high resolution timer */
+static irqreturn_t
+danube_timer6_interrupt(int irq, void *dev_id)
+{
+       timer_interrupt(DANUBE_TIMER6_INT, NULL);
+
+       return IRQ_HANDLED;
+}
+
+static struct irqaction hrt_irqaction = {
+       .handler = danube_timer6_interrupt,
+       .flags = IRQF_DISABLED,
+       .name = "hrt",
+};
+
+void __init
+plat_timer_setup (struct irqaction *irq)
+{
+       unsigned int retval;
+
+       setup_irq(MIPS_CPU_TIMER_IRQ, irq);
+
+       r4k_cur = (read_c0_count() + r4k_offset);
+       write_c0_compare(r4k_cur);
+
+       danube_pmu_enable(DANUBE_PMU_PWDCR_GPT | DANUBE_PMU_PWDCR_FPI);
+
+       writel(0x100, DANUBE_GPTU_GPT_CLC);
+
+       writel(0xffff, DANUBE_GPTU_GPT_CAPREL);
+       writel(0x80C0, DANUBE_GPTU_GPT_T6CON);
+
+       retval = setup_irq(DANUBE_TIMER6_INT, &hrt_irqaction);
+
+       if (retval)
+       {
+               prom_printf("reqeust_irq failed %d. HIGH_RES_TIMER is diabled\n", DANUBE_TIMER6_INT);
+       }
+}
+
+void __init
+plat_mem_setup (void)
+{
+       u32 status;
+       prom_printf("This %s has a cpu rev of 0x%X\n", BOARD_SYSTEM_TYPE, danube_get_cpu_ver());
+
+       //TODO WHY ???
+       /* clear RE bit*/
+       status = read_c0_status();
+       status &= (~(1<<25));
+       write_c0_status(status);
+
+       danube_reboot_setup();
+       board_time_init = danube_time_init;
+       board_be_handler = &danube_be_handler;
+
+       ioport_resource.start = IOPORT_RESOURCE_START;
+       ioport_resource.end = IOPORT_RESOURCE_END;
+       iomem_resource.start = IOMEM_RESOURCE_START;
+       iomem_resource.end = IOMEM_RESOURCE_END;
+}
diff --git a/target/linux/ifxmips/files/drivers/char/danube_eeprom.c b/target/linux/ifxmips/files/drivers/char/danube_eeprom.c
new file mode 100644 (file)
index 0000000..1835f27
--- /dev/null
@@ -0,0 +1,541 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   This driver was originally based on the INCA-IP driver, but due to
+ *   fundamental conceptual drawbacks there has been changed a lot.
+ *
+ *   Based on INCA-IP driver Copyright (c) 2003 Gary Jennejohn <gj@denx.de>
+ *   Based on the VxWorks drivers Copyright (c) 2002, Infineon Technologies.
+ *
+ *   Copyright (C) 2006 infineon
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+
+#define IFAP_EEPROM_DRV_VERSION "0.0.1"
+
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/major.h>
+#include <linux/string.h>
+#include <linux/fs.h>
+#include <linux/fcntl.h>
+#include <linux/ptrace.h>
+#include <linux/mm.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/bitops.h>
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+
+#include <asm/danube/danube.h>
+#include <asm/danube/danube_irq.h>
+#include <asm/danube/ifx_ssc_defines.h>
+#include <asm/danube/ifx_ssc.h>
+
+/* allow the user to set the major device number */
+static int danube_eeprom_maj = 0;
+
+extern int ifx_ssc_init (void);
+extern int ifx_ssc_open (struct inode *inode, struct file *filp);
+extern int ifx_ssc_close (struct inode *inode, struct file *filp);
+extern void ifx_ssc_cleanup_module (void);
+extern int ifx_ssc_ioctl (struct inode *inode, struct file *filp,
+                         unsigned int cmd, unsigned long data);
+extern ssize_t ifx_ssc_kwrite (int port, const char *kbuf, size_t len);
+extern ssize_t ifx_ssc_kread (int port, char *kbuf, size_t len);
+
+extern int ifx_ssc_cs_low (unsigned int pin);
+extern int ifx_ssc_cs_high (unsigned int pin);
+extern int ifx_ssc_txrx (char *tx_buf, unsigned int tx_len, char *rx_buf, unsigned int rx_len);
+extern int ifx_ssc_tx (char *tx_buf, unsigned int tx_len);
+extern int ifx_ssc_rx (char *rx_buf, unsigned int rx_len);
+
+#define EEPROM_CS IFX_SSC_WHBGPOSTAT_OUT0_POS
+
+/* commands for EEPROM, x25160, x25140 */
+#define EEPROM_WREN                    ((unsigned char)0x06)
+#define EEPROM_WRDI                    ((unsigned char)0x04)
+#define EEPROM_RDSR                    ((unsigned char)0x05)
+#define EEPROM_WRSR                    ((unsigned char)0x01)
+#define EEPROM_READ                    ((unsigned char)0x03)
+#define EEPROM_WRITE                   ((unsigned char)0x02)
+#define EEPROM_PAGE_SIZE               4
+#define EEPROM_SIZE                    512
+
+static int
+eeprom_rdsr (void)
+{
+       int ret = 0;
+       unsigned char cmd = EEPROM_RDSR;
+       unsigned long flag;
+       char status;
+
+       local_irq_save(flag);
+
+       if ((ret = ifx_ssc_cs_low(EEPROM_CS)) == 0)
+               if ((ret = ifx_ssc_txrx(&cmd, 1, &status, 1)) >= 0)
+                       ret = status & 1;
+
+       ifx_ssc_cs_high(EEPROM_CS);
+       local_irq_restore(flag);
+
+       return ret;
+}
+
+void
+eeprom_wip_over (void)
+{
+       while (eeprom_rdsr())
+               printk("waiting for eeprom\n");
+}
+
+static int
+eeprom_wren (void)
+{
+       unsigned char cmd = EEPROM_WREN;
+       int ret = 0;
+       unsigned long flag;
+
+       local_irq_save(flag);
+       if ((ret = ifx_ssc_cs_low(EEPROM_CS)) == 0)
+               if ((ret = ifx_ssc_tx(&cmd, 1)) >= 0)
+                       ret = 0;
+
+       ifx_ssc_cs_high(EEPROM_CS);
+       local_irq_restore(flag);
+
+       if (!ret)
+               eeprom_wip_over();
+
+       return ret;
+}
+
+static int
+eeprom_wrsr (void)
+{
+       int ret = 0;
+       unsigned char cmd[2];
+       unsigned long flag;
+
+       cmd[0] = EEPROM_WRSR;
+       cmd[1] = 0;
+
+       if ((ret = eeprom_wren()))
+       {
+               printk ("eeprom_wren fails\n");
+               goto out1;
+       }
+
+       local_irq_save(flag);
+
+       if ((ret = ifx_ssc_cs_low(EEPROM_CS)))
+               goto out;
+
+       if ((ret = ifx_ssc_tx(cmd, 2)) < 0) {
+               ifx_ssc_cs_high(EEPROM_CS);
+               goto out;
+       }
+
+       if ((ret = ifx_ssc_cs_low(EEPROM_CS)))
+               goto out;
+
+       local_irq_restore(flag);
+       eeprom_wip_over();
+
+       return ret;
+
+out:
+       local_irq_restore (flag);
+       eeprom_wip_over ();
+
+out1:
+       return ret;
+}
+
+static int
+eeprom_read (unsigned int addr, unsigned char *buf, unsigned int len)
+{
+       int ret = 0;
+       unsigned char write_buf[2];
+       unsigned int eff = 0;
+       unsigned long flag;
+
+       while (1)
+       {
+               eeprom_wip_over();
+               eff = EEPROM_PAGE_SIZE - (addr % EEPROM_PAGE_SIZE);
+               eff = (eff < len) ? eff : len;
+               local_irq_save(flag);
+
+               if ((ret = ifx_ssc_cs_low(EEPROM_CS)) < 0)
+                       goto out;
+
+               write_buf[0] = EEPROM_READ | ((unsigned char) ((addr & 0x100) >> 5));
+               write_buf[1] = (addr & 0xff);
+
+               if ((ret = ifx_ssc_txrx (write_buf, 2, buf, eff)) != eff)
+               {
+                       printk("ssc_txrx fails %d\n", ret);
+                       ifx_ssc_cs_high (EEPROM_CS);
+                       goto out;
+               }
+
+               buf += ret;
+               len -= ret;
+               addr += ret;
+
+               if ((ret = ifx_ssc_cs_high(EEPROM_CS)))
+                       goto out;
+
+               local_irq_restore(flag);
+
+               if (len <= 0)
+                       goto out2;
+       }
+
+out:
+       local_irq_restore (flag);
+out2:
+       return ret;
+}
+
+static int
+eeprom_write (unsigned int addr, unsigned char *buf, unsigned int len)
+{
+       int ret = 0;
+       unsigned int eff = 0;
+       unsigned char write_buf[2];
+       int i;
+       unsigned char rx_buf[EEPROM_PAGE_SIZE];
+
+       while (1)
+       {
+               eeprom_wip_over();
+
+               if ((ret = eeprom_wren()))
+               {
+                       printk("eeprom_wren fails\n");
+                       goto out;
+               }
+
+               write_buf[0] = EEPROM_WRITE | ((unsigned char) ((addr & 0x100) >> 5));
+               write_buf[1] = (addr & 0xff);
+
+               eff = EEPROM_PAGE_SIZE - (addr % EEPROM_PAGE_SIZE);
+               eff = (eff < len) ? eff : len;
+
+               printk("EEPROM Write:\n");
+               for (i = 0; i < eff; i++) {
+                       printk("%2x ", buf[i]);
+                       if ((i % 16) == 15)
+                               printk("\n");
+               }
+               printk("\n");
+
+               if ((ret = ifx_ssc_cs_low(EEPROM_CS)))
+                       goto out;
+
+               if ((ret = ifx_ssc_tx (write_buf, 2)) < 0)
+               {
+                       printk("ssc_tx fails %d\n", ret);
+                       ifx_ssc_cs_high(EEPROM_CS);
+                       goto out;
+               }
+
+               if ((ret = ifx_ssc_tx (buf, eff)) != eff)
+               {
+                       printk("ssc_tx fails %d\n", ret);
+                       ifx_ssc_cs_high(EEPROM_CS);
+                       goto out;
+               }
+
+               buf += ret;
+               len -= ret;
+               addr += ret;
+
+               if ((ret = ifx_ssc_cs_high (EEPROM_CS)))
+                       goto out;
+
+               printk ("<==");
+               eeprom_read((addr - eff), rx_buf, eff);
+               for (i = 0; i < eff; i++)
+               {
+                       printk ("[%x]", rx_buf[i]);
+               }
+               printk ("\n");
+
+               if (len <= 0)
+                       break;
+       }
+
+out:
+       return ret;
+}
+
+int
+danube_eeprom_open (struct inode *inode, struct file *filp)
+{
+       filp->f_pos = 0;
+       return 0;
+}
+
+int
+danube_eeprom_close (struct inode *inode, struct file *filp)
+{
+       return 0;
+}
+
+int
+danube_eeprom_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data)
+{
+       return 0;
+}
+
+ssize_t
+danube_eeprom_read (char *buf, size_t len, unsigned int addr)
+{
+       int ret = 0;
+       unsigned int data;
+
+       printk("addr:=%d\n", addr);
+       printk("len:=%d\n", len);
+
+       if ((addr + len) > EEPROM_SIZE)
+       {
+               printk("invalid len\n");
+               addr = 0;
+               len = EEPROM_SIZE / 2;
+       }
+
+       if ((ret = ifx_ssc_open((struct inode *) 0, NULL)))
+       {
+               printk("danube_eeprom_open fails\n");
+               goto out;
+       }
+
+       data = (unsigned int)IFX_SSC_MODE_RXTX;
+
+       if ((ret = ifx_ssc_ioctl((struct inode *) 0, NULL, IFX_SSC_RXTX_MODE_SET, (unsigned long) &data)))
+       {
+               printk("set RXTX mode fails\n");
+               goto out;
+       }
+
+       if ((ret = eeprom_wrsr()))
+       {
+               printk("EEPROM reset fails\n");
+               goto out;
+       }
+
+       if ((ret = eeprom_read(addr, buf, len)))
+       {
+               printk("eeprom read fails\n");
+               goto out;
+       }
+
+out:
+       if (ifx_ssc_close((struct inode *) 0, NULL))
+               printk("danube_eeprom_close fails\n");
+
+       return len;
+}
+EXPORT_SYMBOL(danube_eeprom_read);
+
+static ssize_t
+danube_eeprom_fops_read (struct file *filp, char *ubuf, size_t len, loff_t * off)
+{
+       int ret = 0;
+       unsigned char ssc_rx_buf[EEPROM_SIZE];
+       long flag;
+
+       if (*off >= EEPROM_SIZE)
+               return 0;
+
+       if (*off + len > EEPROM_SIZE)
+               len = EEPROM_SIZE - *off;
+
+       if (len == 0)
+               return 0;
+
+       local_irq_save(flag);
+
+       if ((ret = danube_eeprom_read(ssc_rx_buf, len, *off)) < 0)
+       {
+               printk("read fails, err=%x\n", ret);
+               local_irq_restore(flag);
+               return ret;
+       }
+
+       if (copy_to_user((void*)ubuf, ssc_rx_buf, ret) != 0)
+       {
+               local_irq_restore(flag);
+               ret = -EFAULT;
+       }
+
+       local_irq_restore(flag);
+       *off += len;
+
+       return len;
+}
+
+ssize_t
+danube_eeprom_write (char *buf, size_t len, unsigned int addr)
+{
+       int ret = 0;
+       unsigned int data;
+
+       if ((ret = ifx_ssc_open ((struct inode *) 0, NULL)))
+       {
+               printk ("danube_eeprom_open fails\n");
+               goto out;
+       }
+
+       data = (unsigned int) IFX_SSC_MODE_RXTX;
+
+       if ((ret = ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_RXTX_MODE_SET, (unsigned long) &data)))
+       {
+               printk ("set RXTX mode fails\n");
+               goto out;
+       }
+
+       if ((ret = eeprom_wrsr ())) {
+               printk ("EEPROM reset fails\n");
+               goto out;
+       }
+
+       if ((ret = eeprom_write (addr, buf, len))) {
+               printk ("eeprom write fails\n");
+               goto out;
+       }
+
+out:
+       if (ifx_ssc_close ((struct inode *) 0, NULL))
+               printk ("danube_eeprom_close fails\n");
+
+       return ret;
+}
+EXPORT_SYMBOL(danube_eeprom_write);
+
+static ssize_t
+danube_eeprom_fops_write (struct file *filp, const char *ubuf, size_t len, loff_t * off)
+{
+       int ret = 0;
+       unsigned char ssc_tx_buf[EEPROM_SIZE];
+
+       if (*off >= EEPROM_SIZE)
+               return 0;
+
+       if (len + *off > EEPROM_SIZE)
+               len = EEPROM_SIZE - *off;
+
+       if ((ret = copy_from_user (ssc_tx_buf, ubuf, len)))
+               return EFAULT;
+
+       ret = danube_eeprom_write (ssc_tx_buf, len, *off);
+
+       if (ret > 0)
+               *off = ret;
+
+       return ret;
+}
+
+loff_t
+danube_eeprom_llseek (struct file * filp, loff_t off, int whence)
+{
+       loff_t newpos;
+       switch (whence) {
+       case SEEK_SET:
+               newpos = off;
+               break;
+
+       case SEEK_CUR:
+               newpos = filp->f_pos + off;
+               break;
+
+       default:
+               return -EINVAL;
+       }
+
+       if (newpos < 0)
+               return -EINVAL;
+
+       filp->f_pos = newpos;
+
+       return newpos;
+}
+
+static struct file_operations danube_eeprom_fops = {
+      owner:THIS_MODULE,
+      llseek:danube_eeprom_llseek,
+      read:danube_eeprom_fops_read,
+      write:danube_eeprom_fops_write,
+      ioctl:danube_eeprom_ioctl,
+      open:danube_eeprom_open,
+      release:danube_eeprom_close,
+};
+
+int __init
+danube_eeprom_init (void)
+{
+       int ret = 0;
+
+       danube_eeprom_maj = register_chrdev(0, "eeprom", &danube_eeprom_fops);
+
+       if (danube_eeprom_maj < 0)
+       {
+               printk("failed to register eeprom device\n");
+               ret = -EINVAL;
+               
+               goto out;
+       }
+
+       printk("danube_eeprom : /dev/eeprom mayor %d\n", danube_eeprom_maj);
+
+out:
+       return ret;
+}
+
+void __exit
+danube_eeprom_cleanup_module (void)
+{
+       /*if (unregister_chrdev (danube_eeprom_maj, "eeprom")) {
+               printk ("Unable to unregister major %d for the EEPROM\n",
+                       maj);
+       }*/
+}
+
+module_exit (danube_eeprom_cleanup_module);
+module_init (danube_eeprom_init);
+
+MODULE_LICENSE ("GPL");
+MODULE_AUTHOR ("Peng Liu");
+MODULE_DESCRIPTION ("IFAP EEPROM driver");
+MODULE_SUPPORTED_DEVICE ("danube_eeprom");
+
+
diff --git a/target/linux/ifxmips/files/drivers/char/danube_gpio.c b/target/linux/ifxmips/files/drivers/char/danube_gpio.c
new file mode 100644 (file)
index 0000000..dbdb71e
--- /dev/null
@@ -0,0 +1,442 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2005 infineon
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/proc_fs.h>
+#include <linux/init.h>
+#include <linux/ioctl.h>
+#include <asm/semaphore.h>
+#include <asm/uaccess.h>
+#include <asm/danube/danube.h>
+#include <asm/danube/danube_ioctl.h>
+
+#define MAX_PORTS                      2
+#define PINS_PER_PORT          16
+
+static unsigned int danube_gpio_major = 0;
+
+/* TODO do we need this ? */
+static struct semaphore port_sem;
+
+/* TODO do we really need this ? return in a define is forbidden by coding style */
+#define DANUBE_GPIO_SANITY             {if (port > MAX_PORTS || pin > PINS_PER_PORT) return -EINVAL; }
+
+int
+danube_port_reserve_pin (unsigned int port, unsigned int pin)
+{
+       DANUBE_GPIO_SANITY;
+       printk("%s : call to obseleted function\n", __func__);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_reserve_pin);
+
+int
+danube_port_free_pin (unsigned int port, unsigned int pin)
+{
+       DANUBE_GPIO_SANITY;
+       printk("%s : call to obseleted function\n", __func__);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_free_pin);
+
+int
+danube_port_set_open_drain (unsigned int port, unsigned int pin)
+{
+       DANUBE_GPIO_SANITY;
+       writel(readl(DANUBE_GPIO_P0_OD + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_OD);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_set_open_drain);
+
+int
+danube_port_clear_open_drain (unsigned int port, unsigned int pin)
+{
+       DANUBE_GPIO_SANITY;
+       writel(readl(DANUBE_GPIO_P0_OD + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_OD);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_clear_open_drain);
+
+int
+danube_port_set_pudsel (unsigned int port, unsigned int pin)
+{
+    DANUBE_GPIO_SANITY;
+       writel(readl(DANUBE_GPIO_P0_PUDSEL + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_PUDSEL);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_set_pudsel);
+
+int
+danube_port_clear_pudsel (unsigned int port, unsigned int pin)
+{
+    DANUBE_GPIO_SANITY;
+       writel(readl(DANUBE_GPIO_P0_PUDSEL + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_PUDSEL);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_clear_pudsel);
+
+int
+danube_port_set_puden (unsigned int port, unsigned int pin)
+{
+    DANUBE_GPIO_SANITY;
+       writel(readl(DANUBE_GPIO_P0_PUDEN + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_PUDEN);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_set_puden);
+
+int
+danube_port_clear_puden (unsigned int port, unsigned int pin)
+{
+    DANUBE_GPIO_SANITY;
+       writel(readl(DANUBE_GPIO_P0_PUDEN + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_PUDEN);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_clear_puden);
+
+int
+danube_port_set_stoff (unsigned int port, unsigned int pin)
+{
+    DANUBE_GPIO_SANITY;
+       writel(readl(DANUBE_GPIO_P0_STOFF + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_STOFF);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_set_stoff);
+
+int
+danube_port_clear_stoff (unsigned int port, unsigned int pin)
+{
+    DANUBE_GPIO_SANITY;
+       writel(readl(DANUBE_GPIO_P0_STOFF + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_STOFF);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_clear_stoff);
+
+int
+danube_port_set_dir_out (unsigned int port, unsigned int pin)
+{
+    DANUBE_GPIO_SANITY;
+       writel(readl(DANUBE_GPIO_P0_DIR + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_DIR);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_set_dir_out);
+
+int
+danube_port_set_dir_in (unsigned int port, unsigned int pin)
+{
+    DANUBE_GPIO_SANITY;
+       writel(readl(DANUBE_GPIO_P0_DIR + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_DIR);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_set_dir_in);
+
+int
+danube_port_set_output (unsigned int port, unsigned int pin)
+{
+    DANUBE_GPIO_SANITY;
+       writel(readl(DANUBE_GPIO_P0_OUT + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_OUT);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_set_output);
+
+int
+danube_port_clear_output (unsigned int port, unsigned int pin)
+{
+    DANUBE_GPIO_SANITY;
+       writel(readl(DANUBE_GPIO_P0_OUT + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_OUT);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_clear_output);
+
+int
+danube_port_get_input (unsigned int port, unsigned int pin)
+{
+    DANUBE_GPIO_SANITY;
+
+       if (readl(DANUBE_GPIO_P0_IN + (port * 0x30)) & (1 << pin))
+               return 0;
+       else
+               return 1;
+}
+EXPORT_SYMBOL(danube_port_get_input);
+
+int
+danube_port_set_altsel0 (unsigned int port, unsigned int pin)
+{
+    DANUBE_GPIO_SANITY;
+       writel(readl(DANUBE_GPIO_P0_ALTSEL0 + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_ALTSEL0);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_set_altsel0);
+
+int
+danube_port_clear_altsel0 (unsigned int port, unsigned int pin)
+{
+    DANUBE_GPIO_SANITY;
+       writel(readl(DANUBE_GPIO_P0_ALTSEL0 + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_ALTSEL0);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_clear_altsel0);
+
+int
+danube_port_set_altsel1 (unsigned int port, unsigned int pin)
+{
+    DANUBE_GPIO_SANITY;
+       writel(readl(DANUBE_GPIO_P0_ALTSEL1 + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_ALTSEL1);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_set_altsel1);
+
+int
+danube_port_clear_altsel1 (unsigned int port, unsigned int pin)
+{
+    DANUBE_GPIO_SANITY;
+       writel(readl(DANUBE_GPIO_P0_ALTSEL1 + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_ALTSEL1);
+
+       return 0;
+}
+EXPORT_SYMBOL(danube_port_clear_altsel1);
+
+long danube_port_read_procmem_helper(char* tag, u32* in_reg, char *buf)
+{
+       u32 reg, bit = 0;
+       unsigned int len, t;
+
+       len = sprintf(buf, "\n%s: ", tag);
+       reg = readl(in_reg);
+       bit = 0x80000000;
+       for (t = 0; t < 32; t++) {
+               if ((reg & bit) > 0)
+                       len = len + sprintf(buf + len, "X");
+               else
+                       len = len + sprintf(buf + len, " ");
+               bit = bit >> 1;
+       }
+
+       return len;
+}
+
+int
+danube_port_read_procmem (char *buf, char **start, off_t offset, int count,
+                         int *eof, void *data)
+{
+       long len = sprintf (buf, "\nDanube Port Settings\n");
+
+       len += sprintf (buf + len,
+                       "         3         2         1         0\n");
+       len += sprintf (buf + len,
+                       "        10987654321098765432109876543210\n");
+       len += sprintf (buf + len,
+                       "----------------------------------------\n");
+
+       len += danube_port_read_procmem_helper("P0-OUT", DANUBE_GPIO_P0_OUT, &buf[len]);
+       len += danube_port_read_procmem_helper("P1-OUT", DANUBE_GPIO_P1_OUT, &buf[len]);
+       len += danube_port_read_procmem_helper("P0-IN ", DANUBE_GPIO_P0_IN, &buf[len]);
+       len += danube_port_read_procmem_helper("P1-IN ", DANUBE_GPIO_P1_IN, &buf[len]);
+       len += danube_port_read_procmem_helper("P0-DIR", DANUBE_GPIO_P0_DIR, &buf[len]);
+       len += danube_port_read_procmem_helper("P1-DIR", DANUBE_GPIO_P1_DIR, &buf[len]);
+       len += danube_port_read_procmem_helper("P0-STO ", DANUBE_GPIO_P0_STOFF, &buf[len]);
+       len += danube_port_read_procmem_helper("P1-STO ", DANUBE_GPIO_P1_STOFF, &buf[len]);
+       len += danube_port_read_procmem_helper("P0-PUDE", DANUBE_GPIO_P0_PUDEN, &buf[len]);
+       len += danube_port_read_procmem_helper("P1-PUDE", DANUBE_GPIO_P1_PUDEN, &buf[len]);
+       len += danube_port_read_procmem_helper("P0-OD  ", DANUBE_GPIO_P0_OD, &buf[len]);
+       len += danube_port_read_procmem_helper("P1-OD  ", DANUBE_GPIO_P1_OD, &buf[len]);
+       len += danube_port_read_procmem_helper("P0-PUDS", DANUBE_GPIO_P0_PUDSEL, &buf[len]);
+       len += danube_port_read_procmem_helper("P1-PUDS", DANUBE_GPIO_P1_PUDSEL, &buf[len]);
+       len += danube_port_read_procmem_helper("P0-ALT0", DANUBE_GPIO_P0_ALTSEL0, &buf[len]);
+       len += danube_port_read_procmem_helper("P1-ALT0", DANUBE_GPIO_P1_ALTSEL0, &buf[len]);
+       len += danube_port_read_procmem_helper("P0-ALT1", DANUBE_GPIO_P0_ALTSEL1, &buf[len]);
+       len += danube_port_read_procmem_helper("P1-ALT1", DANUBE_GPIO_P1_ALTSEL1, &buf[len]);
+       len = len + sprintf (buf + len, "\n\n");
+
+       *eof = 1;
+
+       return len;
+}
+
+static int
+danube_port_open (struct inode *inode, struct file *filep)
+{
+       return 0;
+}
+
+static int
+danube_port_release (struct inode *inode, struct file *filelp)
+{
+       return 0;
+}
+
+static int
+danube_port_ioctl (struct inode *inode, struct file *filp,
+                       unsigned int cmd, unsigned long arg)
+{
+       int ret = 0;
+       volatile struct danube_port_ioctl_parm parm;
+
+       if (_IOC_TYPE (cmd) != DANUBE_PORT_IOC_MAGIC)
+               return -EINVAL;
+
+       if (_IOC_DIR (cmd) & _IOC_WRITE) {
+               if (!access_ok
+                   (VERIFY_READ, arg,
+                    sizeof (struct danube_port_ioctl_parm)))
+                       return -EFAULT;
+               ret = copy_from_user ((void *) &parm, (void *) arg,
+                                     sizeof (struct danube_port_ioctl_parm));
+       }
+       if (_IOC_DIR (cmd) & _IOC_READ) {
+               if (!access_ok
+                   (VERIFY_WRITE, arg,
+                    sizeof (struct danube_port_ioctl_parm)))
+                       return -EFAULT;
+       }
+
+       if (down_trylock (&port_sem) != 0)
+               return -EBUSY;
+
+       switch (cmd) {
+       case DANUBE_PORT_IOCOD:
+               if (parm.value == 0x00)
+                       danube_port_clear_open_drain(parm.port, parm.pin);
+               else
+                       danube_port_set_open_drain(parm.port, parm.pin);
+               break;
+
+       case DANUBE_PORT_IOCPUDSEL:
+               if (parm.value == 0x00)
+                       danube_port_clear_pudsel(parm.port, parm.pin);
+               else
+                       danube_port_set_pudsel(parm.port, parm.pin);
+               break;
+
+       case DANUBE_PORT_IOCPUDEN:
+               if (parm.value == 0x00)
+                       danube_port_clear_puden(parm.port, parm.pin);
+               else
+                       danube_port_set_puden(parm.port, parm.pin);
+               break;
+
+       case DANUBE_PORT_IOCSTOFF:
+               if (parm.value == 0x00)
+                       danube_port_clear_stoff(parm.port, parm.pin);
+               else
+                       danube_port_set_stoff(parm.port, parm.pin);
+               break;
+
+       case DANUBE_PORT_IOCDIR:
+               if (parm.value == 0x00)
+                       danube_port_set_dir_in(parm.port, parm.pin);
+               else
+                       danube_port_set_dir_out(parm.port, parm.pin);
+               break;
+
+       case DANUBE_PORT_IOCOUTPUT:
+               if (parm.value == 0x00)
+                       danube_port_clear_output(parm.port, parm.pin);
+               else
+                       danube_port_set_output(parm.port, parm.pin);
+               break;
+
+       case DANUBE_PORT_IOCALTSEL0:
+               if (parm.value == 0x00)
+                       danube_port_clear_altsel0(parm.port, parm.pin);
+               else
+                       danube_port_set_altsel0(parm.port, parm.pin);
+               break;
+
+       case DANUBE_PORT_IOCALTSEL1:
+               if (parm.value == 0x00)
+                       danube_port_clear_altsel1(parm.port, parm.pin);
+               else
+                       danube_port_set_altsel1(parm.port, parm.pin);
+               break;
+
+       case DANUBE_PORT_IOCINPUT:
+               parm.value = danube_port_get_input(parm.port, parm.pin);
+               copy_to_user((void*)arg, (void*)&parm,
+                       sizeof(struct danube_port_ioctl_parm));
+               break;
+
+       default:
+               ret = -EINVAL;
+       }
+
+       up (&port_sem);
+
+       return ret;
+}
+
+static struct file_operations port_fops = {
+      .open = danube_port_open,
+      .release = danube_port_release,
+      .ioctl = danube_port_ioctl
+};
+
+int __init
+danube_gpio_init (void)
+{
+       int retval = 0;
+
+       sema_init (&port_sem, 1);
+
+       danube_gpio_major = register_chrdev(0, "danube_gpio", &port_fops);
+       if (!danube_gpio_major)
+       {
+               printk("danube-port: Error! Could not register port device. #%d\n", danube_gpio_major);
+               retval = -EINVAL;
+               goto out;
+       }
+
+       create_proc_read_entry("danube_gpio", 0, NULL,
+                               danube_port_read_procmem, NULL);
+
+       printk("registered danube gpio driver\n");
+
+out:
+       return retval;
+}
+
+void __exit
+danube_gpio_exit (void)
+{
+       unregister_chrdev(danube_gpio_major, "danube_gpio");
+       remove_proc_entry("danube_gpio", NULL);
+}
+
+module_init(danube_gpio_init);
+module_exit(danube_gpio_exit);
diff --git a/target/linux/ifxmips/files/drivers/char/danube_led.c b/target/linux/ifxmips/files/drivers/char/danube_led.c
new file mode 100644 (file)
index 0000000..86a92d5
--- /dev/null
@@ -0,0 +1,197 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2006 infineon
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <asm/uaccess.h>
+#include <asm/unistd.h>
+#include <linux/errno.h>
+#include <asm/danube/danube.h>
+#include <asm/danube/danube_gpio.h>
+#include <asm/danube/danube_pmu.h>
+
+#define DANUBE_LED_CLK_EDGE                            DANUBE_LED_FALLING
+//#define DANUBE_LED_CLK_EDGE                  DANUBE_LED_RISING
+
+#define DANUBE_LED_SPEED                               DANUBE_LED_8HZ
+
+#define DANUBE_LED_GPIO_PORT   0
+
+static int danube_led_major;
+
+void
+danube_led_set (unsigned int led)
+{
+       led &= 0xffffff;
+       writel(readl(DANUBE_LED_CPU0) | led, DANUBE_LED_CPU0);
+}
+EXPORT_SYMBOL(danube_led_set);
+
+void
+danube_led_clear (unsigned int led)
+{
+       led = ~(led & 0xffffff);
+       writel(readl(DANUBE_LED_CPU0) & led, DANUBE_LED_CPU0);
+}
+EXPORT_SYMBOL(danube_led_clear);
+
+void
+danube_led_blink_set (unsigned int led)
+{
+       led &= 0xffffff;
+       writel(readl(DANUBE_LED_CON0) | led, DANUBE_LED_CON0);
+}
+EXPORT_SYMBOL(danube_led_blink_set);
+
+void
+danube_led_blink_clear (unsigned int led)
+{
+       led = ~(led & 0xffffff);
+       writel(readl(DANUBE_LED_CON0) & led, DANUBE_LED_CON0);
+}
+EXPORT_SYMBOL(danube_led_blink_clear);
+
+void
+danube_led_setup_gpio (void)
+{
+       int i = 0;
+
+       /* we need to setup pins SH,D,ST (4,5,6) */
+       for (i = 4; i < 7; i++)
+       {
+               danube_port_set_altsel0(DANUBE_LED_GPIO_PORT, i);
+               danube_port_clear_altsel1(DANUBE_LED_GPIO_PORT, i);
+               danube_port_set_dir_out(DANUBE_LED_GPIO_PORT, i);
+               danube_port_set_open_drain(DANUBE_LED_GPIO_PORT, i);
+       }
+}
+
+static int
+led_ioctl (struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+{
+       int ret = -EINVAL;
+
+       switch ( cmd )
+       {
+       }
+
+       return ret;
+}
+
+static int
+led_open (struct inode *inode, struct file *file)
+{
+       return 0;
+}
+
+static int
+led_release (struct inode *inode, struct file *file)
+{
+       return 0;
+}
+
+static struct file_operations danube_led_fops = {
+       .owner = THIS_MODULE,
+       .ioctl = led_ioctl,
+       .open = led_open,
+       .release = led_release
+};
+
+
+/*
+Map for LED on reference board
+       WLAN_READ     LED11   OUT1    15
+       WARNING       LED12   OUT2    14
+       FXS1_LINK     LED13   OUT3    13
+       FXS2_LINK     LED14   OUT4    12
+       FXO_ACT       LED15   OUT5    11
+       USB_LINK      LED16   OUT6    10
+       ADSL2_LINK    LED19   OUT7    9
+       BT_LINK       LED17   OUT8    8
+       SD_LINK       LED20   OUT9    7
+       ADSL2_TRAFFIC LED31   OUT16   0
+Map for hardware relay on reference board
+       USB Power On          OUT11   5
+       RELAY                 OUT12   4
+*/
+
+
+int __init
+danube_led_init (void)
+{
+       int ret = 0;
+
+       danube_led_setup_gpio();
+
+       writel(0, DANUBE_LED_AR);
+       writel(0, DANUBE_LED_CPU0);
+       writel(0, DANUBE_LED_CPU1);
+       writel(LED_CON0_SWU, DANUBE_LED_CON0);
+       writel(0, DANUBE_LED_CON1);
+
+       /* setup the clock edge that the shift register is triggered on */
+       writel(readl(DANUBE_LED_CON0) & ~DANUBE_LED_EDGE_MASK, DANUBE_LED_CON0);
+       writel(readl(DANUBE_LED_CON0) | DANUBE_LED_CLK_EDGE, DANUBE_LED_CON0);
+
+       /* per default leds 15-0 are set */
+       writel(DANUBE_LED_GROUP1 | DANUBE_LED_GROUP0, DANUBE_LED_CON1);
+
+       /* leds are update periodically by the FPID */
+       writel(readl(DANUBE_LED_CON1) & ~DANUBE_LED_UPD_MASK, DANUBE_LED_CON1);
+       writel(readl(DANUBE_LED_CON1) | DANUBE_LED_UPD_SRC_FPI, DANUBE_LED_CON1);
+
+       /* set led update speed */
+       writel(readl(DANUBE_LED_CON1) & ~DANUBE_LED_MASK, DANUBE_LED_CON1);
+       writel(readl(DANUBE_LED_CON1) | DANUBE_LED_SPEED, DANUBE_LED_CON1);
+
+       /* adsl 0 and 1 leds are updated by the arc */
+       writel(readl(DANUBE_LED_CON0) | DANUBE_LED_ADSL_SRC, DANUBE_LED_CON0);
+
+       /* per default, the leds are turned on */
+       danube_pmu_enable(DANUBE_PMU_PWDCR_LED);
+
+       danube_led_major = register_chrdev(0, "danube_led", &danube_led_fops);
+
+       if (!danube_led_major)
+       {
+               printk("danube_led: Error! Could not register device. %d\n", danube_led_major);
+               ret = -EINVAL;
+
+               goto out;
+       }
+
+       printk(KERN_INFO "danube_led : device registered on major %d\n", danube_led_major);
+
+out:
+       return ret;
+}
+
+void __exit
+danube_led_exit (void)
+{
+       unregister_chrdev(danube_led_major, "danube_led");
+}
+
+module_init(danube_led_init);
+module_exit(danube_led_exit);
diff --git a/target/linux/ifxmips/files/drivers/char/danube_ssc.c b/target/linux/ifxmips/files/drivers/char/danube_ssc.c
new file mode 100644 (file)
index 0000000..1f90dac
--- /dev/null
@@ -0,0 +1,1533 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2006 infineon
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+
+// ### TO DO: general issues:
+//            - power management
+//            - interrupt handling (direct/indirect)
+//            - pin/mux-handling (just overall concept due to project dependency)
+//            - multiple instances capability
+//            - slave functionality
+
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/major.h>
+#include <linux/string.h>
+#include <linux/fs.h>
+#include <linux/proc_fs.h>
+#include <linux/fcntl.h>
+#include <linux/ptrace.h>
+#include <linux/mm.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/bitops.h>
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+
+#include <asm/danube/danube.h>
+#include <asm/danube/danube_irq.h>
+#include <asm/danube/ifx_ssc_defines.h>
+#include <asm/danube/ifx_ssc.h>
+
+#ifdef SSC_FRAME_INT_ENABLE
+#undef SSC_FRAME_INT_ENABLE
+#endif
+
+#define not_yet
+
+#define SPI_VINETIC
+
+
+
+/* allow the user to set the major device number */
+static int maj = 0;
+
+/*
+ * This is the per-channel data structure containing pointers, flags
+ * and variables for the port. This driver supports a maximum of PORT_CNT.
+ * isp is allocated in ifx_ssc_init() based on the chip version.
+ */
+static struct ifx_ssc_port *isp;
+
+/* prototypes for fops */
+static ssize_t ifx_ssc_read (struct file *, char *, size_t, loff_t *);
+static ssize_t ifx_ssc_write (struct file *, const char *, size_t, loff_t *);
+//static unsigned int ifx_ssc_poll(struct file *, struct poll_table_struct *);
+int ifx_ssc_ioctl (struct inode *, struct file *, unsigned int,
+                  unsigned long);
+int ifx_ssc_open (struct inode *, struct file *);
+int ifx_ssc_close (struct inode *, struct file *);
+
+/* other forward declarations */
+static unsigned int ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info);
+static void tx_int (struct ifx_ssc_port *);
+static int ifx_ssc1_read_proc (char *, char **, off_t, int, int *, void *);
+
+extern unsigned int danube_get_fpi_hz (void);
+extern void mask_and_ack_danube_irq (unsigned int irq_nr);
+
+static struct file_operations ifx_ssc_fops = {
+      .owner = THIS_MODULE,
+      .read = ifx_ssc_read,
+      .write = ifx_ssc_write,
+      .ioctl = ifx_ssc_ioctl,
+      .open = ifx_ssc_open,
+      .release = ifx_ssc_close,
+};
+
+static inline unsigned int
+ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info)
+{
+       unsigned int rmc;
+
+       rmc = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
+       if (rmc == 0)
+       {
+               printk ("ifx_ssc_get_kernel_clk rmc==0 \n");
+               return 0;
+       }
+       return danube_get_fpi_hz () / rmc;
+}
+
+#ifndef not_yet
+#ifdef IFX_SSC_INT_USE_BH
+/*
+ * This routine is used by the interrupt handler to schedule
+ * processing in the software interrupt portion of the driver
+ * (also known as the "bottom half").  This can be called any
+ * number of times for any channel without harm.
+ */
+static inline void
+ifx_ssc_sched_event (struct ifx_ssc_port *info, int event)
+{
+       info->event |= 1 << event;      /* remember what kind of event and who */
+       queue_task (&info->tqueue, &tq_cyclades);       /* it belongs to */
+       mark_bh (CYCLADES_BH);  /* then trigger event */
+}
+
+static void
+do_softint (void *private_)
+{
+       struct ifx_ssc_port *info = (struct ifx_ssc_port *) private_;
+
+       if (test_and_clear_bit (Cy_EVENT_HANGUP, &info->event))
+       {
+               wake_up_interruptible (&info->open_wait);
+               info->flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CALLOUT_ACTIVE);
+       }
+
+       if (test_and_clear_bit (Cy_EVENT_OPEN_WAKEUP, &info->event))
+               wake_up_interruptible (&info->open_wait);
+
+       if (test_and_clear_bit (Cy_EVENT_DELTA_WAKEUP, &info->event))
+               wake_up_interruptible (&info->delta_msr_wait);
+
+       if (test_and_clear_bit (Cy_EVENT_WRITE_WAKEUP, &info->event))
+               wake_up_interruptible (&tty->write_wait);
+#ifdef Z_WAKE
+       if (test_and_clear_bit (Cy_EVENT_SHUTDOWN_WAKEUP, &info->event))
+               wake_up_interruptible (&info->shutdown_wait);
+#endif
+}
+#endif
+#endif
+
+inline static void
+rx_int (struct ifx_ssc_port *info)
+{
+       int fifo_fill_lev, bytes_in_buf, i;
+       unsigned long tmp_val;
+       unsigned long *tmp_ptr;
+       unsigned int rx_valid_cnt;
+       /* number of words waiting in the RX FIFO */
+       fifo_fill_lev = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
+       // Note: There are always 32 bits in a fifo-entry except for the last 
+       // word of a contigous transfer block and except for not in rx-only 
+       // mode and CON.ENBV set. But for this case it should be a convention 
+       // in software which helps:
+       // In tx or rx/tx mode all transfers from the buffer to the FIFO are 
+       // 32-bit wide, except for the last three bytes, which could be a 
+       // combination of 16- and 8-bit access.
+       // => The whole block is received as 32-bit words as a contigous stream, 
+       // even if there was a gap in tx which has the fifo run out of data! 
+       // Just the last fifo entry *may* be partially filled (0, 1, 2 or 3 bytes)!
+
+       /* free space in the RX buffer */
+       bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr;
+       // transfer with 32 bits per entry
+       while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) {
+               tmp_ptr = (unsigned long *) info->rxbuf_ptr;
+               *tmp_ptr = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RB);
+               info->rxbuf_ptr += 4;
+               info->stats.rxBytes += 4;
+               fifo_fill_lev--;
+               bytes_in_buf -= 4;
+       }
+
+       // now do the rest as mentioned in STATE.RXBV
+       while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) {
+               rx_valid_cnt = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
+               if (rx_valid_cnt == 0)
+                       break;
+
+               if (rx_valid_cnt > bytes_in_buf)
+                       rx_valid_cnt = bytes_in_buf;
+
+               tmp_val = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RB);
+
+               for (i = 0; i < rx_valid_cnt; i++)
+               {
+                       *info->rxbuf_ptr = (tmp_val >> (8 * (rx_valid_cnt - i - 1))) & 0xff;
+                       bytes_in_buf--;
+                       info->rxbuf_ptr++;
+               }
+               info->stats.rxBytes += rx_valid_cnt;
+       }
+
+       // check if transfer is complete
+       if (info->rxbuf_ptr >= info->rxbuf_end)
+       {
+               disable_irq(info->rxirq);
+               wake_up_interruptible (&info->rwait);
+       } else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) == 0))
+       {
+               if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE)
+                       WRITE_PERIPHERAL_REGISTER ((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
+               else
+                       WRITE_PERIPHERAL_REGISTER (IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET,  info->mapbase + IFX_SSC_RXREQ);
+       }
+}
+
+inline static void
+tx_int (struct ifx_ssc_port *info)
+{
+
+       int fifo_space, fill, i;
+       fifo_space = ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
+               - ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
+
+       if (fifo_space == 0)
+               return;
+
+       fill = info->txbuf_end - info->txbuf_ptr;
+
+       if (fill > fifo_space * 4)
+               fill = fifo_space * 4;
+
+       for (i = 0; i < fill / 4; i++)
+       {
+               // at first 32 bit access
+               WRITE_PERIPHERAL_REGISTER (*(UINT32 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
+               info->txbuf_ptr += 4;
+       }
+
+       fifo_space -= fill / 4;
+       info->stats.txBytes += fill & ~0x3;
+       fill &= 0x3;
+       if ((fifo_space > 0) & (fill > 1))
+       {
+               // trailing 16 bit access
+               WRITE_PERIPHERAL_REGISTER_16 (*(UINT16 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
+               info->txbuf_ptr += 2;
+               info->stats.txBytes += 2;
+               fifo_space--;
+               fill -= 2;
+       }
+
+       if ((fifo_space > 0) & (fill > 0))
+       {
+               // trailing 8 bit access
+               WRITE_PERIPHERAL_REGISTER_8 (*(UINT8 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
+               info->txbuf_ptr++;
+               info->stats.txBytes++;
+       }
+
+       // check if transmission complete
+       if (info->txbuf_ptr >= info->txbuf_end)
+       {
+               disable_irq(info->txirq);
+               kfree (info->txbuf);
+               info->txbuf = NULL;
+       }
+
+}
+
+irqreturn_t
+ifx_ssc_rx_int (int irq, void *dev_id)
+{
+       struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
+       rx_int (info);
+
+       return IRQ_HANDLED;
+}
+
+irqreturn_t
+ifx_ssc_tx_int (int irq, void *dev_id)
+{
+       struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
+       tx_int (info);
+
+       return IRQ_HANDLED;
+}
+
+irqreturn_t
+ifx_ssc_err_int (int irq, void *dev_id)
+{
+       struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
+       unsigned int state;
+       unsigned int write_back = 0;
+       unsigned long flags;
+
+       local_irq_save (flags);
+       state = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE);
+
+       if ((state & IFX_SSC_STATE_RX_UFL) != 0) {
+               info->stats.rxUnErr++;
+               write_back |= IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR;
+       }
+
+       if ((state & IFX_SSC_STATE_RX_OFL) != 0) {
+               info->stats.rxOvErr++;
+               write_back |= IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR;
+       }
+
+       if ((state & IFX_SSC_STATE_TX_OFL) != 0) {
+               info->stats.txOvErr++;
+               write_back |= IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR;
+       }
+
+       if ((state & IFX_SSC_STATE_TX_UFL) != 0) {
+               info->stats.txUnErr++;
+               write_back |= IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR;
+       }
+
+       if ((state & IFX_SSC_STATE_MODE_ERR) != 0) {
+               info->stats.modeErr++;
+               write_back |= IFX_SSC_WHBSTATE_CLR_MODE_ERROR;
+       }
+
+       if (write_back)
+               WRITE_PERIPHERAL_REGISTER (write_back, info->mapbase + IFX_SSC_WHBSTATE);
+
+       local_irq_restore (flags);
+
+       return IRQ_HANDLED;
+}
+
+static void
+ifx_ssc_abort (struct ifx_ssc_port *info)
+{
+       unsigned long flags;
+       bool enabled;
+
+       local_irq_save (flags);
+
+       disable_irq(info->rxirq);
+       disable_irq(info->txirq);
+       disable_irq(info->errirq);
+
+       local_irq_restore (flags);
+
+       // disable SSC (also aborts a receive request!)
+       // ### TO DO: Perhaps it's better to abort after the receiption of a 
+       // complete word. The disable cuts the transmission immediatly and 
+       // releases the chip selects. This could result in unpredictable 
+       // behavior of connected external devices!
+       enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0;
+       WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
+
+       // flush fifos
+       WRITE_PERIPHERAL_REGISTER (IFX_SSC_XFCON_FIFO_FLUSH, info->mapbase + IFX_SSC_TXFCON);
+       WRITE_PERIPHERAL_REGISTER (IFX_SSC_XFCON_FIFO_FLUSH, info->mapbase + IFX_SSC_RXFCON);
+
+       // free txbuf
+       if (info->txbuf != NULL)
+       {
+               kfree (info->txbuf);
+               info->txbuf = NULL;
+       }
+
+       // wakeup read process
+       if (info->rxbuf != NULL)
+               wake_up_interruptible (&info->rwait);
+
+       // clear pending int's 
+       mask_and_ack_danube_irq(info->rxirq);
+       mask_and_ack_danube_irq(info->txirq);
+       mask_and_ack_danube_irq(info->errirq);
+
+       // clear error flags
+       WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ALL_ERROR, info->mapbase + IFX_SSC_WHBSTATE);
+
+       if (enabled)
+               WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
+
+}
+
+/*
+ * This routine is called whenever a port is opened.  It enforces
+ * exclusive opening of a port and enables interrupts, etc.
+ */
+int
+ifx_ssc_open (struct inode *inode, struct file *filp)
+{
+       struct ifx_ssc_port *info;
+       int line;
+       int from_kernel = 0;
+
+       if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1)) {
+               from_kernel = 1;
+               line = (int) inode;
+       } else {
+               line = MINOR (filp->f_dentry->d_inode->i_rdev);
+               filp->f_op = &ifx_ssc_fops;
+       }
+
+       /* don't open more minor devices than we can support */
+       if (line < 0 || line >= PORT_CNT)
+               return -ENXIO;
+
+       info = &isp[line];
+
+       /* exclusive open */
+       if (info->port_is_open != 0)
+               return -EBUSY;
+       info->port_is_open++;
+
+       disable_irq(info->rxirq);
+       disable_irq(info->txirq);
+       disable_irq(info->errirq);
+
+       /* Flush and enable TX/RX FIFO */
+       WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, info->mapbase + IFX_SSC_TXFCON);
+       WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, info->mapbase + IFX_SSC_RXFCON);
+
+       /* logically flush the software FIFOs */
+       info->rxbuf_ptr = 0;
+       info->txbuf_ptr = 0;
+
+       /* clear all error bits */
+       WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ALL_ERROR, info->mapbase + IFX_SSC_WHBSTATE);
+
+       // clear pending interrupts
+       mask_and_ack_danube_irq(info->rxirq);
+       mask_and_ack_danube_irq(info->txirq);
+       mask_and_ack_danube_irq(info->errirq);
+
+       WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
+
+       return 0;
+}
+EXPORT_SYMBOL(ifx_ssc_open);
+
+int
+ifx_ssc_close (struct inode *inode, struct file *filp)
+{
+       struct ifx_ssc_port *info;
+       int idx;
+
+       if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1))
+               idx = (int) inode;
+       else
+               idx = MINOR (filp->f_dentry->d_inode->i_rdev);
+
+       if (idx < 0 || idx >= PORT_CNT)
+               return -ENXIO;
+
+       info = &isp[idx];
+       if (!info)
+               return -ENXIO;
+
+       WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
+
+       ifx_ssc_abort(info);
+
+       info->port_is_open--;
+
+       return 0;
+}
+EXPORT_SYMBOL(ifx_ssc_close);
+
+static ssize_t
+ifx_ssc_read_helper_poll (struct ifx_ssc_port *info, char *buf, size_t len, int from_kernel)
+{
+       ssize_t ret_val;
+       unsigned long flags;
+
+       if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
+               return -EFAULT;
+       local_irq_save (flags);
+       info->rxbuf_ptr = info->rxbuf;
+       info->rxbuf_end = info->rxbuf + len;
+       local_irq_restore (flags);
+       /* Vinetic driver always works in IFX_SSC_MODE_RXTX */
+       /* TXRX in poll mode */
+       while (info->rxbuf_ptr < info->rxbuf_end)
+       {
+               if (info->txbuf_ptr < info->txbuf_end)
+                       tx_int (info);
+
+               rx_int (info);
+       };
+
+       ret_val = info->rxbuf_ptr - info->rxbuf;
+
+       return ret_val;
+}
+
+static ssize_t
+ifx_ssc_read_helper (struct ifx_ssc_port *info, char *buf, size_t len, int from_kernel)
+{
+       ssize_t ret_val;
+       unsigned long flags;
+       DECLARE_WAITQUEUE (wait, current);
+
+       if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
+               return -EFAULT;
+
+       local_irq_save (flags);
+       info->rxbuf_ptr = info->rxbuf;
+       info->rxbuf_end = info->rxbuf + len;
+
+       if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX)
+       {
+               if ((info->txbuf == NULL) || (info->txbuf != info->txbuf_ptr) || (info->txbuf_end != len + info->txbuf))
+               {
+                       local_irq_restore (flags);
+                       printk ("IFX SSC - %s: write must be called before calling " "read in combined RX/TX!\n", __func__);
+                       return -EFAULT;
+               }
+
+               local_irq_restore(flags);
+               tx_int (info);
+
+               if (info->txbuf_ptr < info->txbuf_end)
+                       enable_irq(info->txirq);
+
+               enable_irq(info->rxirq);
+       } else {
+               local_irq_restore(flags);
+               if (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
+                       return -EBUSY;
+               enable_irq(info->rxirq);
+               if (len < IFX_SSC_RXREQ_BLOCK_SIZE)
+                       WRITE_PERIPHERAL_REGISTER (len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
+               else
+                       WRITE_PERIPHERAL_REGISTER (IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
+       }
+
+       __add_wait_queue (&info->rwait, &wait);
+       set_current_state (TASK_INTERRUPTIBLE);
+
+       do {
+               local_irq_save (flags);
+               if (info->rxbuf_ptr >= info->rxbuf_end)
+                       break;
+
+               local_irq_restore (flags);
+
+               if (signal_pending (current))
+               {
+                       ret_val = -ERESTARTSYS;
+                       goto out;
+               }
+               schedule();
+       } while (1);
+
+       ret_val = info->rxbuf_ptr - info->rxbuf;
+       local_irq_restore (flags);
+
+out:
+       current->state = TASK_RUNNING;
+       __remove_wait_queue (&info->rwait, &wait);
+
+       return (ret_val);
+}
+
+static ssize_t
+ifx_ssc_write_helper (struct ifx_ssc_port *info, const char *buf,
+                     size_t len, int from_kernel)
+{
+       if (info->opts.modeRxTx == IFX_SSC_MODE_RX)
+               return -EFAULT;
+
+       info->txbuf_ptr = info->txbuf;
+       info->txbuf_end = len + info->txbuf;
+       if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
+       {
+               tx_int (info);
+               if (info->txbuf_ptr < info->txbuf_end)
+               {
+                       enable_irq(info->txirq);
+               }
+       }
+
+       return len;
+}
+
+ssize_t
+ifx_ssc_kread (int port, char *kbuf, size_t len)
+{
+       struct ifx_ssc_port *info;
+       ssize_t ret_val;
+
+       if (port < 0 || port >= PORT_CNT)
+               return -ENXIO;
+
+       if (len == 0)
+               return 0;
+
+       info = &isp[port];
+
+       if (info->rxbuf != NULL)
+       {
+               printk ("SSC device busy\n");
+               return -EBUSY;
+       }
+
+       info->rxbuf = kbuf;
+       if (info->rxbuf == NULL)
+       {
+               printk ("SSC device error\n");
+               return -EINVAL;
+       }
+
+       ret_val = ifx_ssc_read_helper_poll (info, kbuf, len, 1);
+       info->rxbuf = NULL;
+
+       disable_irq(info->rxirq);
+
+       return ret_val;
+}
+EXPORT_SYMBOL(ifx_ssc_kread);
+
+ssize_t
+ifx_ssc_kwrite (int port, const char *kbuf, size_t len)
+{
+       struct ifx_ssc_port *info;
+       ssize_t ret_val;
+
+       if (port < 0 || port >= PORT_CNT)
+               return -ENXIO;
+
+       if (len == 0)
+               return 0;
+
+       info = &isp[port];
+
+       // check if transmission in progress
+       if (info->txbuf != NULL)
+               return -EBUSY;
+
+       info->txbuf = (char *) kbuf;
+
+       ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 1);
+
+       if (ret_val < 0)
+               info->txbuf = NULL;
+
+       return ret_val;
+}
+EXPORT_SYMBOL(ifx_ssc_kwrite);
+
+static ssize_t
+ifx_ssc_read (struct file *filp, char *ubuf, size_t len, loff_t * off)
+{
+       ssize_t ret_val;
+       int idx;
+       struct ifx_ssc_port *info;
+
+       idx = MINOR (filp->f_dentry->d_inode->i_rdev);
+       info = &isp[idx];
+
+       if (info->rxbuf != NULL)
+               return -EBUSY;
+
+       info->rxbuf = kmalloc (len + 3, GFP_KERNEL);
+       if (info->rxbuf == NULL)
+               return -ENOMEM;
+
+       ret_val = ifx_ssc_read_helper (info, info->rxbuf, len, 0);
+       if (copy_to_user ((void *) ubuf, info->rxbuf, ret_val) != 0)
+               ret_val = -EFAULT;
+
+       disable_irq(info->rxirq);
+
+       kfree (info->rxbuf);
+       info->rxbuf = NULL;
+
+       return (ret_val);
+}
+
+static ssize_t
+ifx_ssc_write (struct file *filp, const char *ubuf, size_t len, loff_t * off)
+{
+       int idx;
+       struct ifx_ssc_port *info;
+       int ret_val;
+
+       if (len == 0)
+               return (0);
+
+       idx = MINOR (filp->f_dentry->d_inode->i_rdev);
+       info = &isp[idx];
+
+       if (info->txbuf != NULL)
+               return -EBUSY;
+
+       info->txbuf = kmalloc (len + 3, GFP_KERNEL);
+       if (info->txbuf == NULL)
+               return -ENOMEM;
+
+       ret_val = copy_from_user (info->txbuf, ubuf, len);
+       if (ret_val == 0)
+               ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 0);
+       else
+               ret_val = -EFAULT;
+
+       if (ret_val < 0)
+       {
+               kfree (info->txbuf);
+               info->txbuf = NULL;
+       }
+
+       return (ret_val);
+}
+
+static struct ifx_ssc_frm_status *
+ifx_ssc_frm_status_get (struct ifx_ssc_port *info)
+{
+       unsigned long tmp;
+
+       tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFSTAT);
+       info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0;
+       info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0;
+       info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET;
+       info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET;
+       tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON);
+       info->frm_status.EnIntAfterData = (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0;
+       info->frm_status.EnIntAfterPause = (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0;
+
+       return &info->frm_status;
+}
+
+
+static struct ifx_ssc_frm_opts *
+ifx_ssc_frm_control_get (struct ifx_ssc_port *info)
+{
+       unsigned long tmp;
+
+       tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON);
+       info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0;
+       info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
+       info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
+       info->frm_opts.IdleData = (tmp & IFX_SSC_SFCON_PAUSE_DATA_MASK) >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
+       info->frm_opts.IdleClock = (tmp & IFX_SSC_SFCON_PAUSE_CLOCK_MASK) >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
+       info->frm_opts.StopAfterPause = (tmp & IFX_SSC_SFCON_STOP_AFTER_PAUSE) > 0;
+
+       return &info->frm_opts;
+}
+
+static int
+ifx_ssc_frm_control_set (struct ifx_ssc_port *info)
+{
+       unsigned long tmp;
+
+       // check parameters
+       if ((info->frm_opts.DataLength > IFX_SSC_SFCON_DATA_LENGTH_MAX)
+           || (info->frm_opts.DataLength < 1)
+           || (info->frm_opts.PauseLength > IFX_SSC_SFCON_PAUSE_LENGTH_MAX)
+           || (info->frm_opts.PauseLength < 1)
+           || (info->frm_opts.IdleData & ~(IFX_SSC_SFCON_PAUSE_DATA_MASK >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET))
+           || (info->frm_opts.IdleClock & ~(IFX_SSC_SFCON_PAUSE_CLOCK_MASK >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET)))
+               return -EINVAL;
+
+       // read interrupt bits (they're not changed here)
+       tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON) &
+               (IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE | IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE);
+
+       // set all values with respect to it's bit position (for data and pause 
+       // length set N-1)
+       tmp = (info->frm_opts.DataLength - 1) << IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
+       tmp |= (info->frm_opts.PauseLength - 1) << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
+       tmp |= info->frm_opts.IdleData << IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
+       tmp |= info->frm_opts.IdleClock << IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
+       tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE;
+       tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE;
+
+       WRITE_PERIPHERAL_REGISTER(tmp, info->mapbase + IFX_SSC_SFCON);
+
+       return 0;
+}
+
+static int
+ifx_ssc_rxtx_mode_set (struct ifx_ssc_port *info, unsigned int val)
+{
+       unsigned long tmp;
+
+       if (!(info) || (val & ~(IFX_SSC_MODE_MASK)))
+               return -EINVAL;
+
+       if ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_BUSY)
+           || (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK))
+               return -EBUSY;
+
+       tmp = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
+       WRITE_PERIPHERAL_REGISTER (tmp, info->mapbase + IFX_SSC_CON);
+       info->opts.modeRxTx = val;
+
+       return 0;
+}
+
+static int
+ifx_ssc_sethwopts (struct ifx_ssc_port *info)
+{
+       unsigned long flags, bits;
+       struct ifx_ssc_hwopts *opts = &info->opts;
+
+       if ((opts->dataWidth < IFX_SSC_MIN_DATA_WIDTH)
+           || (opts->dataWidth > IFX_SSC_MAX_DATA_WIDTH))
+               return -EINVAL;
+
+       bits = (opts->dataWidth - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET;
+       bits |= IFX_SSC_CON_ENABLE_BYTE_VALID;
+
+       if (opts->rxOvErrDetect)
+               bits |= IFX_SSC_CON_RX_OFL_CHECK;
+       if (opts->rxUndErrDetect)
+               bits |= IFX_SSC_CON_RX_UFL_CHECK;
+       if (opts->txOvErrDetect)
+               bits |= IFX_SSC_CON_TX_OFL_CHECK;
+       if (opts->txUndErrDetect)
+               bits |= IFX_SSC_CON_TX_UFL_CHECK;
+       if (opts->loopBack)
+               bits |= IFX_SSC_CON_LOOPBACK_MODE;
+       if (opts->echoMode)
+               bits |= IFX_SSC_CON_ECHO_MODE_ON;
+       if (opts->headingControl)
+               bits |= IFX_SSC_CON_MSB_FIRST;
+       if (opts->clockPhase)
+               bits |= IFX_SSC_CON_LATCH_THEN_SHIFT;
+       if (opts->clockPolarity)
+               bits |= IFX_SSC_CON_CLOCK_FALL;
+
+       switch (opts->modeRxTx)
+       {
+       case IFX_SSC_MODE_TX:
+               bits |= IFX_SSC_CON_RX_OFF;
+               break;
+       case IFX_SSC_MODE_RX:
+               bits |= IFX_SSC_CON_TX_OFF;
+               break;
+       }
+
+       local_irq_save (flags);
+
+       WRITE_PERIPHERAL_REGISTER (bits, info->mapbase + IFX_SSC_CON);
+       WRITE_PERIPHERAL_REGISTER ((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
+                                  (info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), info->mapbase + IFX_SSC_GPOCON);
+
+       WRITE_PERIPHERAL_REGISTER (info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, info->mapbase + IFX_SSC_WHBGPOSTAT);
+
+       //master mode
+       if (opts->masterSelect)
+               WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_MASTER_SELECT, info->mapbase + IFX_SSC_WHBSTATE);
+       else
+               WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, info->mapbase + IFX_SSC_WHBSTATE);
+
+       // init serial framing
+       WRITE_PERIPHERAL_REGISTER (0, info->mapbase + IFX_SSC_SFCON);
+       /* set up the port pins */
+       //check for general requirements to switch (external) pad/pin characteristics
+       /* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */
+       /* p0.15 SPI_CS1(EEPROM), P0.13 SPI_CS3, */
+       /* Set p0.15 to alternative 01, others to 00 (In/OUT) */
+       *(DANUBE_GPIO_P0_DIR) = (*DANUBE_GPIO_P0_DIR) | (0xA000);
+       *(DANUBE_GPIO_P0_ALTSEL0) = (((*DANUBE_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000)));
+       *(DANUBE_GPIO_P0_ALTSEL1) = (((*DANUBE_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000)));
+       *(DANUBE_GPIO_P0_OD) = (*DANUBE_GPIO_P0_OD) | 0xA000;
+
+       /* p1.6 SPI_CS2(SFLASH), p1.0 SPI_DIN, p1.1 SPI_DOUT, p1.2 SPI_CLK */
+       *(DANUBE_GPIO_P1_DIR) = ((*DANUBE_GPIO_P1_DIR) | (0x46)) & (~1);
+       *(DANUBE_GPIO_P1_ALTSEL0) = ((*DANUBE_GPIO_P1_ALTSEL0) | (0x47));
+       *(DANUBE_GPIO_P1_ALTSEL1) = (*DANUBE_GPIO_P1_ALTSEL1) & (~0x47);
+       *(DANUBE_GPIO_P1_OD) = (*DANUBE_GPIO_P1_OD) | 0x0046;
+
+       /*CS3 */
+       /*TODO: CS4 CS5 CS6 */
+       *DANUBE_GPIO_P0_OUT = ((*DANUBE_GPIO_P0_OUT) | 0x2000);
+
+       local_irq_restore (flags);
+
+       return 0;
+}
+
+static int
+ifx_ssc_set_baud (struct ifx_ssc_port *info, unsigned int baud)
+{
+       unsigned int ifx_ssc_clock;
+       unsigned int br;
+       unsigned long flags;
+       bool enabled;
+       int retval = 0;
+
+       ifx_ssc_clock = ifx_ssc_get_kernel_clk(info);
+       if (ifx_ssc_clock == 0)
+       {
+               retval = -EINVAL;
+               goto out;
+       }
+
+       local_irq_save (flags);
+
+       enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
+       WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
+
+       br = (((ifx_ssc_clock >> 1) + baud / 2) / baud) - 1;
+       wmb();
+
+       if (br > 0xffff || ((br == 0) &&
+                       ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) {
+               local_irq_restore (flags);
+               printk ("%s: invalid baudrate %u\n", __func__, baud);
+               return -EINVAL;
+       }
+
+       WRITE_PERIPHERAL_REGISTER (br, info->mapbase + IFX_SSC_BR);
+
+       if (enabled)
+               WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
+
+       local_irq_restore(flags);
+
+out:
+       return retval;
+}
+
+static int
+ifx_ssc_hwinit (struct ifx_ssc_port *info)
+{
+       unsigned long flags;
+       bool enabled;
+
+       enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
+       WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
+
+       if (ifx_ssc_sethwopts (info) < 0)
+       {
+               printk ("%s: setting the hardware options failed\n", __func__);
+               return -EINVAL;
+       }
+
+       if (ifx_ssc_set_baud (info, info->baud) < 0)
+       {
+               printk ("%s: setting the baud rate failed\n", __func__);
+               return -EINVAL;
+       }
+
+       local_irq_save (flags);
+
+       /* TX FIFO */
+       WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE,
+                                  info->mapbase + IFX_SSC_TXFCON);
+       /* RX FIFO */
+       WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, 
+                                  info->mapbase + IFX_SSC_RXFCON);
+
+       local_irq_restore (flags);
+
+       if (enabled)
+               WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
+
+       return 0;
+}
+
+int
+ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data)
+{
+       struct ifx_ssc_port *info;
+       int line, ret_val = 0;
+       unsigned long flags;
+       unsigned long tmp;
+       int from_kernel = 0;
+
+       if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1))
+       {
+               from_kernel = 1;
+               line = (int) inode;
+       } else {
+               line = MINOR (filp->f_dentry->d_inode->i_rdev);
+       }
+
+       if (line < 0 || line >= PORT_CNT)
+               return -ENXIO;
+
+       info = &isp[line];
+
+       switch (cmd)
+       {
+       case IFX_SSC_STATS_READ:
+               /* data must be a pointer to a struct ifx_ssc_statistics */
+               if (from_kernel)
+                       memcpy ((void *) data, (void *) &info->stats,
+                               sizeof (struct ifx_ssc_statistics));
+               else if (copy_to_user ((void *) data,
+                                      (void *) &info->stats,
+                                      sizeof (struct ifx_ssc_statistics)))
+                       ret_val = -EFAULT;
+               break;
+       case IFX_SSC_STATS_RESET:
+               /* just resets the statistics counters */
+               memset ((void *) &info->stats, 0,
+                       sizeof (struct ifx_ssc_statistics));
+               break;
+       case IFX_SSC_BAUD_SET:
+               /* if the buffers are not empty then the port is */
+               /* busy and we shouldn't change things on-the-fly! */
+               if (!info->txbuf || !info->rxbuf ||
+                   (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE)
+                    & IFX_SSC_STATE_BUSY)) {
+                       ret_val = -EBUSY;
+                       break;
+               }
+               /* misuse flags */
+               if (from_kernel)
+                       flags = *((unsigned long *) data);
+               else if (copy_from_user ((void *) &flags,
+                                        (void *) data, sizeof (flags))) {
+                       ret_val = -EFAULT;
+                       break;
+               }
+               if (flags == 0) {
+                       ret_val = -EINVAL;
+                       break;
+               }
+               if (ifx_ssc_set_baud (info, flags) < 0) {
+                       ret_val = -EINVAL;
+                       break;
+               }
+               info->baud = flags;
+               break;
+       case IFX_SSC_BAUD_GET:
+               if (from_kernel)
+                       *((unsigned int *) data) = info->baud;
+               else if (copy_to_user ((void *) data,
+                                      (void *) &info->baud,
+                                      sizeof (unsigned long)))
+                       ret_val = -EFAULT;
+               break;
+       case IFX_SSC_RXTX_MODE_SET:
+               if (from_kernel)
+                       tmp = *((unsigned long *) data);
+               else if (copy_from_user ((void *) &tmp,
+                                        (void *) data, sizeof (tmp))) {
+                       ret_val = -EFAULT;
+                       break;
+               }
+               ret_val = ifx_ssc_rxtx_mode_set (info, tmp);
+               break;
+       case IFX_SSC_RXTX_MODE_GET:
+               tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CON) &
+                       (~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF));
+               if (from_kernel)
+                       *((unsigned int *) data) = tmp;
+               else if (copy_to_user ((void *) data,
+                                      (void *) &tmp, sizeof (tmp)))
+                       ret_val = -EFAULT;
+               break;
+
+       case IFX_SSC_ABORT:
+               ifx_ssc_abort (info);
+               break;
+
+       case IFX_SSC_GPO_OUT_SET:
+               if (from_kernel)
+                       tmp = *((unsigned long *) data);
+               else if (copy_from_user ((void *) &tmp,
+                                        (void *) data, sizeof (tmp))) {
+                       ret_val = -EFAULT;
+                       break;
+               }
+               if (tmp > IFX_SSC_MAX_GPO_OUT)
+                       ret_val = -EINVAL;
+               else
+                       WRITE_PERIPHERAL_REGISTER
+                               (1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
+                                info->mapbase + IFX_SSC_WHBGPOSTAT);
+               break;
+       case IFX_SSC_GPO_OUT_CLR:
+               if (from_kernel)
+                       tmp = *((unsigned long *) data);
+               else if (copy_from_user ((void *) &tmp,
+                                        (void *) data, sizeof (tmp))) {
+                       ret_val = -EFAULT;
+                       break;
+               }
+               if (tmp > IFX_SSC_MAX_GPO_OUT)
+                       ret_val = -EINVAL;
+               else {
+                       WRITE_PERIPHERAL_REGISTER
+                               (1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
+                                info->mapbase + IFX_SSC_WHBGPOSTAT);
+               }
+               break;
+       case IFX_SSC_GPO_OUT_GET:
+               tmp = READ_PERIPHERAL_REGISTER
+                       (info->mapbase + IFX_SSC_GPOSTAT);
+               if (from_kernel)
+                       *((unsigned int *) data) = tmp;
+               else if (copy_to_user ((void *) data,
+                                      (void *) &tmp, sizeof (tmp)))
+                       ret_val = -EFAULT;
+               break;
+       case IFX_SSC_FRM_STATUS_GET:
+               ifx_ssc_frm_status_get (info);
+               if (from_kernel)
+                       memcpy ((void *) data, (void *) &info->frm_status,
+                               sizeof (struct ifx_ssc_frm_status));
+               else if (copy_to_user ((void *) data,
+                                      (void *) &info->frm_status,
+                                      sizeof (struct ifx_ssc_frm_status)))
+                       ret_val = -EFAULT;
+               break;
+       case IFX_SSC_FRM_CONTROL_GET:
+               ifx_ssc_frm_control_get (info);
+               if (from_kernel)
+                       memcpy ((void *) data, (void *) &info->frm_opts,
+                               sizeof (struct ifx_ssc_frm_opts));
+               else if (copy_to_user ((void *) data,
+                                      (void *) &info->frm_opts,
+                                      sizeof (struct ifx_ssc_frm_opts)))
+                       ret_val = -EFAULT;
+               break;
+       case IFX_SSC_FRM_CONTROL_SET:
+               if (from_kernel)
+                       memcpy ((void *) &info->frm_opts, (void *) data,
+                               sizeof (struct ifx_ssc_frm_opts));
+               else if (copy_to_user ((void *) &info->frm_opts,
+                                      (void *) data,
+                                      sizeof (struct ifx_ssc_frm_opts))) {
+                       ret_val = -EFAULT;
+                       break;
+               }
+               ret_val = ifx_ssc_frm_control_set (info);
+               break;
+       case IFX_SSC_HWOPTS_SET:
+               /* data must be a pointer to a struct ifx_ssc_hwopts */
+               /* if the buffers are not empty then the port is */
+               /* busy and we shouldn't change things on-the-fly! */
+               if (!info->txbuf || !info->rxbuf ||
+                   (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE)
+                    & IFX_SSC_STATE_BUSY)) {
+                       ret_val = -EBUSY;
+                       break;
+               }
+               if (from_kernel)
+                       memcpy ((void *) &info->opts, (void *) data,
+                               sizeof (struct ifx_ssc_hwopts));
+               else if (copy_from_user ((void *) &info->opts,
+                                        (void *) data,
+                                        sizeof (struct ifx_ssc_hwopts))) {
+                       ret_val = -EFAULT;
+                       break;
+               }
+               if (ifx_ssc_hwinit (info) < 0) {
+                       ret_val = -EIO;
+               }
+               break;
+       case IFX_SSC_HWOPTS_GET:
+               /* data must be a pointer to a struct ifx_ssc_hwopts */
+               if (from_kernel)
+                       memcpy ((void *) data, (void *) &info->opts,
+                               sizeof (struct ifx_ssc_hwopts));
+               else if (copy_to_user ((void *) data,
+                                      (void *) &info->opts,
+                                      sizeof (struct ifx_ssc_hwopts)))
+                       ret_val = -EFAULT;
+               break;
+       default:
+               ret_val = -ENOIOCTLCMD;
+       }
+
+       return ret_val;
+}
+EXPORT_SYMBOL(ifx_ssc_ioctl);
+
+static int
+ifx_ssc1_read_proc (char *page, char **start, off_t offset, int count, int *eof, void *data)
+{
+       int off = 0;
+       unsigned long flags;
+
+       local_save_flags(flags);
+       local_irq_disable();
+
+       off += sprintf (page + off, "Statistics for Infineon Synchronous Serial Controller SSC1\n");
+       off += sprintf (page + off, "RX overflow errors %d\n", isp[0].stats.rxOvErr);
+       off += sprintf (page + off, "RX underflow errors %d\n", isp[0].stats.rxUnErr);
+       off += sprintf (page + off, "TX overflow errors %d\n", isp[0].stats.txOvErr);
+       off += sprintf (page + off, "TX underflow errors %d\n", isp[0].stats.txUnErr);
+       off += sprintf (page + off, "Abort errors %d\n", isp[0].stats.abortErr);
+       off += sprintf (page + off, "Mode errors %d\n", isp[0].stats.modeErr);
+       off += sprintf (page + off, "RX Bytes %d\n", isp[0].stats.rxBytes);
+       off += sprintf (page + off, "TX Bytes %d\n", isp[0].stats.txBytes);
+
+       local_irq_restore(flags);
+       *eof = 1;
+
+       return off;
+}
+
+int __init
+ifx_ssc_init (void)
+{
+       struct ifx_ssc_port *info;
+       int i, nbytes;
+       unsigned long flags;
+       int ret_val;
+
+       ret_val = -ENOMEM;
+       nbytes = PORT_CNT * sizeof(struct ifx_ssc_port);
+       isp = (struct ifx_ssc_port*)kmalloc(nbytes, GFP_KERNEL);
+
+       if (isp == NULL)
+       {
+               printk("%s: no memory for isp\n", __func__);
+               return (ret_val);
+       }
+       memset(isp, 0, nbytes);
+
+       ret_val = -ENXIO;
+       if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0)
+       {
+               printk ("Unable to register major %d for the Infineon SSC\n", maj);
+               if (maj == 0)
+               {
+                       goto errout;
+               } else {
+                       maj = 0;
+                       if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0)
+                       {
+                               printk ("Unable to register major %d for the Infineon SSC\n", maj);
+                               goto errout;
+                       }
+               }
+       }
+
+       if (maj == 0)
+               maj = i;
+
+       /* set default values in ifx_ssc_port */
+       for (i = 0; i < PORT_CNT; i++) {
+               info = &isp[i];
+               info->port_nr = i;
+               /* default values for the HwOpts */
+               info->opts.AbortErrDetect = IFX_SSC_DEF_ABRT_ERR_DETECT;
+               info->opts.rxOvErrDetect = IFX_SSC_DEF_RO_ERR_DETECT;
+               info->opts.rxUndErrDetect = IFX_SSC_DEF_RU_ERR_DETECT;
+               info->opts.txOvErrDetect = IFX_SSC_DEF_TO_ERR_DETECT;
+               info->opts.txUndErrDetect = IFX_SSC_DEF_TU_ERR_DETECT;
+               info->opts.loopBack = IFX_SSC_DEF_LOOP_BACK;
+               info->opts.echoMode = IFX_SSC_DEF_ECHO_MODE;
+               info->opts.idleValue = IFX_SSC_DEF_IDLE_DATA;
+               info->opts.clockPolarity = IFX_SSC_DEF_CLOCK_POLARITY;
+               info->opts.clockPhase = IFX_SSC_DEF_CLOCK_PHASE;
+               info->opts.headingControl = IFX_SSC_DEF_HEADING_CONTROL;
+               info->opts.dataWidth = IFX_SSC_DEF_DATA_WIDTH;
+               info->opts.modeRxTx = IFX_SSC_DEF_MODE_RXTX;
+               info->opts.gpoCs = IFX_SSC_DEF_GPO_CS;
+               info->opts.gpoInv = IFX_SSC_DEF_GPO_INV;
+               info->opts.masterSelect = IFX_SSC_DEF_MASTERSLAVE;
+               info->baud = IFX_SSC_DEF_BAUDRATE;
+               info->rxbuf = NULL;
+               info->txbuf = NULL;
+               /* values specific to SSC1 */
+               if (i == 0) {
+                       info->mapbase = DANUBE_SSC1_BASE_ADDR;
+                       info->txirq = DANUBE_SSC_TIR;
+                       info->rxirq = DANUBE_SSC_RIR;
+                       info->errirq = DANUBE_SSC_EIR;
+               }
+
+               WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, info->mapbase + IFX_SSC_CLC);
+
+               init_waitqueue_head (&info->rwait);
+
+               local_irq_save (flags);
+
+               // init serial framing register
+               WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_SFCON, info->mapbase + IFX_SSC_SFCON);
+
+               ret_val = request_irq(info->txirq, ifx_ssc_tx_int, SA_INTERRUPT, "ifx_ssc_tx", info);
+               if (ret_val)
+               {
+                       printk("%s: unable to get irq %d\n", __func__, info->txirq);
+                       local_irq_restore(flags);
+                       goto errout;
+               }
+
+               ret_val = request_irq(info->rxirq, ifx_ssc_rx_int, SA_INTERRUPT, "ifx_ssc_rx", info);
+               if (ret_val)
+               {
+                       printk ("%s: unable to get irq %d\n", __func__, info->rxirq);
+                       local_irq_restore (flags);
+                       goto irqerr;
+               }
+
+               ret_val = request_irq(info->errirq, ifx_ssc_err_int, SA_INTERRUPT,"ifx_ssc_err", info);
+               if (ret_val)
+               {
+                       printk ("%s: unable to get irq %d\n", __func__, info->errirq);
+                       local_irq_restore (flags);
+                       goto irqerr;
+               }
+               WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_IRNEN, info->mapbase + IFX_SSC_IRN_EN);
+
+               enable_irq(info->txirq);
+               enable_irq(info->rxirq);
+               enable_irq(info->errirq);
+
+               local_irq_restore (flags);
+       }
+
+       for (i = 0; i < PORT_CNT; i++) {
+               info = &isp[i];
+               if (ifx_ssc_hwinit (info) < 0)
+               {
+                       printk ("%s: hardware init failed for port %d\n", __func__, i);
+                       goto irqerr;
+               }
+       }
+
+       create_proc_read_entry ("driver/ssc1", 0, NULL, ifx_ssc1_read_proc, NULL);
+
+       return 0;
+
+irqerr:
+       free_irq(isp[0].txirq, &isp[0]);
+       free_irq(isp[0].rxirq, &isp[0]);
+       free_irq(isp[0].errirq, &isp[0]);
+errout:
+       kfree (isp);
+       return (ret_val);
+}
+
+void
+ifx_ssc_cleanup_module (void)
+{
+       int i;
+
+       for (i = 0; i < PORT_CNT; i++) {
+               WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, isp[i].mapbase + IFX_SSC_WHBSTATE);
+               free_irq(isp[i].txirq, &isp[i]);
+               free_irq(isp[i].rxirq, &isp[i]);
+               free_irq(isp[i].errirq, &isp[i]);
+       }
+       kfree (isp);
+       remove_proc_entry ("driver/ssc1", NULL);
+}
+
+module_init(ifx_ssc_init);
+module_exit(ifx_ssc_cleanup_module);
+
+
+inline int
+ifx_ssc_cs_low (u32 pin)
+{
+       int ret = 0;
+       if ((ret = ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_CLR, (unsigned long) &pin)))
+               printk ("clear CS %d fails\n", pin);
+       wmb ();
+
+       return ret;
+}
+EXPORT_SYMBOL(ifx_ssc_cs_low);
+
+inline int
+ifx_ssc_cs_high (u32 pin)
+{
+       int ret = 0;
+       if ((ret = ifx_ssc_ioctl((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_SET, (unsigned long) &pin)))
+               printk ("set CS %d fails\n", pin);
+       wmb ();
+
+       return ret;
+}
+EXPORT_SYMBOL(ifx_ssc_cs_high);
+
+static int
+ssc_session (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
+{
+       int ret = 0;
+
+       char *ssc_tx_buf = NULL;
+       char *ssc_rx_buf = NULL;
+       int eff_size = 0;
+       u8 mode = 0;
+
+       if (tx_buf == NULL && tx_len == 0 && rx_buf == NULL && rx_len == 0) {
+               printk ("invalid parameters\n");
+               ret = -EINVAL;
+               goto ssc_session_exit;
+       }
+       else if (tx_buf == NULL || tx_len == 0) {
+               if (rx_buf != NULL && rx_len != 0) {
+                       mode = IFX_SSC_MODE_RX;
+               }
+               else {
+                       printk ("invalid parameters\n");
+                       ret = -EINVAL;
+                       goto ssc_session_exit;
+               }
+       }
+       else if (rx_buf == NULL || rx_len == 0) {
+               if (tx_buf != NULL && tx_len != 0) {
+                       mode = IFX_SSC_MODE_TX;
+               }
+               else {
+                       printk ("invalid parameters\n");
+                       ret = -EINVAL;
+                       goto ssc_session_exit;
+               }
+       }
+       else {
+               mode = IFX_SSC_MODE_RXTX;
+       }
+
+       if (mode == IFX_SSC_MODE_RXTX) {
+               eff_size = tx_len + rx_len;
+       }
+       else if (mode == IFX_SSC_MODE_RX) {
+               eff_size = rx_len;
+       }
+       else {
+               eff_size = tx_len;
+       }
+
+       //4 bytes alignment,  required by driver
+       /* change by TaiCheng */
+       //if (in_irq()){
+       if (1) {
+               ssc_tx_buf =
+                       (char *) kmalloc (sizeof (char) *
+                                         ((eff_size + 3) & (~3)),
+                                         GFP_ATOMIC);
+               ssc_rx_buf =
+                       (char *) kmalloc (sizeof (char) *
+                                         ((eff_size + 3) & (~3)),
+                                         GFP_ATOMIC);
+       }
+       else {
+               ssc_tx_buf =
+                       (char *) kmalloc (sizeof (char) *
+                                         ((eff_size + 3) & (~3)),
+                                         GFP_KERNEL);
+               ssc_rx_buf =
+                       (char *) kmalloc (sizeof (char) *
+                                         ((eff_size + 3) & (~3)),
+                                         GFP_KERNEL);
+       }
+       if (ssc_tx_buf == NULL || ssc_rx_buf == NULL) {
+               printk ("no memory for size of %d\n", eff_size);
+               ret = -ENOMEM;
+               goto ssc_session_exit;
+       }
+       memset ((void *) ssc_tx_buf, 0, eff_size);
+       memset ((void *) ssc_rx_buf, 0, eff_size);
+
+       if (tx_len > 0) {
+               memcpy (ssc_tx_buf, tx_buf, tx_len);
+       }
+
+       ret = ifx_ssc_kwrite (0, ssc_tx_buf, eff_size);
+
+       if (ret > 0) {
+               ssc_tx_buf = NULL;      //should be freed by ifx_ssc_kwrite
+       }
+
+       if (ret != eff_size) {
+               printk ("ifx_ssc_write return %d\n", ret);
+               goto ssc_session_exit;
+       }
+       ret = ifx_ssc_kread (0, ssc_rx_buf, eff_size);
+       if (ret != eff_size) {
+               printk ("ifx_ssc_read return %d\n", ret);
+               goto ssc_session_exit;
+       }
+
+       memcpy (rx_buf, ssc_rx_buf + tx_len, rx_len);
+
+       if (mode == IFX_SSC_MODE_TX) {
+               ret = tx_len;
+       }
+       else {
+               ret = rx_len;
+       }
+      ssc_session_exit:
+
+       if (ssc_tx_buf != NULL)
+               kfree (ssc_tx_buf);
+       if (ssc_rx_buf != NULL)
+               kfree (ssc_rx_buf);
+
+       if (ret < 0) {
+               printk ("ssc session fails\n");
+       }
+       return ret;
+}
+
+int
+ifx_ssc_txrx (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
+{
+       return ssc_session(tx_buf, tx_len, rx_buf, rx_len);
+}
+EXPORT_SYMBOL(ifx_ssc_txrx);
+
+int
+ifx_ssc_tx (char *tx_buf, u32 tx_len)
+{
+       return ssc_session(tx_buf, tx_len, NULL, 0);
+}
+EXPORT_SYMBOL(ifx_ssc_tx);
+
+int
+ifx_ssc_rx (char *rx_buf, u32 rx_len)
+{
+       return ssc_session(NULL, 0, rx_buf, rx_len);
+}
+EXPORT_SYMBOL(ifx_ssc_rx);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION("danube ssc driver");
+
diff --git a/target/linux/ifxmips/files/drivers/char/watchdog/danube_wdt.c b/target/linux/ifxmips/files/drivers/char/watchdog/danube_wdt.c
new file mode 100644 (file)
index 0000000..be2b339
--- /dev/null
@@ -0,0 +1,287 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2006 infineon
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+
+#include <asm/uaccess.h>
+#include <linux/errno.h>
+#include <linux/proc_fs.h>
+#include <linux/ioctl.h>
+#include <linux/module.h>
+#include <asm-mips/danube/danube_wdt.h>
+#include <asm-mips/danube/danube.h>
+
+
+// TODO remove magic numbers and weirdo macros
+
+extern unsigned int danube_get_fpi_hz (void);
+
+static int danube_wdt_inuse = 0;
+static int danube_wdt_major = 0;
+
+int
+danube_wdt_enable (unsigned int timeout)
+{
+       unsigned int wdt_cr = 0;
+       unsigned int wdt_reload = 0;
+       unsigned int wdt_clkdiv, wdt_pwl, ffpi;
+       int retval = 0;
+
+       /* clock divider & prewarning limit */
+       wdt_clkdiv = 1 << (7 * DANUBE_BIU_WDT_CR_CLKDIV_GET(readl(DANUBE_BIU_WDT_CR)));
+       wdt_pwl = 0x8000 >> DANUBE_BIU_WDT_CR_PWL_GET(readl(DANUBE_BIU_WDT_CR));
+
+       //TODO
+       printk("WARNING FUNCTION CALL MISSING!!!");
+       //ffpi = cgu_get_io_region_clock();
+       printk("cpu clock = %d\n", ffpi);
+
+       /* caculate reload value */
+       wdt_reload = (timeout * (ffpi / wdt_clkdiv)) + wdt_pwl;
+
+       printk("wdt_pwl=0x%x, wdt_clkdiv=%d, ffpi=%d, wdt_reload = 0x%x\n",
+               wdt_pwl, wdt_clkdiv, ffpi, wdt_reload);
+
+       if (wdt_reload > 0xFFFF)
+       {
+               printk ("timeout too large %d\n", timeout);
+               retval = -EINVAL;
+               goto out;
+       }
+
+       /* Write first part of password access */
+       writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
+
+       wdt_cr = readl(DANUBE_BIU_WDT_CR);
+       wdt_cr &= (!DANUBE_BIU_WDT_CR_PW_SET(0xff) &
+                  !DANUBE_BIU_WDT_CR_PWL_SET(0x3) &
+                  !DANUBE_BIU_WDT_CR_CLKDIV_SET(0x3) &
+                  !DANUBE_BIU_WDT_CR_RELOAD_SET(0xffff));
+
+       wdt_cr |= (DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2) |
+                  DANUBE_BIU_WDT_CR_PWL_SET(DANUBE_BIU_WDT_CR_PWL_GET(readl(DANUBE_BIU_WDT_CR))) |
+                  DANUBE_BIU_WDT_CR_CLKDIV_SET(DANUBE_BIU_WDT_CR_CLKDIV_GET(readl(DANUBE_BIU_WDT_CR))) |
+                  DANUBE_BIU_WDT_CR_RELOAD_SET(wdt_reload) |
+                  DANUBE_BIU_WDT_CR_GEN);
+
+       writel(wdt_cr, DANUBE_BIU_WDT_CR);
+
+       printk("watchdog enabled\n");
+
+out:
+       return retval;
+}
+
+void
+danube_wdt_disable (void)
+{
+       writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
+       writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2), DANUBE_BIU_WDT_CR);
+
+       printk("watchdog disabled\n");
+}
+
+/* passed LPEN or DSEN */
+void
+danube_wdt_enable_feature (int en, int type)
+{
+       unsigned int wdt_cr = 0;
+
+       writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
+
+       wdt_cr = readl(DANUBE_BIU_WDT_CR);
+
+       if (en)
+       {
+               wdt_cr &= (~DANUBE_BIU_WDT_CR_PW_SET(0xff));
+               wdt_cr |= (DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2) | type);
+       } else {
+               wdt_cr &= (~DANUBE_BIU_WDT_CR_PW_SET(0xff) & ~type);
+               wdt_cr |= DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2);
+       }
+
+       writel(wdt_cr, DANUBE_BIU_WDT_CR);
+}
+
+void
+danube_wdt_prewarning_limit (int pwl)
+{
+       unsigned int wdt_cr = 0;
+
+       wdt_cr = readl(DANUBE_BIU_WDT_CR);
+       writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
+
+       wdt_cr &= 0xf300ffff;
+       wdt_cr |= (DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2) | DANUBE_BIU_WDT_CR_PWL_SET(pwl));
+
+       /* Set reload value in second password access */
+       writel(wdt_cr, DANUBE_BIU_WDT_CR);
+}
+
+void
+danube_wdt_set_clkdiv (int clkdiv)
+{
+       unsigned int wdt_cr = 0;
+
+       wdt_cr = readl(DANUBE_BIU_WDT_CR);
+       writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
+
+       wdt_cr &= 0xfc00ffff;
+       wdt_cr |= (DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2) | DANUBE_BIU_WDT_CR_CLKDIV_SET(clkdiv));
+
+       /* Set reload value in second password access */
+       writel(wdt_cr, DANUBE_BIU_WDT_CR);
+}
+
+static int
+danube_wdt_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
+          unsigned long arg)
+{
+       int result = 0;
+       static int timeout = -1;
+       unsigned int user_arg;
+
+       if ((cmd != DANUBE_WDT_IOC_STOP) && (cmd != DANUBE_WDT_IOC_PING) && (cmd != DANUBE_WDT_IOC_GET_STATUS))
+       {
+               if (copy_from_user((void *) &user_arg, (void *) arg, sizeof (int))){
+                       result = -EINVAL;
+                       goto out;
+               }
+       }
+
+       switch (cmd)
+       {
+       case DANUBE_WDT_IOC_START:
+               if ((result = danube_wdt_enable(user_arg)) < 0)
+                       timeout = -1;
+               else
+                       timeout = user_arg;
+               break;
+
+       case DANUBE_WDT_IOC_STOP:
+               printk("disable watch dog timer\n");
+               danube_wdt_disable();
+               break;
+
+       case DANUBE_WDT_IOC_PING:
+               if (timeout < 0)
+                       result = -EIO;
+               else
+                       result = danube_wdt_enable(timeout);
+               break;
+
+       case DANUBE_WDT_IOC_GET_STATUS:
+               user_arg = readl(DANUBE_BIU_WDT_SR);
+               copy_to_user((int*)arg, (int*)&user_arg, sizeof(int));
+               break;
+
+       case DANUBE_WDT_IOC_SET_PWL:
+               danube_wdt_prewarning_limit(user_arg);
+               break;
+
+       case DANUBE_WDT_IOC_SET_DSEN:
+               danube_wdt_enable_feature(user_arg, DANUBE_BIU_WDT_CR_DSEN);
+               break;
+
+       case DANUBE_WDT_IOC_SET_LPEN:
+               danube_wdt_enable_feature(user_arg, DANUBE_BIU_WDT_CR_LPEN);
+               break;
+
+       case DANUBE_WDT_IOC_SET_CLKDIV:
+               danube_wdt_set_clkdiv(user_arg);
+               break;
+
+       default:
+               printk("unknown watchdog iotcl\n");
+       }
+
+out:
+       return result;
+}
+
+static int
+danube_wdt_open (struct inode *inode, struct file *file)
+{
+       if (danube_wdt_inuse)
+               return -EBUSY;
+
+       danube_wdt_inuse = 1;
+
+       return 0;
+}
+
+static int
+danube_wdt_release (struct inode *inode, struct file *file)
+{
+       danube_wdt_inuse = 0;
+
+       return 0;
+}
+
+int
+danube_wdt_register_proc_read (char *buf, char **start, off_t offset, int count,
+                       int *eof, void *data)
+{
+       int len = 0;
+
+       len += sprintf (buf + len, "DANUBE_BIU_WDT_PROC_READ\n");
+       len += sprintf (buf + len, "DANUBE_BIU_WDT_CR(0x%08x)   : 0x%08x\n",
+                       (unsigned int)DANUBE_BIU_WDT_CR, readl(DANUBE_BIU_WDT_CR));
+       len += sprintf (buf + len, "DANUBE_BIU_WDT_SR(0x%08x)   : 0x%08x\n",
+                       (unsigned int)DANUBE_BIU_WDT_SR, readl(DANUBE_BIU_WDT_SR));
+
+       *eof = 1;
+
+       return len;
+}
+
+static struct file_operations wdt_fops = {
+      .owner = THIS_MODULE,
+      .ioctl = danube_wdt_ioctl,
+      .open = danube_wdt_open,
+      .release = danube_wdt_release,
+};
+
+int __init
+danube_wdt_init_module (void)
+{
+       danube_wdt_major = register_chrdev(0, "wdt", &wdt_fops);
+
+       if (danube_wdt_major < 0)
+       {
+               printk("cannot register watchdog device\n");
+
+               return -EINVAL;
+       }
+
+       create_proc_read_entry("danube_wdt", 0, NULL, danube_wdt_register_proc_read, NULL);
+
+       printk("danube watchdog loaded\n");
+
+       return 0;
+}
+
+void
+danube_wdt_cleanup_module (void)
+{
+       unregister_chrdev(danube_wdt_major, "wdt");
+       remove_proc_entry("danube_wdt", NULL);
+}
+
+module_init(danube_wdt_init_module);
+module_exit(danube_wdt_cleanup_module);
diff --git a/target/linux/ifxmips/files/drivers/mtd/maps/danube.c b/target/linux/ifxmips/files/drivers/mtd/maps/danube.c
new file mode 100644 (file)
index 0000000..25e9df3
--- /dev/null
@@ -0,0 +1,194 @@
+/*
+ *  Driver for DANUBE flashmap 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE
+ * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <asm/io.h>
+
+#include <linux/init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/cfi.h>
+#include <asm/danube/danube.h>
+#include <linux/magic.h>
+
+static struct map_info
+danube_map = {
+       .name = "DANUBE_FLASH",
+       .bankwidth = 2,
+       .size = 0x400000,
+};
+
+static map_word
+danube_read16 (struct map_info * map, unsigned long adr)
+{
+       map_word temp;
+
+       adr ^= 2;
+       temp.x[0] = *((__u16 *) (map->virt + adr));
+
+       return temp;
+}
+
+static void
+danube_write16 (struct map_info *map, map_word d, unsigned long adr)
+{
+       adr ^= 2;
+       *((__u16 *) (map->virt + adr)) = d.x[0];
+}
+
+void
+danube_copy_from (struct map_info *map, void *to, unsigned long from, ssize_t len)
+{
+       u8 *p;
+       u8 *to_8;
+
+       from = (unsigned long) (from + map->virt);
+       p = (u8 *) from;
+       to_8 = (u8 *) to;
+       while(len--){
+               *to_8++ = *p++;
+       }
+}
+
+void
+danube_copy_to (struct map_info *map, unsigned long to, const void *from, ssize_t len)
+{
+       u8 *p =  (u8*) from;
+       u8 *to_8;
+
+       to += (unsigned long) map->virt;
+       to_8 = (u8*)to;
+       while(len--){
+               *p++ = *to_8++;
+       }
+}
+
+static struct mtd_partition
+danube_partitions[4] = {
+       {
+               name:"U-Boot",
+               offset:0x00000000,
+               size:0x00020000,
+       },
+       {
+               name:"U-Boot-Env",
+               offset:0x00020000,
+               size:0x00010000,
+       },
+       {
+               name:"kernel",
+               offset:0x00030000,
+               size:0x0,
+       },
+       {
+               name:"rootfs",
+               offset:0x0,
+               size:0x0,
+       },
+};
+
+#define DANUBE_FLASH_START             0x10000000
+#define DANUBE_FLASH_MAX               0x2000000
+
+int
+find_uImage_size (unsigned long start_offset){
+       unsigned long temp;
+
+       danube_copy_from(&danube_map, &temp, start_offset + 12, 4);
+       printk("kernel size is %ld \n", temp + 0x40);
+       return temp + 0x40;
+}
+
+int
+detect_squashfs_partition (unsigned long start_offset){
+       unsigned long temp;
+
+       danube_copy_from(&danube_map, &temp, start_offset, 4);
+
+       return (temp == SQUASHFS_MAGIC);
+}
+
+int __init
+init_danube_mtd (void)
+{
+       struct mtd_info *danube_mtd = NULL;
+       struct mtd_partition *parts = NULL;
+       unsigned long uimage_size;
+
+       writel(0x1d7ff, DANUBE_EBU_BUSCON0);
+
+       danube_map.read = danube_read16;
+       danube_map.write = danube_write16;
+       danube_map.copy_from = danube_copy_from;
+       danube_map.copy_to = danube_copy_to;
+
+       danube_map.phys = DANUBE_FLASH_START;
+       danube_map.virt = ioremap_nocache(DANUBE_FLASH_START, DANUBE_FLASH_MAX);
+       danube_map.size = DANUBE_FLASH_MAX;
+       if (!danube_map.virt) {
+               printk(KERN_WARNING "Failed to ioremap!\n");
+               return -EIO;
+       }
+
+       danube_mtd = (struct mtd_info *) do_map_probe("cfi_probe", &danube_map);
+       if (!danube_mtd) {
+               iounmap(danube_map.virt);
+               printk("probing failed\n");
+               return -ENXIO;
+       }
+
+       danube_mtd->owner = THIS_MODULE;
+
+       uimage_size = find_uImage_size(danube_partitions[2].offset);
+
+       if(detect_squashfs_partition(danube_partitions[2].offset + uimage_size)){
+               printk("Found a squashfs following the uImage\n");
+       } else {
+               uimage_size &= ~0xffff;
+               uimage_size += 0x10000;
+       }
+
+       danube_partitions[2].size = uimage_size;
+       danube_partitions[3].offset = danube_partitions[2].offset + danube_partitions[2].size;
+       danube_partitions[3].size = ((danube_mtd->size >> 20) * 1024 * 1024) - danube_partitions[3].offset;
+
+       parts = &danube_partitions[0];
+       add_mtd_partitions(danube_mtd, parts, 4);
+
+       printk("Added danube flash with %dMB\n", danube_mtd->size >> 20);
+       return 0;
+}
+
+static void
+__exit
+cleanup_danube_mtd (void)
+{
+}
+
+module_init (init_danube_mtd);
+module_exit (cleanup_danube_mtd);
+
+MODULE_LICENSE ("GPL");
+MODULE_AUTHOR ("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION ("MTD map driver for DANUBE boards");
diff --git a/target/linux/ifxmips/files/drivers/net/danube_mii0.c b/target/linux/ifxmips/files/drivers/net/danube_mii0.c
new file mode 100644 (file)
index 0000000..354ccc3
--- /dev/null
@@ -0,0 +1,433 @@
+/*
+ *   drivers/net/danube_mii0.c
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2005 Infineon
+ *
+ *   Rewrite of Infineon Danube code, thanks to infineon for the support,
+ *   software and hardware
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <asm/uaccess.h>
+#include <linux/in.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/skbuff.h>
+#include <linux/mm.h>
+#include <linux/ethtool.h>
+#include <asm/checksum.h>
+#include <linux/init.h>
+#include <asm/delay.h>
+#include <asm/danube/danube.h>
+#include <asm/danube/danube_mii0.h>
+#include <asm/danube/danube_dma.h>
+#include <asm/danube/danube_pmu.h>
+
+static struct net_device danube_mii0_dev;
+static unsigned char u_boot_ethaddr[MAX_ADDR_LEN];
+
+void
+danube_write_mdio (u32 phy_addr, u32 phy_reg, u16 phy_data)
+{
+       u32 val = MDIO_ACC_REQUEST |
+               ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
+               ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
+               phy_data;
+
+       while (readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
+       writel(val, DANUBE_PPE32_MDIO_ACC);
+}
+
+unsigned short
+danube_read_mdio (u32 phy_addr, u32 phy_reg)
+{
+       u32 val = MDIO_ACC_REQUEST | MDIO_ACC_READ |
+               ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
+               ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
+
+       writel(val, DANUBE_PPE32_MDIO_ACC);
+       while (readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
+       val = readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
+
+       return val;
+}
+
+int
+danube_switch_open (struct net_device *dev)
+{
+       struct switch_priv* priv = (struct switch_priv*)dev->priv;
+       struct dma_device_info* dma_dev = priv->dma_device;
+       int i;
+
+       for (i = 0; i < dma_dev->max_rx_chan_num; i++)
+       {
+               if ((dma_dev->rx_chan[i])->control == DANUBE_DMA_CH_ON)
+                       (dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]);
+       }
+
+       netif_start_queue(dev);
+
+       return 0;
+}
+
+int
+switch_release (struct net_device *dev){
+       struct switch_priv* priv = (struct switch_priv*)dev->priv;
+       struct dma_device_info* dma_dev = priv->dma_device;
+       int i;
+
+       for (i = 0; i < dma_dev->max_rx_chan_num; i++)
+               dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]);
+
+       netif_stop_queue(dev);
+
+       return 0;
+}
+
+int
+switch_hw_receive (struct net_device* dev,struct dma_device_info* dma_dev)
+{
+       struct switch_priv *priv = (struct switch_priv*)dev->priv;
+       unsigned char* buf = NULL;
+       struct sk_buff *skb = NULL;
+       int len = 0;
+
+       len = dma_device_read(dma_dev, &buf, (void**)&skb);
+
+       if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE)
+       {
+               printk("packet too large %d\n",len);
+               goto switch_hw_receive_err_exit;
+       }
+
+       /* remove CRC */
+       len -= 4;
+       if (skb == NULL )
+       {
+               printk("cannot restore pointer\n");
+               goto switch_hw_receive_err_exit;
+       }
+
+       if (len > (skb->end - skb->tail))
+       {
+               printk("BUG, len:%d end:%p tail:%p\n", (len+4), skb->end, skb->tail);
+               goto switch_hw_receive_err_exit;
+       }
+
+       skb_put(skb, len);
+       skb->dev = dev;
+       skb->protocol = eth_type_trans(skb, dev);
+       netif_rx(skb);
+
+       priv->stats.rx_packets++;
+       priv->stats.rx_bytes += len;
+
+       return 0;
+
+switch_hw_receive_err_exit:
+       if (len == 0)
+       {
+               if(skb)
+                       dev_kfree_skb_any(skb);
+               priv->stats.rx_errors++;
+               priv->stats.rx_dropped++;
+
+               return -EIO;
+       } else {
+               return len;
+       }
+}
+
+int
+switch_hw_tx (char *buf, int len, struct net_device *dev)
+{
+       int ret = 0;
+       struct switch_priv *priv = dev->priv;
+       struct dma_device_info* dma_dev = priv->dma_device;
+
+       ret = dma_device_write(dma_dev, buf, len, priv->skb);
+
+       return ret;
+}
+
+int
+switch_tx (struct sk_buff *skb, struct net_device *dev)
+{
+       int len;
+       char *data;
+       struct switch_priv *priv = dev->priv;
+       struct dma_device_info* dma_dev = priv->dma_device;
+
+       len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
+       data = skb->data;
+       priv->skb = skb;
+       dev->trans_start = jiffies;
+       // TODO we got more than 1 dma channel, so we should do something intelligent
+       // here to select one
+       dma_dev->current_tx_chan = 0;
+
+       wmb();
+
+       if (switch_hw_tx(data, len, dev) != len)
+       {
+               dev_kfree_skb_any(skb);
+               priv->stats.tx_errors++;
+               priv->stats.tx_dropped++;
+       } else {
+               priv->stats.tx_packets++;
+               priv->stats.tx_bytes+=len;
+       }
+
+       return 0;
+}
+
+void
+switch_tx_timeout (struct net_device *dev)
+{
+       int i;
+       struct switch_priv* priv = (struct switch_priv*)dev->priv;
+
+       priv->stats.tx_errors++;
+
+       for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
+       {
+               priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]);
+       }
+
+       netif_wake_queue(dev);
+
+       return;
+}
+
+int
+dma_intr_handler (struct dma_device_info* dma_dev, int status)
+{
+       int i;
+
+       switch (status)
+       {
+       case RCV_INT:
+               switch_hw_receive(&danube_mii0_dev, dma_dev);
+               break;
+
+       case TX_BUF_FULL_INT:
+               printk("tx buffer full\n");
+               netif_stop_queue(&danube_mii0_dev);
+               for (i = 0; i < dma_dev->max_tx_chan_num; i++)
+               {
+                       if ((dma_dev->tx_chan[i])->control==DANUBE_DMA_CH_ON)
+                               dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]);
+               }
+               break;
+
+       case TRANSMIT_CPT_INT:
+               for (i = 0; i < dma_dev->max_tx_chan_num; i++)
+                       dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]);
+
+               netif_wake_queue(&danube_mii0_dev);
+               break;
+       }
+
+       return 0;
+}
+
+unsigned char*
+danube_etop_dma_buffer_alloc (int len, int *byte_offset, void **opt)
+{
+       unsigned char *buffer = NULL;
+       struct sk_buff *skb = NULL;
+
+       skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE);
+       if (skb == NULL)
+               return NULL;
+
+       buffer = (unsigned char*)(skb->data);
+       skb_reserve(skb, 2);
+       *(int*)opt = (int)skb;
+       *byte_offset = 2;
+
+       return buffer;
+}
+
+void
+danube_etop_dma_buffer_free (unsigned char *dataptr, void *opt)
+{
+       struct sk_buff *skb = NULL;
+
+       if(opt == NULL)
+       {
+               kfree(dataptr);
+       } else {
+               skb = (struct sk_buff*)opt;
+               dev_kfree_skb_any(skb);
+       }
+}
+
+static struct net_device_stats*
+danube_get_stats (struct net_device *dev)
+{
+       return (struct net_device_stats *)dev->priv;
+}
+
+static int
+switch_init (struct net_device *dev)
+{
+       u64 retval = 0;
+       int i;
+       struct switch_priv *priv;
+
+       ether_setup(dev);
+
+       printk("%s up\n", dev->name);
+
+       dev->open = danube_switch_open;
+       dev->stop = switch_release;
+       dev->hard_start_xmit = switch_tx;
+       dev->get_stats = danube_get_stats;
+       dev->tx_timeout = switch_tx_timeout;
+       dev->watchdog_timeo = 10 * HZ;
+       dev->priv = kmalloc(sizeof(struct switch_priv), GFP_KERNEL);
+
+       if (dev->priv == NULL)
+               return -ENOMEM;
+
+       memset(dev->priv, 0, sizeof(struct switch_priv));
+       priv = dev->priv;
+
+       priv->dma_device = dma_device_reserve("PPE");
+
+       if (!priv->dma_device){
+               BUG();
+               return -ENODEV;
+       }
+
+       priv->dma_device->buffer_alloc = &danube_etop_dma_buffer_alloc;
+       priv->dma_device->buffer_free = &danube_etop_dma_buffer_free;
+       priv->dma_device->intr_handler = &dma_intr_handler;
+       priv->dma_device->max_rx_chan_num = 4;
+
+       for (i = 0; i < priv->dma_device->max_rx_chan_num; i++)
+       {
+               priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE;
+               priv->dma_device->rx_chan[i]->control = DANUBE_DMA_CH_ON;
+       }
+
+       for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
+       {
+               if(i == 0)
+                       priv->dma_device->tx_chan[i]->control = DANUBE_DMA_CH_ON;
+               else
+                       priv->dma_device->tx_chan[i]->control = DANUBE_DMA_CH_OFF;
+       }
+
+       dma_device_register(priv->dma_device);
+
+       /*read the mac address from the mac table and put them into the mac table.*/
+       for (i = 0; i < 6; i++)
+       {
+               retval += u_boot_ethaddr[i];
+       }
+
+       //TODO
+       /* ethaddr not set in u-boot ? */
+       if (retval == 0)
+       {
+               printk("use default MAC address\n");
+               dev->dev_addr[0] = 0x00;
+               dev->dev_addr[1] = 0x11;
+               dev->dev_addr[2] = 0x22;
+               dev->dev_addr[3] = 0x33;
+               dev->dev_addr[4] = 0x44;
+               dev->dev_addr[5] = 0x55;
+       } else {
+               for (i = 0; i < 6; i++)
+                       dev->dev_addr[i] = u_boot_ethaddr[i];
+       }
+
+       return 0;
+}
+
+static void
+danube_sw_chip_init (int mode)
+{
+       danube_pmu_enable(DANUBE_PMU_PWDCR_DMA);
+       danube_pmu_enable(DANUBE_PMU_PWDCR_PPE);
+
+       if(mode == REV_MII_MODE)
+               writel((readl(DANUBE_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, DANUBE_PPE32_CFG);
+       else if(mode == MII_MODE)
+               writel((readl(DANUBE_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, DANUBE_PPE32_CFG);
+
+       writel(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, DANUBE_PPE32_IG_PLEN_CTRL);
+
+       writel(PPE32_CGEN, DANUBE_PPE32_ENET_MAC_CFG);
+
+       wmb();
+}
+
+int __init
+switch_init_module(void)
+{
+       int result = 0;
+
+       danube_mii0_dev.init = switch_init;
+
+       strcpy(danube_mii0_dev.name, "eth%d");
+       SET_MODULE_OWNER(dev);
+
+       result = register_netdev(&danube_mii0_dev);
+       if (result)
+       {
+               printk("error %i registering device \"%s\"\n", result, danube_mii0_dev.name);
+               goto out;
+       }
+
+       /* danube eval kit connects the phy/switch in REV mode */
+       danube_sw_chip_init(REV_MII_MODE);
+       printk("danube MAC driver loaded!\n");
+
+out:
+       return result;
+}
+
+static void __exit
+switch_cleanup(void)
+{
+       struct switch_priv *priv = (struct switch_priv*)danube_mii0_dev.priv;
+
+       printk("danube_mii0 cleanup\n");
+
+       dma_device_unregister(priv->dma_device);
+       dma_device_release(priv->dma_device);
+       kfree(priv->dma_device);
+       kfree(danube_mii0_dev.priv);
+       unregister_netdev(&danube_mii0_dev);
+
+       return;
+}
+
+module_init(switch_init_module);
+module_exit(switch_cleanup);
diff --git a/target/linux/ifxmips/files/drivers/serial/danube_asc.c b/target/linux/ifxmips/files/drivers/serial/danube_asc.c
new file mode 100644 (file)
index 0000000..b50b1e7
--- /dev/null
@@ -0,0 +1,608 @@
+/*
+ *  Driver for DANUBEASC serial ports
+ *
+ *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * Copyright (C) 2004 Infineon IFAP DC COM CPE
+ * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/major.h>
+#include <linux/string.h>
+#include <linux/fcntl.h>
+#include <linux/ptrace.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/circ_buf.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+#include <linux/irq.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/bitops.h>
+#include <asm/danube/danube.h>
+#include <asm/danube/danube_irq.h>
+#include <asm/danube/danube_serial.h>
+
+#define PORT_DANUBEASC  111
+
+#include <linux/serial_core.h>
+
+#define UART_DUMMY_UER_RX 1
+
+static void danubeasc_tx_chars(struct uart_port *port);
+extern void prom_printf(const char * fmt, ...);
+static struct uart_port danubeasc_port;
+static struct uart_driver danubeasc_reg;
+static unsigned int uartclk = 0;
+extern unsigned int danube_get_fpi_hz(void);
+
+static void
+danubeasc_stop_tx (struct uart_port *port)
+{
+       /* fifo underrun shuts up after firing once */
+       return;
+}
+
+static void
+danubeasc_start_tx (struct uart_port *port)
+{
+       unsigned long flags;
+
+       local_irq_save(flags);
+       danubeasc_tx_chars(port);
+       local_irq_restore(flags);
+
+       return;
+}
+
+static void
+danubeasc_stop_rx (struct uart_port *port)
+{
+       /* clear the RX enable bit */
+       writel(ASCWHBSTATE_CLRREN, DANUBE_ASC1_WHBSTATE);
+}
+
+static void
+danubeasc_enable_ms (struct uart_port *port)
+{
+       /* no modem signals */
+       return;
+}
+
+static void
+danubeasc_rx_chars (struct uart_port *port)
+{
+       struct tty_struct *tty = port->info->tty;
+       unsigned int ch = 0, rsr = 0, fifocnt;
+
+       fifocnt = readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_RXFFLMASK;
+       while (fifocnt--)
+       {
+               u8 flag = TTY_NORMAL;
+               ch = readl(DANUBE_ASC1_RBUF);
+               rsr = (readl(DANUBE_ASC1_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
+               tty_flip_buffer_push(tty);
+               port->icount.rx++;
+
+               /*
+                * Note that the error handling code is
+                * out of the main execution path
+                */
+               if (rsr & ASCSTATE_ANY) {
+                       if (rsr & ASCSTATE_PE) {
+                               port->icount.parity++;
+                               writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE, DANUBE_ASC1_WHBSTATE);
+                       } else if (rsr & ASCSTATE_FE) {
+                               port->icount.frame++;
+                               writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRFE, DANUBE_ASC1_WHBSTATE);
+                       }
+                       if (rsr & ASCSTATE_ROE) {
+                               port->icount.overrun++;
+                               writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRROE, DANUBE_ASC1_WHBSTATE);
+                       }
+
+                       rsr &= port->read_status_mask;
+
+                       if (rsr & ASCSTATE_PE)
+                               flag = TTY_PARITY;
+                       else if (rsr & ASCSTATE_FE)
+                               flag = TTY_FRAME;
+               }
+
+               if ((rsr & port->ignore_status_mask) == 0)
+                       tty_insert_flip_char(tty, ch, flag);
+
+               if (rsr & ASCSTATE_ROE)
+                       /*
+                        * Overrun is special, since it's reported
+                        * immediately, and doesn't affect the current
+                        * character
+                        */
+                       tty_insert_flip_char(tty, 0, TTY_OVERRUN);
+       }
+       if (ch != 0)
+               tty_flip_buffer_push(tty);
+
+       return;
+}
+
+
+static void
+danubeasc_tx_chars (struct uart_port *port)
+{
+       struct circ_buf *xmit = &port->info->xmit;
+
+       if (uart_tx_stopped(port)) {
+               danubeasc_stop_tx(port);
+               return;
+       }
+
+       while(((readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
+                               >> ASCFSTAT_TXFFLOFF) != DANUBEASC_TXFIFO_FULL)
+       {
+               if (port->x_char) {
+                       writel(port->x_char, DANUBE_ASC1_TBUF);
+                       port->icount.tx++;
+                       port->x_char = 0;
+                       continue;
+               }
+
+               if (uart_circ_empty(xmit))
+                       break;
+
+               writel(port->info->xmit.buf[port->info->xmit.tail], DANUBE_ASC1_TBUF);
+               xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+               port->icount.tx++;
+       }
+
+       if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+               uart_write_wakeup(port);
+}
+
+static irqreturn_t
+danubeasc_tx_int (int irq, void *port)
+{
+       writel(ASC_IRNCR_TIR, DANUBE_ASC1_IRNCR);
+       danubeasc_start_tx(port);
+       mask_and_ack_danube_irq(irq);
+
+       return IRQ_HANDLED;
+}
+
+static irqreturn_t
+danubeasc_er_int (int irq, void *port)
+{
+       /* clear any pending interrupts */
+       writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE |
+                       ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, DANUBE_ASC1_WHBSTATE);
+
+       return IRQ_HANDLED;
+}
+
+static irqreturn_t
+danubeasc_rx_int (int irq, void *port)
+{
+       writel(ASC_IRNCR_RIR, DANUBE_ASC1_IRNCR);
+       danubeasc_rx_chars((struct uart_port *) port);
+       mask_and_ack_danube_irq(irq);
+
+       return IRQ_HANDLED;
+}
+
+static unsigned int
+danubeasc_tx_empty (struct uart_port *port)
+{
+       int status;
+
+       status = readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK;
+
+       return status ? 0 : TIOCSER_TEMT;
+}
+
+static unsigned int
+danubeasc_get_mctrl (struct uart_port *port)
+{
+       return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
+}
+
+static void
+danubeasc_set_mctrl (struct uart_port *port, u_int mctrl)
+{
+       return;
+}
+
+static void
+danubeasc_break_ctl (struct uart_port *port, int break_state)
+{
+       return;
+}
+
+static void
+danubeasc1_hw_init (void)
+{
+       /* this setup was probably already done in ROM/u-boot  but we do it again*/
+       /* TODO: GPIO pins are multifunction */
+       writel(readl(DANUBE_ASC1_CLC) & ~DANUBE_ASC1_CLC_DISS, DANUBE_ASC1_CLC);
+       writel((readl(DANUBE_ASC1_CLC) & ~ASCCLC_RMCMASK) | (1 << ASCCLC_RMCOFFSET), DANUBE_ASC1_CLC);
+       writel(0, DANUBE_ASC1_PISEL);
+       writel(((DANUBEASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) &
+               ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, DANUBE_ASC1_TXFCON);
+       writel(((DANUBEASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) &
+               ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, DANUBE_ASC1_RXFCON);
+       wmb ();
+
+       /*framing, overrun, enable */
+       writel(readl(DANUBE_ASC1_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN,
+               DANUBE_ASC1_CON);
+}
+
+static int
+danubeasc_startup (struct uart_port *port)
+{
+       unsigned long flags;
+       int retval;
+
+       /* this assumes: CON.BRS = CON.FDE = 0 */
+       if (uartclk == 0)
+               uartclk = danube_get_fpi_hz();
+
+       danubeasc_port.uartclk = uartclk;
+
+       danubeasc1_hw_init();
+
+       local_irq_save(flags);
+
+       retval = request_irq(DANUBEASC1_RIR, danubeasc_rx_int, IRQF_DISABLED, "asc_rx", port);
+       if (retval){
+               printk("failed to request danubeasc_rx_int\n");
+               return retval;
+       }
+
+       retval = request_irq(DANUBEASC1_TIR, danubeasc_tx_int, IRQF_DISABLED, "asc_tx", port);
+       if (retval){
+               printk("failed to request danubeasc_tx_int\n");
+               goto err1;
+       }
+
+       retval = request_irq(DANUBEASC1_EIR, danubeasc_er_int, IRQF_DISABLED, "asc_er", port);
+       if (retval){
+               printk("failed to request danubeasc_er_int\n");
+               goto err2;
+       }
+
+       writel(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX,
+               DANUBE_ASC1_IRNREN);
+
+       local_irq_restore(flags);
+
+       return 0;
+
+err2:
+       free_irq(DANUBEASC1_TIR, port);
+
+err1:
+       free_irq(DANUBEASC1_RIR, port);
+       local_irq_restore(flags);
+
+       return retval;
+}
+
+static void
+danubeasc_shutdown (struct uart_port *port)
+{
+       free_irq(DANUBEASC1_RIR, port);
+       free_irq(DANUBEASC1_TIR, port);
+       free_irq(DANUBEASC1_EIR, port);
+       /*
+        * disable the baudrate generator to disable the ASC
+        */
+       writel(0, DANUBE_ASC1_CON);
+
+       /* flush and then disable the fifos */
+       writel(readl(DANUBE_ASC1_RXFCON) | ASCRXFCON_RXFFLU, DANUBE_ASC1_RXFCON);
+       writel(readl(DANUBE_ASC1_RXFCON) & ~ASCRXFCON_RXFEN, DANUBE_ASC1_RXFCON);
+       writel(readl(DANUBE_ASC1_TXFCON) | ASCTXFCON_TXFFLU, DANUBE_ASC1_TXFCON);
+       writel(readl(DANUBE_ASC1_TXFCON) & ~ASCTXFCON_TXFEN, DANUBE_ASC1_TXFCON);
+}
+
+static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
+{
+       unsigned int cflag;
+       unsigned int iflag;
+       unsigned int quot;
+       unsigned int baud;
+       unsigned int con = 0;
+       unsigned long flags;
+
+       cflag = new->c_cflag;
+       iflag = new->c_iflag;
+
+       /* byte size and parity */
+       switch (cflag & CSIZE) {
+       case CS7:
+               con = ASCCON_M_7ASYNC;
+               break;
+
+       case CS5:
+       case CS6:
+       default:
+               con = ASCCON_M_8ASYNC;
+               break;
+       }
+
+       if (cflag & CSTOPB)
+               con |= ASCCON_STP;
+
+       if (cflag & PARENB) {
+               if (!(cflag & PARODD))
+                       con &= ~ASCCON_ODD;
+               else
+                       con |= ASCCON_ODD;
+       }
+
+       port->read_status_mask = ASCSTATE_ROE;
+       if (iflag & INPCK)
+               port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
+
+       port->ignore_status_mask = 0;
+       if (iflag & IGNPAR)
+               port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
+
+       if (iflag & IGNBRK) {
+               /*
+                * If we're ignoring parity and break indicators,
+                * ignore overruns too (for real raw support).
+                */
+               if (iflag & IGNPAR)
+                       port->ignore_status_mask |= ASCSTATE_ROE;
+       }
+
+       if ((cflag & CREAD) == 0)
+               port->ignore_status_mask |= UART_DUMMY_UER_RX;
+
+       /* set error signals  - framing, parity  and overrun, enable receiver */
+       con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
+
+       local_irq_save(flags);
+
+       /* set up CON */
+       writel(readl(DANUBE_ASC1_CON) | con, DANUBE_ASC1_CON);
+
+       /* Set baud rate - take a divider of 2 into account */
+    baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
+       quot = uart_get_divisor(port, baud);
+       quot = quot / 2 - 1;
+
+       /* disable the baudrate generator */
+       writel(readl(DANUBE_ASC1_CON) & ~ASCCON_R, DANUBE_ASC1_CON);
+
+       /* make sure the fractional divider is off */
+       writel(readl(DANUBE_ASC1_CON) & ~ASCCON_FDE, DANUBE_ASC1_CON);
+
+       /* set up to use divisor of 2 */
+       writel(readl(DANUBE_ASC1_CON) & ~ASCCON_BRS, DANUBE_ASC1_CON);
+
+       /* now we can write the new baudrate into the register */
+       writel(quot, DANUBE_ASC1_BG);
+
+       /* turn the baudrate generator back on */
+       writel(readl(DANUBE_ASC1_CON) | ASCCON_R, DANUBE_ASC1_CON);
+
+       /* enable rx */
+       writel(ASCWHBSTATE_SETREN, DANUBE_ASC1_WHBSTATE);
+
+       local_irq_restore(flags);
+}
+
+static const char*
+danubeasc_type (struct uart_port *port)
+{
+       return port->type == PORT_DANUBEASC ? "DANUBEASC" : NULL;
+}
+
+static void
+danubeasc_release_port (struct uart_port *port)
+{
+       return;
+}
+
+static int
+danubeasc_request_port (struct uart_port *port)
+{
+       return 0;
+}
+
+static void
+danubeasc_config_port (struct uart_port *port, int flags)
+{
+       if (flags & UART_CONFIG_TYPE) {
+               port->type = PORT_DANUBEASC;
+               danubeasc_request_port(port);
+       }
+}
+
+static int
+danubeasc_verify_port (struct uart_port *port, struct serial_struct *ser)
+{
+       int ret = 0;
+       if (ser->type != PORT_UNKNOWN && ser->type != PORT_DANUBEASC)
+               ret = -EINVAL;
+       if (ser->irq < 0 || ser->irq >= NR_IRQS)
+               ret = -EINVAL;
+       if (ser->baud_base < 9600)
+               ret = -EINVAL;
+       return ret;
+}
+
+static struct uart_ops danubeasc_pops = {
+       .tx_empty =             danubeasc_tx_empty,
+       .set_mctrl =    danubeasc_set_mctrl,
+       .get_mctrl =    danubeasc_get_mctrl,
+       .stop_tx =              danubeasc_stop_tx,
+       .start_tx =             danubeasc_start_tx,
+       .stop_rx =              danubeasc_stop_rx,
+       .enable_ms =    danubeasc_enable_ms,
+       .break_ctl =    danubeasc_break_ctl,
+       .startup =              danubeasc_startup,
+       .shutdown =             danubeasc_shutdown,
+       .set_termios =  danubeasc_set_termios,
+       .type =                 danubeasc_type,
+       .release_port = danubeasc_release_port,
+       .request_port = danubeasc_request_port,
+       .config_port =  danubeasc_config_port,
+       .verify_port =  danubeasc_verify_port,
+};
+
+static struct uart_port danubeasc_port = {
+               membase:        (void *)DANUBE_ASC1_BASE_ADDR,
+               mapbase:        DANUBE_ASC1_BASE_ADDR,
+               iotype:         SERIAL_IO_MEM,
+               irq:            DANUBEASC1_RIR,
+               uartclk:        0,
+               fifosize:       16,
+               unused:         {DANUBEASC1_TIR, DANUBEASC1_EIR},
+               type:           PORT_DANUBEASC,
+               ops:            &danubeasc_pops,
+               flags:          ASYNC_BOOT_AUTOCONF,
+};
+
+static void
+danubeasc_console_write (struct console *co, const char *s, u_int count)
+{
+       int i, fifocnt;
+       unsigned long flags;
+
+       local_irq_save(flags);
+       for (i = 0; i < count; i++)
+       {
+               /* wait until the FIFO is not full */
+               do
+               {
+                       fifocnt = (readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
+                                       >> ASCFSTAT_TXFFLOFF;
+               } while (fifocnt == DANUBEASC_TXFIFO_FULL);
+
+               if (s[i] == '\0')
+               {
+                       break;
+               }
+
+               if (s[i] == '\n')
+               {
+                       writel('\r', DANUBE_ASC1_TBUF);
+                       do
+                       {
+                               fifocnt = (readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
+                                       >> ASCFSTAT_TXFFLOFF;
+                       } while (fifocnt == DANUBEASC_TXFIFO_FULL);
+               }
+               writel(s[i], DANUBE_ASC1_TBUF);
+       }
+
+       local_irq_restore(flags);
+}
+
+static int __init
+danubeasc_console_setup (struct console *co, char *options)
+{
+       struct uart_port *port;
+       int baud = 115200;
+       int bits = 8;
+       int parity = 'n';
+       int flow = 'n';
+
+       if (uartclk == 0)
+               uartclk = danube_get_fpi_hz();
+       co->index = 0;
+       port = &danubeasc_port;
+       danubeasc_port.uartclk = uartclk;
+       danubeasc_port.type = PORT_DANUBEASC;
+
+       if (options){
+               uart_parse_options(options, &baud, &parity, &bits, &flow);
+       }
+
+       return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+static struct uart_driver danubeasc_reg;
+static struct console danubeasc_console = {
+       name:           "ttyS",
+       write:          danubeasc_console_write,
+       device:         uart_console_device,
+       setup:          danubeasc_console_setup,
+       flags:          CON_PRINTBUFFER,
+       index:          -1,
+       data:           &danubeasc_reg,
+};
+
+static int __init
+danubeasc_console_init (void)
+{
+       register_console(&danubeasc_console);
+       return 0;
+}
+console_initcall(danubeasc_console_init);
+
+static struct uart_driver danubeasc_reg = {
+       .owner =                        THIS_MODULE,
+       .driver_name =          "serial",
+       .dev_name =                     "ttyS",
+       .major =                        TTY_MAJOR,
+       .minor =                        64,
+       .nr =                           1,
+       .cons =                         &danubeasc_console,
+};
+
+static int __init
+danubeasc_init (void)
+{
+       unsigned char res;
+
+       uart_register_driver(&danubeasc_reg);
+       res = uart_add_one_port(&danubeasc_reg, &danubeasc_port);
+
+       return res;
+}
+
+static void __exit
+danubeasc_exit (void)
+{
+       uart_unregister_driver(&danubeasc_reg);
+}
+
+module_init(danubeasc_init);
+module_exit(danubeasc_exit);
+
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION("MIPS Danube serial port driver");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube.h
new file mode 100644 (file)
index 0000000..5bad876
--- /dev/null
@@ -0,0 +1,358 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2005 infineon
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+#ifndef _DANUBE_H__
+#define _DANUBE_H__
+
+
+/*------------ GENERAL */
+
+#define BOARD_SYSTEM_TYPE              "DANUBE"
+
+#define IOPORT_RESOURCE_START  0x10000000
+#define IOPORT_RESOURCE_END            0xffffffff
+#define IOMEM_RESOURCE_START   0x10000000
+#define IOMEM_RESOURCE_END             0xffffffff
+
+
+/*------------ ASC1 */
+
+#define DANUBE_ASC1_BASE_ADDR  (KSEG1 + 0x1E100C00)
+
+/* FIFO status register */
+#define DANUBE_ASC1_FSTAT              ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0048))
+#define ASCFSTAT_TXFFLMASK             0x3F00
+#define ASCFSTAT_TXFFLOFF              8
+
+/* ASC1 transmit buffer */
+#define DANUBE_ASC1_TBUF               ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0020))
+
+/* channel operating modes */
+#define ASCOPT_CSIZE                   0x3
+#define ASCOPT_CS7                             0x1
+#define ASCOPT_CS8                             0x2
+#define ASCOPT_PARENB                  0x4
+#define ASCOPT_STOPB                   0x8
+#define ASCOPT_PARODD                  0x0
+#define ASCOPT_CREAD                   0x20
+
+/* hardware modified control register */
+#define DANUBE_ASC1_WHBSTATE   ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0018))
+
+/* receive buffer register */
+#define DANUBE_ASC1_RBUF               ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0024))
+
+/* status register */
+#define DANUBE_ASC1_STATE              ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0014))
+
+/* interrupt control */
+#define DANUBE_ASC1_IRNCR              ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F8))
+
+#define ASC_IRNCR_TIR                  0x4
+#define ASC_IRNCR_RIR                  0x2
+#define ASC_IRNCR_EIR                  0x4
+
+/* clock control */
+#define DANUBE_ASC1_CLC                        ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0000))
+
+#define DANUBE_ASC1_CLC_DISS   0x2
+
+/* port input select register */
+#define DANUBE_ASC1_PISEL              ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0004))
+
+/* tx fifo */
+#define DANUBE_ASC1_TXFCON             ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0044))
+
+/* rx fifo */
+#define DANUBE_ASC1_RXFCON             ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0040))
+
+/* control */
+#define DANUBE_ASC1_CON                        ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0010))
+
+/* timer reload */
+#define DANUBE_ASC1_BG                 ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0050))
+
+/* int enable */
+#define DANUBE_ASC1_IRNREN             ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F4))
+
+#define ASC_IRNREN_RX_BUF              0x8
+#define ASC_IRNREN_TX_BUF              0x4
+#define ASC_IRNREN_ERR                 0x2
+#define ASC_IRNREN_TX                  0x1
+
+
+/*------------ RCU */
+
+#define DANUBE_RCU_BASE_ADDR   0xBF203000
+
+/* reset request */
+#define DANUBE_RCU_REQ                 ((u32*)(DANUBE_RCU_BASE_ADDR + 0x0010))
+#define DANUBE_RST_ALL                 0x40000000
+
+
+/*------------ MCD */
+
+#define DANUBE_MCD_BASE_ADDR   (KSEG1 + 0x1F106000)
+
+/* chip id */
+#define DANUBE_MCD_CHIPID              ((u32*)(DANUBE_MCD_BASE_ADDR + 0x0028))
+
+
+/*------------ GPTU */
+
+#define DANUBE_GPTU_BASE_ADDR  0xB8000300
+
+/* clock control register */
+#define DANUBE_GPTU_GPT_CLC            ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0000))
+
+/* captur reload register */
+#define DANUBE_GPTU_GPT_CAPREL ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0030))
+
+/* timer 6 control register */
+#define DANUBE_GPTU_GPT_T6CON  ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0020))
+
+
+/*------------ EBU */
+
+#define DANUBE_EBU_BASE_ADDR   0xBE105300
+
+/* bus configuration register */
+#define DANUBE_EBU_BUSCON0             ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0060))
+#define DANUBE_EBU_PCC_CON             ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0090))
+#define DANUBE_EBU_PCC_IEN             ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A4))
+#define DANUBE_EBU_PCC_ISTAT   ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A0))
+
+
+/*------------ CGU */
+
+#define DANUBE_CGU_BASE_ADDR   0xBF103000
+
+/* clock mux */
+#define DANUBE_CGU_SYS                 ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0010))
+#define DANUBE_CGU_IFCCR               ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0018))
+#define DANUBE_CGU_PCICR               ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0034))
+
+#define CLOCK_60M                              60000000
+#define CLOCK_83M                              83333333
+#define CLOCK_111M                             111111111
+#define CLOCK_133M                             133333333
+#define CLOCK_167M                             166666667
+#define CLOCK_333M                             333333333
+
+
+/*------------ CGU */
+
+#define DANUBE_PMU_BASE_ADDR   (KSEG1 + 0x1F102000)
+
+#define DANUBE_PMU_PWDCR               ((u32*)(DANUBE_PMU_BASE_ADDR + 0x001C))
+#define DANUBE_PMU_PWDSR               ((u32*)(DANUBE_PMU_BASE_ADDR + 0x0020))
+
+
+/*------------ ICU */
+
+#define DANUBE_ICU_BASE_ADDR   0xBF880200
+
+
+#define DANUBE_ICU_IM0_ISR             ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0000))
+#define DANUBE_ICU_IM0_IER             ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0008))
+#define DANUBE_ICU_IM0_IOSR            ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0010))
+#define DANUBE_ICU_IM0_IRSR            ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0018))
+#define DANUBE_ICU_IM0_IMR             ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0020))
+
+#define DANUBE_ICU_IM1_ISR             ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0028))
+
+#define DANUBE_ICU_OFFSET              (DANUBE_ICU_IM1_ISR - DANUBE_ICU_IM0_ISR)
+
+
+/*------------ ETOP */
+
+#define DANUBE_PPE32_BASE_ADDR 0xBE180000
+
+#define ETHERNET_PACKET_DMA_BUFFER_SIZE                0x600
+
+#define DANUBE_PPE32_MEM_MAP   (DANUBE_PPE32_BASE_ADDR + 0x10000 )
+
+#define MII_MODE 1
+
+#define REV_MII_MODE 2
+
+/* mdio access */
+#define DANUBE_PPE32_MDIO_ACC  ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1804))
+
+#define MDIO_ACC_REQUEST               0x80000000
+#define MDIO_ACC_READ                  0x40000000
+#define MDIO_ACC_ADDR_MASK             0x1f
+#define MDIO_ACC_ADDR_OFFSET   0x15
+#define MDIO_ACC_REG_MASK              0xff
+#define MDIO_ACC_REG_OFFSET            0x10
+#define MDIO_ACC_VAL_MASK              0xffff
+
+/* configuration */
+#define DANUBE_PPE32_CFG               ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1808))
+
+#define PPE32_MII_MASK                 0xfffffffc
+#define PPE32_MII_NORMAL               0x8
+#define PPE32_MII_REVERSE              0xe
+
+/* packet length */
+#define DANUBE_PPE32_IG_PLEN_CTRL      ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1820))
+
+#define PPE32_PLEN_OVER                        0x5ee
+#define PPE32_PLEN_UNDER               0x400000
+
+/* enet */
+#define DANUBE_PPE32_ENET_MAC_CFG      ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1840))
+
+#define PPE32_CGEN                             0x800
+
+
+/*------------ DMA */
+#define DANUBE_DMA_BASE_ADDR   0xBE104100
+
+#define DANUBE_DMA_CS                  ((u32*)(DANUBE_DMA_BASE_ADDR + 0x18))
+#define DANUBE_DMA_CIE                 ((u32*)(DANUBE_DMA_BASE_ADDR + 0x2C))
+#define DANUBE_DMA_IRNEN               ((u32*)(DANUBE_DMA_BASE_ADDR + 0xf4))
+#define DANUBE_DMA_CCTRL               ((u32*)(DANUBE_DMA_BASE_ADDR + 0x1C))
+#define DANUBE_DMA_CIS                 ((u32*)(DANUBE_DMA_BASE_ADDR + 0x28))
+#define DANUBE_DMA_CDLEN               ((u32*)(DANUBE_DMA_BASE_ADDR + 0x24))
+#define DANUBE_DMA_PS                  ((u32*)(DANUBE_DMA_BASE_ADDR + 0x40))
+#define DANUBE_DMA_PCTRL               ((u32*)(DANUBE_DMA_BASE_ADDR + 0x44))
+#define DANUBE_DMA_CTRL                        ((u32*)(DANUBE_DMA_BASE_ADDR + 0x10))
+#define DANUBE_DMA_CPOLL               ((u32*)(DANUBE_DMA_BASE_ADDR + 0x14))
+#define DANUBE_DMA_CDBA                        ((u32*)(DANUBE_DMA_BASE_ADDR + 0x20))
+
+
+/*------------ PCI */
+#define PCI_CR_PR_BASE_ADDR            (KSEG1 + 0x1E105400)
+
+#define PCI_CR_FCI_ADDR_MAP0   ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C0))
+#define PCI_CR_FCI_ADDR_MAP1   ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C4))
+#define PCI_CR_FCI_ADDR_MAP2   ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C8))
+#define PCI_CR_FCI_ADDR_MAP3   ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00CC))
+#define PCI_CR_FCI_ADDR_MAP4   ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D0))
+#define PCI_CR_FCI_ADDR_MAP5   ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D4))
+#define PCI_CR_FCI_ADDR_MAP6   ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D8))
+#define PCI_CR_FCI_ADDR_MAP7   ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00DC))
+#define PCI_CR_CLK_CTRL                        ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0000))
+#define PCI_CR_PCI_MOD                 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0030))
+#define PCI_CR_PC_ARB                  ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0080))
+#define PCI_CR_FCI_ADDR_MAP11hg        ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E4))
+#define PCI_CR_BAR11MASK               ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0044))
+#define PCI_CR_BAR12MASK               ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0048))
+#define PCI_CR_BAR13MASK               ((u32*)(PCI_CR_PR_BASE_ADDR + 0x004C))
+#define PCI_CS_BASE_ADDR1              ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0010))
+#define PCI_CR_PCI_ADDR_MAP11  ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0064))
+#define PCI_CR_FCI_BURST_LENGTH        ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E8))
+#define PCI_CR_PCI_EOI                 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x002C))
+
+#define PCI_CS_PR_BASE_ADDR            (KSEG1 + 0x17000000)
+
+#define PCI_CS_STS_CMD                 ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0004))
+
+#define PCI_MASTER0_REQ_MASK_2BITS     8
+#define PCI_MASTER1_REQ_MASK_2BITS     10
+#define PCI_MASTER2_REQ_MASK_2BITS     12
+#define INTERNAL_ARB_ENABLE_BIT                0
+
+
+/*------------ WDT */
+
+#define DANUBE_WDT_BASE_ADDR   (KSEG1 + 0x1F880000)
+
+#define DANUBE_BIU_WDT_CR              ((u32*)(DANUBE_WDT_BASE_ADDR + 0x03F0))
+#define DANUBE_BIU_WDT_SR              ((u32*)(DANUBE_WDT_BASE_ADDR + 0x03F8))
+
+#define DANUBE_BIU_WDT_CR_GEN                          (1 << 31)
+#define DANUBE_BIU_WDT_CR_DSEN                         (1 << 30)
+#define DANUBE_BIU_WDT_CR_LPEN                         (1 << 29)
+
+#define DANUBE_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
+#define DANUBE_BIU_WDT_CR_PWL_GET(value)       (((value) >> 26) & ((1 << 2) - 1))
+#define DANUBE_BIU_WDT_CR_PWL_SET(value)       ((((1 << 2) - 1) & (value)) << 26)
+#define DANUBE_BIU_WDT_CR_PW_SET(value)                (((( 1 << 8) - 1) & (value)) << 16)
+#define DANUBE_BIU_WDT_CR_CLKDIV_SET(value)    (((( 1 << 2) - 1) & (value)) << 24)
+#define DANUBE_BIU_WDT_CR_RELOAD_SET(value)    (((( 1 << 16) - 1) & (value)) << 0)
+
+
+/*------------ LED */
+
+#define DANUBE_LED_BASE_ADDR   (KSEG1 + 0x1E100BB0)
+#define DANUBE_LED_CON0                        ((u32*)(DANUBE_LED_BASE_ADDR + 0x0000))
+#define DANUBE_LED_CON1                        ((u32*)(DANUBE_LED_BASE_ADDR + 0x0004))
+#define DANUBE_LED_CPU0                        ((u32*)(DANUBE_LED_BASE_ADDR + 0x0008))
+#define DANUBE_LED_CPU1                        ((u32*)(DANUBE_LED_BASE_ADDR + 0x000C))
+#define DANUBE_LED_AR                  ((u32*)(DANUBE_LED_BASE_ADDR + 0x0010))
+
+#define LED_CON0_SWU                   (1 << 31)
+#define LED_CON0_AD1                   (1 << 25)
+#define LED_CON0_AD0                   (1 << 24)
+
+#define DANUBE_LED_2HZ          (0)
+#define DANUBE_LED_4HZ          (1 << 23)
+#define DANUBE_LED_8HZ          (2 << 23)
+#define DANUBE_LED_10HZ         (3 << 23)
+#define DANUBE_LED_MASK         (0xf << 23)
+
+#define DANUBE_LED_UPD_SRC_FPI  (1 << 31)
+#define DANUBE_LED_UPD_MASK     (3 << 30)
+#define DANUBE_LED_ADSL_SRC            (3 << 24)
+
+#define DANUBE_LED_GROUP0              (1 << 0)
+#define DANUBE_LED_GROUP1              (1 << 1)
+#define DANUBE_LED_GROUP2              (1 << 2)
+
+#define DANUBE_LED_RISING              0
+#define DANUBE_LED_FALLING             (1 << 26)
+#define DANUBE_LED_EDGE_MASK   (1 << 26)
+
+
+/*------------ GPIO */
+
+#define DANUBE_GPIO_BASE_ADDR  (0xBE100B00)
+
+#define DANUBE_GPIO_P0_OUT             ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0010))
+#define DANUBE_GPIO_P1_OUT             ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0040))
+#define DANUBE_GPIO_P0_IN              ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0014))
+#define DANUBE_GPIO_P1_IN              ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0044))
+#define DANUBE_GPIO_P0_DIR             ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0018))
+#define DANUBE_GPIO_P1_DIR             ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0048))
+#define DANUBE_GPIO_P0_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x001C))
+#define DANUBE_GPIO_P1_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x004C))
+#define DANUBE_GPIO_P0_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0020))
+#define DANUBE_GPIO_P1_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0050))
+#define DANUBE_GPIO_P0_OD              ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0024))
+#define DANUBE_GPIO_P1_OD              ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0054))
+#define DANUBE_GPIO_P0_STOFF   ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0028))
+#define DANUBE_GPIO_P1_STOFF   ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0058))
+#define DANUBE_GPIO_P0_PUDSEL  ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x002C))
+#define DANUBE_GPIO_P1_PUDSEL  ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x005C))
+#define DANUBE_GPIO_P0_PUDEN   ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0030))
+#define DANUBE_GPIO_P1_PUDEN   ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0060))
+
+
+/*------------ SSC */
+
+#define DANUBE_SSC1_BASE_ADDR  (KSEG1 + 0x1e100800)
+
+
+
+
+
+
+#endif
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_dma.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_dma.h
new file mode 100644 (file)
index 0000000..219fd49
--- /dev/null
@@ -0,0 +1,202 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2005 infineon
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+#ifndef _DANUBE_DMA_H__
+#define _DANUBE_DMA_H__
+
+#define RCV_INT                                                        1
+#define TX_BUF_FULL_INT                                        2
+#define TRANSMIT_CPT_INT                               4
+#define DANUBE_DMA_CH_ON                               1
+#define DANUBE_DMA_CH_OFF                              0
+#define DANUBE_DMA_CH_DEFAULT_WEIGHT   100
+
+enum attr_t{
+       TX = 0,
+       RX = 1,
+       RESERVED = 2,
+       DEFAULT = 3,
+};
+
+#define DMA_OWN                                                        1
+#define CPU_OWN                                                        0
+#define DMA_MAJOR                                              250
+
+#define DMA_DESC_OWN_CPU                               0x0
+#define DMA_DESC_OWN_DMA                               0x80000000
+#define DMA_DESC_CPT_SET                               0x40000000
+#define DMA_DESC_SOP_SET                               0x20000000
+#define DMA_DESC_EOP_SET                               0x10000000
+
+#define MISCFG_MASK                                            0x40
+#define RDERR_MASK                                             0x20
+#define CHOFF_MASK                                             0x10
+#define DESCPT_MASK                                            0x8
+#define DUR_MASK                                               0x4
+#define EOP_MASK                                               0x2
+
+#define DMA_DROP_MASK                                  (1<<31)
+
+#define DANUBE_DMA_RX                                  -1
+#define DANUBE_DMA_TX                                  1
+
+typedef struct dma_chan_map {
+       char dev_name[15];
+       enum attr_t dir;
+       int pri;
+       int irq;
+       int rel_chan_no;
+} _dma_chan_map;
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+typedef struct rx_desc{
+       u32 data_length:16;
+       volatile u32 reserved:7;
+       volatile u32 byte_offset:2;
+       volatile u32 Burst_length_offset:3;
+       volatile u32 EoP:1;
+       volatile u32 Res:1;
+       volatile u32 C:1;
+       volatile u32 OWN:1;
+       volatile u32 Data_Pointer;
+       /*fix me:should be 28 bits here, 32 bits just for host simulatiuon purpose*/
+}_rx_desc;
+
+typedef struct tx_desc{
+       volatile u32 data_length:16;
+       volatile u32 reserved1:7;
+       volatile u32 byte_offset:5;
+       volatile u32 EoP:1;
+       volatile u32 SoP:1;
+       volatile u32 C:1;
+       volatile u32 OWN:1;
+       volatile u32 Data_Pointer;//fix me:should be 28 bits here
+}_tx_desc;
+#else //BIG
+typedef struct rx_desc{
+       union
+       {
+               struct
+               {
+                       volatile u32 OWN:1;
+                       volatile u32 C:1;
+                       volatile u32 SoP:1;
+                       volatile u32 EoP:1;
+                       volatile u32 Burst_length_offset:3;
+                       volatile u32 byte_offset:2;
+                       volatile u32 reserve:7;
+                       volatile u32 data_length:16;
+               }field;
+               volatile u32 word;
+       }status;
+       volatile u32 Data_Pointer;
+}_rx_desc;
+
+typedef struct tx_desc{
+       union
+       {
+               struct
+               {
+                       volatile u32 OWN:1;
+                       volatile u32 C:1;
+                       volatile u32 SoP:1;
+                       volatile u32 EoP:1;
+                       volatile u32 byte_offset:5;
+                       volatile u32 reserved:7;
+                       volatile u32 data_length:16;
+               }field;
+               volatile u32 word;
+       }status;
+       volatile u32 Data_Pointer;
+}_tx_desc;
+#endif //ENDIAN
+
+typedef struct dma_channel_info{
+   /*relative channel number*/
+   int rel_chan_no;
+   /*class for this channel for QoS*/
+   int pri;
+   /*specify byte_offset*/
+   int byte_offset;
+   /*direction*/
+   int dir;
+   /*irq number*/
+   int irq;
+   /*descriptor parameter*/
+   int desc_base;
+   int desc_len;
+   int curr_desc;
+   int prev_desc;/*only used if it is a tx channel*/
+   /*weight setting for WFQ algorithm*/
+   int weight;
+   int default_weight;
+   int packet_size;
+   int burst_len;
+   /*on or off of this channel*/
+   int control;
+   /**optional information for the upper layer devices*/
+#if defined(CONFIG_DANUBE_ETHERNET_D2) || defined(CONFIG_DANUBE_PPA)
+   void* opt[64];
+#else
+   void* opt[25];
+#endif
+   /*Pointer to the peripheral device who is using this channel*/
+   void* dma_dev;
+   /*channel operations*/
+   void (*open)(struct dma_channel_info* pCh);
+   void (*close)(struct dma_channel_info* pCh);
+   void (*reset)(struct dma_channel_info* pCh);
+   void (*enable_irq)(struct dma_channel_info* pCh);
+   void (*disable_irq)(struct dma_channel_info* pCh);
+}_dma_channel_info;
+
+typedef struct dma_device_info{
+    /*device name of this peripheral*/
+    char device_name[15];
+    int reserved;
+    int tx_burst_len;
+    int rx_burst_len;
+    int default_weight;
+    int  current_tx_chan;
+       int  current_rx_chan;
+    int  num_tx_chan;
+    int  num_rx_chan;
+    int  max_rx_chan_num;
+    int  max_tx_chan_num;
+    _dma_channel_info* tx_chan[20];
+    _dma_channel_info* rx_chan[20];
+    /*functions, optional*/
+    u8* (*buffer_alloc)(int len,int* offset, void** opt);
+    void (*buffer_free)(u8* dataptr, void* opt);
+    int (*intr_handler)(struct dma_device_info* info, int status);
+    void * priv;               /* used by peripheral driver only */
+}_dma_device_info;
+
+_dma_device_info* dma_device_reserve(char* dev_name);
+
+void dma_device_release(_dma_device_info* dev);
+
+void dma_device_register(_dma_device_info* info);
+
+void dma_device_unregister(_dma_device_info* info);
+
+int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt);
+
+int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt);
+#endif
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_gpio.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_gpio.h
new file mode 100644 (file)
index 0000000..2ea8d9c
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+#ifndef _DANUBE_GPIO_H__
+#define _DANUBE_GPIO_H__
+
+extern int danube_port_reserve_pin (unsigned int port, unsigned int pin);
+extern int danube_port_free_pin (unsigned int port, unsigned int pin);
+extern int danube_port_set_open_drain (unsigned int port, unsigned int pin);
+extern int danube_port_clear_open_drain (unsigned int port, unsigned int pin);
+extern int danube_port_set_pudsel (unsigned int port, unsigned int pin);
+extern int danube_port_clear_pudsel (unsigned int port, unsigned int pin);
+extern int danube_port_set_puden (unsigned int port, unsigned int pin);
+extern int danube_port_clear_puden (unsigned int port, unsigned int pin);
+extern int danube_port_set_stoff (unsigned int port, unsigned int pin);
+extern int danube_port_clear_stoff (unsigned int port, unsigned int pin);
+extern int danube_port_set_dir_out (unsigned int port, unsigned int pin);
+extern int danube_port_set_dir_in (unsigned int port, unsigned int pin);
+extern int danube_port_set_output (unsigned int port, unsigned int pin);
+extern int danube_port_clear_output (unsigned int port, unsigned int pin);
+extern int danube_port_get_input (unsigned int port, unsigned int pin);
+extern int danube_port_set_altsel0 (unsigned int port, unsigned int pin);
+extern int danube_port_clear_altsel0 (unsigned int port, unsigned int pin);
+extern int danube_port_set_altsel1 (unsigned int port, unsigned int pin);
+extern int danube_port_clear_altsel1 (unsigned int port, unsigned int pin);
+
+#endif
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_ioctl.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_ioctl.h
new file mode 100644 (file)
index 0000000..6d14f5d
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+#ifndef _DANUBE_IOCTL_H__
+#define _DANUBE_IOCTL_H__
+
+/*------------ LED */
+
+struct danube_port_ioctl_parm
+{
+       int port;
+       int pin;
+       int value;
+};
+
+#define DANUBE_PORT_IOC_MAGIC          0xbf
+#define DANUBE_PORT_IOCOD                      _IOW(DANUBE_PORT_IOC_MAGIC,0,struct danube_port_ioctl_parm)
+#define DANUBE_PORT_IOCPUDSEL          _IOW(DANUBE_PORT_IOC_MAGIC,1,struct danube_port_ioctl_parm)
+#define DANUBE_PORT_IOCPUDEN           _IOW(DANUBE_PORT_IOC_MAGIC,2,struct danube_port_ioctl_parm)
+#define DANUBE_PORT_IOCSTOFF           _IOW(DANUBE_PORT_IOC_MAGIC,3,struct danube_port_ioctl_parm)
+#define DANUBE_PORT_IOCDIR                     _IOW(DANUBE_PORT_IOC_MAGIC,4,struct danube_port_ioctl_parm)
+#define DANUBE_PORT_IOCOUTPUT          _IOW(DANUBE_PORT_IOC_MAGIC,5,struct danube_port_ioctl_parm)
+#define DANUBE_PORT_IOCINPUT           _IOWR(DANUBE_PORT_IOC_MAGIC,6,struct danube_port_ioctl_parm)
+#define DANUBE_PORT_IOCALTSEL0         _IOW(DANUBE_PORT_IOC_MAGIC,7,struct danube_port_ioctl_parm)
+#define DANUBE_PORT_IOCALTSEL1         _IOW(DANUBE_PORT_IOC_MAGIC,8,struct danube_port_ioctl_parm)
+
+#endif
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h
new file mode 100644 (file)
index 0000000..4579683
--- /dev/null
@@ -0,0 +1,66 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2005 infineon
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+#ifndef _DANUBE_IRQ__
+#define _DANUBE_IRQ__
+
+#define INT_NUM_IRQ0                   8
+#define INT_NUM_IM0_IRL0               (INT_NUM_IRQ0 + 0)
+#define INT_NUM_IM1_IRL0               (INT_NUM_IRQ0 + 32)
+#define INT_NUM_IM2_IRL0               (INT_NUM_IRQ0 + 64)
+#define INT_NUM_IM3_IRL0               (INT_NUM_IRQ0 + 96)
+#define INT_NUM_IM4_IRL0               (INT_NUM_IRQ0 + 128)
+#define INT_NUM_IM_OFFSET              (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
+
+#define DANUBEASC1_TIR                 (INT_NUM_IM3_IRL0 + 7)
+#define DANUBEASC1_RIR                 (INT_NUM_IM3_IRL0 + 9)
+#define DANUBEASC1_EIR                 (INT_NUM_IM3_IRL0 + 10)
+
+#define DANUBE_SSC_TIR                 (INT_NUM_IM0_IRL0 + 15)
+#define DANUBE_SSC_RIR                 (INT_NUM_IM0_IRL0 + 14)
+#define DANUBE_SSC_EIR                 (INT_NUM_IM0_IRL0 + 16)
+
+#define DANUBE_TIMER6_INT              (INT_NUM_IM1_IRL0 + 23)
+
+#define MIPS_CPU_TIMER_IRQ             7
+
+#define DANUBE_DMA_CH0_INT             (INT_NUM_IM2_IRL0)
+#define DANUBE_DMA_CH1_INT             (INT_NUM_IM2_IRL0 + 1)
+#define DANUBE_DMA_CH2_INT             (INT_NUM_IM2_IRL0 + 2)
+#define DANUBE_DMA_CH3_INT             (INT_NUM_IM2_IRL0 + 3)
+#define DANUBE_DMA_CH4_INT             (INT_NUM_IM2_IRL0 + 4)
+#define DANUBE_DMA_CH5_INT             (INT_NUM_IM2_IRL0 + 5)
+#define DANUBE_DMA_CH6_INT             (INT_NUM_IM2_IRL0 + 6)
+#define DANUBE_DMA_CH7_INT             (INT_NUM_IM2_IRL0 + 7)
+#define DANUBE_DMA_CH8_INT             (INT_NUM_IM2_IRL0 + 8)
+#define DANUBE_DMA_CH9_INT             (INT_NUM_IM2_IRL0 + 9)
+#define DANUBE_DMA_CH10_INT            (INT_NUM_IM2_IRL0 + 10)
+#define DANUBE_DMA_CH11_INT            (INT_NUM_IM2_IRL0 + 11)
+#define DANUBE_DMA_CH12_INT            (INT_NUM_IM2_IRL0 + 25)
+#define DANUBE_DMA_CH13_INT            (INT_NUM_IM2_IRL0 + 26)
+#define DANUBE_DMA_CH14_INT            (INT_NUM_IM2_IRL0 + 27)
+#define DANUBE_DMA_CH15_INT            (INT_NUM_IM2_IRL0 + 28)
+#define DANUBE_DMA_CH16_INT            (INT_NUM_IM2_IRL0 + 29)
+#define DANUBE_DMA_CH17_INT            (INT_NUM_IM2_IRL0 + 30)
+#define DANUBE_DMA_CH18_INT            (INT_NUM_IM2_IRL0 + 16)
+#define DANUBE_DMA_CH19_INT            (INT_NUM_IM2_IRL0 + 21)
+
+extern void mask_and_ack_danube_irq (unsigned int irq_nr);
+
+#endif
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_mii0.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_mii0.h
new file mode 100644 (file)
index 0000000..6f96ef6
--- /dev/null
@@ -0,0 +1,254 @@
+#ifndef DANUBE_SW_H
+#define DANUBE_SW_H
+
+
+
+/******************************************************************************
+**
+** FILE NAME    : danube_sw.h
+** PROJECT      : Danube
+** MODULES             : ETH Interface (MII0)
+**
+** DATE         : 11 AUG 2005
+** AUTHOR       : Wu Qi Ming
+** DESCRIPTION  : ETH Interface (MII0) Driver Header File
+** COPYRIGHT    :      Copyright (c) 2006
+**                     Infineon Technologies AG
+**                     Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+**    This program is free software; you can redistribute it and/or modify
+**    it under the terms of the GNU General Public License as published by
+**    the Free Software Foundation; either version 2 of the License, or
+**    (at your option) any later version.
+**
+** HISTORY
+** $Date        $Author         $Comment
+** 11 AUG 2005  Wu Qi Ming      Initiate Version
+** 23 OCT 2006  Xu Liang        Add GPL header.
+*******************************************************************************/
+
+
+#define SET_ETH_SPEED_AUTO   SIOCDEVPRIVATE
+#define SET_ETH_SPEED_10     SIOCDEVPRIVATE+1
+#define SET_ETH_SPEED_100    SIOCDEVPRIVATE+2
+#define SET_ETH_DUPLEX_AUTO  SIOCDEVPRIVATE+3
+#define SET_ETH_DUPLEX_HALF  SIOCDEVPRIVATE+4
+#define SET_ETH_DUPLEX_FULL  SIOCDEVPRIVATE+5
+#define SET_ETH_REG          SIOCDEVPRIVATE+6
+#define VLAN_TOOLS           SIOCDEVPRIVATE+7
+#define MAC_TABLE_TOOLS      SIOCDEVPRIVATE+8
+#define SET_VLAN_COS         SIOCDEVPRIVATE+9
+#define SET_DSCP_COS         SIOCDEVPRIVATE+10
+#define ENABLE_VLAN_CLASSIFICATION    SIOCDEVPRIVATE+11
+#define DISABLE_VLAN_CLASSIFICATION   SIOCDEVPRIVATE+12
+#define VLAN_CLASS_FIRST              SIOCDEVPRIVATE+13
+#define VLAN_CLASS_SECOND             SIOCDEVPRIVATE+14
+#define ENABLE_DSCP_CLASSIFICATION    SIOCDEVPRIVATE+15
+#define DISABLE_DSCP_CLASSIFICATION   SIOCDEVPRIVATE+16
+#define PASS_UNICAST_PACKETS          SIOCDEVPRIVATE+17
+#define FILTER_UNICAST_PACKETS        SIOCDEVPRIVATE+18
+#define KEEP_BROADCAST_PACKETS        SIOCDEVPRIVATE+19
+#define DROP_BROADCAST_PACKETS        SIOCDEVPRIVATE+20
+#define KEEP_MULTICAST_PACKETS        SIOCDEVPRIVATE+21
+#define DROP_MULTICAST_PACKETS        SIOCDEVPRIVATE+22
+
+
+/*===mac table commands==*/
+#define RESET_MAC_TABLE     0
+#define READ_MAC_ENTRY    1
+#define WRITE_MAC_ENTRY   2
+#define ADD_MAC_ENTRY     3
+
+/*====vlan commands===*/
+
+#define CHANGE_VLAN_CTRL     0
+#define READ_VLAN_ENTRY      1
+#define UPDATE_VLAN_ENTRY    2
+#define CLEAR_VLAN_ENTRY     3
+#define RESET_VLAN_TABLE     4
+#define ADD_VLAN_ENTRY       5
+
+/*
+** MDIO constants.
+*/
+
+#define MDIO_BASE_STATUS_REG                0x1
+#define MDIO_BASE_CONTROL_REG               0x0
+#define MDIO_PHY_ID_HIGH_REG                0x2
+#define MDIO_PHY_ID_LOW_REG                 0x3
+#define MDIO_BC_NEGOTIATE                0x0200
+#define MDIO_BC_FULL_DUPLEX_MASK         0x0100
+#define MDIO_BC_AUTO_NEG_MASK            0x1000
+#define MDIO_BC_SPEED_SELECT_MASK        0x2000
+#define MDIO_STATUS_100_FD               0x4000
+#define MDIO_STATUS_100_HD               0x2000
+#define MDIO_STATUS_10_FD                0x1000
+#define MDIO_STATUS_10_HD                0x0800
+#define MDIO_STATUS_SPEED_DUPLEX_MASK   0x7800
+#define MDIO_ADVERTISMENT_REG               0x4
+#define MDIO_ADVERT_100_FD                0x100
+#define MDIO_ADVERT_100_HD                0x080
+#define MDIO_ADVERT_10_FD                 0x040
+#define MDIO_ADVERT_10_HD                 0x020
+#define MDIO_LINK_UP_MASK                   0x4
+#define MDIO_START                          0x1
+#define MDIO_READ                           0x2
+#define MDIO_WRITE                          0x1
+#define MDIO_PREAMBLE              0xfffffffful
+
+#define PHY_RESET                        0x8000
+#define AUTO_NEGOTIATION_ENABLE          0X1000
+#define AUTO_NEGOTIATION_COMPLETE          0x20
+#define RESTART_AUTO_NEGOTIATION          0X200
+
+
+/*ETOP_MDIO_CFG MASKS*/
+#define SMRST_MASK 0X2000
+#define PHYA1_MASK 0X1F00
+#define PHYA0_MASK 0XF8
+#define UMM1_MASK  0X4
+#define UMM0_MASK  0X2
+
+/*ETOP_MDIO_ACCESS MASKS*/
+#define MDIO_RA_MASK    0X80000000
+#define MDIO_RW_MASK    0X40000000
+
+
+/*ENET_MAC_CFG MASKS*/
+#define BP_MASK     1<<12
+#define CGEN_MASK   1<<11
+#define IFG_MASK    0x3F<<5
+#define IPAUS_MASK  1<<4
+#define EPAUS_MASK  1<<3
+#define DUPLEX_MASK 1<<2
+#define SPEED_MASK  0x2
+#define LINK_MASK   1
+
+/*ENETS_CoS_CFG MASKS*/
+#define VLAN_MASK    2
+#define DSCP_MASK    1
+
+/*ENET_CFG MASKS*/
+#define VL2_MASK     1<<29
+#define FTUC_MASK    1<<25
+#define DPBC_MASK    1<<24
+#define DPMC_MASK    1<<23
+
+#define PHY0_ADDR    0
+#define PHY1_ADDR    1
+#define P1M          0
+
+#define DANUBE_SW_REG32(reg_num) *((volatile u32*)(reg_num))
+
+#define OK 0;
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+typedef struct mac_table_entry{
+   u64 mac_address:48;
+   u64 p0:1;
+   u64 p1:1;
+   u64 p2:1;
+   u64 cr:1;
+   u64 ma_st:3;
+   u64 res:9;
+}_mac_table_entry;
+
+typedef struct IFX_Switch_VLanTableEntry{
+    u32 vlan_id:12;
+    u32 mp0:1;
+    u32 mp1:1;
+    u32 mp2:1;
+    u32 v:1;
+    u32 res:16;
+}_IFX_Switch_VLanTableEntry;
+
+typedef struct mac_table_req{
+    int cmd;
+    int index;
+    u32 data;
+    u64 entry_value;
+}_mac_table_req;
+
+#else //not CONFIG_CPU_LITTLE_ENDIAN
+typedef struct mac_table_entry{
+   u64 mac_address:48;
+   u64 p0:1;
+   u64 p1:1;
+   u64 p2:1;
+   u64 cr:1;
+   u64 ma_st:3;
+   u64 res:9;
+}_mac_table_entry;
+
+typedef struct IFX_Switch_VLanTableEntry{
+    u32 vlan_id:12;
+    u32 mp0:1;
+    u32 mp1:1;
+    u32 mp2:1;
+    u32 v:1;
+    u32 res:16;
+}_IFX_Switch_VLanTableEntry;
+
+
+typedef struct mac_table_req{
+    int cmd;
+    int index;
+    u32 data;
+    u64 entry_value;
+}_mac_table_req;
+
+#endif //CONFIG_CPU_LITTLE_ENDIAN
+
+typedef struct vlan_cos_req{
+    int pri;
+    int cos_value;
+}_vlan_cos_req;
+
+typedef struct dscp_cos_req{
+    int dscp;
+    int cos_value;
+}_dscp_cos_req;
+
+
+typedef struct vlan_req{
+    int cmd;
+    int index;
+    u32 data;
+    u32 entry_value;
+}_vlan_req;
+
+typedef struct data_req{
+    int index;
+    u32 value;
+}_data_req;
+
+enum duplex
+{
+   half,
+   full,
+   autoneg
+};
+
+struct switch_priv {
+    struct net_device_stats stats;
+    int rx_packetlen;
+    u8 *rx_packetdata;
+    int rx_status;
+    int tx_packetlen;
+#ifdef CONFIG_NET_HW_FLOWCONTROL
+    int fc_bit;
+#endif //CONFIG_NET_HW_FLOWCONTROL
+    u8 *tx_packetdata;
+    int tx_status;
+    struct dma_device_info *dma_device;
+    struct sk_buff *skb;
+    spinlock_t lock;
+    int mdio_phy_addr;
+    int current_speed;
+    int current_speed_selection;
+    int rx_queue_len;
+    int full_duplex;
+    enum duplex current_duplex;
+};
+
+#endif //DANUBE_SW_H
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_orig.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_orig.h
new file mode 100644 (file)
index 0000000..4197933
--- /dev/null
@@ -0,0 +1,2021 @@
+#ifndef DANUBE_H
+#define DANUBE_H
+/******************************************************************************
+       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
+
+                               No Warranty
+   Because the program is licensed free of charge, there is no warranty for 
+   the program, to the extent permitted by applicable law.  Except when     
+   otherwise stated in writing the copyright holders and/or other parties   
+   provide the program "as is" without warranty of any kind, either         
+   expressed or implied, including, but not limited to, the implied         
+   warranties of merchantability and fitness for a particular purpose. The  
+   entire risk as to the quality and performance of the program is with     
+   you.  should the program prove defective, you assume the cost of all     
+   necessary servicing, repair or correction.                               
+                                                                            
+   In no event unless required by applicable law or agreed to in writing    
+   will any copyright holder, or any other party who may modify and/or      
+   redistribute the program as permitted above, be liable to you for        
+   damages, including any general, special, incidental or consequential     
+   damages arising out of the use or inability to use the program           
+   (including but not limited to loss of data or data being rendered        
+   inaccurate or losses sustained by you or third parties or a failure of   
+   the program to operate with any other programs), even if such holder or  
+   other party has been advised of the possibility of such damages. 
+******************************************************************************/
+
+/***********************************************************************/
+/*  Module      :  WDT register address and bits                       */
+/***********************************************************************/
+
+#define BOARD_SYSTEM_TYPE       "DANUBE"
+
+#define DANUBE_BIU_WDT                           (KSEG1+0x1F880000)
+
+/***Watchdog Timer Control Register ***/
+#define DANUBE_BIU_WDT_CR                   ((volatile u32*)(DANUBE_BIU_WDT + 0x03F0))
+#define DANUBE_BIU_WDT_CR_GEN               (1 << 31)
+#define DANUBE_BIU_WDT_CR_DSEN              (1 << 30)
+#define DANUBE_BIU_WDT_CR_LPEN              (1 << 29)
+#define DANUBE_BIU_WDT_CR_PWL_GET(value)    (((value) >> 26) & ((1 << 2) - 1))
+#define DANUBE_BIU_WDT_CR_PWL_SET(value)    (((( 1 << 2) - 1) & (value)) << 26)
+#define DANUBE_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
+#define DANUBE_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24)
+#define DANUBE_BIU_WDT_CR_PW_GET(value)     (((value) >> 16) & ((1 << 8) - 1))
+#define DANUBE_BIU_WDT_CR_PW_SET(value)     (((( 1 << 8) - 1) & (value)) << 16)
+#define DANUBE_BIU_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1))
+#define DANUBE_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
+
+/***Watchdog Timer Status Register***/
+#define DANUBE_BIU_WDT_SR                   ((volatile u32*)(DANUBE_BIU_WDT + 0x03F8))
+#define DANUBE_BIU_WDT_SR_EN                (1 << 31)
+#define DANUBE_BIU_WDT_SR_AE                (1 << 30)
+#define DANUBE_BIU_WDT_SR_PRW               (1 << 29)
+#define DANUBE_BIU_WDT_SR_EXP               (1 << 28)
+#define DANUBE_BIU_WDT_SR_PWD               (1 << 27)
+#define DANUBE_BIU_WDT_SR_DS                (1 << 26)
+#define DANUBE_BIU_WDT_SR_VALUE_GET(value)  (((value) >> 0) & ((1 << 16) - 1))
+#define DANUBE_BIU_WDT_SR_VALUE_SET(value)  (((( 1 << 16) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/*  Module      :  PMU register address and bits                       */
+/***********************************************************************/
+
+#define DANUBE_PMU                             (KSEG1+0x1F102000)
+
+/* PMU Power down Control Register */
+#define DANUBE_PMU_PWDCR                        ((volatile u32*)(DANUBE_PMU+0x001C))
+#define DANUBE_PMU_PWDCR_GPT                                   (1 << 12)
+#define DANUBE_PMU_PWDCR_FPI                                   (1 << 14)
+
+
+/* PMU Status Register */
+#define DANUBE_PMU_SR                           ((volatile u32*)(DANUBE_PMU+0x0020))
+
+#define DANUBE_PMU_DMA_SHIFT                    5
+#define DANUBE_PMU_PPE_SHIFT                    13
+#define DANUBE_PMU_SDIO_SHIFT                   16
+#define DANUBE_PMU_ETOP_SHIFT                   22
+#define DANUBE_PMU_ENET0_SHIFT                  24
+#define DANUBE_PMU_ENET1_SHIFT                  25
+
+/***********************************************************************/
+/*  Module      :  RCU register address and bits                       */
+/***********************************************************************/
+#define DANUBE_RCU_BASE_ADDR           (0xBF203000)
+
+#define DANUBE_RCU_REQ                         (0x0010 + DANUBE_RCU_BASE_ADDR) /* will remove this, pls use DANUBE_RCU_RST_REQ */
+
+#define DANUBE_RCU_RST_REQ              ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x0010))
+#define DANUBE_RCU_RST_STAT             ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x0014))
+#define DANUBE_RST_ALL                  (0x40000000)
+
+/***Reset Request Register***/
+#define DANUBE_RCU_RST_REQ_CPU0                 (1 << 31)
+#define DANUBE_RCU_RST_REQ_CPU1                 (1 << 3)
+#define DANUBE_RCU_RST_REQ_CPUSUB               (1 << 29)
+#define DANUBE_RCU_RST_REQ_HRST                 (1 << 28)
+#define DANUBE_RCU_RST_REQ_WDT0                 (1 << 27)
+#define DANUBE_RCU_RST_REQ_WDT1                 (1 << 26)
+#define DANUBE_RCU_RST_REQ_CFG_GET(value)       (((value) >> 23) & ((1 << 3) - 1))
+#define DANUBE_RCU_RST_REQ_CFG_SET(value)       (((( 1 << 3) - 1) & (value)) << 23)
+#define DANUBE_RCU_RST_REQ_SWTBOOT              (1 << 22)
+#define DANUBE_RCU_RST_REQ_DMA                  (1 << 21)
+#define DANUBE_RCU_RST_REQ_ARC_JTAG              (1 << 20)
+#define DANUBE_RCU_RST_REQ_ETHPHY0              (1 << 19)
+#define DANUBE_RCU_RST_REQ_CPU0_BR              (1 << 18)
+
+#define DANBUE_RCU_RST_REQ_AFE                 (1 << 11)
+#define DANBUE_RCU_RST_REQ_DFE                 (1 << 7)
+
+/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */
+#define DANUBE_RCU_RST_REQ_ALL                  DANUBE_RST_ALL
+
+#define DANUBE_RCU_STAT                        (0x0014 + DANUBE_RCU_BASE_ADDR)
+#define DANUBE_RCU_RST_SR              ( (volatile u32 *)(DANUBE_RCU_STAT))    /* will remove this, pls use DANUBE_RCU_RST_STAT */
+
+/*#define DANUBE_RCU_MON                  (0x0030 + DANUBE_RCU_BASE_ADDR) */
+
+/***********************************************************************/
+/*  Module      :  BCU  register address and bits                       */
+/***********************************************************************/
+
+#define DANUBE_BCU_BASE_ADDR                   (KSEG1+0x1E100000)
+
+/***BCU Control Register (0010H)***/
+#define DANUBE_BCU_CON                          ((volatile u32*)(0x0010 + DANUBE_BCU_BASE_ADDR))
+#define DANUBE_BCU_BCU_CON_SPC (value)                (((( 1 << 8) - 1) & (value)) << 24)
+#define DANUBE_BCU_BCU_CON_SPE                              (1 << 19)
+#define DANUBE_BCU_BCU_CON_PSE                              (1 << 18)
+#define DANUBE_BCU_BCU_CON_DBG                              (1 << 16)
+#define DANUBE_BCU_BCU_CON_TOUT (value)               (((( 1 << 16) - 1) & (value)) << 0)
+
+/***BCU Error Control Capture Register (0020H)***/
+#define DANUBE_BCU_ECON                         ((volatile u32*)(0x0020 + DANUBE_BCU_BASE_ADDR))
+#define DANUBE_BCU_BCU_ECON_TAG (value)                (((( 1 << 4) - 1) & (value)) << 24)
+#define DANUBE_BCU_BCU_ECON_RDN                              (1 << 23)
+#define DANUBE_BCU_BCU_ECON_WRN                              (1 << 22)
+#define DANUBE_BCU_BCU_ECON_SVM                              (1 << 21)
+#define DANUBE_BCU_BCU_ECON_ACK (value)                (((( 1 << 2) - 1) & (value)) << 19)
+#define DANUBE_BCU_BCU_ECON_ABT                              (1 << 18)
+#define DANUBE_BCU_BCU_ECON_RDY                              (1 << 17)
+#define DANUBE_BCU_BCU_ECON_TOUT                             (1 << 16)
+#define DANUBE_BCU_BCU_ECON_ERRCNT (value)             (((( 1 << 16) - 1) & (value)) << 0)
+#define DANUBE_BCU_BCU_ECON_OPC (value)                (((( 1 << 4) - 1) & (value)) << 28)
+
+/***BCU Error Address Capture Register (0024 H)***/
+#define DANUBE_BCU_EADD                        ((volatile u32*)(0x0024 + DANUBE_BCU_BASE_ADDR))
+
+/***BCU Error Data Capture Register (0028H)***/
+#define DANUBE_BCU_EDAT                        ((volatile u32*)(0x0028 + DANUBE_BCU_BASE_ADDR))
+#define DANUBE_BCU_IRNEN                       ((volatile u32*)(0x00F4 + DANUBE_BCU_BASE_ADDR))
+#define DANUBE_BCU_IRNICR                      ((volatile u32*)(0x00F8 + DANUBE_BCU_BASE_ADDR))
+#define DANUBE_BCU_IRNCR                       ((volatile u32*)(0x00FC + DANUBE_BCU_BASE_ADDR))
+
+/***********************************************************************/
+/*  Module      :  MBC register address and bits                       */
+/***********************************************************************/
+
+#define DANUBE_MBC                          (0xBF103000)
+/***********************************************************************/
+
+/***Mailbox CPU Configuration Register***/
+#define DANUBE_MBC_MBC_CFG                      ((volatile u32*)(DANUBE_MBC+ 0x0080))
+#define DANUBE_MBC_MBC_CFG_SWAP (value)               (((( 1 << 2) - 1) & (value)) << 6)
+#define DANUBE_MBC_MBC_CFG_RES                              (1 << 5)
+#define DANUBE_MBC_MBC_CFG_FWID (value)               (((( 1 << 4) - 1) & (value)) << 1)
+#define DANUBE_MBC_MBC_CFG_SIZE                            (1 << 0)
+
+/***Mailbox CPU Interrupt Status Register***/
+#define DANUBE_MBC_MBC_ISR                      ((volatile u32*)(DANUBE_MBC+ 0x0084))
+#define DANUBE_MBC_MBC_ISR_B3DA                            (1 << 31)
+#define DANUBE_MBC_MBC_ISR_B2DA                            (1 << 30)
+#define DANUBE_MBC_MBC_ISR_B1E                              (1 << 29)
+#define DANUBE_MBC_MBC_ISR_B0E                              (1 << 28)
+#define DANUBE_MBC_MBC_ISR_WDT                              (1 << 27)
+#define DANUBE_MBC_MBC_ISR_DS260 (value)             (((( 1 << 27) - 1) & (value)) << 0)
+
+/***Mailbox CPU Mask Register***/
+#define DANUBE_MBC_MBC_MSK                      ((volatile u32*)(DANUBE_MBC+ 0x0088))
+#define DANUBE_MBC_MBC_MSK_B3DA                            (1 << 31)
+#define DANUBE_MBC_MBC_MSK_B2DA                            (1 << 30)
+#define DANUBE_MBC_MBC_MSK_B1E                              (1 << 29)
+#define DANUBE_MBC_MBC_MSK_B0E                              (1 << 28)
+#define DANUBE_MBC_MBC_MSK_WDT                              (1 << 27)
+#define DANUBE_MBC_MBC_MSK_DS260 (value)             (((( 1 << 27) - 1) & (value)) << 0)
+
+/***Mailbox CPU Mask 01 Register***/
+#define DANUBE_MBC_MBC_MSK01                    ((volatile u32*)(DANUBE_MBC+ 0x008C))
+#define DANUBE_MBC_MBC_MSK01_B3DA                            (1 << 31)
+#define DANUBE_MBC_MBC_MSK01_B2DA                            (1 << 30)
+#define DANUBE_MBC_MBC_MSK01_B1E                              (1 << 29)
+#define DANUBE_MBC_MBC_MSK01_B0E                              (1 << 28)
+#define DANUBE_MBC_MBC_MSK01_WDT                              (1 << 27)
+#define DANUBE_MBC_MBC_MSK01_DS260 (value)             (((( 1 << 27) - 1) & (value)) << 0)
+
+/***Mailbox CPU Mask 10 Register***/
+#define DANUBE_MBC_MBC_MSK10                    ((volatile u32*)(DANUBE_MBC+ 0x0090))
+#define DANUBE_MBC_MBC_MSK10_B3DA                            (1 << 31)
+#define DANUBE_MBC_MBC_MSK10_B2DA                            (1 << 30)
+#define DANUBE_MBC_MBC_MSK10_B1E                              (1 << 29)
+#define DANUBE_MBC_MBC_MSK10_B0E                              (1 << 28)
+#define DANUBE_MBC_MBC_MSK10_WDT                              (1 << 27)
+#define DANUBE_MBC_MBC_MSK10_DS260 (value)             (((( 1 << 27) - 1) & (value)) << 0)
+
+/***Mailbox CPU Short Command Register***/
+#define DANUBE_MBC_MBC_CMD                      ((volatile u32*)(DANUBE_MBC+ 0x0094))
+#define DANUBE_MBC_MBC_CMD_CS270 (value)             (((( 1 << 28) - 1) & (value)) << 0)
+
+/***Mailbox CPU Input Data of Buffer 0***/
+#define DANUBE_MBC_MBC_ID0                      ((volatile u32*)(DANUBE_MBC+ 0x0000))
+#define DANUBE_MBC_MBC_ID0_INDATA
+
+/***Mailbox CPU Input Data of Buffer 1***/
+#define DANUBE_MBC_MBC_ID1                      ((volatile u32*)(DANUBE_MBC+ 0x0020))
+#define DANUBE_MBC_MBC_ID1_INDATA
+
+/***Mailbox CPU Output Data of Buffer 2***/
+#define DANUBE_MBC_MBC_OD2                      ((volatile u32*)(DANUBE_MBC+ 0x0040))
+#define DANUBE_MBC_MBC_OD2_OUTDATA
+
+/***Mailbox CPU Output Data of Buffer 3***/
+#define DANUBE_MBC_MBC_OD3                      ((volatile u32*)(DANUBE_MBC+ 0x0060))
+#define DANUBE_MBC_MBC_OD3_OUTDATA
+
+/***Mailbox CPU Control Register of Buffer 0***/
+#define DANUBE_MBC_MBC_CR0                      ((volatile u32*)(DANUBE_MBC+ 0x0004))
+#define DANUBE_MBC_MBC_CR0_RDYABTFLS (value)          (((( 1 << 3) - 1) & (value)) << 0)
+
+/***Mailbox CPU Control Register of Buffer 1***/
+#define DANUBE_MBC_MBC_CR1                      ((volatile u32*)(DANUBE_MBC+ 0x0024))
+#define DANUBE_MBC_MBC_CR1_RDYABTFLS (value)          (((( 1 << 3) - 1) & (value)) << 0)
+
+/***Mailbox CPU Control Register of Buffer 2***/
+#define DANUBE_MBC_MBC_CR2                      ((volatile u32*)(DANUBE_MBC+ 0x0044))
+#define DANUBE_MBC_MBC_CR2_RDYABTFLS (value)          (((( 1 << 3) - 1) & (value)) << 0)
+
+/***Mailbox CPU Control Register of Buffer 3***/
+#define DANUBE_MBC_MBC_CR3                      ((volatile u32*)(DANUBE_MBC+ 0x0064))
+#define DANUBE_MBC_MBC_CR3_RDYABTFLS (value)          (((( 1 << 3) - 1) & (value)) << 0)
+
+/***Mailbox CPU Free Space of Buffer 0***/
+#define DANUBE_MBC_MBC_FS0                      ((volatile u32*)(DANUBE_MBC+ 0x0008))
+#define DANUBE_MBC_MBC_FS0_FS
+
+/***Mailbox CPU Free Space of Buffer 1***/
+#define DANUBE_MBC_MBC_FS1                      ((volatile u32*)(DANUBE_MBC+ 0x0028))
+#define DANUBE_MBC_MBC_FS1_FS
+
+/***Mailbox CPU Free Space of Buffer 2***/
+#define DANUBE_MBC_MBC_FS2                      ((volatile u32*)(DANUBE_MBC+ 0x0048))
+#define DANUBE_MBC_MBC_FS2_FS
+
+/***Mailbox CPU Free Space of Buffer 3***/
+#define DANUBE_MBC_MBC_FS3                      ((volatile u32*)(DANUBE_MBC+ 0x0068))
+#define DANUBE_MBC_MBC_FS3_FS
+
+/***Mailbox CPU Data Available in Buffer 0***/
+#define DANUBE_MBC_MBC_DA0                      ((volatile u32*)(DANUBE_MBC+ 0x000C))
+#define DANUBE_MBC_MBC_DA0_DA
+
+/***Mailbox CPU Data Available in Buffer 1***/
+#define DANUBE_MBC_MBC_DA1                      ((volatile u32*)(DANUBE_MBC+ 0x002C))
+#define DANUBE_MBC_MBC_DA1_DA
+
+/***Mailbox CPU Data Available in Buffer 2***/
+#define DANUBE_MBC_MBC_DA2                      ((volatile u32*)(DANUBE_MBC+ 0x004C))
+#define DANUBE_MBC_MBC_DA2_DA
+
+/***Mailbox CPU Data Available in Buffer 3***/
+#define DANUBE_MBC_MBC_DA3                      ((volatile u32*)(DANUBE_MBC+ 0x006C))
+#define DANUBE_MBC_MBC_DA3_DA
+
+/***Mailbox CPU Input Absolute Pointer of Buffer 0***/
+#define DANUBE_MBC_MBC_IABS0                    ((volatile u32*)(DANUBE_MBC+ 0x0010))
+#define DANUBE_MBC_MBC_IABS0_IABS
+
+/***Mailbox CPU Input Absolute Pointer of Buffer 1***/
+#define DANUBE_MBC_MBC_IABS1                    ((volatile u32*)(DANUBE_MBC+ 0x0030))
+#define DANUBE_MBC_MBC_IABS1_IABS
+
+/***Mailbox CPU Input Absolute Pointer of Buffer 2***/
+#define DANUBE_MBC_MBC_IABS2                    ((volatile u32*)(DANUBE_MBC+ 0x0050))
+#define DANUBE_MBC_MBC_IABS2_IABS
+
+/***Mailbox CPU Input Absolute Pointer of Buffer 3***/
+#define DANUBE_MBC_MBC_IABS3                    ((volatile u32*)(DANUBE_MBC+ 0x0070))
+#define DANUBE_MBC_MBC_IABS3_IABS
+
+/***Mailbox CPU Input Temporary Pointer of Buffer 0***/
+#define DANUBE_MBC_MBC_ITMP0                    ((volatile u32*)(DANUBE_MBC+ 0x0014))
+#define DANUBE_MBC_MBC_ITMP0_ITMP
+
+/***Mailbox CPU Input Temporary Pointer of Buffer 1***/
+#define DANUBE_MBC_MBC_ITMP1                    ((volatile u32*)(DANUBE_MBC+ 0x0034))
+#define DANUBE_MBC_MBC_ITMP1_ITMP
+
+/***Mailbox CPU Input Temporary Pointer of Buffer 2***/
+#define DANUBE_MBC_MBC_ITMP2                    ((volatile u32*)(DANUBE_MBC+ 0x0054))
+#define DANUBE_MBC_MBC_ITMP2_ITMP
+
+/***Mailbox CPU Input Temporary Pointer of Buffer 3***/
+#define DANUBE_MBC_MBC_ITMP3                    ((volatile u32*)(DANUBE_MBC+ 0x0074))
+#define DANUBE_MBC_MBC_ITMP3_ITMP
+
+/***Mailbox CPU Output Absolute Pointer of Buffer 0***/
+#define DANUBE_MBC_MBC_OABS0                    ((volatile u32*)(DANUBE_MBC+ 0x0018))
+#define DANUBE_MBC_MBC_OABS0_OABS
+
+/***Mailbox CPU Output Absolute Pointer of Buffer 1***/
+#define DANUBE_MBC_MBC_OABS1                    ((volatile u32*)(DANUBE_MBC+ 0x0038))
+#define DANUBE_MBC_MBC_OABS1_OABS
+
+/***Mailbox CPU Output Absolute Pointer of Buffer 2***/
+#define DANUBE_MBC_MBC_OABS2                    ((volatile u32*)(DANUBE_MBC+ 0x0058))
+#define DANUBE_MBC_MBC_OABS2_OABS
+
+/***Mailbox CPU Output Absolute Pointer of Buffer 3***/
+#define DANUBE_MBC_MBC_OABS3                    ((volatile u32*)(DANUBE_MBC+ 0x0078))
+#define DANUBE_MBC_MBC_OABS3_OABS
+
+/***Mailbox CPU Output Temporary Pointer of Buffer 0***/
+#define DANUBE_MBC_MBC_OTMP0                    ((volatile u32*)(DANUBE_MBC+ 0x001C))
+#define DANUBE_MBC_MBC_OTMP0_OTMP
+
+/***Mailbox CPU Output Temporary Pointer of Buffer 1***/
+#define DANUBE_MBC_MBC_OTMP1                    ((volatile u32*)(DANUBE_MBC+ 0x003C))
+#define DANUBE_MBC_MBC_OTMP1_OTMP
+
+/***Mailbox CPU Output Temporary Pointer of Buffer 2***/
+#define DANUBE_MBC_MBC_OTMP2                    ((volatile u32*)(DANUBE_MBC+ 0x005C))
+#define DANUBE_MBC_MBC_OTMP2_OTMP
+
+/***Mailbox CPU Output Temporary Pointer of Buffer 3***/
+#define DANUBE_MBC_MBC_OTMP3                    ((volatile u32*)(DANUBE_MBC+ 0x007C))
+#define DANUBE_MBC_MBC_OTMP3_OTMP
+
+/***DSP Control Register***/
+#define DANUBE_MBC_DCTRL                        ((volatile u32*)(DANUBE_MBC+ 0x00A0))
+#define DANUBE_MBC_DCTRL_BA                              (1 << 0)
+#define DANUBE_MBC_DCTRL_BMOD (value)               (((( 1 << 3) - 1) & (value)) << 1)
+#define DANUBE_MBC_DCTRL_IDL                              (1 << 4)
+#define DANUBE_MBC_DCTRL_RES                              (1 << 15)
+
+/***DSP Status Register***/
+#define DANUBE_MBC_DSTA                         ((volatile u32*)(DANUBE_MBC+ 0x00A4))
+#define DANUBE_MBC_DSTA_IDLE                            (1 << 0)
+#define DANUBE_MBC_DSTA_PD                              (1 << 1)
+
+/***DSP Test 1 Register***/
+#define DANUBE_MBC_DTST1                        ((volatile u32*)(DANUBE_MBC+ 0x00A8))
+#define DANUBE_MBC_DTST1_ABORT                          (1 << 0)
+#define DANUBE_MBC_DTST1_HWF32                          (1 << 1)
+#define DANUBE_MBC_DTST1_HWF4M                          (1 << 2)
+#define DANUBE_MBC_DTST1_HWFOP                          (1 << 3)
+
+/***********************************************************************/
+/*  Module      :  MEI register address and bits                       */
+/***********************************************************************/
+#define MEI_SPACE_ACCESS       0xBE116000
+
+/***   Register address offsets, relative to MEI_SPACE_ADDRESS ***/
+#define MEI_DATA_XFR                           ((volatile u32*)(0x0000 + MEI_SPACE_ACCESS))
+#define        MEI_VERSION                             ((volatile u32*)(0x0004 + MEI_SPACE_ACCESS))
+#define        MEI_ARC_GP_STAT                         ((volatile u32*)(0x0008 + MEI_SPACE_ACCESS))
+#define MEI_DATA_XFR_STAT                      ((volatile u32*)(0x000C + MEI_SPACE_ACCESS))
+#define        MEI_XFR_ADDR                            ((volatile u32*)(0x0010 + MEI_SPACE_ACCESS))
+#define MEI_MAX_WAIT                           ((volatile u32*)(0x0014 + MEI_SPACE_ACCESS))
+#define        MEI_TO_ARC_INT                          ((volatile u32*)(0x0018 + MEI_SPACE_ACCESS))
+#define        ARC_TO_MEI_INT                          ((volatile u32*)(0x001C + MEI_SPACE_ACCESS))
+#define        ARC_TO_MEI_INT_MASK                     ((volatile u32*)(0x0020 + MEI_SPACE_ACCESS))
+#define        MEI_DEBUG_WAD                           ((volatile u32*)(0x0024 + MEI_SPACE_ACCESS))
+#define MEI_DEBUG_RAD                          ((volatile u32*)(0x0028 + MEI_SPACE_ACCESS))
+#define        MEI_DEBUG_DATA                          ((volatile u32*)(0x002C + MEI_SPACE_ACCESS))
+#define        MEI_DEBUG_DEC                           ((volatile u32*)(0x0030 + MEI_SPACE_ACCESS))
+#define MEI_CONFIG                             ((volatile u32*)(0x0034 + MEI_SPACE_ACCESS))
+#define        MEI_RST_CONTROL                         ((volatile u32*)(0x0038 + MEI_SPACE_ACCESS))
+#define        MEI_DBG_MASTER                          ((volatile u32*)(0x003C + MEI_SPACE_ACCESS))
+#define        MEI_CLK_CONTROL                         ((volatile u32*)(0x0040 + MEI_SPACE_ACCESS))
+#define        MEI_BIST_CONTROL                        ((volatile u32*)(0x0044 + MEI_SPACE_ACCESS))
+#define        MEI_BIST_STAT                           ((volatile u32*)(0x0048 + MEI_SPACE_ACCESS))
+#define MEI_XDATA_BASE_SH                      ((volatile u32*)(0x004c + MEI_SPACE_ACCESS))
+#define MEI_XDATA_BASE                         ((volatile u32*)(0x0050 + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR_BASE                      ((volatile u32*)(0x0054 + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR0                          ((volatile u32*)(0x0054 + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR1                          ((volatile u32*)(0x0058 + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR2                          ((volatile u32*)(0x005C + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR3                          ((volatile u32*)(0x0060 + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR4                          ((volatile u32*)(0x0064 + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR5                          ((volatile u32*)(0x0068 + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR6                          ((volatile u32*)(0x006C + MEI_SPACE_ACCESS)))
+#define MEI_XMEM_BAR7                          ((volatile u32*)(0x0070 + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR8                          ((volatile u32*)(0x0074 + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR9                          ((volatile u32*)(0x0078 + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR10                         ((volatile u32*)(0x007C + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR11                         ((volatile u32*)(0x0080 + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR12                         ((volatile u32*)(0x0084 + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR13                         ((volatile u32*)(0x0088 + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR14                         ((volatile u32*)(0x008C + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR15                         ((volatile u32*)(0x0090 + MEI_SPACE_ACCESS))
+#define MEI_XMEM_BAR16                         ((volatile u32*)(0x0094 + MEI_SPACE_ACCESS))
+
+/***********************************************************************/
+/*  Module      :  SSC1 register address and bits                      */
+/***********************************************************************/
+
+#define DANUBE_SSC1                            (KSEG1+0x1e100800)
+/***********************************************************************/
+/***SSC Clock Control Register***/
+#define DANUBE_SSC_CLC                         (0x0000)
+#define DANUBE_SSC_CLC_RMC(value)               (((( 1 << 8) - 1) & (value)) << 8)
+#define DANUBE_SSC_CLC_DISS                     (1 << 1)
+#define DANUBE_SSC_CLC_DISR                     (1 << 0)
+/***SSC Port Input Selection Register***/
+#define DANUBE_SSC_PISEL                        (0x0004)
+/***SSC Identification Register***/
+#define DANUBE_SSC_ID                           (0x0008)
+/***Control Register (Programming Mode)***/
+#define DANUBE_SSC_CON                                 (0x0010)
+#define DANUBE_SSC_CON_RUEN                            (1 << 12)
+#define DANUBE_SSC_CON_TUEN                              (1 << 11)
+#define DANUBE_SSC_CON_AEN                              (1 << 10)
+#define DANUBE_SSC_CON_REN                              (1 << 9)
+#define DANUBE_SSC_CON_TEN                              (1 << 8)
+#define DANUBE_SSC_CON_LB                              (1 << 7)
+#define DANUBE_SSC_CON_PO                              (1 << 6)
+#define DANUBE_SSC_CON_PH                              (1 << 5)
+#define DANUBE_SSC_CON_HB                              (1 << 4)
+#define DANUBE_SSC_CON_BM(value)                       (((( 1 << 5) - 1) & (value)) << 16)
+#define DANUBE_SSC_CON_RX_OFF                          (1 << 1)
+#define DANUBE_SSC_CON_TX_OFF                          (1 << 0)
+/***SCC Status Register***/
+#define DANUBE_SSC_STATE                  (0x0014)
+#define DANUBE_SSC_STATE_EN                              (1 << 0)
+#define DANUBE_SSC_STATE_MS                              (1 << 1)
+#define DANUBE_SSC_STATE_BSY                              (1 << 13)
+#define DANUBE_SSC_STATE_RUE                              (1 << 12)
+#define DANUBE_SSC_STATE_TUE                              (1 << 11)
+#define DANUBE_SSC_STATE_AE                              (1 << 10)
+#define DANUBE_SSC_STATE_RE                              (1 << 9)
+#define DANUBE_SSC_STATE_TE                              (1 << 8)
+#define DANUBE_SSC_STATE_BC(value)                (((( 1 << 5) - 1) & (value)) << 16)
+/***SSC Write Hardware Modified Control Register***/
+#define DANUBE_SSC_WHBSTATE                   ( 0x0018)
+#define DANUBE_SSC_WHBSTATE_SETBE                          (1 << 15)
+#define DANUBE_SSC_WHBSTATE_SETPE                          (1 << 14)
+#define DANUBE_SSC_WHBSTATE_SETRE                          (1 << 13)
+#define DANUBE_SSC_WHBSTATE_SETTE                          (1 << 12)
+#define DANUBE_SSC_WHBSTATE_CLRBE                          (1 << 11)
+#define DANUBE_SSC_WHBSTATE_CLRPE                          (1 << 10)
+#define DANUBE_SSC_WHBSTATE_CLRRE                          (1 << 9)
+#define DANUBE_SSC_WHBSTATE_CLRTE                          (1 << 8)
+/***SSC Transmitter Buffer Register***/
+#define DANUBE_SSC_TB                       (0x0020)
+#define DANUBE_SSC_TB_TB_VALUE(value)          (((( 1 << 16) - 1) & (value)) << 0)
+/***SSC Receiver Buffer Register***/
+#define DANUBE_SSC_RB                       (0x0024)
+#define DANUBE_SSC_RB_RB_VALUE(value)          (((( 1 << 16) - 1) & (value)) << 0)
+/***SSC Receive FIFO Control Register***/
+#define DANUBE_SSC_RXFCON                   (0x0030)
+#define DANUBE_SSC_RXFCON_RXFITL(value)             (((( 1 << 6) - 1) & (value)) << 8)
+#define DANUBE_SSC_RXFCON_RXTMEN                        (1 << 2)
+#define DANUBE_SSC_RXFCON_RXFLU                          (1 << 1)
+#define DANUBE_SSC_RXFCON_RXFEN                          (1 << 0)
+/***SSC Transmit FIFO Control Register***/
+#define DANUBE_SSC_TXFCON                   ( 0x0034)
+#define DANUBE_SSC_TXFCON_RXFITL(value)             (((( 1 << 6) - 1) & (value)) << 8)
+#define DANUBE_SSC_TXFCON_TXTMEN                        (1 << 2)
+#define DANUBE_SSC_TXFCON_TXFLU                          (1 << 1)
+#define DANUBE_SSC_TXFCON_TXFEN                          (1 << 0)
+/***SSC FIFO Status Register***/
+#define DANUBE_SSC_FSTAT                    (0x0038)
+#define DANUBE_SSC_FSTAT_TXFFL(value)              (((( 1 << 6) - 1) & (value)) << 8)
+#define DANUBE_SSC_FSTAT_RXFFL(value)              (((( 1 << 6) - 1) & (value)) << 0)
+/***SSC Baudrate Timer Reload Register***/
+#define DANUBE_SSC_BR                       (0x0040)
+#define DANUBE_SSC_BR_BR_VALUE(value)          (((( 1 << 16) - 1) & (value)) << 0)
+#define DANUBE_SSC_BRSTAT                       (0x0044)
+#define DANUBE_SSC_SFCON                        (0x0060)
+#define DANUBE_SSC_SFSTAT                       (0x0064)
+#define DANUBE_SSC_GPOCON                       (0x0070)
+#define DANUBE_SSC_GPOSTAT                      (0x0074)
+#define DANUBE_SSC_WHBGPOSTAT                   (0x0078)
+#define DANUBE_SSC_RXREQ                        (0x0080)
+#define DANUBE_SSC_RXCNT                        (0x0084)
+/*DMA Registers in Bus Clock Domain*/
+#define DANUBE_SSC_DMA_CON                      (0x00EC)
+/*interrupt Node Registers in Bus Clock Domain*/
+#define DANUBE_SSC_IRNEN                        (0x00F4)
+#define DANUBE_SSC_IRNCR                        (0x00F8)
+#define DANUBE_SSC_IRNICR                       (0x00FC)
+#define DANUBE_SSC_IRN_FIR                     0x8
+#define DANUBE_SSC_IRN_EIR                     0x4
+#define DANUBE_SSC_IRN_RIR                     0x2
+#define DANUBE_SSC_IRN_TIR                     0x1
+
+#define        DANUBE_SSC1_CLC                 ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CLC))
+#define        DANUBE_SSC1_ID                  ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_ID))
+#define        DANUBE_SSC1_CON                 ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CON))
+#define        DANUBE_SSC1_STATE                       ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_STATE))
+#define        DANUBE_SSC1_WHBSTATE                    ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBSTATE))
+#define        DANUBE_SSC1_TB                  ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TB))
+#define        DANUBE_SSC1_RB                  ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RB))
+#define        DANUBE_SSC1_FSTAT                       ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_FSTAT))
+#define        DANUBE_SSC1_PISEL                       ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_PISEL))
+#define        DANUBE_SSC1_RXFCON                      ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXFCON))
+#define        DANUBE_SSC1_TXFCON                      ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TXFCON))
+#define        DANUBE_SSC1_BR                  ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BR))
+#define        DANUBE_SSC1_BRSTAT                      ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BRSTAT))
+#define        DANUBE_SSC1_SFCON                       ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFCON))
+#define        DANUBE_SSC1_SFSTAT                      ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFSTAT))
+#define        DANUBE_SSC1_GPOCON                      ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOCON))
+#define        DANUBE_SSC1_GPOSTAT                     ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOSTAT))
+#define        DANUBE_SSC1_WHBGPOSTAT                  ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBGPOSTAT))
+#define        DANUBE_SSC1_RXREQ                       ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXREQ))
+#define        DANUBE_SSC1_RXCNT                       ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXCNT))
+#define        DANUBE_SSC1_DMA_CON                     ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_DMA_CON))
+#define        DANUBE_SSC1_IRNEN                       ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNEN))
+#define        DANUBE_SSC1_IRNICR                      ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNICR))
+#define        DANUBE_SSC1_IRNCR                       ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNCR))
+
+/***********************************************************************/
+/*  Module      :  GPIO register address and bits                       */
+/***********************************************************************/
+#define DANUBE_GPIO                     (0xBE100B00)
+/***Port 0 Data Output Register (0010H)***/
+#define DANUBE_GPIO_P0_OUT              ((volatile u32 *)(DANUBE_GPIO+ 0x0010))
+/***Port 1 Data Output Register (0040H)***/
+#define DANUBE_GPIO_P1_OUT              ((volatile u32 *)(DANUBE_GPIO+ 0x0040))
+/***Port 0 Data Input Register (0014H)***/
+#define DANUBE_GPIO_P0_IN               ((volatile u32 *)(DANUBE_GPIO+ 0x0014))
+/***Port 1 Data Input Register (0044H)***/
+#define DANUBE_GPIO_P1_IN               ((volatile u32 *)(DANUBE_GPIO+ 0x0044))
+/***Port 0 Direction Register (0018H)***/
+#define DANUBE_GPIO_P0_DIR              ((volatile u32 *)(DANUBE_GPIO+ 0x0018))
+/***Port 1 Direction Register (0048H)***/
+#define DANUBE_GPIO_P1_DIR              ((volatile u32 *)(DANUBE_GPIO+ 0x0048))
+/***Port 0 Alternate Function Select Register 0 (001C H) ***/
+#define DANUBE_GPIO_P0_ALTSEL0          ((volatile u32 *)(DANUBE_GPIO+ 0x001C))
+/***Port 1 Alternate Function Select Register 0 (004C H) ***/
+#define DANUBE_GPIO_P1_ALTSEL0          ((volatile u32 *)(DANUBE_GPIO+ 0x004C))
+/***Port 0 Alternate Function Select Register 1 (0020 H) ***/
+#define DANUBE_GPIO_P0_ALTSEL1          ((volatile u32 *)(DANUBE_GPIO+ 0x0020))
+/***Port 1 Alternate Function Select Register 0 (0050 H) ***/
+#define DANUBE_GPIO_P1_ALTSEL1          ((volatile u32 *)(DANUBE_GPIO+ 0x0050))
+/***Port 0 Open Drain Control Register (0024H)***/
+#define DANUBE_GPIO_P0_OD               ((volatile u32 *)(DANUBE_GPIO+ 0x0024))
+/***Port 1 Open Drain Control Register (0054H)***/
+#define DANUBE_GPIO_P1_OD               ((volatile u32 *)(DANUBE_GPIO+ 0x0054))
+/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/
+#define DANUBE_GPIO_P0_STOFF            ((volatile u32 *)(DANUBE_GPIO+ 0x0028))
+/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/
+#define DANUBE_GPIO_P1_STOFF            ((volatile u32 *)(DANUBE_GPIO+ 0x0058))
+/***Port 0 Pull Up/Pull Down Select Register (002C H)***/
+#define DANUBE_GPIO_P0_PUDSEL           ((volatile u32 *)(DANUBE_GPIO+ 0x002C))
+/***Port 1 Pull Up/Pull Down Select Register (005C H)***/
+#define DANUBE_GPIO_P1_PUDSEL           ((volatile u32 *)(DANUBE_GPIO+ 0x005C))
+/***Port 0 Pull Up Device Enable Register (0030 H)***/
+#define DANUBE_GPIO_P0_PUDEN            ((volatile u32 *)(DANUBE_GPIO+ 0x0030))
+/***Port 1 Pull Up Device Enable Register (0060 H)***/
+#define DANUBE_GPIO_P1_PUDEN            ((volatile u32 *)(DANUBE_GPIO+ 0x0060))
+/***********************************************************************/
+/*  Module      :  CGU register address and bits                       */
+/***********************************************************************/
+
+#define DANUBE_CGU                          (0xBF103000)
+/***********************************************************************/
+/***CGU Clock PLL0 ***/
+#define DANUBE_CGU_PLL0_CFG                    ((volatile u32*)(DANUBE_CGU+ 0x0004))
+/***CGU Clock PLL1 ***/
+#define DANUBE_CGU_PLL1_CFG                    ((volatile u32*)(DANUBE_CGU+ 0x0008))
+/***CGU Clock SYS Mux Register***/
+#define DANUBE_CGU_SYS                         ((volatile u32*)(DANUBE_CGU+ 0x0010))
+/***CGU Interface Clock Control Register***/
+#define DANUBE_CGU_IFCCR                        ((volatile u32*)(DANUBE_CGU+ 0x0018))
+/***CGU PCI Clock Control Register**/
+#define DANUBE_CGU_PCICR                          ((volatile u32*)(DANUBE_CGU+ 0x0034))
+#define CLOCK_60M                60000000
+#define CLOCK_83M                83333333
+#define CLOCK_111M               111111111
+#define CLOCK_133M               133333333
+#define CLOCK_167M               166666667
+#define CLOCK_333M               333333333
+
+/***********************************************************************/
+/*  Module      :  MCD register address and bits                       */
+/***********************************************************************/
+#define DANUBE_MCD                                     (KSEG1+0x1F106000)
+
+/***Manufacturer Identification Register***/
+#define DANUBE_MCD_MANID                               ((volatile u32*)(DANUBE_MCD+ 0x0024))
+#define DANUBE_MCD_MANID_MANUF(value)                  (((( 1 << 11) - 1) & (value)) << 5)
+
+/***Chip Identification Register***/
+#define DANUBE_MCD_CHIPID                              ((volatile u32*)(DANUBE_MCD+ 0x0028))
+#define DANUBE_MCD_CHIPID_VERSION_GET(value)             (((value) >> 28) & ((1 << 4) - 1))
+#define DANUBE_MCD_CHIPID_VERSION_SET(value)             (((( 1 << 4) - 1) & (value)) << 28)
+#define DANUBE_MCD_CHIPID_PART_NUMBER_GET(value)         (((value) >> 12) & ((1 << 16) - 1))
+#define DANUBE_MCD_CHIPID_PART_NUMBER_SET(value)         (((( 1 << 16) - 1) & (value)) << 12)
+#define DANUBE_MCD_CHIPID_MANID_GET(value)               (((value) >> 1) & ((1 << 11) - 1))
+#define DANUBE_MCD_CHIPID_MANID_SET(value)               (((( 1 << 11) - 1) & (value)) << 1)
+
+#define DANUBE_CHIPID_STANDARD                         0x00EB
+#define DANUBE_CHIPID_YANGTSE                          0x00ED
+
+/***Redesign Tracing Identification Register***/
+#define DANUBE_MCD_RTID                                ((volatile u32*)(DANUBE_MCD+ 0x002C))
+#define DANUBE_MCD_RTID_LC                              (1 << 15)
+#define DANUBE_MCD_RTID_RIX(value)                     (((( 1 << 3) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/*  Module      :  EBU register address and bits                       */
+/***********************************************************************/
+
+#define DANUBE_EBU                          (0xBE105300)
+
+/***********************************************************************/
+
+/***EBU Clock Control Register***/
+#define DANUBE_EBU_CLC                      ((volatile u32*)(DANUBE_EBU+ 0x0000))
+#define DANUBE_EBU_CLC_DISS                            (1 << 1)
+#define DANUBE_EBU_CLC_DISR                            (1 << 0)
+
+/***EBU Global Control Register***/
+#define DANUBE_EBU_CON                      ((volatile u32*)(DANUBE_EBU+ 0x0010))
+#define DANUBE_EBU_CON_DTACS (value)              (((( 1 << 3) - 1) & (value)) << 20)
+#define DANUBE_EBU_CON_DTARW (value)              (((( 1 << 3) - 1) & (value)) << 16)
+#define DANUBE_EBU_CON_TOUTC (value)              (((( 1 << 8) - 1) & (value)) << 8)
+#define DANUBE_EBU_CON_ARBMODE (value)            (((( 1 << 2) - 1) & (value)) << 6)
+#define DANUBE_EBU_CON_ARBSYNC                      (1 << 5)
+#define DANUBE_EBU_CON_1                              (1 << 3)
+
+/***EBU Address Select Register 0***/
+#define DANUBE_EBU_ADDSEL0                  ((volatile u32*)(DANUBE_EBU+ 0x0020))
+#define DANUBE_EBU_ADDSEL0_BASE (value)               (((( 1 << 20) - 1) & (value)) << 12)
+#define DANUBE_EBU_ADDSEL0_MASK (value)               (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_EBU_ADDSEL0_MIRRORE                      (1 << 1)
+#define DANUBE_EBU_ADDSEL0_REGEN                          (1 << 0)
+
+/***EBU Address Select Register 1***/
+#define DANUBE_EBU_ADDSEL1                  ((volatile u32*)(DANUBE_EBU+ 0x0024))
+#define DANUBE_EBU_ADDSEL1_BASE (value)               (((( 1 << 20) - 1) & (value)) << 12)
+#define DANUBE_EBU_ADDSEL1_MASK (value)               (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_EBU_ADDSEL1_MIRRORE                      (1 << 1)
+#define DANUBE_EBU_ADDSEL1_REGEN                          (1 << 0)
+
+/***EBU Address Select Register 2***/
+#define DANUBE_EBU_ADDSEL2                  ((volatile u32*)(DANUBE_EBU+ 0x0028))
+#define DANUBE_EBU_ADDSEL2_BASE (value)               (((( 1 << 20) - 1) & (value)) << 12)
+#define DANUBE_EBU_ADDSEL2_MASK (value)               (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_EBU_ADDSEL2_MIRRORE                      (1 << 1)
+#define DANUBE_EBU_ADDSEL2_REGEN                          (1 << 0)
+
+/***EBU Address Select Register 3***/
+#define DANUBE_EBU_ADDSEL3                  ((volatile u32*)(DANUBE_EBU+ 0x0028))
+#define DANUBE_EBU_ADDSEL3_BASE (value)               (((( 1 << 20) - 1) & (value)) << 12)
+#define DANUBE_EBU_ADDSEL3_MASK (value)               (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_EBU_ADDSEL3_MIRRORE                      (1 << 1)
+#define DANUBE_EBU_ADDSEL3_REGEN                          (1 << 0)
+
+/***EBU Bus Configuration Register 0***/
+#define DANUBE_EBU_BUSCON0                  ((volatile u32*)(DANUBE_EBU+ 0x0060))
+#define DANUBE_EBU_BUSCON0_WRDIS                          (1 << 31)
+#define DANUBE_EBU_BUSCON0_ALEC (value)               (((( 1 << 2) - 1) & (value)) << 29)
+#define DANUBE_EBU_BUSCON0_BCGEN (value)              (((( 1 << 2) - 1) & (value)) << 27)
+#define DANUBE_EBU_BUSCON0_AGEN (value)               (((( 1 << 2) - 1) & (value)) << 24)
+#define DANUBE_EBU_BUSCON0_CMULTR (value)             (((( 1 << 2) - 1) & (value)) << 22)
+#define DANUBE_EBU_BUSCON0_WAIT (value)               (((( 1 << 2) - 1) & (value)) << 20)
+#define DANUBE_EBU_BUSCON0_WAITINV                      (1 << 19)
+#define DANUBE_EBU_BUSCON0_SETUP                          (1 << 18)
+#define DANUBE_EBU_BUSCON0_PORTW (value)              (((( 1 << 2) - 1) & (value)) << 16)
+#define DANUBE_EBU_BUSCON0_WAITRDC (value)            (((( 1 << 7) - 1) & (value)) << 9)
+#define DANUBE_EBU_BUSCON0_WAITWRC (value)            (((( 1 << 3) - 1) & (value)) << 6)
+#define DANUBE_EBU_BUSCON0_HOLDC (value)              (((( 1 << 2) - 1) & (value)) << 4)
+#define DANUBE_EBU_BUSCON0_RECOVC (value)             (((( 1 << 2) - 1) & (value)) << 2)
+#define DANUBE_EBU_BUSCON0_CMULT (value)              (((( 1 << 2) - 1) & (value)) << 0)
+
+/***EBU Bus Configuration Register 1***/
+#define DANUBE_EBU_BUSCON1                  ((volatile u32*)(DANUBE_EBU+ 0x0064))
+#define DANUBE_EBU_BUSCON1_WRDIS                          (1 << 31)
+#define DANUBE_EBU_BUSCON1_ALEC (value)               (((( 1 << 2) - 1) & (value)) << 29)
+#define DANUBE_EBU_BUSCON1_BCGEN (value)              (((( 1 << 2) - 1) & (value)) << 27)
+#define DANUBE_EBU_BUSCON1_AGEN (value)               (((( 1 << 2) - 1) & (value)) << 24)
+#define DANUBE_EBU_BUSCON1_CMULTR (value)             (((( 1 << 2) - 1) & (value)) << 22)
+#define DANUBE_EBU_BUSCON1_WAIT (value)               (((( 1 << 2) - 1) & (value)) << 20)
+#define DANUBE_EBU_BUSCON1_WAITINV                      (1 << 19)
+#define DANUBE_EBU_BUSCON1_SETUP                          (1 << 18)
+#define DANUBE_EBU_BUSCON1_PORTW (value)              (((( 1 << 2) - 1) & (value)) << 16)
+#define DANUBE_EBU_BUSCON1_WAITRDC (value)            (((( 1 << 7) - 1) & (value)) << 9)
+#define DANUBE_EBU_BUSCON1_WAITWRC (value)            (((( 1 << 3) - 1) & (value)) << 6)
+#define DANUBE_EBU_BUSCON1_HOLDC (value)              (((( 1 << 2) - 1) & (value)) << 4)
+#define DANUBE_EBU_BUSCON1_RECOVC (value)             (((( 1 << 2) - 1) & (value)) << 2)
+#define DANUBE_EBU_BUSCON1_CMULT (value)              (((( 1 << 2) - 1) & (value)) << 0)
+
+/***EBU Bus Configuration Register 2***/
+#define DANUBE_EBU_BUSCON2                  ((volatile u32*)(DANUBE_EBU+ 0x0068))
+#define DANUBE_EBU_BUSCON2_WRDIS                          (1 << 31)
+#define DANUBE_EBU_BUSCON2_ALEC (value)               (((( 1 << 2) - 1) & (value)) << 29)
+#define DANUBE_EBU_BUSCON2_BCGEN (value)              (((( 1 << 2) - 1) & (value)) << 27)
+#define DANUBE_EBU_BUSCON2_AGEN (value)               (((( 1 << 2) - 1) & (value)) << 24)
+#define DANUBE_EBU_BUSCON2_CMULTR (value)             (((( 1 << 2) - 1) & (value)) << 22)
+#define DANUBE_EBU_BUSCON2_WAIT (value)               (((( 1 << 2) - 1) & (value)) << 20)
+#define DANUBE_EBU_BUSCON2_WAITINV                      (1 << 19)
+#define DANUBE_EBU_BUSCON2_SETUP                          (1 << 18)
+#define DANUBE_EBU_BUSCON2_PORTW (value)              (((( 1 << 2) - 1) & (value)) << 16)
+#define DANUBE_EBU_BUSCON2_WAITRDC (value)            (((( 1 << 7) - 1) & (value)) << 9)
+#define DANUBE_EBU_BUSCON2_WAITWRC (value)            (((( 1 << 3) - 1) & (value)) << 6)
+#define DANUBE_EBU_BUSCON2_HOLDC (value)              (((( 1 << 2) - 1) & (value)) << 4)
+#define DANUBE_EBU_BUSCON2_RECOVC (value)             (((( 1 << 2) - 1) & (value)) << 2)
+#define DANUBE_EBU_BUSCON2_CMULT (value)              (((( 1 << 2) - 1) & (value)) << 0)
+
+#define DANUBE_EBU_PCC_CON                  ((volatile u32*)(DANUBE_EBU+ 0x0090))
+#define DANUBE_EBU_PCC_STAT                  ((volatile u32*)(DANUBE_EBU+ 0x0094))
+#define DANUBE_EBU_PCC_ISTAT                  ((volatile u32*)(DANUBE_EBU+ 0x00A0))
+#define DANUBE_EBU_PCC_IEN                  ((volatile u32*)(DANUBE_EBU+ 0x00A4))
+/***********************************************************************/
+/*  Module      :  SDRAM register address and bits                     */
+/***********************************************************************/
+
+#define DANUBE_SDRAM                        (0xBF800000)
+/***********************************************************************/
+
+/***MC Access Error Cause Register***/
+#define DANUBE_SDRAM_MC_ERRCAUSE                  ((volatile u32*)(DANUBE_SDRAM+ 0x0100))
+#define DANUBE_SDRAM_MC_ERRCAUSE_ERR                              (1 << 31)
+#define DANUBE_SDRAM_MC_ERRCAUSE_PORT (value)               (((( 1 << 4) - 1) & (value)) << 16)
+#define DANUBE_SDRAM_MC_ERRCAUSE_CAUSE (value)              (((( 1 << 2) - 1) & (value)) << 0)
+#define DANUBE_SDRAM_MC_ERRCAUSE_Res (value)                (((( 1 << NaN) - 1) & (value)) << NaN)
+
+/***MC Access Error Address Register***/
+#define DANUBE_SDRAM_MC_ERRADDR                   ((volatile u32*)(DANUBE_SDRAM+ 0x0108))
+#define DANUBE_SDRAM_MC_ERRADDR_ADDR
+
+/***MC I/O General Purpose Register***/
+#define DANUBE_SDRAM_MC_IOGP                      ((volatile u32*)(DANUBE_SDRAM+ 0x0800))
+#define DANUBE_SDRAM_MC_IOGP_GPR6 (value)               (((( 1 << 4) - 1) & (value)) << 28)
+#define DANUBE_SDRAM_MC_IOGP_GPR5 (value)               (((( 1 << 4) - 1) & (value)) << 24)
+#define DANUBE_SDRAM_MC_IOGP_GPR4 (value)               (((( 1 << 4) - 1) & (value)) << 20)
+#define DANUBE_SDRAM_MC_IOGP_GPR3 (value)               (((( 1 << 4) - 1) & (value)) << 16)
+#define DANUBE_SDRAM_MC_IOGP_GPR2 (value)               (((( 1 << 4) - 1) & (value)) << 12)
+#define DANUBE_SDRAM_MC_IOGP_CPS                              (1 << 11)
+#define DANUBE_SDRAM_MC_IOGP_CLKDELAY (value)          (((( 1 << 3) - 1) & (value)) << 8)
+#define DANUBE_SDRAM_MC_IOGP_CLKRAT (value)             (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_SDRAM_MC_IOGP_RDDEL (value)              (((( 1 << 4) - 1) & (value)) << 0)
+
+/***MC Self Refresh Register***/
+#define DANUBE_SDRAM_MC_SELFRFSH                  ((volatile u32*)(DANUBE_SDRAM+ 0x0A00))
+#define DANUBE_SDRAM_MC_SELFRFSH_PWDS                            (1 << 1)
+#define DANUBE_SDRAM_MC_SELFRFSH_PWD                              (1 << 0)
+#define DANUBE_SDRAM_MC_SELFRFSH_Res (value)                (((( 1 << 30) - 1) & (value)) << 2)
+
+/***MC Enable Register***/
+#define DANUBE_SDRAM_MC_CTRLENA                   ((volatile u32*)(DANUBE_SDRAM+ 0x1000))
+#define DANUBE_SDRAM_MC_CTRLENA_ENA                              (1 << 0)
+#define DANUBE_SDRAM_MC_CTRLENA_Res (value)                (((( 1 << 31) - 1) & (value)) << 1)
+
+/***MC Mode Register Setup Code***/
+#define DANUBE_SDRAM_MC_MRSCODE                   ((volatile u32*)(DANUBE_SDRAM+ 0x1008))
+#define DANUBE_SDRAM_MC_MRSCODE_UMC (value)                (((( 1 << 5) - 1) & (value)) << 7)
+#define DANUBE_SDRAM_MC_MRSCODE_CL (value)                (((( 1 << 3) - 1) & (value)) << 4)
+#define DANUBE_SDRAM_MC_MRSCODE_WT                              (1 << 3)
+#define DANUBE_SDRAM_MC_MRSCODE_BL (value)                (((( 1 << 3) - 1) & (value)) << 0)
+
+/***MC Configuration Data-word Width Register***/
+#define DANUBE_SDRAM_MC_CFGDW                    ((volatile u32*)(DANUBE_SDRAM+ 0x1010))
+#define DANUBE_SDRAM_MC_CFGDW_DW (value)                (((( 1 << 4) - 1) & (value)) << 0)
+#define DANUBE_SDRAM_MC_CFGDW_Res (value)                (((( 1 << 28) - 1) & (value)) << 4)
+
+/***MC Configuration Physical Bank 0 Register***/
+#define DANUBE_SDRAM_MC_CFGPB0                    ((volatile u32*)(DANUBE_SDRAM+ 0x1018))
+#define DANUBE_SDRAM_MC_CFGPB0_MCSEN0 (value)             (((( 1 << 4) - 1) & (value)) << 12)
+#define DANUBE_SDRAM_MC_CFGPB0_BANKN0 (value)             (((( 1 << 4) - 1) & (value)) << 8)
+#define DANUBE_SDRAM_MC_CFGPB0_ROWW0 (value)              (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_SDRAM_MC_CFGPB0_COLW0 (value)              (((( 1 << 4) - 1) & (value)) << 0)
+#define DANUBE_SDRAM_MC_CFGPB0_Res (value)                (((( 1 << 16) - 1) & (value)) << 16)
+
+/***MC Latency Register***/
+#define DANUBE_SDRAM_MC_LATENCY                   ((volatile u32*)(DANUBE_SDRAM+ 0x1038))
+#define DANUBE_SDRAM_MC_LATENCY_TRP (value)                (((( 1 << 4) - 1) & (value)) << 16)
+#define DANUBE_SDRAM_MC_LATENCY_TRAS (value)               (((( 1 << 4) - 1) & (value)) << 12)
+#define DANUBE_SDRAM_MC_LATENCY_TRCD (value)               (((( 1 << 4) - 1) & (value)) << 8)
+#define DANUBE_SDRAM_MC_LATENCY_TDPL (value)               (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_SDRAM_MC_LATENCY_TDAL (value)               (((( 1 << 4) - 1) & (value)) << 0)
+#define DANUBE_SDRAM_MC_LATENCY_Res (value)                (((( 1 << 12) - 1) & (value)) << 20)
+
+/***MC Refresh Cycle Time Register***/
+#define DANUBE_SDRAM_MC_TREFRESH                  ((volatile u32*)(DANUBE_SDRAM+ 0x1040))
+#define DANUBE_SDRAM_MC_TREFRESH_TREF (value)               (((( 1 << 13) - 1) & (value)) << 0)
+#define DANUBE_SDRAM_MC_TREFRESH_Res (value)                (((( 1 << 19) - 1) & (value)) << 13)
+
+/***********************************************************************/
+/*  Module      :  GPTC register address and bits                       */
+/***********************************************************************/
+
+#define DANUBE_GPTC                   (KSEG1 + 0x1E100A00)
+#define DANUBE_GPTC_CLC               ((volatile u32*) (DANUBE_GPTC + 0x0000))
+#define DANUBE_GPTC_ID                ((volatile u32*) (DANUBE_GPTC + 0x0008))
+#define DANUBE_GPTC_IRNEN             ((volatile u32*) (DANUBE_GPTC + 0x00F4))
+#define DANUBE_GPTC_IRNICR    ((volatile u32*) (DANUBE_GPTC + 0x00F8)
+#define DANUBE_GPTC_IRNCR             ((volatile u32*) (DANUBE_GPTC + 0x00FC))
+
+#define DANUBE_GPTC_CON_1A    ((volatile u32*) (DANUBE_GPTC + 0x0010))
+#define DANUBE_GPTC_RUN_1A    ((volatile u32*) (DANUBE_GPTC + 0x0018))
+#define DANUBE_GPTC_RELOAD_1A ((volatile u32*) (DANUBE_GPTC + 0x0020))
+#define DANUBE_GPTC_COUNT_1A  ((volatile u32*) (DANUBE_GPTC + 0x0028))
+
+#define DANUBE_GPTC_CON_1B    ((volatile u32*) (DANUBE_GPTC + 0x0014))
+#define DANUBE_GPTC_RUN_1B    ((volatile u32*) (DANUBE_GPTC + 0x001C))
+#define DANUBE_GPTC_RELOAD_1B ((volatile u32*) (DANUBE_GPTC + 0x0024))
+#define DANUBE_GPTC_COUNT_1B  ((volatile u32*) (DANUBE_GPTC + 0x002C))
+
+#define DANUBE_GPTC_CON_2A    ((volatile u32*) (DANUBE_GPTC + 0x0030))
+#define DANUBE_GPTC_RUN_2A    ((volatile u32*) (DANUBE_GPTC + 0x0038))
+#define DANUBE_GPTC_RELOAD_2A ((volatile u32*) (DANUBE_GPTC + 0x0040))
+#define DANUBE_GPTC_COUNT_2A  ((volatile u32*) (DANUBE_GPTC + 0x0048))
+
+#define DANUBE_GPTC_CON_2B    ((volatile u32*) (DANUBE_GPTC + 0x0034))
+#define DANUBE_GPTC_RUN_2B    ((volatile u32*) (DANUBE_GPTC + 0x003C))
+#define DANUBE_GPTC_RELOAD_2B ((volatile u32*) (DANUBE_GPTC + 0x0044))
+#define DANUBE_GPTC_COUNT_2B  ((volatile u32*) (DANUBE_GPTC + 0x004C))
+
+/***********************************************************************/
+/*  Module      :  GPTU register address and bits                      */
+/***********************************************************************/
+
+#define DANUBE_GPTU                         (0xB8000300)
+/***********************************************************************/
+
+/***GPT Clock Control Register***/
+#define DANUBE_GPTU_GPT_CLC                      ((volatile u32*)(DANUBE_GPTU+ 0x0000))
+#define DANUBE_GPTU_GPT_CLC_RMC (value)                (((( 1 << 8) - 1) & (value)) << 8)
+#define DANUBE_GPTU_GPT_CLC_DISS                            (1 << 1)
+#define DANUBE_GPTU_GPT_CLC_DISR                            (1 << 0)
+
+/***GPT Timer 3 Control Register***/
+#define DANUBE_GPTU_GPT_T3CON                    ((volatile u32*)(DANUBE_GPTU+ 0x0014))
+#define DANUBE_GPTU_GPT_T3CON_T3RDIR                        (1 << 15)
+#define DANUBE_GPTU_GPT_T3CON_T3CHDIR                      (1 << 14)
+#define DANUBE_GPTU_GPT_T3CON_T3EDGE                        (1 << 13)
+#define DANUBE_GPTU_GPT_T3CON_BPS1 (value)               (((( 1 << 2) - 1) & (value)) << 11)
+#define DANUBE_GPTU_GPT_T3CON_T3OTL                          (1 << 10)
+#define DANUBE_GPTU_GPT_T3CON_T3UD                            (1 << 7)
+#define DANUBE_GPTU_GPT_T3CON_T3R                              (1 << 6)
+#define DANUBE_GPTU_GPT_T3CON_T3M (value)                (((( 1 << 3) - 1) & (value)) << 3)
+#define DANUBE_GPTU_GPT_T3CON_T3I (value)                (((( 1 << 3) - 1) & (value)) << 0)
+
+/***GPT Write Hardware Modified Timer 3 Control Register
+If set and clear bit are written concurrently with 1, the associated bit is not changed.***/
+#define DANUBE_GPTU_GPT_WHBT3CON                 ((volatile u32*)(DANUBE_GPTU+ 0x004C))
+#define DANUBE_GPTU_GPT_WHBT3CON_SETT3CHDIR                (1 << 15)
+#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3CHDIR                (1 << 14)
+#define DANUBE_GPTU_GPT_WHBT3CON_SETT3EDGE                  (1 << 13)
+#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3EDGE                  (1 << 12)
+#define DANUBE_GPTU_GPT_WHBT3CON_SETT3OTL                  (1 << 11)
+#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3OTL                  (1 << 10)
+
+/***GPT Timer 2 Control Register***/
+#define DANUBE_GPTU_GPT_T2CON                    ((volatile u32*)(DANUBE_GPTU+ 0x0010))
+#define DANUBE_GPTU_GPT_T2CON_TxRDIR                        (1 << 15)
+#define DANUBE_GPTU_GPT_T2CON_TxCHDIR                      (1 << 14)
+#define DANUBE_GPTU_GPT_T2CON_TxEDGE                        (1 << 13)
+#define DANUBE_GPTU_GPT_T2CON_TxIRDIS                      (1 << 12)
+#define DANUBE_GPTU_GPT_T2CON_TxRC                            (1 << 9)
+#define DANUBE_GPTU_GPT_T2CON_TxUD                            (1 << 7)
+#define DANUBE_GPTU_GPT_T2CON_TxR                              (1 << 6)
+#define DANUBE_GPTU_GPT_T2CON_TxM (value)                (((( 1 << 3) - 1) & (value)) << 3)
+#define DANUBE_GPTU_GPT_T2CON_TxI (value)                (((( 1 << 3) - 1) & (value)) << 0)
+
+/***GPT Timer 4 Control Register***/
+#define DANUBE_GPTU_GPT_T4CON                    ((volatile u32*)(DANUBE_GPTU+ 0x0018))
+#define DANUBE_GPTU_GPT_T4CON_TxRDIR                        (1 << 15)
+#define DANUBE_GPTU_GPT_T4CON_TxCHDIR                      (1 << 14)
+#define DANUBE_GPTU_GPT_T4CON_TxEDGE                        (1 << 13)
+#define DANUBE_GPTU_GPT_T4CON_TxIRDIS                      (1 << 12)
+#define DANUBE_GPTU_GPT_T4CON_TxRC                            (1 << 9)
+#define DANUBE_GPTU_GPT_T4CON_TxUD                            (1 << 7)
+#define DANUBE_GPTU_GPT_T4CON_TxR                              (1 << 6)
+#define DANUBE_GPTU_GPT_T4CON_TxM (value)                (((( 1 << 3) - 1) & (value)) << 3)
+#define DANUBE_GPTU_GPT_T4CON_TxI (value)                (((( 1 << 3) - 1) & (value)) << 0)
+
+/***GPT Write HW Modified Timer 2 Control Register If set
+ and clear bit are written concurrently with 1, the associated bit is not changed.***/
+#define DANUBE_GPTU_GPT_WHBT2CON                 ((volatile u32*)(DANUBE_GPTU+ 0x0048))
+#define DANUBE_GPTU_GPT_WHBT2CON_SETTxCHDIR                (1 << 15)
+#define DANUBE_GPTU_GPT_WHBT2CON_CLRTxCHDIR                (1 << 14)
+#define DANUBE_GPTU_GPT_WHBT2CON_SETTxEDGE                  (1 << 13)
+#define DANUBE_GPTU_GPT_WHBT2CON_CLRTxEDGE                  (1 << 12)
+
+/***GPT Write HW Modified Timer 4 Control Register If set
+ and clear bit are written concurrently with 1, the associated bit is not changed.***/
+#define DANUBE_GPTU_GPT_WHBT4CON                 ((volatile u32*)(DANUBE_GPTU+ 0x0050))
+#define DANUBE_GPTU_GPT_WHBT4CON_SETTxCHDIR                (1 << 15)
+#define DANUBE_GPTU_GPT_WHBT4CON_CLRTxCHDIR                (1 << 14)
+#define DANUBE_GPTU_GPT_WHBT4CON_SETTxEDGE                  (1 << 13)
+#define DANUBE_GPTU_GPT_WHBT4CON_CLRTxEDGE                  (1 << 12)
+
+/***GPT Capture Reload Register***/
+#define DANUBE_GPTU_GPT_CAPREL                   ((volatile u32*)(DANUBE_GPTU+ 0x0030))
+#define DANUBE_GPTU_GPT_CAPREL_CAPREL (value)             (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 2 Register***/
+#define DANUBE_GPTU_GPT_T2                       ((volatile u32*)(DANUBE_GPTU+ 0x0034))
+#define DANUBE_GPTU_GPT_T2_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 3 Register***/
+#define DANUBE_GPTU_GPT_T3                       ((volatile u32*)(DANUBE_GPTU+ 0x0038))
+#define DANUBE_GPTU_GPT_T3_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 4 Register***/
+#define DANUBE_GPTU_GPT_T4                       ((volatile u32*)(DANUBE_GPTU+ 0x003C))
+#define DANUBE_GPTU_GPT_T4_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 5 Register***/
+#define DANUBE_GPTU_GPT_T5                       ((volatile u32*)(DANUBE_GPTU+ 0x0040))
+#define DANUBE_GPTU_GPT_T5_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 6 Register***/
+#define DANUBE_GPTU_GPT_T6                       ((volatile u32*)(DANUBE_GPTU+ 0x0044))
+#define DANUBE_GPTU_GPT_T6_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 6 Control Register***/
+#define DANUBE_GPTU_GPT_T6CON                    ((volatile u32*)(DANUBE_GPTU+ 0x0020))
+#define DANUBE_GPTU_GPT_T6CON_T6SR                            (1 << 15)
+#define DANUBE_GPTU_GPT_T6CON_T6CLR                          (1 << 14)
+#define DANUBE_GPTU_GPT_T6CON_BPS2 (value)               (((( 1 << 2) - 1) & (value)) << 11)
+#define DANUBE_GPTU_GPT_T6CON_T6OTL                          (1 << 10)
+#define DANUBE_GPTU_GPT_T6CON_T6UD                            (1 << 7)
+#define DANUBE_GPTU_GPT_T6CON_T6R                              (1 << 6)
+#define DANUBE_GPTU_GPT_T6CON_T6M (value)                (((( 1 << 3) - 1) & (value)) << 3)
+#define DANUBE_GPTU_GPT_T6CON_T6I (value)                (((( 1 << 3) - 1) & (value)) << 0)
+
+/***GPT Write HW Modified Timer 6 Control Register If set
+ and clear bit are written concurrently with 1, the associated bit is not changed.***/
+#define DANUBE_GPTU_GPT_WHBT6CON                 ((volatile u32*)(DANUBE_GPTU+ 0x0054))
+#define DANUBE_GPTU_GPT_WHBT6CON_SETT6OTL                  (1 << 11)
+#define DANUBE_GPTU_GPT_WHBT6CON_CLRT6OTL                  (1 << 10)
+
+/***GPT Timer 5 Control Register***/
+#define DANUBE_GPTU_GPT_T5CON                    ((volatile u32*)(DANUBE_GPTU+ 0x001C))
+#define DANUBE_GPTU_GPT_T5CON_T5SC                            (1 << 15)
+#define DANUBE_GPTU_GPT_T5CON_T5CLR                          (1 << 14)
+#define DANUBE_GPTU_GPT_T5CON_CI (value)                (((( 1 << 2) - 1) & (value)) << 12)
+#define DANUBE_GPTU_GPT_T5CON_T5CC                            (1 << 11)
+#define DANUBE_GPTU_GPT_T5CON_CT3                              (1 << 10)
+#define DANUBE_GPTU_GPT_T5CON_T5RC                            (1 << 9)
+#define DANUBE_GPTU_GPT_T5CON_T5UDE                          (1 << 8)
+#define DANUBE_GPTU_GPT_T5CON_T5UD                            (1 << 7)
+#define DANUBE_GPTU_GPT_T5CON_T5R                              (1 << 6)
+#define DANUBE_GPTU_GPT_T5CON_T5M (value)                (((( 1 << 3) - 1) & (value)) << 3)
+#define DANUBE_GPTU_GPT_T5CON_T5I (value)                (((( 1 << 3) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/*  Module      :  IOM register address and bits                       */
+/***********************************************************************/
+
+#define DANUBE_IOM                          (0xBF105000)
+/***********************************************************************/
+
+/***Receive FIFO***/
+#define DANUBE_IOM_RFIFO                        ((volatile u32*)(DANUBE_IOM+ 0x0000))
+#define DANUBE_IOM_RFIFO_RXD (value)                (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Transmit FIFO***/
+#define DANUBE_IOM_XFIFO                        ((volatile u32*)(DANUBE_IOM+ 0x0000))
+#define DANUBE_IOM_XFIFO_TXD (value)                (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Interrupt Status Register HDLC***/
+#define DANUBE_IOM_ISTAH                        ((volatile u32*)(DANUBE_IOM+ 0x0080))
+#define DANUBE_IOM_ISTAH_RME                              (1 << 7)
+#define DANUBE_IOM_ISTAH_RPF                              (1 << 6)
+#define DANUBE_IOM_ISTAH_RFO                              (1 << 5)
+#define DANUBE_IOM_ISTAH_XPR                              (1 << 4)
+#define DANUBE_IOM_ISTAH_XMR                              (1 << 3)
+#define DANUBE_IOM_ISTAH_XDU                              (1 << 2)
+
+/***Interrupt Mask Register HDLC***/
+#define DANUBE_IOM_MASKH                        ((volatile u32*)(DANUBE_IOM+ 0x0080))
+#define DANUBE_IOM_MASKH_RME                              (1 << 7)
+#define DANUBE_IOM_MASKH_RPF                              (1 << 6)
+#define DANUBE_IOM_MASKH_RFO                              (1 << 5)
+#define DANUBE_IOM_MASKH_XPR                              (1 << 4)
+#define DANUBE_IOM_MASKH_XMR                              (1 << 3)
+#define DANUBE_IOM_MASKH_XDU                              (1 << 2)
+
+/***Status Register***/
+#define DANUBE_IOM_STAR                         ((volatile u32*)(DANUBE_IOM+ 0x0084))
+#define DANUBE_IOM_STAR_XDOV                            (1 << 7)
+#define DANUBE_IOM_STAR_XFW                              (1 << 6)
+#define DANUBE_IOM_STAR_RACI                            (1 << 3)
+#define DANUBE_IOM_STAR_XACI                            (1 << 1)
+
+/***Command Register***/
+#define DANUBE_IOM_CMDR                         ((volatile u32*)(DANUBE_IOM+ 0x0084))
+#define DANUBE_IOM_CMDR_RMC                              (1 << 7)
+#define DANUBE_IOM_CMDR_RRES                            (1 << 6)
+#define DANUBE_IOM_CMDR_XTF                              (1 << 3)
+#define DANUBE_IOM_CMDR_XME                              (1 << 1)
+#define DANUBE_IOM_CMDR_XRES                            (1 << 0)
+
+/***Mode Register***/
+#define DANUBE_IOM_MODEH                        ((volatile u32*)(DANUBE_IOM+ 0x0088))
+#define DANUBE_IOM_MODEH_MDS2                            (1 << 7)
+#define DANUBE_IOM_MODEH_MDS1                            (1 << 6)
+#define DANUBE_IOM_MODEH_MDS0                            (1 << 5)
+#define DANUBE_IOM_MODEH_RAC                              (1 << 3)
+#define DANUBE_IOM_MODEH_DIM2                            (1 << 2)
+#define DANUBE_IOM_MODEH_DIM1                            (1 << 1)
+#define DANUBE_IOM_MODEH_DIM0                            (1 << 0)
+
+/***Extended Mode Register***/
+#define DANUBE_IOM_EXMR                         ((volatile u32*)(DANUBE_IOM+ 0x008C))
+#define DANUBE_IOM_EXMR_XFBS                            (1 << 7)
+#define DANUBE_IOM_EXMR_RFBS (value)               (((( 1 << 2) - 1) & (value)) << 5)
+#define DANUBE_IOM_EXMR_SRA                              (1 << 4)
+#define DANUBE_IOM_EXMR_XCRC                            (1 << 3)
+#define DANUBE_IOM_EXMR_RCRC                            (1 << 2)
+#define DANUBE_IOM_EXMR_ITF                              (1 << 0)
+
+/***SAPI1 Register***/
+#define DANUBE_IOM_SAP1                         ((volatile u32*)(DANUBE_IOM+ 0x0094))
+#define DANUBE_IOM_SAP1_SAPI1 (value)              (((( 1 << 6) - 1) & (value)) << 2)
+#define DANUBE_IOM_SAP1_MHA                              (1 << 0)
+
+/***Receive Frame Byte Count Low***/
+#define DANUBE_IOM_RBCL                         ((volatile u32*)(DANUBE_IOM+ 0x0098))
+#define DANUBE_IOM_RBCL_RBC(value)              (1 << value)
+
+/***SAPI2 Register***/
+#define DANUBE_IOM_SAP2                         ((volatile u32*)(DANUBE_IOM+ 0x0098))
+#define DANUBE_IOM_SAP2_SAPI2 (value)              (((( 1 << 6) - 1) & (value)) << 2)
+#define DANUBE_IOM_SAP2_MLA                              (1 << 0)
+
+/***Receive Frame Byte Count High***/
+#define DANUBE_IOM_RBCH                         ((volatile u32*)(DANUBE_IOM+ 0x009C))
+#define DANUBE_IOM_RBCH_OV                              (1 << 4)
+#define DANUBE_IOM_RBCH_RBC11                          (1 << 3)
+#define DANUBE_IOM_RBCH_RBC10                          (1 << 2)
+#define DANUBE_IOM_RBCH_RBC9                            (1 << 1)
+#define DANUBE_IOM_RBCH_RBC8                            (1 << 0)
+
+/***TEI1 Register 1***/
+#define DANUBE_IOM_TEI1                         ((volatile u32*)(DANUBE_IOM+ 0x009C))
+#define DANUBE_IOM_TEI1_TEI1 (value)               (((( 1 << 7) - 1) & (value)) << 1)
+#define DANUBE_IOM_TEI1_EA                              (1 << 0)
+
+/***Receive Status Register***/
+#define DANUBE_IOM_RSTA                         ((volatile u32*)(DANUBE_IOM+ 0x00A0))
+#define DANUBE_IOM_RSTA_VFR                              (1 << 7)
+#define DANUBE_IOM_RSTA_RDO                              (1 << 6)
+#define DANUBE_IOM_RSTA_CRC                              (1 << 5)
+#define DANUBE_IOM_RSTA_RAB                              (1 << 4)
+#define DANUBE_IOM_RSTA_SA1                              (1 << 3)
+#define DANUBE_IOM_RSTA_SA0                              (1 << 2)
+#define DANUBE_IOM_RSTA_TA                              (1 << 0)
+#define DANUBE_IOM_RSTA_CR                              (1 << 1)
+
+/***TEI2 Register***/
+#define DANUBE_IOM_TEI2                         ((volatile u32*)(DANUBE_IOM+ 0x00A0))
+#define DANUBE_IOM_TEI2_TEI2 (value)               (((( 1 << 7) - 1) & (value)) << 1)
+#define DANUBE_IOM_TEI2_EA                              (1 << 0)
+
+/***Test Mode Register HDLC***/
+#define DANUBE_IOM_TMH                          ((volatile u32*)(DANUBE_IOM+ 0x00A4))
+#define DANUBE_IOM_TMH_TLP                              (1 << 0)
+
+/***Command/Indication Receive 0***/
+#define DANUBE_IOM_CIR0                         ((volatile u32*)(DANUBE_IOM+ 0x00B8))
+#define DANUBE_IOM_CIR0_CODR0 (value)              (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_IOM_CIR0_CIC0                            (1 << 3)
+#define DANUBE_IOM_CIR0_CIC1                            (1 << 2)
+#define DANUBE_IOM_CIR0_SG                              (1 << 1)
+#define DANUBE_IOM_CIR0_BAS                              (1 << 0)
+
+/***Command/Indication Transmit 0***/
+#define DANUBE_IOM_CIX0                         ((volatile u32*)(DANUBE_IOM+ 0x00B8))
+#define DANUBE_IOM_CIX0_CODX0 (value)              (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_IOM_CIX0_TBA2                            (1 << 3)
+#define DANUBE_IOM_CIX0_TBA1                            (1 << 2)
+#define DANUBE_IOM_CIX0_TBA0                            (1 << 1)
+#define DANUBE_IOM_CIX0_BAC                              (1 << 0)
+
+/***Command/Indication Receive 1***/
+#define DANUBE_IOM_CIR1                         ((volatile u32*)(DANUBE_IOM+ 0x00BC))
+#define DANUBE_IOM_CIR1_CODR1 (value)              (((( 1 << 6) - 1) & (value)) << 2)
+
+/***Command/Indication Transmit 1***/
+#define DANUBE_IOM_CIX1                         ((volatile u32*)(DANUBE_IOM+ 0x00BC))
+#define DANUBE_IOM_CIX1_CODX1 (value)              (((( 1 << 6) - 1) & (value)) << 2)
+#define DANUBE_IOM_CIX1_CICW                            (1 << 1)
+#define DANUBE_IOM_CIX1_CI1E                            (1 << 0)
+
+/***Controller Data Access Reg. (CH10)***/
+#define DANUBE_IOM_CDA10                        ((volatile u32*)(DANUBE_IOM+ 0x0100))
+#define DANUBE_IOM_CDA10_CDA (value)                (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Controller Data Access Reg. (CH11)***/
+#define DANUBE_IOM_CDA11                        ((volatile u32*)(DANUBE_IOM+ 0x0104))
+#define DANUBE_IOM_CDA11_CDA (value)                (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Controller Data Access Reg. (CH20)***/
+#define DANUBE_IOM_CDA20                        ((volatile u32*)(DANUBE_IOM+ 0x0108))
+#define DANUBE_IOM_CDA20_CDA (value)                (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Controller Data Access Reg. (CH21)***/
+#define DANUBE_IOM_CDA21                        ((volatile u32*)(DANUBE_IOM+ 0x010C))
+#define DANUBE_IOM_CDA21_CDA (value)                (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH10)***/
+#define DANUBE_IOM_CDA_TSDP10                   ((volatile u32*)(DANUBE_IOM+ 0x0110))
+#define DANUBE_IOM_CDA_TSDP10_DPS                              (1 << 7)
+#define DANUBE_IOM_CDA_TSDP10_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH11)***/
+#define DANUBE_IOM_CDA_TSDP11                   ((volatile u32*)(DANUBE_IOM+ 0x0114))
+#define DANUBE_IOM_CDA_TSDP11_DPS                              (1 << 7)
+#define DANUBE_IOM_CDA_TSDP11_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH20)***/
+#define DANUBE_IOM_CDA_TSDP20                   ((volatile u32*)(DANUBE_IOM+ 0x0118))
+#define DANUBE_IOM_CDA_TSDP20_DPS                              (1 << 7)
+#define DANUBE_IOM_CDA_TSDP20_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH21)***/
+#define DANUBE_IOM_CDA_TSDP21                   ((volatile u32*)(DANUBE_IOM+ 0x011C))
+#define DANUBE_IOM_CDA_TSDP21_DPS                              (1 << 7)
+#define DANUBE_IOM_CDA_TSDP21_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH10)***/
+#define DANUBE_IOM_CO_TSDP10                    ((volatile u32*)(DANUBE_IOM+ 0x0120))
+#define DANUBE_IOM_CO_TSDP10_DPS                              (1 << 7)
+#define DANUBE_IOM_CO_TSDP10_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH11)***/
+#define DANUBE_IOM_CO_TSDP11                    ((volatile u32*)(DANUBE_IOM+ 0x0124))
+#define DANUBE_IOM_CO_TSDP11_DPS                              (1 << 7)
+#define DANUBE_IOM_CO_TSDP11_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH20)***/
+#define DANUBE_IOM_CO_TSDP20                    ((volatile u32*)(DANUBE_IOM+ 0x0128))
+#define DANUBE_IOM_CO_TSDP20_DPS                              (1 << 7)
+#define DANUBE_IOM_CO_TSDP20_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH21)***/
+#define DANUBE_IOM_CO_TSDP21                    ((volatile u32*)(DANUBE_IOM+ 0x012C))
+#define DANUBE_IOM_CO_TSDP21_DPS                              (1 << 7)
+#define DANUBE_IOM_CO_TSDP21_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Ctrl. Reg. Contr. Data Access CH1x***/
+#define DANUBE_IOM_CDA1_CR                      ((volatile u32*)(DANUBE_IOM+ 0x0138))
+#define DANUBE_IOM_CDA1_CR_EN_TBM                        (1 << 5)
+#define DANUBE_IOM_CDA1_CR_EN_I1                          (1 << 4)
+#define DANUBE_IOM_CDA1_CR_EN_I0                          (1 << 3)
+#define DANUBE_IOM_CDA1_CR_EN_O1                          (1 << 2)
+#define DANUBE_IOM_CDA1_CR_EN_O0                          (1 << 1)
+#define DANUBE_IOM_CDA1_CR_SWAP                            (1 << 0)
+
+/***Ctrl. Reg. Contr. Data Access CH1x***/
+#define DANUBE_IOM_CDA2_CR                      ((volatile u32*)(DANUBE_IOM+ 0x013C))
+#define DANUBE_IOM_CDA2_CR_EN_TBM                        (1 << 5)
+#define DANUBE_IOM_CDA2_CR_EN_I1                          (1 << 4)
+#define DANUBE_IOM_CDA2_CR_EN_I0                          (1 << 3)
+#define DANUBE_IOM_CDA2_CR_EN_O1                          (1 << 2)
+#define DANUBE_IOM_CDA2_CR_EN_O0                          (1 << 1)
+#define DANUBE_IOM_CDA2_CR_SWAP                            (1 << 0)
+
+/***Control Register B-Channel Data***/
+#define DANUBE_IOM_BCHA_CR                      ((volatile u32*)(DANUBE_IOM+ 0x0144))
+#define DANUBE_IOM_BCHA_CR_EN_BC2                        (1 << 4)
+#define DANUBE_IOM_BCHA_CR_EN_BC1                        (1 << 3)
+
+/***Control Register B-Channel Data***/
+#define DANUBE_IOM_BCHB_CR                      ((volatile u32*)(DANUBE_IOM+ 0x0148))
+#define DANUBE_IOM_BCHB_CR_EN_BC2                        (1 << 4)
+#define DANUBE_IOM_BCHB_CR_EN_BC1                        (1 << 3)
+
+/***Control Reg. for HDLC and CI1 Data***/
+#define DANUBE_IOM_DCI_CR                       ((volatile u32*)(DANUBE_IOM+ 0x014C))
+#define DANUBE_IOM_DCI_CR_DPS_CI1                      (1 << 7)
+#define DANUBE_IOM_DCI_CR_EN_CI1                        (1 << 6)
+#define DANUBE_IOM_DCI_CR_EN_D                            (1 << 5)
+
+/***Control Reg. for HDLC and CI1 Data***/
+#define DANUBE_IOM_DCIC_CR                      ((volatile u32*)(DANUBE_IOM+ 0x014C))
+#define DANUBE_IOM_DCIC_CR_DPS_CI0                      (1 << 7)
+#define DANUBE_IOM_DCIC_CR_EN_CI0                        (1 << 6)
+#define DANUBE_IOM_DCIC_CR_DPS_D                          (1 << 5)
+
+/***Control Reg. Serial Data Strobe x***/
+#define DANUBE_IOM_SDS_CR                       ((volatile u32*)(DANUBE_IOM+ 0x0154))
+#define DANUBE_IOM_SDS_CR_ENS_TSS                      (1 << 7)
+#define DANUBE_IOM_SDS_CR_ENS_TSS_1                  (1 << 6)
+#define DANUBE_IOM_SDS_CR_ENS_TSS_3                  (1 << 5)
+#define DANUBE_IOM_SDS_CR_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Control Register IOM Data***/
+#define DANUBE_IOM_IOM_CR                       ((volatile u32*)(DANUBE_IOM+ 0x015C))
+#define DANUBE_IOM_IOM_CR_SPU                              (1 << 7)
+#define DANUBE_IOM_IOM_CR_CI_CS                          (1 << 5)
+#define DANUBE_IOM_IOM_CR_TIC_DIS                      (1 << 4)
+#define DANUBE_IOM_IOM_CR_EN_BCL                        (1 << 3)
+#define DANUBE_IOM_IOM_CR_CLKM                            (1 << 2)
+#define DANUBE_IOM_IOM_CR_Res                              (1 << 1)
+#define DANUBE_IOM_IOM_CR_DIS_IOM                      (1 << 0)
+
+/***Synchronous Transfer Interrupt***/
+#define DANUBE_IOM_STI                          ((volatile u32*)(DANUBE_IOM+ 0x0160))
+#define DANUBE_IOM_STI_STOV21                        (1 << 7)
+#define DANUBE_IOM_STI_STOV20                        (1 << 6)
+#define DANUBE_IOM_STI_STOV11                        (1 << 5)
+#define DANUBE_IOM_STI_STOV10                        (1 << 4)
+#define DANUBE_IOM_STI_STI21                          (1 << 3)
+#define DANUBE_IOM_STI_STI20                          (1 << 2)
+#define DANUBE_IOM_STI_STI11                          (1 << 1)
+#define DANUBE_IOM_STI_STI10                          (1 << 0)
+
+/***Acknowledge Synchronous Transfer Interrupt***/
+#define DANUBE_IOM_ASTI                         ((volatile u32*)(DANUBE_IOM+ 0x0160))
+#define DANUBE_IOM_ASTI_ACK21                          (1 << 3)
+#define DANUBE_IOM_ASTI_ACK20                          (1 << 2)
+#define DANUBE_IOM_ASTI_ACK11                          (1 << 1)
+#define DANUBE_IOM_ASTI_ACK10                          (1 << 0)
+
+/***Mask Synchronous Transfer Interrupt***/
+#define DANUBE_IOM_MSTI                         ((volatile u32*)(DANUBE_IOM+ 0x0164))
+#define DANUBE_IOM_MSTI_STOV21                        (1 << 7)
+#define DANUBE_IOM_MSTI_STOV20                        (1 << 6)
+#define DANUBE_IOM_MSTI_STOV11                        (1 << 5)
+#define DANUBE_IOM_MSTI_STOV10                        (1 << 4)
+#define DANUBE_IOM_MSTI_STI21                          (1 << 3)
+#define DANUBE_IOM_MSTI_STI20                          (1 << 2)
+#define DANUBE_IOM_MSTI_STI11                          (1 << 1)
+#define DANUBE_IOM_MSTI_STI10                          (1 << 0)
+
+/***Configuration Register for Serial Data Strobes***/
+#define DANUBE_IOM_SDS_CONF                    ((volatile u32*)(DANUBE_IOM+ 0x0168))
+#define DANUBE_IOM_SDS_CONF_SDS_BCL                      (1 << 0)
+
+/***Monitoring CDA Bits***/
+#define DANUBE_IOM_MCDA                         ((volatile u32*)(DANUBE_IOM+ 0x016C))
+#define DANUBE_IOM_MCDA_MCDA21 (value)             (((( 1 << 2) - 1) & (value)) << 6)
+#define DANUBE_IOM_MCDA_MCDA20 (value)             (((( 1 << 2) - 1) & (value)) << 4)
+#define DANUBE_IOM_MCDA_MCDA11 (value)             (((( 1 << 2) - 1) & (value)) << 2)
+#define DANUBE_IOM_MCDA_MCDA10 (value)             (((( 1 << 2) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/*  Module      :  ASC0 register address and bits                      */
+/***********************************************************************/
+#define DANUBE_ASC0                          (KSEG1+0x1E100400)
+/***********************************************************************/
+#define DANUBE_ASC0_TBUF                        ((volatile u32*)(DANUBE_ASC0 + 0x0020))
+#define DANUBE_ASC0_RBUF                        ((volatile u32*)(DANUBE_ASC0 + 0x0024))
+#define DANUBE_ASC0_FSTAT                       ((volatile u32*)(DANUBE_ASC0 + 0x0048))
+#define DANUBE_ASC0_FSTAT_TXFREE_GET(value)     (((value) >> 24) & ((1 << 6) - 1))
+#define DANUBE_ASC0_FSTAT_TXFREE_SET(value)     (((( 1 << 6) - 1) & (value)) << 24)
+#define DANUBE_ASC0_FSTAT_RXFREE_GET(value)     (((value) >> 16) & ((1 << 6) - 1))
+#define DANUBE_ASC0_FSTAT_RXFREE_SET(value)     (((( 1 << 6) - 1) & (value)) << 16)
+#define DANUBE_ASC0_FSTAT_TXFFL_GET(value)      (((value) >> 8) & ((1 << 6) - 1))
+#define DANUBE_ASC0_FSTAT_TXFFL_SET(value)      (((( 1 << 6) - 1) & (value)) << 8)
+#define DANUBE_ASC0_FSTAT_RXFFL_GET(value)      (((value) >> 0) & ((1 << 6) - 1))
+#define DANUBE_ASC0_FSTAT_RXFFL_SET(value)      (((( 1 << 6) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/*  Module      :  ASC1 register address and bits                      */
+/***********************************************************************/
+
+#define DANUBE_ASC1                          (KSEG1+0x1E100C00)
+/***********************************************************************/
+/***ASC Clock Control Register***/
+#define DANUBE_ASC1_CLC                      ((volatile u32*)(DANUBE_ASC1+ 0x0000))
+#define DANUBE_ASC1_CLC_RMC(value)                (((( 1 << 8) - 1) & (value)) << 8)
+#define DANUBE_ASC1_CLC_DISS                            (1 << 1)
+#define DANUBE_ASC1_CLC_DISR                            (1 << 0)
+
+/***ASC Port Input Select Register***/
+#define DANUBE_ASC1_PISEL                    ((volatile u32*)(DANUBE_ASC1+ 0x0004))
+#define DANUBE_ASC1_PISEL                    ((volatile u32*)(DANUBE_ASC1+ 0x0004))
+#define DANUBE_ASC1_PISEL_RIS                              (1 << 0)
+
+/***ASC Control Register***/
+#define DANUBE_ASC1_CON