kernel: backport support for BCM54810 PHY
authorRafał Miłecki <rafal@milecki.pl>
Sat, 28 Jan 2017 17:44:23 +0000 (18:44 +0100)
committerRafał Miłecki <rafal@milecki.pl>
Sat, 28 Jan 2017 18:12:42 +0000 (19:12 +0100)
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
target/linux/generic/patches-4.4/078-0003-net-phy-cherry-pick-Broadcom-drivers-updates-from-v4.patch

index 6f6536b..0aed558 100644 (file)
@@ -7,10 +7,101 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
 
 --- a/drivers/net/phy/broadcom.c
 +++ b/drivers/net/phy/broadcom.c
-@@ -337,6 +337,41 @@ static int bcm5481_config_aneg(struct ph
-       return ret;
+@@ -18,7 +18,7 @@
+ #include <linux/module.h>
+ #include <linux/phy.h>
+ #include <linux/brcmphy.h>
+-
++#include <linux/of.h>
+ #define BRCM_PHY_MODEL(phydev) \
+       ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
+@@ -30,11 +30,49 @@ MODULE_DESCRIPTION("Broadcom PHY driver"
+ MODULE_AUTHOR("Maciej W. Rozycki");
+ MODULE_LICENSE("GPL");
++static int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
++{
++      /* The register must be written to both the Shadow Register Select and
++       * the Shadow Read Register Selector
++       */
++      phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum |
++                regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
++      return phy_read(phydev, MII_BCM54XX_AUX_CTL);
++}
++
+ static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
+ {
+       return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
  }
  
++static int bcm54810_config(struct phy_device *phydev)
++{
++      int rc, val;
++
++      val = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
++      val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
++      rc = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
++                             val);
++      if (rc < 0)
++              return rc;
++
++      val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
++      val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
++      val |= MII_BCM54XX_AUXCTL_MISC_WREN;
++      rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
++                                val);
++      if (rc < 0)
++              return rc;
++
++      val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
++      val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
++      rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
++      if (rc < 0)
++              return rc;
++
++      return 0;
++}
++
+ /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
+ static int bcm50610_a0_workaround(struct phy_device *phydev)
+ {
+@@ -207,6 +245,12 @@ static int bcm54xx_config_init(struct ph
+           (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
+               bcm54xx_adjust_rxrefclk(phydev);
++      if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
++              err = bcm54810_config(phydev);
++              if (err)
++                      return err;
++      }
++
+       bcm54xx_phydsp_config(phydev);
+       return 0;
+@@ -304,6 +348,7 @@ static int bcm5482_read_status(struct ph
+ static int bcm5481_config_aneg(struct phy_device *phydev)
+ {
++      struct device_node *np = phydev->dev.of_node;
+       int ret;
+       /* Aneg firsly. */
+@@ -334,6 +379,49 @@ static int bcm5481_config_aneg(struct ph
+               phy_write(phydev, 0x18, reg);
+       }
++      if (of_property_read_bool(np, "enet-phy-lane-swap")) {
++              /* Lane Swap - Undocumented register...magic! */
++              ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
++                                      0x11B);
++              if (ret < 0)
++                      return ret;
++      }
++
++      return ret;
++}
++
 +static int bcm54612e_config_aneg(struct phy_device *phydev)
 +{
 +      int ret;
@@ -43,13 +134,10 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
 +                                   MII_BCM54XX_AUXCTL_MISC_WREN | reg);
 +      }
 +
-+      return ret;
-+}
-+
- static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
- {
-       int val;
-@@ -488,6 +523,19 @@ static struct phy_driver broadcom_driver
+       return ret;
+ }
+@@ -488,6 +576,19 @@ static struct phy_driver broadcom_driver
        .config_intr    = bcm_phy_config_intr,
        .driver         = { .owner = THIS_MODULE },
  }, {
@@ -69,7 +157,27 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
        .phy_id         = PHY_ID_BCM54616S,
        .phy_id_mask    = 0xfffffff0,
        .name           = "Broadcom BCM54616S",
-@@ -612,6 +660,7 @@ static struct mdio_device_id __maybe_unu
+@@ -527,6 +628,19 @@ static struct phy_driver broadcom_driver
+       .config_intr    = bcm_phy_config_intr,
+       .driver         = { .owner = THIS_MODULE },
+ }, {
++      .phy_id         = PHY_ID_BCM54810,
++      .phy_id_mask    = 0xfffffff0,
++      .name           = "Broadcom BCM54810",
++      .features       = PHY_GBIT_FEATURES |
++                        SUPPORTED_Pause | SUPPORTED_Asym_Pause,
++      .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
++      .config_init    = bcm54xx_config_init,
++      .config_aneg    = bcm5481_config_aneg,
++      .read_status    = genphy_read_status,
++      .ack_interrupt  = bcm_phy_ack_intr,
++      .config_intr    = bcm_phy_config_intr,
++      .driver         = { .owner = THIS_MODULE },
++}, {
+       .phy_id         = PHY_ID_BCM5482,
+       .phy_id_mask    = 0xfffffff0,
+       .name           = "Broadcom BCM5482",
+@@ -612,9 +726,11 @@ static struct mdio_device_id __maybe_unu
        { PHY_ID_BCM5411, 0xfffffff0 },
        { PHY_ID_BCM5421, 0xfffffff0 },
        { PHY_ID_BCM5461, 0xfffffff0 },
@@ -77,9 +185,19 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
        { PHY_ID_BCM54616S, 0xfffffff0 },
        { PHY_ID_BCM5464, 0xfffffff0 },
        { PHY_ID_BCM5481, 0xfffffff0 },
++      { PHY_ID_BCM54810, 0xfffffff0 },
+       { PHY_ID_BCM5482, 0xfffffff0 },
+       { PHY_ID_BCM50610, 0xfffffff0 },
+       { PHY_ID_BCM50610M, 0xfffffff0 },
 --- a/include/linux/brcmphy.h
 +++ b/include/linux/brcmphy.h
-@@ -18,6 +18,7 @@
+@@ -13,11 +13,13 @@
+ #define PHY_ID_BCM5241                        0x0143bc30
+ #define PHY_ID_BCMAC131                       0x0143bc70
+ #define PHY_ID_BCM5481                        0x0143bca0
++#define PHY_ID_BCM54810                       0x03625d00
+ #define PHY_ID_BCM5482                        0x0143bcb0
+ #define PHY_ID_BCM5411                        0x00206070
  #define PHY_ID_BCM5421                        0x002060e0
  #define PHY_ID_BCM5464                        0x002060b0
  #define PHY_ID_BCM5461                        0x002060c0
@@ -87,7 +205,15 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  #define PHY_ID_BCM54616S              0x03625d10
  #define PHY_ID_BCM57780                       0x03625d90
  
-@@ -102,11 +103,12 @@
+@@ -52,6 +54,7 @@
+ #define PHY_BRCM_EXT_IBND_TX_ENABLE   0x00002000
+ #define PHY_BRCM_CLEAR_RGMII_MODE     0x00004000
+ #define PHY_BRCM_DIS_TXCRXC_NOENRGY   0x00008000
++
+ /* Broadcom BCM7xxx specific workarounds */
+ #define PHY_BRCM_7XXX_REV(x)          (((x) >> 8) & 0xff)
+ #define PHY_BRCM_7XXX_PATCH(x)                ((x) & 0xff)
+@@ -102,11 +105,14 @@
  #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA     0x0800
  
  #define MII_BCM54XX_AUXCTL_MISC_WREN  0x8000
@@ -95,9 +221,35 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX   0x0200
  #define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC    0x7000
  #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC       0x0007
++#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
++#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN (1 << 8)
  
 -#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL     0x0000
 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK       0x0007
  
  /*
   * Broadcom LED source encodings.  These are used in BCM5461, BCM5481,
+@@ -186,6 +192,12 @@
+ #define BCM5482_SSD_SGMII_SLAVE_EN    0x0002  /* Slave mode enable */
+ #define BCM5482_SSD_SGMII_SLAVE_AD    0x0001  /* Slave auto-detection */
++/* BCM54810 Registers */
++#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL  (MII_BCM54XX_EXP_SEL_ER + 0x90)
++#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN       (1 << 0)
++#define BCM54810_SHD_CLK_CTL                  0x3
++#define BCM54810_SHD_CLK_CTL_GTXCLK_EN                (1 << 9)
++
+ /*****************************************************************************/
+ /* Fast Ethernet Transceiver definitions. */
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -77,7 +77,7 @@ config BROADCOM_PHY
+       select BCM_NET_PHYLIB
+       ---help---
+         Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
+-        BCM5481 and BCM5482 PHYs.
++        BCM5481, BCM54810 and BCM5482 PHYs.
+ config BCM_CYGNUS_PHY
+       tristate "Drivers for Broadcom Cygnus SoC internal PHY"