++static int bcm54810_config(struct phy_device *phydev)
++{
++ int rc, val;
++
++ val = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
++ val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
++ rc = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
++ val);
++ if (rc < 0)
++ return rc;
++
++ val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
++ val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
++ val |= MII_BCM54XX_AUXCTL_MISC_WREN;
++ rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
++ val);
++ if (rc < 0)
++ return rc;
++
++ val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
++ val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
++ rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
++ if (rc < 0)
++ return rc;
++
++ return 0;
++}
++
+ /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
+ static int bcm50610_a0_workaround(struct phy_device *phydev)
+ {
+@@ -207,6 +245,12 @@ static int bcm54xx_config_init(struct ph
+ (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
+ bcm54xx_adjust_rxrefclk(phydev);
+
++ if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
++ err = bcm54810_config(phydev);
++ if (err)
++ return err;
++ }
++
+ bcm54xx_phydsp_config(phydev);
+
+ return 0;
+@@ -304,6 +348,7 @@ static int bcm5482_read_status(struct ph
+
+ static int bcm5481_config_aneg(struct phy_device *phydev)
+ {
++ struct device_node *np = phydev->dev.of_node;
+ int ret;
+
+ /* Aneg firsly. */
+@@ -334,6 +379,49 @@ static int bcm5481_config_aneg(struct ph
+ phy_write(phydev, 0x18, reg);
+ }
+
++ if (of_property_read_bool(np, "enet-phy-lane-swap")) {
++ /* Lane Swap - Undocumented register...magic! */
++ ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
++ 0x11B);
++ if (ret < 0)
++ return ret;
++ }
++
++ return ret;
++}
++