ipq806x: add ipq4019 support
authorChristian Lamparter <chunkeey@googlemail.com>
Tue, 14 Mar 2017 16:02:20 +0000 (17:02 +0100)
committerJohn Crispin <john@phrozen.org>
Wed, 22 Mar 2017 08:45:18 +0000 (09:45 +0100)
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: John Crispin <john@phrozen.org>
31 files changed:
target/linux/ipq806x/config-4.9
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-bus.dtsi [new file with mode: 0644]
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-fritz4040.dts [new file with mode: 0644]
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-nbg6617.dts [new file with mode: 0644]
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-rt-ac58u.dts [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/0021-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch [deleted file]
target/linux/ipq806x/patches-4.9/0022-dts-ipq4019-support-ARMv7-PMU.patch
target/linux/ipq806x/patches-4.9/0023-qcom-ipq4019-Add-IPQ4019-USB-HS-SS-PHY-drivers.patch [deleted file]
target/linux/ipq806x/patches-4.9/0024-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch [deleted file]
target/linux/ipq806x/patches-4.9/0025-qcom-ipq4019-enable-USB-bus-for-DK01.1-board.patch [deleted file]
target/linux/ipq806x/patches-4.9/0026-dts-ipq4019-Add-support-for-IPQ4019-DK04-board.patch
target/linux/ipq806x/patches-4.9/0069-arm-boot-add-dts-files.patch
target/linux/ipq806x/patches-4.9/104-mtd-nand-add-Winbond-manufacturer-and-chip.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/105-mtd-nor-add-mx25l25635f.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/130-pinctrl-ipq4019-add-pinctrl.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/307-ARM-qcom-Add-IPQ4019-SoC-support.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/308-dts-ipq4019-add-both-IPQ4019-wifi-block-definitions.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/309-dts-ipq4019-add-pseudo-random-number-generator.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/310-msm-adhoc-bus-support.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/400-mtd-ubi-add-quirk-to-autoload-ubi-on-rt-ac58u.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/605-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/700-net-add-qualcomm-mdio-and-phy.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/701-dts-ipq4019-add-mdio-node.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/702-dts-ipq4019-add-PHY-switch-nodes.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/710-net-add-qualcomm-essedma-ethernet-driver.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/711-dts-ipq4019-add-ethernet-essedma-node.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/820-qcom-ipq4019-Add-IPQ4019-USB-HS-SS-PHY-drivers.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/830-usb-dwc3-register-qca-ipq4019-dwc3-in-dwc3-of-simple.patch [new file with mode: 0644]
target/linux/ipq806x/patches-4.9/850-soc-add-qualcomm-syscon.patch [new file with mode: 0644]

index b66717d..3897284 100644 (file)
@@ -2,6 +2,7 @@ CONFIG_ALIGNMENT_TRAP=y
 # CONFIG_AMBA_PL08X is not set
 CONFIG_APQ_GCC_8084=y
 CONFIG_APQ_MMCC_8084=y
+CONFIG_AR40XX_PHY=y
 CONFIG_AR8216_PHY=y
 CONFIG_ARCH_CLOCKSOURCE_DATA=y
 CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
@@ -10,6 +11,7 @@ CONFIG_ARCH_HAS_SG_CHAIN=y
 CONFIG_ARCH_HAS_TICK_BROADCAST=y
 CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_IPQ40XX=y
 # CONFIG_ARCH_MDM9615 is not set
 CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
 CONFIG_ARCH_MSM8960=y
@@ -66,6 +68,7 @@ CONFIG_BLK_MQ_PCI=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
 CONFIG_BOUNCE=y
+CONFIG_BUS_TOPOLOGY_ADHOC=y
 # CONFIG_CACHE_L2X0 is not set
 CONFIG_CLKDEV_LOOKUP=y
 CONFIG_CLKSRC_OF=y
@@ -143,6 +146,7 @@ CONFIG_DYNAMIC_DEBUG=y
 CONFIG_EARLY_PRINTK=y
 CONFIG_EDAC_ATOMIC_SCRUB=y
 CONFIG_EDAC_SUPPORT=y
+CONFIG_ESSEDMA=y
 CONFIG_ETHERNET_PACKET_MANGLE=y
 CONFIG_FIXED_PHY=y
 CONFIG_FIX_EARLYCON_MEM=y
@@ -253,6 +257,7 @@ CONFIG_LZO_DECOMPRESS=y
 CONFIG_MDIO_BITBANG=y
 CONFIG_MDIO_BOARDINFO=y
 CONFIG_MDIO_GPIO=y
+CONFIG_MDIO_IPQ40XX=y
 # CONFIG_MDM_GCC_9615 is not set
 # CONFIG_MDM_LCC_9615 is not set
 # CONFIG_MFD_MAX77620 is not set
@@ -272,6 +277,7 @@ CONFIG_MMC_SDHCI_MSM=y
 CONFIG_MMC_SDHCI_PLTFM=y
 # CONFIG_MMC_TIFM_SD is not set
 CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MSM_BUS_SCALING=y
 CONFIG_MSM_GCC_8660=y
 # CONFIG_MSM_GCC_8916 is not set
 CONFIG_MSM_GCC_8960=y
@@ -291,6 +297,7 @@ CONFIG_MTD_NAND_QCOM=y
 CONFIG_MTD_QCOM_SMEM_PARTS=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIRMWARE_NAME="firmware"
 CONFIG_MTD_SPLIT_FIT_FW=y
 CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_BEB_LIMIT=20
@@ -389,6 +396,7 @@ CONFIG_QCOM_SCM_32=y
 CONFIG_QCOM_SMEM=y
 # CONFIG_QCOM_SMP2P is not set
 # CONFIG_QCOM_SMSM is not set
+CONFIG_QCOM_TCSR=y
 CONFIG_QCOM_TSENS=y
 # CONFIG_QCOM_WCNSS_PIL is not set
 CONFIG_QCOM_WDT=y
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-bus.dtsi b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-bus.dtsi
new file mode 100644 (file)
index 0000000..1695059
--- /dev/null
@@ -0,0 +1,1142 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+/ {
+
+soc {
+       ad_hoc_bus: ad-hoc-bus {
+               compatible = "qcom,msm-bus-device";
+               reg = <0x580000 0x14000>,
+                       <0x500000 0x11000>;
+               reg-names = "snoc-base", "pcnoc-base";
+
+               /*Buses*/
+
+               fab_pcnoc: fab-pcnoc {
+                       cell-id = <MSM_BUS_FAB_PERIPH_NOC>;
+                       label = "fab-pcnoc";
+                       qcom,fab-dev;
+                       qcom,base-name = "pcnoc-base";
+                       qcom,bypass-qos-prg;
+                       qcom,bus-type = <1>;
+                       qcom,qos-off = <0x1000>;
+                       qcom,base-offset = <0x0>;
+                       clocks = <>;
+               };
+
+               fab_snoc: fab-snoc {
+                       cell-id = <MSM_BUS_FAB_SYS_NOC>;
+                       label = "fab-snoc";
+                       qcom,fab-dev;
+                       qcom,base-name = "snoc-base";
+                       qcom,bypass-qos-prg;
+                       qcom,bus-type = <1>;
+                       qcom,qos-off = <0x80>;
+                       qcom,base-offset = <0x0>;
+                       clocks = <>;
+               };
+
+               /*Masters*/
+
+               mas_blsp_bam: mas-blsp-bam {
+                       cell-id = <MSM_BUS_MASTER_BLSP_BAM>;
+                       label = "mas-blsp-bam";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_m_0>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_BLSP_BAM>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_usb2_bam: mas-usb2-bam {
+                       cell-id = <MSM_BUS_MASTER_USB2_BAM>;
+                       label = "mas-usb2-bam";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,qport = <15>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&slv_pcnoc_snoc>;
+                       qcom,prio1 = <1>;
+                       qcom,prio0 = <1>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_USB2_BAM>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_adss_dma0: mas-adss-dma0 {
+                       cell-id = <MSM_BUS_MASTER_ADDS_DMA0>;
+                       label = "mas-adss-dma0";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_m_1>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_ADSS_DMA0>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_adss_dma1: mas-adss-dma1 {
+                       cell-id = <MSM_BUS_MASTER_ADDS_DMA1>;
+                       label = "mas-adss-dma1";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_m_1>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_ADSS_DMA1>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_adss_dma2: mas-adss-dma2 {
+                       cell-id = <MSM_BUS_MASTER_ADDS_DMA2>;
+                       label = "mas-adss-dma2";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_m_1>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_ADSS_DMA2>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_adss_dma3: mas-adss-dma3 {
+                       cell-id = <MSM_BUS_MASTER_ADDS_DMA3>;
+                       label = "mas-adss-dma3";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_m_1>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_ADSS_DMA3>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_qpic_bam: mas-qpic-bam {
+                       cell-id = <MSM_BUS_MASTER_QPIC_BAM>;
+                       label = "mas-qpic-bam";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_m_0>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_QPIC_BAM>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_spdm: mas-spdm {
+                       cell-id = <MSM_BUS_MASTER_SPDM>;
+                       label = "mas-spdm";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_m_0>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_SPDM>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_pcnoc_cfg: mas-pcnoc-cfg {
+                       cell-id = <MSM_BUS_MASTER_PNOC_CFG>;
+                       label = "mas-pcnoc-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&slv_srvc_pcnoc>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_CFG>;
+               };
+
+               mas_tic: mas-tic {
+                       cell-id = <MSM_BUS_MASTER_TIC>;
+                       label = "mas-tic";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_int_0 &slv_pcnoc_snoc>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_TIC>;
+               };
+
+               mas_sdcc_bam: mas-sdcc-bam {
+                       cell-id = <MSM_BUS_MASTER_SDCC_BAM>;
+                       label = "mas-sdcc-bam";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,qport = <14>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&slv_pcnoc_snoc>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_SDCC_BAM>;
+                       qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
+                                &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
+                                &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
+                                &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
+                                &slv_srif &slv_prng &slv_qdss_cfg
+                                &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
+                                &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
+                                &slv_boot_rom &slv_security &slv_spdm
+                                &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
+                                &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
+                                &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
+                                &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
+                                &slv_sdcc_cfg &slv_snoc_cfg>;
+               };
+
+               mas_snoc_pcnoc: mas-snoc-pcnoc {
+                       cell-id = <MSM_BUS_SNOC_PNOC_MAS>;
+                       label = "mas-snoc-pcnoc";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,qport = <16>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&pcnoc_int_0>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_SNOC_PCNOC>;
+               };
+
+               mas_qdss_dap: mas-qdss-dap {
+                       cell-id = <MSM_BUS_MASTER_QDSS_DAP>;
+                       label = "mas-qdss-dap";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&pcnoc_int_0 &slv_pcnoc_snoc>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_QDSS_DAP>;
+               };
+
+               mas_ddrc_snoc: mas-ddrc-snoc {
+                       cell-id = <MSM_BUS_MASTER_DDRC_SNOC>;
+                       label = "mas-ddrc-snoc";
+                       qcom,buswidth = <16>;
+                       qcom,ap-owned;
+                       qcom,connections = <&snoc_int_0 &snoc_int_1
+                                &slv_pcie>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_DDRC_SNOC>;
+                       qcom,blacklist = <&slv_snoc_ddrc_m1 &slv_srvc_snoc>;
+               };
+
+               mas_wss_0: mas-wss-0 {
+                       cell-id = <MSM_BUS_MASTER_WSS_0>;
+                       label = "mas-wss-0";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,qport = <26>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_WSS_0>;
+                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_pcie
+                                &slv_wss1_cfg &slv_wss0_cfg &slv_crypto_cfg
+                                &slv_srvc_snoc>;
+               };
+
+               mas_wss_1: mas-wss-1 {
+                       cell-id = <MSM_BUS_MASTER_WSS_1>;
+                       label = "mas-wss-1";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,qport = <27>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_WSS_1>;
+                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_pcie
+                                &slv_wss1_cfg &slv_wss0_cfg &slv_crypto_cfg
+                                &slv_srvc_snoc>;
+               };
+
+               mas_crypto: mas-crypto {
+                       cell-id = <MSM_BUS_MASTER_CRYPTO>;
+                       label = "mas-crypto";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,qport = <5>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&snoc_int_0 &snoc_int_1
+                                &slv_snoc_ddrc_m1>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO>;
+                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
+                                &slv_pcie &slv_qdss_stm &slv_crypto_cfg
+                                &slv_srvc_snoc>;
+               };
+
+               mas_ess: mas-ess {
+                       cell-id = <MSM_BUS_MASTER_ESS>;
+                       label = "mas-ess";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,qport = <44>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_ESS>;
+                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
+                                &slv_pcie &slv_qdss_stm &slv_wss1_cfg
+                                &slv_wss0_cfg &slv_crypto_cfg &slv_srvc_snoc>;
+               };
+
+               mas_pcie: mas-pcie {
+                       cell-id = <MSM_BUS_MASTER_PCIE>;
+                       label = "mas-pcie";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,qport = <6>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCIE>;
+                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_pcie
+                                &slv_qdss_stm &slv_wss1_cfg &slv_wss0_cfg
+                                &slv_crypto_cfg &slv_srvc_snoc>;
+               };
+
+               mas_usb3: mas-usb3 {
+                       cell-id = <MSM_BUS_MASTER_USB3>;
+                       label = "mas-usb3";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,qport = <7>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_USB3>;
+                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
+                                &slv_pcie &slv_qdss_stm &slv_wss1_cfg
+                                &slv_wss0_cfg &slv_crypto_cfg &slv_srvc_snoc>;
+               };
+
+               mas_qdss_etr: mas-qdss-etr {
+                       cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
+                       label = "mas-qdss-etr";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,qport = <544>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&qdss_int>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>;
+                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
+                                &slv_pcie &slv_qdss_stm &slv_wss1_cfg
+                                &slv_wss0_cfg &slv_crypto_cfg &slv_srvc_snoc>;
+               };
+
+               mas_qdss_bamndp: mas-qdss-bamndp {
+                       cell-id = <MSM_BUS_MASTER_QDSS_BAMNDP>;
+                       label = "mas-qdss-bamndp";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,qport = <576>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&qdss_int>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAMNDP>;
+                       qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
+                                &slv_pcie &slv_qdss_stm &slv_wss1_cfg
+                                &slv_wss0_cfg &slv_crypto_cfg &slv_srvc_snoc>;
+               };
+
+               mas_pcnoc_snoc: mas-pcnoc-snoc {
+                       cell-id = <MSM_BUS_PNOC_SNOC_MAS>;
+                       label = "mas-pcnoc-snoc";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,qport = <384>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&snoc_int_0 &snoc_int_1
+                                &slv_snoc_ddrc_m1>;
+                       qcom,prio1 = <0>;
+                       qcom,prio0 = <0>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PNOC_SNOC>;
+                       qcom,blacklist = <&slv_srvc_snoc>;
+               };
+
+               mas_snoc_cfg: mas-snoc-cfg {
+                       cell-id = <MSM_BUS_MASTER_QDSS_SNOC_CFG>;
+                       label = "mas-snoc-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&slv_srvc_snoc>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_QDSS_SNOC_CFG>;
+               };
+
+               /*Internal nodes*/
+
+
+               pcnoc_m_0: pcnoc-m-0 {
+                       cell-id = <MSM_BUS_PNOC_M_0>;
+                       label = "pcnoc-m-0";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,qport = <12>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&slv_pcnoc_snoc>;
+                       qcom,prio1 = <1>;
+                       qcom,prio0 = <1>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_0>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_0>;
+               };
+
+               pcnoc_m_1: pcnoc-m-1 {
+                       cell-id = <MSM_BUS_PNOC_M_1>;
+                       label = "pcnoc-m-1";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,qport = <13>;
+                       qcom,qos-mode = "fixed";
+                       qcom,connections = <&slv_pcnoc_snoc>;
+                       qcom,prio1 = <1>;
+                       qcom,prio0 = <1>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_1>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_1>;
+               };
+
+               pcnoc_int_0: pcnoc-int-0 {
+                       cell-id = <MSM_BUS_PNOC_INT_0>;
+                       label = "pcnoc-int-0";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,connections = < &pcnoc_s_1 &pcnoc_s_2 &pcnoc_s_0
+                                &pcnoc_s_4 &pcnoc_s_5
+                                &pcnoc_s_6 &pcnoc_s_7
+                                &pcnoc_s_8 &pcnoc_s_9
+                                &pcnoc_s_3>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_0>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_0>;
+               };
+
+               pcnoc_s_0: pcnoc-s-0 {
+                       cell-id = <MSM_BUS_PNOC_SLV_0>;
+                       label = "pcnoc-s-0";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&slv_clk_ctl &slv_tcsr &slv_security
+                                &slv_tlmm>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_0>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_0>;
+               };
+
+               pcnoc_s_1: pcnoc-s-1 {
+                       cell-id = <MSM_BUS_PNOC_SLV_1>;
+                       label = "pcnoc-s-1";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_prng_apu_cfg &slv_prng&slv_imem_cfg>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_1>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_1>;
+               };
+
+               pcnoc_s_2: pcnoc-s-2 {
+                       cell-id = <MSM_BUS_PNOC_SLV_2>;
+                       label = "pcnoc-s-2";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_spdm &slv_pcnoc_mpu_cfg &slv_pcnoc_cfg
+                               &slv_boot_rom>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_2>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_2>;
+               };
+
+               pcnoc_s_3: pcnoc-s-3 {
+                       cell-id = <MSM_BUS_PNOC_SLV_3>;
+                       label = "pcnoc-s-3";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_qdss_cfg&slv_gcnt &slv_snoc_cfg
+                                &slv_snoc_mpu_cfg>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_3>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_3>;
+               };
+
+               pcnoc_s_4: pcnoc-s-4 {
+                       cell-id = <MSM_BUS_PNOC_SLV_4>;
+                       label = "pcnoc-s-4";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&slv_adss_cfg &slv_adss_vmidmt_cfg &slv_adss_apu>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_4>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_4>;
+               };
+
+               pcnoc_s_5: pcnoc-s-5 {
+                       cell-id = <MSM_BUS_PNOC_SLV_5>;
+                       label = "pcnoc-s-5";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = <&slv_qhss_apu_cfg &slv_fephy_cfg &slv_mdio
+                                &slv_srif>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_5>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_5>;
+               };
+
+               pcnoc_s_6: pcnoc-s-6 {
+                       cell-id = <MSM_BUS_PNOC_SLV_6>;
+                       label = "pcnoc-s-6";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_ddrc_mpu0_cfg &slv_ddrc_apu_cfg &slv_ddrc_mpu2_cfg
+                               &slv_ddrc_cfg &slv_ddrc_mpu1_cfg>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_6>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_6>;
+               };
+
+               pcnoc_s_7: pcnoc-s-7 {
+                       cell-id = <MSM_BUS_PNOC_SLV_7>;
+                       label = "pcnoc-s-7";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_ess_apu_cfg &slv_usb2_cfg&slv_ess_vmidmt_cfg>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_7>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_7>;
+               };
+
+               pcnoc_s_8: pcnoc-s-8 {
+                       cell-id = <MSM_BUS_PNOC_SLV_8>;
+                       label = "pcnoc-s-8";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_sdcc_cfg &slv_qpic_cfg&slv_blsp_cfg>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_8>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_8>;
+               };
+
+               pcnoc_s_9: pcnoc-s-9 {
+                       cell-id = <MSM_BUS_PNOC_SLV_9>;
+                       label = "pcnoc-s-9";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_wss1_apu_cfg &slv_wss1_vmidmt_cfg&slv_wss0_vmidmt_cfg
+                                &slv_wss0_apu_cfg>;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_9>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_9>;
+               };
+
+               snoc_int_0: snoc-int-0 {
+                       cell-id = <MSM_BUS_SNOC_INT_0>;
+                       label = "snoc-int-0";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_ocimem&slv_qdss_stm>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_0>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_0>;
+               };
+
+               snoc_int_1: snoc-int-1 {
+                       cell-id = <MSM_BUS_SNOC_INT_1>;
+                       label = "snoc-int-1";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,connections = < &slv_crypto_cfg &slv_a7ss &slv_ess_cfg
+                                &slv_usb3_cfg &slv_wss1_cfg
+                               &slv_wss0_cfg>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_1>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_1>;
+               };
+
+               qdss_int: qdss-int {
+                       cell-id = <MSM_BUS_SNOC_QDSS_INT>;
+                       label = "qdss-int";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,mas-rpm-id = <ICBID_MASTER_QDSS_INT>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_INT>;
+               };
+               /*Slaves*/
+
+               slv_clk_ctl:slv-clk-ctl {
+                       cell-id = <MSM_BUS_SLAVE_CLK_CTL>;
+                       label = "slv-clk-ctl";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_CLK_CTL>;
+               };
+
+               slv_security:slv-security {
+                       cell-id = <MSM_BUS_SLAVE_SECURITY>;
+                       label = "slv-security";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SECURITY>;
+               };
+
+               slv_tcsr:slv-tcsr {
+                       cell-id = <MSM_BUS_SLAVE_TCSR>;
+                       label = "slv-tcsr";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>;
+               };
+
+               slv_tlmm:slv-tlmm {
+                       cell-id = <MSM_BUS_SLAVE_TLMM>;
+                       label = "slv-tlmm";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_TLMM>;
+               };
+
+               slv_imem_cfg:slv-imem-cfg {
+                       cell-id = <MSM_BUS_SLAVE_IMEM_CFG>;
+                       label = "slv-imem-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_IMEM_CFG>;
+               };
+
+               slv_prng:slv-prng {
+                       cell-id = <MSM_BUS_SLAVE_PRNG>;
+                       label = "slv-prng";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>;
+               };
+
+               slv_prng_apu_cfg:slv-prng-apu-cfg {
+                       cell-id = <MSM_BUS_SLAVE_PRNG_APU_CFG>;
+                       label = "slv-prng-apu-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PRNG_APU_CFG>;
+               };
+
+               slv_boot_rom:slv-boot-rom {
+                       cell-id = <MSM_BUS_SLAVE_BOOT_ROM>;
+                       label = "slv-boot-rom";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_BOOT_ROM>;
+               };
+
+               slv_spdm:slv-spdm {
+                       cell-id = <MSM_BUS_SLAVE_SPDM_WRAPPER>;
+                       label = "slv-spdm";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SPDM_WRAPPER>;
+               };
+
+               slv_pcnoc_cfg:slv-pcnoc-cfg {
+                       cell-id = <MSM_BUS_SLAVE_PNOC_CFG>;
+                       label = "slv-pcnoc-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PNOC_CFG>;
+               };
+
+               slv_pcnoc_mpu_cfg:slv-pcnoc-mpu-cfg {
+                       cell-id = <MSM_BUS_SLAVE_PERIPH_MPU_CFG>;
+                       label = "slv-pcnoc-mpu-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PERIPH_MPU_CFG>;
+               };
+
+               slv_gcnt:slv-gcnt {
+                       cell-id = <MSM_BUS_SLAVE_GCNT>;
+                       label = "slv-gcnt";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_GCNT>;
+               };
+
+               slv_qdss_cfg:slv-qdss-cfg {
+                       cell-id = <MSM_BUS_SLAVE_QDSS_CFG>;
+                       label = "slv-qdss-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_CFG>;
+               };
+
+               slv_snoc_cfg:slv-snoc-cfg {
+                       cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
+                       label = "slv-snoc-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CFG>;
+               };
+
+               slv_snoc_mpu_cfg:slv-snoc-mpu-cfg {
+                       cell-id = <MSM_BUS_SLAVE_SNOC_MPU_CFG>;
+                       label = "slv-snoc-mpu-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_MPU_CFG>;
+               };
+
+               slv_adss_cfg:slv-adss-cfg {
+                       cell-id = <MSM_BUS_SLAVE_ADSS_CFG>;
+                       label = "slv-adss-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_ADSS_CFG>;
+               };
+
+               slv_adss_apu:slv-adss-apu {
+                       cell-id = <MSM_BUS_SLAVE_ADSS_VMIDMT_CFG>;
+                       label = "slv-adss-apu";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_ADSS_APU>;
+               };
+
+               slv_adss_vmidmt_cfg:slv-adss-vmidmt-cfg {
+                       cell-id = <MSM_BUS_SLAVE_ADSS_VMIDMT_CFG>;
+                       label = "slv-adss-vmidmt-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_ADSS_VMIDMT_CFG>;
+               };
+
+               slv_qhss_apu_cfg:slv-qhss-apu-cfg {
+                       cell-id = <MSM_BUS_SLAVE_QHSS_APU_CFG>;
+                       label = "slv-qhss-apu-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_QHSS_APU_CFG>;
+               };
+
+               slv_mdio:slv-mdio {
+                       cell-id = <MSM_BUS_SLAVE_MDIO>;
+                       label = "slv-mdio";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_MDIO>;
+               };
+
+               slv_fephy_cfg:slv-fephy-cfg {
+                       cell-id = <MSM_BUS_SLAVE_FEPHY_CFG>;
+                       label = "slv-fephy-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_FEPHY_CFG>;
+               };
+
+               slv_srif:slv-srif {
+                       cell-id = <MSM_BUS_SLAVE_SRIF>;
+                       label = "slv-srif";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SRIF>;
+               };
+
+               slv_ddrc_cfg:slv-ddrc-cfg {
+                       cell-id = <MSM_BUS_SLAVE_DDRC_CFG>;
+                       label = "slv-ddrc-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_CFG>;
+               };
+
+               slv_ddrc_apu_cfg:slv-ddrc-apu-cfg {
+                       cell-id = <MSM_BUS_SLAVE_DDRC_APU_CFG>;
+                       label = "slv-ddrc-apu-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_APU_CFG>;
+               };
+
+               slv_ddrc_mpu0_cfg:slv-ddrc-mpu0-cfg {
+                       cell-id = <MSM_BUS_SLAVE_MPU0_CFG>;
+                       label = "slv-ddrc-mpu0-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_MPU0_CFG>;
+               };
+
+               slv_ddrc_mpu1_cfg:slv-ddrc-mpu1-cfg {
+                       cell-id = <MSM_BUS_SLAVE_MPU1_CFG>;
+                       label = "slv-ddrc-mpu1-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_MPU1_CFG>;
+               };
+
+               slv_ddrc_mpu2_cfg:slv-ddrc-mpu2-cfg {
+                       cell-id = <MSM_BUS_SLAVE_MPU2_CFG>;
+                       label = "slv-ddrc-mpu2-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_MPU2_CFG>;
+               };
+
+               slv_ess_vmidmt_cfg:slv-ess-vmidmt-cfg {
+                       cell-id = <MSM_BUS_SLAVE_ESS_VMIDMT_CFG>;
+                       label = "slv-ess-vmidmt-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_ESS_VMIDMT_CFG>;
+               };
+
+               slv_ess_apu_cfg:slv-ess-apu-cfg {
+                       cell-id = <MSM_BUS_SLAVE_ESS_APU_CFG>;
+                       label = "slv-ess-apu-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_ESS_APU_CFG>;
+               };
+
+               slv_usb2_cfg:slv-usb2-cfg {
+                       cell-id = <MSM_BUS_SLAVE_USB2_CFG>;
+                       label = "slv-usb2-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_USB2_CFG>;
+               };
+
+               slv_blsp_cfg:slv-blsp-cfg {
+                       cell-id = <MSM_BUS_SLAVE_BLSP_CFG>;
+                       label = "slv-blsp-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_CFG>;
+               };
+
+               slv_qpic_cfg:slv-qpic-cfg {
+                       cell-id = <MSM_BUS_SLAVE_QPIC_CFG>;
+                       label = "slv-qpic-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_QPIC_CFG>;
+               };
+
+               slv_sdcc_cfg:slv-sdcc-cfg {
+                       cell-id = <MSM_BUS_SLAVE_SDCC_CFG>;
+                       label = "slv-sdcc-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_CFG>;
+               };
+
+               slv_wss0_vmidmt_cfg:slv-wss0-vmidmt-cfg {
+                       cell-id = <MSM_BUS_SLAVE_WSS0_VMIDMT_CFG>;
+                       label = "slv-wss0-vmidmt-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS0_VMIDMT_CFG>;
+               };
+
+               slv_wss0_apu_cfg:slv-wss0-apu-cfg {
+                       cell-id = <MSM_BUS_SLAVE_WSS0_APU_CFG>;
+                       label = "slv-wss0-apu-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS0_APU_CFG>;
+               };
+
+               slv_wss1_vmidmt_cfg:slv-wss1-vmidmt-cfg {
+                       cell-id = <MSM_BUS_SLAVE_WSS1_VMIDMT_CFG>;
+                       label = "slv-wss1-vmidmt-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS1_VMIDMT_CFG>;
+               };
+
+               slv_wss1_apu_cfg:slv-wss1-apu-cfg {
+                       cell-id = <MSM_BUS_SLAVE_WSS1_APU_CFG>;
+                       label = "slv-wss1-apu-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS1_APU_CFG>;
+               };
+
+               slv_pcnoc_snoc:slv-pcnoc-snoc {
+                       cell-id = <MSM_BUS_PNOC_SNOC_SLV>;
+                       label = "slv-pcnoc-snoc";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_SNOC>;
+               };
+
+               slv_srvc_pcnoc:slv-srvc-pcnoc {
+                       cell-id = <MSM_BUS_SLAVE_SRVC_PCNOC>;
+                       label = "slv-srvc-pcnoc";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_pcnoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SRVC_PCNOC>;
+               };
+
+               slv_snoc_ddrc_m1:slv-snoc-ddrc-m1 {
+                       cell-id = <MSM_BUS_SLAVE_SNOC_DDRC>;
+                       label = "slv-snoc-ddrc-m1";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_DDRC>;
+               };
+
+               slv_a7ss:slv-a7ss {
+                       cell-id = <MSM_BUS_SLAVE_A7SS>;
+                       label = "slv-a7ss";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_A7SS>;
+               };
+
+               slv_ocimem:slv-ocimem {
+                       cell-id = <MSM_BUS_SLAVE_OCIMEM>;
+                       label = "slv-ocimem";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_OCIMEM>;
+               };
+
+               slv_wss0_cfg:slv-wss0-cfg {
+                       cell-id = <MSM_BUS_SLAVE_WSS0_CFG>;
+                       label = "slv-wss0-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS0_CFG>;
+               };
+
+               slv_wss1_cfg:slv-wss1-cfg {
+                       cell-id = <MSM_BUS_SLAVE_WSS1_CFG>;
+                       label = "slv-wss1-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_WSS1_CFG>;
+               };
+
+               slv_pcie:slv-pcie {
+                       cell-id = <MSM_BUS_SLAVE_PCIE>;
+                       label = "slv-pcie";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_PCIE>;
+               };
+
+               slv_usb3_cfg:slv-usb3-cfg {
+                       cell-id = <MSM_BUS_SLAVE_USB3_CFG>;
+                       label = "slv-usb3-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_USB3_CFG>;
+               };
+
+               slv_crypto_cfg:slv-crypto-cfg {
+                       cell-id = <MSM_BUS_SLAVE_CRYPTO_CFG>;
+                       label = "slv-crypto-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_CRYPTO_CFG>;
+               };
+
+               slv_ess_cfg:slv-ess-cfg {
+                       cell-id = <MSM_BUS_SLAVE_ESS_CFG>;
+                       label = "slv-ess-cfg";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_ESS_CFG>;
+               };
+
+               slv_qdss_stm:slv-qdss-stm {
+                       cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
+                       label = "slv-qdss-stm";
+                       qcom,buswidth = <4>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>;
+               };
+
+               slv_srvc_snoc:slv-srvc-snoc {
+                       cell-id = <MSM_BUS_SLAVE_SRVC_SNOC>;
+                       label = "slv-srvc-snoc";
+                       qcom,buswidth = <8>;
+                       qcom,ap-owned;
+                       qcom,bus-dev = <&fab_snoc>;
+                       qcom,slv-rpm-id = <ICBID_SLAVE_SRVC_SNOC>;
+               };
+       };
+};
+
+};
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-fritz4040.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-fritz4040.dts
new file mode 100644 (file)
index 0000000..fdd565c
--- /dev/null
@@ -0,0 +1,293 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019-ap.dk01.1.dtsi"
+#include "qcom-ipq4019-bus.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+       model = "AVM FRITZ!Box 4040";
+       compatible = "avm,fritzbox-4040", "qcom,ipq4019";
+
+       reserved-memory {
+               #address-cells = <0x1>;
+               #size-cells = <0x1>;
+               ranges;
+
+               rsvd1@87000000 {
+                       reg = <0x87000000 0x500000>;
+                       no-map;
+               };
+
+               wifi_dump@87500000 {
+                       reg = <0x87500000 0x600000>;
+                       no-map;
+               };
+
+               rsvd2@87B00000 {
+                       reg = <0x87b00000 0x500000>;
+                       no-map;
+               };
+       };
+/*
+       This also works. Maybe it could be smaller still.
+
+       reserved-memory {
+               #address-cells = <0x1>;
+               #size-cells = <0x1>;
+               ranges;
+
+               rsvd1@87E00000 {
+                       reg = <0x87e00000 0x200000>;
+                       no-map;
+               };
+       };
+*/
+
+       soc {
+               tcsr@194b000 {
+                       /* select hostmode */
+                       compatible = "qcom,tcsr";
+                       reg = <0x194b000 0x100>;
+                       qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+                       status = "ok";
+               };
+
+               ess_tcsr@1953000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1953000 0x1000>;
+                       qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+               };
+
+
+               tcsr@1949000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1949000 0x100>;
+                       qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+               };
+
+               tcsr@1957000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1957000 0x100>;
+                       qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+               };
+
+               counter@4a1000 {
+                       compatible = "qcom,qca-gcnt";
+                       reg = <0x4a1000 0x4>;
+               };
+
+               mdio@90000 {
+                       status = "okay";
+               };
+
+               qca8075: ess-switch@c000000 {
+                       status = "okay";
+
+                       #gpio-cells = <2>;
+                       gpio-controller;
+
+                       enable-usb-power {
+                               gpio-hog;
+                               line-name = "enable USB3 power";
+                               gpios = <0x7 GPIO_ACTIVE_HIGH>;
+                               output-high;
+                       };
+               };
+
+               ess-psgmii@98000 {
+                       status = "okay";
+               };
+
+               edma@c080000 {
+                       status = "okay";
+               };
+
+               wifi@a000000 {
+                       status = "okay";
+               };
+
+               wifi@a800000 {
+                       status = "okay";
+               };
+
+               cryptobam: dma@8e04000 {
+                       status = "okay";
+               };
+
+               crypto@8e3a000 {
+                       status = "okay";
+               };
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+
+               wlan {
+                       label = "wlan";
+                       gpios = <&tlmm 0x3a GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_RFKILL>;
+               };
+
+               wps {
+                       label = "wps";
+                       gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_WPS_BUTTON>;
+               };
+       };
+
+       aliases {
+               led-boot = &power;
+               led-failsafe = &flash;
+               led-running = &power;
+               led-upgrade = &flash;
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+
+               wlan {
+                       label = "fritz4040:green:wlan";
+                       gpios = <&qca8075 0x1 GPIO_ACTIVE_HIGH>;
+               };
+
+               panic: info_red {
+                       label = "fritz4040:red:info";
+                       gpios = <&qca8075 0x3 GPIO_ACTIVE_HIGH>;
+                       panic-indicator;
+               };
+
+               wan {
+                       label = "fritz4040:green:wan";
+                       gpios = <&qca8075 0x5 GPIO_ACTIVE_HIGH>;
+               };
+
+               power: power {
+                       label = "fritz4040:green:power";
+                       gpios = <&qca8075 0xb GPIO_ACTIVE_HIGH>;
+               };
+
+               lan {
+                       label = "fritz4040:green:lan";
+                       gpios = <&qca8075 0xd GPIO_ACTIVE_HIGH>;
+               };
+
+               flash: info_amber {
+                       label = "fritz4040:amber:info";
+                       gpios = <&qca8075 0xf GPIO_ACTIVE_HIGH>;
+               };
+       };
+};
+
+&spi_0 { /* BLSP1 QUP1 */
+       status = "ok";
+
+       mx25l25635e@0 {
+               status = "disabled";
+       };
+
+       mx25l25635f@0 {
+               compatible = "mx25l25635f", "jedec,spi-nor";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0>;
+               spi-max-frequency = <24000000>;
+               status = "ok";
+               m25p,fast-read;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition0@0 {
+                               label = "SBL1";
+                               reg = <0x00000000 0x00040000>;
+                               read-only;
+                       };
+                       partition1@40000 {
+                               label = "MIBIB";
+                               reg = <0x00040000 0x00020000>;
+                               read-only;
+                       };
+                       partition2@60000 {
+                               label = "QSEE";
+                               reg = <0x00060000 0x00060000>;
+                               read-only;
+                       };
+                       partition3@c0000 {
+                               label = "CDT";
+                               reg = <0x000c0000 0x00010000>;
+                               read-only;
+                       };
+                       partition4@d0000 {
+                               label = "DDRPARAMS";
+                               reg = <0x000d0000 0x00010000>;
+                               read-only;
+                       };
+                       partition5@e0000 {
+                               label = "APPSBLENV"; /* uboot env - empty */
+                               reg = <0x000e0000 0x00010000>;
+                               read-only;
+                       };
+                       partition6@f0000 {
+                               label = "urlader"; /* APPSBL */
+                               reg = <0x000f0000 0x0002dc000>;
+                               read-only;
+                       };
+                       partition7@11dc00 {
+                               /* make a backup of this partition! */
+                               label = "urlader_config";
+                               reg = <0x0011dc00 0x00002400>;
+                               read-only;
+                       };
+                       partition8@120000 {
+                               label = "tffs1";
+                               reg = <0x00120000 0x00080000>;
+                               read-only;
+                       };
+                       partition9@1a0000 {
+                               label = "tffs2";
+                               reg = <0x001a0000 0x00080000>;
+                               read-only;
+                       };
+                       partition10@220000 {
+                               label = "uboot";
+                               reg = <0x00220000 0x00080000>;
+                               read-only;
+                       };
+                       partition11@2A0000 {
+                               label = "image"; /* firmware */
+                               reg = <0x002A0000 0x01C60000>;
+                       };
+                       partition12@1f00000 {
+                               label = "jffs2";
+                               reg = <0x01F00000 0x00100000>;
+                       };
+               };
+       };
+};
+
+&cpu0_opp_table {
+       /delete-node/ opp@666000000;
+
+       opp@710000000 {
+               opp-hz = /bits/ 64 <710000000>;
+               clock-latency-ns = <256000>;
+       };
+};
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-nbg6617.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-nbg6617.dts
new file mode 100644 (file)
index 0000000..b58f4db
--- /dev/null
@@ -0,0 +1,208 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019-ap.dk01.1.dtsi"
+#include "qcom-ipq4019-bus.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+       model = "ZyXEL NBG6617";
+       compatible = "zyxel,nbg6617", "qcom,ipq4019";
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x10000000>;
+       };
+
+       aliases {
+               led-boot = &power;
+               led-failsafe = &power;
+               led-running = &power;
+               led-upgrade = &power;
+       };
+
+       reserved-memory {
+               #address-cells = <0x1>;
+               #size-cells = <0x1>;
+               ranges;
+
+               rsvd1@87000000 {
+                       reg = <0x87000000 0x0500000>;
+                       no-map;
+               };
+
+               wifi_dump@87500000 {
+                       reg = <0x87500000 0x600000>;
+                       no-map;
+               };
+
+               rsvd2@87B00000 {
+                       reg = <0x87b00000 0x500000>;
+                       no-map;
+               };
+       };
+
+       soc {
+               pinctrl@0x01000000 {
+                       led_pinmux {
+                               mux {
+                                       pins = "gpio0", "gpio1", "gpio3", "gpio5", "gpio58";
+                                       drive-strength = <0x8>;
+                                       bias-pull-up;
+                                       output-high;
+                               };
+                       };
+               };
+
+               tcsr@194b000 {
+                       /* select hostmode */
+                       compatible = "qcom,tcsr";
+                       reg = <0x194b000 0x100>;
+                       qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+                       status = "ok";
+               };
+
+               ess_tcsr@1953000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1953000 0x1000>;
+                       qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+               };
+
+
+               tcsr@1949000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1949000 0x100>;
+                       qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+               };
+
+               tcsr@1957000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1957000 0x100>;
+                       qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+               };
+
+               counter@4a1000 {
+                       compatible = "qcom,qca-gcnt";
+                       reg = <0x4a1000 0x4>;
+               };
+
+               mdio@90000 {
+                       status = "okay";
+               };
+
+               ess-switch@c000000 {
+                       status = "okay";
+               };
+
+               ess-psgmii@98000 {
+                       status = "okay";
+               };
+
+               edma@c080000 {
+                       status = "okay";
+               };
+
+               wifi@a000000 {
+                       status = "okay";
+               };
+
+               wifi@a800000 {
+                       status = "okay";
+               };
+
+               cryptobam: dma@8e04000 {
+                       status = "okay";
+               };
+
+               crypto@8e3a000 {
+                       status = "okay";
+               };
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+
+               wlan {
+                       label = "wlan";
+                       gpios = <&tlmm 0x2 GPIO_ACTIVE_HIGH>;
+                       linux,code = <KEY_RFKILL>;
+               };
+
+               wps {
+                       label = "wps";
+                       gpios = <&tlmm 0x3f GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_WPS_BUTTON>;
+               };
+
+               reset {
+                       label = "reset";
+                       gpios = <&tlmm 0x4 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_RESTART>;
+               };
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+
+               power: power {
+                       label = "nbg6617:green:power";
+                       gpios = <&tlmm 0x3 GPIO_ACTIVE_HIGH>;
+               };
+
+               wps {
+                       label = "nbg6617:green:wps";
+                       gpios = <&tlmm 0x1 GPIO_ACTIVE_HIGH>;
+               };
+
+               wlan2G {
+                       label = "nbg6617:green:wlan2G";
+                       gpios = <&tlmm 0x3a GPIO_ACTIVE_HIGH>;
+               };
+
+               wlan5G {
+                       label = "nbg6617:green:wlan5G";
+                       gpios = <&tlmm 0x5 GPIO_ACTIVE_HIGH>;
+               };
+       };
+};
+
+
+&spi_0 { /* BLSP1 QUP1 */
+       status = "ok";
+
+       mx25l25635e@0 {
+               status = "disabled";
+       };
+
+       n25q128a11@0 {
+               status = "okay";
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition0@0 {
+                               label = "all";
+                               reg = <0x00000000 0x08000000>;
+                               read-only; /* for now */
+                       };
+               };
+
+       };
+};
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-rt-ac58u.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-rt-ac58u.dts
new file mode 100644 (file)
index 0000000..e11868d
--- /dev/null
@@ -0,0 +1,271 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019-ap.dk01.1.dtsi"
+#include "qcom-ipq4019-bus.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+       model = "ASUS RT-AC58U";
+       compatible = "asus,rt-ac58u", "qcom,ipq4019";
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x8000000>;
+       };
+
+       aliases {
+               led-boot = &power;
+               led-failsafe = &power;
+               led-running = &power;
+               led-upgrade = &power;
+       };
+
+       reserved-memory {
+               #address-cells = <0x1>;
+               #size-cells = <0x1>;
+               ranges;
+
+               rsvd1@87E00000 {
+                       reg = <0x87e00000 0x200000>;
+                       no-map;
+               };
+       };
+
+       soc {
+
+               tcsr@194b000 {
+                       /* select hostmode */
+                       compatible = "qcom,tcsr";
+                       reg = <0x194b000 0x100>;
+                       qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+                       status = "ok";
+               };
+
+               ess_tcsr@1953000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1953000 0x1000>;
+                       qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+               };
+
+
+               tcsr@1949000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1949000 0x100>;
+                       qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+               };
+
+               tcsr@1957000 {
+                       compatible = "qcom,tcsr";
+                       reg = <0x1957000 0x100>;
+                       qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+               };
+
+               counter@4a1000 {
+                       compatible = "qcom,qca-gcnt";
+                       reg = <0x4a1000 0x4>;
+               };
+
+               mdio@90000 {
+                       status = "okay";
+               };
+
+               ess-switch@c000000 {
+                       status = "okay";
+               };
+
+               ess-psgmii@98000 {
+                       status = "okay";
+               };
+
+               edma@c080000 {
+                       status = "okay";
+               };
+
+               wifi@a000000 {
+                       status = "okay";
+               };
+
+               wifi@a800000 {
+                       status = "okay";
+               };
+
+               cryptobam: dma@8e04000 {
+                       status = "okay";
+               };
+
+               crypto@8e3a000 {
+                       status = "okay";
+               };
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+
+               reset {
+                       label = "reset";
+                       gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_RESTART>;
+               };
+
+               wps {
+                       label = "wps";
+                       gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_WPS_BUTTON>;
+               };
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+
+               power: status {
+                       label = "rt-ac58u:blue:status";
+                       gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+               };
+
+               wan {
+                       label = "rt-ac58u:blue:wan";
+                       gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
+               };
+
+               wlan2G {
+                       label = "rt-ac58u:blue:wlan2G";
+                       gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
+               };
+
+               wan5G {
+                       label = "rt-ac58u:blue:wlan5G";
+                       gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+               };
+
+               usb {
+                       label = "rt-ac58u:blue:usb";
+                       gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+               };
+
+               lan {
+                       label = "rt-ac58u:blue:lan";
+                       gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+               };
+       };
+};
+
+&spi_0_pins {
+       pinmux_cs {
+               function = "gpio";
+               pins = "gpio54", "gpio59";
+       };
+       pinconf_cs {
+               pins = "gpio54", "gpio59";
+               drive-strength = <2>;
+               bias-disable;
+               output-high;
+       };
+};
+
+
+&spi_0 { /* BLSP1 QUP1 */
+       status = "ok";
+       cs-gpios = <&tlmm 54 0>,
+                  <&tlmm 59 0>;
+
+       mx25l25635e@0 {
+               status = "disabled";
+       };
+
+       m25p80@0 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               /*
+                * U-boot looks for "n25q128a11" node,
+                * if we don't have it, it will spit out the following warning:
+                * "ipq: fdt fixup unable to find compatible node".
+                */
+               compatible = "mx25l1606e", "n25q128a11";
+               reg = <0>;
+               linux,modalias = "m25p80", "mx25l1606e", "n25q128a11";
+               spi-max-frequency = <24000000>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition0@0 {
+                               label = "SBL1";
+                               reg = <0x00000000 0x00040000>;
+                               read-only;
+                       };
+                       partition1@40000 {
+                               label = "MIBIB";
+                               reg = <0x00040000 0x00020000>;
+                               read-only;
+                       };
+                       partition2@60000 {
+                               label = "QSEE";
+                               reg = <0x00060000 0x00060000>;
+                               read-only;
+                       };
+                       partition3@c0000 {
+                               label = "CDT";
+                               reg = <0x000c0000 0x00010000>;
+                               read-only;
+                       };
+                       partition4@d0000 {
+                               label = "DDRPARAMS";
+                               reg = <0x000d0000 0x00010000>;
+                               read-only;
+                       };
+                       partition5@e0000 {
+                               label = "APPSBLENV"; /* uboot env*/
+                               reg = <0x000e0000 0x00010000>;
+                               read-only;
+                       };
+                       partition5@f0000 {
+                               label = "APPSBL"; /* uboot */
+                               reg = <0x000f0000 0x00080000>;
+                               read-only;
+                       };
+                       partition5@170000 {
+                               label = "ART";
+                               reg = <0x00170000 0x00010000>;
+                               read-only;
+                       };
+                       /* 0x00180000 - 0x00200000 unused */
+               };
+       };
+
+       mt29f@1 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "spinand,mt29f", "w25n01gv";
+               reg = <1>;
+               spi-max-frequency = <24000000>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition0@0 {
+                               label = "ubi";
+                               reg = <0x00000000 0x08000000>;
+                       };
+               };
+       };
+};
diff --git a/target/linux/ipq806x/patches-4.9/0021-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch b/target/linux/ipq806x/patches-4.9/0021-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch
deleted file mode 100644 (file)
index 887ebf3..0000000
+++ /dev/null
@@ -1,108 +0,0 @@
-From 644ad7209637b02a0ca6d72f0715a9f52532fc70 Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Fri, 8 Apr 2016 15:26:10 -0500
-Subject: [PATCH 21/69] qcom: ipq4019: use v2 of the kpss bringup mechanism
-
-v1 was the incorrect choice here and sometimes the board would not come
-up properly
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 32 ++++++++++++++++++++++++--------
- 1 file changed, 24 insertions(+), 8 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -34,7 +34,8 @@
-               cpu@0 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a7";
--                      enable-method = "qcom,kpss-acc-v1";
-+                      enable-method = "qcom,kpss-acc-v2";
-+                      next-level-cache = <&L2>;
-                       qcom,acc = <&acc0>;
-                       qcom,saw = <&saw0>;
-                       reg = <0x0>;
-@@ -46,7 +47,8 @@
-               cpu@1 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a7";
--                      enable-method = "qcom,kpss-acc-v1";
-+                      enable-method = "qcom,kpss-acc-v2";
-+                      next-level-cache = <&L2>;
-                       qcom,acc = <&acc1>;
-                       qcom,saw = <&saw1>;
-                       reg = <0x1>;
-@@ -58,7 +60,8 @@
-               cpu@2 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a7";
--                      enable-method = "qcom,kpss-acc-v1";
-+                      enable-method = "qcom,kpss-acc-v2";
-+                      next-level-cache = <&L2>;
-                       qcom,acc = <&acc2>;
-                       qcom,saw = <&saw2>;
-                       reg = <0x2>;
-@@ -70,7 +73,8 @@
-               cpu@3 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a7";
--                      enable-method = "qcom,kpss-acc-v1";
-+                      enable-method = "qcom,kpss-acc-v2";
-+                      next-level-cache = <&L2>;
-                       qcom,acc = <&acc3>;
-                       qcom,saw = <&saw3>;
-                       reg = <0x3>;
-@@ -100,6 +104,12 @@
-                       opp-hz = /bits/ 64 <666000000>;
-                       clock-latency-ns = <256000>;
-               };
-+
-+              L2: l2-cache {
-+                      compatible = "qcom,arch-cache";
-+                      cache-level = <2>;
-+                      qcom,saw = <&saw_l2>;
-+              };
-       };
-       pmu {
-@@ -212,22 +222,22 @@
-               };
-                 acc0: clock-controller@b088000 {
--                        compatible = "qcom,kpss-acc-v1";
-+                        compatible = "qcom,kpss-acc-v2";
-                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
-                 };
-                 acc1: clock-controller@b098000 {
--                        compatible = "qcom,kpss-acc-v1";
-+                        compatible = "qcom,kpss-acc-v2";
-                         reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
-                 };
-                 acc2: clock-controller@b0a8000 {
--                        compatible = "qcom,kpss-acc-v1";
-+                        compatible = "qcom,kpss-acc-v2";
-                         reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
-                 };
-                 acc3: clock-controller@b0b8000 {
--                        compatible = "qcom,kpss-acc-v1";
-+                        compatible = "qcom,kpss-acc-v2";
-                         reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
-                 };
-@@ -255,6 +265,12 @@
-                         regulator;
-                 };
-+              saw_l2: regulator@b012000 {
-+                      compatible = "qcom,saw2";
-+                      reg = <0xb012000 0x1000>;
-+                      regulator;
-+              };
-+
-               serial@78af000 {
-                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-                       reg = <0x78af000 0x200>;
index e5dbba7..c427d66 100644 (file)
@@ -13,7 +13,7 @@ Signed-off-by: Matthew McClintock <mmcclint@qca.qualcomm.com>
 
 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -118,6 +118,12 @@
+@@ -108,6 +108,12 @@
                                         IRQ_TYPE_LEVEL_HIGH)>;
        };
  
diff --git a/target/linux/ipq806x/patches-4.9/0023-qcom-ipq4019-Add-IPQ4019-USB-HS-SS-PHY-drivers.patch b/target/linux/ipq806x/patches-4.9/0023-qcom-ipq4019-Add-IPQ4019-USB-HS-SS-PHY-drivers.patch
deleted file mode 100644 (file)
index e8f4bfc..0000000
+++ /dev/null
@@ -1,488 +0,0 @@
-From 04d3f9be0ce80fac99d4ca1f46faf3605258ca1f Mon Sep 17 00:00:00 2001
-From: Senthilkumar N L <snlakshm@codeaurora.org>
-Date: Tue, 6 Jan 2015 12:52:23 +0530
-Subject: [PATCH 23/69] qcom: ipq4019: Add IPQ4019 USB HS/SS PHY drivers
-
-These drivers handles control and configuration of the HS
-and SS USB PHY transceivers.
-
-Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
----
- drivers/usb/phy/Kconfig          |  11 ++
- drivers/usb/phy/Makefile         |   2 +
- drivers/usb/phy/phy-qca-baldur.c | 262 +++++++++++++++++++++++++++++++++++++++
- drivers/usb/phy/phy-qca-uniphy.c | 171 +++++++++++++++++++++++++
- 4 files changed, 446 insertions(+)
- create mode 100644 drivers/usb/phy/phy-qca-baldur.c
- create mode 100644 drivers/usb/phy/phy-qca-uniphy.c
-
---- a/drivers/usb/phy/Kconfig
-+++ b/drivers/usb/phy/Kconfig
-@@ -194,6 +194,17 @@ config USB_MXS_PHY
-         MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
-+config USB_IPQ4019_PHY
-+      tristate "IPQ4019 PHY wrappers support"
-+      depends on (USB || USB_GADGET) && ARCH_QCOM
-+      select USB_PHY
-+      help
-+        Enable this to support the USB PHY transceivers on QCA961x chips.
-+        It handles PHY initialization, clock management required after
-+        resetting the hardware and power management.
-+        This driver is required even for peripheral only or host only
-+        mode configurations.
-+
- config USB_ULPI
-       bool "Generic ULPI Transceiver Driver"
-       depends on ARM || ARM64
---- a/drivers/usb/phy/Makefile
-+++ b/drivers/usb/phy/Makefile
-@@ -21,6 +21,8 @@ obj-$(CONFIG_USB_GPIO_VBUS)          += phy-gpio
- obj-$(CONFIG_USB_ISP1301)             += phy-isp1301.o
- obj-$(CONFIG_USB_MSM_OTG)             += phy-msm-usb.o
- obj-$(CONFIG_USB_QCOM_8X16_PHY)       += phy-qcom-8x16-usb.o
-+obj-$(CONFIG_USB_IPQ4019_PHY)           += phy-qca-baldur.o
-+obj-$(CONFIG_USB_IPQ4019_PHY)           += phy-qca-uniphy.o
- obj-$(CONFIG_USB_MV_OTG)              += phy-mv-usb.o
- obj-$(CONFIG_USB_MXS_PHY)             += phy-mxs-usb.o
- obj-$(CONFIG_USB_ULPI)                        += phy-ulpi.o
---- /dev/null
-+++ b/drivers/usb/phy/phy-qca-baldur.c
-@@ -0,0 +1,262 @@
-+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for any
-+ * purpose with or without fee is hereby granted, provided that the above
-+ * copyright notice and this permission notice appear in all copies.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ *
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/usb/phy.h>
-+#include <linux/reset.h>
-+#include <linux/of_device.h>
-+
-+/**
-+ *  USB Hardware registers
-+ */
-+#define PHY_CTRL0_ADDR        0x000
-+#define PHY_CTRL1_ADDR        0x004
-+#define PHY_CTRL2_ADDR        0x008
-+#define PHY_CTRL3_ADDR        0x00C
-+#define PHY_CTRL4_ADDR        0x010
-+#define PHY_MISC_ADDR 0x024
-+#define PHY_IPG_ADDR  0x030
-+
-+#define PHY_CTRL0_EMU_ADDR    0x180
-+#define PHY_CTRL1_EMU_ADDR    0x184
-+#define PHY_CTRL2_EMU_ADDR    0x188
-+#define PHY_CTRL3_EMU_ADDR    0x18C
-+#define PHY_CTRL4_EMU_ADDR    0x190
-+#define PHY_MISC_EMU_ADDR     0x1A4
-+#define PHY_IPG_EMU_ADDR      0x1B0
-+
-+#define PHY_CTRL0_VAL 0xA4600015
-+#define PHY_CTRL1_VAL 0x09500000
-+#define PHY_CTRL2_VAL 0x00058180
-+#define PHY_CTRL3_VAL 0x6DB6DCD6
-+#define PHY_CTRL4_VAL 0x836DB6DB
-+#define PHY_MISC_VAL  0x3803FB0C
-+#define PHY_IPG_VAL           0x47323232
-+
-+#define PHY_CTRL0_EMU_VAL     0xb4000015
-+#define PHY_CTRL1_EMU_VAL     0x09500000
-+#define PHY_CTRL2_EMU_VAL     0x00058180
-+#define PHY_CTRL3_EMU_VAL     0x6DB6DCD6
-+#define PHY_CTRL4_EMU_VAL     0x836DB6DB
-+#define PHY_MISC_EMU_VAL      0x3803FB0C
-+#define PHY_IPG_EMU_VAL               0x47323232
-+
-+#define USB30_HS_PHY_HOST_MODE        (0x01 << 21)
-+#define USB20_HS_PHY_HOST_MODE        (0x01 << 5)
-+
-+/* used to differentiate between USB3 HS and USB2 HS PHY */
-+struct qca_baldur_hs_data {
-+      unsigned int usb3_hs_phy;
-+      unsigned int phy_config_offset;
-+};
-+
-+struct qca_baldur_hs_phy {
-+      struct device *dev;
-+      struct usb_phy phy;
-+
-+      void __iomem *base;
-+      void __iomem *qscratch_base;
-+
-+      struct reset_control *por_rst;
-+      struct reset_control *srif_rst;
-+
-+      unsigned int host;
-+      unsigned int emulation;
-+      const struct qca_baldur_hs_data *data;
-+};
-+
-+#define       phy_to_dw_phy(x)        container_of((x), struct qca_baldur_hs_phy, phy)
-+
-+static int qca_baldur_phy_read(struct usb_phy *x, u32 reg)
-+{
-+      struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
-+
-+      return readl(phy->base + reg);
-+}
-+
-+static int qca_baldur_phy_write(struct usb_phy *x, u32 val, u32 reg)
-+{
-+      struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
-+
-+      writel(val, phy->base + reg);
-+      return 0;
-+}
-+
-+static int qca_baldur_hs_phy_init(struct usb_phy *x)
-+{
-+      struct qca_baldur_hs_phy        *phy = phy_to_dw_phy(x);
-+
-+      /* assert HS PHY POR reset */
-+      reset_control_assert(phy->por_rst);
-+      msleep(10);
-+
-+      /* assert HS PHY SRIF reset */
-+      reset_control_assert(phy->srif_rst);
-+      msleep(10);
-+
-+      /* deassert HS PHY SRIF reset and program HS PHY registers */
-+      reset_control_deassert(phy->srif_rst);
-+      msleep(10);
-+
-+      if (!phy->emulation) {
-+              /* perform PHY register writes */
-+              writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
-+              writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
-+              writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR);
-+              writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR);
-+              writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
-+              writel(PHY_MISC_VAL, phy->base + PHY_MISC_ADDR);
-+              writel(PHY_IPG_VAL, phy->base + PHY_IPG_ADDR);
-+      } else {
-+              /* perform PHY register writes */
-+              writel(PHY_CTRL0_EMU_VAL, phy->base + PHY_CTRL0_EMU_ADDR);
-+              writel(PHY_CTRL1_EMU_VAL, phy->base + PHY_CTRL1_EMU_ADDR);
-+              writel(PHY_CTRL2_EMU_VAL, phy->base + PHY_CTRL2_EMU_ADDR);
-+              writel(PHY_CTRL3_EMU_VAL, phy->base + PHY_CTRL3_EMU_ADDR);
-+              writel(PHY_CTRL4_EMU_VAL, phy->base + PHY_CTRL4_EMU_ADDR);
-+              writel(PHY_MISC_EMU_VAL, phy->base + PHY_MISC_EMU_ADDR);
-+              writel(PHY_IPG_EMU_VAL, phy->base + PHY_IPG_EMU_ADDR);
-+      }
-+
-+      msleep(10);
-+
-+      /* de-assert USB3 HS PHY POR reset */
-+      reset_control_deassert(phy->por_rst);
-+
-+      return 0;
-+}
-+
-+static int qca_baldur_hs_get_resources(struct qca_baldur_hs_phy *phy)
-+{
-+      struct platform_device *pdev = to_platform_device(phy->dev);
-+      struct resource *res;
-+
-+      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+      phy->base = devm_ioremap_resource(phy->dev, res);
-+      if (IS_ERR(phy->base))
-+              return PTR_ERR(phy->base);
-+
-+      phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
-+      if (IS_ERR(phy->por_rst))
-+              return PTR_ERR(phy->por_rst);
-+
-+      phy->srif_rst = devm_reset_control_get(phy->dev, "srif_rst");
-+      if (IS_ERR(phy->srif_rst))
-+              return PTR_ERR(phy->srif_rst);
-+
-+      return 0;
-+}
-+
-+static void qca_baldur_hs_put_resources(struct qca_baldur_hs_phy *phy)
-+{
-+      reset_control_assert(phy->srif_rst);
-+      reset_control_assert(phy->por_rst);
-+}
-+
-+static int qca_baldur_hs_remove(struct platform_device *pdev)
-+{
-+      struct qca_baldur_hs_phy *phy = platform_get_drvdata(pdev);
-+
-+      usb_remove_phy(&phy->phy);
-+      return 0;
-+}
-+
-+static void qca_baldur_hs_phy_shutdown(struct usb_phy *x)
-+{
-+      struct qca_baldur_hs_phy   *phy = phy_to_dw_phy(x);
-+
-+      qca_baldur_hs_put_resources(phy);
-+}
-+
-+static struct usb_phy_io_ops qca_baldur_io_ops = {
-+      .read = qca_baldur_phy_read,
-+      .write = qca_baldur_phy_write,
-+};
-+
-+static const struct qca_baldur_hs_data usb3_hs_data = {
-+      .usb3_hs_phy = 1,
-+      .phy_config_offset = USB30_HS_PHY_HOST_MODE,
-+};
-+
-+static const struct qca_baldur_hs_data usb2_hs_data = {
-+      .usb3_hs_phy = 0,
-+      .phy_config_offset = USB20_HS_PHY_HOST_MODE,
-+};
-+
-+static const struct of_device_id qca_baldur_hs_id_table[] = {
-+      { .compatible = "qca,baldur-usb3-hsphy", .data = &usb3_hs_data },
-+      { .compatible = "qca,baldur-usb2-hsphy", .data = &usb2_hs_data },
-+      { /* Sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, qca_baldur_hs_id_table);
-+
-+static int qca_baldur_hs_probe(struct platform_device *pdev)
-+{
-+      const struct of_device_id *match;
-+      struct qca_baldur_hs_phy *phy;
-+      int err;
-+
-+      match = of_match_device(qca_baldur_hs_id_table, &pdev->dev);
-+      if (!match)
-+              return -ENODEV;
-+
-+      phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
-+      if (!phy)
-+              return -ENOMEM;
-+
-+      platform_set_drvdata(pdev, phy);
-+      phy->dev = &pdev->dev;
-+
-+      phy->data = match->data;
-+
-+      err = qca_baldur_hs_get_resources(phy);
-+      if (err < 0) {
-+              dev_err(&pdev->dev, "failed to request resources: %d\n", err);
-+              return err;
-+      }
-+
-+      phy->phy.dev            = phy->dev;
-+      phy->phy.label          = "qca-baldur-hsphy";
-+      phy->phy.init           = qca_baldur_hs_phy_init;
-+      phy->phy.shutdown       = qca_baldur_hs_phy_shutdown;
-+      phy->phy.type           = USB_PHY_TYPE_USB2;
-+      phy->phy.io_ops         = &qca_baldur_io_ops;
-+
-+      err = usb_add_phy_dev(&phy->phy);
-+      return err;
-+}
-+
-+static struct platform_driver qca_baldur_hs_driver = {
-+      .probe          = qca_baldur_hs_probe,
-+      .remove         = qca_baldur_hs_remove,
-+      .driver         = {
-+              .name   = "qca-baldur-hsphy",
-+              .owner  = THIS_MODULE,
-+              .of_match_table = qca_baldur_hs_id_table,
-+      },
-+};
-+
-+module_platform_driver(qca_baldur_hs_driver);
-+
-+MODULE_ALIAS("platform:qca-baldur-hsphy");
-+MODULE_LICENSE("Dual BSD/GPL");
-+MODULE_DESCRIPTION("USB3 QCA BALDUR HSPHY driver");
---- /dev/null
-+++ b/drivers/usb/phy/phy-qca-uniphy.c
-@@ -0,0 +1,171 @@
-+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for any
-+ * purpose with or without fee is hereby granted, provided that the above
-+ * copyright notice and this permission notice appear in all copies.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ *
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/usb/phy.h>
-+#include <linux/reset.h>
-+#include <linux/of_device.h>
-+
-+struct qca_uni_ss_phy {
-+      struct usb_phy phy;
-+      struct device *dev;
-+
-+      void __iomem *base;
-+
-+      struct reset_control *por_rst;
-+
-+      unsigned int host;
-+};
-+
-+#define       phy_to_dw_phy(x)        container_of((x), struct qca_uni_ss_phy, phy)
-+
-+/**
-+ * Write register
-+ *
-+ * @base - PHY base virtual address.
-+ * @offset - register offset.
-+ */
-+static u32 qca_uni_ss_read(void __iomem *base, u32 offset)
-+{
-+      u32 value;
-+      value = readl_relaxed(base + offset);
-+      return value;
-+}
-+
-+/**
-+ * Write register
-+ *
-+ * @base - PHY base virtual address.
-+ * @offset - register offset.
-+ * @val - value to write.
-+ */
-+static void qca_uni_ss_write(void __iomem *base, u32 offset, u32 val)
-+{
-+      writel(val, base + offset);
-+      udelay(100);
-+}
-+
-+static void qca_uni_ss_phy_shutdown(struct usb_phy *x)
-+{
-+      struct qca_uni_ss_phy *phy = phy_to_dw_phy(x);
-+
-+      /* assert SS PHY POR reset */
-+      reset_control_assert(phy->por_rst);
-+}
-+
-+static int qca_uni_ss_phy_init(struct usb_phy *x)
-+{
-+      struct qca_uni_ss_phy *phy = phy_to_dw_phy(x);
-+
-+      /* assert SS PHY POR reset */
-+      reset_control_assert(phy->por_rst);
-+
-+      msleep(10);
-+
-+      msleep(10);
-+
-+      /* deassert SS PHY POR reset */
-+      reset_control_deassert(phy->por_rst);
-+
-+      return 0;
-+}
-+
-+static int qca_uni_ss_get_resources(struct platform_device *pdev,
-+              struct qca_uni_ss_phy *phy)
-+{
-+      struct resource *res;
-+
-+      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+      phy->base = devm_ioremap_resource(phy->dev, res);
-+      if (IS_ERR(phy->base))
-+              return PTR_ERR(phy->base);
-+
-+      phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
-+      if (IS_ERR(phy->por_rst))
-+              return PTR_ERR(phy->por_rst);
-+
-+      return 0;
-+}
-+
-+static int qca_uni_ss_remove(struct platform_device *pdev)
-+{
-+      struct qca_uni_ss_phy *phy = platform_get_drvdata(pdev);
-+
-+      usb_remove_phy(&phy->phy);
-+      return 0;
-+}
-+
-+static const struct of_device_id qca_uni_ss_id_table[] = {
-+      { .compatible = "qca,uni-ssphy" },
-+      { /* Sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, qca_uni_ss_id_table);
-+
-+static int qca_uni_ss_probe(struct platform_device *pdev)
-+{
-+      const struct of_device_id *match;
-+      struct device_node *np = pdev->dev.of_node;
-+      struct qca_uni_ss_phy  *phy;
-+      int ret;
-+
-+      match = of_match_device(qca_uni_ss_id_table, &pdev->dev);
-+      if (!match)
-+              return -ENODEV;
-+
-+      phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
-+      if (!phy)
-+              return -ENOMEM;
-+
-+      platform_set_drvdata(pdev, phy);
-+      phy->dev = &pdev->dev;
-+
-+      ret = qca_uni_ss_get_resources(pdev, phy);
-+      if (ret < 0) {
-+              dev_err(&pdev->dev, "failed to request resources: %d\n", ret);
-+              return ret;
-+      }
-+
-+      phy->phy.dev        = phy->dev;
-+      phy->phy.label      = "qca-uni-ssphy";
-+      phy->phy.init       = qca_uni_ss_phy_init;
-+      phy->phy.shutdown   = qca_uni_ss_phy_shutdown;
-+      phy->phy.type       = USB_PHY_TYPE_USB3;
-+
-+      ret = usb_add_phy_dev(&phy->phy);
-+      return ret;
-+}
-+
-+static struct platform_driver qca_uni_ss_driver = {
-+      .probe          = qca_uni_ss_probe,
-+      .remove         = qca_uni_ss_remove,
-+      .driver         = {
-+              .name   = "qca-uni-ssphy",
-+              .owner  = THIS_MODULE,
-+              .of_match_table = qca_uni_ss_id_table,
-+      },
-+};
-+
-+module_platform_driver(qca_uni_ss_driver);
-+
-+MODULE_ALIAS("platform:qca-uni-ssphy");
-+MODULE_LICENSE("Dual BSD/GPL");
-+MODULE_DESCRIPTION("USB3 QCA UNI SSPHY driver");
diff --git a/target/linux/ipq806x/patches-4.9/0024-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch b/target/linux/ipq806x/patches-4.9/0024-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch
deleted file mode 100644 (file)
index cea6bd0..0000000
+++ /dev/null
@@ -1,87 +0,0 @@
-From 0fba6eceb6e16fa8fd5834d65fcb771fa263a44b Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Thu, 17 Mar 2016 16:22:28 -0500
-Subject: [PATCH 24/69] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree
-
-This adds the SoC nodes to the ipq4019 device tree
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 67 +++++++++++++++++++++++++++++++++++++
- 1 file changed, 67 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -313,5 +313,72 @@
-                       compatible = "qcom,pshold";
-                       reg = <0x4ab000 0x4>;
-               };
-+
-+                usb3_ss_phy: ssphy@9a000 {
-+                        compatible = "qca,uni-ssphy";
-+                        reg = <0x9a000 0x800>;
-+                        reg-names = "phy_base";
-+                        resets = <&gcc USB3_UNIPHY_PHY_ARES>;
-+                        reset-names = "por_rst";
-+                        status = "disabled";
-+                };
-+
-+                usb3_hs_phy: hsphy@a6000 {
-+                        compatible = "qca,baldur-usb3-hsphy";
-+                        reg = <0xa6000 0x40>;
-+                        reg-names = "phy_base";
-+                        resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
-+                        reset-names = "por_rst", "srif_rst";
-+                        status = "disabled";
-+                };
-+
-+              usb3@0 {
-+                        compatible = "qcom,dwc3";
-+                        #address-cells = <1>;
-+                        #size-cells = <1>;
-+                        clocks = <&gcc GCC_USB3_MASTER_CLK>;
-+                      clock-names = "core";
-+                        ranges;
-+                        status = "disabled";
-+
-+                        dwc3@8a00000 {
-+                                compatible = "snps,dwc3";
-+                                reg = <0x8a00000 0xf8000>;
-+                                interrupts = <0 132 0>;
-+                                usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
-+                                phy-names = "usb2-phy", "usb3-phy";
-+                                tx-fifo-resize;
-+                                dr_mode = "host";
-+                        };
-+                };
-+
-+                usb2_hs_phy: hsphy@a8000 {
-+                        compatible = "qca,baldur-usb2-hsphy";
-+                        reg = <0xa8000 0x40>;
-+                        reg-names = "phy_base";
-+                        resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
-+                        reset-names = "por_rst", "srif_rst";
-+                        status = "disabled";
-+                };
-+
-+                usb2@0 {
-+                        compatible = "qcom,dwc3";
-+                        #address-cells = <1>;
-+                        #size-cells = <1>;
-+                        clocks = <&gcc GCC_USB2_MASTER_CLK>;
-+                      clock-names = "core";
-+                        ranges;
-+                        status = "disabled";
-+
-+                        dwc3@6000000 {
-+                                compatible = "snps,dwc3";
-+                                reg = <0x6000000 0xf8000>;
-+                                interrupts = <0 136 0>;
-+                                usb-phy = <&usb2_hs_phy>;
-+                                phy-names = "usb2-phy";
-+                                tx-fifo-resize;
-+                                dr_mode = "host";
-+                        };
-+                };
-       };
- };
diff --git a/target/linux/ipq806x/patches-4.9/0025-qcom-ipq4019-enable-USB-bus-for-DK01.1-board.patch b/target/linux/ipq806x/patches-4.9/0025-qcom-ipq4019-enable-USB-bus-for-DK01.1-board.patch
deleted file mode 100644 (file)
index 975f42f..0000000
+++ /dev/null
@@ -1,45 +0,0 @@
-From ae5e11c926f710595d0080e51bd10e704776669d Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Mon, 21 Mar 2016 16:12:05 -0500
-Subject: [PATCH 25/69] qcom: ipq4019: enable USB bus for DK01.1 board
-
-This enables the USB block
-
-Change-Id: I384dd1874bba341713f384cf6199abd446e3f3c0
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
----
- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 24 ++++++++++++++++++++++++
- 1 file changed, 24 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-@@ -108,5 +108,29 @@
-               watchdog@b017000 {
-                       status = "ok";
-               };
-+
-+                usb3_ss_phy: ssphy@0 {
-+                        status = "ok";
-+                };
-+
-+                dummy_ss_phy: ssphy@1 {
-+                        status = "ok";
-+                };
-+
-+                usb3_hs_phy: hsphy@a6000 {
-+                        status = "ok";
-+                };
-+
-+                usb2_hs_phy: hsphy@a8000 {
-+                        status = "ok";
-+                };
-+
-+                usb3: usb3@8a00000 {
-+                        status = "ok";
-+                };
-+
-+                usb2: usb2@6000000 {
-+                        status = "ok";
-+                };
-       };
- };
index 32c52b0..de0ea8e 100644 (file)
@@ -32,40 +32,6 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
        qcom-ipq8064-ap148.dtb \
        qcom-msm8660-surf.dtb \
        qcom-msm8960-cdp.dtb \
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-@@ -109,11 +109,7 @@
-                       status = "ok";
-               };
--                usb3_ss_phy: ssphy@0 {
--                        status = "ok";
--                };
--
--                dummy_ss_phy: ssphy@1 {
-+                usb3_ss_phy: ssphy@9a000 {
-                         status = "ok";
-                 };
-@@ -121,15 +117,15 @@
-                         status = "ok";
-                 };
--                usb2_hs_phy: hsphy@a8000 {
-+                usb3@0 {
-                         status = "ok";
-                 };
--                usb3: usb3@8a00000 {
-+                usb2_hs_phy: hsphy@a8000 {
-                         status = "ok";
-                 };
--                usb2: usb2@6000000 {
-+                usb2@0{
-                         status = "ok";
-                 };
-       };
 --- /dev/null
 +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
 @@ -0,0 +1,21 @@
@@ -142,13 +108,13 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
 +                              };
 +                      };
 +
-+                        serial_1_pins: serial1_pinmux {
-+                                mux {
-+                                        pins = "gpio8", "gpio9";
-+                                        function = "blsp_uart1";
-+                                        bias-disable;
-+                                };
-+                        };
++                       serial_1_pins: serial1_pinmux {
++                              mux {
++                                      pins = "gpio8", "gpio9";
++                                      function = "blsp_uart1";
++                                      bias-disable;
++                              };
++                      };
 +
 +                      spi_0_pins: spi_0_pinmux {
 +                              pinmux {
@@ -204,12 +170,12 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
 +                      };
 +              };
 +
-+                i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
-+                        pinctrl-0 = <&i2c_0_pins>;
-+                        pinctrl-names = "default";
++              i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
++                      pinctrl-0 = <&i2c_0_pins>;
++                      pinctrl-names = "default";
 +
 +                      status = "ok";
-+                };
++              };
 +
 +              serial@78af000 {
 +                      pinctrl-0 = <&serial_0_pins>;
@@ -217,31 +183,31 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
 +                      status = "ok";
 +              };
 +
-+                serial@78b0000 {
-+                        pinctrl-0 = <&serial_1_pins>;
-+                        pinctrl-names = "default";
-+                        status = "ok";
-+                };
++              serial@78b0000 {
++                      pinctrl-0 = <&serial_1_pins>;
++                      pinctrl-names = "default";
++                      status = "ok";
++              };
 +
-+                usb3_ss_phy: ssphy@9a000 {
-+                        status = "ok";
-+                };
++              usb3_ss_phy: ssphy@9a000 {
++                      status = "ok";
++              };
 +
-+                usb3_hs_phy: hsphy@a6000 {
-+                        status = "ok";
-+                };
++              usb3_hs_phy: hsphy@a6000 {
++                      status = "ok";
++              };
 +
-+                usb3: usb3@0 {
-+                        status = "ok";
-+                };
++              usb3: usb3@8af8800 {
++                      status = "ok";
++              };
 +
-+                usb2_hs_phy: hsphy@a8000 {
-+                        status = "ok";
-+                };
++              usb2_hs_phy: hsphy@a8000 {
++                      status = "ok";
++              };
 +
-+                usb2: usb2@6000000 {
-+                        status = "ok";
-+                };
++              usb2: usb2@60f8800 {
++                      status = "ok";
++              };
 +
 +              cryptobam: dma@8e04000 {
 +                      status = "ok";
index 860ee62..bab2808 100644 (file)
@@ -10,9 +10,13 @@ Signed-off-by: John Crispin <john@phrozen.org>
 
 --- a/arch/arm/boot/dts/Makefile
 +++ b/arch/arm/boot/dts/Makefile
-@@ -619,6 +619,14 @@ dtb-$(CONFIG_ARCH_QCOM) += \
+@@ -618,7 +618,18 @@ dtb-$(CONFIG_ARCH_QCOM) += \
+       qcom-apq8084-mtp.dtb \
        qcom-ipq4019-ap.dk01.1-c1.dtb \
        qcom-ipq4019-ap.dk04.1-c1.dtb \
++      qcom-ipq4019-fritz4040.dtb \
++      qcom-ipq4019-nbg6617.dtb \
++      qcom-ipq4019-rt-ac58u.dtb \
        qcom-ipq8064-ap148.dtb \
 +      qcom-ipq8064-c2600.dtb \
 +      qcom-ipq8064-d7800.dtb \
diff --git a/target/linux/ipq806x/patches-4.9/104-mtd-nand-add-Winbond-manufacturer-and-chip.patch b/target/linux/ipq806x/patches-4.9/104-mtd-nand-add-Winbond-manufacturer-and-chip.patch
new file mode 100644 (file)
index 0000000..5aa37db
--- /dev/null
@@ -0,0 +1,56 @@
+From 07b6d0cdbbda8c917480eceaec668f09e4cf24a5 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Mon, 14 Nov 2016 23:49:22 +0100
+Subject: [PATCH] mtd: nand: add Winbond manufacturer and chip
+
+This patch adds the W25N01GV NAND to the table of
+known devices. Without this patch the device gets detected:
+
+nand: device found, Manufacturer ID: 0xef, Chip ID: 0xaa
+nand: Unknown NAND 256MiB 1,8V 8-bit
+nand: 256 MiB, SLC, erase size: 64 KiB, page size: 1024, OOB size : 16
+
+Whereas the u-boot identifies it as:
+spi_nand: spi_nand_flash_probe SF NAND ID 00:ef:aa:21
+SF: Detected W25N01GV with page size 2 KiB, total 128 MiB
+
+Due to the page size discrepancy, it's impossible to attach
+ubi volumes on the device.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ drivers/mtd/nand/nand_ids.c | 4 ++++
+ include/linux/mtd/nand.h    | 1 +
+ 2 files changed, 5 insertions(+)
+
+--- a/drivers/mtd/nand/nand_ids.c
++++ b/drivers/mtd/nand/nand_ids.c
+@@ -52,6 +52,10 @@ struct nand_flash_dev nand_flash_ids[] =
+               { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
+                 SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
+                 NAND_ECC_INFO(40, SZ_1K), 4 },
++      {"W25N01GV 1G 3.3V 8-bit",
++              { .id = {0xef, 0xaa} },
++                SZ_2K, SZ_128, SZ_128K, NAND_NO_SUBPAGE_WRITE,
++                2, 64, NAND_ECC_INFO(1, SZ_512) },
+       LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
+       LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
+@@ -182,6 +186,7 @@ struct nand_manufacturers nand_manuf_ids
+       {NAND_MFR_SANDISK, "SanDisk"},
+       {NAND_MFR_INTEL, "Intel"},
+       {NAND_MFR_ATO, "ATO"},
++      {NAND_MFR_WINBOND, "Winbond"},
+       {0x0, "Unknown"}
+ };
+--- a/include/linux/mtd/nand.h
++++ b/include/linux/mtd/nand.h
+@@ -924,6 +924,7 @@ static inline void nand_set_controller_d
+ #define NAND_MFR_MICRON               0x2c
+ #define NAND_MFR_AMD          0x01
+ #define NAND_MFR_MACRONIX     0xc2
++#define NAND_MFR_WINBOND      0xef
+ #define NAND_MFR_EON          0x92
+ #define NAND_MFR_SANDISK      0x45
+ #define NAND_MFR_INTEL                0x89
diff --git a/target/linux/ipq806x/patches-4.9/105-mtd-nor-add-mx25l25635f.patch b/target/linux/ipq806x/patches-4.9/105-mtd-nor-add-mx25l25635f.patch
new file mode 100644 (file)
index 0000000..de54dba
--- /dev/null
@@ -0,0 +1,22 @@
+Subject: mtd: spi-nor: add mx25l25635f with SECT_4K
+
+This patch fixes an issue with the creation of the
+ubi volume on the AVM FRITZ!Box 4040. The mx25l25635f
+and mx25l25635e support SECT_4K which will set the
+erase size to 4K. This is used by ubi to calculate
+VID header offsets. Without this, uboot and linux
+disagrees about the layout and refuse to attach
+the ubi volume created by the other.
+
+---
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -1018,7 +1018,7 @@ static const struct flash_info spi_nor_i
+       { "mx25u6435f",  INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
+       { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
+       { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
+-      { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
++      { "mx25l25635f", INFO(0xc22019, 0, 64 * 1024, 512, SECT_4K) },
+       { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K) },
+       { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
+       { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
diff --git a/target/linux/ipq806x/patches-4.9/130-pinctrl-ipq4019-add-pinctrl.patch b/target/linux/ipq806x/patches-4.9/130-pinctrl-ipq4019-add-pinctrl.patch
new file mode 100644 (file)
index 0000000..2c285df
--- /dev/null
@@ -0,0 +1,51 @@
+From e7748d641ae37081e2034869491f1629461ae13c Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Thu, 16 Mar 2017 21:00:18 +0100
+Subject: [PATCH] pinctrl: ipq4019: Add missing pingroups
+
+This patch adds the missing PINGROUP for GPIO70-99.
+This fixes a crash that happens in pinctrl-msm, if any
+of the GPIO70-99 are accessed.
+
+Fixes: 5303f7827fcd41d ("pinctrl: qcom: ipq4019: set ngpios to correct value")
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
++++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+@@ -405,6 +405,36 @@ static const struct msm_pingroup ipq4019
+       PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+       PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+       PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(82, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(83, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(84, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(85, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(88, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(89, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(90, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(91, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(92, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(93, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(94, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(95, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(97, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
++      PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ };
+ static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
diff --git a/target/linux/ipq806x/patches-4.9/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch b/target/linux/ipq806x/patches-4.9/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch
new file mode 100644 (file)
index 0000000..560eee7
--- /dev/null
@@ -0,0 +1,109 @@
+From 6a6c067b7ce2b3de4efbafddc134afbea3ddc1a3 Mon Sep 17 00:00:00 2001
+From: Matthew McClintock <mmcclint@codeaurora.org>
+Date: Fri, 8 Apr 2016 15:26:10 -0500
+Subject: [PATCH] qcom: ipq4019: use v2 of the kpss bringup mechanism
+
+v1 was the incorrect choice here and sometimes the board
+would not come up properly.
+
+Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+Changes:
+       - moved L2-Cache to be a subnode of cpu0
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 32 ++++++++++++++++++++++++--------
+ 1 file changed, 24 insertions(+), 8 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -34,19 +34,27 @@
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+-                      enable-method = "qcom,kpss-acc-v1";
++                      enable-method = "qcom,kpss-acc-v2";
++                      next-level-cache = <&L2>;
+                       qcom,acc = <&acc0>;
+                       qcom,saw = <&saw0>;
+                       reg = <0x0>;
+                       clocks = <&gcc GCC_APPS_CLK_SRC>;
+                       clock-frequency = <0>;
+                       operating-points-v2 = <&cpu0_opp_table>;
++
++                      L2: l2-cache {
++                              compatible = "qcom,arch-cache";
++                              cache-level = <2>;
++                              qcom,saw = <&saw_l2>;
++                      };
+               };
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+-                      enable-method = "qcom,kpss-acc-v1";
++                      enable-method = "qcom,kpss-acc-v2";
++                      next-level-cache = <&L2>;
+                       qcom,acc = <&acc1>;
+                       qcom,saw = <&saw1>;
+                       reg = <0x1>;
+@@ -58,7 +66,8 @@
+               cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+-                      enable-method = "qcom,kpss-acc-v1";
++                      enable-method = "qcom,kpss-acc-v2";
++                      next-level-cache = <&L2>;
+                       qcom,acc = <&acc2>;
+                       qcom,saw = <&saw2>;
+                       reg = <0x2>;
+@@ -70,7 +79,8 @@
+               cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+-                      enable-method = "qcom,kpss-acc-v1";
++                      enable-method = "qcom,kpss-acc-v2";
++                      next-level-cache = <&L2>;
+                       qcom,acc = <&acc3>;
+                       qcom,saw = <&saw3>;
+                       reg = <0x3>;
+@@ -218,22 +228,22 @@
+               };
+                 acc0: clock-controller@b088000 {
+-                        compatible = "qcom,kpss-acc-v1";
++                        compatible = "qcom,kpss-acc-v2";
+                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
+                 };
+                 acc1: clock-controller@b098000 {
+-                        compatible = "qcom,kpss-acc-v1";
++                        compatible = "qcom,kpss-acc-v2";
+                         reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
+                 };
+                 acc2: clock-controller@b0a8000 {
+-                        compatible = "qcom,kpss-acc-v1";
++                        compatible = "qcom,kpss-acc-v2";
+                         reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
+                 };
+                 acc3: clock-controller@b0b8000 {
+-                        compatible = "qcom,kpss-acc-v1";
++                        compatible = "qcom,kpss-acc-v2";
+                         reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
+                 };
+@@ -261,6 +271,12 @@
+                         regulator;
+                 };
++              saw_l2: regulator@b012000 {
++                      compatible = "qcom,saw2";
++                      reg = <0xb012000 0x1000>;
++                      regulator;
++              };
++
+               serial@78af000 {
+                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+                       reg = <0x78af000 0x200>;
diff --git a/target/linux/ipq806x/patches-4.9/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch b/target/linux/ipq806x/patches-4.9/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch
new file mode 100644 (file)
index 0000000..b780d78
--- /dev/null
@@ -0,0 +1,130 @@
+From ea5f4d6f4716f3a0bb4fc3614b7a0e8c0df1cb81 Mon Sep 17 00:00:00 2001
+From: Matthew McClintock <mmcclint@codeaurora.org>
+Date: Thu, 17 Mar 2016 16:22:28 -0500
+Subject: [PATCH] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree
+
+This adds the SoC nodes to the ipq4019 device tree and
+enable it for the DK01.1 board.
+
+Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+Changes:
+       - replaced space with tab
+       - added sleep and mock_utmi clocks
+       - added registers for usb2 and usb3 parent node
+       - changed compatible to qca,ipa4019-dwc3
+       - updated usb2 and usb3 names
+         (included the reg - in case they become necessary later)
+---
+ arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
+ arch/arm/boot/dts/qcom-ipq4019.dtsi           | 71 +++++++++++++++++++++++++++
+ 2 files changed, 91 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+@@ -108,5 +108,25 @@
+               watchdog@b017000 {
+                       status = "ok";
+               };
++
++              usb3_ss_phy: ssphy@9a000 {
++                      status = "ok";
++              };
++
++              usb3_hs_phy: hsphy@a6000 {
++                      status = "ok";
++              };
++
++              usb3: usb3@8af8800 {
++                      status = "ok";
++              };
++
++              usb2_hs_phy: hsphy@a8000 {
++                      status = "ok";
++              };
++
++              usb2: usb2@60f8800 {
++                      status = "ok";
++              };
+       };
+ };
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -313,5 +313,76 @@
+                       compatible = "qcom,pshold";
+                       reg = <0x4ab000 0x4>;
+               };
++
++              usb3_ss_phy: ssphy@9a000 {
++                      compatible = "qca,uni-ssphy";
++                      reg = <0x9a000 0x800>;
++                      reg-names = "phy_base";
++                      resets = <&gcc USB3_UNIPHY_PHY_ARES>;
++                      reset-names = "por_rst";
++                      status = "disabled";
++              };
++
++              usb3_hs_phy: hsphy@a6000 {
++                      compatible = "qca,baldur-usb3-hsphy";
++                      reg = <0xa6000 0x40>;
++                      reg-names = "phy_base";
++                      resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
++                      reset-names = "por_rst", "srif_rst";
++                      status = "disabled";
++              };
++
++              usb3@8af8800 {
++                      compatible = "qca,ipq4019-dwc3";
++                      reg = <0x8af8800 0x100>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      clocks = <&gcc GCC_USB3_MASTER_CLK>,
++                               <&gcc GCC_USB3_SLEEP_CLK>,
++                               <&gcc GCC_USB3_MOCK_UTMI_CLK>;
++                      clock-names = "master", "sleep", "mock_utmi";
++                      ranges;
++                      status = "disabled";
++
++                      dwc3@8a00000 {
++                              compatible = "snps,dwc3";
++                              reg = <0x8a00000 0xf8000>;
++                              interrupts = <0 132 0>;
++                              usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
++                              phy-names = "usb2-phy", "usb3-phy";
++                              dr_mode = "host";
++                      };
++              };
++
++              usb2_hs_phy: hsphy@a8000 {
++                      compatible = "qca,baldur-usb2-hsphy";
++                      reg = <0xa8000 0x40>;
++                      reg-names = "phy_base";
++                      resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
++                      reset-names = "por_rst", "srif_rst";
++                      status = "disabled";
++              };
++
++              usb2@60f8800 {
++                      compatible = "qca,ipq4019-dwc3";
++                      reg = <0x60f8800 0x100>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      clocks = <&gcc GCC_USB2_MASTER_CLK>,
++                               <&gcc GCC_USB2_SLEEP_CLK>,
++                               <&gcc GCC_USB2_MOCK_UTMI_CLK>;
++                      clock-names = "master", "sleep", "mock_utmi";
++                      ranges;
++                      status = "disabled";
++
++                      dwc3@6000000 {
++                              compatible = "snps,dwc3";
++                              reg = <0x6000000 0xf8000>;
++                              interrupts = <0 136 0>;
++                              usb-phy = <&usb2_hs_phy>;
++                              phy-names = "usb2-phy";
++                              dr_mode = "host";
++                      };
++              };
+       };
+ };
diff --git a/target/linux/ipq806x/patches-4.9/307-ARM-qcom-Add-IPQ4019-SoC-support.patch b/target/linux/ipq806x/patches-4.9/307-ARM-qcom-Add-IPQ4019-SoC-support.patch
new file mode 100644 (file)
index 0000000..4cbcc0a
--- /dev/null
@@ -0,0 +1,35 @@
+From e7748d641ae37081e2034869491f1629461ae13c Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sat, 19 Nov 2016 00:58:18 +0100
+Subject: [PATCH] ARM: qcom: Add IPQ4019 SoC support
+
+Add support for the Qualcomm Atheros IPQ4019 SoC.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ arch/arm/Makefile          | 1 +
+ arch/arm/mach-qcom/Kconfig | 5 +++++
+ 2 files changed, 6 insertions(+)
+
+--- a/arch/arm/Makefile
++++ b/arch/arm/Makefile
+@@ -147,6 +147,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
+ endif
+ textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
+ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
++textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
+ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
+ # Machine directory name.  This list is sorted alphanumerically
+--- a/arch/arm/mach-qcom/Kconfig
++++ b/arch/arm/mach-qcom/Kconfig
+@@ -28,4 +28,9 @@ config ARCH_MDM9615
+       bool "Enable support for MDM9615"
+       select CLKSRC_QCOM
++config ARCH_IPQ40XX
++      bool "Enable support for IPQ40XX"
++      select CLKSRC_QCOM
++      select HAVE_ARM_ARCH_TIMER
++
+ endif
diff --git a/target/linux/ipq806x/patches-4.9/308-dts-ipq4019-add-both-IPQ4019-wifi-block-definitions.patch b/target/linux/ipq806x/patches-4.9/308-dts-ipq4019-add-both-IPQ4019-wifi-block-definitions.patch
new file mode 100644 (file)
index 0000000..ad7ce16
--- /dev/null
@@ -0,0 +1,105 @@
+From 6091a49b0b06bf838fed80498c4f5f40d0fbd447 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sat, 19 Nov 2016 01:22:46 +0100
+Subject: [PATCH] dts: ipq4019: add both IPQ4019 wifi block definitions
+
+The IPQ4019 has two ath10k blocks on the AHB. Both wifi's
+are already supported by ath10k.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 84 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 84 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -384,5 +384,89 @@
+                               dr_mode = "host";
+                       };
+               };
++
++              wifi0: wifi@a000000 {
++                      compatible = "qcom,ipq4019-wifi";
++                      reg = <0xa000000 0x200000>;
++                      resets = <&gcc WIFI0_CPU_INIT_RESET
++                                &gcc WIFI0_RADIO_SRIF_RESET
++                                &gcc WIFI0_RADIO_WARM_RESET
++                                &gcc WIFI0_RADIO_COLD_RESET
++                                &gcc WIFI0_CORE_WARM_RESET
++                                &gcc WIFI0_CORE_COLD_RESET>;
++                      reset-names = "wifi_cpu_init", "wifi_radio_srif",
++                                    "wifi_radio_warm", "wifi_radio_cold",
++                                    "wifi_core_warm", "wifi_core_cold";
++                      clocks = <&gcc GCC_WCSS2G_CLK
++                                &gcc GCC_WCSS2G_REF_CLK
++                                &gcc GCC_WCSS2G_RTC_CLK>;
++                      clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
++                                    "wifi_wcss_rtc";
++                      interrupts = <0 32 IRQ_TYPE_EDGE_RISING
++                                    0 33 IRQ_TYPE_EDGE_RISING
++                                    0 34 IRQ_TYPE_EDGE_RISING
++                                    0 35 IRQ_TYPE_EDGE_RISING
++                                    0 36 IRQ_TYPE_EDGE_RISING
++                                    0 37 IRQ_TYPE_EDGE_RISING
++                                    0 38 IRQ_TYPE_EDGE_RISING
++                                    0 39 IRQ_TYPE_EDGE_RISING
++                                    0 40 IRQ_TYPE_EDGE_RISING
++                                    0 41 IRQ_TYPE_EDGE_RISING
++                                    0 42 IRQ_TYPE_EDGE_RISING
++                                    0 43 IRQ_TYPE_EDGE_RISING
++                                    0 44 IRQ_TYPE_EDGE_RISING
++                                    0 45 IRQ_TYPE_EDGE_RISING
++                                    0 46 IRQ_TYPE_EDGE_RISING
++                                    0 47 IRQ_TYPE_EDGE_RISING
++                                    0 168 IRQ_TYPE_NONE>;
++                      interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
++                                         "msi4",  "msi5",  "msi6",  "msi7",
++                                         "msi8",  "msi9", "msi10", "msi11",
++                                        "msi12", "msi13", "msi14", "msi15",
++                                        "legacy";
++                      status = "disabled";
++              };
++
++              wifi1: wifi@a800000 {
++                      compatible = "qcom,ipq4019-wifi";
++                      reg = <0xa800000 0x200000>;
++                      resets = <&gcc WIFI1_CPU_INIT_RESET
++                                &gcc WIFI1_RADIO_SRIF_RESET
++                                &gcc WIFI1_RADIO_WARM_RESET
++                                &gcc WIFI1_RADIO_COLD_RESET
++                                &gcc WIFI1_CORE_WARM_RESET
++                                &gcc WIFI1_CORE_COLD_RESET>;
++                      reset-names = "wifi_cpu_init", "wifi_radio_srif",
++                                    "wifi_radio_warm", "wifi_radio_cold",
++                                    "wifi_core_warm", "wifi_core_cold";
++                      clocks = <&gcc GCC_WCSS5G_CLK
++                                &gcc GCC_WCSS5G_REF_CLK
++                                &gcc GCC_WCSS5G_RTC_CLK>;
++                      clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
++                                    "wifi_wcss_rtc";
++                      interrupts = <0 48 IRQ_TYPE_EDGE_RISING
++                                    0 49 IRQ_TYPE_EDGE_RISING
++                                    0 50 IRQ_TYPE_EDGE_RISING
++                                    0 51 IRQ_TYPE_EDGE_RISING
++                                    0 52 IRQ_TYPE_EDGE_RISING
++                                    0 53 IRQ_TYPE_EDGE_RISING
++                                    0 54 IRQ_TYPE_EDGE_RISING
++                                    0 55 IRQ_TYPE_EDGE_RISING
++                                    0 56 IRQ_TYPE_EDGE_RISING
++                                    0 57 IRQ_TYPE_EDGE_RISING
++                                    0 58 IRQ_TYPE_EDGE_RISING
++                                    0 59 IRQ_TYPE_EDGE_RISING
++                                    0 60 IRQ_TYPE_EDGE_RISING
++                                    0 61 IRQ_TYPE_EDGE_RISING
++                                    0 62 IRQ_TYPE_EDGE_RISING
++                                    0 63 IRQ_TYPE_EDGE_RISING
++                                    0 169 IRQ_TYPE_NONE>;
++                      interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
++                                         "msi4",  "msi5",  "msi6",  "msi7",
++                                         "msi8",  "msi9", "msi10", "msi11",
++                                        "msi12", "msi13", "msi14", "msi15",
++                                        "legacy";
++                      status = "disabled";
++              };
+       };
+ };
diff --git a/target/linux/ipq806x/patches-4.9/309-dts-ipq4019-add-pseudo-random-number-generator.patch b/target/linux/ipq806x/patches-4.9/309-dts-ipq4019-add-pseudo-random-number-generator.patch
new file mode 100644 (file)
index 0000000..8323ff0
--- /dev/null
@@ -0,0 +1,29 @@
+From 26fa6fdc627b523277c7a79907233596b2f8a3ef Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sat, 19 Nov 2016 03:29:04 +0100
+Subject: [PATCH] dts: ipq4019: add pseudo random number generator
+
+This architecture has a pseudo random number generator
+supported by the existing "qcom,prng" binding.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -277,6 +277,13 @@
+                       regulator;
+               };
++              rng@22000 {
++                      compatible = "qcom,prng";
++                      reg = <0x22000 0x140>;
++                      clocks = <&gcc GCC_PRNG_AHB_CLK>;
++                      clock-names = "core";
++              };
++
+               serial@78af000 {
+                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+                       reg = <0x78af000 0x200>;
diff --git a/target/linux/ipq806x/patches-4.9/310-msm-adhoc-bus-support.patch b/target/linux/ipq806x/patches-4.9/310-msm-adhoc-bus-support.patch
new file mode 100644 (file)
index 0000000..ff0e1e0
--- /dev/null
@@ -0,0 +1,11026 @@
+From: Christian Lamparter <chunkeey@googlemail.com>
+Subject: BUS: add MSM_BUS
+--- a/drivers/bus/Makefile
++++ b/drivers/bus/Makefile
+@@ -10,6 +10,7 @@ obj-$(CONFIG_BRCMSTB_GISB_ARB)       += brcmst
+ obj-$(CONFIG_IMX_WEIM)                += imx-weim.o
+ obj-$(CONFIG_MIPS_CDMM)               += mips_cdmm.o
+ obj-$(CONFIG_MVEBU_MBUS)      += mvebu-mbus.o
++obj-$(CONFIG_BUS_TOPOLOGY_ADHOC)+= msm_bus/
+ # Interconnect bus driver for OMAP SoCs.
+ obj-$(CONFIG_OMAP_INTERCONNECT)       += omap_l3_smx.o omap_l3_noc.o
+--- a/drivers/bus/Kconfig
++++ b/drivers/bus/Kconfig
+@@ -92,6 +92,8 @@ config MVEBU_MBUS
+         Driver needed for the MBus configuration on Marvell EBU SoCs
+         (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
++source "drivers/bus/msm_bus/Kconfig"
++
+ config OMAP_INTERCONNECT
+       tristate "OMAP INTERCONNECT DRIVER"
+       depends on ARCH_OMAP2PLUS
+--- /dev/null
++++ b/include/dt-bindings/msm/msm-bus-ids.h
+@@ -0,0 +1,869 @@
++/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef __MSM_BUS_IDS_H
++#define __MSM_BUS_IDS_H
++
++/* Topology related enums */
++#define       MSM_BUS_FAB_DEFAULT 0
++#define       MSM_BUS_FAB_APPSS 0
++#define       MSM_BUS_FAB_SYSTEM 1024
++#define       MSM_BUS_FAB_MMSS 2048
++#define       MSM_BUS_FAB_SYSTEM_FPB 3072
++#define       MSM_BUS_FAB_CPSS_FPB 4096
++
++#define       MSM_BUS_FAB_BIMC 0
++#define       MSM_BUS_FAB_SYS_NOC 1024
++#define       MSM_BUS_FAB_MMSS_NOC 2048
++#define       MSM_BUS_FAB_OCMEM_NOC 3072
++#define       MSM_BUS_FAB_PERIPH_NOC 4096
++#define       MSM_BUS_FAB_CONFIG_NOC 5120
++#define       MSM_BUS_FAB_OCMEM_VNOC 6144
++#define       MSM_BUS_FAB_MMSS_AHB 2049
++#define       MSM_BUS_FAB_A0_NOC 6145
++#define       MSM_BUS_FAB_A1_NOC 6146
++#define       MSM_BUS_FAB_A2_NOC 6147
++
++#define       MSM_BUS_MASTER_FIRST 1
++#define       MSM_BUS_MASTER_AMPSS_M0 1
++#define       MSM_BUS_MASTER_AMPSS_M1 2
++#define       MSM_BUS_APPSS_MASTER_FAB_MMSS 3
++#define       MSM_BUS_APPSS_MASTER_FAB_SYSTEM 4
++#define       MSM_BUS_SYSTEM_MASTER_FAB_APPSS 5
++#define       MSM_BUS_MASTER_SPS 6
++#define       MSM_BUS_MASTER_ADM_PORT0 7
++#define       MSM_BUS_MASTER_ADM_PORT1 8
++#define       MSM_BUS_SYSTEM_MASTER_ADM1_PORT0 9
++#define       MSM_BUS_MASTER_ADM1_PORT1 10
++#define       MSM_BUS_MASTER_LPASS_PROC 11
++#define       MSM_BUS_MASTER_MSS_PROCI 12
++#define       MSM_BUS_MASTER_MSS_PROCD 13
++#define       MSM_BUS_MASTER_MSS_MDM_PORT0 14
++#define       MSM_BUS_MASTER_LPASS 15
++#define       MSM_BUS_SYSTEM_MASTER_CPSS_FPB 16
++#define       MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB 17
++#define       MSM_BUS_SYSTEM_MASTER_MMSS_FPB 18
++#define       MSM_BUS_MASTER_ADM1_CI 19
++#define       MSM_BUS_MASTER_ADM0_CI 20
++#define       MSM_BUS_MASTER_MSS_MDM_PORT1 21
++#define       MSM_BUS_MASTER_MDP_PORT0 22
++#define       MSM_BUS_MASTER_MDP_PORT1 23
++#define       MSM_BUS_MMSS_MASTER_ADM1_PORT0 24
++#define       MSM_BUS_MASTER_ROTATOR 25
++#define       MSM_BUS_MASTER_GRAPHICS_3D 26
++#define       MSM_BUS_MASTER_JPEG_DEC 27
++#define       MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28
++#define       MSM_BUS_MASTER_VFE 29
++#define       MSM_BUS_MASTER_VPE 30
++#define       MSM_BUS_MASTER_JPEG_ENC 31
++#define       MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32
++#define       MSM_BUS_MMSS_MASTER_APPS_FAB 33
++#define       MSM_BUS_MASTER_HD_CODEC_PORT0 34
++#define       MSM_BUS_MASTER_HD_CODEC_PORT1 35
++#define       MSM_BUS_MASTER_SPDM 36
++#define       MSM_BUS_MASTER_RPM 37
++#define       MSM_BUS_MASTER_MSS 38
++#define       MSM_BUS_MASTER_RIVA 39
++#define       MSM_BUS_MASTER_SNOC_VMEM 40
++#define       MSM_BUS_MASTER_MSS_SW_PROC 41
++#define       MSM_BUS_MASTER_MSS_FW_PROC 42
++#define       MSM_BUS_MASTER_HMSS 43
++#define       MSM_BUS_MASTER_GSS_NAV 44
++#define       MSM_BUS_MASTER_PCIE 45
++#define       MSM_BUS_MASTER_SATA 46
++#define       MSM_BUS_MASTER_CRYPTO 47
++#define       MSM_BUS_MASTER_VIDEO_CAP 48
++#define       MSM_BUS_MASTER_GRAPHICS_3D_PORT1 49
++#define       MSM_BUS_MASTER_VIDEO_ENC 50
++#define       MSM_BUS_MASTER_VIDEO_DEC 51
++#define       MSM_BUS_MASTER_LPASS_AHB 52
++#define       MSM_BUS_MASTER_QDSS_BAM 53
++#define       MSM_BUS_MASTER_SNOC_CFG 54
++#define       MSM_BUS_MASTER_CRYPTO_CORE0 55
++#define       MSM_BUS_MASTER_CRYPTO_CORE1 56
++#define       MSM_BUS_MASTER_MSS_NAV 57
++#define       MSM_BUS_MASTER_OCMEM_DMA 58
++#define       MSM_BUS_MASTER_WCSS 59
++#define       MSM_BUS_MASTER_QDSS_ETR 60
++#define       MSM_BUS_MASTER_USB3 61
++#define       MSM_BUS_MASTER_JPEG 62
++#define       MSM_BUS_MASTER_VIDEO_P0 63
++#define       MSM_BUS_MASTER_VIDEO_P1 64
++#define       MSM_BUS_MASTER_MSS_PROC 65
++#define       MSM_BUS_MASTER_JPEG_OCMEM 66
++#define       MSM_BUS_MASTER_MDP_OCMEM 67
++#define       MSM_BUS_MASTER_VIDEO_P0_OCMEM 68
++#define       MSM_BUS_MASTER_VIDEO_P1_OCMEM 69
++#define       MSM_BUS_MASTER_VFE_OCMEM 70
++#define       MSM_BUS_MASTER_CNOC_ONOC_CFG 71
++#define       MSM_BUS_MASTER_RPM_INST 72
++#define       MSM_BUS_MASTER_RPM_DATA 73
++#define       MSM_BUS_MASTER_RPM_SYS 74
++#define       MSM_BUS_MASTER_DEHR 75
++#define       MSM_BUS_MASTER_QDSS_DAP 76
++#define       MSM_BUS_MASTER_TIC 77
++#define       MSM_BUS_MASTER_SDCC_1 78
++#define       MSM_BUS_MASTER_SDCC_3 79
++#define       MSM_BUS_MASTER_SDCC_4 80
++#define       MSM_BUS_MASTER_SDCC_2 81
++#define       MSM_BUS_MASTER_TSIF 82
++#define       MSM_BUS_MASTER_BAM_DMA 83
++#define       MSM_BUS_MASTER_BLSP_2 84
++#define       MSM_BUS_MASTER_USB_HSIC 85
++#define       MSM_BUS_MASTER_BLSP_1 86
++#define       MSM_BUS_MASTER_USB_HS 87
++#define       MSM_BUS_MASTER_PNOC_CFG 88
++#define       MSM_BUS_MASTER_V_OCMEM_GFX3D 89
++#define       MSM_BUS_MASTER_IPA 90
++#define       MSM_BUS_MASTER_QPIC 91
++#define       MSM_BUS_MASTER_MDPE 92
++#define       MSM_BUS_MASTER_USB_HS2 93
++#define       MSM_BUS_MASTER_VPU 94
++#define       MSM_BUS_MASTER_UFS 95
++#define       MSM_BUS_MASTER_BCAST 96
++#define       MSM_BUS_MASTER_CRYPTO_CORE2 97
++#define       MSM_BUS_MASTER_EMAC 98
++#define       MSM_BUS_MASTER_VPU_1 99
++#define       MSM_BUS_MASTER_PCIE_1 100
++#define       MSM_BUS_MASTER_USB3_1 101
++#define       MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG 102
++#define       MSM_BUS_MASTER_CNOC_MNOC_CFG 103
++#define       MSM_BUS_MASTER_TCU_0 104
++#define       MSM_BUS_MASTER_TCU_1 105
++#define       MSM_BUS_MASTER_CPP 106
++#define       MSM_BUS_MASTER_AUDIO 107
++#define       MSM_BUS_MASTER_PCIE_2 108
++#define       MSM_BUS_MASTER_BLSP_BAM 109
++#define       MSM_BUS_MASTER_USB2_BAM 110
++#define       MSM_BUS_MASTER_ADDS_DMA0 111
++#define       MSM_BUS_MASTER_ADDS_DMA1 112
++#define       MSM_BUS_MASTER_ADDS_DMA2 113
++#define       MSM_BUS_MASTER_ADDS_DMA3 114
++#define       MSM_BUS_MASTER_QPIC_BAM 115
++#define       MSM_BUS_MASTER_SDCC_BAM 116
++#define       MSM_BUS_MASTER_DDRC_SNOC 117
++#define       MSM_BUS_MASTER_WSS_0  118
++#define       MSM_BUS_MASTER_WSS_1  119
++#define       MSM_BUS_MASTER_ESS 120
++#define       MSM_BUS_MASTER_QDSS_BAMNDP 121
++#define       MSM_BUS_MASTER_QDSS_SNOC_CFG 122
++#define       MSM_BUS_MASTER_LAST 130
++
++#define       MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB
++#define       MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB
++
++#define       MSM_BUS_SNOC_MM_INT_0 10000
++#define       MSM_BUS_SNOC_MM_INT_1 10001
++#define       MSM_BUS_SNOC_MM_INT_2 10002
++#define       MSM_BUS_SNOC_MM_INT_BIMC 10003
++#define       MSM_BUS_SNOC_INT_0 10004
++#define       MSM_BUS_SNOC_INT_1 10005
++#define       MSM_BUS_SNOC_INT_BIMC 10006
++#define       MSM_BUS_SNOC_BIMC_0_MAS 10007
++#define       MSM_BUS_SNOC_BIMC_1_MAS 10008
++#define       MSM_BUS_SNOC_QDSS_INT 10009
++#define       MSM_BUS_PNOC_SNOC_MAS 10010
++#define       MSM_BUS_PNOC_SNOC_SLV 10011
++#define       MSM_BUS_PNOC_INT_0 10012
++#define       MSM_BUS_PNOC_INT_1 10013
++#define       MSM_BUS_PNOC_M_0 10014
++#define       MSM_BUS_PNOC_M_1 10015
++#define       MSM_BUS_BIMC_SNOC_MAS 10016
++#define       MSM_BUS_BIMC_SNOC_SLV 10017
++#define       MSM_BUS_PNOC_SLV_0 10018
++#define       MSM_BUS_PNOC_SLV_1 10019
++#define       MSM_BUS_PNOC_SLV_2 10020
++#define       MSM_BUS_PNOC_SLV_3 10021
++#define       MSM_BUS_PNOC_SLV_4 10022
++#define       MSM_BUS_PNOC_SLV_8 10023
++#define       MSM_BUS_PNOC_SLV_9 10024
++#define       MSM_BUS_SNOC_BIMC_0_SLV 10025
++#define       MSM_BUS_SNOC_BIMC_1_SLV 10026
++#define       MSM_BUS_MNOC_BIMC_MAS 10027
++#define       MSM_BUS_MNOC_BIMC_SLV 10028
++#define       MSM_BUS_BIMC_MNOC_MAS 10029
++#define       MSM_BUS_BIMC_MNOC_SLV 10030
++#define       MSM_BUS_SNOC_BIMC_MAS 10031
++#define       MSM_BUS_SNOC_BIMC_SLV 10032
++#define       MSM_BUS_CNOC_SNOC_MAS 10033
++#define       MSM_BUS_CNOC_SNOC_SLV 10034
++#define       MSM_BUS_SNOC_CNOC_MAS 10035
++#define       MSM_BUS_SNOC_CNOC_SLV 10036
++#define       MSM_BUS_OVNOC_SNOC_MAS 10037
++#define       MSM_BUS_OVNOC_SNOC_SLV 10038
++#define       MSM_BUS_SNOC_OVNOC_MAS 10039
++#define       MSM_BUS_SNOC_OVNOC_SLV 10040
++#define       MSM_BUS_SNOC_PNOC_MAS 10041
++#define       MSM_BUS_SNOC_PNOC_SLV 10042
++#define       MSM_BUS_BIMC_INT_APPS_EBI 10043
++#define       MSM_BUS_BIMC_INT_APPS_SNOC 10044
++#define       MSM_BUS_SNOC_BIMC_2_MAS 10045
++#define       MSM_BUS_SNOC_BIMC_2_SLV 10046
++#define       MSM_BUS_PNOC_SLV_5 10047
++#define       MSM_BUS_PNOC_SLV_6 10048
++#define       MSM_BUS_PNOC_INT_2 10049
++#define       MSM_BUS_PNOC_INT_3 10050
++#define       MSM_BUS_PNOC_INT_4 10051
++#define       MSM_BUS_PNOC_INT_5 10052
++#define       MSM_BUS_PNOC_INT_6 10053
++#define       MSM_BUS_PNOC_INT_7 10054
++#define       MSM_BUS_BIMC_SNOC_1_MAS 10055
++#define       MSM_BUS_BIMC_SNOC_1_SLV 10056
++#define       MSM_BUS_PNOC_A1NOC_MAS 10057
++#define       MSM_BUS_PNOC_A1NOC_SLV 10058
++#define       MSM_BUS_CNOC_A1NOC_MAS 10059
++#define       MSM_BUS_A0NOC_SNOC_MAS 10060
++#define       MSM_BUS_A0NOC_SNOC_SLV 10061
++#define       MSM_BUS_A1NOC_SNOC_SLV 10062
++#define       MSM_BUS_A1NOC_SNOC_MAS 10063
++#define       MSM_BUS_A2NOC_SNOC_MAS 10064
++#define       MSM_BUS_A2NOC_SNOC_SLV 10065
++#define       MSM_BUS_PNOC_SLV_7 10066
++#define       MSM_BUS_INT_LAST 10067
++
++#define       MSM_BUS_SLAVE_FIRST 512
++#define       MSM_BUS_SLAVE_EBI_CH0 512
++#define       MSM_BUS_SLAVE_EBI_CH1 513
++#define       MSM_BUS_SLAVE_AMPSS_L2 514
++#define       MSM_BUS_APPSS_SLAVE_FAB_MMSS 515
++#define       MSM_BUS_APPSS_SLAVE_FAB_SYSTEM 516
++#define       MSM_BUS_SYSTEM_SLAVE_FAB_APPS 517
++#define       MSM_BUS_SLAVE_SPS 518
++#define       MSM_BUS_SLAVE_SYSTEM_IMEM 519
++#define       MSM_BUS_SLAVE_AMPSS 520
++#define       MSM_BUS_SLAVE_MSS 521
++#define       MSM_BUS_SLAVE_LPASS 522
++#define       MSM_BUS_SYSTEM_SLAVE_CPSS_FPB 523
++#define       MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB 524
++#define       MSM_BUS_SYSTEM_SLAVE_MMSS_FPB 525
++#define       MSM_BUS_SLAVE_CORESIGHT 526
++#define       MSM_BUS_SLAVE_RIVA 527
++#define       MSM_BUS_SLAVE_SMI 528
++#define       MSM_BUS_MMSS_SLAVE_FAB_APPS 529
++#define       MSM_BUS_MMSS_SLAVE_FAB_APPS_1 530
++#define       MSM_BUS_SLAVE_MM_IMEM 531
++#define       MSM_BUS_SLAVE_CRYPTO 532
++#define       MSM_BUS_SLAVE_SPDM 533
++#define       MSM_BUS_SLAVE_RPM 534
++#define       MSM_BUS_SLAVE_RPM_MSG_RAM 535
++#define       MSM_BUS_SLAVE_MPM 536
++#define       MSM_BUS_SLAVE_PMIC1_SSBI1_A 537
++#define       MSM_BUS_SLAVE_PMIC1_SSBI1_B 538
++#define       MSM_BUS_SLAVE_PMIC1_SSBI1_C 539
++#define       MSM_BUS_SLAVE_PMIC2_SSBI2_A 540
++#define       MSM_BUS_SLAVE_PMIC2_SSBI2_B 541
++#define       MSM_BUS_SLAVE_GSBI1_UART 542
++#define       MSM_BUS_SLAVE_GSBI2_UART 543
++#define       MSM_BUS_SLAVE_GSBI3_UART 544
++#define       MSM_BUS_SLAVE_GSBI4_UART 545
++#define       MSM_BUS_SLAVE_GSBI5_UART 546
++#define       MSM_BUS_SLAVE_GSBI6_UART 547
++#define       MSM_BUS_SLAVE_GSBI7_UART 548
++#define       MSM_BUS_SLAVE_GSBI8_UART 549
++#define       MSM_BUS_SLAVE_GSBI9_UART 550
++#define       MSM_BUS_SLAVE_GSBI10_UART 551
++#define       MSM_BUS_SLAVE_GSBI11_UART 552
++#define       MSM_BUS_SLAVE_GSBI12_UART 553
++#define       MSM_BUS_SLAVE_GSBI1_QUP 554
++#define       MSM_BUS_SLAVE_GSBI2_QUP 555
++#define       MSM_BUS_SLAVE_GSBI3_QUP 556
++#define       MSM_BUS_SLAVE_GSBI4_QUP 557
++#define       MSM_BUS_SLAVE_GSBI5_QUP 558
++#define       MSM_BUS_SLAVE_GSBI6_QUP 559
++#define       MSM_BUS_SLAVE_GSBI7_QUP 560
++#define       MSM_BUS_SLAVE_GSBI8_QUP 561
++#define       MSM_BUS_SLAVE_GSBI9_QUP 562
++#define       MSM_BUS_SLAVE_GSBI10_QUP 563
++#define       MSM_BUS_SLAVE_GSBI11_QUP 564
++#define       MSM_BUS_SLAVE_GSBI12_QUP 565
++#define       MSM_BUS_SLAVE_EBI2_NAND 566
++#define       MSM_BUS_SLAVE_EBI2_CS0 567
++#define       MSM_BUS_SLAVE_EBI2_CS1 568
++#define       MSM_BUS_SLAVE_EBI2_CS2 569
++#define       MSM_BUS_SLAVE_EBI2_CS3 570
++#define       MSM_BUS_SLAVE_EBI2_CS4 571
++#define       MSM_BUS_SLAVE_EBI2_CS5 572
++#define       MSM_BUS_SLAVE_USB_FS1 573
++#define       MSM_BUS_SLAVE_USB_FS2 574
++#define       MSM_BUS_SLAVE_TSIF 575
++#define       MSM_BUS_SLAVE_MSM_TSSC 576
++#define       MSM_BUS_SLAVE_MSM_PDM 577
++#define       MSM_BUS_SLAVE_MSM_DIMEM 578
++#define       MSM_BUS_SLAVE_MSM_TCSR 579
++#define       MSM_BUS_SLAVE_MSM_PRNG 580
++#define       MSM_BUS_SLAVE_GSS 581
++#define       MSM_BUS_SLAVE_SATA 582
++#define       MSM_BUS_SLAVE_USB3 583
++#define       MSM_BUS_SLAVE_WCSS 584
++#define       MSM_BUS_SLAVE_OCIMEM 585
++#define       MSM_BUS_SLAVE_SNOC_OCMEM 586
++#define       MSM_BUS_SLAVE_SERVICE_SNOC 587
++#define       MSM_BUS_SLAVE_QDSS_STM 588
++#define       MSM_BUS_SLAVE_CAMERA_CFG 589
++#define       MSM_BUS_SLAVE_DISPLAY_CFG 590
++#define       MSM_BUS_SLAVE_OCMEM_CFG 591
++#define       MSM_BUS_SLAVE_CPR_CFG 592
++#define       MSM_BUS_SLAVE_CPR_XPU_CFG 593
++#define       MSM_BUS_SLAVE_MISC_CFG 594
++#define       MSM_BUS_SLAVE_MISC_XPU_CFG 595
++#define       MSM_BUS_SLAVE_VENUS_CFG 596
++#define       MSM_BUS_SLAVE_MISC_VENUS_CFG 597
++#define       MSM_BUS_SLAVE_GRAPHICS_3D_CFG 598
++#define       MSM_BUS_SLAVE_MMSS_CLK_CFG 599
++#define       MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG 600
++#define       MSM_BUS_SLAVE_MNOC_MPU_CFG 601
++#define       MSM_BUS_SLAVE_ONOC_MPU_CFG 602
++#define       MSM_BUS_SLAVE_SERVICE_MNOC 603
++#define       MSM_BUS_SLAVE_OCMEM 604
++#define       MSM_BUS_SLAVE_SERVICE_ONOC 605
++#define       MSM_BUS_SLAVE_SDCC_1 606
++#define       MSM_BUS_SLAVE_SDCC_3 607
++#define       MSM_BUS_SLAVE_SDCC_2 608
++#define       MSM_BUS_SLAVE_SDCC_4 609
++#define       MSM_BUS_SLAVE_BAM_DMA 610
++#define       MSM_BUS_SLAVE_BLSP_2 611
++#define       MSM_BUS_SLAVE_USB_HSIC 612
++#define       MSM_BUS_SLAVE_BLSP_1 613
++#define       MSM_BUS_SLAVE_USB_HS 614
++#define       MSM_BUS_SLAVE_PDM 615
++#define       MSM_BUS_SLAVE_PERIPH_APU_CFG 616
++#define       MSM_BUS_SLAVE_PNOC_MPU_CFG 617
++#define       MSM_BUS_SLAVE_PRNG 618
++#define       MSM_BUS_SLAVE_SERVICE_PNOC 619
++#define       MSM_BUS_SLAVE_CLK_CTL 620
++#define       MSM_BUS_SLAVE_CNOC_MSS 621
++#define       MSM_BUS_SLAVE_SECURITY 622
++#define       MSM_BUS_SLAVE_TCSR 623
++#define       MSM_BUS_SLAVE_TLMM 624
++#define       MSM_BUS_SLAVE_CRYPTO_0_CFG 625
++#define       MSM_BUS_SLAVE_CRYPTO_1_CFG 626
++#define       MSM_BUS_SLAVE_IMEM_CFG 627
++#define       MSM_BUS_SLAVE_MESSAGE_RAM 628
++#define       MSM_BUS_SLAVE_BIMC_CFG 629
++#define       MSM_BUS_SLAVE_BOOT_ROM 630
++#define       MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG 631
++#define       MSM_BUS_SLAVE_PMIC_ARB 632
++#define       MSM_BUS_SLAVE_SPDM_WRAPPER 633
++#define       MSM_BUS_SLAVE_DEHR_CFG 634
++#define       MSM_BUS_SLAVE_QDSS_CFG 635
++#define       MSM_BUS_SLAVE_RBCPR_CFG 636
++#define       MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG 637
++#define       MSM_BUS_SLAVE_SNOC_MPU_CFG 638
++#define       MSM_BUS_SLAVE_CNOC_ONOC_CFG 639
++#define       MSM_BUS_SLAVE_CNOC_MNOC_CFG 640
++#define       MSM_BUS_SLAVE_PNOC_CFG 641
++#define       MSM_BUS_SLAVE_SNOC_CFG 642
++#define       MSM_BUS_SLAVE_EBI1_DLL_CFG 643
++#define       MSM_BUS_SLAVE_PHY_APU_CFG 644
++#define       MSM_BUS_SLAVE_EBI1_PHY_CFG 645
++#define       MSM_BUS_SLAVE_SERVICE_CNOC 646
++#define       MSM_BUS_SLAVE_IPS_CFG 647
++#define       MSM_BUS_SLAVE_QPIC 648
++#define       MSM_BUS_SLAVE_DSI_CFG 649
++#define       MSM_BUS_SLAVE_UFS_CFG 650
++#define       MSM_BUS_SLAVE_RBCPR_CX_CFG 651
++#define       MSM_BUS_SLAVE_RBCPR_MX_CFG 652
++#define       MSM_BUS_SLAVE_PCIE_CFG 653
++#define       MSM_BUS_SLAVE_USB_PHYS_CFG 654
++#define       MSM_BUS_SLAVE_VIDEO_CAP_CFG 655
++#define       MSM_BUS_SLAVE_AVSYNC_CFG 656
++#define       MSM_BUS_SLAVE_CRYPTO_2_CFG 657
++#define       MSM_BUS_SLAVE_VPU_CFG 658
++#define       MSM_BUS_SLAVE_BCAST_CFG 659
++#define       MSM_BUS_SLAVE_KLM_CFG 660
++#define       MSM_BUS_SLAVE_GENI_IR_CFG 661
++#define       MSM_BUS_SLAVE_OCMEM_GFX 662
++#define       MSM_BUS_SLAVE_CATS_128 663
++#define       MSM_BUS_SLAVE_OCMEM_64 664
++#define MSM_BUS_SLAVE_PCIE_0 665
++#define MSM_BUS_SLAVE_PCIE_1 666
++#define       MSM_BUS_SLAVE_PCIE_0_CFG 667
++#define       MSM_BUS_SLAVE_PCIE_1_CFG 668
++#define       MSM_BUS_SLAVE_SRVC_MNOC 669
++#define       MSM_BUS_SLAVE_USB_HS2 670
++#define       MSM_BUS_SLAVE_AUDIO     671
++#define       MSM_BUS_SLAVE_TCU       672
++#define       MSM_BUS_SLAVE_APPSS     673
++#define       MSM_BUS_SLAVE_PCIE_PARF 674
++#define       MSM_BUS_SLAVE_USB3_PHY_CFG      675
++#define       MSM_BUS_SLAVE_IPA_CFG   676
++#define       MSM_BUS_SLAVE_A0NOC_SNOC 677
++#define       MSM_BUS_SLAVE_A1NOC_SNOC 678
++#define       MSM_BUS_SLAVE_A2NOC_SNOC 679
++#define       MSM_BUS_SLAVE_HMSS_L3 680
++#define       MSM_BUS_SLAVE_PIMEM_CFG 681
++#define       MSM_BUS_SLAVE_DCC_CFG 682
++#define       MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683
++#define       MSM_BUS_SLAVE_PCIE_2_CFG 684
++#define       MSM_BUS_SLAVE_PCIE20_AHB2PHY 685
++#define       MSM_BUS_SLAVE_A0NOC_CFG 686
++#define       MSM_BUS_SLAVE_A1NOC_CFG 687
++#define       MSM_BUS_SLAVE_A2NOC_CFG 688
++#define       MSM_BUS_SLAVE_A1NOC_MPU_CFG 689
++#define       MSM_BUS_SLAVE_A2NOC_MPU_CFG 690
++#define       MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691
++#define       MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692
++#define       MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693
++#define       MSM_BUS_SLAVE_LPASS_SMMU_CFG 694
++#define       MSM_BUS_SLAVE_MMAGIC_CFG 695
++#define       MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696
++#define       MSM_BUS_SLAVE_SSC_CFG 697
++#define       MSM_BUS_SLAVE_DSA_CFG 698
++#define       MSM_BUS_SLAVE_DSA_MPU_CFG 699
++#define       MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700
++#define       MSM_BUS_SLAVE_SMMU_CPP_CFG 701
++#define       MSM_BUS_SLAVE_SMMU_JPEG_CFG 702
++#define       MSM_BUS_SLAVE_SMMU_MDP_CFG 703
++#define       MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704
++#define       MSM_BUS_SLAVE_SMMU_VENUS_CFG 705
++#define       MSM_BUS_SLAVE_SMMU_VFE_CFG 706
++#define       MSM_BUS_SLAVE_A0NOC_MPU_CFG 707
++#define       MSM_BUS_SLAVE_VMEM_CFG 708
++#define       MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 700
++#define       MSM_BUS_SLAVE_VMEM 709
++#define       MSM_BUS_SLAVE_AHB2PHY 710
++#define       MSM_BUS_SLAVE_PIMEM 711
++#define       MSM_BUS_SLAVE_SNOC_VMEM 712
++#define       MSM_BUS_SLAVE_PCIE_2 713
++#define       MSM_BUS_SLAVE_RBCPR_MX 714
++#define       MSM_BUS_SLAVE_RBCPR_CX 715
++#define       MSM_BUS_SLAVE_PRNG_APU_CFG 716
++#define       MSM_BUS_SLAVE_PERIPH_MPU_CFG 717
++#define       MSM_BUS_SLAVE_GCNT 718
++#define       MSM_BUS_SLAVE_ADSS_CFG 719
++#define       MSM_BUS_SLAVE_ADSS_VMIDMT_CFG 720
++#define       MSM_BUS_SLAVE_QHSS_APU_CFG 721
++#define       MSM_BUS_SLAVE_MDIO 722
++#define       MSM_BUS_SLAVE_FEPHY_CFG 723
++#define       MSM_BUS_SLAVE_SRIF 724
++#define       MSM_BUS_SLAVE_LAST 730
++#define       MSM_BUS_SLAVE_DDRC_CFG 731
++#define       MSM_BUS_SLAVE_DDRC_APU_CFG 732
++#define       MSM_BUS_SLAVE_MPU0_CFG 733
++#define       MSM_BUS_SLAVE_MPU1_CFG 734
++#define       MSM_BUS_SLAVE_MPU2_CFG 734
++#define       MSM_BUS_SLAVE_ESS_VMIDMT_CFG 735
++#define       MSM_BUS_SLAVE_ESS_APU_CFG 736
++#define       MSM_BUS_SLAVE_USB2_CFG 737
++#define       MSM_BUS_SLAVE_BLSP_CFG 738
++#define       MSM_BUS_SLAVE_QPIC_CFG 739
++#define       MSM_BUS_SLAVE_SDCC_CFG 740
++#define       MSM_BUS_SLAVE_WSS0_VMIDMT_CFG 741
++#define       MSM_BUS_SLAVE_WSS0_APU_CFG 742
++#define       MSM_BUS_SLAVE_WSS1_VMIDMT_CFG 743
++#define       MSM_BUS_SLAVE_WSS1_APU_CFG 744
++#define       MSM_BUS_SLAVE_SRVC_PCNOC 745
++#define       MSM_BUS_SLAVE_SNOC_DDRC 746
++#define       MSM_BUS_SLAVE_A7SS 747
++#define       MSM_BUS_SLAVE_WSS0_CFG 748
++#define       MSM_BUS_SLAVE_WSS1_CFG 749
++#define       MSM_BUS_SLAVE_PCIE 750
++#define       MSM_BUS_SLAVE_USB3_CFG 751
++#define       MSM_BUS_SLAVE_CRYPTO_CFG 752
++#define       MSM_BUS_SLAVE_ESS_CFG 753
++#define       MSM_BUS_SLAVE_SRVC_SNOC 754
++
++#define       MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM  MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB
++#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB
++
++/*
++ * ID's used in RPM messages
++ */
++#define ICBID_MASTER_APPSS_PROC 0
++#define ICBID_MASTER_MSS_PROC 1
++#define ICBID_MASTER_MNOC_BIMC 2
++#define ICBID_MASTER_SNOC_BIMC 3
++#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC
++#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4
++#define ICBID_MASTER_CNOC_MNOC_CFG 5
++#define ICBID_MASTER_GFX3D 6
++#define ICBID_MASTER_JPEG 7
++#define ICBID_MASTER_MDP 8
++#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP
++#define ICBID_MASTER_MDPS ICBID_MASTER_MDP
++#define ICBID_MASTER_VIDEO 9
++#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO
++#define ICBID_MASTER_VIDEO_P1 10
++#define ICBID_MASTER_VFE 11
++#define ICBID_MASTER_CNOC_ONOC_CFG 12
++#define ICBID_MASTER_JPEG_OCMEM 13
++#define ICBID_MASTER_MDP_OCMEM 14
++#define ICBID_MASTER_VIDEO_P0_OCMEM 15
++#define ICBID_MASTER_VIDEO_P1_OCMEM 16
++#define ICBID_MASTER_VFE_OCMEM 17
++#define ICBID_MASTER_LPASS_AHB 18
++#define ICBID_MASTER_QDSS_BAM 19
++#define ICBID_MASTER_SNOC_CFG 20
++#define ICBID_MASTER_BIMC_SNOC 21
++#define ICBID_MASTER_CNOC_SNOC 22
++#define ICBID_MASTER_CRYPTO 23
++#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO
++#define ICBID_MASTER_CRYPTO_CORE1 24
++#define ICBID_MASTER_LPASS_PROC 25
++#define ICBID_MASTER_MSS 26
++#define ICBID_MASTER_MSS_NAV 27
++#define ICBID_MASTER_OCMEM_DMA 28
++#define ICBID_MASTER_PNOC_SNOC 29
++#define ICBID_MASTER_WCSS 30
++#define ICBID_MASTER_QDSS_ETR 31
++#define ICBID_MASTER_USB3 32
++#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3
++#define ICBID_MASTER_SDCC_1 33
++#define ICBID_MASTER_SDCC_3 34
++#define ICBID_MASTER_SDCC_2 35
++#define ICBID_MASTER_SDCC_4 36
++#define ICBID_MASTER_TSIF 37
++#define ICBID_MASTER_BAM_DMA 38
++#define ICBID_MASTER_BLSP_2 39
++#define ICBID_MASTER_USB_HSIC 40
++#define ICBID_MASTER_BLSP_1 41
++#define ICBID_MASTER_USB_HS 42
++#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS
++#define ICBID_MASTER_PNOC_CFG 43
++#define ICBID_MASTER_SNOC_PNOC 44
++#define ICBID_MASTER_RPM_INST 45
++#define ICBID_MASTER_RPM_DATA 46
++#define ICBID_MASTER_RPM_SYS 47
++#define ICBID_MASTER_DEHR 48
++#define ICBID_MASTER_QDSS_DAP 49
++#define ICBID_MASTER_SPDM 50
++#define ICBID_MASTER_TIC 51
++#define ICBID_MASTER_SNOC_CNOC 52
++#define ICBID_MASTER_GFX3D_OCMEM 53
++#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM
++#define ICBID_MASTER_OVIRT_SNOC 54
++#define ICBID_MASTER_SNOC_OVIRT 55
++#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT
++#define ICBID_MASTER_ONOC_OVIRT 56
++#define ICBID_MASTER_USB_HS2 57
++#define ICBID_MASTER_QPIC 58
++#define ICBID_MASTER_IPA 59
++#define ICBID_MASTER_DSI 60
++#define ICBID_MASTER_MDP1 61
++#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1
++#define ICBID_MASTER_VPU_PROC 62
++#define ICBID_MASTER_VPU 63
++#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU
++#define ICBID_MASTER_CRYPTO_CORE2 64
++#define ICBID_MASTER_PCIE_0 65
++#define ICBID_MASTER_PCIE_1 66
++#define ICBID_MASTER_SATA 67
++#define ICBID_MASTER_UFS 68
++#define ICBID_MASTER_USB3_1 69
++#define ICBID_MASTER_VIDEO_OCMEM 70
++#define ICBID_MASTER_VPU1 71
++#define ICBID_MASTER_VCAP 72
++#define ICBID_MASTER_EMAC 73
++#define ICBID_MASTER_BCAST 74
++#define ICBID_MASTER_MMSS_PROC 75
++#define ICBID_MASTER_SNOC_BIMC_1 76
++#define ICBID_MASTER_SNOC_PCNOC 77
++#define ICBID_MASTER_AUDIO 78
++#define ICBID_MASTER_MM_INT_0 79
++#define ICBID_MASTER_MM_INT_1 80
++#define ICBID_MASTER_MM_INT_2 81
++#define ICBID_MASTER_MM_INT_BIMC 82
++#define ICBID_MASTER_MSS_INT 83
++#define ICBID_MASTER_PCNOC_CFG 84
++#define ICBID_MASTER_PCNOC_INT_0 85
++#define ICBID_MASTER_PCNOC_INT_1 86
++#define ICBID_MASTER_PCNOC_M_0 87
++#define ICBID_MASTER_PCNOC_M_1 88
++#define ICBID_MASTER_PCNOC_S_0 89
++#define ICBID_MASTER_PCNOC_S_1 90
++#define ICBID_MASTER_PCNOC_S_2 91
++#define ICBID_MASTER_PCNOC_S_3 92
++#define ICBID_MASTER_PCNOC_S_4 93
++#define ICBID_MASTER_PCNOC_S_6 94
++#define ICBID_MASTER_PCNOC_S_7 95
++#define ICBID_MASTER_PCNOC_S_8 96
++#define ICBID_MASTER_PCNOC_S_9 97
++#define ICBID_MASTER_QDSS_INT 98
++#define ICBID_MASTER_SNOC_INT_0 99
++#define ICBID_MASTER_SNOC_INT_1 100
++#define ICBID_MASTER_SNOC_INT_BIMC 101
++#define ICBID_MASTER_TCU_0 102
++#define ICBID_MASTER_TCU_1 103
++#define ICBID_MASTER_BIMC_INT_0 104
++#define ICBID_MASTER_BIMC_INT_1 105
++#define ICBID_MASTER_CAMERA 106
++#define ICBID_MASTER_RICA 107
++#define ICBID_MASTER_PCNOC_S_5        129
++#define ICBID_MASTER_PCNOC_INT_2      124
++#define ICBID_MASTER_PCNOC_INT_3      125
++#define ICBID_MASTER_PCNOC_INT_4      126
++#define ICBID_MASTER_PCNOC_INT_5      127
++#define ICBID_MASTER_PCNOC_INT_6      128
++#define ICBID_MASTER_PCIE_2 119
++#define ICBID_MASTER_MASTER_CNOC_A1NOC 116
++#define ICBID_MASTER_A0NOC_SNOC 110
++#define ICBID_MASTER_A1NOC_SNOC 111
++#define ICBID_MASTER_A2NOC_SNOC 112
++#define ICBID_MASTER_PNOC_A1NOC 117
++#define ICBID_MASTER_ROTATOR 120
++#define ICBID_MASTER_SNOC_VMEM 114
++#define ICBID_MASTER_VENUS_VMEM 121
++#define ICBID_MASTER_HMSS 118
++#define ICBID_MASTER_BIMC_SNOC_1 109
++#define ICBID_MASTER_CNOC_A1NOC 116
++#define ICBID_MASTER_CPP 115
++#define ICBID_MASTER_BLSP_BAM 130
++#define ICBID_MASTER_USB2_BAM 131
++#define ICBID_MASTER_ADSS_DMA0 132
++#define ICBID_MASTER_ADSS_DMA1 133
++#define ICBID_MASTER_ADSS_DMA2 134
++#define ICBID_MASTER_ADSS_DMA3 135
++#define ICBID_MASTER_QPIC_BAM 136
++#define ICBID_MASTER_SDCC_BAM 137
++#define ICBID_MASTER_DDRC_SNOC 138
++#define ICBID_MASTER_WSS_0 139
++#define ICBID_MASTER_WSS_1 140
++#define ICBID_MASTER_ESS 141
++#define ICBID_MASTER_PCIE 142
++#define ICBID_MASTER_QDSS_BAMNDP 143
++#define ICBID_MASTER_QDSS_SNOC_CFG 144
++
++#define ICBID_SLAVE_EBI1 0
++#define ICBID_SLAVE_APPSS_L2 1
++#define ICBID_SLAVE_BIMC_SNOC 2
++#define ICBID_SLAVE_CAMERA_CFG 3
++#define ICBID_SLAVE_DISPLAY_CFG 4
++#define ICBID_SLAVE_OCMEM_CFG 5
++#define ICBID_SLAVE_CPR_CFG 6
++#define ICBID_SLAVE_CPR_XPU_CFG 7
++#define ICBID_SLAVE_MISC_CFG 8
++#define ICBID_SLAVE_MISC_XPU_CFG 9
++#define ICBID_SLAVE_VENUS_CFG 10
++#define ICBID_SLAVE_GFX3D_CFG 11
++#define ICBID_SLAVE_MMSS_CLK_CFG 12
++#define ICBID_SLAVE_MMSS_CLK_XPU_CFG 13
++#define ICBID_SLAVE_MNOC_MPU_CFG 14
++#define ICBID_SLAVE_ONOC_MPU_CFG 15
++#define ICBID_SLAVE_MNOC_BIMC 16
++#define ICBID_SLAVE_SERVICE_MNOC 17
++#define ICBID_SLAVE_OCMEM 18
++#define ICBID_SLAVE_GMEM ICBID_SLAVE_OCMEM
++#define ICBID_SLAVE_SERVICE_ONOC 19
++#define ICBID_SLAVE_APPSS 20
++#define ICBID_SLAVE_LPASS 21
++#define ICBID_SLAVE_USB3 22
++#define ICBID_SLAVE_USB3_0 ICBID_SLAVE_USB3
++#define ICBID_SLAVE_WCSS 23
++#define ICBID_SLAVE_SNOC_BIMC 24
++#define ICBID_SLAVE_SNOC_BIMC_0 ICBID_SLAVE_SNOC_BIMC
++#define ICBID_SLAVE_SNOC_CNOC 25
++#define ICBID_SLAVE_IMEM 26
++#define ICBID_SLAVE_OCIMEM ICBID_SLAVE_IMEM
++#define ICBID_SLAVE_SNOC_OVIRT 27
++#define ICBID_SLAVE_SNOC_GVIRT ICBID_SLAVE_SNOC_OVIRT
++#define ICBID_SLAVE_SNOC_PNOC 28
++#define ICBID_SLAVE_SNOC_PCNOC ICBID_SLAVE_SNOC_PNOC
++#define ICBID_SLAVE_SERVICE_SNOC 29
++#define ICBID_SLAVE_QDSS_STM 30
++#define ICBID_SLAVE_SDCC_1 31
++#define ICBID_SLAVE_SDCC_3 32
++#define ICBID_SLAVE_SDCC_2 33
++#define ICBID_SLAVE_SDCC_4 34
++#define ICBID_SLAVE_TSIF 35
++#define ICBID_SLAVE_BAM_DMA 36
++#define ICBID_SLAVE_BLSP_2 37
++#define ICBID_SLAVE_USB_HSIC 38
++#define ICBID_SLAVE_BLSP_1 39
++#define ICBID_SLAVE_USB_HS 40
++#define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS
++#define ICBID_SLAVE_PDM 41
++#define ICBID_SLAVE_PERIPH_APU_CFG 42
++#define ICBID_SLAVE_PNOC_MPU_CFG 43
++#define ICBID_SLAVE_PRNG 44
++#define ICBID_SLAVE_PNOC_SNOC 45
++#define ICBID_SLAVE_PCNOC_SNOC ICBID_SLAVE_PNOC_SNOC
++#define ICBID_SLAVE_SERVICE_PNOC 46
++#define ICBID_SLAVE_CLK_CTL 47
++#define ICBID_SLAVE_CNOC_MSS 48
++#define ICBID_SLAVE_PCNOC_MSS ICBID_SLAVE_CNOC_MSS
++#define ICBID_SLAVE_SECURITY 49
++#define ICBID_SLAVE_TCSR 50
++#define ICBID_SLAVE_TLMM 51
++#define ICBID_SLAVE_CRYPTO_0_CFG 52
++#define ICBID_SLAVE_CRYPTO_1_CFG 53
++#define ICBID_SLAVE_IMEM_CFG 54
++#define ICBID_SLAVE_MESSAGE_RAM 55
++#define ICBID_SLAVE_BIMC_CFG 56
++#define ICBID_SLAVE_BOOT_ROM 57
++#define ICBID_SLAVE_CNOC_MNOC_MMSS_CFG 58
++#define ICBID_SLAVE_PMIC_ARB 59
++#define ICBID_SLAVE_SPDM_WRAPPER 60
++#define ICBID_SLAVE_DEHR_CFG 61
++#define ICBID_SLAVE_MPM 62
++#define ICBID_SLAVE_QDSS_CFG 63
++#define ICBID_SLAVE_RBCPR_CFG 64
++#define ICBID_SLAVE_RBCPR_CX_CFG ICBID_SLAVE_RBCPR_CFG
++#define ICBID_SLAVE_RBCPR_QDSS_APU_CFG 65
++#define ICBID_SLAVE_CNOC_MNOC_CFG 66
++#define ICBID_SLAVE_SNOC_MPU_CFG 67
++#define ICBID_SLAVE_CNOC_ONOC_CFG 68
++#define ICBID_SLAVE_PNOC_CFG 69
++#define ICBID_SLAVE_SNOC_CFG 70
++#define ICBID_SLAVE_EBI1_DLL_CFG 71
++#define ICBID_SLAVE_PHY_APU_CFG 72
++#define ICBID_SLAVE_EBI1_PHY_CFG 73
++#define ICBID_SLAVE_RPM 74
++#define ICBID_SLAVE_CNOC_SNOC 75
++#define ICBID_SLAVE_SERVICE_CNOC 76
++#define ICBID_SLAVE_OVIRT_SNOC 77
++#define ICBID_SLAVE_OVIRT_OCMEM 78
++#define ICBID_SLAVE_USB_HS2 79
++#define ICBID_SLAVE_QPIC 80
++#define ICBID_SLAVE_IPS_CFG 81
++#define ICBID_SLAVE_DSI_CFG 82
++#define ICBID_SLAVE_USB3_1 83
++#define ICBID_SLAVE_PCIE_0 84
++#define ICBID_SLAVE_PCIE_1 85
++#define ICBID_SLAVE_PSS_SMMU_CFG 86
++#define ICBID_SLAVE_CRYPTO_2_CFG 87
++#define ICBID_SLAVE_PCIE_0_CFG 88
++#define ICBID_SLAVE_PCIE_1_CFG 89
++#define ICBID_SLAVE_SATA_CFG 90
++#define ICBID_SLAVE_SPSS_GENI_IR 91
++#define ICBID_SLAVE_UFS_CFG 92
++#define ICBID_SLAVE_AVSYNC_CFG 93
++#define ICBID_SLAVE_VPU_CFG 94
++#define ICBID_SLAVE_USB_PHY_CFG 95
++#define ICBID_SLAVE_RBCPR_MX_CFG 96
++#define ICBID_SLAVE_PCIE_PARF 97
++#define ICBID_SLAVE_VCAP_CFG 98
++#define ICBID_SLAVE_EMAC_CFG 99
++#define ICBID_SLAVE_BCAST_CFG 100
++#define ICBID_SLAVE_KLM_CFG 101
++#define ICBID_SLAVE_DISPLAY_PWM 102
++#define ICBID_SLAVE_GENI 103
++#define ICBID_SLAVE_SNOC_BIMC_1 104
++#define ICBID_SLAVE_AUDIO 105
++#define ICBID_SLAVE_CATS_0 106
++#define ICBID_SLAVE_CATS_1 107
++#define ICBID_SLAVE_MM_INT_0 108
++#define ICBID_SLAVE_MM_INT_1 109
++#define ICBID_SLAVE_MM_INT_2 110
++#define ICBID_SLAVE_MM_INT_BIMC 111
++#define ICBID_SLAVE_MMU_MODEM_XPU_CFG 112
++#define ICBID_SLAVE_MSS_INT 113
++#define ICBID_SLAVE_PCNOC_INT_0 114
++#define ICBID_SLAVE_PCNOC_INT_1 115
++#define ICBID_SLAVE_PCNOC_M_0 116
++#define ICBID_SLAVE_PCNOC_M_1 117
++#define ICBID_SLAVE_PCNOC_S_0 118
++#define ICBID_SLAVE_PCNOC_S_1 119
++#define ICBID_SLAVE_PCNOC_S_2 120
++#define ICBID_SLAVE_PCNOC_S_3 121
++#define ICBID_SLAVE_PCNOC_S_4 122
++#define ICBID_SLAVE_PCNOC_S_6 123
++#define ICBID_SLAVE_PCNOC_S_7 124
++#define ICBID_SLAVE_PCNOC_S_8 125
++#define ICBID_SLAVE_PCNOC_S_9 126
++#define ICBID_SLAVE_PRNG_XPU_CFG 127
++#define ICBID_SLAVE_QDSS_INT 128
++#define ICBID_SLAVE_RPM_XPU_CFG 129
++#define ICBID_SLAVE_SNOC_INT_0 130
++#define ICBID_SLAVE_SNOC_INT_1 131
++#define ICBID_SLAVE_SNOC_INT_BIMC 132
++#define ICBID_SLAVE_TCU 133
++#define ICBID_SLAVE_BIMC_INT_0 134
++#define ICBID_SLAVE_BIMC_INT_1 135
++#define ICBID_SLAVE_RICA_CFG 136
++#define ICBID_SLAVE_PCNOC_S_5 189
++#define ICBID_SLAVE_PCNOC_S_7 124
++#define ICBID_SLAVE_PCNOC_INT_2 184
++#define ICBID_SLAVE_PCNOC_INT_3 185
++#define ICBID_SLAVE_PCNOC_INT_4 186
++#define ICBID_SLAVE_PCNOC_INT_5 187
++#define ICBID_SLAVE_PCNOC_INT_6 188
++#define ICBID_SLAVE_USB3_PHY_CFG 182
++#define ICBID_SLAVE_IPA_CFG 183
++
++#define ICBID_SLAVE_A0NOC_SNOC 141
++#define ICBID_SLAVE_A1NOC_SNOC 142
++#define ICBID_SLAVE_A2NOC_SNOC 143
++#define ICBID_SLAVE_BIMC_SNOC_1 138
++#define ICBID_SLAVE_PIMEM 167
++#define ICBID_SLAVE_PIMEM_CFG 168
++#define ICBID_SLAVE_DCC_CFG 155
++#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168
++#define ICBID_SLAVE_A0NOC_CFG 144
++#define ICBID_SLAVE_PCIE_2_CFG 165
++#define ICBID_SLAVE_PCIE20_AHB2PHY 163
++#define ICBID_SLAVE_PCIE_2 164
++#define ICBID_SLAVE_A1NOC_CFG 147
++#define ICBID_SLAVE_A1NOC_MPU_CFG 148
++#define ICBID_SLAVE_A1NOC_SMMU_CFG 149
++#define ICBID_SLAVE_A2NOC_CFG 150
++#define ICBID_SLAVE_A2NOC_MPU_CFG 151
++#define ICBID_SLAVE_A2NOC_SMMU_CFG 152
++#define ICBID_SLAVE_AHB2PHY 153
++#define ICBID_SLAVE_HMSS_L3 161
++#define ICBID_SLAVE_LPASS_SMMU_CFG 161
++#define ICBID_SLAVE_MMAGIC_CFG 162
++#define ICBID_SLAVE_SSC_CFG 177
++#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178
++#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156
++#define ICBID_SLAVE_CAMERA_THROTTLE_CFG 154
++#define ICBID_SLAVE_DSA_CFG 157
++#define ICBID_SLAVE_DSA_MPU_CFG 158
++#define ICBID_SLAVE_SMMU_CPP_CFG 171
++#define ICBID_SLAVE_SMMU_JPEG_CFG 172
++#define ICBID_SLAVE_SMMU_MDP_CFG 173
++#define ICBID_SLAVE_SMMU_ROTATOR_CFG 174
++#define ICBID_SLAVE_SMMU_VENUS_CFG 175
++#define ICBID_SLAVE_SMMU_VFE_CFG 176
++#define ICBID_SLAVE_A0NOC_MPU_CFG 145
++#define ICBID_SLAVE_A0NOC_SMMU_CFG 146
++#define ICBID_SLAVE_VMEM_CFG 180
++#define ICBID_SLAVE_VMEM 179
++#define ICBID_SLAVE_PNOC_A1NOC 139
++#define ICBID_SLAVE_SNOC_VMEM 140
++#define ICBID_SLAVE_RBCPR_MX 170
++#define ICBID_SLAVE_RBCPR_CX 169
++#define ICBID_SLAVE_PRNG_APU_CFG 190
++#define ICBID_SLAVE_PERIPH_MPU_CFG 191
++#define ICBID_SLAVE_GCNT 192
++#define ICBID_SLAVE_ADSS_CFG 193
++#define ICBID_SLAVE_ADSS_APU 194
++#define ICBID_SLAVE_ADSS_VMIDMT_CFG 195
++#define ICBID_SLAVE_QHSS_APU_CFG 196
++#define ICBID_SLAVE_MDIO 197
++#define ICBID_SLAVE_FEPHY_CFG 198
++#define ICBID_SLAVE_SRIF 199
++#define ICBID_SLAVE_DDRC_CFG 200
++#define ICBID_SLAVE_DDRC_APU_CFG 201
++#define ICBID_SLAVE_DDRC_MPU0_CFG 202
++#define ICBID_SLAVE_DDRC_MPU1_CFG 203
++#define ICBID_SLAVE_DDRC_MPU2_CFG 210
++#define ICBID_SLAVE_ESS_VMIDMT_CFG 211
++#define ICBID_SLAVE_ESS_APU_CFG 212
++#define ICBID_SLAVE_USB2_CFG 213
++#define ICBID_SLAVE_BLSP_CFG 214
++#define ICBID_SLAVE_QPIC_CFG 215
++#define ICBID_SLAVE_SDCC_CFG 216
++#define ICBID_SLAVE_WSS0_VMIDMT_CFG 217
++#define ICBID_SLAVE_WSS0_APU_CFG 218
++#define ICBID_SLAVE_WSS1_VMIDMT_CFG 219
++#define ICBID_SLAVE_WSS1_APU_CFG 220
++#define ICBID_SLAVE_SRVC_PCNOC 221
++#define ICBID_SLAVE_SNOC_DDRC 222
++#define ICBID_SLAVE_A7SS 223
++#define ICBID_SLAVE_WSS0_CFG 224
++#define ICBID_SLAVE_WSS1_CFG 225
++#define ICBID_SLAVE_PCIE 226
++#define ICBID_SLAVE_USB3_CFG 227
++#define ICBID_SLAVE_CRYPTO_CFG 228
++#define ICBID_SLAVE_ESS_CFG 229
++#define ICBID_SLAVE_SRVC_SNOC 230
++#endif
+--- /dev/null
++++ b/include/dt-bindings/msm/msm-bus-rule-ops.h
+@@ -0,0 +1,32 @@
++/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef __MSM_BUS_RULE_OPS_H
++#define __MSM_BUS_RULE_OPS_H
++
++#define FLD_IB        0
++#define FLD_AB        1
++#define FLD_CLK       2
++
++#define OP_LE 0
++#define OP_LT 1
++#define OP_GE 2
++#define OP_GT 3
++#define OP_NOOP       4
++
++#define RULE_STATE_NOT_APPLIED        0
++#define RULE_STATE_APPLIED    1
++
++#define THROTTLE_ON   0
++#define THROTTLE_OFF  1
++
++#endif
+--- /dev/null
++++ b/drivers/bus/msm_bus/Kconfig
+@@ -0,0 +1,19 @@
++config BUS_TOPOLOGY_ADHOC
++      bool "ad-hoc bus scaling topology"
++      depends on ARCH_QCOM
++      default n
++      help
++        This option enables a driver that can handle adhoc bus topologies.
++        Adhoc bus topology driver allows one to many connections and maintains
++        directionality of connections by explicitly listing device connections
++        thus avoiding illegal routes.
++
++config MSM_BUS_SCALING
++      bool "Bus scaling driver"
++      depends on BUS_TOPOLOGY_ADHOC
++      default n
++      help
++        This option enables bus scaling on MSM devices.  Bus scaling
++        allows devices to request the clocks be set to rates sufficient
++        for the active devices needs without keeping the clocks at max
++        frequency when a slower speed is sufficient.
+--- /dev/null
++++ b/drivers/bus/msm_bus/Makefile
+@@ -0,0 +1,12 @@
++#
++# Makefile for msm-bus driver specific files
++#
++obj-y += msm_bus_bimc.o msm_bus_noc.o msm_bus_core.o msm_bus_client_api.o \
++       msm_bus_id.o
++obj-$(CONFIG_OF) += msm_bus_of.o
++
++obj-y += msm_bus_fabric_adhoc.o msm_bus_arb_adhoc.o msm_bus_rules.o
++obj-$(CONFIG_OF) += msm_bus_of_adhoc.o
++obj-$(CONFIG_CORESIGHT) +=  msm_buspm_coresight_adhoc.o
++
++obj-$(CONFIG_DEBUG_FS) += msm_bus_dbg.o
+--- /dev/null
++++ b/drivers/bus/msm_bus/msm-bus-board.h
+@@ -0,0 +1,198 @@
++/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef __ASM_ARCH_MSM_BUS_BOARD_H
++#define __ASM_ARCH_MSM_BUS_BOARD_H
++
++#include <linux/types.h>
++#include <linux/input.h>
++
++enum context {
++      DUAL_CTX,
++      ACTIVE_CTX,
++      NUM_CTX
++};
++
++struct msm_bus_fabric_registration {
++      unsigned int id;
++      const char *name;
++      struct msm_bus_node_info *info;
++      unsigned int len;
++      int ahb;
++      const char *fabclk[NUM_CTX];
++      const char *iface_clk;
++      unsigned int offset;
++      unsigned int haltid;
++      unsigned int rpm_enabled;
++      unsigned int nmasters;
++      unsigned int nslaves;
++      unsigned int ntieredslaves;
++      bool il_flag;
++      const struct msm_bus_board_algorithm *board_algo;
++      int hw_sel;
++      void *hw_data;
++      uint32_t qos_freq;
++      uint32_t qos_baseoffset;
++      u64 nr_lim_thresh;
++      uint32_t eff_fact;
++      uint32_t qos_delta;
++      bool virt;
++};
++
++struct msm_bus_device_node_registration {
++      struct msm_bus_node_device_type *info;
++      unsigned int num_devices;
++      bool virt;
++};
++
++enum msm_bus_bw_tier_type {
++      MSM_BUS_BW_TIER1 = 1,
++      MSM_BUS_BW_TIER2,
++      MSM_BUS_BW_COUNT,
++      MSM_BUS_BW_SIZE = 0x7FFFFFFF,
++};
++
++struct msm_bus_halt_vector {
++      uint32_t haltval;
++      uint32_t haltmask;
++};
++
++extern struct msm_bus_fabric_registration msm_bus_apps_fabric_pdata;
++extern struct msm_bus_fabric_registration msm_bus_sys_fabric_pdata;
++extern struct msm_bus_fabric_registration msm_bus_mm_fabric_pdata;
++extern struct msm_bus_fabric_registration msm_bus_sys_fpb_pdata;
++extern struct msm_bus_fabric_registration msm_bus_cpss_fpb_pdata;
++extern struct msm_bus_fabric_registration msm_bus_def_fab_pdata;
++
++extern struct msm_bus_fabric_registration msm_bus_8960_apps_fabric_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8960_sys_fabric_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8960_mm_fabric_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8960_sg_mm_fabric_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8960_sys_fpb_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8960_cpss_fpb_pdata;
++
++extern struct msm_bus_fabric_registration msm_bus_8064_apps_fabric_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8064_sys_fabric_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8064_mm_fabric_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8064_sys_fpb_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8064_cpss_fpb_pdata;
++
++extern struct msm_bus_fabric_registration msm_bus_9615_sys_fabric_pdata;
++extern struct msm_bus_fabric_registration msm_bus_9615_def_fab_pdata;
++
++extern struct msm_bus_fabric_registration msm_bus_8930_apps_fabric_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8930_sys_fabric_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8930_mm_fabric_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8930_sys_fpb_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8930_cpss_fpb_pdata;
++
++extern struct msm_bus_fabric_registration msm_bus_8974_sys_noc_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8974_mmss_noc_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8974_bimc_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8974_ocmem_noc_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8974_periph_noc_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8974_config_noc_pdata;
++extern struct msm_bus_fabric_registration msm_bus_8974_ocmem_vnoc_pdata;
++
++extern struct msm_bus_fabric_registration msm_bus_9625_sys_noc_pdata;
++extern struct msm_bus_fabric_registration msm_bus_9625_bimc_pdata;
++extern struct msm_bus_fabric_registration msm_bus_9625_periph_noc_pdata;
++extern struct msm_bus_fabric_registration msm_bus_9625_config_noc_pdata;
++
++extern int msm_bus_device_match_adhoc(struct device *dev, void *id);
++
++void msm_bus_rpm_set_mt_mask(void);
++int msm_bus_board_rpm_get_il_ids(uint16_t *id);
++int msm_bus_board_get_iid(int id);
++
++#define NFAB_MSM8226 6
++#define NFAB_MSM8610 5
++
++/*
++ * These macros specify the convention followed for allocating
++ * ids to fabrics, masters and slaves for 8x60.
++ *
++ * A node can be identified as a master/slave/fabric by using
++ * these ids.
++ */
++#define FABRIC_ID_KEY 1024
++#define SLAVE_ID_KEY ((FABRIC_ID_KEY) >> 1)
++#define MAX_FAB_KEY 7168  /* OR(All fabric ids) */
++#define INT_NODE_START 10000
++
++#define GET_FABID(id) ((id) & MAX_FAB_KEY)
++
++#define NODE_ID(id) ((id) & (FABRIC_ID_KEY - 1))
++#define IS_SLAVE(id) ((NODE_ID(id)) >= SLAVE_ID_KEY ? 1 : 0)
++#define CHECK_ID(iid, id) (((iid & id) != id) ? -ENXIO : iid)
++
++/*
++ * The following macros are used to format the data for port halt
++ * and unhalt requests.
++ */
++#define MSM_BUS_CLK_HALT 0x1
++#define MSM_BUS_CLK_HALT_MASK 0x1
++#define MSM_BUS_CLK_HALT_FIELDSIZE 0x1
++#define MSM_BUS_CLK_UNHALT 0x0
++
++#define MSM_BUS_MASTER_SHIFT(master, fieldsize) \
++      ((master) * (fieldsize))
++
++#define MSM_BUS_SET_BITFIELD(word, fieldmask, fieldvalue) \
++      {       \
++              (word) &= ~(fieldmask); \
++              (word) |= (fieldvalue); \
++      }
++
++
++#define MSM_BUS_MASTER_HALT(u32haltmask, u32haltval, master) \
++      MSM_BUS_SET_BITFIELD(u32haltmask, \
++              MSM_BUS_CLK_HALT_MASK<<MSM_BUS_MASTER_SHIFT((master),\
++              MSM_BUS_CLK_HALT_FIELDSIZE), \
++              MSM_BUS_CLK_HALT_MASK<<MSM_BUS_MASTER_SHIFT((master),\
++              MSM_BUS_CLK_HALT_FIELDSIZE))\
++      MSM_BUS_SET_BITFIELD(u32haltval, \
++              MSM_BUS_CLK_HALT_MASK<<MSM_BUS_MASTER_SHIFT((master),\
++              MSM_BUS_CLK_HALT_FIELDSIZE), \
++              MSM_BUS_CLK_HALT<<MSM_BUS_MASTER_SHIFT((master),\
++              MSM_BUS_CLK_HALT_FIELDSIZE))\
++
++#define MSM_BUS_MASTER_UNHALT(u32haltmask, u32haltval, master) \
++      MSM_BUS_SET_BITFIELD(u32haltmask, \
++              MSM_BUS_CLK_HALT_MASK<<MSM_BUS_MASTER_SHIFT((master),\
++              MSM_BUS_CLK_HALT_FIELDSIZE), \
++              MSM_BUS_CLK_HALT_MASK<<MSM_BUS_MASTER_SHIFT((master),\
++              MSM_BUS_CLK_HALT_FIELDSIZE))\
++      MSM_BUS_SET_BITFIELD(u32haltval, \
++              MSM_BUS_CLK_HALT_MASK<<MSM_BUS_MASTER_SHIFT((master),\
++              MSM_BUS_CLK_HALT_FIELDSIZE), \
++              MSM_BUS_CLK_UNHALT<<MSM_BUS_MASTER_SHIFT((master),\
++              MSM_BUS_CLK_HALT_FIELDSIZE))\
++
++#define RPM_BUS_SLAVE_REQ     0x766c7362
++#define RPM_BUS_MASTER_REQ    0x73616d62
++
++enum msm_bus_rpm_slave_field_type {
++      RPM_SLAVE_FIELD_BW = 0x00007762,
++};
++
++enum msm_bus_rpm_mas_field_type {
++      RPM_MASTER_FIELD_BW =           0x00007762,
++      RPM_MASTER_FIELD_BW_T0 =        0x30747762,
++      RPM_MASTER_FIELD_BW_T1 =        0x31747762,
++      RPM_MASTER_FIELD_BW_T2 =        0x32747762,
++};
++
++#include <dt-bindings/msm/msm-bus-ids.h>
++
++
++#endif /*__ASM_ARCH_MSM_BUS_BOARD_H */
+--- /dev/null
++++ b/drivers/bus/msm_bus/msm-bus.h
+@@ -0,0 +1,139 @@
++/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _ARCH_ARM_MACH_MSM_BUS_H
++#define _ARCH_ARM_MACH_MSM_BUS_H
++
++#include <linux/types.h>
++#include <linux/input.h>
++#include <linux/platform_device.h>
++
++/*
++ * Macros for clients to convert their data to ib and ab
++ * Ws : Time window over which to transfer the data in SECONDS
++ * Bs : Size of the data block in bytes
++ * Per : Recurrence period
++ * Tb : Throughput bandwidth to prevent stalling
++ * R  : Ratio of actual bandwidth used to Tb
++ * Ib : Instantaneous bandwidth
++ * Ab : Arbitrated bandwidth
++ *
++ * IB_RECURRBLOCK and AB_RECURRBLOCK:
++ * These are used if the requirement is to transfer a
++ * recurring block of data over a known time window.
++ *
++ * IB_THROUGHPUTBW and AB_THROUGHPUTBW:
++ * These are used for CPU style masters. Here the requirement
++ * is to have minimum throughput bandwidth available to avoid
++ * stalling.
++ */
++#define IB_RECURRBLOCK(Ws, Bs) ((Ws) == 0 ? 0 : ((Bs)/(Ws)))
++#define AB_RECURRBLOCK(Ws, Per) ((Ws) == 0 ? 0 : ((Bs)/(Per)))
++#define IB_THROUGHPUTBW(Tb) (Tb)
++#define AB_THROUGHPUTBW(Tb, R) ((Tb) * (R))
++
++struct msm_bus_vectors {
++      int src; /* Master */
++      int dst; /* Slave */
++      uint64_t ab; /* Arbitrated bandwidth */
++      uint64_t ib; /* Instantaneous bandwidth */
++};
++
++struct msm_bus_paths {
++      int num_paths;
++      struct msm_bus_vectors *vectors;
++};
++
++struct msm_bus_scale_pdata {
++      struct msm_bus_paths *usecase;
++      int num_usecases;
++      const char *name;
++      /*
++       * If the active_only flag is set to 1, the BW request is applied
++       * only when at least one CPU is active (powered on). If the flag
++       * is set to 0, then the BW request is always applied irrespective
++       * of the CPU state.
++       */
++      unsigned int active_only;
++};
++
++/* Scaling APIs */
++
++/*
++ * This function returns a handle to the client. This should be used to
++ * call msm_bus_scale_client_update_request.
++ * The function returns 0 if bus driver is unable to register a client
++ */
++
++#if (defined(CONFIG_MSM_BUS_SCALING) || defined(CONFIG_BUS_TOPOLOGY_ADHOC))
++int __init msm_bus_fabric_init_driver(void);
++uint32_t msm_bus_scale_register_client(struct msm_bus_scale_pdata *pdata);
++int msm_bus_scale_client_update_request(uint32_t cl, unsigned int index);
++void msm_bus_scale_unregister_client(uint32_t cl);
++/* AXI Port configuration APIs */
++int msm_bus_axi_porthalt(int master_port);
++int msm_bus_axi_portunhalt(int master_port);
++
++#else
++static inline int __init msm_bus_fabric_init_driver(void) { return 0; }
++
++static inline uint32_t
++msm_bus_scale_register_client(struct msm_bus_scale_pdata *pdata)
++{
++      return 1;
++}
++
++static inline int
++msm_bus_scale_client_update_request(uint32_t cl, unsigned int index)
++{
++      return 0;
++}
++
++static inline void
++msm_bus_scale_unregister_client(uint32_t cl)
++{
++}
++
++static inline int msm_bus_axi_porthalt(int master_port)
++{
++      return 0;
++}
++
++static inline int msm_bus_axi_portunhalt(int master_port)
++{
++      return 0;
++}
++#endif
++
++#if defined(CONFIG_OF) && defined(CONFIG_MSM_BUS_SCALING)
++struct msm_bus_scale_pdata *msm_bus_pdata_from_node(
++              struct platform_device *pdev, struct device_node *of_node);
++struct msm_bus_scale_pdata *msm_bus_cl_get_pdata(struct platform_device *pdev);
++void msm_bus_cl_clear_pdata(struct msm_bus_scale_pdata *pdata);
++#else
++static inline struct msm_bus_scale_pdata
++*msm_bus_cl_get_pdata(struct platform_device *pdev)
++{
++      return NULL;
++}
++
++static inline struct msm_bus_scale_pdata *msm_bus_pdata_from_node(
++              struct platform_device *pdev, struct device_node *of_node)
++{
++      return NULL;
++}
++
++static inline void msm_bus_cl_clear_pdata(struct msm_bus_scale_pdata *pdata)
++{
++}
++#endif
++#endif /*_ARCH_ARM_MACH_MSM_BUS_H*/
+--- /dev/null
++++ b/drivers/bus/msm_bus/msm_bus_adhoc.h
+@@ -0,0 +1,141 @@
++/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _ARCH_ARM_MACH_MSM_BUS_ADHOC_H
++#define _ARCH_ARM_MACH_MSM_BUS_ADHOC_H
++
++#include <linux/types.h>
++#include <linux/device.h>
++#include "msm-bus-board.h"
++#include "msm-bus.h"
++#include "msm_bus_rules.h"
++#include "msm_bus_core.h"
++
++struct msm_bus_node_device_type;
++struct link_node {
++      uint64_t lnode_ib[NUM_CTX];
++      uint64_t lnode_ab[NUM_CTX];
++      int next;
++      struct device *next_dev;
++      struct list_head link;
++      uint32_t in_use;
++};
++
++/* New types introduced for adhoc topology */
++struct msm_bus_noc_ops {
++      int (*qos_init)(struct msm_bus_node_device_type *dev,
++                      void __iomem *qos_base, uint32_t qos_off,
++                      uint32_t qos_delta, uint32_t qos_freq);
++      int (*set_bw)(struct msm_bus_node_device_type *dev,
++                      void __iomem *qos_base, uint32_t qos_off,
++                      uint32_t qos_delta, uint32_t qos_freq);
++      int (*limit_mport)(struct msm_bus_node_device_type *dev,
++                      void __iomem *qos_base, uint32_t qos_off,
++                      uint32_t qos_delta, uint32_t qos_freq, bool enable_lim,
++                      uint64_t lim_bw);
++      bool (*update_bw_reg)(int mode);
++};
++
++struct nodebw {
++      uint64_t ab[NUM_CTX];
++      bool dirty;
++};
++
++struct msm_bus_fab_device_type {
++      void __iomem *qos_base;
++      phys_addr_t pqos_base;
++      size_t qos_range;
++      uint32_t base_offset;
++      uint32_t qos_freq;
++      uint32_t qos_off;
++      uint32_t util_fact;
++      uint32_t vrail_comp;
++      struct msm_bus_noc_ops noc_ops;
++      enum msm_bus_hw_sel bus_type;
++      bool bypass_qos_prg;
++};
++
++struct qos_params_type {
++      int mode;
++      unsigned int prio_lvl;
++      unsigned int prio_rd;
++      unsigned int prio_wr;
++      unsigned int prio1;
++      unsigned int prio0;
++      unsigned int gp;
++      unsigned int thmp;
++      unsigned int ws;
++      int cur_mode;
++      u64 bw_buffer;
++};
++
++struct msm_bus_node_info_type {
++      const char *name;
++      unsigned int id;
++      int mas_rpm_id;
++      int slv_rpm_id;
++      int num_ports;
++      int num_qports;
++      int *qport;
++      struct qos_params_type qos_params;
++      unsigned int num_connections;
++      unsigned int num_blist;
++      bool is_fab_dev;
++      bool virt_dev;
++      bool is_traversed;
++      unsigned int *connections;
++      unsigned int *black_listed_connections;
++      struct device **dev_connections;
++      struct device **black_connections;
++      unsigned int bus_device_id;
++      struct device *bus_device;
++      unsigned int buswidth;
++      struct rule_update_path_info rule;
++      uint64_t lim_bw;
++      uint32_t util_fact;
++      uint32_t vrail_comp;
++};
++
++struct msm_bus_node_device_type {
++      struct msm_bus_node_info_type *node_info;
++      struct msm_bus_fab_device_type *fabdev;
++      int num_lnodes;
++      struct link_node *lnode_list;
++      uint64_t cur_clk_hz[NUM_CTX];
++      struct nodebw node_ab;
++      struct list_head link;
++      unsigned int ap_owned;
++      struct nodeclk clk[NUM_CTX];
++      struct nodeclk qos_clk;
++};
++
++int msm_bus_enable_limiter(struct msm_bus_node_device_type *nodedev,
++                              bool throttle_en, uint64_t lim_bw);
++int msm_bus_update_clks(struct msm_bus_node_device_type *nodedev,
++      int ctx, int **dirty_nodes, int *num_dirty);
++int msm_bus_commit_data(int *dirty_nodes, int ctx, int num_dirty);
++int msm_bus_update_bw(struct msm_bus_node_device_type *nodedev, int ctx,
++      int64_t add_bw, int **dirty_nodes, int *num_dirty);
++void *msm_bus_realloc_devmem(struct device *dev, void *p, size_t old_size,
++                                      size_t new_size, gfp_t flags);
++
++extern struct msm_bus_device_node_registration
++      *msm_bus_of_to_pdata(struct platform_device *pdev);
++extern void msm_bus_arb_setops_adhoc(struct msm_bus_arb_ops *arb_ops);
++extern int msm_bus_bimc_set_ops(struct msm_bus_node_device_type *bus_dev);
++extern int msm_bus_noc_set_ops(struct msm_bus_node_device_type *bus_dev);
++extern int msm_bus_of_get_static_rules(struct platform_device *pdev,
++                                      struct bus_rule_type **static_rule);
++extern int msm_rules_update_path(struct list_head *input_list,
++                              struct list_head *output_list);
++extern void print_all_rules(void);
++#endif /* _ARCH_ARM_MACH_MSM_BUS_ADHOC_H */
+--- /dev/null
++++ b/drivers/bus/msm_bus/msm_bus_arb_adhoc.c
+@@ -0,0 +1,998 @@
++/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
++ *
++ * This program is Mree software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/list.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/mutex.h>
++#include <linux/clk.h>
++#include "msm-bus.h"
++#include "msm_bus_core.h"
++#include "msm_bus_adhoc.h"
++
++#define NUM_CL_HANDLES        50
++#define NUM_LNODES    3
++
++struct bus_search_type {
++      struct list_head link;
++      struct list_head node_list;
++};
++
++struct handle_type {
++      int num_entries;
++      struct msm_bus_client **cl_list;
++};
++
++static struct handle_type handle_list;
++struct list_head input_list;
++struct list_head apply_list;
++
++DEFINE_MUTEX(msm_bus_adhoc_lock);
++
++static bool chk_bl_list(struct list_head *black_list, unsigned int id)
++{
++      struct msm_bus_node_device_type *bus_node = NULL;
++
++      list_for_each_entry(bus_node, black_list, link) {
++              if (bus_node->node_info->id == id)
++                      return true;
++      }
++      return false;
++}
++
++static void copy_remaining_nodes(struct list_head *edge_list, struct list_head
++      *traverse_list, struct list_head *route_list)
++{
++      struct bus_search_type *search_node;
++
++      if (list_empty(edge_list) && list_empty(traverse_list))
++              return;
++
++      search_node = kzalloc(sizeof(struct bus_search_type), GFP_KERNEL);
++      INIT_LIST_HEAD(&search_node->node_list);
++      list_splice_init(edge_list, traverse_list);
++      list_splice_init(traverse_list, &search_node->node_list);
++      list_add_tail(&search_node->link, route_list);
++}
++
++/*
++ * Duplicate instantiaion from msm_bus_arb.c. Todo there needs to be a
++ * "util" file for these common func/macros.
++ *
++ * */
++uint64_t msm_bus_div64(unsigned int w, uint64_t bw)
++{
++      uint64_t *b = &bw;
++
++      if ((bw > 0) && (bw < w))
++              return 1;
++
++      switch (w) {
++      case 0:
++              WARN(1, "AXI: Divide by 0 attempted\n");
++      case 1: return bw;
++      case 2: return (bw >> 1);
++      case 4: return (bw >> 2);
++      case 8: return (bw >> 3);
++      case 16: return (bw >> 4);
++      case 32: return (bw >> 5);
++      }
++
++      do_div(*b, w);
++      return *b;
++}
++
++int msm_bus_device_match_adhoc(struct device *dev, void *id)
++{
++      int ret = 0;
++      struct msm_bus_node_device_type *bnode = dev->platform_data;
++
++      if (bnode)
++              ret = (bnode->node_info->id == *(unsigned int *)id);
++      else
++              ret = 0;
++
++      return ret;
++}
++
++static int gen_lnode(struct device *dev,
++                      int next_hop, int prev_idx)
++{
++      struct link_node *lnode;
++      struct msm_bus_node_device_type *cur_dev = NULL;
++      int lnode_idx = -1;
++
++      if (!dev)
++              goto exit_gen_lnode;
++
++      cur_dev = dev->platform_data;
++      if (!cur_dev) {
++              MSM_BUS_ERR("%s: Null device ptr", __func__);
++              goto exit_gen_lnode;
++      }
++
++      if (!cur_dev->num_lnodes) {
++              cur_dev->lnode_list = devm_kzalloc(dev,
++                              sizeof(struct link_node) * NUM_LNODES,
++                                                              GFP_KERNEL);
++              if (!cur_dev->lnode_list)
++                      goto exit_gen_lnode;
++
++              lnode = cur_dev->lnode_list;
++              cur_dev->num_lnodes = NUM_LNODES;
++              lnode_idx = 0;
++      } else {
++              int i;
++              for (i = 0; i < cur_dev->num_lnodes; i++) {
++                      if (!cur_dev->lnode_list[i].in_use)
++                              break;
++              }
++
++              if (i < cur_dev->num_lnodes) {
++                      lnode = &cur_dev->lnode_list[i];
++                      lnode_idx = i;
++              } else {
++                      struct link_node *realloc_list;
++                      size_t cur_size = sizeof(struct link_node) *
++                                      cur_dev->num_lnodes;
++
++                      cur_dev->num_lnodes += NUM_LNODES;
++                      realloc_list = msm_bus_realloc_devmem(
++                                      dev,
++                                      cur_dev->lnode_list,
++                                      cur_size,
++                                      sizeof(struct link_node) *
++                                      cur_dev->num_lnodes, GFP_KERNEL);
++
++                      if (!realloc_list)
++                              goto exit_gen_lnode;
++
++                      cur_dev->lnode_list = realloc_list;
++                      lnode = &cur_dev->lnode_list[i];
++                      lnode_idx = i;
++              }
++      }
++
++      lnode->in_use = 1;
++      if (next_hop == cur_dev->node_info->id) {
++              lnode->next = -1;
++              lnode->next_dev = NULL;
++      } else {
++              lnode->next = prev_idx;
++              lnode->next_dev = bus_find_device(&msm_bus_type, NULL,
++                                      (void *) &next_hop,
++                                      msm_bus_device_match_adhoc);
++      }
++
++      memset(lnode->lnode_ib, 0, sizeof(uint64_t) * NUM_CTX);
++      memset(lnode->lnode_ab, 0, sizeof(uint64_t) * NUM_CTX);
++
++exit_gen_lnode:
++      return lnode_idx;
++}
++
++static int remove_lnode(struct msm_bus_node_device_type *cur_dev,
++                              int lnode_idx)
++{
++      int ret = 0;
++
++      if (!cur_dev) {
++              MSM_BUS_ERR("%s: Null device ptr", __func__);
++              ret = -ENODEV;
++              goto exit_remove_lnode;
++      }
++
++      if (lnode_idx != -1) {
++              if (!cur_dev->num_lnodes ||
++                              (lnode_idx > (cur_dev->num_lnodes - 1))) {
++                      MSM_BUS_ERR("%s: Invalid Idx %d, num_lnodes %d",
++                              __func__, lnode_idx, cur_dev->num_lnodes);
++                      ret = -ENODEV;
++                      goto exit_remove_lnode;
++              }
++
++              cur_dev->lnode_list[lnode_idx].next = -1;
++              cur_dev->lnode_list[lnode_idx].next_dev = NULL;
++              cur_dev->lnode_list[lnode_idx].in_use = 0;
++      }
++
++exit_remove_lnode:
++      return ret;
++}
++
++static int prune_path(struct list_head *route_list, int dest, int src,
++                              struct list_head *black_list, int found)
++{
++      struct bus_search_type *search_node, *temp_search_node;
++      struct msm_bus_node_device_type *bus_node;
++      struct list_head *bl_list;
++      struct list_head *temp_bl_list;
++      int search_dev_id = dest;
++      struct device *dest_dev = bus_find_device(&msm_bus_type, NULL,
++                                      (void *) &dest,
++                                      msm_bus_device_match_adhoc);
++      int lnode_hop = -1;
++
++      if (!found)
++              goto reset_links;
++
++      if (!dest_dev) {
++              MSM_BUS_ERR("%s: Can't find dest dev %d", __func__, dest);
++              goto exit_prune_path;
++      }
++
++      lnode_hop = gen_lnode(dest_dev, search_dev_id, lnode_hop);
++
++      list_for_each_entry_reverse(search_node, route_list, link) {
++              list_for_each_entry(bus_node, &search_node->node_list, link) {
++                      unsigned int i;
++                      for (i = 0; i < bus_node->node_info->num_connections;
++                                                                      i++) {
++                              if (bus_node->node_info->connections[i] ==
++                                                              search_dev_id) {
++                                      dest_dev = bus_find_device(
++                                              &msm_bus_type,
++                                              NULL,
++                                              (void *)
++                                              &bus_node->node_info->
++                                              id,
++                                              msm_bus_device_match_adhoc);
++
++                                      if (!dest_dev) {
++                                              lnode_hop = -1;
++                                              goto reset_links;
++                                      }
++
++                                      lnode_hop = gen_lnode(dest_dev,
++                                                      search_dev_id,
++                                                      lnode_hop);
++                                      search_dev_id =
++                                              bus_node->node_info->id;
++                                      break;
++                              }
++                      }
++              }
++      }
++reset_links:
++      list_for_each_entry_safe(search_node, temp_search_node, route_list,
++                                                                      link) {
++                      list_for_each_entry(bus_node, &search_node->node_list,
++                                                                      link)
++                              bus_node->node_info->is_traversed = false;
++
++                      list_del(&search_node->link);
++                      kfree(search_node);
++      }
++
++      list_for_each_safe(bl_list, temp_bl_list, black_list)
++              list_del(bl_list);
++
++exit_prune_path:
++      return lnode_hop;
++}
++
++static void setup_bl_list(struct msm_bus_node_device_type *node,
++                              struct list_head *black_list)
++{
++      unsigned int i;
++
++      for (i = 0; i < node->node_info->num_blist; i++) {
++              struct msm_bus_node_device_type *bdev;
++              bdev = node->node_info->black_connections[i]->platform_data;
++              list_add_tail(&bdev->link, black_list);
++      }
++}
++
++static int getpath(int src, int dest)
++{
++      struct list_head traverse_list;
++      struct list_head edge_list;
++      struct list_head route_list;
++      struct list_head black_list;
++      struct device *src_dev = bus_find_device(&msm_bus_type, NULL,
++                                      (void *) &src,
++                                      msm_bus_device_match_adhoc);
++      struct msm_bus_node_device_type *src_node;
++      struct bus_search_type *search_node;
++      int found = 0;
++      int depth_index = 0;
++      int first_hop = -1;
++
++      INIT_LIST_HEAD(&traverse_list);
++      INIT_LIST_HEAD(&edge_list);
++      INIT_LIST_HEAD(&route_list);
++      INIT_LIST_HEAD(&black_list);
++
++      if (!src_dev) {
++              MSM_BUS_ERR("%s: Cannot locate src dev %d", __func__, src);
++              goto exit_getpath;
++      }
++
++      src_node = src_dev->platform_data;
++      if (!src_node) {
++              MSM_BUS_ERR("%s:Fatal, Source dev %d not found", __func__, src);
++              goto exit_getpath;
++      }
++      list_add_tail(&src_node->link, &traverse_list);
++
++      while ((!found && !list_empty(&traverse_list))) {
++              struct msm_bus_node_device_type *bus_node = NULL;
++              /* Locate dest_id in the traverse list */
++              list_for_each_entry(bus_node, &traverse_list, link) {
++                      if (bus_node->node_info->id == dest) {
++                              found = 1;
++                              break;
++                      }
++              }
++
++              if (!found) {
++                      unsigned int i;
++                      /* Setup the new edge list */
++                      list_for_each_entry(bus_node, &traverse_list, link) {
++                              /* Setup list of black-listed nodes */
++                              setup_bl_list(bus_node, &black_list);
++
++                              for (i = 0; i < bus_node->node_info->
++                                              num_connections; i++) {
++                                      bool skip;
++                                      struct msm_bus_node_device_type
++                                                      *node_conn;
++                                      node_conn = bus_node->node_info->
++                                              dev_connections[i]->
++                                              platform_data;
++                                      if (node_conn->node_info->
++                                                      is_traversed) {
++                                              MSM_BUS_ERR("Circ Path %d\n",
++                                              node_conn->node_info->id);
++                                              goto reset_traversed;
++                                      }
++                                      skip = chk_bl_list(&black_list,
++                                                      bus_node->node_info->
++                                                      connections[i]);
++                                      if (!skip) {
++                                              list_add_tail(&node_conn->link,
++                                                      &edge_list);
++                                              node_conn->node_info->
++                                                      is_traversed = true;
++                                      }
++                              }
++                      }
++
++                      /* Keep tabs of the previous search list */
++                      search_node = kzalloc(sizeof(struct bus_search_type),
++                                       GFP_KERNEL);
++                      INIT_LIST_HEAD(&search_node->node_list);
++                      list_splice_init(&traverse_list,
++                                       &search_node->node_list);
++                      /* Add the previous search list to a route list */
++                      list_add_tail(&search_node->link, &route_list);
++                      /* Advancing the list depth */
++                      depth_index++;
++                      list_splice_init(&edge_list, &traverse_list);
++              }
++      }
++reset_traversed:
++      copy_remaining_nodes(&edge_list, &traverse_list, &route_list);
++      first_hop = prune_path(&route_list, dest, src, &black_list, found);
++
++exit_getpath:
++      return first_hop;
++}
++
++static uint64_t arbitrate_bus_req(struct msm_bus_node_device_type *bus_dev,
++                                                              int ctx)
++{
++      int i;
++      uint64_t max_ib = 0;
++      uint64_t sum_ab = 0;
++      uint64_t bw_max_hz;
++      struct msm_bus_node_device_type *fab_dev = NULL;
++      uint32_t util_fact = 0;
++      uint32_t vrail_comp = 0;
++
++      /* Find max ib */
++      for (i = 0; i < bus_dev->num_lnodes; i++) {
++              max_ib = max(max_ib, bus_dev->lnode_list[i].lnode_ib[ctx]);
++              sum_ab += bus_dev->lnode_list[i].lnode_ab[ctx];
++      }
++      /*
++       *  Account for Util factor and vrail comp. The new aggregation
++       *  formula is:
++       *  Freq_hz = max((sum(ab) * util_fact)/num_chan, max(ib)/vrail_comp)
++       *                              / bus-width
++       *  util_fact and vrail comp are obtained from fabric/Node's dts
++       *  properties.
++       *  They default to 100 if absent.
++       */
++      fab_dev = bus_dev->node_info->bus_device->platform_data;
++      /* Don't do this for virtual fabrics */
++      if (fab_dev && fab_dev->fabdev) {
++              util_fact = bus_dev->node_info->util_fact ?
++                      bus_dev->node_info->util_fact :
++                      fab_dev->fabdev->util_fact;
++              vrail_comp = bus_dev->node_info->vrail_comp ?
++                      bus_dev->node_info->vrail_comp :
++                      fab_dev->fabdev->vrail_comp;
++              sum_ab *= util_fact;
++              sum_ab = msm_bus_div64(100, sum_ab);
++              max_ib *= 100;
++              max_ib = msm_bus_div64(vrail_comp, max_ib);
++      }
++
++      /* Account for multiple channels if any */
++      if (bus_dev->node_info->num_qports > 1)
++              sum_ab = msm_bus_div64(bus_dev->node_info->num_qports,
++                                      sum_ab);
++
++      if (!bus_dev->node_info->buswidth) {
++              MSM_BUS_WARN("No bus width found for %d. Using default\n",
++                                      bus_dev->node_info->id);
++              bus_dev->node_info->buswidth = 8;
++      }
++
++      bw_max_hz = max(max_ib, sum_ab);
++      bw_max_hz = msm_bus_div64(bus_dev->node_info->buswidth,
++                                      bw_max_hz);
++
++      return bw_max_hz;
++}
++
++static void del_inp_list(struct list_head *list)
++{
++      struct rule_update_path_info *rule_node;
++      struct rule_update_path_info *rule_node_tmp;
++
++      list_for_each_entry_safe(rule_node, rule_node_tmp, list, link)
++              list_del(&rule_node->link);
++}
++
++static void del_op_list(struct list_head *list)
++{
++      struct rule_apply_rcm_info *rule;
++      struct rule_apply_rcm_info *rule_tmp;
++
++      list_for_each_entry_safe(rule, rule_tmp, list, link)
++              list_del(&rule->link);
++}
++
++static int msm_bus_apply_rules(struct list_head *list, bool after_clk_commit)
++{
++      struct rule_apply_rcm_info *rule;
++      struct device *dev = NULL;
++      struct msm_bus_node_device_type *dev_info = NULL;
++      int ret = 0;
++      bool throttle_en = false;
++
++      list_for_each_entry(rule, list, link) {
++              if (!rule)
++                      break;
++
++              if (rule && (rule->after_clk_commit != after_clk_commit))
++                      continue;
++
++              dev = bus_find_device(&msm_bus_type, NULL,
++                              (void *) &rule->id,
++                              msm_bus_device_match_adhoc);
++
++              if (!dev) {
++                      MSM_BUS_ERR("Can't find dev node for %d", rule->id);
++                      continue;
++              }
++              dev_info = dev->platform_data;
++
++              throttle_en = ((rule->throttle == THROTTLE_ON) ? true : false);
++              ret = msm_bus_enable_limiter(dev_info, throttle_en,
++                                                      rule->lim_bw);
++              if (ret)
++                      MSM_BUS_ERR("Failed to set limiter for %d", rule->id);
++      }
++
++      return ret;
++}
++
++static uint64_t get_node_aggab(struct msm_bus_node_device_type *bus_dev)
++{
++      int i;
++      int ctx;
++      uint64_t max_agg_ab = 0;
++      uint64_t agg_ab = 0;
++
++      for (ctx = 0; ctx < NUM_CTX; ctx++) {
++              for (i = 0; i < bus_dev->num_lnodes; i++)
++                      agg_ab += bus_dev->lnode_list[i].lnode_ab[ctx];
++
++              if (bus_dev->node_info->num_qports > 1)
++                      agg_ab = msm_bus_div64(bus_dev->node_info->num_qports,
++                                                      agg_ab);
++
++              max_agg_ab = max(max_agg_ab, agg_ab);
++      }
++
++      return max_agg_ab;
++}
++
++static uint64_t get_node_ib(struct msm_bus_node_device_type *bus_dev)
++{
++      int i;
++      int ctx;
++      uint64_t max_ib = 0;
++
++      for (ctx = 0; ctx < NUM_CTX; ctx++) {
++              for (i = 0; i < bus_dev->num_lnodes; i++)
++                      max_ib = max(max_ib,
++                              bus_dev->lnode_list[i].lnode_ib[ctx]);
++      }
++      return max_ib;
++}
++
++static int update_path(int src, int dest, uint64_t req_ib, uint64_t req_bw,
++                      uint64_t cur_ib, uint64_t cur_bw, int src_idx, int ctx)
++{
++      struct device *src_dev = NULL;
++      struct device *next_dev = NULL;
++      struct link_node *lnode = NULL;
++      struct msm_bus_node_device_type *dev_info = NULL;
++      int curr_idx;
++      int ret = 0;
++      int *dirty_nodes = NULL;
++      int num_dirty = 0;
++      struct rule_update_path_info *rule_node;
++      bool rules_registered = msm_rule_are_rules_registered();
++
++      src_dev = bus_find_device(&msm_bus_type, NULL,
++                              (void *) &src,
++                              msm_bus_device_match_adhoc);
++
++      if (!src_dev) {
++              MSM_BUS_ERR("%s: Can't find source device %d", __func__, src);
++              ret = -ENODEV;
++              goto exit_update_path;
++      }
++
++      next_dev = src_dev;
++
++      if (src_idx < 0) {
++              MSM_BUS_ERR("%s: Invalid lnode idx %d", __func__, src_idx);
++              ret = -ENXIO;
++              goto exit_update_path;
++      }
++      curr_idx = src_idx;
++
++      INIT_LIST_HEAD(&input_list);
++      INIT_LIST_HEAD(&apply_list);
++
++      while (next_dev) {
++              dev_info = next_dev->platform_data;
++
++              if (curr_idx >= dev_info->num_lnodes) {
++                      MSM_BUS_ERR("%s: Invalid lnode Idx %d num lnodes %d",
++                       __func__, curr_idx, dev_info->num_lnodes);
++                      ret = -ENXIO;
++                      goto exit_update_path;
++              }
++
++              lnode = &dev_info->lnode_list[curr_idx];
++              lnode->lnode_ib[ctx] = req_ib;
++              lnode->lnode_ab[ctx] = req_bw;
++
++              dev_info->cur_clk_hz[ctx] = arbitrate_bus_req(dev_info, ctx);
++
++              /* Start updating the clocks at the first hop.
++               * Its ok to figure out the aggregated
++               * request at this node.
++               */
++              if (src_dev != next_dev) {
++                      ret = msm_bus_update_clks(dev_info, ctx, &dirty_nodes,
++                                                              &num_dirty);
++                      if (ret) {
++                              MSM_BUS_ERR("%s: Failed to update clks dev %d",
++                                      __func__, dev_info->node_info->id);
++                              goto exit_update_path;
++                      }
++              }
++
++              ret = msm_bus_update_bw(dev_info, ctx, req_bw, &dirty_nodes,
++                                                              &num_dirty);
++              if (ret) {
++                      MSM_BUS_ERR("%s: Failed to update bw dev %d",
++                              __func__, dev_info->node_info->id);
++                      goto exit_update_path;
++              }
++
++              if (rules_registered) {
++                      rule_node = &dev_info->node_info->rule;
++                      rule_node->id = dev_info->node_info->id;
++                      rule_node->ib = get_node_ib(dev_info);
++                      rule_node->ab = get_node_aggab(dev_info);
++                      rule_node->clk = max(dev_info->cur_clk_hz[ACTIVE_CTX],
++                                              dev_info->cur_clk_hz[DUAL_CTX]);
++                      list_add_tail(&rule_node->link, &input_list);
++              }
++
++              next_dev = lnode->next_dev;
++              curr_idx = lnode->next;
++      }
++
++      if (rules_registered) {
++              msm_rules_update_path(&input_list, &apply_list);
++              msm_bus_apply_rules(&apply_list, false);
++      }
++
++      msm_bus_commit_data(dirty_nodes, ctx, num_dirty);
++
++      if (rules_registered) {
++              msm_bus_apply_rules(&apply_list, true);
++              del_inp_list(&input_list);
++              del_op_list(&apply_list);
++      }
++exit_update_path:
++      return ret;
++}
++
++static int remove_path(int src, int dst, uint64_t cur_ib, uint64_t cur_ab,
++                              int src_idx, int active_only)
++{
++      struct device *src_dev = NULL;
++      struct device *next_dev = NULL;
++      struct link_node *lnode = NULL;
++      struct msm_bus_node_device_type *dev_info = NULL;
++      int ret = 0;
++      int cur_idx = src_idx;
++      int next_idx;
++
++      /* Update the current path to zero out all request from
++       * this cient on all paths
++       */
++
++      ret = update_path(src, dst, 0, 0, cur_ib, cur_ab, src_idx,
++                                                      active_only);
++      if (ret) {
++              MSM_BUS_ERR("%s: Error zeroing out path ctx %d",
++                                      __func__, ACTIVE_CTX);
++              goto exit_remove_path;
++      }
++
++      src_dev = bus_find_device(&msm_bus_type, NULL,
++                              (void *) &src,
++                              msm_bus_device_match_adhoc);
++      if (!src_dev) {
++              MSM_BUS_ERR("%s: Can't find source device %d", __func__, src);
++              ret = -ENODEV;
++              goto exit_remove_path;
++      }
++
++      next_dev = src_dev;
++
++      while (next_dev) {
++              dev_info = next_dev->platform_data;
++              lnode = &dev_info->lnode_list[cur_idx];
++              next_idx = lnode->next;
++              next_dev = lnode->next_dev;
++              remove_lnode(dev_info, cur_idx);
++              cur_idx = next_idx;
++      }
++
++exit_remove_path:
++      return ret;
++}
++
++static void getpath_debug(int src, int curr, int active_only)
++{
++      struct device *dev_node;
++      struct device *dev_it;
++      unsigned int hop = 1;
++      int idx;
++      struct msm_bus_node_device_type *devinfo;
++      int i;
++
++      dev_node = bus_find_device(&msm_bus_type, NULL,
++                              (void *) &src,
++                              msm_bus_device_match_adhoc);
++
++      if (!dev_node) {
++              MSM_BUS_ERR("SRC NOT FOUND %d", src);
++              return;
++      }
++
++      idx = curr;
++      devinfo = dev_node->platform_data;
++      dev_it = dev_node;
++
++      MSM_BUS_ERR("Route list Src %d", src);
++      while (dev_it) {
++              struct msm_bus_node_device_type *busdev =
++                      devinfo->node_info->bus_device->platform_data;
++
++              MSM_BUS_ERR("Hop[%d] at Device %d ctx %d", hop,
++                                      devinfo->node_info->id, active_only);
++
++              for (i = 0; i < NUM_CTX; i++) {
++                      MSM_BUS_ERR("dev info sel ib %llu",
++                                              devinfo->cur_clk_hz[i]);
++                      MSM_BUS_ERR("dev info sel ab %llu",
++                                              devinfo->node_ab.ab[i]);
++              }
++
++              dev_it = devinfo->lnode_list[idx].next_dev;
++              idx = devinfo->lnode_list[idx].next;
++              if (dev_it)
++                      devinfo = dev_it->platform_data;
++
++              MSM_BUS_ERR("Bus Device %d", busdev->node_info->id);
++              MSM_BUS_ERR("Bus Clock %llu", busdev->clk[active_only].rate);
++
++              if (idx < 0)
++                      break;
++              hop++;
++      }
++}
++
++static void unregister_client_adhoc(uint32_t cl)
++{
++      int i;
++      struct msm_bus_scale_pdata *pdata;
++      int lnode, src, curr, dest;
++      uint64_t  cur_clk, cur_bw;
++      struct msm_bus_client *client;
++
++      mutex_lock(&msm_bus_adhoc_lock);
++      if (!cl) {
++              MSM_BUS_ERR("%s: Null cl handle passed unregister\n",
++                              __func__);
++              goto exit_unregister_client;
++      }
++      client = handle_list.cl_list[cl];
++      pdata = client->pdata;
++      if (!pdata) {
++              MSM_BUS_ERR("%s: Null pdata passed to unregister\n",
++                              __func__);
++              goto exit_unregister_client;
++      }
++
++      curr = client->curr;
++      if (curr >= pdata->num_usecases) {
++              MSM_BUS_ERR("Invalid index Defaulting curr to 0");
++              curr = 0;
++      }
++
++      MSM_BUS_DBG("%s: Unregistering client %p", __func__, client);
++
++      for (i = 0; i < pdata->usecase->num_paths; i++) {
++              src = client->pdata->usecase[curr].vectors[i].src;
++              dest = client->pdata->usecase[curr].vectors[i].dst;
++
++              lnode = client->src_pnode[i];
++              cur_clk = client->pdata->usecase[curr].vectors[i].ib;
++              cur_bw = client->pdata->usecase[curr].vectors[i].ab;
++              remove_path(src, dest, cur_clk, cur_bw, lnode,
++                                              pdata->active_only);
++      }
++      msm_bus_dbg_client_data(client->pdata, MSM_BUS_DBG_UNREGISTER, cl);
++      kfree(client->src_pnode);
++      kfree(client);
++      handle_list.cl_list[cl] = NULL;
++exit_unregister_client:
++      mutex_unlock(&msm_bus_adhoc_lock);
++      return;
++}
++
++static int alloc_handle_lst(int size)
++{
++      int ret = 0;
++      struct msm_bus_client **t_cl_list;
++
++      if (!handle_list.num_entries) {
++              t_cl_list = kzalloc(sizeof(struct msm_bus_client *)
++                      * NUM_CL_HANDLES, GFP_KERNEL);
++              if (ZERO_OR_NULL_PTR(t_cl_list)) {
++                      ret = -ENOMEM;
++                      MSM_BUS_ERR("%s: Failed to allocate handles list",
++                                                              __func__);
++                      goto exit_alloc_handle_lst;
++              }
++              handle_list.cl_list = t_cl_list;
++              handle_list.num_entries += NUM_CL_HANDLES;
++      } else {
++              t_cl_list = krealloc(handle_list.cl_list,
++                              sizeof(struct msm_bus_client *) *
++                              handle_list.num_entries + NUM_CL_HANDLES,
++                              GFP_KERNEL);
++              if (ZERO_OR_NULL_PTR(t_cl_list)) {
++                      ret = -ENOMEM;
++                      MSM_BUS_ERR("%s: Failed to allocate handles list",
++                                                              __func__);
++                      goto exit_alloc_handle_lst;
++              }
++
++              memset(&handle_list.cl_list[handle_list.num_entries], 0,
++                      NUM_CL_HANDLES * sizeof(struct msm_bus_client *));
++              handle_list.num_entries += NUM_CL_HANDLES;
++              handle_list.cl_list = t_cl_list;
++      }
++exit_alloc_handle_lst:
++      return ret;
++}
++
++static uint32_t gen_handle(struct msm_bus_client *client)
++{
++      uint32_t handle = 0;
++      int i;
++      int ret = 0;
++
++      for (i = 0; i < handle_list.num_entries; i++) {
++              if (i && !handle_list.cl_list[i]) {
++                      handle = i;
++                      break;
++              }
++      }
++
++      if (!handle) {
++              ret = alloc_handle_lst(NUM_CL_HANDLES);
++
++              if (ret) {
++                      MSM_BUS_ERR("%s: Failed to allocate handle list",
++                                                      __func__);
++                      goto exit_gen_handle;
++              }
++              handle = i + 1;
++      }
++      handle_list.cl_list[handle] = client;
++exit_gen_handle:
++      return handle;
++}
++
++static uint32_t register_client_adhoc(struct msm_bus_scale_pdata *pdata)
++{
++      int src, dest;
++      int i;
++      struct msm_bus_client *client = NULL;
++      int *lnode;
++      uint32_t handle = 0;
++
++      mutex_lock(&msm_bus_adhoc_lock);
++      client = kzalloc(sizeof(struct msm_bus_client), GFP_KERNEL);
++      if (!client) {
++              MSM_BUS_ERR("%s: Error allocating client data", __func__);
++              goto exit_register_client;
++      }
++      client->pdata = pdata;
++
++      lnode = kzalloc(pdata->usecase->num_paths * sizeof(int), GFP_KERNEL);
++      if (ZERO_OR_NULL_PTR(lnode)) {
++              MSM_BUS_ERR("%s: Error allocating pathnode ptr!", __func__);
++              goto exit_register_client;
++      }
++      client->src_pnode = lnode;
++
++      for (i = 0; i < pdata->usecase->num_paths; i++) {
++              src = pdata->usecase->vectors[i].src;
++              dest = pdata->usecase->vectors[i].dst;
++
++              if ((src < 0) || (dest < 0)) {
++                      MSM_BUS_ERR("%s:Invalid src/dst.src %d dest %d",
++                              __func__, src, dest);
++                      goto exit_register_client;
++              }
++
++              lnode[i] = getpath(src, dest);
++              if (lnode[i] < 0) {
++                      MSM_BUS_ERR("%s:Failed to find path.src %d dest %d",
++                              __func__, src, dest);
++                      goto exit_register_client;
++              }
++      }
++
++      handle = gen_handle(client);
++      msm_bus_dbg_client_data(client->pdata, MSM_BUS_DBG_REGISTER,
++                                      handle);
++      MSM_BUS_DBG("%s:Client handle %d %s", __func__, handle,
++                                              client->pdata->name);
++exit_register_client:
++      mutex_unlock(&msm_bus_adhoc_lock);
++      return handle;
++}
++
++static int update_request_adhoc(uint32_t cl, unsigned int index)
++{
++      int i, ret = 0;
++      struct msm_bus_scale_pdata *pdata;
++      int lnode, src, curr, dest;
++      uint64_t req_clk, req_bw, curr_clk, curr_bw;
++      struct msm_bus_client *client;
++      const char *test_cl = "Null";
++      bool log_transaction = false;
++
++      mutex_lock(&msm_bus_adhoc_lock);
++
++      if (!cl) {
++              MSM_BUS_ERR("%s: Invalid client handle %d", __func__, cl);
++              ret = -ENXIO;
++              goto exit_update_request;
++      }
++
++      client = handle_list.cl_list[cl];
++      pdata = client->pdata;
++      if (!pdata) {
++              MSM_BUS_ERR("%s: Client data Null.[client didn't register]",
++                              __func__);
++              ret = -ENXIO;
++              goto exit_update_request;
++      }
++
++      if (index >= pdata->num_usecases) {
++              MSM_BUS_ERR("Client %u passed invalid index: %d\n",
++                      cl, index);
++              ret = -ENXIO;
++              goto exit_update_request;
++      }
++
++      if (client->curr == index) {
++              MSM_BUS_DBG("%s: Not updating client request idx %d unchanged",
++                              __func__, index);
++              goto exit_update_request;
++      }
++
++      curr = client->curr;
++      client->curr = index;
++
++      if (!strcmp(test_cl, pdata->name))
++              log_transaction = true;
++
++      MSM_BUS_DBG("%s: cl: %u index: %d curr: %d num_paths: %d\n", __func__,
++              cl, index, client->curr, client->pdata->usecase->num_paths);
++
++      for (i = 0; i < pdata->usecase->num_paths; i++) {
++              src = client->pdata->usecase[index].vectors[i].src;
++              dest = client->pdata->usecase[index].vectors[i].dst;
++
++              lnode = client->src_pnode[i];
++              req_clk = client->pdata->usecase[index].vectors[i].ib;
++              req_bw = client->pdata->usecase[index].vectors[i].ab;
++              if (curr < 0) {
++                      curr_clk = 0;
++                      curr_bw = 0;
++              } else {
++                      curr_clk = client->pdata->usecase[curr].vectors[i].ib;
++                      curr_bw = client->pdata->usecase[curr].vectors[i].ab;
++                      MSM_BUS_DBG("%s:ab: %llu ib: %llu\n", __func__,
++                                      curr_bw, curr_clk);
++              }
++
++              ret = update_path(src, dest, req_clk, req_bw,
++                              curr_clk, curr_bw, lnode, pdata->active_only);
++
++              if (ret) {
++                      MSM_BUS_ERR("%s: Update path failed! %d ctx %d\n",
++                                      __func__, ret, ACTIVE_CTX);
++                      goto exit_update_request;
++              }
++
++              if (log_transaction)
++                      getpath_debug(src, lnode, pdata->active_only);
++      }
++      msm_bus_dbg_client_data(client->pdata, index , cl);
++exit_update_request:
++      mutex_unlock(&msm_bus_adhoc_lock);
++      return ret;
++}
++
++/**
++ *  msm_bus_arb_setops_adhoc() : Setup the bus arbitration ops
++ *  @ arb_ops: pointer to the arb ops.
++ */
++void msm_bus_arb_setops_adhoc(struct msm_bus_arb_ops *arb_ops)
++{
++      arb_ops->register_client = register_client_adhoc;
++      arb_ops->update_request = update_request_adhoc;
++      arb_ops->unregister_client = unregister_client_adhoc;
++}
+--- /dev/null
++++ b/drivers/bus/msm_bus/msm_bus_bimc.c
+@@ -0,0 +1,2112 @@
++/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#define pr_fmt(fmt) "AXI: BIMC: %s(): " fmt, __func__
++
++#include <linux/slab.h>
++#include <linux/io.h>
++#include "msm-bus-board.h"
++#include "msm_bus_core.h"
++#include "msm_bus_bimc.h"
++#include "msm_bus_adhoc.h"
++#include <trace/events/trace_msm_bus.h>
++
++enum msm_bus_bimc_slave_block {
++      SLAVE_BLOCK_RESERVED = 0,
++      SLAVE_BLOCK_SLAVE_WAY,
++      SLAVE_BLOCK_XPU,
++      SLAVE_BLOCK_ARBITER,
++      SLAVE_BLOCK_SCMO,
++};
++
++enum bke_sw {
++      BKE_OFF = 0,
++      BKE_ON = 1,
++};
++
++/* M_Generic */
++
++#define M_REG_BASE(b)         ((b) + 0x00008000)
++
++#define M_COMPONENT_INFO_ADDR(b, n) \
++              (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000000)
++enum bimc_m_component_info {
++      M_COMPONENT_INFO_RMSK           = 0xffffff,
++      M_COMPONENT_INFO_INSTANCE_BMSK  = 0xff0000,
++      M_COMPONENT_INFO_INSTANCE_SHFT  = 0x10,
++      M_COMPONENT_INFO_SUB_TYPE_BMSK  = 0xff00,
++      M_COMPONENT_INFO_SUB_TYPE_SHFT  = 0x8,
++      M_COMPONENT_INFO_TYPE_BMSK      = 0xff,
++      M_COMPONENT_INFO_TYPE_SHFT      = 0x0,
++};
++
++#define M_CONFIG_INFO_0_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000020)
++enum bimc_m_config_info_0 {
++      M_CONFIG_INFO_0_RMSK                    = 0xff00ffff,
++      M_CONFIG_INFO_0_SYNC_MODE_BMSK          = 0xff000000,
++      M_CONFIG_INFO_0_SYNC_MODE_SHFT          = 0x18,
++      M_CONFIG_INFO_0_CONNECTION_TYPE_BMSK    = 0xff00,
++      M_CONFIG_INFO_0_CONNECTION_TYPE_SHFT    = 0x8,
++      M_CONFIG_INFO_0_FUNC_BMSK               = 0xff,
++      M_CONFIG_INFO_0_FUNC_SHFT               = 0x0,
++};
++
++#define M_CONFIG_INFO_1_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000030)
++enum bimc_m_config_info_1 {
++      M_CONFIG_INFO_1_RMSK                    = 0xffffffff,
++      M_CONFIG_INFO_1_SWAY_CONNECTIVITY_BMSK  = 0xffffffff,
++      M_CONFIG_INFO_1_SWAY_CONNECTIVITY_SHFT  = 0x0,
++};
++
++#define M_CONFIG_INFO_2_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000040)
++enum bimc_m_config_info_2 {
++      M_CONFIG_INFO_2_RMSK                    = 0xffffffff,
++      M_CONFIG_INFO_2_M_DATA_WIDTH_BMSK       = 0xffff0000,
++      M_CONFIG_INFO_2_M_DATA_WIDTH_SHFT       = 0x10,
++      M_CONFIG_INFO_2_M_TID_WIDTH_BMSK        = 0xff00,
++      M_CONFIG_INFO_2_M_TID_WIDTH_SHFT        = 0x8,
++      M_CONFIG_INFO_2_M_MID_WIDTH_BMSK        = 0xff,
++      M_CONFIG_INFO_2_M_MID_WIDTH_SHFT        = 0x0,
++};
++
++#define M_CONFIG_INFO_3_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000050)
++enum bimc_m_config_info_3 {
++      M_CONFIG_INFO_3_RMSK                    = 0xffffffff,
++      M_CONFIG_INFO_3_RCH_DEPTH_BMSK          = 0xff000000,
++      M_CONFIG_INFO_3_RCH_DEPTH_SHFT          = 0x18,
++      M_CONFIG_INFO_3_BCH_DEPTH_BMSK          = 0xff0000,
++      M_CONFIG_INFO_3_BCH_DEPTH_SHFT          = 0x10,
++      M_CONFIG_INFO_3_WCH_DEPTH_BMSK          = 0xff00,
++      M_CONFIG_INFO_3_WCH_DEPTH_SHFT          = 0x8,
++      M_CONFIG_INFO_3_ACH_DEPTH_BMSK          = 0xff,
++      M_CONFIG_INFO_3_ACH_DEPTH_SHFT          = 0x0,
++};
++
++#define M_CONFIG_INFO_4_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000060)
++enum bimc_m_config_info_4 {
++      M_CONFIG_INFO_4_RMSK                    = 0xffff,
++      M_CONFIG_INFO_4_REORDER_BUF_DEPTH_BMSK  = 0xff00,
++      M_CONFIG_INFO_4_REORDER_BUF_DEPTH_SHFT  = 0x8,
++      M_CONFIG_INFO_4_REORDER_TABLE_DEPTH_BMSK        = 0xff,
++      M_CONFIG_INFO_4_REORDER_TABLE_DEPTH_SHFT        = 0x0,
++};
++
++#define M_CONFIG_INFO_5_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000070)
++enum bimc_m_config_info_5 {
++      M_CONFIG_INFO_5_RMSK                    = 0x111,
++      M_CONFIG_INFO_5_MP2ARB_PIPELINE_EN_BMSK = 0x100,
++      M_CONFIG_INFO_5_MP2ARB_PIPELINE_EN_SHFT = 0x8,
++      M_CONFIG_INFO_5_MPBUF_PIPELINE_EN_BMSK  = 0x10,
++      M_CONFIG_INFO_5_MPBUF_PIPELINE_EN_SHFT  = 0x4,
++      M_CONFIG_INFO_5_M2MP_PIPELINE_EN_BMSK   = 0x1,
++      M_CONFIG_INFO_5_M2MP_PIPELINE_EN_SHFT   = 0x0,
++};
++
++#define M_INT_STATUS_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000100)
++enum bimc_m_int_status {
++      M_INT_STATUS_RMSK                       = 0x3,
++};
++
++#define M_INT_CLR_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000108)
++enum bimc_m_int_clr {
++      M_INT_CLR_RMSK                  = 0x3,
++};
++
++#define M_INT_EN_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x0000010c)
++enum bimc_m_int_en {
++      M_INT_EN_RMSK                   = 0x3,
++};
++
++#define M_CLK_CTRL_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000200)
++enum bimc_m_clk_ctrl {
++      M_CLK_CTRL_RMSK                         = 0x3,
++      M_CLK_CTRL_MAS_CLK_GATING_EN_BMSK       = 0x2,
++      M_CLK_CTRL_MAS_CLK_GATING_EN_SHFT       = 0x1,
++      M_CLK_CTRL_CORE_CLK_GATING_EN_BMSK      = 0x1,
++      M_CLK_CTRL_CORE_CLK_GATING_EN_SHFT      = 0x0,
++};
++
++#define M_MODE_ADDR(b, n) \
++              (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000210)
++enum bimc_m_mode {
++      M_MODE_RMSK                             = 0xf0000011,
++      M_MODE_WR_GATHER_BEATS_BMSK             = 0xf0000000,
++      M_MODE_WR_GATHER_BEATS_SHFT             = 0x1c,
++      M_MODE_NARROW_WR_BMSK                   = 0x10,
++      M_MODE_NARROW_WR_SHFT                   = 0x4,
++      M_MODE_ORDERING_MODEL_BMSK              = 0x1,
++      M_MODE_ORDERING_MODEL_SHFT              = 0x0,
++};
++
++#define M_PRIOLVL_OVERRIDE_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000230)
++enum bimc_m_priolvl_override {
++      M_PRIOLVL_OVERRIDE_RMSK                 = 0x301,
++      M_PRIOLVL_OVERRIDE_BMSK                 = 0x300,
++      M_PRIOLVL_OVERRIDE_SHFT                 = 0x8,
++      M_PRIOLVL_OVERRIDE_OVERRIDE_PRIOLVL_BMSK        = 0x1,
++      M_PRIOLVL_OVERRIDE_OVERRIDE_PRIOLVL_SHFT        = 0x0,
++};
++
++#define M_RD_CMD_OVERRIDE_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000240)
++enum bimc_m_read_command_override {
++      M_RD_CMD_OVERRIDE_RMSK                  = 0x3071f7f,
++      M_RD_CMD_OVERRIDE_AREQPRIO_BMSK         = 0x3000000,
++      M_RD_CMD_OVERRIDE_AREQPRIO_SHFT         = 0x18,
++      M_RD_CMD_OVERRIDE_AMEMTYPE_BMSK         = 0x70000,
++      M_RD_CMD_OVERRIDE_AMEMTYPE_SHFT         = 0x10,
++      M_RD_CMD_OVERRIDE_ATRANSIENT_BMSK               = 0x1000,
++      M_RD_CMD_OVERRIDE_ATRANSIENT_SHFT               = 0xc,
++      M_RD_CMD_OVERRIDE_ASHARED_BMSK          = 0x800,
++      M_RD_CMD_OVERRIDE_ASHARED_SHFT          = 0xb,
++      M_RD_CMD_OVERRIDE_AREDIRECT_BMSK                = 0x400,
++      M_RD_CMD_OVERRIDE_AREDIRECT_SHFT                = 0xa,
++      M_RD_CMD_OVERRIDE_AOOO_BMSK                     = 0x200,
++      M_RD_CMD_OVERRIDE_AOOO_SHFT                     = 0x9,
++      M_RD_CMD_OVERRIDE_AINNERSHARED_BMSK             = 0x100,
++      M_RD_CMD_OVERRIDE_AINNERSHARED_SHFT             = 0x8,
++      M_RD_CMD_OVERRIDE_OVERRIDE_AREQPRIO_BMSK        = 0x40,
++      M_RD_CMD_OVERRIDE_OVERRIDE_AREQPRIO_SHFT        = 0x6,
++      M_RD_CMD_OVERRIDE_OVERRIDE_ATRANSIENT_BMSK      = 0x20,
++      M_RD_CMD_OVERRIDE_OVERRIDE_ATRANSIENT_SHFT      = 0x5,
++      M_RD_CMD_OVERRIDE_OVERRIDE_AMEMTYPE_BMSK        = 0x10,
++      M_RD_CMD_OVERRIDE_OVERRIDE_AMEMTYPE_SHFT        = 0x4,
++      M_RD_CMD_OVERRIDE_OVERRIDE_ASHARED_BMSK = 0x8,
++      M_RD_CMD_OVERRIDE_OVERRIDE_ASHARED_SHFT = 0x3,
++      M_RD_CMD_OVERRIDE_OVERRIDE_AREDIRECT_BMSK       = 0x4,
++      M_RD_CMD_OVERRIDE_OVERRIDE_AREDIRECT_SHFT       = 0x2,
++      M_RD_CMD_OVERRIDE_OVERRIDE_AOOO_BMSK            = 0x2,
++      M_RD_CMD_OVERRIDE_OVERRIDE_AOOO_SHFT            = 0x1,
++      M_RD_CMD_OVERRIDE_OVERRIDE_AINNERSHARED_BMSK    = 0x1,
++      M_RD_CMD_OVERRIDE_OVERRIDE_AINNERSHARED_SHFT    = 0x0,
++};
++
++#define M_WR_CMD_OVERRIDE_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000250)
++enum bimc_m_write_command_override {
++      M_WR_CMD_OVERRIDE_RMSK                  = 0x3071f7f,
++      M_WR_CMD_OVERRIDE_AREQPRIO_BMSK         = 0x3000000,
++      M_WR_CMD_OVERRIDE_AREQPRIO_SHFT         = 0x18,
++      M_WR_CMD_OVERRIDE_AMEMTYPE_BMSK         = 0x70000,
++      M_WR_CMD_OVERRIDE_AMEMTYPE_SHFT         = 0x10,
++      M_WR_CMD_OVERRIDE_ATRANSIENT_BMSK       = 0x1000,
++      M_WR_CMD_OVERRIDE_ATRANSIENT_SHFT       = 0xc,
++      M_WR_CMD_OVERRIDE_ASHARED_BMSK          = 0x800,
++      M_WR_CMD_OVERRIDE_ASHARED_SHFT          = 0xb,
++      M_WR_CMD_OVERRIDE_AREDIRECT_BMSK                = 0x400,
++      M_WR_CMD_OVERRIDE_AREDIRECT_SHFT                = 0xa,
++      M_WR_CMD_OVERRIDE_AOOO_BMSK                     = 0x200,
++      M_WR_CMD_OVERRIDE_AOOO_SHFT                     = 0x9,
++      M_WR_CMD_OVERRIDE_AINNERSHARED_BMSK             = 0x100,
++      M_WR_CMD_OVERRIDE_AINNERSHARED_SHFT             = 0x8,
++      M_WR_CMD_OVERRIDE_OVERRIDE_AREQPRIO_BMSK        = 0x40,
++      M_WR_CMD_OVERRIDE_OVERRIDE_AREQPRIO_SHFT        = 0x6,
++      M_WR_CMD_OVERRIDE_OVERRIDE_ATRANSIENT_BMSK      = 0x20,
++      M_WR_CMD_OVERRIDE_OVERRIDE_ATRANSIENT_SHFT      = 0x5,
++      M_WR_CMD_OVERRIDE_OVERRIDE_AMEMTYPE_BMSK        = 0x10,
++      M_WR_CMD_OVERRIDE_OVERRIDE_AMEMTYPE_SHFT        = 0x4,
++      M_WR_CMD_OVERRIDE_OVERRIDE_ASHARED_BMSK = 0x8,
++      M_WR_CMD_OVERRIDE_OVERRIDE_ASHARED_SHFT = 0x3,
++      M_WR_CMD_OVERRIDE_OVERRIDE_AREDIRECT_BMSK       = 0x4,
++      M_WR_CMD_OVERRIDE_OVERRIDE_AREDIRECT_SHFT       = 0x2,
++      M_WR_CMD_OVERRIDE_OVERRIDE_AOOO_BMSK    = 0x2,
++      M_WR_CMD_OVERRIDE_OVERRIDE_AOOO_SHFT    = 0x1,
++      M_WR_CMD_OVERRIDE_OVERRIDE_AINNERSHARED_BMSK    = 0x1,
++      M_WR_CMD_OVERRIDE_OVERRIDE_AINNERSHARED_SHFT    = 0x0,
++};
++
++#define M_BKE_EN_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000300)
++enum bimc_m_bke_en {
++      M_BKE_EN_RMSK                   = 0x1,
++      M_BKE_EN_EN_BMSK                = 0x1,
++      M_BKE_EN_EN_SHFT                = 0x0,
++};
++
++/* Grant Period registers */
++#define M_BKE_GP_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000304)
++enum bimc_m_bke_grant_period {
++      M_BKE_GP_RMSK           = 0x3ff,
++      M_BKE_GP_GP_BMSK        = 0x3ff,
++      M_BKE_GP_GP_SHFT        = 0x0,
++};
++
++/* Grant count register.
++ * The Grant count register represents a signed 16 bit
++ * value, range 0-0x7fff
++ */
++#define M_BKE_GC_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000308)
++enum bimc_m_bke_grant_count {
++      M_BKE_GC_RMSK                   = 0xffff,
++      M_BKE_GC_GC_BMSK                = 0xffff,
++      M_BKE_GC_GC_SHFT                = 0x0,
++};
++
++/* Threshold High Registers */
++#define M_BKE_THH_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000320)
++enum bimc_m_bke_thresh_high {
++      M_BKE_THH_RMSK          = 0xffff,
++      M_BKE_THH_THRESH_BMSK   = 0xffff,
++      M_BKE_THH_THRESH_SHFT   = 0x0,
++};
++
++/* Threshold Medium Registers */
++#define M_BKE_THM_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000324)
++enum bimc_m_bke_thresh_medium {
++      M_BKE_THM_RMSK          = 0xffff,
++      M_BKE_THM_THRESH_BMSK   = 0xffff,
++      M_BKE_THM_THRESH_SHFT   = 0x0,
++};
++
++/* Threshold Low Registers */
++#define M_BKE_THL_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000328)
++enum bimc_m_bke_thresh_low {
++      M_BKE_THL_RMSK                  = 0xffff,
++      M_BKE_THL_THRESH_BMSK           = 0xffff,
++      M_BKE_THL_THRESH_SHFT           = 0x0,
++};
++
++#define M_BKE_HEALTH_0_CONFIG_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000340)
++enum bimc_m_bke_health_0 {
++      M_BKE_HEALTH_0_CONFIG_RMSK                      = 0x80000303,
++      M_BKE_HEALTH_0_CONFIG_LIMIT_CMDS_BMSK           = 0x80000000,
++      M_BKE_HEALTH_0_CONFIG_LIMIT_CMDS_SHFT           = 0x1f,
++      M_BKE_HEALTH_0_CONFIG_AREQPRIO_BMSK             = 0x300,
++      M_BKE_HEALTH_0_CONFIG_AREQPRIO_SHFT             = 0x8,
++      M_BKE_HEALTH_0_CONFIG_PRIOLVL_BMSK              = 0x3,
++      M_BKE_HEALTH_0_CONFIG_PRIOLVL_SHFT              = 0x0,
++};
++
++#define M_BKE_HEALTH_1_CONFIG_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000344)
++enum bimc_m_bke_health_1 {
++      M_BKE_HEALTH_1_CONFIG_RMSK                      = 0x80000303,
++      M_BKE_HEALTH_1_CONFIG_LIMIT_CMDS_BMSK           = 0x80000000,
++      M_BKE_HEALTH_1_CONFIG_LIMIT_CMDS_SHFT           = 0x1f,
++      M_BKE_HEALTH_1_CONFIG_AREQPRIO_BMSK             = 0x300,
++      M_BKE_HEALTH_1_CONFIG_AREQPRIO_SHFT             = 0x8,
++      M_BKE_HEALTH_1_CONFIG_PRIOLVL_BMSK              = 0x3,
++      M_BKE_HEALTH_1_CONFIG_PRIOLVL_SHFT              = 0x0,
++};
++
++#define M_BKE_HEALTH_2_CONFIG_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000348)
++enum bimc_m_bke_health_2 {
++      M_BKE_HEALTH_2_CONFIG_RMSK                      = 0x80000303,
++      M_BKE_HEALTH_2_CONFIG_LIMIT_CMDS_BMSK           = 0x80000000,
++      M_BKE_HEALTH_2_CONFIG_LIMIT_CMDS_SHFT           = 0x1f,
++      M_BKE_HEALTH_2_CONFIG_AREQPRIO_BMSK             = 0x300,
++      M_BKE_HEALTH_2_CONFIG_AREQPRIO_SHFT             = 0x8,
++      M_BKE_HEALTH_2_CONFIG_PRIOLVL_BMSK              = 0x3,
++      M_BKE_HEALTH_2_CONFIG_PRIOLVL_SHFT              = 0x0,
++};
++
++#define M_BKE_HEALTH_3_CONFIG_ADDR(b, n) \
++      (M_REG_BASE(b) + (0x4000 * (n)) + 0x0000034c)
++enum bimc_m_bke_health_3 {
++      M_BKE_HEALTH_3_CONFIG_RMSK                      = 0x303,
++      M_BKE_HEALTH_3_CONFIG_AREQPRIO_BMSK     = 0x300,
++      M_BKE_HEALTH_3_CONFIG_AREQPRIO_SHFT     = 0x8,
++      M_BKE_HEALTH_3_CONFIG_PRIOLVL_BMSK              = 0x3,
++      M_BKE_HEALTH_3_CONFIG_PRIOLVL_SHFT              = 0x0,
++};
++
++#define M_BUF_STATUS_ADDR(b, n) \
++              (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000400)
++enum bimc_m_buf_status {
++      M_BUF_STATUS_RMSK                       = 0xf03f030,
++      M_BUF_STATUS_RCH_DATA_WR_FULL_BMSK      = 0x8000000,
++      M_BUF_STATUS_RCH_DATA_WR_FULL_SHFT      = 0x1b,
++      M_BUF_STATUS_RCH_DATA_WR_EMPTY_BMSK     = 0x4000000,
++      M_BUF_STATUS_RCH_DATA_WR_EMPTY_SHFT     = 0x1a,
++      M_BUF_STATUS_RCH_CTRL_WR_FULL_BMSK      = 0x2000000,
++      M_BUF_STATUS_RCH_CTRL_WR_FULL_SHFT      = 0x19,
++      M_BUF_STATUS_RCH_CTRL_WR_EMPTY_BMSK     = 0x1000000,
++      M_BUF_STATUS_RCH_CTRL_WR_EMPTY_SHFT     = 0x18,
++      M_BUF_STATUS_BCH_WR_FULL_BMSK           = 0x20000,
++      M_BUF_STATUS_BCH_WR_FULL_SHFT           = 0x11,
++      M_BUF_STATUS_BCH_WR_EMPTY_BMSK          = 0x10000,
++      M_BUF_STATUS_BCH_WR_EMPTY_SHFT          = 0x10,
++      M_BUF_STATUS_WCH_DATA_RD_FULL_BMSK      = 0x8000,
++      M_BUF_STATUS_WCH_DATA_RD_FULL_SHFT      = 0xf,
++      M_BUF_STATUS_WCH_DATA_RD_EMPTY_BMSK     = 0x4000,
++      M_BUF_STATUS_WCH_DATA_RD_EMPTY_SHFT     = 0xe,
++      M_BUF_STATUS_WCH_CTRL_RD_FULL_BMSK      = 0x2000,
++      M_BUF_STATUS_WCH_CTRL_RD_FULL_SHFT      = 0xd,
++      M_BUF_STATUS_WCH_CTRL_RD_EMPTY_BMSK     = 0x1000,
++      M_BUF_STATUS_WCH_CTRL_RD_EMPTY_SHFT     = 0xc,
++      M_BUF_STATUS_ACH_RD_FULL_BMSK           = 0x20,
++      M_BUF_STATUS_ACH_RD_FULL_SHFT           = 0x5,
++      M_BUF_STATUS_ACH_RD_EMPTY_BMSK          = 0x10,
++      M_BUF_STATUS_ACH_RD_EMPTY_SHFT          = 0x4,
++};
++/*BIMC Generic */
++
++#define S_REG_BASE(b) ((b) + 0x00048000)
++
++#define S_COMPONENT_INFO_ADDR(b, n) \
++      (S_REG_BASE(b) + (0x8000 * (n)) + 0x00000000)
++enum bimc_s_component_info {
++      S_COMPONENT_INFO_RMSK                   = 0xffffff,
++      S_COMPONENT_INFO_INSTANCE_BMSK          = 0xff0000,
++      S_COMPONENT_INFO_INSTANCE_SHFT          = 0x10,
++      S_COMPONENT_INFO_SUB_TYPE_BMSK          = 0xff00,
++      S_COMPONENT_INFO_SUB_TYPE_SHFT          = 0x8,
++      S_COMPONENT_INFO_TYPE_BMSK              = 0xff,
++      S_COMPONENT_INFO_TYPE_SHFT              = 0x0,
++};
++
++#define S_HW_INFO_ADDR(b, n) \
++      (S_REG_BASE(b) + (0x80000 * (n)) + 0x00000010)
++enum bimc_s_hw_info {
++      S_HW_INFO_RMSK                          = 0xffffffff,
++      S_HW_INFO_MAJOR_BMSK                    = 0xff000000,
++      S_HW_INFO_MAJOR_SHFT                    = 0x18,
++      S_HW_INFO_BRANCH_BMSK                   = 0xff0000,
++      S_HW_INFO_BRANCH_SHFT                   = 0x10,
++      S_HW_INFO_MINOR_BMSK                    = 0xff00,
++      S_HW_INFO_MINOR_SHFT                    = 0x8,
++      S_HW_INFO_ECO_BMSK                      = 0xff,
++      S_HW_INFO_ECO_SHFT                      = 0x0,
++};
++
++
++/* S_SCMO_GENERIC */
++
++#define S_SCMO_REG_BASE(b)    ((b) + 0x00048000)
++
++#define S_SCMO_CONFIG_INFO_0_ADDR(b, n) \
++              (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000020)
++enum bimc_s_scmo_config_info_0 {
++      S_SCMO_CONFIG_INFO_0_RMSK               = 0xffffffff,
++      S_SCMO_CONFIG_INFO_0_DATA_WIDTH_BMSK    = 0xffff0000,
++      S_SCMO_CONFIG_INFO_0_DATA_WIDTH_SHFT    = 0x10,
++      S_SCMO_CONFIG_INFO_0_TID_WIDTH_BMSK     = 0xff00,
++      S_SCMO_CONFIG_INFO_0_TID_WIDTH_SHFT     = 0x8,
++      S_SCMO_CONFIG_INFO_0_MID_WIDTH_BMSK     = 0xff,
++      S_SCMO_CONFIG_INFO_0_MID_WIDTH_SHFT     = 0x0,
++};
++
++#define S_SCMO_CONFIG_INFO_1_ADDR(b, n) \
++              (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000030)
++enum bimc_s_scmo_config_info_1 {
++      S_SCMO_CONFIG_INFO_1_RMSK                       = 0xffffffff,
++      S_SCMO_CONFIG_INFO_1_MPORT_CONNECTIVITY_BMSK    = 0xffffffff,
++      S_SCMO_CONFIG_INFO_1_MPORT_CONNECTIVITY_SHFT    = 0x0,
++};
++
++#define S_SCMO_CONFIG_INFO_2_ADDR(b, n) \
++              (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000040)
++enum bimc_s_scmo_config_info_2 {
++      S_SCMO_CONFIG_INFO_2_RMSK                       = 0xff00ff,
++      S_SCMO_CONFIG_INFO_2_NUM_GLOBAL_MONS_BMSK       = 0xff0000,
++      S_SCMO_CONFIG_INFO_2_NUM_GLOBAL_MONS_SHFT       = 0x10,
++      S_SCMO_CONFIG_INFO_2_VMID_WIDTH_BMSK    = 0xff,
++      S_SCMO_CONFIG_INFO_2_VMID_WIDTH_SHFT    = 0x0,
++};
++
++#define S_SCMO_CONFIG_INFO_3_ADDR(b, n) \
++              (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000050)
++enum bimc_s_scmo_config_info_3 {
++      S_SCMO_CONFIG_INFO_3_RMSK                       = 0xffffffff,
++      S_SCMO_CONFIG_INFO_3_RCH0_CTRL_DEPTH_BMSK       = 0xff000000,
++      S_SCMO_CONFIG_INFO_3_RCH0_CTRL_DEPTH_SHFT       = 0x18,
++      S_SCMO_CONFIG_INFO_3_RCH0_DEPTH_BMSK            = 0xff0000,
++      S_SCMO_CONFIG_INFO_3_RCH0_DEPTH_SHFT            = 0x10,
++      S_SCMO_CONFIG_INFO_3_BCH_DEPTH_BMSK             = 0xff00,
++      S_SCMO_CONFIG_INFO_3_BCH_DEPTH_SHFT             = 0x8,
++      S_SCMO_CONFIG_INFO_3_WCH_DEPTH_BMSK             = 0xff,
++      S_SCMO_CONFIG_INFO_3_WCH_DEPTH_SHFT             = 0x0,
++};
++
++#define S_SCMO_CONFIG_INFO_4_ADDR(b, n) \
++              (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000060)
++enum bimc_s_scmo_config_info_4 {
++      S_SCMO_CONFIG_INFO_4_RMSK                       = 0xffff,
++      S_SCMO_CONFIG_INFO_4_RCH1_CTRL_DEPTH_BMSK       = 0xff00,
++      S_SCMO_CONFIG_INFO_4_RCH1_CTRL_DEPTH_SHFT       = 0x8,
++      S_SCMO_CONFIG_INFO_4_RCH1_DEPTH_BMSK            = 0xff,
++      S_SCMO_CONFIG_INFO_4_RCH1_DEPTH_SHFT            = 0x0,
++};
++
++#define S_SCMO_CONFIG_INFO_5_ADDR(b, n) \
++              (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000070)
++enum bimc_s_scmo_config_info_5 {
++      S_SCMO_CONFIG_INFO_5_RMSK                       = 0xffff,
++      S_SCMO_CONFIG_INFO_5_DPE_CQ_DEPTH_BMSK          = 0xff00,
++      S_SCMO_CONFIG_INFO_5_DPE_CQ_DEPTH_SHFT          = 0x8,
++      S_SCMO_CONFIG_INFO_5_DDR_BUS_WIDTH_BMSK         = 0xff,
++      S_SCMO_CONFIG_INFO_5_DDR_BUS_WIDTH_SHFT         = 0x0,
++};
++
++#define S_SCMO_CONFIG_INFO_6_ADDR(b, n) \
++              (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000080)
++enum bimc_s_scmo_config_info_6 {
++      S_SCMO_CONFIG_INFO_6_RMSK                       = 0x1111,
++      S_SCMO_CONFIG_INFO_6_WBUFC_PIPE_BMSK            = 0x1000,
++      S_SCMO_CONFIG_INFO_6_WBUFC_PIPE_SHFT            = 0xc,
++      S_SCMO_CONFIG_INFO_6_RDOPT_PIPE_BMSK            = 0x100,
++      S_SCMO_CONFIG_INFO_6_RDOPT_PIPE_SHFT            = 0x8,
++      S_SCMO_CONFIG_INFO_6_ACHAN_INTF_PIPE_BMSK       = 0x10,
++      S_SCMO_CONFIG_INFO_6_ACHAN_INTF_PIPE_SHFT       = 0x4,
++      S_SCMO_CONFIG_INFO_6_ADDR_DECODE_HT_BMSK        = 0x1,
++      S_SCMO_CONFIG_INFO_6_ADDR_DECODE_HT_SHFT        = 0x0,
++};
++
++#define S_SCMO_INT_STATUS_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000100)
++enum bimc_s_scmo_int_status {
++      S_SCMO_INT_STATUS_RMSK                  = 0x1,
++      S_SCMO_INT_STATUS_ERR_OCCURED_BMSK      = 0x1,
++      S_SCMO_INT_STATUS_ERR_OCCURED_SHFT      = 0x0,
++};
++
++#define S_SCMO_INT_CLR_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000108)
++enum bimc_s_scmo_int_clr {
++      S_SCMO_INT_CLR_RMSK             = 0x1,
++      S_SCMO_INT_CLR_IRQ_CLR_BMSK     = 0x1,
++      S_SCMO_INT_CLR_IRQ_CLR_SHFT     = 0x0,
++};
++
++#define S_SCMO_INT_EN_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x0000010c)
++enum bimc_s_scmo_int_en {
++      S_SCMO_INT_EN_RMSK              = 0x1,
++      S_SCMO_INT_EN_IRQ_EN_BMSK       = 0x1,
++      S_SCMO_INT_EN_IRQ_EN_SHFT       = 0x0,
++};
++
++#define S_SCMO_ESYN_ADDR_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000120)
++enum bimc_s_scmo_esyn_addr {
++      S_SCMO_ESYN_ADDR_RMSK                           = 0xffffffff,
++      S_SCMO_ESYN_ADDR_ESYN_ADDR_ERR_ADDR_BMSK        = 0xffffffff,
++      S_SCMO_ESYN_ADDR_ESYN_ADDR_ERR_ADDR_SHFT        = 0x0,
++};
++
++#define S_SCMO_ESYN_APACKET_0_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000128)
++enum bimc_s_scmo_esyn_apacket_0 {
++      S_SCMO_ESYN_APACKET_0_RMSK                      = 0xff1fffff,
++      S_SCMO_ESYN_APACKET_0_ERR_ATID_BMSK             = 0xff000000,
++      S_SCMO_ESYN_APACKET_0_ERR_ATID_SHFT             = 0x18,
++      S_SCMO_ESYN_APACKET_0_ERR_AVMID_BMSK            = 0x1f0000,
++      S_SCMO_ESYN_APACKET_0_ERR_AVMID_SHFT            = 0x10,
++      S_SCMO_ESYN_APACKET_0_ERR_AMID_BMSK             = 0xffff,
++      S_SCMO_ESYN_APACKET_0_ERR_AMID_SHFT             = 0x0,
++};
++
++#define S_SCMO_ESYN_APACKET_1_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x0000012c)
++enum bimc_s_scmo_esyn_apacket_1 {
++      S_SCMO_ESYN_APACKET_1_RMSK                      = 0x10ff117,
++      S_SCMO_ESYN_APACKET_1_ERR_CODE_BMSK             = 0x1000000,
++      S_SCMO_ESYN_APACKET_1_ERR_CODE_SHFT             = 0x18,
++      S_SCMO_ESYN_APACKET_1_ERR_ALEN_BMSK             = 0xf0000,
++      S_SCMO_ESYN_APACKET_1_ERR_ALEN_SHFT             = 0x10,
++      S_SCMO_ESYN_APACKET_1_ERR_ASIZE_BMSK            = 0xe000,
++      S_SCMO_ESYN_APACKET_1_ERR_ASIZE_SHFT            = 0xd,
++      S_SCMO_ESYN_APACKET_1_ERR_ABURST_BMSK           = 0x1000,
++      S_SCMO_ESYN_APACKET_1_ERR_ABURST_SHFT           = 0xc,
++      S_SCMO_ESYN_APACKET_1_ERR_AEXCLUSIVE_BMSK       = 0x100,
++      S_SCMO_ESYN_APACKET_1_ERR_AEXCLUSIVE_SHFT       = 0x8,
++      S_SCMO_ESYN_APACKET_1_ERR_APRONTS_BMSK          = 0x10,
++      S_SCMO_ESYN_APACKET_1_ERR_APRONTS_SHFT          = 0x4,
++      S_SCMO_ESYN_APACKET_1_ERR_AOOORD_BMSK           = 0x4,
++      S_SCMO_ESYN_APACKET_1_ERR_AOOORD_SHFT           = 0x2,
++      S_SCMO_ESYN_APACKET_1_ERR_AOOOWR_BMSK           = 0x2,
++      S_SCMO_ESYN_APACKET_1_ERR_AOOOWR_SHFT           = 0x1,
++      S_SCMO_ESYN_APACKET_1_ERR_AWRITE_BMSK           = 0x1,
++      S_SCMO_ESYN_APACKET_1_ERR_AWRITE_SHFT           = 0x0,
++};
++
++#define S_SCMO_CLK_CTRL_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000200)
++enum bimc_s_scmo_clk_ctrl {
++      S_SCMO_CLK_CTRL_RMSK                            = 0xffff1111,
++      S_SCMO_CLK_CTRL_PEN_CMD_CG_EN_BMSK              = 0x10000,
++      S_SCMO_CLK_CTRL_PEN_CMD_CG_EN_SHFT              = 0x10,
++      S_SCMO_CLK_CTRL_RCH_CG_EN_BMSK                  = 0x1000,
++      S_SCMO_CLK_CTRL_RCH_CG_EN_SHFT                  = 0xc,
++      S_SCMO_CLK_CTRL_FLUSH_CG_EN_BMSK                = 0x100,
++      S_SCMO_CLK_CTRL_FLUSH_CG_EN_SHFT                = 0x8,
++      S_SCMO_CLK_CTRL_WCH_CG_EN_BMSK                  = 0x10,
++      S_SCMO_CLK_CTRL_WCH_CG_EN_SHFT                  = 0x4,
++      S_SCMO_CLK_CTRL_ACH_CG_EN_BMSK                  = 0x1,
++      S_SCMO_CLK_CTRL_ACH_CG_EN_SHFT                  = 0x0,
++};
++
++#define S_SCMO_SLV_INTERLEAVE_CFG_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000400)
++enum bimc_s_scmo_slv_interleave_cfg {
++      S_SCMO_SLV_INTERLEAVE_CFG_RMSK                  = 0xff,
++      S_SCMO_SLV_INTERLEAVE_CFG_INTERLEAVE_CS1_BMSK   = 0x10,
++      S_SCMO_SLV_INTERLEAVE_CFG_INTERLEAVE_CS1_SHFT   = 0x4,
++      S_SCMO_SLV_INTERLEAVE_CFG_INTERLEAVE_CS0_BMSK   = 0x1,
++      S_SCMO_SLV_INTERLEAVE_CFG_INTERLEAVE_CS0_SHFT   = 0x0,
++};
++
++#define S_SCMO_ADDR_BASE_CSn_ADDR(b, n, o)    \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000410 + 0x4 * (o))
++enum bimc_s_scmo_addr_base_csn {
++      S_SCMO_ADDR_BASE_CSn_RMSK                       = 0xffff,
++      S_SCMO_ADDR_BASE_CSn_MAXn                       = 1,
++      S_SCMO_ADDR_BASE_CSn_ADDR_BASE_BMSK             = 0xfc,
++      S_SCMO_ADDR_BASE_CSn_ADDR_BASE_SHFT             = 0x2,
++};
++
++#define S_SCMO_ADDR_MAP_CSn_ADDR(b, n, o) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000420 + 0x4 * (o))
++enum bimc_s_scmo_addr_map_csn {
++      S_SCMO_ADDR_MAP_CSn_RMSK                = 0xffff,
++      S_SCMO_ADDR_MAP_CSn_MAXn                = 1,
++      S_SCMO_ADDR_MAP_CSn_RANK_EN_BMSK        = 0x8000,
++      S_SCMO_ADDR_MAP_CSn_RANK_EN_SHFT        = 0xf,
++      S_SCMO_ADDR_MAP_CSn_ADDR_MODE_BMSK      = 0x1000,
++      S_SCMO_ADDR_MAP_CSn_ADDR_MODE_SHFT      = 0xc,
++      S_SCMO_ADDR_MAP_CSn_BANK_SIZE_BMSK      = 0x100,
++      S_SCMO_ADDR_MAP_CSn_BANK_SIZE_SHFT      = 0x8,
++      S_SCMO_ADDR_MAP_CSn_ROW_SIZE_BMSK       = 0x30,
++      S_SCMO_ADDR_MAP_CSn_ROW_SIZE_SHFT       = 0x4,
++      S_SCMO_ADDR_MAP_CSn_COL_SIZE_BMSK       = 0x3,
++      S_SCMO_ADDR_MAP_CSn_COL_SIZE_SHFT       = 0x0,
++};
++
++#define S_SCMO_ADDR_MASK_CSn_ADDR(b, n, o) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000430 + 0x4 * (0))
++enum bimc_s_scmo_addr_mask_csn {
++      S_SCMO_ADDR_MASK_CSn_RMSK               = 0xffff,
++      S_SCMO_ADDR_MASK_CSn_MAXn               = 1,
++      S_SCMO_ADDR_MASK_CSn_ADDR_MASK_BMSK     = 0xfc,
++      S_SCMO_ADDR_MASK_CSn_ADDR_MASK_SHFT     = 0x2,
++};
++
++#define S_SCMO_SLV_STATUS_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000450)
++enum bimc_s_scmo_slv_status {
++      S_SCMO_SLV_STATUS_RMSK                          = 0xff3,
++      S_SCMO_SLV_STATUS_GLOBAL_MONS_IN_USE_BMSK       = 0xff0,
++      S_SCMO_SLV_STATUS_GLOBAL_MONS_IN_USE_SHFT       = 0x4,
++      S_SCMO_SLV_STATUS_SLAVE_IDLE_BMSK               = 0x3,
++      S_SCMO_SLV_STATUS_SLAVE_IDLE_SHFT               = 0x0,
++};
++
++#define S_SCMO_CMD_BUF_CFG_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000500)
++enum bimc_s_scmo_cmd_buf_cfg {
++      S_SCMO_CMD_BUF_CFG_RMSK                         = 0xf1f,
++      S_SCMO_CMD_BUF_CFG_CMD_ORDERING_BMSK            = 0x300,
++      S_SCMO_CMD_BUF_CFG_CMD_ORDERING_SHFT            = 0x8,
++      S_SCMO_CMD_BUF_CFG_HP_CMD_AREQPRIO_MAP_BMSK     = 0x10,
++      S_SCMO_CMD_BUF_CFG_HP_CMD_AREQPRIO_MAP_SHFT     = 0x4,
++      S_SCMO_CMD_BUF_CFG_HP_CMD_Q_DEPTH_BMSK          = 0x7,
++      S_SCMO_CMD_BUF_CFG_HP_CMD_Q_DEPTH_SHFT          = 0x0,
++};
++
++#define S_SCM_CMD_BUF_STATUS_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000520)
++enum bimc_s_scm_cmd_buf_status {
++      S_SCMO_CMD_BUF_STATUS_RMSK                              = 0x77,
++      S_SCMO_CMD_BUF_STATUS_HP_CMD_BUF_ENTRIES_IN_USE_BMSK    = 0x70,
++      S_SCMO_CMD_BUF_STATUS_HP_CMD_BUF_ENTRIES_IN_USE_SHFT    = 0x4,
++      S_SCMO_CMD_BUF_STATUS_LP_CMD_BUF_ENTRIES_IN_USE_BMSK    = 0x7,
++      S_SCMO_CMD_BUF_STATUS_LP_CMD_BUF_ENTRIES_IN_USE_SHFT    = 0x0,
++};
++
++#define S_SCMO_RCH_SEL_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000540)
++enum bimc_s_scmo_rch_sel {
++      S_SCMO_RCH_SEL_RMSK                     = 0xffffffff,
++      S_SCMO_CMD_BUF_STATUS_RCH_PORTS_BMSK    = 0xffffffff,
++      S_SCMO_CMD_BUF_STATUS_RCH_PORTS_SHFT    = 0x0,
++};
++
++#define S_SCMO_RCH_BKPR_CFG_ADDR(b, n) \
++              (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000544)
++enum bimc_s_scmo_rch_bkpr_cfg {
++      S_SCMO_RCH_BKPR_CFG_RMSK                        = 0xffffffff,
++      S_SCMO_RCH_BKPR_CFG_RCH1_FIFO_BKPR_HI_TH_BMSK   = 0x3f000000,
++      S_SCMO_RCH_BKPR_CFG_RCH1_FIFO_BKPR_HI_TH_SHFT   = 0x18,
++      S_SCMO_RCH_BKPR_CFG_RCH1_FIFO_BKPR_LO_TH_BMSK   = 0x3f0000,
++      S_SCMO_RCH_BKPR_CFG_RCH1_FIFO_BKPR_LO_TH_SHFT   = 0x10,
++      S_SCMO_RCH_BKPR_CFG_RCH0_FIFO_BKPR_HI_TH_BMSK   = 0x3f00,
++      S_SCMO_RCH_BKPR_CFG_RCH0_FIFO_BKPR_HI_TH_SHFT   = 0x8,
++      S_SCMO_RCH_BKPR_CFG_RCH0_FIFO_BKPR_LO_TH_BMSK   = 0x3f,
++      S_SCMO_RCH_BKPR_CFG_RCH0_FIFO_BKPR_LO_TH_SHFT   = 0x0,
++};
++
++#define S_SCMO_RCH_STATUS_ADDR(b, n) \
++              (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000560)
++enum bimc_s_scmo_rch_status {
++      S_SCMO_RCH_STATUS_RMSK                          = 0x33333,
++      S_SCMO_RCH_STATUS_PRQ_FIFO_FULL_BMSK            = 0x20000,
++      S_SCMO_RCH_STATUS_PRQ_FIFO_FULL_SHFT            = 0x11,
++      S_SCMO_RCH_STATUS_PRQ_FIFO_EMPTY_BMSK           = 0x10000,
++      S_SCMO_RCH_STATUS_PRQ_FIFO_EMPTY_SHFT           = 0x10,
++      S_SCMO_RCH_STATUS_RCH1_QUAL_FIFO_FULL_BMSK      = 0x2000,
++      S_SCMO_RCH_STATUS_RCH1_QUAL_FIFO_FULL_SHFT      = 0xd,
++      S_SCMO_RCH_STATUS_RCH1_QUAL_FIFO_EMPTY_BMSK     = 0x1000,
++      S_SCMO_RCH_STATUS_RCH1_QUAL_FIFO_EMPTY_SHFT     = 0xc,
++      S_SCMO_RCH_STATUS_RCH1_DATA_FIFO_FULL_BMSK      = 0x200,
++      S_SCMO_RCH_STATUS_RCH1_DATA_FIFO_FULL_SHFT      = 0x9,
++      S_SCMO_RCH_STATUS_RCH1_DATA_FIFO_EMPTY_BMSK     = 0x100,
++      S_SCMO_RCH_STATUS_RCH1_DATA_FIFO_EMPTY_SHFT     = 0x8,
++      S_SCMO_RCH_STATUS_RCH0_QUAL_FIFO_FULL_BMSK      = 0x20,
++      S_SCMO_RCH_STATUS_RCH0_QUAL_FIFO_FULL_SHFT      = 0x5,
++      S_SCMO_RCH_STATUS_RCH0_QUAL_FIFO_EMPTY_BMSK     = 0x10,
++      S_SCMO_RCH_STATUS_RCH0_QUAL_FIFO_EMPTY_SHFT     = 0x4,
++      S_SCMO_RCH_STATUS_RCH0_DATA_FIFO_FULL_BMSK      = 0x2,
++      S_SCMO_RCH_STATUS_RCH0_DATA_FIFO_FULL_SHFT      = 0x1,
++      S_SCMO_RCH_STATUS_RCH0_DATA_FIFO_EMPTY_BMSK     = 0x1,
++      S_SCMO_RCH_STATUS_RCH0_DATA_FIFO_EMPTY_SHFT     = 0x0,
++};
++
++#define S_SCMO_WCH_BUF_CFG_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000580)
++enum bimc_s_scmo_wch_buf_cfg {
++      S_SCMO_WCH_BUF_CFG_RMSK                         = 0xff,
++      S_SCMO_WCH_BUF_CFG_WRITE_BLOCK_READ_BMSK        = 0x10,
++      S_SCMO_WCH_BUF_CFG_WRITE_BLOCK_READ_SHFT        = 0x4,
++      S_SCMO_WCH_BUF_CFG_COALESCE_EN_BMSK             = 0x1,
++      S_SCMO_WCH_BUF_CFG_COALESCE_EN_SHFT             = 0x0,
++};
++
++#define S_SCMO_WCH_STATUS_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x000005a0)
++enum bimc_s_scmo_wch_status {
++      S_SCMO_WCH_STATUS_RMSK                          = 0x333,
++      S_SCMO_WCH_STATUS_BRESP_FIFO_FULL_BMSK          = 0x200,
++      S_SCMO_WCH_STATUS_BRESP_FIFO_FULL_SHFT          = 0x9,
++      S_SCMO_WCH_STATUS_BRESP_FIFO_EMPTY_BMSK         = 0x100,
++      S_SCMO_WCH_STATUS_BRESP_FIFO_EMPTY_SHFT         = 0x8,
++      S_SCMO_WCH_STATUS_WDATA_FIFO_FULL_BMSK          = 0x20,
++      S_SCMO_WCH_STATUS_WDATA_FIFO_FULL_SHFT          = 0x5,
++      S_SCMO_WCH_STATUS_WDATA_FIFO_EMPTY_BMSK         = 0x10,
++      S_SCMO_WCH_STATUS_WDATA_FIFO_EMPTY_SHFT         = 0x4,
++      S_SCMO_WCH_STATUS_WBUF_FULL_BMSK                = 0x2,
++      S_SCMO_WCH_STATUS_WBUF_FULL_SHFT                = 0x1,
++      S_SCMO_WCH_STATUS_WBUF_EMPTY_BMSK               = 0x1,
++      S_SCMO_WCH_STATUS_WBUF_EMPTY_SHFT               = 0x0,
++};
++
++#define S_SCMO_FLUSH_CFG_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x000005c0)
++enum bimc_s_scmo_flush_cfg {
++      S_SCMO_FLUSH_CFG_RMSK                           = 0xffffffff,
++      S_SCMO_FLUSH_CFG_FLUSH_IN_ORDER_BMSK            = 0x10000000,
++      S_SCMO_FLUSH_CFG_FLUSH_IN_ORDER_SHFT            = 0x1c,
++      S_SCMO_FLUSH_CFG_FLUSH_IDLE_DELAY_BMSK          = 0x3ff0000,
++      S_SCMO_FLUSH_CFG_FLUSH_IDLE_DELAY_SHFT          = 0x10,
++      S_SCMO_FLUSH_CFG_FLUSH_UPPER_LIMIT_BMSK         = 0xf00,
++      S_SCMO_FLUSH_CFG_FLUSH_UPPER_LIMIT_SHFT         = 0x8,
++      S_SCMO_FLUSH_CFG_FLUSH_LOWER_LIMIT_BMSK         = 0xf,
++      S_SCMO_FLUSH_CFG_FLUSH_LOWER_LIMIT_SHFT         = 0x0,
++};
++
++#define S_SCMO_FLUSH_CMD_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x000005c4)
++enum bimc_s_scmo_flush_cmd {
++      S_SCMO_FLUSH_CMD_RMSK                           = 0xf,
++      S_SCMO_FLUSH_CMD_FLUSH_ALL_BUF_BMSK             = 0x3,
++      S_SCMO_FLUSH_CMD_FLUSH_ALL_BUF_SHFT             = 0x0,
++};
++
++#define S_SCMO_CMD_OPT_CFG0_ADDR(b, n) \
++      (S_SCM0_REG_BASE(b) + (0x8000 * (n)) + 0x00000700)
++enum bimc_s_scmo_cmd_opt_cfg0 {
++      S_SCMO_CMD_OPT_CFG0_RMSK                = 0xffffff,
++      S_SCMO_CMD_OPT_CFG0_IGNORE_BANK_UNAVL_BMSK      = 0x100000,
++      S_SCMO_CMD_OPT_CFG0_IGNORE_BANK_UNAVL_SHFT      = 0x14,
++      S_SCMO_CMD_OPT_CFG0_MASK_CMDOUT_PRI_BMSK        = 0x10000,
++      S_SCMO_CMD_OPT_CFG0_MASK_CMDOUT_PRI_SHFT        = 0x10,
++      S_SCMO_CMD_OPT_CFG0_DPE_CMD_REORDERING_BMSK     = 0x1000,
++      S_SCMO_CMD_OPT_CFG0_DPE_CMD_REORDERING_SHFT     = 0xc,
++      S_SCMO_CMD_OPT_CFG0_WR_OPT_EN_BMSK              = 0x100,
++      S_SCMO_CMD_OPT_CFG0_WR_OPT_EN_SHFT              = 0x8,
++      S_SCMO_CMD_OPT_CFG0_RD_OPT_EN_BMSK              = 0x10,
++      S_SCMO_CMD_OPT_CFG0_RD_OPT_EN_SHFT              = 0x4,
++      S_SCMO_CMD_OPT_CFG0_PAGE_MGMT_POLICY_BMSK       = 0x1,
++      S_SCMO_CMD_OPT_CFG0_PAGE_MGMT_POLICY_SHFT       = 0x0,
++};
++
++#define S_SCMO_CMD_OPT_CFG1_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000704)
++enum bimc_s_scmo_cmd_opt_cfg1 {
++      S_SCMO_CMD_OPT_CFG1_RMSK                        = 0xffffffff,
++      S_SCMO_CMD_OPT_CFG1_HSTP_CMD_TIMEOUT_BMSK       = 0x1f000000,
++      S_SCMO_CMD_OPT_CFG1_HSTP_CMD_TIMEOUT_SHFT       = 0x18,
++      S_SCMO_CMD_OPT_CFG1_HP_CMD_TIMEOUT_BMSK         = 0x1f0000,
++      S_SCMO_CMD_OPT_CFG1_HP_CMD_TIMEOUT_SHFT         = 0x10,
++      S_SCMO_CMD_OPT_CFG1_MP_CMD_TIMEOUT_BMSK         = 0x1f00,
++      S_SCMO_CMD_OPT_CFG1_MP_CMD_TIMEOUT_SHFT         = 0x8,
++      S_SCMO_CMD_OPT_CFG1_LP_CMD_TIMEOUT_BMSK         = 0x1f,
++      S_SCMO_CMD_OPT_CFG1_LP_CMD_TIMEOUT_SHFT         = 0x0,
++};
++
++#define S_SCMO_CMD_OPT_CFG2_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000708)
++enum bimc_s_scmo_cmd_opt_cfg2 {
++      S_SCMO_CMD_OPT_CFG2_RMSK                        = 0xff,
++      S_SCMO_CMD_OPT_CFG2_RWOPT_CMD_TIMEOUT_BMSK      = 0xf,
++      S_SCMO_CMD_OPT_CFG2_RWOPT_CMD_TIMEOUT_SHFT      = 0x0,
++};
++
++#define S_SCMO_CMD_OPT_CFG3_ADDR(b, n) \
++      (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x0000070c)
++enum bimc_s_scmo_cmd_opt_cfg3 {
++      S_SCMO_CMD_OPT_CFG3_RMSK                        = 0xff,
++      S_SCMO_CMD_OPT_CFG3_FLUSH_CMD_TIMEOUT_BMSK      = 0xf,
++      S_SCMO_CMD_OPT_CFG3_FLUSH_CMD_TIMEOUT_SHFT      = 0x0,
++};
++
++/* S_SWAY_GENERIC */
++#define S_SWAY_REG_BASE(b)    ((b) + 0x00048000)
++
++#define S_SWAY_CONFIG_INFO_0_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000020)
++enum bimc_s_sway_config_info_0 {
++      S_SWAY_CONFIG_INFO_0_RMSK               = 0xff0000ff,
++      S_SWAY_CONFIG_INFO_0_SYNC_MODE_BMSK     = 0xff000000,
++      S_SWAY_CONFIG_INFO_0_SYNC_MODE_SHFT     = 0x18,
++      S_SWAY_CONFIG_INFO_0_FUNC_BMSK          = 0xff,
++      S_SWAY_CONFIG_INFO_0_FUNC_SHFT          = 0x0,
++};
++
++#define S_SWAY_CONFIG_INFO_1_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000030)
++enum bimc_s_sway_config_info_1 {
++      S_SWAY_CONFIG_INFO_1_RMSK                       = 0xffffffff,
++      S_SWAY_CONFIG_INFO_1_MPORT_CONNECTIVITY_BMSK    = 0xffffffff,
++      S_SWAY_CONFIG_INFO_1_MPORT_CONNECTIVITY_SHFT    = 0x0,
++};
++
++#define S_SWAY_CONFIG_INFO_2_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000040)
++enum bimc_s_sway_config_info_2 {
++      S_SWAY_CONFIG_INFO_2_RMSK                       = 0xffff0000,
++      S_SWAY_CONFIG_INFO_2_MPORT_CONNECTIVITY_BMSK    = 0xffff0000,
++      S_SWAY_CONFIG_INFO_2_MPORT_CONNECTIVITY_SHFT    = 0x10,
++};
++
++#define S_SWAY_CONFIG_INFO_3_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000050)
++enum bimc_s_sway_config_info_3 {
++      S_SWAY_CONFIG_INFO_3_RMSK                       = 0xffffffff,
++      S_SWAY_CONFIG_INFO_3_RCH0_DEPTH_BMSK            = 0xff000000,
++      S_SWAY_CONFIG_INFO_3_RCH0_DEPTH_SHFT            = 0x18,
++      S_SWAY_CONFIG_INFO_3_BCH_DEPTH_BMSK             = 0xff0000,
++      S_SWAY_CONFIG_INFO_3_BCH_DEPTH_SHFT             = 0x10,
++      S_SWAY_CONFIG_INFO_3_WCH_DEPTH_BMSK             = 0xff,
++      S_SWAY_CONFIG_INFO_3_WCH_DEPTH_SHFT             = 0x0,
++};
++
++#define S_SWAY_CONFIG_INFO_4_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000060)
++enum bimc_s_sway_config_info_4 {
++      S_SWAY_CONFIG_INFO_4_RMSK                       = 0x800000ff,
++      S_SWAY_CONFIG_INFO_4_DUAL_RCH_EN_BMSK           = 0x80000000,
++      S_SWAY_CONFIG_INFO_4_DUAL_RCH_EN_SHFT           = 0x1f,
++      S_SWAY_CONFIG_INFO_4_RCH1_DEPTH_BMSK            = 0xff,
++      S_SWAY_CONFIG_INFO_4_RCH1_DEPTH_SHFT            = 0x0,
++};
++
++#define S_SWAY_CONFIG_INFO_5_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000070)
++enum bimc_s_sway_config_info_5 {
++      S_SWAY_CONFIG_INFO_5_RMSK                       = 0x800000ff,
++      S_SWAY_CONFIG_INFO_5_QCH_EN_BMSK                = 0x80000000,
++      S_SWAY_CONFIG_INFO_5_QCH_EN_SHFT                = 0x1f,
++      S_SWAY_CONFIG_INFO_5_QCH_DEPTH_BMSK             = 0xff,
++      S_SWAY_CONFIG_INFO_5_QCH_DEPTH_SHFT             = 0x0,
++};
++
++#define S_SWAY_CONFIG_INFO_6_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000080)
++enum bimc_s_sway_config_info_6 {
++      S_SWAY_CONFIG_INFO_6_RMSK                       = 0x1,
++      S_SWAY_CONFIG_INFO_6_S2SW_PIPELINE_EN_BMSK      = 0x1,
++      S_SWAY_CONFIG_INFO_6_S2SW_PIPELINE_EN_SHFT      = 0x0,
++};
++
++#define S_SWAY_INT_STATUS_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000100)
++enum bimc_s_sway_int_status {
++      S_SWAY_INT_STATUS_RMSK          = 0x3,
++      S_SWAY_INT_STATUS_RFU_BMSK      = 0x3,
++      S_SWAY_INT_STATUS_RFU_SHFT      = 0x0,
++};
++
++#define S_SWAY_INT_CLR_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000108)
++enum bimc_s_sway_int_clr {
++      S_SWAY_INT_CLR_RMSK             = 0x3,
++      S_SWAY_INT_CLR_RFU_BMSK         = 0x3,
++      S_SWAY_INT_CLR_RFU_SHFT         = 0x0,
++};
++
++
++#define S_SWAY_INT_EN_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x0000010c)
++enum bimc_s_sway_int_en {
++      S_SWAY_INT_EN_RMSK              = 0x3,
++      S_SWAY_INT_EN_RFU_BMSK          = 0x3,
++      S_SWAY_INT_EN_RFU_SHFT          = 0x0,
++};
++
++#define S_SWAY_CLK_CTRL_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000200)
++enum bimc_s_sway_clk_ctrl {
++      S_SWAY_CLK_CTRL_RMSK                            = 0x3,
++      S_SWAY_CLK_CTRL_SLAVE_CLK_GATING_EN_BMSK        = 0x2,
++      S_SWAY_CLK_CTRL_SLAVE_CLK_GATING_EN_SHFT        = 0x1,
++      S_SWAY_CLK_CTRL_CORE_CLK_GATING_EN_BMSK         = 0x1,
++      S_SWAY_CLK_CTRL_CORE_CLK_GATING_EN_SHFT         = 0x0,
++};
++
++#define S_SWAY_RCH_SEL_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000210)
++enum bimc_s_sway_rch_sel {
++      S_SWAY_RCH_SEL_RMSK             = 0x7f,
++      S_SWAY_RCH_SEL_UNUSED_BMSK      = 0x7f,
++      S_SWAY_RCH_SEL_UNUSED_SHFT      = 0x0,
++};
++
++
++#define S_SWAY_MAX_OUTSTANDING_REQS_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000220)
++enum bimc_s_sway_max_outstanding_reqs {
++      S_SWAY_MAX_OUTSTANDING_REQS_RMSK        = 0xffff,
++      S_SWAY_MAX_OUTSTANDING_REQS_WRITE_BMSK  = 0xff00,
++      S_SWAY_MAX_OUTSTANDING_REQS_WRITE_SHFT  = 0x8,
++      S_SWAY_MAX_OUTSTANDING_REQS_READ_BMSK   = 0xff,
++      S_SWAY_MAX_OUTSTANDING_REQS_READ_SHFT   = 0x0,
++};
++
++
++#define S_SWAY_BUF_STATUS_0_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000400)
++enum bimc_s_sway_buf_status_0 {
++      S_SWAY_BUF_STATUS_0_RMSK                        = 0xf0300f03,
++      S_SWAY_BUF_STATUS_0_RCH0_DATA_RD_FULL_BMSK      = 0x80000000,
++      S_SWAY_BUF_STATUS_0_RCH0_DATA_RD_FULL_SHFT      = 0x1f,
++      S_SWAY_BUF_STATUS_0_RCH0_DATA_RD_EMPTY_BMSK     = 0x40000000,
++      S_SWAY_BUF_STATUS_0_RCH0_DATA_RD_EMPTY_SHFT     = 0x1e,
++      S_SWAY_BUF_STATUS_0_RCH0_CTRL_RD_FULL_BMSK      = 0x20000000,
++      S_SWAY_BUF_STATUS_0_RCH0_CTRL_RD_FULL_SHFT      = 0x1d,
++      S_SWAY_BUF_STATUS_0_RCH0_CTRL_RD_EMPTY_BMSK     = 0x10000000,
++      S_SWAY_BUF_STATUS_0_RCH0_CTRL_RD_EMPTY_SHFT     = 0x1c,
++      S_SWAY_BUF_STATUS_0_BCH_RD_FULL_BMSK            = 0x200000,
++      S_SWAY_BUF_STATUS_0_BCH_RD_FULL_SHFT            = 0x15,
++      S_SWAY_BUF_STATUS_0_BCH_RD_EMPTY_BMSK           = 0x100000,
++      S_SWAY_BUF_STATUS_0_BCH_RD_EMPTY_SHFT           = 0x14,
++      S_SWAY_BUF_STATUS_0_WCH_DATA_WR_FULL_BMSK       = 0x800,
++      S_SWAY_BUF_STATUS_0_WCH_DATA_WR_FULL_SHFT       = 0xb,
++      S_SWAY_BUF_STATUS_0_WCH_DATA_WR_EMPTY_BMSK      = 0x400,
++      S_SWAY_BUF_STATUS_0_WCH_DATA_WR_EMPTY_SHFT      = 0xa,
++      S_SWAY_BUF_STATUS_0_WCH_CTRL_WR_FULL_BMSK       = 0x200,
++      S_SWAY_BUF_STATUS_0_WCH_CTRL_WR_FULL_SHFT       = 0x9,
++      S_SWAY_BUF_STATUS_0_WCH_CTRL_WR_EMPTY_BMSK      = 0x100,
++      S_SWAY_BUF_STATUS_0_WCH_CTRL_WR_EMPTY_SHFT      = 0x8,
++      S_SWAY_BUF_STATUS_0_ACH_WR_FULL_BMSK            = 0x2,
++      S_SWAY_BUF_STATUS_0_ACH_WR_FULL_SHFT            = 0x1,
++      S_SWAY_BUF_STATUS_0_ACH_WR_EMPTY_BMSK           = 0x1,
++      S_SWAY_BUF_STATUS_0_ACH_WR_EMPTY_SHFT           = 0x0,
++};
++
++#define S_SWAY_BUF_STATUS_1_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000410)
++enum bimc_s_sway_buf_status_1 {
++      S_SWAY_BUF_STATUS_1_RMSK                        = 0xf0,
++      S_SWAY_BUF_STATUS_1_RCH1_DATA_RD_FULL_BMSK      = 0x80,
++      S_SWAY_BUF_STATUS_1_RCH1_DATA_RD_FULL_SHFT      = 0x7,
++      S_SWAY_BUF_STATUS_1_RCH1_DATA_RD_EMPTY_BMSK     = 0x40,
++      S_SWAY_BUF_STATUS_1_RCH1_DATA_RD_EMPTY_SHFT     = 0x6,
++      S_SWAY_BUF_STATUS_1_RCH1_CTRL_RD_FULL_BMSK      = 0x20,
++      S_SWAY_BUF_STATUS_1_RCH1_CTRL_RD_FULL_SHFT      = 0x5,
++      S_SWAY_BUF_STATUS_1_RCH1_CTRL_RD_EMPTY_BMSK     = 0x10,
++      S_SWAY_BUF_STATUS_1_RCH1_CTRL_RD_EMPTY_SHFT     = 0x4,
++};
++
++#define S_SWAY_BUF_STATUS_2_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000420)
++enum bimc_s_sway_buf_status_2 {
++      S_SWAY_BUF_STATUS_2_RMSK                = 0x30,
++      S_SWAY_BUF_STATUS_2_QCH_RD_FULL_BMSK    = 0x20,
++      S_SWAY_BUF_STATUS_2_QCH_RD_FULL_SHFT    = 0x5,
++      S_SWAY_BUF_STATUS_2_QCH_RD_EMPTY_BMSK   = 0x10,
++      S_SWAY_BUF_STATUS_2_QCH_RD_EMPTY_SHFT   = 0x4,
++};
++
++/* S_ARB_GENERIC */
++
++#define S_ARB_REG_BASE(b)     ((b) + 0x00049000)
++
++#define S_ARB_COMPONENT_INFO_ADDR(b, n) \
++      (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000000)
++enum bimc_s_arb_component_info {
++      S_ARB_COMPONENT_INFO_RMSK               = 0xffffff,
++      S_ARB_COMPONENT_INFO_INSTANCE_BMSK      = 0xff0000,
++      S_ARB_COMPONENT_INFO_INSTANCE_SHFT      = 0x10,
++      S_ARB_COMPONENT_INFO_SUB_TYPE_BMSK      = 0xff00,
++      S_ARB_COMPONENT_INFO_SUB_TYPE_SHFT      = 0x8,
++      S_ARB_COMPONENT_INFO_TYPE_BMSK          = 0xff,
++      S_ARB_COMPONENT_INFO_TYPE_SHFT          = 0x0,
++};
++
++#define S_ARB_CONFIG_INFO_0_ADDR(b, n) \
++              (S_ARB_REG_BASE(b) + (0x8000 * (n)) + 0x00000020)
++enum bimc_s_arb_config_info_0 {
++      S_ARB_CONFIG_INFO_0_RMSK                        = 0x800000ff,
++      S_ARB_CONFIG_INFO_0_ARB2SW_PIPELINE_EN_BMSK     = 0x80000000,
++      S_ARB_CONFIG_INFO_0_ARB2SW_PIPELINE_EN_SHFT     = 0x1f,
++      S_ARB_CONFIG_INFO_0_FUNC_BMSK                   = 0xff,
++      S_ARB_CONFIG_INFO_0_FUNC_SHFT                   = 0x0,
++};
++
++#define S_ARB_CONFIG_INFO_1_ADDR(b, n) \
++              (S_ARB_REG_BASE(b) + (0x8000 * (n)) + 0x00000030)
++enum bimc_s_arb_config_info_1 {
++      S_ARB_CONFIG_INFO_1_RMSK                        = 0xffffffff,
++      S_ARB_CONFIG_INFO_1_MPORT_CONNECTIVITY_BMSK     = 0xffffffff,
++      S_ARB_CONFIG_INFO_1_MPORT_CONNECTIVITY_SHFT     = 0x0,
++};
++
++#define S_ARB_CLK_CTRL_ADDR(b) \
++      (S_ARB_REG_BASE(b) + (0x8000 * (n)) + 0x00000200)
++enum bimc_s_arb_clk_ctrl {
++      S_ARB_CLK_CTRL_RMSK                             = 0x1,
++      S_ARB_CLK_CTRL_SLAVE_CLK_GATING_EN_BMSK         = 0x2,
++      S_ARB_CLK_CTRL_SLAVE_CLK_GATING_EN_SHFT         = 0x1,
++      S_ARB_CLK_CTRL_CORE_CLK_GATING_EN_BMSK          = 0x1,
++      S_ARB_CLK_CTRL_CORE_CLK_GATING_EN_SHFT          = 0x0,
++      S_ARB_CLK_CTRL_CLK_GATING_EN_BMSK               = 0x1,
++      S_ARB_CLK_CTRL_CLK_GATING_EN_SHFT               = 0x0,
++};
++
++#define S_ARB_MODE_ADDR(b, n) \
++      (S_ARB_REG_BASE(b) + (0x8000 * (n)) + 0x00000210)
++enum bimc_s_arb_mode {
++      S_ARB_MODE_RMSK                         = 0xf0000001,
++      S_ARB_MODE_WR_GRANTS_AHEAD_BMSK         = 0xf0000000,
++      S_ARB_MODE_WR_GRANTS_AHEAD_SHFT         = 0x1c,
++      S_ARB_MODE_PRIO_RR_EN_BMSK              = 0x1,
++      S_ARB_MODE_PRIO_RR_EN_SHFT              = 0x0,
++};
++
++#define BKE_HEALTH_MASK \
++      (M_BKE_HEALTH_0_CONFIG_LIMIT_CMDS_BMSK |\
++      M_BKE_HEALTH_0_CONFIG_AREQPRIO_BMSK |\
++      M_BKE_HEALTH_0_CONFIG_PRIOLVL_BMSK)
++
++#define BKE_HEALTH_VAL(limit, areq, plvl) \
++      ((((limit) << M_BKE_HEALTH_0_CONFIG_LIMIT_CMDS_SHFT) & \
++      M_BKE_HEALTH_0_CONFIG_LIMIT_CMDS_BMSK) | \
++      (((areq) << M_BKE_HEALTH_0_CONFIG_AREQPRIO_SHFT) & \
++      M_BKE_HEALTH_0_CONFIG_AREQPRIO_BMSK) | \
++      (((plvl) << M_BKE_HEALTH_0_CONFIG_PRIOLVL_SHFT) & \
++      M_BKE_HEALTH_0_CONFIG_PRIOLVL_BMSK))
++
++#define MAX_GRANT_PERIOD \
++      (M_BKE_GP_GP_BMSK >> \
++      M_BKE_GP_GP_SHFT)
++
++#define MAX_GC \
++      (M_BKE_GC_GC_BMSK >> \
++      (M_BKE_GC_GC_SHFT + 1))
++
++static int bimc_div(int64_t *a, uint32_t b)
++{
++      if ((*a > 0) && (*a < b)) {
++              *a = 0;
++              return 1;
++      } else {
++              return do_div(*a, b);
++      }
++}
++
++#define ENABLE(val) ((val) == 1 ? 1 : 0)
++void msm_bus_bimc_set_mas_clk_gate(struct msm_bus_bimc_info *binfo,
++      uint32_t mas_index, struct msm_bus_bimc_clk_gate *bgate)
++{
++      uint32_t val, mask, reg_val;
++      void __iomem *addr;
++
++      reg_val = readl_relaxed(M_CLK_CTRL_ADDR(binfo->base,
++                      mas_index)) & M_CLK_CTRL_RMSK;
++      addr = M_CLK_CTRL_ADDR(binfo->base, mas_index);
++      mask = (M_CLK_CTRL_MAS_CLK_GATING_EN_BMSK |
++              M_CLK_CTRL_CORE_CLK_GATING_EN_BMSK);
++      val = (bgate->core_clk_gate_en <<
++              M_CLK_CTRL_MAS_CLK_GATING_EN_SHFT) |
++              bgate->port_clk_gate_en;
++      writel_relaxed(((reg_val & (~mask)) | (val & mask)), addr);
++      /* Ensure clock gating enable mask is set before exiting */
++      wmb();
++}
++
++void msm_bus_bimc_arb_en(struct msm_bus_bimc_info *binfo,
++      uint32_t slv_index, bool en)
++{
++      uint32_t reg_val, reg_mask_val, enable, val;
++
++      reg_mask_val = (readl_relaxed(S_ARB_CONFIG_INFO_0_ADDR(binfo->
++              base, slv_index)) & S_ARB_CONFIG_INFO_0_FUNC_BMSK)
++              >> S_ARB_CONFIG_INFO_0_FUNC_SHFT;
++      enable = ENABLE(en);
++      val = enable << S_ARB_MODE_PRIO_RR_EN_SHFT;
++      if (reg_mask_val == BIMC_ARB_MODE_PRIORITY_RR) {
++              reg_val = readl_relaxed(S_ARB_CONFIG_INFO_0_ADDR(binfo->
++                      base, slv_index)) & S_ARB_MODE_RMSK;
++              writel_relaxed(((reg_val & (~(S_ARB_MODE_PRIO_RR_EN_BMSK))) |
++                      (val & S_ARB_MODE_PRIO_RR_EN_BMSK)),
++                      S_ARB_MODE_ADDR(binfo->base, slv_index));
++              /* Ensure arbitration mode is set before returning */
++              wmb();
++      }
++}
++
++static void set_qos_mode(void __iomem *baddr, uint32_t index, uint32_t val0,
++      uint32_t val1, uint32_t val2)
++{
++      uint32_t reg_val, val;
++
++      reg_val = readl_relaxed(M_PRIOLVL_OVERRIDE_ADDR(baddr,
++              index)) & M_PRIOLVL_OVERRIDE_RMSK;
++      val = val0 << M_PRIOLVL_OVERRIDE_OVERRIDE_PRIOLVL_SHFT;
++      writel_relaxed(((reg_val & ~(M_PRIOLVL_OVERRIDE_OVERRIDE_PRIOLVL_BMSK))
++              | (val & M_PRIOLVL_OVERRIDE_OVERRIDE_PRIOLVL_BMSK)),
++              M_PRIOLVL_OVERRIDE_ADDR(baddr, index));
++      reg_val = readl_relaxed(M_RD_CMD_OVERRIDE_ADDR(baddr, index)) &
++              M_RD_CMD_OVERRIDE_RMSK;
++      val = val1 << M_RD_CMD_OVERRIDE_OVERRIDE_AREQPRIO_SHFT;
++      writel_relaxed(((reg_val & ~(M_RD_CMD_OVERRIDE_OVERRIDE_AREQPRIO_BMSK
++              )) | (val & M_RD_CMD_OVERRIDE_OVERRIDE_AREQPRIO_BMSK)),
++              M_RD_CMD_OVERRIDE_ADDR(baddr, index));
++      reg_val = readl_relaxed(M_WR_CMD_OVERRIDE_ADDR(baddr, index)) &
++              M_WR_CMD_OVERRIDE_RMSK;
++      val = val2 << M_WR_CMD_OVERRIDE_OVERRIDE_AREQPRIO_SHFT;
++      writel_relaxed(((reg_val & ~(M_WR_CMD_OVERRIDE_OVERRIDE_AREQPRIO_BMSK
++              )) | (val & M_WR_CMD_OVERRIDE_OVERRIDE_AREQPRIO_BMSK)),
++              M_WR_CMD_OVERRIDE_ADDR(baddr, index));
++      /* Ensure the priority register writes go through */
++      wmb();
++}
++
++static void msm_bus_bimc_set_qos_mode(void __iomem *base,
++      uint32_t mas_index, uint8_t qmode_sel)
++{
++      uint32_t reg_val, val;
++
++      switch (qmode_sel) {
++      case BIMC_QOS_MODE_FIXED:
++              reg_val = readl_relaxed(M_BKE_EN_ADDR(base,
++                      mas_index));
++              writel_relaxed((reg_val & (~M_BKE_EN_EN_BMSK)),
++                      M_BKE_EN_ADDR(base, mas_index));
++              /* Ensure that the book-keeping register writes
++               * go through before setting QoS mode.
++               * QoS mode registers might write beyond 1K
++               * boundary in future
++               */
++              wmb();
++              set_qos_mode(base, mas_index, 1, 1, 1);
++              break;
++
++      case BIMC_QOS_MODE_BYPASS:
++              reg_val = readl_relaxed(M_BKE_EN_ADDR(base,
++                      mas_index));
++              writel_relaxed((reg_val & (~M_BKE_EN_EN_BMSK)),
++                      M_BKE_EN_ADDR(base, mas_index));
++              /* Ensure that the book-keeping register writes
++               * go through before setting QoS mode.
++               * QoS mode registers might write beyond 1K
++               * boundary in future
++               */
++              wmb();
++              set_qos_mode(base, mas_index, 0, 0, 0);
++              break;
++
++      case BIMC_QOS_MODE_REGULATOR:
++      case BIMC_QOS_MODE_LIMITER:
++              set_qos_mode(base, mas_index, 0, 0, 0);
++              reg_val = readl_relaxed(M_BKE_EN_ADDR(base,
++                      mas_index));
++              val = 1 << M_BKE_EN_EN_SHFT;
++              /* Ensure that the book-keeping register writes
++               * go through before setting QoS mode.
++               * QoS mode registers might write beyond 1K
++               * boundary in future
++               */
++              wmb();
++              writel_relaxed(((reg_val & (~M_BKE_EN_EN_BMSK)) | (val &
++                      M_BKE_EN_EN_BMSK)), M_BKE_EN_ADDR(base,
++                      mas_index));
++              break;
++      default:
++              break;
++      }
++}
++
++static void set_qos_prio_rl(void __iomem *addr, uint32_t rmsk,
++      uint8_t index, struct msm_bus_bimc_qos_mode *qmode)
++{
++      uint32_t reg_val, val0, val;
++
++      /* Note, addr is already passed with right mas_index */
++      reg_val = readl_relaxed(addr) & rmsk;
++      val0 = BKE_HEALTH_VAL(qmode->rl.qhealth[index].limit_commands,
++              qmode->rl.qhealth[index].areq_prio,
++              qmode->rl.qhealth[index].prio_level);
++      val = ((reg_val & (~(BKE_HEALTH_MASK))) | (val0 & BKE_HEALTH_MASK));
++      writel_relaxed(val, addr);
++      /* Ensure that priority for regulator/limiter modes are
++       * set before returning
++       */
++      wmb();
++
++}
++
++static void msm_bus_bimc_set_qos_prio(void __iomem *base,
++      uint32_t mas_index, uint8_t qmode_sel,
++      struct msm_bus_bimc_qos_mode *qmode)
++{
++      uint32_t reg_val, val;
++
++      switch (qmode_sel) {
++      case BIMC_QOS_MODE_FIXED:
++              reg_val = readl_relaxed(M_PRIOLVL_OVERRIDE_ADDR(
++                      base, mas_index)) & M_PRIOLVL_OVERRIDE_RMSK;
++              val =  qmode->fixed.prio_level <<
++                      M_PRIOLVL_OVERRIDE_SHFT;
++              writel_relaxed(((reg_val &
++                      ~(M_PRIOLVL_OVERRIDE_BMSK)) | (val
++                      & M_PRIOLVL_OVERRIDE_BMSK)),
++                      M_PRIOLVL_OVERRIDE_ADDR(base, mas_index));
++
++              reg_val = readl_relaxed(M_RD_CMD_OVERRIDE_ADDR(
++                      base, mas_index)) & M_RD_CMD_OVERRIDE_RMSK;
++              val =  qmode->fixed.areq_prio_rd <<
++                      M_RD_CMD_OVERRIDE_AREQPRIO_SHFT;
++              writel_relaxed(((reg_val & ~(M_RD_CMD_OVERRIDE_AREQPRIO_BMSK))
++                      | (val & M_RD_CMD_OVERRIDE_AREQPRIO_BMSK)),
++                      M_RD_CMD_OVERRIDE_ADDR(base, mas_index));
++
++              reg_val = readl_relaxed(M_WR_CMD_OVERRIDE_ADDR(
++                      base, mas_index)) & M_WR_CMD_OVERRIDE_RMSK;
++              val =  qmode->fixed.areq_prio_wr <<
++                      M_WR_CMD_OVERRIDE_AREQPRIO_SHFT;
++              writel_relaxed(((reg_val & ~(M_WR_CMD_OVERRIDE_AREQPRIO_BMSK))
++                      | (val & M_WR_CMD_OVERRIDE_AREQPRIO_BMSK)),
++                      M_WR_CMD_OVERRIDE_ADDR(base, mas_index));
++              /* Ensure that fixed mode register writes go through
++               * before returning
++               */
++              wmb();
++              break;
++
++      case BIMC_QOS_MODE_REGULATOR:
++      case BIMC_QOS_MODE_LIMITER:
++              set_qos_prio_rl(M_BKE_HEALTH_3_CONFIG_ADDR(base,
++                      mas_index), M_BKE_HEALTH_3_CONFIG_RMSK, 3, qmode);
++              set_qos_prio_rl(M_BKE_HEALTH_2_CONFIG_ADDR(base,
++                      mas_index), M_BKE_HEALTH_2_CONFIG_RMSK, 2, qmode);
++              set_qos_prio_rl(M_BKE_HEALTH_1_CONFIG_ADDR(base,
++                      mas_index), M_BKE_HEALTH_1_CONFIG_RMSK, 1, qmode);
++              set_qos_prio_rl(M_BKE_HEALTH_0_CONFIG_ADDR(base,
++                      mas_index), M_BKE_HEALTH_0_CONFIG_RMSK, 0 , qmode);
++              break;
++      case BIMC_QOS_MODE_BYPASS:
++      default:
++              break;
++      }
++}
++
++static void set_qos_bw_regs(void __iomem *baddr, uint32_t mas_index,
++      int32_t th, int32_t tm, int32_t tl, uint32_t gp,
++      uint32_t gc)
++{
++      int32_t reg_val, val;
++      int32_t bke_reg_val;
++      int16_t val2;
++
++      /* Disable BKE before writing to registers as per spec */
++      bke_reg_val = readl_relaxed(M_BKE_EN_ADDR(baddr, mas_index));
++      writel_relaxed((bke_reg_val & ~(M_BKE_EN_EN_BMSK)),
++              M_BKE_EN_ADDR(baddr, mas_index));
++
++      /* Write values of registers calculated */
++      reg_val = readl_relaxed(M_BKE_GP_ADDR(baddr, mas_index))
++              & M_BKE_GP_RMSK;
++      val =  gp << M_BKE_GP_GP_SHFT;
++      writel_relaxed(((reg_val & ~(M_BKE_GP_GP_BMSK)) | (val &
++              M_BKE_GP_GP_BMSK)), M_BKE_GP_ADDR(baddr, mas_index));
++
++      reg_val = readl_relaxed(M_BKE_GC_ADDR(baddr, mas_index)) &
++              M_BKE_GC_RMSK;
++      val =  gc << M_BKE_GC_GC_SHFT;
++      writel_relaxed(((reg_val & ~(M_BKE_GC_GC_BMSK)) | (val &
++              M_BKE_GC_GC_BMSK)), M_BKE_GC_ADDR(baddr, mas_index));
++
++      reg_val = readl_relaxed(M_BKE_THH_ADDR(baddr, mas_index)) &
++              M_BKE_THH_RMSK;
++      val =  th << M_BKE_THH_THRESH_SHFT;
++      writel_relaxed(((reg_val & ~(M_BKE_THH_THRESH_BMSK)) | (val &
++              M_BKE_THH_THRESH_BMSK)), M_BKE_THH_ADDR(baddr, mas_index));
++
++      reg_val = readl_relaxed(M_BKE_THM_ADDR(baddr, mas_index)) &
++              M_BKE_THM_RMSK;
++      val2 =  tm << M_BKE_THM_THRESH_SHFT;
++      writel_relaxed(((reg_val & ~(M_BKE_THM_THRESH_BMSK)) | (val2 &
++              M_BKE_THM_THRESH_BMSK)), M_BKE_THM_ADDR(baddr, mas_index));
++
++      reg_val = readl_relaxed(M_BKE_THL_ADDR(baddr, mas_index)) &
++              M_BKE_THL_RMSK;
++      val2 =  tl << M_BKE_THL_THRESH_SHFT;
++      writel_relaxed(((reg_val & ~(M_BKE_THL_THRESH_BMSK)) |
++              (val2 & M_BKE_THL_THRESH_BMSK)), M_BKE_THL_ADDR(baddr,
++              mas_index));
++
++      /* Ensure that all bandwidth register writes have completed
++       * before returning
++       */
++      wmb();
++}
++
++static void msm_bus_bimc_set_qos_bw(void __iomem *base, uint32_t qos_freq,
++      uint32_t mas_index, struct msm_bus_bimc_qos_bw *qbw)
++{
++      uint32_t bke_en;
++
++      /* Validate QOS Frequency */
++      if (qos_freq == 0) {
++              MSM_BUS_DBG("Zero frequency\n");
++              return;
++      }
++
++      /* Get enable bit for BKE before programming the period */
++      bke_en = (readl_relaxed(M_BKE_EN_ADDR(base, mas_index)) &
++              M_BKE_EN_EN_BMSK) >> M_BKE_EN_EN_SHFT;
++
++      /* Only calculate if there's a requested bandwidth and window */
++      if (qbw->bw && qbw->ws) {
++              int64_t th, tm, tl;
++              uint32_t gp, gc;
++              int64_t gp_nominal, gp_required, gp_calc, data, temp;
++              int64_t win = qbw->ws * qos_freq;
++              temp = win;
++              /*
++               * Calculate nominal grant period defined by requested
++               * window size.
++               * Ceil this value to max grant period.
++               */
++              bimc_div(&temp, 1000000);
++              gp_nominal = min_t(uint64_t, MAX_GRANT_PERIOD, temp);
++              /*
++               * Calculate max window size, defined by bw request.
++               * Units: (KHz, MB/s)
++               */
++              gp_calc = MAX_GC * qos_freq * 1000;
++              gp_required = gp_calc;
++              bimc_div(&gp_required, qbw->bw);
++
++              /* User min of two grant periods */
++              gp = min_t(int64_t, gp_nominal, gp_required);
++
++              /* Calculate bandwith in grants and ceil. */
++              temp = qbw->bw * gp;
++              data = qos_freq * 1000;
++              bimc_div(&temp, data);
++              gc = min_t(int64_t, MAX_GC, temp);
++
++              /* Calculate thresholds */
++              th = qbw->bw - qbw->thh;
++              tm = qbw->bw - qbw->thm;
++              tl = qbw->bw - qbw->thl;
++
++              th = th * gp;
++              bimc_div(&th, data);
++              tm = tm * gp;
++              bimc_div(&tm, data);
++              tl = tl * gp;
++              bimc_div(&tl, data);
++
++              MSM_BUS_DBG("BIMC: BW: mas_index: %d, th: %llu tm: %llu\n",
++                      mas_index, th, tm);
++              MSM_BUS_DBG("BIMC: tl: %llu gp:%u gc: %u bke_en: %u\n",
++                      tl, gp, gc, bke_en);
++              set_qos_bw_regs(base, mas_index, th, tm, tl, gp, gc);
++      } else
++              /* Clear bandwidth registers */
++              set_qos_bw_regs(base, mas_index, 0, 0, 0, 0, 0);
++}
++
++static int msm_bus_bimc_allocate_commit_data(struct msm_bus_fabric_registration
++      *fab_pdata, void **cdata, int ctx)
++{
++      struct msm_bus_bimc_commit **cd = (struct msm_bus_bimc_commit **)cdata;
++      struct msm_bus_bimc_info *binfo =
++              (struct msm_bus_bimc_info *)fab_pdata->hw_data;
++
++      MSM_BUS_DBG("Allocating BIMC commit data\n");
++      *cd = kzalloc(sizeof(struct msm_bus_bimc_commit), GFP_KERNEL);
++      if (!*cd) {
++              MSM_BUS_DBG("Couldn't alloc mem for cdata\n");
++              return -ENOMEM;
++      }
++
++      (*cd)->mas = binfo->cdata[ctx].mas;
++      (*cd)->slv = binfo->cdata[ctx].slv;
++
++      return 0;
++}
++
++static void *msm_bus_bimc_allocate_bimc_data(struct platform_device *pdev,
++      struct msm_bus_fabric_registration *fab_pdata)
++{
++      struct resource *bimc_mem;
++      struct resource *bimc_io;
++      struct msm_bus_bimc_info *binfo;
++      int i;
++
++      MSM_BUS_DBG("Allocating BIMC data\n");
++      binfo = kzalloc(sizeof(struct msm_bus_bimc_info), GFP_KERNEL);
++      if (!binfo) {
++              WARN(!binfo, "Couldn't alloc mem for bimc_info\n");
++              return NULL;
++      }
++
++      binfo->qos_freq = fab_pdata->qos_freq;
++
++      binfo->params.nmasters = fab_pdata->nmasters;
++      binfo->params.nslaves = fab_pdata->nslaves;
++      binfo->params.bus_id = fab_pdata->id;
++
++      for (i = 0; i < NUM_CTX; i++) {
++              binfo->cdata[i].mas = kzalloc(sizeof(struct
++                      msm_bus_node_hw_info) * fab_pdata->nmasters * 2,
++                      GFP_KERNEL);
++              if (!binfo->cdata[i].mas) {
++                      MSM_BUS_ERR("Couldn't alloc mem for bimc master hw\n");
++                      kfree(binfo);
++                      return NULL;
++