ipq806x: fix EA8500 switch control
authorPavel Kubelun <be.dissent@gmail.com>
Thu, 18 Jan 2018 16:45:15 +0000 (19:45 +0300)
committerJohn Crispin <john@phrozen.org>
Thu, 24 May 2018 15:24:31 +0000 (17:24 +0200)
EA8500 has pcie2 slot unequipped.
By EA8500 hw design default pcie2 reset gpio (gpio63) is used to
reset the switch. That's why enabling pcie2 brings the switch into
a working state.

So let's just control the gpio63 without enabling the pcie2 slot.

We have to remove the pcie2_pins node so the gpio63 is not defined
twice. Because pcie2 node has a reference to pcie2_pins we have to
remove it as well.

Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
[slh: rebase for kernel v4.14 as well]
Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
(cherry picked from commit 7f694ef3d9f1121c03935c330093c594b8437098)

target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts

index 2c8fe92..cd8fa63 100644 (file)
 
        soc {
                pinmux@800000 {
+
+                       pinctrl-0 = <&switch_reset>;
+                       pinctrl-names = "default";
+
                        button_pins: button_pins {
                                mux {
                                        pins = "gpio65", "gpio67", "gpio68";
                                };
                        };
 
+                       switch_reset: switch_reset_pins {
+                               mux {
+                                       pins = "gpio63";
+                                       function = "gpio";
+                                       drive-strength = <2>;
+                                       bias-disable;
+                                       output-low;
+                               };
+                       };
+
                        mdio0_pins: mdio0_pins {
                                mux {
                                        pins = "gpio0", "gpio1";
                        status = "ok";
                };
 
-               pcie2: pci@1b900000 {
-                       status = "ok";
-               };
-
                nand@1ac00000 {
                        status = "ok";
 
                };
        };
 };
+
+/delete-node/ &pcie2_pins;
+/delete-node/ &pcie2;
index 7f49db2..8e1a9c4 100644 (file)
 
        soc {
                pinmux@800000 {
+
+                       pinctrl-0 = <&switch_reset>;
+                       pinctrl-names = "default";
+
                        button_pins: button_pins {
                                mux {
                                        pins = "gpio65", "gpio67", "gpio68";
                                };
                        };
 
+                       switch_reset: switch_reset_pins {
+                               mux {
+                                       pins = "gpio63";
+                                       function = "gpio";
+                                       drive-strength = <2>;
+                                       bias-disable;
+                                       output-low;
+                               };
+                       };
+
                        mdio0_pins: mdio0_pins {
                                mux {
                                        pins = "gpio0", "gpio1";
                        status = "ok";
                };
 
-               pcie2: pci@1b900000 {
-                       status = "ok";
-               };
-
                nand@1ac00000 {
                        status = "ok";
 
                };
        };
 };
+
+/delete-node/ &pcie2_pins;
+/delete-node/ &pcie2;