mediatek: backport upstream mediatek patches
authorJohn Crispin <john@phrozen.org>
Mon, 7 May 2018 10:07:32 +0000 (12:07 +0200)
committerJohn Crispin <john@phrozen.org>
Mon, 18 Jun 2018 19:21:53 +0000 (21:21 +0200)
Signed-off-by: John Crispin <john@phrozen.org>
(cherry picked from commit 050da2107a7eb2a571a8a3d0cee21cc6a44b72b8)

132 files changed:
target/linux/mediatek/32/profiles/default.mk [deleted file]
target/linux/mediatek/32/target.mk [deleted file]
target/linux/mediatek/Makefile
target/linux/mediatek/base-files/etc/inittab
target/linux/mediatek/base-files/lib/upgrade/platform.sh
target/linux/mediatek/config-4.14 [deleted file]
target/linux/mediatek/image/32.mk [deleted file]
target/linux/mediatek/image/Makefile
target/linux/mediatek/image/mt7623.mk [new file with mode: 0644]
target/linux/mediatek/mt7623/config-4.14 [new file with mode: 0644]
target/linux/mediatek/mt7623/profiles/default.mk [new file with mode: 0644]
target/linux/mediatek/mt7623/target.mk [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0101-reset-mediatek-add-reset-controller-dt-bindings-requ.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0102-soc-mediatek-pwrap-fixup-warnings-from-coding-style.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0104-usb-mtu3-support-option-to-disable-usb3-ports.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0105-usb-mtu3-remove-dummy-wakeup-debounce-clocks.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0106-usb-mtu3-add-optional-mcu-and-dma-bus-clocks.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0107-usb-mtu3-support-36-bit-DMA-address.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0108-usb-mtu3-use-FORCE-RG_IDDIG-to-implement-manual-DRD-.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0109-usb-mtu3-add-support-for-usb3.1-IP.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0110-usb-mtu3-get-optional-vbus-for-host-only-mode.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0111-usb-mtu3-set-invalid-dr_mode-as-dual-role-mode.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0112-usb-mtu3-set-otg_sel-for-u2port-only-if-works-as-dua.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0113-dt-bindings-usb-mtu3-add-a-optional-property-to-disa.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0114-dt-bindings-usb-mtu3-remove-dummy-clocks-and-add-opt.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0115-dt-bindings-usb-mtu3-remove-optional-pinctrls.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0116-dt-bindings-arm-mediatek-add-MT7622-string-to-the-PM.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0117-soc-mediatek-pwrap-add-pwrap_read32-for-reading-in-3.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0118-soc-mediatek-pwrap-add-pwrap_write32-for-writing-in-.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0119-soc-mediatek-pwrap-refactor-pwrap_init-for-the-vario.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0120-soc-mediatek-pwrap-add-MediaTek-MT6380-as-one-slave-.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0121-soc-mediatek-pwrap-add-common-way-for-setup-CS-timin.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0122-soc-mediatek-pwrap-add-support-for-MT7622-SoC.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0123-soc-mediatek-place-Kconfig-for-all-SoC-drivers-under.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0124-arm64-mediatek-cleanup-message-for-platform-selectio.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0125-phy-phy-mtk-tphy-add-set_mode-callback.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0126-usb-xhci-mtk-use-dma_set_mask_and_coherent-in-probe-.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0127-usb-xhci-mtk-use-ports-count-from-xhci-in-xhci_mtk_s.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0128-usb-xhci-mtk-check-clock-stability-of-U3_MAC.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0129-usb-xhci-mtk-support-option-to-disable-usb3-ports.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0130-usb-xhci-mtk-remove-dummy-wakeup-debounce-clocks.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0131-usb-xhci-mtk-add-optional-mcu-and-dma-bus-clocks.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0132-usb-host-modify-description-for-MTK-xHCI-config.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0133-dt-bindings-usb-mtk-xhci-add-a-optional-property-to-.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0134-dt-bindings-usb-mtk-xhci-remove-dummy-clocks-and-add.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0135-dt-bindings-mtd-add-new-compatible-strings-and-impro.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0136-mtd-mtk-nor-add-suspend-resume-support.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0137-dt-bindings-rtc-mediatek-add-bindings-for-MediaTek-S.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0138-rtc-mediatek-add-driver-for-RTC-on-MT7622-SoC.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0139-rtc-mediatek-enhance-the-description-for-MediaTek-PM.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0140-mtd-nand-mtk-change-the-compile-sequence-of-mtk_nand.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0142-mmc-dt-bindings-Add-reg-source_cg-latch-ck-for-Media.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0143-mmc-mediatek-add-support-of-mt2701-mt2712.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0144-dt-bindings-ARM-Mediatek-Document-bindings-for-MT271.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0145-clk-mediatek-Add-dt-bindings-for-MT2712-clocks.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0146-clk-mediatek-Add-MT2712-clock-support.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0147-dt-bindings-clock-mediatek-document-clk-bindings-for.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0149-clk-mediatek-add-clocks-dt-bindings-required-header-.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0150-clk-mediatek-add-clock-support-for-MT7622-SoC.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0151-arm64-dts-mt8173-remove-mediatek-mt8135-mmc-from-mmc.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0152-mmc-mediatek-make-hs400_tune_response-only-for-mt817.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0153-mmc-mediatek-add-pad_tune0-support.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0154-mmc-mediatek-add-async-fifo-and-data-tune-support.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0155-mmc-mediatek-add-busy_check-support.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0156-mmc-mediatek-add-stop_clk-fix-and-enhance_rx-support.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0157-mmc-mediatek-add-support-of-source_cg-clock.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0158-mmc-mediatek-add-latch-ck-support.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0159-mmc-mediatek-improve-eMMC-hs400-mode-read-performanc.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0160-mmc-mediatek-perfer-to-use-rise-edge-latching-for-cm.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0161-pwm-mediatek-Add-MT2712-MT7622-support.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0162-mtd-nand-mtk-use-nand_reset-to-reset-NAND-devices-in.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0164-cpufreq-mediatek-add-mt2712-into-compatible-list.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0165-mtd-nand-mtk-update-DT-bindings.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0166-mtd-nand-mtk-Support-different-MTK-NAND-flash-contro.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0167-mtd-nand-mtk-Support-MT7622-NAND-flash-controller.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0168-mmc-dt-bindings-add-mmc-support-to-MT7623-SoC.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0169-dt-bindings-pinctrl-add-bindings-for-MediaTek-MT7622.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0170-pinctrl-mediatek-cleanup-for-placing-all-drivers-und.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0171-pinctrl-mediatek-add-pinctrl-driver-for-MT7622-SoC.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0172-clk-mediatek-group-drivers-under-indpendent-menu.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0173-clk-mediatek-fixup-test-building-of-MediaTek-clock-d.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0174-dt-bindings-net-mediatek-add-condition-to-property-m.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0175-net-mediatek-remove-superfluous-pin-setup-for-MT7622.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0176-clk-mediatek-Fix-all-warnings-for-missing-struct-clk.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0177-phy-phy-mtk-tphy-use-auto-instead-of-force-to-bypass.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0178-phy-phy-mtk-tphy-make-shared-banks-optional-for-V1-T.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0179-phy-phy-mtk-tphy-use-of_device_get_match_data.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0180-ASoC-mediatek-fix-error-handling-in-mt2701_afe_pcm_d.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0181-ASoC-mediatek-rework-clock-functions-for-MT2701.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0182-ASoC-mediatek-cleanup-audio-driver-for-MT2701.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0183-ASoC-mediatek-update-clock-related-properties-of-MT2.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0184-ASoC-mediatek-add-some-core-clocks-for-MT2701-AFE.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0185-ASoC-mediatek-modify-MT2701-AFE-driver-to-adapt-mfd-.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0186-ASoC-mediatek-update-MT2701-AFE-documentation-to-ada.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0187-usb-mtu3-fix-error-code-for-getting-extcon-device.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0188-usb-mtu3-supports-remote-wakeup-for-mt2712-with-two-.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0189-dt-bindings-usb-mtu3-update-USB-wakeup-properties.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0190-usb-xhci-mtk-supports-remote-wakeup-for-mt2712-with-.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0191-usb-xhci-allow-imod-interval-to-be-configurable.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0192-dt-bindings-usb-mtk-xhci-update-USB-wakeup-propertie.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0193-clk-mediatek-adjust-dependency-of-reset.c-to-avoid-u.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0194-pinctrl-mediatek-mt7622-fix-potential-uninitialized-.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0195-pinctrl-mediatek-mt7622-align-error-handling-of-mtk_.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0196-mtd-mtk-nor-modify-functions-name-more-generally.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0197-hwrng-mediatek-Setup-default-RNG-quality.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0198-dt-bindings-thermal-add-binding-for-MT7622-SoC.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0199-thermal-mtk-Cleanup-unused-defines.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0200-thermal-mediatek-add-support-for-MT7622-SoC.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0201-dt-bindings-clock-mediatek-add-missing-required-rese.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0202-mmc-dt-bindings-add-support-for-MT7622-SoC.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0203-mmc-mediatek-add-support-for-MT7622-SoC.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0204-dt-bindings-dmaengine-Add-MediaTek-High-Speed-DMA-co.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0205-dmaengine-mediatek-Add-MediaTek-High-Speed-DMA-contr.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0206-dt-bindings-clock-mediatek-update-audsys-documentati.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0207-dt-bindings-clock-mediatek-add-audsys-support-for-MT.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0208-clk-mediatek-update-missing-clock-data-for-MT7622-au.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0209-clk-mediatek-add-devm_of_platform_populate-for-MT762.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0210-arm64-dts-mt7622-add-clock-controller-device-nodes.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0211-arm64-dts-mt7622-add-power-domain-controller-device-.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0212-arm64-dts-mt7622-add-pinctrl-related-device-nodes.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0213-arm64-dts-mt7622-add-PMIC-MT6380-related-nodes.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0214-arm64-dts-mt7622-add-cpufreq-related-device-nodes.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0215-arm64-dts-mt7622-turn-uart0-clock-to-real-ones.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0216-arm64-dts-mt7622-add-SoC-and-peripheral-related-devi.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0217-arm64-dts-mt7622-add-flash-related-device-nodes.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0218-arm64-dts-mt7622-add-ethernet-device-nodes.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0219-arm64-dts-mt7622-add-PCIe-device-nodes.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0220-arm64-dts-mt7622-add-SATA-device-nodes.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0221-arm64-dts-mt7622-add-usb-device-nodes.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0222-arm64-dts-mt7622-add-High-Speed-DMA-device-nodes.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0223-arm64-dts-mt7622-add-mmc-related-device-nodes.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.14/0224-add-mt7622-defconfig-for-testing-these-new-drivers.patch [new file with mode: 0644]

diff --git a/target/linux/mediatek/32/profiles/default.mk b/target/linux/mediatek/32/profiles/default.mk
deleted file mode 100644 (file)
index 2ef570b..0000000
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Copyright (C) 2015 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Default
-       NAME:=Default Profile (minimum package set)
-endef
-
-define Profile/Default/Description
-       Default package set compatible with most boards.
-endef
-$(eval $(call Profile,Default))
diff --git a/target/linux/mediatek/32/target.mk b/target/linux/mediatek/32/target.mk
deleted file mode 100644 (file)
index 0a444c2..0000000
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright (C) 2009 OpenWrt.org
-#
-
-SUBTARGET:=32
-BOARDNAME:=32bit
-CPU_TYPE:=cortex-a7
-CPU_SUBTYPE:=neon-vfpv4
-
-define Target/Description
-       Build firmware images for MediaTek 32bit ARM based boards.
-endef
-
index 6b30f3b..7b8742d 100644 (file)
@@ -5,14 +5,12 @@ include $(TOPDIR)/rules.mk
 ARCH:=arm
 BOARD:=mediatek
 BOARDNAME:=MediaTek Ralink ARM
-SUBTARGETS:=32
+SUBTARGETS:=mt7623
 FEATURES:=squashfs nand ramdisk fpu
 MAINTAINER:=John Crispin <john@phrozen.org>
 
 KERNEL_PATCHVER:=4.14
 
-KERNELNAME:=Image dtbs zImage
-
 include $(INCLUDE_DIR)/target.mk
 DEFAULT_PACKAGES += \
        kmod-mt76 kmod-leds-gpio kmod-gpio-button-hotplug \
index b169c82..9820e71 100644 (file)
@@ -1,3 +1,3 @@
 ::sysinit:/etc/init.d/rcS S boot
 ::shutdown:/etc/init.d/rcS K shutdown
-ttyS0::askfirst:/usr/libexec/login.sh
+::askconsole:/usr/libexec/login.sh
index 0429ca8..646ce0d 100755 (executable)
@@ -1,49 +1,29 @@
-#
-# Copyright (C) 2016 OpenWrt.org
-#
+platform_do_upgrade() {                 
+       default_do_upgrade "$ARGV"                                               
+}                                                                                
 
-platform_do_upgrade() {
-       local tar_file="$1"
-       local board="$(board_name)"
+PART_NAME=firmware
 
-       case "$(board_name)" in
-       mediatek,mt7623-rfb-nand-ephy |\
-       mediatek,mt7623-rfb-nand)
-               nand_do_upgrade $1
-               ;;
-       *)
-               echo "flashing kernel"
-               tar xf $tar_file sysupgrade-$board/kernel -O | mtd write - kernel
+platform_check_image() {                                                         
+       local board=$(board_name)                                                
+       local magic="$(get_magic_long "$1")"                                     
 
-               echo "flashing rootfs"
-               tar xf $tar_file sysupgrade-$board/root -O | mtd write - rootfs
+       [ "$#" -gt 1 ] && return 1                                               
 
-               return 0
-               ;;
-       esac
-}
+       case "$board" in                                                       
+       bananapi,bpi-r2)                                                       
+               [ "$magic" != "27051956" ] && {   
+                       echo "Invalid image type."
+                       return 1                                     
+               }                                                    
+               return 0                                             
+               ;;                                                   
 
-platform_check_image() {
-       local tar_file="$1"
-       local board=$(board_name)
-
-       case "$board" in
-       bananapi,bpi-r2 |\
-       mediatek,mt7623a-rfb-emmc)
-               local kernel_length=`(tar xf $tar_file sysupgrade-$board/kernel -O | wc -c) 2> /dev/null`
-               local rootfs_length=`(tar xf $tar_file sysupgrade-$board/root -O | wc -c) 2> /dev/null`
-               ;;
-
-       *)
+       *)                                                           
                echo "Sysupgrade is not supported on your board yet."
-               return 1
-               ;;
-       esac
-
-       [ "$kernel_length" = 0 -o "$rootfs_length" = 0 ] && {
-               echo "The upgarde image is corrupt."
-               return 1
-       }
+               return 1                                             
+               ;;                                
+       esac                                      
 
-       return 0
-}
+       return 0                                                                                         
+}                   
diff --git a/target/linux/mediatek/config-4.14 b/target/linux/mediatek/config-4.14
deleted file mode 100644 (file)
index 02365ca..0000000
+++ /dev/null
@@ -1,490 +0,0 @@
-# CONFIG_AHCI_MTK is not set
-# CONFIG_AIO is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_CPU_SUSPEND=y
-# CONFIG_ARM_CPU_TOPOLOGY is not set
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_LPAE is not set
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_STACKPROTECTOR=y
-# CONFIG_CC_STACKPROTECTOR_NONE is not set
-CONFIG_CC_STACKPROTECTOR_REGULAR=y
-CONFIG_CLEANCACHE=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_FORCE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT2701=y
-CONFIG_COMMON_CLK_MT2701_BDPSYS=y
-CONFIG_COMMON_CLK_MT2701_ETHSYS=y
-CONFIG_COMMON_CLK_MT2701_HIFSYS=y
-CONFIG_COMMON_CLK_MT2701_IMGSYS=y
-CONFIG_COMMON_CLK_MT2701_MMSYS=y
-CONFIG_COMMON_CLK_MT2701_VDECSYS=y
-# CONFIG_COMMON_CLK_MT8135 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-CONFIG_COMPACTION=y
-CONFIG_COREDUMP=y
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-# CONFIG_CPU_THERMAL is not set
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_ACOMP2=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_CTR=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DEV_MEDIATEK=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_MT6589_UART0=y
-# CONFIG_DEBUG_MT8127_UART0 is not set
-# CONFIG_DEBUG_MT8135_UART3 is not set
-CONFIG_DEBUG_PREEMPT=y
-CONFIG_DEBUG_UART_8250=y
-# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
-CONFIG_DEBUG_UART_8250_SHIFT=2
-# CONFIG_DEBUG_UART_8250_WORD is not set
-CONFIG_DEBUG_UART_PHYS=0x11004000
-CONFIG_DEBUG_UART_VIRT=0xf1004000
-CONFIG_DEBUG_UNCOMPRESS=y
-# CONFIG_DEBUG_USER is not set
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_ELF_CORE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FREEZER=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_GRO_CELLS is not set
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_AUDITSYSCALL=y
-CONFIG_HAVE_ARCH_BITREVERSE=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARM_ARCH_TIMER=y
-CONFIG_HAVE_ARM_SMCCC=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_EBPF_JIT=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_IIO=y
-# CONFIG_IIO_BUFFER is not set
-# CONFIG_IIO_TRIGGER is not set
-CONFIG_INITRAMFS_COMPRESSION=""
-# CONFIG_INITRAMFS_FORCE is not set
-CONFIG_INITRAMFS_ROOT_GID=1000
-CONFIG_INITRAMFS_ROOT_UID=1000
-CONFIG_INITRAMFS_SOURCE="/openwrt/trunk/build_dir/target-arm_cortex-a7_musl-1.1.14_eabi/root-mediatek /openwrt/trunk/target/linux/generic/image/initramfs-base-files.txt"
-CONFIG_IOMMU_HELPER=y
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_KALLSYMS=y
-CONFIG_LEDS_MT6323=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACH_MT2701=y
-# CONFIG_MACH_MT6589 is not set
-# CONFIG_MACH_MT6592 is not set
-CONFIG_MACH_MT7623=y
-CONFIG_MACH_MT8127=y
-# CONFIG_MACH_MT8135 is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MEDIATEK_MT6577_AUXADC=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_MT6397=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_MTK=y
-CONFIG_MMC_SDHCI=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-# CONFIG_MMC_TIFM_SD is not set
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_MT81xx_NOR=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_MTK=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-# CONFIG_MTD_UBI_FASTMAP is not set
-# CONFIG_MTD_UBI_GLUEBI is not set
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTK_EFUSE=y
-CONFIG_MTK_INFRACFG=y
-# CONFIG_MTK_IOMMU is not set
-# CONFIG_MTK_IOMMU_V1 is not set
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_TIMER=y
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_SWITCHDEV=y
-# CONFIG_NET_VENDOR_AURORA is not set
-CONFIG_NET_VENDOR_MEDIATEK=y
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_NLS=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_ADDRESS_PCI=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHY_MTK_TPHY=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_MT2701=y
-CONFIG_PINCTRL_MT6397=y
-CONFIG_PINCTRL_MT8127=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_PM_OPP=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_CPU_STALL_TIMEOUT=21
-# CONFIG_RCU_EXPERT is not set
-CONFIG_RCU_NEED_SEGCBLIST=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_MT6323=y
-# CONFIG_REGULATOR_MT6380 is not set
-# CONFIG_REGULATOR_MT6397 is not set
-# CONFIG_REGULATOR_QCOM_SPMI is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_MT6397 is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_SCHED_INFO is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SERIAL_8250_DMA is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MT65XX=y
-CONFIG_SPMI=y
-CONFIG_SRCU=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWCONFIG=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TASKS_RCU=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-# CONFIG_USB_EHCI_HCD is not set
-# CONFIG_USB_MTU3 is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_MTK=y
-CONFIG_USB_XHCI_PLATFORM=y
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/mediatek/image/32.mk b/target/linux/mediatek/image/32.mk
deleted file mode 100644 (file)
index 7b7e303..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-define Image/BuilduImage
-       $(CP) $(KDIR)/zImage$(2) $(KDIR)/zImage-$(1)$(2)
-       cat $(LINUX_DIR)/arch/arm/boot/dts/$1.dtb >> $(KDIR)/zImage-$(1)$(2)
-       mkimage -A arm -O linux -T kernel -C none -a 0x80008000 -e 0x80008000 -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)'  -d $(KDIR)/zImage-$(1)$(2) $(KDIR)/uImage-$(1)$(2)
-endef
-
-define Image/Build/SysupgradeCombined
-       $(call Image/BuilduImage,$1)
-ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
-       $(call Image/BuilduImage,$1,-initramfs)
-       $(CP) $(KDIR)/uImage-$(1)-initramfs $(BIN_DIR)/$(IMG_PREFIX)-uImage-$(1)-initramfs
-endif
-       mkdir -p "$(KDIR_TMP)/sysupgrade-$(3)/"
-       echo "BOARD=$(3)" > "$(KDIR_TMP)/sysupgrade-$(3)/CONTROL"
-       $(CP) "$(KDIR)/root.$(2)" "$(KDIR_TMP)/sysupgrade-$(3)/root"
-       $(CP) "$(KDIR)/uImage-$(1)" "$(KDIR_TMP)/sysupgrade-$(3)/kernel"
-       (cd "$(KDIR_TMP)"; $(TAR) cvf \
-               "$(BIN_DIR)/$(IMG_PREFIX)-$(3)-sysupgrade.tar" sysupgrade-$(3) \
-                       $(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") \
-       )
-endef
-
-COMPAT_BPI-R2:=bananapi,bpi-r2
-COMPAT_EMMC:=mediatek,mt7623a-rfb-emmc
-
-define Image/Build/squashfs
-       $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
-       $(CP) $(KDIR)/root.squashfs $(BIN_DIR)/$(IMG_PREFIX)-root.squashfs
-
-       $(call Image/Build/SysupgradeCombined,mt7623n-bananapi-bpi-r2,squashfs,$$(COMPAT_BPI-R2))
-       $(call Image/Build/SysupgradeCombined,mt7623a-rfb-emmc,squashfs,$$(COMPAT_EMMC))
-endef
index 6721259..9e2575b 100644 (file)
@@ -1,10 +1,42 @@
+#
+# Copyright (C) 2012-2015 OpenWrt.org
+# Copyright (C) 2016-2017 LEDE project
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/image.mk
 
-include $(SUBTARGET).mk
+# for arm
+KERNEL_LOADADDR := 0x80008000
+
+# build dtb
+define Build/dtb
+        $(call Image/BuildDTB,$(DEVICE_DTS_DIR)/$(DEVICE_DTS).dts,$(DEVICE_DTS_DIR)/$(DEVICE_DTS).dtb)
+       $(CP) $(DEVICE_DTS_DIR)/$(DEVICE_DTS).dtb $(BIN_DIR)/
+endef
+
+# default all platform image(fit) build 
+define Device/Default
+  PROFILES = Default $$(DEVICE_NAME)
+  KERNEL_NAME := zImage
+  FILESYSTEMS := squashfs
+  DEVICE_DTS_DIR := $(DTS_DIR)
+  IMAGES := sysupgrade.bin
+  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata 
+  KERNEL_NAME := zImage
+  KERNEL := dtb | kernel-bin | append-dtb | uImage none
+  KERNEL_INITRAMFS := dtb | kernel-bin | append-dtb | uImage none
+endef
+
+ifeq ($(SUBTARGET),mt7623)
+include mt7623.mk
+endif
 
 define Image/Build
        $(call Image/Build/$(1),$(1))
 endef
 
 $(eval $(call BuildImage))
+
diff --git a/target/linux/mediatek/image/mt7623.mk b/target/linux/mediatek/image/mt7623.mk
new file mode 100644 (file)
index 0000000..ddb4faa
--- /dev/null
@@ -0,0 +1,6 @@
+define Device/7623n-bananapi-bpi-r2
+  DEVICE_TITLE := MTK7623n BananaPi R2
+  DEVICE_DTS := mt7623n-bananapi-bpi-r2
+endef
+
+TARGET_DEVICES += 7623n-bananapi-bpi-r2
diff --git a/target/linux/mediatek/mt7623/config-4.14 b/target/linux/mediatek/mt7623/config-4.14
new file mode 100644 (file)
index 0000000..4cdd0e7
--- /dev/null
@@ -0,0 +1,491 @@
+# CONFIG_AIO is not set
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARM=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_CPU_SUSPEND=y
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+# CONFIG_ARM_LPAE is not set
+CONFIG_ARM_MEDIATEK_CPUFREQ=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOUNCE=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CC_STACKPROTECTOR=y
+# CONFIG_CC_STACKPROTECTOR_NONE is not set
+CONFIG_CC_STACKPROTECTOR_REGULAR=y
+CONFIG_CLEANCACHE=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_MEDIATEK=y
+CONFIG_COMMON_CLK_MT2701=y
+CONFIG_COMMON_CLK_MT2701_BDPSYS=y
+CONFIG_COMMON_CLK_MT2701_ETHSYS=y
+CONFIG_COMMON_CLK_MT2701_HIFSYS=y
+CONFIG_COMMON_CLK_MT2701_IMGSYS=y
+CONFIG_COMMON_CLK_MT2701_MMSYS=y
+CONFIG_COMMON_CLK_MT2701_VDECSYS=y
+# CONFIG_COMMON_CLK_MT7622 is not set
+# CONFIG_COMMON_CLK_MT8135 is not set
+# CONFIG_COMMON_CLK_MT8173 is not set
+CONFIG_COMPACTION=y
+CONFIG_COREDUMP=y
+# CONFIG_CPUFREQ_DT is not set
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+# CONFIG_CPU_THERMAL is not set
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DEV_MEDIATEK=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
+CONFIG_DEBUG_MT6589_UART0=y
+# CONFIG_DEBUG_MT8127_UART0 is not set
+# CONFIG_DEBUG_MT8135_UART3 is not set
+CONFIG_DEBUG_PREEMPT=y
+CONFIG_DEBUG_UART_8250=y
+# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
+CONFIG_DEBUG_UART_8250_SHIFT=2
+# CONFIG_DEBUG_UART_8250_WORD is not set
+CONFIG_DEBUG_UART_PHYS=0x11004000
+CONFIG_DEBUG_UART_VIRT=0xf1004000
+CONFIG_DEBUG_UNCOMPRESS=y
+# CONFIG_DEBUG_USER is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_ELF_CORE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FREEZER=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_GRO_CELLS is not set
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_HAVE_ARM_SMCCC=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_EBPF_JIT=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SMP=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MTK=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MT65XX=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_IIO=y
+# CONFIG_IIO_BUFFER is not set
+# CONFIG_IIO_TRIGGER is not set
+CONFIG_INITRAMFS_COMPRESSION=""
+CONFIG_INITRAMFS_ROOT_GID=1000
+CONFIG_INITRAMFS_ROOT_UID=1000
+CONFIG_INITRAMFS_SOURCE="/openwrt/trunk/build_dir/target-arm_cortex-a7_musl-1.1.14_eabi/root-mediatek /openwrt/trunk/target/linux/generic/image/initramfs-base-files.txt"
+CONFIG_IOMMU_HELPER=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_KALLSYMS=y
+CONFIG_LEDS_MT6323=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+# CONFIG_MACH_MT2701 is not set
+# CONFIG_MACH_MT6589 is not set
+# CONFIG_MACH_MT6592 is not set
+CONFIG_MACH_MT7623=y
+# CONFIG_MACH_MT8127 is not set
+# CONFIG_MACH_MT8135 is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MEDIATEK_MT6577_AUXADC=y
+CONFIG_MEDIATEK_WATCHDOG=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_MT6397=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_MTK=y
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_BLOCK2MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_MT81xx_NOR=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_MTK=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTK_EFUSE=y
+# CONFIG_MTK_HSDMA is not set
+CONFIG_MTK_INFRACFG=y
+# CONFIG_MTK_IOMMU is not set
+# CONFIG_MTK_IOMMU_V1 is not set
+CONFIG_MTK_PMIC_WRAP=y
+CONFIG_MTK_SCPSYS=y
+CONFIG_MTK_THERMAL=y
+CONFIG_MTK_TIMER=y
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MT7530=y
+CONFIG_NET_DSA_TAG_MTK=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_MEDIATEK_SOC=y
+CONFIG_NET_SWITCHDEV=y
+# CONFIG_NET_VENDOR_AURORA is not set
+CONFIG_NET_VENDOR_MEDIATEK=y
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_NLS=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MT2701=y
+CONFIG_PINCTRL_MT6397=y
+CONFIG_PINCTRL_MTK=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PWM=y
+CONFIG_PWM_MEDIATEK=y
+# CONFIG_PWM_MTK_DISP is not set
+CONFIG_PWM_SYSFS=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+# CONFIG_RCU_EXPERT is not set
+CONFIG_RCU_NEED_SEGCBLIST=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MT6323=y
+# CONFIG_REGULATOR_MT6380 is not set
+# CONFIG_REGULATOR_MT6397 is not set
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_MT6397 is not set
+# CONFIG_RTC_DRV_MT7622 is not set
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+# CONFIG_SCHED_INFO is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250_DMA is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_MT6577=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SMP=y
+# CONFIG_SMP_ON_UP is not set
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MT65XX=y
+CONFIG_SPMI=y
+CONFIG_SRCU=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWCONFIG=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TASKS_RCU=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USE_OF=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/mediatek/mt7623/profiles/default.mk b/target/linux/mediatek/mt7623/profiles/default.mk
new file mode 100644 (file)
index 0000000..2ef570b
--- /dev/null
@@ -0,0 +1,15 @@
+#
+# Copyright (C) 2015 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+define Profile/Default
+       NAME:=Default Profile (minimum package set)
+endef
+
+define Profile/Default/Description
+       Default package set compatible with most boards.
+endef
+$(eval $(call Profile,Default))
diff --git a/target/linux/mediatek/mt7623/target.mk b/target/linux/mediatek/mt7623/target.mk
new file mode 100644 (file)
index 0000000..9f995f9
--- /dev/null
@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2009 OpenWrt.org
+#
+
+ARCH:=arm
+SUBTARGET:=mt7623
+BOARDNAME:=MT7623
+CPU_TYPE:=cortex-a7
+CPU_SUBTYPE:=neon-vfpv4
+
+KERNELNAME:=Image dtbs zImage
+
+define Target/Description
+       Build firmware images for MediaTek mt7623 ARM based boards.
+endef
+
diff --git a/target/linux/mediatek/patches-4.14/0101-reset-mediatek-add-reset-controller-dt-bindings-requ.patch b/target/linux/mediatek/patches-4.14/0101-reset-mediatek-add-reset-controller-dt-bindings-requ.patch
new file mode 100644 (file)
index 0000000..64f3107
--- /dev/null
@@ -0,0 +1,120 @@
+From 5d6a82632eb7258c8ca49cc96c18b8b4071b6639 Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Wed, 20 Sep 2017 17:40:16 +0800
+Subject: [PATCH 101/224] reset: mediatek: add reset controller dt-bindings
+ required header for MT7622 SoC
+
+Add the reset controller dt-bindings exported from infracfg, pericfg,
+hifsys and ethsys which could be found on MT7622 SoC. So that we can
+reference them from within a device-tree file.
+
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
+---
+ include/dt-bindings/reset/mt7622-reset.h | 94 ++++++++++++++++++++++++++++++++
+ 1 file changed, 94 insertions(+)
+ create mode 100644 include/dt-bindings/reset/mt7622-reset.h
+
+diff --git a/include/dt-bindings/reset/mt7622-reset.h b/include/dt-bindings/reset/mt7622-reset.h
+new file mode 100644
+index 000000000000..234052f80417
+--- /dev/null
++++ b/include/dt-bindings/reset/mt7622-reset.h
+@@ -0,0 +1,94 @@
++/*
++ * Copyright (c) 2017 MediaTek Inc.
++ * Author: Sean Wang <sean.wang@mediatek.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622
++#define _DT_BINDINGS_RESET_CONTROLLER_MT7622
++
++/* INFRACFG resets */
++#define MT7622_INFRA_EMI_REG_RST              0
++#define MT7622_INFRA_DRAMC0_A0_RST            1
++#define MT7622_INFRA_APCIRQ_EINT_RST          3
++#define MT7622_INFRA_APXGPT_RST                       4
++#define MT7622_INFRA_SCPSYS_RST                       5
++#define MT7622_INFRA_PMIC_WRAP_RST            7
++#define MT7622_INFRA_IRRX_RST                 9
++#define MT7622_INFRA_EMI_RST                  16
++#define MT7622_INFRA_WED0_RST                 17
++#define MT7622_INFRA_DRAMC_RST                        18
++#define MT7622_INFRA_CCI_INTF_RST             19
++#define MT7622_INFRA_TRNG_RST                 21
++#define MT7622_INFRA_SYSIRQ_RST                       22
++#define MT7622_INFRA_WED1_RST                 25
++
++/* PERICFG Subsystem resets */
++#define MT7622_PERI_UART0_SW_RST              0
++#define MT7622_PERI_UART1_SW_RST              1
++#define MT7622_PERI_UART2_SW_RST              2
++#define MT7622_PERI_UART3_SW_RST              3
++#define MT7622_PERI_UART4_SW_RST              4
++#define MT7622_PERI_BTIF_SW_RST                       6
++#define MT7622_PERI_PWM_SW_RST                        8
++#define MT7622_PERI_AUXADC_SW_RST             10
++#define MT7622_PERI_DMA_SW_RST                        11
++#define MT7622_PERI_IRTX_SW_RST                       13
++#define MT7622_PERI_NFI_SW_RST                        14
++#define MT7622_PERI_THERM_SW_RST              16
++#define MT7622_PERI_MSDC0_SW_RST              19
++#define MT7622_PERI_MSDC1_SW_RST              20
++#define MT7622_PERI_I2C0_SW_RST                       22
++#define MT7622_PERI_I2C1_SW_RST                       23
++#define MT7622_PERI_I2C2_SW_RST                       24
++#define MT7622_PERI_SPI0_SW_RST                       33
++#define MT7622_PERI_SPI1_SW_RST                       34
++#define MT7622_PERI_FLASHIF_SW_RST            36
++
++/* TOPRGU resets */
++#define MT7622_TOPRGU_INFRA_RST                       0
++#define MT7622_TOPRGU_ETHDMA_RST              1
++#define MT7622_TOPRGU_DDRPHY_RST              6
++#define MT7622_TOPRGU_INFRA_AO_RST            8
++#define MT7622_TOPRGU_CONN_RST                        9
++#define MT7622_TOPRGU_APMIXED_RST             10
++#define MT7622_TOPRGU_CONN_MCU_RST            12
++
++/* PCIe/SATA Subsystem resets */
++#define MT7622_SATA_PHY_REG_RST                       12
++#define MT7622_SATA_PHY_SW_RST                        13
++#define MT7622_SATA_AXI_BUS_RST                       15
++#define MT7622_PCIE1_CORE_RST                 19
++#define MT7622_PCIE1_MMIO_RST                 20
++#define MT7622_PCIE1_HRST                     21
++#define MT7622_PCIE1_USER_RST                 22
++#define MT7622_PCIE1_PIPE_RST                 23
++#define MT7622_PCIE0_CORE_RST                 27
++#define MT7622_PCIE0_MMIO_RST                 28
++#define MT7622_PCIE0_HRST                     29
++#define MT7622_PCIE0_USER_RST                 30
++#define MT7622_PCIE0_PIPE_RST                 31
++
++/* SSUSB Subsystem resets */
++#define MT7622_SSUSB_PHY_PWR_RST              3
++#define MT7622_SSUSB_MAC_PWR_RST              4
++
++/* ETHSYS Subsystem resets */
++#define MT7622_ETHSYS_SYS_RST                 0
++#define MT7622_ETHSYS_MCM_RST                 2
++#define MT7622_ETHSYS_HSDMA_RST                       5
++#define MT7622_ETHSYS_FE_RST                  6
++#define MT7622_ETHSYS_GMAC_RST                        23
++#define MT7622_ETHSYS_EPHY_RST                        24
++#define MT7622_ETHSYS_CRYPTO_RST              29
++#define MT7622_ETHSYS_PPE_RST                 31
++
++#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0102-soc-mediatek-pwrap-fixup-warnings-from-coding-style.patch b/target/linux/mediatek/patches-4.14/0102-soc-mediatek-pwrap-fixup-warnings-from-coding-style.patch
new file mode 100644 (file)
index 0000000..408de3a
--- /dev/null
@@ -0,0 +1,76 @@
+From c7cb4b7e750fc9a23cd80ef34ad4ef8a47f895d5 Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Thu, 21 Sep 2017 16:26:57 +0800
+Subject: [PATCH 102/224] soc: mediatek: pwrap: fixup warnings from coding
+ style
+
+fixup those warnings such as lines over 80 words and parenthesis
+alignment which would be complained by checkpatch.pl.
+
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ drivers/soc/mediatek/mtk-pmic-wrap.c | 20 +++++++++++++-------
+ 1 file changed, 13 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index c2048382830f..f095faac1e04 100644
+--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
++++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
+@@ -827,7 +827,8 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
+       /* wait for cipher data ready@PMIC */
+       ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
+       if (ret) {
+-              dev_err(wrp->dev, "timeout waiting for cipher data ready@PMIC\n");
++              dev_err(wrp->dev,
++                      "timeout waiting for cipher data ready@PMIC\n");
+               return ret;
+       }
+@@ -1159,23 +1160,27 @@ static int pwrap_probe(struct platform_device *pdev)
+               if (IS_ERR(wrp->bridge_base))
+                       return PTR_ERR(wrp->bridge_base);
+-              wrp->rstc_bridge = devm_reset_control_get(wrp->dev, "pwrap-bridge");
++              wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
++                                                        "pwrap-bridge");
+               if (IS_ERR(wrp->rstc_bridge)) {
+                       ret = PTR_ERR(wrp->rstc_bridge);
+-                      dev_dbg(wrp->dev, "cannot get pwrap-bridge reset: %d\n", ret);
++                      dev_dbg(wrp->dev,
++                              "cannot get pwrap-bridge reset: %d\n", ret);
+                       return ret;
+               }
+       }
+       wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
+       if (IS_ERR(wrp->clk_spi)) {
+-              dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_spi));
++              dev_dbg(wrp->dev, "failed to get clock: %ld\n",
++                      PTR_ERR(wrp->clk_spi));
+               return PTR_ERR(wrp->clk_spi);
+       }
+       wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
+       if (IS_ERR(wrp->clk_wrap)) {
+-              dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_wrap));
++              dev_dbg(wrp->dev, "failed to get clock: %ld\n",
++                      PTR_ERR(wrp->clk_wrap));
+               return PTR_ERR(wrp->clk_wrap);
+       }
+@@ -1220,8 +1225,9 @@ static int pwrap_probe(struct platform_device *pdev)
+       pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
+       irq = platform_get_irq(pdev, 0);
+-      ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, IRQF_TRIGGER_HIGH,
+-                      "mt-pmic-pwrap", wrp);
++      ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
++                             IRQF_TRIGGER_HIGH,
++                             "mt-pmic-pwrap", wrp);
+       if (ret)
+               goto err_out2;
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0104-usb-mtu3-support-option-to-disable-usb3-ports.patch b/target/linux/mediatek/patches-4.14/0104-usb-mtu3-support-option-to-disable-usb3-ports.patch
new file mode 100644 (file)
index 0000000..51b5bcf
--- /dev/null
@@ -0,0 +1,117 @@
+From 7a46c3488c48a0fbe313ed25c12af3fb3af48a01 Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 17:10:38 +0800
+Subject: [PATCH 104/224] usb: mtu3: support option to disable usb3 ports
+
+Add support to disable specific usb3 ports, it's useful when
+usb3 phy is shared with PCIe or SATA, because we should disable
+the corresponding usb3 port if the phy is used by PCIe or SATA.
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+---
+ drivers/usb/mtu3/mtu3.h      |  3 +++
+ drivers/usb/mtu3/mtu3_host.c | 16 +++++++++++++---
+ drivers/usb/mtu3/mtu3_plat.c |  8 ++++++--
+ 3 files changed, 22 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/usb/mtu3/mtu3.h b/drivers/usb/mtu3/mtu3.h
+index b26fffc58446..112723d6e7bc 100644
+--- a/drivers/usb/mtu3/mtu3.h
++++ b/drivers/usb/mtu3/mtu3.h
+@@ -210,6 +210,8 @@ struct otg_switch_mtk {
+  *            host only, device only or dual-role mode
+  * @u2_ports: number of usb2.0 host ports
+  * @u3_ports: number of usb3.0 host ports
++ * @u3p_dis_msk: mask of disabling usb3 ports, for example, bit0==1 to
++ *            disable u3port0, bit1==1 to disable u3port1,... etc
+  * @dbgfs_root: only used when supports manual dual-role switch via debugfs
+  * @wakeup_en: it's true when supports remote wakeup in host mode
+  * @wk_deb_p0: port0's wakeup debounce clock
+@@ -232,6 +234,7 @@ struct ssusb_mtk {
+       bool is_host;
+       int u2_ports;
+       int u3_ports;
++      int u3p_dis_msk;
+       struct dentry *dbgfs_root;
+       /* usb wakeup for host mode */
+       bool wakeup_en;
+diff --git a/drivers/usb/mtu3/mtu3_host.c b/drivers/usb/mtu3/mtu3_host.c
+index e42d308b8dc2..4dd9508a60b5 100644
+--- a/drivers/usb/mtu3/mtu3_host.c
++++ b/drivers/usb/mtu3/mtu3_host.c
+@@ -151,6 +151,7 @@ int ssusb_host_enable(struct ssusb_mtk *ssusb)
+       void __iomem *ibase = ssusb->ippc_base;
+       int num_u3p = ssusb->u3_ports;
+       int num_u2p = ssusb->u2_ports;
++      int u3_ports_disabed;
+       u32 check_clk;
+       u32 value;
+       int i;
+@@ -158,8 +159,14 @@ int ssusb_host_enable(struct ssusb_mtk *ssusb)
+       /* power on host ip */
+       mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
+-      /* power on and enable all u3 ports */
++      /* power on and enable u3 ports except skipped ones */
++      u3_ports_disabed = 0;
+       for (i = 0; i < num_u3p; i++) {
++              if ((0x1 << i) & ssusb->u3p_dis_msk) {
++                      u3_ports_disabed++;
++                      continue;
++              }
++
+               value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
+               value &= ~(SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS);
+               value |= SSUSB_U3_PORT_HOST_SEL;
+@@ -175,7 +182,7 @@ int ssusb_host_enable(struct ssusb_mtk *ssusb)
+       }
+       check_clk = SSUSB_XHCI_RST_B_STS;
+-      if (num_u3p)
++      if (num_u3p > u3_ports_disabed)
+               check_clk = SSUSB_U3_MAC_RST_B_STS;
+       return ssusb_check_clocks(ssusb, check_clk);
+@@ -190,8 +197,11 @@ int ssusb_host_disable(struct ssusb_mtk *ssusb, bool suspend)
+       int ret;
+       int i;
+-      /* power down and disable all u3 ports */
++      /* power down and disable u3 ports except skipped ones */
+       for (i = 0; i < num_u3p; i++) {
++              if ((0x1 << i) & ssusb->u3p_dis_msk)
++                      continue;
++
+               value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
+               value |= SSUSB_U3_PORT_PDN;
+               value |= suspend ? 0 : SSUSB_U3_PORT_DIS;
+diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c
+index 088e3e685c4f..9edad30c8ae5 100644
+--- a/drivers/usb/mtu3/mtu3_plat.c
++++ b/drivers/usb/mtu3/mtu3_plat.c
+@@ -276,6 +276,10 @@ static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
+       if (ret)
+               return ret;
++      /* optional property, ignore the error if it does not exist */
++      of_property_read_u32(node, "mediatek,u3p-dis-msk",
++                           &ssusb->u3p_dis_msk);
++
+       if (ssusb->dr_mode != USB_DR_MODE_OTG)
+               return 0;
+@@ -304,8 +308,8 @@ static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
+               }
+       }
+-      dev_info(dev, "dr_mode: %d, is_u3_dr: %d\n",
+-              ssusb->dr_mode, otg_sx->is_u3_drd);
++      dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk:%x\n",
++              ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk);
+       return 0;
+ }
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0105-usb-mtu3-remove-dummy-wakeup-debounce-clocks.patch b/target/linux/mediatek/patches-4.14/0105-usb-mtu3-remove-dummy-wakeup-debounce-clocks.patch
new file mode 100644 (file)
index 0000000..adf1cec
--- /dev/null
@@ -0,0 +1,126 @@
+From 50005796f146351dc9c34bbf8898b305c562e964 Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 17:10:39 +0800
+Subject: [PATCH 105/224] usb: mtu3: remove dummy wakeup debounce clocks
+
+The wakeup debounce clocks for each ports in fact are not
+needed, so remove them.
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+---
+ drivers/usb/mtu3/mtu3.h      |  4 ----
+ drivers/usb/mtu3/mtu3_host.c | 57 ++++----------------------------------------
+ 2 files changed, 4 insertions(+), 57 deletions(-)
+
+diff --git a/drivers/usb/mtu3/mtu3.h b/drivers/usb/mtu3/mtu3.h
+index 112723d6e7bc..6d3278e46431 100644
+--- a/drivers/usb/mtu3/mtu3.h
++++ b/drivers/usb/mtu3/mtu3.h
+@@ -214,8 +214,6 @@ struct otg_switch_mtk {
+  *            disable u3port0, bit1==1 to disable u3port1,... etc
+  * @dbgfs_root: only used when supports manual dual-role switch via debugfs
+  * @wakeup_en: it's true when supports remote wakeup in host mode
+- * @wk_deb_p0: port0's wakeup debounce clock
+- * @wk_deb_p1: it's optional, and depends on port1 is supported or not
+  */
+ struct ssusb_mtk {
+       struct device *dev;
+@@ -238,8 +236,6 @@ struct ssusb_mtk {
+       struct dentry *dbgfs_root;
+       /* usb wakeup for host mode */
+       bool wakeup_en;
+-      struct clk *wk_deb_p0;
+-      struct clk *wk_deb_p1;
+       struct regmap *pericfg;
+ };
+diff --git a/drivers/usb/mtu3/mtu3_host.c b/drivers/usb/mtu3/mtu3_host.c
+index 4dd9508a60b5..edcc59148171 100644
+--- a/drivers/usb/mtu3/mtu3_host.c
++++ b/drivers/usb/mtu3/mtu3_host.c
+@@ -79,20 +79,6 @@ int ssusb_wakeup_of_property_parse(struct ssusb_mtk *ssusb,
+       if (!ssusb->wakeup_en)
+               return 0;
+-      ssusb->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0");
+-      if (IS_ERR(ssusb->wk_deb_p0)) {
+-              dev_err(dev, "fail to get wakeup_deb_p0\n");
+-              return PTR_ERR(ssusb->wk_deb_p0);
+-      }
+-
+-      if (of_property_read_bool(dn, "wakeup_deb_p1")) {
+-              ssusb->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1");
+-              if (IS_ERR(ssusb->wk_deb_p1)) {
+-                      dev_err(dev, "fail to get wakeup_deb_p1\n");
+-                      return PTR_ERR(ssusb->wk_deb_p1);
+-              }
+-      }
+-
+       ssusb->pericfg = syscon_regmap_lookup_by_phandle(dn,
+                                               "mediatek,syscon-wakeup");
+       if (IS_ERR(ssusb->pericfg)) {
+@@ -103,36 +89,6 @@ int ssusb_wakeup_of_property_parse(struct ssusb_mtk *ssusb,
+       return 0;
+ }
+-static int ssusb_wakeup_clks_enable(struct ssusb_mtk *ssusb)
+-{
+-      int ret;
+-
+-      ret = clk_prepare_enable(ssusb->wk_deb_p0);
+-      if (ret) {
+-              dev_err(ssusb->dev, "failed to enable wk_deb_p0\n");
+-              goto usb_p0_err;
+-      }
+-
+-      ret = clk_prepare_enable(ssusb->wk_deb_p1);
+-      if (ret) {
+-              dev_err(ssusb->dev, "failed to enable wk_deb_p1\n");
+-              goto usb_p1_err;
+-      }
+-
+-      return 0;
+-
+-usb_p1_err:
+-      clk_disable_unprepare(ssusb->wk_deb_p0);
+-usb_p0_err:
+-      return -EINVAL;
+-}
+-
+-static void ssusb_wakeup_clks_disable(struct ssusb_mtk *ssusb)
+-{
+-      clk_disable_unprepare(ssusb->wk_deb_p1);
+-      clk_disable_unprepare(ssusb->wk_deb_p0);
+-}
+-
+ static void host_ports_num_get(struct ssusb_mtk *ssusb)
+ {
+       u32 xhci_cap;
+@@ -286,19 +242,14 @@ void ssusb_host_exit(struct ssusb_mtk *ssusb)
+ int ssusb_wakeup_enable(struct ssusb_mtk *ssusb)
+ {
+-      int ret = 0;
+-
+-      if (ssusb->wakeup_en) {
+-              ret = ssusb_wakeup_clks_enable(ssusb);
++      if (ssusb->wakeup_en)
+               ssusb_wakeup_ip_sleep_en(ssusb);
+-      }
+-      return ret;
++
++      return 0;
+ }
+ void ssusb_wakeup_disable(struct ssusb_mtk *ssusb)
+ {
+-      if (ssusb->wakeup_en) {
++      if (ssusb->wakeup_en)
+               ssusb_wakeup_ip_sleep_dis(ssusb);
+-              ssusb_wakeup_clks_disable(ssusb);
+-      }
+ }
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0106-usb-mtu3-add-optional-mcu-and-dma-bus-clocks.patch b/target/linux/mediatek/patches-4.14/0106-usb-mtu3-add-optional-mcu-and-dma-bus-clocks.patch
new file mode 100644 (file)
index 0000000..93a8c65
--- /dev/null
@@ -0,0 +1,233 @@
+From 677805f6d83524717b46b3cde74aa455dbf6299f Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 17:10:40 +0800
+Subject: [PATCH 106/224] usb: mtu3: add optional mcu and dma bus clocks
+
+There are mcu_bus and dma_bus clocks needed to be turned on/off by
+driver on some SoCs, so add them as optional ones
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+---
+ drivers/usb/mtu3/mtu3.h      |   5 ++
+ drivers/usb/mtu3/mtu3_plat.c | 121 +++++++++++++++++++++++++++++--------------
+ 2 files changed, 86 insertions(+), 40 deletions(-)
+
+diff --git a/drivers/usb/mtu3/mtu3.h b/drivers/usb/mtu3/mtu3.h
+index 6d3278e46431..2795294ec92a 100644
+--- a/drivers/usb/mtu3/mtu3.h
++++ b/drivers/usb/mtu3/mtu3.h
+@@ -206,6 +206,9 @@ struct otg_switch_mtk {
+  * @ippc_base: register base address of IP Power and Clock interface (IPPC)
+  * @vusb33: usb3.3V shared by device/host IP
+  * @sys_clk: system clock of mtu3, shared by device/host IP
++ * @ref_clk: reference clock
++ * @mcu_clk: mcu_bus_ck clock for AHB bus etc
++ * @dma_clk: dma_bus_ck clock for AXI bus etc
+  * @dr_mode: works in which mode:
+  *            host only, device only or dual-role mode
+  * @u2_ports: number of usb2.0 host ports
+@@ -226,6 +229,8 @@ struct ssusb_mtk {
+       struct regulator *vusb33;
+       struct clk *sys_clk;
+       struct clk *ref_clk;
++      struct clk *mcu_clk;
++      struct clk *dma_clk;
+       /* otg */
+       struct otg_switch_mtk otg_switch;
+       enum usb_dr_mode dr_mode;
+diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c
+index 9edad30c8ae5..fb8992011bde 100644
+--- a/drivers/usb/mtu3/mtu3_plat.c
++++ b/drivers/usb/mtu3/mtu3_plat.c
+@@ -110,15 +110,9 @@ static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
+               phy_power_off(ssusb->phys[i]);
+ }
+-static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
++static int ssusb_clks_enable(struct ssusb_mtk *ssusb)
+ {
+-      int ret = 0;
+-
+-      ret = regulator_enable(ssusb->vusb33);
+-      if (ret) {
+-              dev_err(ssusb->dev, "failed to enable vusb33\n");
+-              goto vusb33_err;
+-      }
++      int ret;
+       ret = clk_prepare_enable(ssusb->sys_clk);
+       if (ret) {
+@@ -132,6 +126,52 @@ static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
+               goto ref_clk_err;
+       }
++      ret = clk_prepare_enable(ssusb->mcu_clk);
++      if (ret) {
++              dev_err(ssusb->dev, "failed to enable mcu_clk\n");
++              goto mcu_clk_err;
++      }
++
++      ret = clk_prepare_enable(ssusb->dma_clk);
++      if (ret) {
++              dev_err(ssusb->dev, "failed to enable dma_clk\n");
++              goto dma_clk_err;
++      }
++
++      return 0;
++
++dma_clk_err:
++      clk_disable_unprepare(ssusb->mcu_clk);
++mcu_clk_err:
++      clk_disable_unprepare(ssusb->ref_clk);
++ref_clk_err:
++      clk_disable_unprepare(ssusb->sys_clk);
++sys_clk_err:
++      return ret;
++}
++
++static void ssusb_clks_disable(struct ssusb_mtk *ssusb)
++{
++      clk_disable_unprepare(ssusb->dma_clk);
++      clk_disable_unprepare(ssusb->mcu_clk);
++      clk_disable_unprepare(ssusb->ref_clk);
++      clk_disable_unprepare(ssusb->sys_clk);
++}
++
++static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
++{
++      int ret = 0;
++
++      ret = regulator_enable(ssusb->vusb33);
++      if (ret) {
++              dev_err(ssusb->dev, "failed to enable vusb33\n");
++              goto vusb33_err;
++      }
++
++      ret = ssusb_clks_enable(ssusb);
++      if (ret)
++              goto clks_err;
++
+       ret = ssusb_phy_init(ssusb);
+       if (ret) {
+               dev_err(ssusb->dev, "failed to init phy\n");
+@@ -149,20 +189,16 @@ static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
+ phy_err:
+       ssusb_phy_exit(ssusb);
+ phy_init_err:
+-      clk_disable_unprepare(ssusb->ref_clk);
+-ref_clk_err:
+-      clk_disable_unprepare(ssusb->sys_clk);
+-sys_clk_err:
++      ssusb_clks_disable(ssusb);
++clks_err:
+       regulator_disable(ssusb->vusb33);
+ vusb33_err:
+-
+       return ret;
+ }
+ static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
+ {
+-      clk_disable_unprepare(ssusb->sys_clk);
+-      clk_disable_unprepare(ssusb->ref_clk);
++      ssusb_clks_disable(ssusb);
+       regulator_disable(ssusb->vusb33);
+       ssusb_phy_power_off(ssusb);
+       ssusb_phy_exit(ssusb);
+@@ -203,6 +239,19 @@ static int get_iddig_pinctrl(struct ssusb_mtk *ssusb)
+       return 0;
+ }
++/* ignore the error if the clock does not exist */
++static struct clk *get_optional_clk(struct device *dev, const char *id)
++{
++      struct clk *opt_clk;
++
++      opt_clk = devm_clk_get(dev, id);
++      /* ignore error number except EPROBE_DEFER */
++      if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER))
++              opt_clk = NULL;
++
++      return opt_clk;
++}
++
+ static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
+ {
+       struct device_node *node = pdev->dev.of_node;
+@@ -225,18 +274,17 @@ static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
+               return PTR_ERR(ssusb->sys_clk);
+       }
+-      /*
+-       * reference clock is usually a "fixed-clock", make it optional
+-       * for backward compatibility and ignore the error if it does
+-       * not exist.
+-       */
+-      ssusb->ref_clk = devm_clk_get(dev, "ref_ck");
+-      if (IS_ERR(ssusb->ref_clk)) {
+-              if (PTR_ERR(ssusb->ref_clk) == -EPROBE_DEFER)
+-                      return -EPROBE_DEFER;
++      ssusb->ref_clk = get_optional_clk(dev, "ref_ck");
++      if (IS_ERR(ssusb->ref_clk))
++              return PTR_ERR(ssusb->ref_clk);
+-              ssusb->ref_clk = NULL;
+-      }
++      ssusb->mcu_clk = get_optional_clk(dev, "mcu_ck");
++      if (IS_ERR(ssusb->mcu_clk))
++              return PTR_ERR(ssusb->mcu_clk);
++
++      ssusb->dma_clk = get_optional_clk(dev, "dma_ck");
++      if (IS_ERR(ssusb->dma_clk))
++              return PTR_ERR(ssusb->dma_clk);
+       ssusb->num_phys = of_count_phandle_with_args(node,
+                       "phys", "#phy-cells");
+@@ -451,8 +499,7 @@ static int __maybe_unused mtu3_suspend(struct device *dev)
+       ssusb_host_disable(ssusb, true);
+       ssusb_phy_power_off(ssusb);
+-      clk_disable_unprepare(ssusb->sys_clk);
+-      clk_disable_unprepare(ssusb->ref_clk);
++      ssusb_clks_disable(ssusb);
+       ssusb_wakeup_enable(ssusb);
+       return 0;
+@@ -470,27 +517,21 @@ static int __maybe_unused mtu3_resume(struct device *dev)
+               return 0;
+       ssusb_wakeup_disable(ssusb);
+-      ret = clk_prepare_enable(ssusb->sys_clk);
+-      if (ret)
+-              goto err_sys_clk;
+-
+-      ret = clk_prepare_enable(ssusb->ref_clk);
++      ret = ssusb_clks_enable(ssusb);
+       if (ret)
+-              goto err_ref_clk;
++              goto clks_err;
+       ret = ssusb_phy_power_on(ssusb);
+       if (ret)
+-              goto err_power_on;
++              goto phy_err;
+       ssusb_host_enable(ssusb);
+       return 0;
+-err_power_on:
+-      clk_disable_unprepare(ssusb->ref_clk);
+-err_ref_clk:
+-      clk_disable_unprepare(ssusb->sys_clk);
+-err_sys_clk:
++phy_err:
++      ssusb_clks_disable(ssusb);
++clks_err:
+       return ret;
+ }
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0107-usb-mtu3-support-36-bit-DMA-address.patch b/target/linux/mediatek/patches-4.14/0107-usb-mtu3-support-36-bit-DMA-address.patch
new file mode 100644 (file)
index 0000000..652116d
--- /dev/null
@@ -0,0 +1,373 @@
+From d366bf086a61b7a895d8819a3c1349b9c6b8e40f Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 17:10:41 +0800
+Subject: [PATCH 107/224] usb: mtu3: support 36-bit DMA address
+
+add support for 36-bit DMA address
+
+[ Felipe Balbi: fix printk format for dma_addr_t ]
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+---
+ drivers/usb/mtu3/mtu3.h         |  17 ++++++-
+ drivers/usb/mtu3/mtu3_core.c    |  34 +++++++++++++-
+ drivers/usb/mtu3/mtu3_hw_regs.h |  10 ++++
+ drivers/usb/mtu3/mtu3_qmu.c     | 102 +++++++++++++++++++++++++++++++++-------
+ 4 files changed, 142 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/usb/mtu3/mtu3.h b/drivers/usb/mtu3/mtu3.h
+index 2795294ec92a..ef2dc92a2109 100644
+--- a/drivers/usb/mtu3/mtu3.h
++++ b/drivers/usb/mtu3/mtu3.h
+@@ -46,6 +46,9 @@ struct mtu3_request;
+ #define       MU3D_EP_RXCR1(epnum)    (U3D_RX1CSR1 + (((epnum) - 1) * 0x10))
+ #define       MU3D_EP_RXCR2(epnum)    (U3D_RX1CSR2 + (((epnum) - 1) * 0x10))
++#define USB_QMU_TQHIAR(epnum) (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4))
++#define USB_QMU_RQHIAR(epnum) (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4))
++
+ #define USB_QMU_RQCSR(epnum)  (U3D_RXQCSR1 + (((epnum) - 1) * 0x10))
+ #define USB_QMU_RQSAR(epnum)  (U3D_RXQSAR1 + (((epnum) - 1) * 0x10))
+ #define USB_QMU_RQCPR(epnum)  (U3D_RXQCPR1 + (((epnum) - 1) * 0x10))
+@@ -138,23 +141,33 @@ struct mtu3_fifo_info {
+  *    Checksum value is calculated over the 16 bytes of the GPD by default;
+  * @data_buf_len (RX ONLY): This value indicates the length of
+  *    the assigned data buffer
++ * @tx_ext_addr (TX ONLY): [3:0] are 4 extension bits of @buffer,
++ *    [7:4] are 4 extension bits of @next_gpd
+  * @next_gpd: Physical address of the next GPD
+  * @buffer: Physical address of the data buffer
+  * @buf_len:
+  *    (TX): This value indicates the length of the assigned data buffer
+  *    (RX): The total length of data received
+  * @ext_len: reserved
++ * @rx_ext_addr(RX ONLY): [3:0] are 4 extension bits of @buffer,
++ *    [7:4] are 4 extension bits of @next_gpd
+  * @ext_flag:
+  *    bit5 (TX ONLY): Zero Length Packet (ZLP),
+  */
+ struct qmu_gpd {
+       __u8 flag;
+       __u8 chksum;
+-      __le16 data_buf_len;
++      union {
++              __le16 data_buf_len;
++              __le16 tx_ext_addr;
++      };
+       __le32 next_gpd;
+       __le32 buffer;
+       __le16 buf_len;
+-      __u8 ext_len;
++      union {
++              __u8 ext_len;
++              __u8 rx_ext_addr;
++      };
+       __u8 ext_flag;
+ } __packed;
+diff --git a/drivers/usb/mtu3/mtu3_core.c b/drivers/usb/mtu3/mtu3_core.c
+index 947579842ad7..cd4528f5f337 100644
+--- a/drivers/usb/mtu3/mtu3_core.c
++++ b/drivers/usb/mtu3/mtu3_core.c
+@@ -17,6 +17,7 @@
+  *
+  */
++#include <linux/dma-mapping.h>
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/of_address.h>
+@@ -759,7 +760,31 @@ static void mtu3_hw_exit(struct mtu3 *mtu)
+       mtu3_mem_free(mtu);
+ }
+-/*-------------------------------------------------------------------------*/
++/**
++ * we set 32-bit DMA mask by default, here check whether the controller
++ * supports 36-bit DMA or not, if it does, set 36-bit DMA mask.
++ */
++static int mtu3_set_dma_mask(struct mtu3 *mtu)
++{
++      struct device *dev = mtu->dev;
++      bool is_36bit = false;
++      int ret = 0;
++      u32 value;
++
++      value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL);
++      if (value & DMA_ADDR_36BIT) {
++              is_36bit = true;
++              ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
++              /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */
++              if (ret) {
++                      is_36bit = false;
++                      ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
++              }
++      }
++      dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32");
++
++      return ret;
++}
+ int ssusb_gadget_init(struct ssusb_mtk *ssusb)
+ {
+@@ -820,6 +845,12 @@ int ssusb_gadget_init(struct ssusb_mtk *ssusb)
+               return ret;
+       }
++      ret = mtu3_set_dma_mask(mtu);
++      if (ret) {
++              dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret);
++              goto dma_mask_err;
++      }
++
+       ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu);
+       if (ret) {
+               dev_err(dev, "request irq %d failed!\n", mtu->irq);
+@@ -845,6 +876,7 @@ int ssusb_gadget_init(struct ssusb_mtk *ssusb)
+ gadget_err:
+       device_init_wakeup(dev, false);
++dma_mask_err:
+ irq_err:
+       mtu3_hw_exit(mtu);
+       ssusb->u3d = NULL;
+diff --git a/drivers/usb/mtu3/mtu3_hw_regs.h b/drivers/usb/mtu3/mtu3_hw_regs.h
+index 06b29664470f..b6059752dc12 100644
+--- a/drivers/usb/mtu3/mtu3_hw_regs.h
++++ b/drivers/usb/mtu3/mtu3_hw_regs.h
+@@ -58,6 +58,8 @@
+ #define U3D_QCR1              (SSUSB_DEV_BASE + 0x0404)
+ #define U3D_QCR2              (SSUSB_DEV_BASE + 0x0408)
+ #define U3D_QCR3              (SSUSB_DEV_BASE + 0x040C)
++#define U3D_TXQHIAR1          (SSUSB_DEV_BASE + 0x0484)
++#define U3D_RXQHIAR1          (SSUSB_DEV_BASE + 0x04C4)
+ #define U3D_TXQCSR1           (SSUSB_DEV_BASE + 0x0510)
+ #define U3D_TXQSAR1           (SSUSB_DEV_BASE + 0x0514)
+@@ -189,6 +191,13 @@
+ #define QMU_RX_COZ(x)         (BIT(16) << (x))
+ #define QMU_RX_ZLP(x)         (BIT(0) << (x))
++/* U3D_TXQHIAR1 */
++/* U3D_RXQHIAR1 */
++#define QMU_LAST_DONE_PTR_HI(x)       (((x) >> 16) & 0xf)
++#define QMU_CUR_GPD_ADDR_HI(x)        (((x) >> 8) & 0xf)
++#define QMU_START_ADDR_HI_MSK GENMASK(3, 0)
++#define QMU_START_ADDR_HI(x)  (((x) & 0xf) << 0)
++
+ /* U3D_TXQCSR1 */
+ /* U3D_RXQCSR1 */
+ #define QMU_Q_ACTIVE          BIT(15)
+@@ -225,6 +234,7 @@
+ #define CAP_TX_EP_NUM(x)      ((x) & 0x1f)
+ /* U3D_MISC_CTRL */
++#define DMA_ADDR_36BIT                BIT(31)
+ #define VBUS_ON                       BIT(1)
+ #define VBUS_FRC_EN           BIT(0)
+diff --git a/drivers/usb/mtu3/mtu3_qmu.c b/drivers/usb/mtu3/mtu3_qmu.c
+index 7d9ba8a52368..42145a3f1422 100644
+--- a/drivers/usb/mtu3/mtu3_qmu.c
++++ b/drivers/usb/mtu3/mtu3_qmu.c
+@@ -40,7 +40,58 @@
+ #define GPD_FLAGS_IOC BIT(7)
+ #define GPD_EXT_FLAG_ZLP      BIT(5)
++#define GPD_EXT_NGP(x)                (((x) & 0xf) << 4)
++#define GPD_EXT_BUF(x)                (((x) & 0xf) << 0)
++#define HILO_GEN64(hi, lo) (((u64)(hi) << 32) + (lo))
++#define HILO_DMA(hi, lo)      \
++      ((dma_addr_t)HILO_GEN64((le32_to_cpu(hi)), (le32_to_cpu(lo))))
++
++static dma_addr_t read_txq_cur_addr(void __iomem *mbase, u8 epnum)
++{
++      u32 txcpr;
++      u32 txhiar;
++
++      txcpr = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
++      txhiar = mtu3_readl(mbase, USB_QMU_TQHIAR(epnum));
++
++      return HILO_DMA(QMU_CUR_GPD_ADDR_HI(txhiar), txcpr);
++}
++
++static dma_addr_t read_rxq_cur_addr(void __iomem *mbase, u8 epnum)
++{
++      u32 rxcpr;
++      u32 rxhiar;
++
++      rxcpr = mtu3_readl(mbase, USB_QMU_RQCPR(epnum));
++      rxhiar = mtu3_readl(mbase, USB_QMU_RQHIAR(epnum));
++
++      return HILO_DMA(QMU_CUR_GPD_ADDR_HI(rxhiar), rxcpr);
++}
++
++static void write_txq_start_addr(void __iomem *mbase, u8 epnum, dma_addr_t dma)
++{
++      u32 tqhiar;
++
++      mtu3_writel(mbase, USB_QMU_TQSAR(epnum),
++                  cpu_to_le32(lower_32_bits(dma)));
++      tqhiar = mtu3_readl(mbase, USB_QMU_TQHIAR(epnum));
++      tqhiar &= ~QMU_START_ADDR_HI_MSK;
++      tqhiar |= QMU_START_ADDR_HI(upper_32_bits(dma));
++      mtu3_writel(mbase, USB_QMU_TQHIAR(epnum), tqhiar);
++}
++
++static void write_rxq_start_addr(void __iomem *mbase, u8 epnum, dma_addr_t dma)
++{
++      u32 rqhiar;
++
++      mtu3_writel(mbase, USB_QMU_RQSAR(epnum),
++                  cpu_to_le32(lower_32_bits(dma)));
++      rqhiar = mtu3_readl(mbase, USB_QMU_RQHIAR(epnum));
++      rqhiar &= ~QMU_START_ADDR_HI_MSK;
++      rqhiar |= QMU_START_ADDR_HI(upper_32_bits(dma));
++      mtu3_writel(mbase, USB_QMU_RQHIAR(epnum), rqhiar);
++}
+ static struct qmu_gpd *gpd_dma_to_virt(struct mtu3_gpd_ring *ring,
+               dma_addr_t dma_addr)
+@@ -193,21 +244,27 @@ static int mtu3_prepare_tx_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq)
+       struct mtu3_gpd_ring *ring = &mep->gpd_ring;
+       struct qmu_gpd *gpd = ring->enqueue;
+       struct usb_request *req = &mreq->request;
++      dma_addr_t enq_dma;
++      u16 ext_addr;
+       /* set all fields to zero as default value */
+       memset(gpd, 0, sizeof(*gpd));
+-      gpd->buffer = cpu_to_le32((u32)req->dma);
++      gpd->buffer = cpu_to_le32(lower_32_bits(req->dma));
++      ext_addr = GPD_EXT_BUF(upper_32_bits(req->dma));
+       gpd->buf_len = cpu_to_le16(req->length);
+       gpd->flag |= GPD_FLAGS_IOC;
+       /* get the next GPD */
+       enq = advance_enq_gpd(ring);
+-      dev_dbg(mep->mtu->dev, "TX-EP%d queue gpd=%p, enq=%p\n",
+-              mep->epnum, gpd, enq);
++      enq_dma = gpd_virt_to_dma(ring, enq);
++      dev_dbg(mep->mtu->dev, "TX-EP%d queue gpd=%p, enq=%p, qdma=%pad\n",
++              mep->epnum, gpd, enq, enq_dma);
+       enq->flag &= ~GPD_FLAGS_HWO;
+-      gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq));
++      gpd->next_gpd = cpu_to_le32(lower_32_bits(enq_dma));
++      ext_addr |= GPD_EXT_NGP(upper_32_bits(enq_dma));
++      gpd->tx_ext_addr = cpu_to_le16(ext_addr);
+       if (req->zero)
+               gpd->ext_flag |= GPD_EXT_FLAG_ZLP;
+@@ -226,21 +283,27 @@ static int mtu3_prepare_rx_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq)
+       struct mtu3_gpd_ring *ring = &mep->gpd_ring;
+       struct qmu_gpd *gpd = ring->enqueue;
+       struct usb_request *req = &mreq->request;
++      dma_addr_t enq_dma;
++      u16 ext_addr;
+       /* set all fields to zero as default value */
+       memset(gpd, 0, sizeof(*gpd));
+-      gpd->buffer = cpu_to_le32((u32)req->dma);
++      gpd->buffer = cpu_to_le32(lower_32_bits(req->dma));
++      ext_addr = GPD_EXT_BUF(upper_32_bits(req->dma));
+       gpd->data_buf_len = cpu_to_le16(req->length);
+       gpd->flag |= GPD_FLAGS_IOC;
+       /* get the next GPD */
+       enq = advance_enq_gpd(ring);
+-      dev_dbg(mep->mtu->dev, "RX-EP%d queue gpd=%p, enq=%p\n",
+-              mep->epnum, gpd, enq);
++      enq_dma = gpd_virt_to_dma(ring, enq);
++      dev_dbg(mep->mtu->dev, "RX-EP%d queue gpd=%p, enq=%p, qdma=%pad\n",
++              mep->epnum, gpd, enq, enq_dma);
+       enq->flag &= ~GPD_FLAGS_HWO;
+-      gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq));
++      gpd->next_gpd = cpu_to_le32(lower_32_bits(enq_dma));
++      ext_addr |= GPD_EXT_NGP(upper_32_bits(enq_dma));
++      gpd->rx_ext_addr = cpu_to_le16(ext_addr);
+       gpd->chksum = qmu_calc_checksum((u8 *)gpd);
+       gpd->flag |= GPD_FLAGS_HWO;
+@@ -267,8 +330,8 @@ int mtu3_qmu_start(struct mtu3_ep *mep)
+       if (mep->is_in) {
+               /* set QMU start address */
+-              mtu3_writel(mbase, USB_QMU_TQSAR(mep->epnum), ring->dma);
+-              mtu3_setbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_DMAREQEN);
++              write_txq_start_addr(mbase, epnum, ring->dma);
++              mtu3_setbits(mbase, MU3D_EP_TXCR0(epnum), TX_DMAREQEN);
+               mtu3_setbits(mbase, U3D_QCR0, QMU_TX_CS_EN(epnum));
+               /* send zero length packet according to ZLP flag in GPD */
+               mtu3_setbits(mbase, U3D_QCR1, QMU_TX_ZLP(epnum));
+@@ -282,8 +345,8 @@ int mtu3_qmu_start(struct mtu3_ep *mep)
+               mtu3_writel(mbase, USB_QMU_TQCSR(epnum), QMU_Q_START);
+       } else {
+-              mtu3_writel(mbase, USB_QMU_RQSAR(mep->epnum), ring->dma);
+-              mtu3_setbits(mbase, MU3D_EP_RXCR0(mep->epnum), RX_DMAREQEN);
++              write_rxq_start_addr(mbase, epnum, ring->dma);
++              mtu3_setbits(mbase, MU3D_EP_RXCR0(epnum), RX_DMAREQEN);
+               mtu3_setbits(mbase, U3D_QCR0, QMU_RX_CS_EN(epnum));
+               /* don't expect ZLP */
+               mtu3_clrbits(mbase, U3D_QCR3, QMU_RX_ZLP(epnum));
+@@ -353,9 +416,9 @@ static void qmu_tx_zlp_error_handler(struct mtu3 *mtu, u8 epnum)
+       struct mtu3_gpd_ring *ring = &mep->gpd_ring;
+       void __iomem *mbase = mtu->mac_base;
+       struct qmu_gpd *gpd_current = NULL;
+-      dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
+       struct usb_request *req = NULL;
+       struct mtu3_request *mreq;
++      dma_addr_t cur_gpd_dma;
+       u32 txcsr = 0;
+       int ret;
+@@ -365,7 +428,8 @@ static void qmu_tx_zlp_error_handler(struct mtu3 *mtu, u8 epnum)
+       else
+               return;
+-      gpd_current = gpd_dma_to_virt(ring, gpd_dma);
++      cur_gpd_dma = read_txq_cur_addr(mbase, epnum);
++      gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
+       if (le16_to_cpu(gpd_current->buf_len) != 0) {
+               dev_err(mtu->dev, "TX EP%d buffer length error(!=0)\n", epnum);
+@@ -408,12 +472,13 @@ static void qmu_done_tx(struct mtu3 *mtu, u8 epnum)
+       void __iomem *mbase = mtu->mac_base;
+       struct qmu_gpd *gpd = ring->dequeue;
+       struct qmu_gpd *gpd_current = NULL;
+-      dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
+       struct usb_request *request = NULL;
+       struct mtu3_request *mreq;
++      dma_addr_t cur_gpd_dma;
+       /*transfer phy address got from QMU register to virtual address */
+-      gpd_current = gpd_dma_to_virt(ring, gpd_dma);
++      cur_gpd_dma = read_txq_cur_addr(mbase, epnum);
++      gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
+       dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n",
+               __func__, epnum, gpd, gpd_current, ring->enqueue);
+@@ -446,11 +511,12 @@ static void qmu_done_rx(struct mtu3 *mtu, u8 epnum)
+       void __iomem *mbase = mtu->mac_base;
+       struct qmu_gpd *gpd = ring->dequeue;
+       struct qmu_gpd *gpd_current = NULL;
+-      dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_RQCPR(epnum));
+       struct usb_request *req = NULL;
+       struct mtu3_request *mreq;
++      dma_addr_t cur_gpd_dma;
+-      gpd_current = gpd_dma_to_virt(ring, gpd_dma);
++      cur_gpd_dma = read_rxq_cur_addr(mbase, epnum);
++      gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
+       dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n",
+               __func__, epnum, gpd, gpd_current, ring->enqueue);
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0108-usb-mtu3-use-FORCE-RG_IDDIG-to-implement-manual-DRD-.patch b/target/linux/mediatek/patches-4.14/0108-usb-mtu3-use-FORCE-RG_IDDIG-to-implement-manual-DRD-.patch
new file mode 100644 (file)
index 0000000..ce454fe
--- /dev/null
@@ -0,0 +1,290 @@
+From 6c4995c9a8ba8841ba640201636954c84f494587 Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 17:10:42 +0800
+Subject: [PATCH 108/224] usb: mtu3: use FORCE/RG_IDDIG to implement manual DRD
+ switch
+
+In order to keep manual DRD switch independent on IDDIG interrupt,
+make use of FORCE/RG_IDDIG instead of IDDIG EINT interrupt to
+implement manual DRD switch function.
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+---
+ drivers/usb/mtu3/mtu3.h         | 18 ++++++++----
+ drivers/usb/mtu3/mtu3_dr.c      | 61 ++++++++++++++++++++++++++++++-----------
+ drivers/usb/mtu3/mtu3_dr.h      |  6 ++++
+ drivers/usb/mtu3/mtu3_host.c    |  5 ++++
+ drivers/usb/mtu3/mtu3_hw_regs.h |  2 ++
+ drivers/usb/mtu3/mtu3_plat.c    | 38 ++-----------------------
+ 6 files changed, 74 insertions(+), 56 deletions(-)
+
+diff --git a/drivers/usb/mtu3/mtu3.h b/drivers/usb/mtu3/mtu3.h
+index ef2dc92a2109..b0c2b5dca045 100644
+--- a/drivers/usb/mtu3/mtu3.h
++++ b/drivers/usb/mtu3/mtu3.h
+@@ -115,6 +115,19 @@ enum mtu3_g_ep0_state {
+ };
+ /**
++ * MTU3_DR_FORCE_NONE: automatically switch host and periperal mode
++ *            by IDPIN signal.
++ * MTU3_DR_FORCE_HOST: force to enter host mode and override OTG
++ *            IDPIN signal.
++ * MTU3_DR_FORCE_DEVICE: force to enter peripheral mode.
++ */
++enum mtu3_dr_force_mode {
++      MTU3_DR_FORCE_NONE = 0,
++      MTU3_DR_FORCE_HOST,
++      MTU3_DR_FORCE_DEVICE,
++};
++
++/**
+  * @base: the base address of fifo
+  * @limit: the bitmap size in bits
+  * @bitmap: fifo bitmap in unit of @MTU3_EP_FIFO_UNIT
+@@ -196,7 +209,6 @@ struct mtu3_gpd_ring {
+ *             xHCI driver initialization, it's necessary for system bootup
+ *             as device.
+ * @is_u3_drd: whether port0 supports usb3.0 dual-role device or not
+-* @id_*: used to maually switch between host and device modes by idpin
+ * @manual_drd_enabled: it's true when supports dual-role device by debugfs
+ *             to switch host/device modes depending on user input.
+ */
+@@ -207,10 +219,6 @@ struct otg_switch_mtk {
+       struct notifier_block id_nb;
+       struct delayed_work extcon_reg_dwork;
+       bool is_u3_drd;
+-      /* dual-role switch by debugfs */
+-      struct pinctrl *id_pinctrl;
+-      struct pinctrl_state *id_float;
+-      struct pinctrl_state *id_ground;
+       bool manual_drd_enabled;
+ };
+diff --git a/drivers/usb/mtu3/mtu3_dr.c b/drivers/usb/mtu3/mtu3_dr.c
+index 560256115b23..ec442cd5a1ad 100644
+--- a/drivers/usb/mtu3/mtu3_dr.c
++++ b/drivers/usb/mtu3/mtu3_dr.c
+@@ -261,21 +261,22 @@ static void extcon_register_dwork(struct work_struct *work)
+  * depending on user input.
+  * This is useful in special cases, such as uses TYPE-A receptacle but also
+  * wants to support dual-role mode.
+- * It generates cable state changes by pulling up/down IDPIN and
+- * notifies driver to switch mode by "extcon-usb-gpio".
+- * NOTE: when use MICRO receptacle, should not enable this interface.
+  */
+ static void ssusb_mode_manual_switch(struct ssusb_mtk *ssusb, int to_host)
+ {
+       struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
+-      if (to_host)
+-              pinctrl_select_state(otg_sx->id_pinctrl, otg_sx->id_ground);
+-      else
+-              pinctrl_select_state(otg_sx->id_pinctrl, otg_sx->id_float);
++      if (to_host) {
++              ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_HOST);
++              ssusb_set_mailbox(otg_sx, MTU3_VBUS_OFF);
++              ssusb_set_mailbox(otg_sx, MTU3_ID_GROUND);
++      } else {
++              ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_DEVICE);
++              ssusb_set_mailbox(otg_sx, MTU3_ID_FLOAT);
++              ssusb_set_mailbox(otg_sx, MTU3_VBUS_VALID);
++      }
+ }
+-
+ static int ssusb_mode_show(struct seq_file *sf, void *unused)
+ {
+       struct ssusb_mtk *ssusb = sf->private;
+@@ -388,17 +389,45 @@ static void ssusb_debugfs_exit(struct ssusb_mtk *ssusb)
+       debugfs_remove_recursive(ssusb->dbgfs_root);
+ }
++void ssusb_set_force_mode(struct ssusb_mtk *ssusb,
++                        enum mtu3_dr_force_mode mode)
++{
++      u32 value;
++
++      value = mtu3_readl(ssusb->ippc_base, SSUSB_U2_CTRL(0));
++      switch (mode) {
++      case MTU3_DR_FORCE_DEVICE:
++              value |= SSUSB_U2_PORT_FORCE_IDDIG | SSUSB_U2_PORT_RG_IDDIG;
++              break;
++      case MTU3_DR_FORCE_HOST:
++              value |= SSUSB_U2_PORT_FORCE_IDDIG;
++              value &= ~SSUSB_U2_PORT_RG_IDDIG;
++              break;
++      case MTU3_DR_FORCE_NONE:
++              value &= ~(SSUSB_U2_PORT_FORCE_IDDIG | SSUSB_U2_PORT_RG_IDDIG);
++              break;
++      default:
++              return;
++      }
++      mtu3_writel(ssusb->ippc_base, SSUSB_U2_CTRL(0), value);
++}
++
+ int ssusb_otg_switch_init(struct ssusb_mtk *ssusb)
+ {
+       struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
+-      INIT_DELAYED_WORK(&otg_sx->extcon_reg_dwork, extcon_register_dwork);
+-
+-      if (otg_sx->manual_drd_enabled)
++      if (otg_sx->manual_drd_enabled) {
+               ssusb_debugfs_init(ssusb);
+-
+-      /* It is enough to delay 1s for waiting for host initialization */
+-      schedule_delayed_work(&otg_sx->extcon_reg_dwork, HZ);
++      } else {
++              INIT_DELAYED_WORK(&otg_sx->extcon_reg_dwork,
++                                extcon_register_dwork);
++
++              /*
++               * It is enough to delay 1s for waiting for
++               * host initialization
++               */
++              schedule_delayed_work(&otg_sx->extcon_reg_dwork, HZ);
++      }
+       return 0;
+ }
+@@ -407,8 +436,8 @@ void ssusb_otg_switch_exit(struct ssusb_mtk *ssusb)
+ {
+       struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
+-      cancel_delayed_work(&otg_sx->extcon_reg_dwork);
+-
+       if (otg_sx->manual_drd_enabled)
+               ssusb_debugfs_exit(ssusb);
++      else
++              cancel_delayed_work(&otg_sx->extcon_reg_dwork);
+ }
+diff --git a/drivers/usb/mtu3/mtu3_dr.h b/drivers/usb/mtu3/mtu3_dr.h
+index 9b228b5811b0..0f0cbac00192 100644
+--- a/drivers/usb/mtu3/mtu3_dr.h
++++ b/drivers/usb/mtu3/mtu3_dr.h
+@@ -87,6 +87,8 @@ static inline void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
+ int ssusb_otg_switch_init(struct ssusb_mtk *ssusb);
+ void ssusb_otg_switch_exit(struct ssusb_mtk *ssusb);
+ int ssusb_set_vbus(struct otg_switch_mtk *otg_sx, int is_on);
++void ssusb_set_force_mode(struct ssusb_mtk *ssusb,
++                        enum mtu3_dr_force_mode mode);
+ #else
+@@ -103,6 +105,10 @@ static inline int ssusb_set_vbus(struct otg_switch_mtk *otg_sx, int is_on)
+       return 0;
+ }
++static inline void
++ssusb_set_force_mode(struct ssusb_mtk *ssusb, enum mtu3_dr_force_mode mode)
++{}
++
+ #endif
+ #endif                /* _MTU3_DR_H_ */
+diff --git a/drivers/usb/mtu3/mtu3_host.c b/drivers/usb/mtu3/mtu3_host.c
+index edcc59148171..ec76b86dd887 100644
+--- a/drivers/usb/mtu3/mtu3_host.c
++++ b/drivers/usb/mtu3/mtu3_host.c
+@@ -189,6 +189,8 @@ int ssusb_host_disable(struct ssusb_mtk *ssusb, bool suspend)
+ static void ssusb_host_setup(struct ssusb_mtk *ssusb)
+ {
++      struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
++
+       host_ports_num_get(ssusb);
+       /*
+@@ -197,6 +199,9 @@ static void ssusb_host_setup(struct ssusb_mtk *ssusb)
+        */
+       ssusb_host_enable(ssusb);
++      if (otg_sx->manual_drd_enabled)
++              ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_HOST);
++
+       /* if port0 supports dual-role, works as host mode by default */
+       ssusb_set_vbus(&ssusb->otg_switch, 1);
+ }
+diff --git a/drivers/usb/mtu3/mtu3_hw_regs.h b/drivers/usb/mtu3/mtu3_hw_regs.h
+index b6059752dc12..a7e35f6ad90a 100644
+--- a/drivers/usb/mtu3/mtu3_hw_regs.h
++++ b/drivers/usb/mtu3/mtu3_hw_regs.h
+@@ -472,6 +472,8 @@
+ #define SSUSB_U3_PORT_DIS             BIT(0)
+ /* U3D_SSUSB_U2_CTRL_0P */
++#define SSUSB_U2_PORT_RG_IDDIG                BIT(12)
++#define SSUSB_U2_PORT_FORCE_IDDIG     BIT(11)
+ #define SSUSB_U2_PORT_VBUSVALID       BIT(9)
+ #define SSUSB_U2_PORT_OTG_SEL         BIT(7)
+ #define SSUSB_U2_PORT_HOST            BIT(2)
+diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c
+index fb8992011bde..1e473b068650 100644
+--- a/drivers/usb/mtu3/mtu3_plat.c
++++ b/drivers/usb/mtu3/mtu3_plat.c
+@@ -21,7 +21,6 @@
+ #include <linux/module.h>
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
+-#include <linux/pinctrl/consumer.h>
+ #include <linux/platform_device.h>
+ #include "mtu3.h"
+@@ -212,33 +211,6 @@ static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
+       mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
+ }
+-static int get_iddig_pinctrl(struct ssusb_mtk *ssusb)
+-{
+-      struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
+-
+-      otg_sx->id_pinctrl = devm_pinctrl_get(ssusb->dev);
+-      if (IS_ERR(otg_sx->id_pinctrl)) {
+-              dev_err(ssusb->dev, "Cannot find id pinctrl!\n");
+-              return PTR_ERR(otg_sx->id_pinctrl);
+-      }
+-
+-      otg_sx->id_float =
+-              pinctrl_lookup_state(otg_sx->id_pinctrl, "id_float");
+-      if (IS_ERR(otg_sx->id_float)) {
+-              dev_err(ssusb->dev, "Cannot find pinctrl id_float!\n");
+-              return PTR_ERR(otg_sx->id_float);
+-      }
+-
+-      otg_sx->id_ground =
+-              pinctrl_lookup_state(otg_sx->id_pinctrl, "id_ground");
+-      if (IS_ERR(otg_sx->id_ground)) {
+-              dev_err(ssusb->dev, "Cannot find pinctrl id_ground!\n");
+-              return PTR_ERR(otg_sx->id_ground);
+-      }
+-
+-      return 0;
+-}
+-
+ /* ignore the error if the clock does not exist */
+ static struct clk *get_optional_clk(struct device *dev, const char *id)
+ {
+@@ -349,15 +321,11 @@ static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
+                       dev_err(ssusb->dev, "couldn't get extcon device\n");
+                       return -EPROBE_DEFER;
+               }
+-              if (otg_sx->manual_drd_enabled) {
+-                      ret = get_iddig_pinctrl(ssusb);
+-                      if (ret)
+-                              return ret;
+-              }
+       }
+-      dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk:%x\n",
+-              ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk);
++      dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk: %x, drd: %s\n",
++              ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk,
++              otg_sx->manual_drd_enabled ? "manual" : "auto");
+       return 0;
+ }
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0109-usb-mtu3-add-support-for-usb3.1-IP.patch b/target/linux/mediatek/patches-4.14/0109-usb-mtu3-add-support-for-usb3.1-IP.patch
new file mode 100644 (file)
index 0000000..020dabf
--- /dev/null
@@ -0,0 +1,165 @@
+From 8f444887e23b9f0ea31aaae74fbc18171714d8d2 Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 17:10:43 +0800
+Subject: [PATCH 109/224] usb: mtu3: add support for usb3.1 IP
+
+Support SuperSpeedPlus for usb3.1 device IP
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+---
+ drivers/usb/mtu3/mtu3.h            |  1 +
+ drivers/usb/mtu3/mtu3_core.c       | 14 +++++++++++---
+ drivers/usb/mtu3/mtu3_gadget.c     |  3 ++-
+ drivers/usb/mtu3/mtu3_gadget_ep0.c | 16 ++++++++--------
+ drivers/usb/mtu3/mtu3_hw_regs.h    |  1 +
+ 5 files changed, 23 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/usb/mtu3/mtu3.h b/drivers/usb/mtu3/mtu3.h
+index b0c2b5dca045..d80e4e813248 100644
+--- a/drivers/usb/mtu3/mtu3.h
++++ b/drivers/usb/mtu3/mtu3.h
+@@ -94,6 +94,7 @@ enum mtu3_speed {
+       MTU3_SPEED_FULL = 1,
+       MTU3_SPEED_HIGH = 3,
+       MTU3_SPEED_SUPER = 4,
++      MTU3_SPEED_SUPER_PLUS = 5,
+ };
+ /**
+diff --git a/drivers/usb/mtu3/mtu3_core.c b/drivers/usb/mtu3/mtu3_core.c
+index cd4528f5f337..67f7a309aba7 100644
+--- a/drivers/usb/mtu3/mtu3_core.c
++++ b/drivers/usb/mtu3/mtu3_core.c
+@@ -237,7 +237,7 @@ void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
+ void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
+ {
+-      if (mtu->is_u3_ip && (mtu->max_speed == USB_SPEED_SUPER))
++      if (mtu->is_u3_ip && mtu->max_speed >= USB_SPEED_SUPER)
+               mtu3_ss_func_set(mtu, is_on);
+       else
+               mtu3_hs_softconn_set(mtu, is_on);
+@@ -547,6 +547,9 @@ static void mtu3_set_speed(struct mtu3 *mtu)
+               mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
+               /* HS/FS detected by HW */
+               mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
++      } else if (mtu->max_speed == USB_SPEED_SUPER) {
++              mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
++                           SSUSB_U3_PORT_SSP_SPEED);
+       }
+       dev_info(mtu->dev, "max_speed: %s\n",
+@@ -624,6 +627,10 @@ static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
+               udev_speed = USB_SPEED_SUPER;
+               maxpkt = 512;
+               break;
++      case MTU3_SPEED_SUPER_PLUS:
++              udev_speed = USB_SPEED_SUPER_PLUS;
++              maxpkt = 512;
++              break;
+       default:
+               udev_speed = USB_SPEED_UNKNOWN;
+               break;
+@@ -825,14 +832,15 @@ int ssusb_gadget_init(struct ssusb_mtk *ssusb)
+       case USB_SPEED_FULL:
+       case USB_SPEED_HIGH:
+       case USB_SPEED_SUPER:
++      case USB_SPEED_SUPER_PLUS:
+               break;
+       default:
+               dev_err(dev, "invalid max_speed: %s\n",
+                       usb_speed_string(mtu->max_speed));
+               /* fall through */
+       case USB_SPEED_UNKNOWN:
+-              /* default as SS */
+-              mtu->max_speed = USB_SPEED_SUPER;
++              /* default as SSP */
++              mtu->max_speed = USB_SPEED_SUPER_PLUS;
+               break;
+       }
+diff --git a/drivers/usb/mtu3/mtu3_gadget.c b/drivers/usb/mtu3/mtu3_gadget.c
+index 434fca58143c..b495471f689f 100644
+--- a/drivers/usb/mtu3/mtu3_gadget.c
++++ b/drivers/usb/mtu3/mtu3_gadget.c
+@@ -89,6 +89,7 @@ static int mtu3_ep_enable(struct mtu3_ep *mep)
+       switch (mtu->g.speed) {
+       case USB_SPEED_SUPER:
++      case USB_SPEED_SUPER_PLUS:
+               if (usb_endpoint_xfer_int(desc) ||
+                               usb_endpoint_xfer_isoc(desc)) {
+                       interval = desc->bInterval;
+@@ -456,7 +457,7 @@ static int mtu3_gadget_wakeup(struct usb_gadget *gadget)
+               return  -EOPNOTSUPP;
+       spin_lock_irqsave(&mtu->lock, flags);
+-      if (mtu->g.speed == USB_SPEED_SUPER) {
++      if (mtu->g.speed >= USB_SPEED_SUPER) {
+               mtu3_setbits(mtu->mac_base, U3D_LINK_POWER_CONTROL, UX_EXIT);
+       } else {
+               mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT, RESUME);
+diff --git a/drivers/usb/mtu3/mtu3_gadget_ep0.c b/drivers/usb/mtu3/mtu3_gadget_ep0.c
+index 958d74dd2b78..020b25314a68 100644
+--- a/drivers/usb/mtu3/mtu3_gadget_ep0.c
++++ b/drivers/usb/mtu3/mtu3_gadget_ep0.c
+@@ -212,8 +212,8 @@ ep0_get_status(struct mtu3 *mtu, const struct usb_ctrlrequest *setup)
+       case USB_RECIP_DEVICE:
+               result[0] = mtu->is_self_powered << USB_DEVICE_SELF_POWERED;
+               result[0] |= mtu->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
+-              /* superspeed only */
+-              if (mtu->g.speed == USB_SPEED_SUPER) {
++
++              if (mtu->g.speed >= USB_SPEED_SUPER) {
+                       result[0] |= mtu->u1_enable << USB_DEV_STAT_U1_ENABLED;
+                       result[0] |= mtu->u2_enable << USB_DEV_STAT_U2_ENABLED;
+               }
+@@ -329,8 +329,8 @@ static int ep0_handle_feature_dev(struct mtu3 *mtu,
+               handled = handle_test_mode(mtu, setup);
+               break;
+       case USB_DEVICE_U1_ENABLE:
+-              if (mtu->g.speed != USB_SPEED_SUPER ||
+-                      mtu->g.state != USB_STATE_CONFIGURED)
++              if (mtu->g.speed < USB_SPEED_SUPER ||
++                  mtu->g.state != USB_STATE_CONFIGURED)
+                       break;
+               lpc = mtu3_readl(mbase, U3D_LINK_POWER_CONTROL);
+@@ -344,8 +344,8 @@ static int ep0_handle_feature_dev(struct mtu3 *mtu,
+               handled = 1;
+               break;
+       case USB_DEVICE_U2_ENABLE:
+-              if (mtu->g.speed != USB_SPEED_SUPER ||
+-                      mtu->g.state != USB_STATE_CONFIGURED)
++              if (mtu->g.speed < USB_SPEED_SUPER ||
++                  mtu->g.state != USB_STATE_CONFIGURED)
+                       break;
+               lpc = mtu3_readl(mbase, U3D_LINK_POWER_CONTROL);
+@@ -384,8 +384,8 @@ static int ep0_handle_feature(struct mtu3 *mtu,
+               break;
+       case USB_RECIP_INTERFACE:
+               /* superspeed only */
+-              if ((value == USB_INTRF_FUNC_SUSPEND)
+-                      && (mtu->g.speed == USB_SPEED_SUPER)) {
++              if (value == USB_INTRF_FUNC_SUSPEND &&
++                  mtu->g.speed >= USB_SPEED_SUPER) {
+                       /*
+                        * forward the request because function drivers
+                        * should handle it
+diff --git a/drivers/usb/mtu3/mtu3_hw_regs.h b/drivers/usb/mtu3/mtu3_hw_regs.h
+index a7e35f6ad90a..6953436a1688 100644
+--- a/drivers/usb/mtu3/mtu3_hw_regs.h
++++ b/drivers/usb/mtu3/mtu3_hw_regs.h
+@@ -467,6 +467,7 @@
+ #define SSUSB_VBUS_CHG_INT_B_EN               BIT(6)
+ /* U3D_SSUSB_U3_CTRL_0P */
++#define SSUSB_U3_PORT_SSP_SPEED       BIT(9)
+ #define SSUSB_U3_PORT_HOST_SEL                BIT(2)
+ #define SSUSB_U3_PORT_PDN             BIT(1)
+ #define SSUSB_U3_PORT_DIS             BIT(0)
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0110-usb-mtu3-get-optional-vbus-for-host-only-mode.patch b/target/linux/mediatek/patches-4.14/0110-usb-mtu3-get-optional-vbus-for-host-only-mode.patch
new file mode 100644 (file)
index 0000000..d55fe7d
--- /dev/null
@@ -0,0 +1,45 @@
+From b6712b72d1273e792ee8a533048ba731a3709163 Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 17:10:44 +0800
+Subject: [PATCH 110/224] usb: mtu3: get optional vbus for host only mode
+
+When dr_mode is set as USB_DR_MODE_HOST, it's better to try to
+get optional vbus, this can increase flexibility, although we
+can set vbus as always on for regulator or put it in host driver
+to turn it on.
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+---
+ drivers/usb/mtu3/mtu3_plat.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c
+index 1e473b068650..7ca81f4e78a3 100644
+--- a/drivers/usb/mtu3/mtu3_plat.c
++++ b/drivers/usb/mtu3/mtu3_plat.c
+@@ -300,10 +300,6 @@ static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
+       of_property_read_u32(node, "mediatek,u3p-dis-msk",
+                            &ssusb->u3p_dis_msk);
+-      if (ssusb->dr_mode != USB_DR_MODE_OTG)
+-              return 0;
+-
+-      /* if dual-role mode is supported */
+       vbus = devm_regulator_get(&pdev->dev, "vbus");
+       if (IS_ERR(vbus)) {
+               dev_err(dev, "failed to get vbus\n");
+@@ -311,6 +307,10 @@ static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
+       }
+       otg_sx->vbus = vbus;
++      if (ssusb->dr_mode == USB_DR_MODE_HOST)
++              return 0;
++
++      /* if dual-role mode is supported */
+       otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd");
+       otg_sx->manual_drd_enabled =
+               of_property_read_bool(node, "enable-manual-drd");
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0111-usb-mtu3-set-invalid-dr_mode-as-dual-role-mode.patch b/target/linux/mediatek/patches-4.14/0111-usb-mtu3-set-invalid-dr_mode-as-dual-role-mode.patch
new file mode 100644 (file)
index 0000000..1c23d15
--- /dev/null
@@ -0,0 +1,34 @@
+From e315036cdbf8dad7cff4df9dfe8bcff2eddf2277 Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 17:10:45 +0800
+Subject: [PATCH 111/224] usb: mtu3: set invalid dr_mode as dual-role mode
+
+Treat dr_mode of USB_DR_MODE_UNKNOWN as USB_DR_MODE_OTG to
+enhance functional robustness.
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+---
+ drivers/usb/mtu3/mtu3_plat.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c
+index 7ca81f4e78a3..9ff33579b42e 100644
+--- a/drivers/usb/mtu3/mtu3_plat.c
++++ b/drivers/usb/mtu3/mtu3_plat.c
+@@ -283,10 +283,8 @@ static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
+               return PTR_ERR(ssusb->ippc_base);
+       ssusb->dr_mode = usb_get_dr_mode(dev);
+-      if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) {
+-              dev_err(dev, "dr_mode is error\n");
+-              return -EINVAL;
+-      }
++      if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN)
++              ssusb->dr_mode = USB_DR_MODE_OTG;
+       if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
+               return 0;
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0112-usb-mtu3-set-otg_sel-for-u2port-only-if-works-as-dua.patch b/target/linux/mediatek/patches-4.14/0112-usb-mtu3-set-otg_sel-for-u2port-only-if-works-as-dua.patch
new file mode 100644 (file)
index 0000000..3a74fe5
--- /dev/null
@@ -0,0 +1,49 @@
+From 36f70702b66cd3453b65d46b5c26ea87d8897363 Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 17:10:46 +0800
+Subject: [PATCH 112/224] usb: mtu3: set otg_sel for u2port only if works as
+ dual-role mode
+
+When set otg_sel(SSUSB_U2_PORT_OTG_SEL) for u2port which supports
+dual-role mode, the controller will automatically switch mode
+between host and device according to IDDIG signal. But if the
+u2port only supports device mode, and no IDDIG pin is provided,
+setting otg_sel may cause failure of detection by host.
+So set it only for dual-role mode.
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+---
+ drivers/usb/mtu3/mtu3_core.c | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/mtu3/mtu3_core.c b/drivers/usb/mtu3/mtu3_core.c
+index 67f7a309aba7..7c149a7da14e 100644
+--- a/drivers/usb/mtu3/mtu3_core.c
++++ b/drivers/usb/mtu3/mtu3_core.c
+@@ -115,7 +115,9 @@ static int mtu3_device_enable(struct mtu3 *mtu)
+       mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
+               (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
+               SSUSB_U2_PORT_HOST_SEL));
+-      mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
++
++      if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
++              mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
+       return ssusb_check_clocks(mtu->ssusb, check_clk);
+ }
+@@ -130,7 +132,10 @@ static void mtu3_device_disable(struct mtu3 *mtu)
+       mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
+               SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
+-      mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
++
++      if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
++              mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
++
+       mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
+ }
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0113-dt-bindings-usb-mtu3-add-a-optional-property-to-disa.patch b/target/linux/mediatek/patches-4.14/0113-dt-bindings-usb-mtu3-add-a-optional-property-to-disa.patch
new file mode 100644 (file)
index 0000000..c45f7d2
--- /dev/null
@@ -0,0 +1,30 @@
+From 6b6f2c178ee2cd57713993e3cf0afbe4effb2578 Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 17:10:47 +0800
+Subject: [PATCH 113/224] dt-bindings: usb: mtu3: add a optional property to
+ disable u3ports
+
+Add a new optional property to disable u3ports
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+---
+ Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
+index 49f54767cd21..7c611d14a0a0 100644
+--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
++++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
+@@ -44,6 +44,8 @@ Optional properties:
+  - mediatek,enable-wakeup : supports ip sleep wakeup used by host mode
+  - mediatek,syscon-wakeup : phandle to syscon used to access USB wakeup
+       control register, it depends on "mediatek,enable-wakeup".
++ - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
++      bit1 for u3port1, ... etc;
+ Sub-nodes:
+ The xhci should be added as subnode to mtu3 as shown in the following example
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0114-dt-bindings-usb-mtu3-remove-dummy-clocks-and-add-opt.patch b/target/linux/mediatek/patches-4.14/0114-dt-bindings-usb-mtu3-remove-dummy-clocks-and-add-opt.patch
new file mode 100644 (file)
index 0000000..71e44b3
--- /dev/null
@@ -0,0 +1,46 @@
+From 2c90367440a0dbf9962e7a7f701b0e7a320d325a Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 17:10:48 +0800
+Subject: [PATCH 114/224] dt-bindings: usb: mtu3: remove dummy clocks and add
+ optional ones
+
+Remove dummy clocks for usb wakeup and add optional ones for
+mcu_bus and dma_bus bus.
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+---
+ Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
+index 7c611d14a0a0..49c982bb5bfc 100644
+--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
++++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
+@@ -14,9 +14,9 @@ Required properties:
+  - vusb33-supply : regulator of USB avdd3.3v
+  - clocks : a list of phandle + clock-specifier pairs, one for each
+       entry in clock-names
+- - clock-names : must contain "sys_ck" and "ref_ck" for clock of controller;
+-      "wakeup_deb_p0" and "wakeup_deb_p1" are optional, they are
+-      depends on "mediatek,enable-wakeup"
++ - clock-names : must contain "sys_ck" for clock of controller,
++      the following clocks are optional:
++      "ref_ck", "mcu_ck" and "dam_ck";
+  - phys : a list of phandle + phy specifier pairs
+  - dr_mode : should be one of "host", "peripheral" or "otg",
+       refer to usb/generic.txt
+@@ -65,9 +65,7 @@ ssusb: usb@11271000 {
+       clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>,
+                <&pericfg CLK_PERI_USB0>,
+                <&pericfg CLK_PERI_USB1>;
+-      clock-names = "sys_ck", "ref_ck",
+-                    "wakeup_deb_p0",
+-                    "wakeup_deb_p1";
++      clock-names = "sys_ck", "ref_ck";
+       vusb33-supply = <&mt6397_vusb_reg>;
+       vbus-supply = <&usb_p0_vbus>;
+       extcon = <&extcon_usb>;
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0115-dt-bindings-usb-mtu3-remove-optional-pinctrls.patch b/target/linux/mediatek/patches-4.14/0115-dt-bindings-usb-mtu3-remove-optional-pinctrls.patch
new file mode 100644 (file)
index 0000000..ea5cf5f
--- /dev/null
@@ -0,0 +1,35 @@
+From df2f0d10213798a806c90bc06db6bed501e7bf7d Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 17:10:49 +0800
+Subject: [PATCH 115/224] dt-bindings: usb: mtu3: remove optional pinctrls
+
+Remove optional pinctrls due to using FORCE/RG_IDDIG to implement
+manual switch function.
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+---
+ Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
+index 49c982bb5bfc..b2271d8e6b50 100644
+--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
++++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
+@@ -30,9 +30,10 @@ Optional properties:
+       when supports dual-role mode.
+  - vbus-supply : reference to the VBUS regulator, needed when supports
+       dual-role mode.
+- - pinctl-names : a pinctrl state named "default" must be defined,
+-      "id_float" and "id_ground" are optinal which depends on
+-      "mediatek,enable-manual-drd"
++ - pinctrl-names : a pinctrl state named "default" is optional, and need be
++      defined if auto drd switch is enabled, that means the property dr_mode
++      is set as "otg", and meanwhile the property "mediatek,enable-manual-drd"
++      is not set.
+  - pinctrl-0 : pin control group
+       See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0116-dt-bindings-arm-mediatek-add-MT7622-string-to-the-PM.patch b/target/linux/mediatek/patches-4.14/0116-dt-bindings-arm-mediatek-add-MT7622-string-to-the-PM.patch
new file mode 100644 (file)
index 0000000..540c127
--- /dev/null
@@ -0,0 +1,43 @@
+From 1567cde49a0f2304e18c08e2ccd830e0686fc0a7 Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Wed, 18 Oct 2017 16:28:42 +0800
+Subject: [PATCH 116/224] dt-bindings: arm: mediatek: add MT7622 string to the
+ PMIC wrapper doc
+
+Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com>
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
+index 107700d00df4..bf80e3f96f8c 100644
+--- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
++++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
+@@ -19,6 +19,7 @@ IP Pairing
+ Required properties in pwrap device node.
+ - compatible:
+       "mediatek,mt2701-pwrap" for MT2701/7623 SoCs
++      "mediatek,mt7622-pwrap" for MT7622 SoCs
+       "mediatek,mt8135-pwrap" for MT8135 SoCs
+       "mediatek,mt8173-pwrap" for MT8173 SoCs
+ - interrupts: IRQ for pwrap in SOC
+@@ -36,9 +37,12 @@ Required properties in pwrap device node.
+ - clocks: Must contain an entry for each entry in clock-names.
+ Optional properities:
+-- pmic: Mediatek PMIC MFD is the child device of pwrap
++- pmic: Using either MediaTek PMIC MFD as the child device of pwrap
+   See the following for child node definitions:
+   Documentation/devicetree/bindings/mfd/mt6397.txt
++  or the regulator-only device as the child device of pwrap, such as MT6380.
++  See the following definitions for such kinds of devices.
++  Documentation/devicetree/bindings/regulator/mt6380-regulator.txt
+ Example:
+       pwrap: pwrap@1000f000 {
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0117-soc-mediatek-pwrap-add-pwrap_read32-for-reading-in-3.patch b/target/linux/mediatek/patches-4.14/0117-soc-mediatek-pwrap-add-pwrap_read32-for-reading-in-3.patch
new file mode 100644 (file)
index 0000000..c178ddc
--- /dev/null
@@ -0,0 +1,139 @@
+From 9c37953bd08daa3ca227098d763e980d1898add3 Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Wed, 18 Oct 2017 16:28:43 +0800
+Subject: [PATCH 117/224] soc: mediatek: pwrap: add pwrap_read32 for reading in
+ 32-bit mode
+
+Some regulators such as MediaTek MT6380 has to be read in 32-bit mode.
+So the patch adds pwrap_read32, rename old pwrap_read into pwrap_read16
+and one function pointer is introduced for increasing flexibility allowing
+the determination which mode is used by the pwrap slave detection through
+device tree.
+
+Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com>
+Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ drivers/soc/mediatek/mtk-pmic-wrap.c | 55 +++++++++++++++++++++++++++++++++++-
+ 1 file changed, 54 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index f095faac1e04..06930e2ebe4c 100644
+--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
++++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
+@@ -487,6 +487,7 @@ static int mt8135_regs[] = {
+ enum pmic_type {
+       PMIC_MT6323,
++      PMIC_MT6380,
+       PMIC_MT6397,
+ };
+@@ -496,9 +497,16 @@ enum pwrap_type {
+       PWRAP_MT8173,
+ };
++struct pmic_wrapper;
+ struct pwrap_slv_type {
+       const u32 *dew_regs;
+       enum pmic_type type;
++      /*
++       * pwrap operations are highly associated with the PMIC types,
++       * so the pointers added increases flexibility allowing determination
++       * which type is used by the detection through device tree.
++       */
++      int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
+ };
+ struct pmic_wrapper {
+@@ -609,7 +617,7 @@ static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
+       return 0;
+ }
+-static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
++static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
+ {
+       int ret;
+@@ -632,6 +640,39 @@ static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
+       return 0;
+ }
++static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
++{
++      int ret, msb;
++
++      *rdata = 0;
++      for (msb = 0; msb < 2; msb++) {
++              ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
++              if (ret) {
++                      pwrap_leave_fsm_vldclr(wrp);
++                      return ret;
++              }
++
++              pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
++                           PWRAP_WACS2_CMD);
++
++              ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
++              if (ret)
++                      return ret;
++
++              *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
++                         PWRAP_WACS2_RDATA)) << (16 * msb));
++
++              pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
++      }
++
++      return 0;
++}
++
++static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
++{
++      return wrp->slave->pwrap_read(wrp, adr, rdata);
++}
++
+ static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
+ {
+       return pwrap_read(context, adr, rdata);
+@@ -752,6 +793,8 @@ static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
+               pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
+               pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
+               break;
++      default:
++              break;
+       }
+       return 0;
+@@ -815,6 +858,8 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
+               pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
+                           0x1);
+               break;
++      default:
++              break;
+       }
+       /* wait for cipher data ready@AP */
+@@ -1036,11 +1081,19 @@ static const struct regmap_config pwrap_regmap_config = {
+ static const struct pwrap_slv_type pmic_mt6323 = {
+       .dew_regs = mt6323_regs,
+       .type = PMIC_MT6323,
++      .pwrap_read = pwrap_read16,
++};
++
++static const struct pwrap_slv_type pmic_mt6380 = {
++      .dew_regs = NULL,
++      .type = PMIC_MT6380,
++      .pwrap_read = pwrap_read32,
+ };
+ static const struct pwrap_slv_type pmic_mt6397 = {
+       .dew_regs = mt6397_regs,
+       .type = PMIC_MT6397,
++      .pwrap_read = pwrap_read16,
+ };
+ static const struct of_device_id of_slave_match_tbl[] = {
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0118-soc-mediatek-pwrap-add-pwrap_write32-for-writing-in-.patch b/target/linux/mediatek/patches-4.14/0118-soc-mediatek-pwrap-add-pwrap_write32-for-writing-in-.patch
new file mode 100644 (file)
index 0000000..6048d6e
--- /dev/null
@@ -0,0 +1,137 @@
+From 635f800995e4ea2a18ce7520d816dab018ce091f Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Wed, 18 Oct 2017 16:28:44 +0800
+Subject: [PATCH 118/224] soc: mediatek: pwrap: add pwrap_write32 for writing
+ in 32-bit mode
+
+Some regulators such as MediaTek MT6380 also has to be written in
+32-bit mode. So the patch adds pwrap_write32, rename old pwrap_write
+into pwrap_write16 and one additional function pointer is introduced
+for increasing flexibility allowing the determination which mode is
+used by the pwrap slave detection through device tree.
+
+Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com>
+Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ drivers/soc/mediatek/mtk-pmic-wrap.c | 70 +++++++++++++++++++++++++++---------
+ 1 file changed, 54 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 06930e2ebe4c..2d3a8faae124 100644
+--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
++++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
+@@ -507,6 +507,7 @@ struct pwrap_slv_type {
+        * which type is used by the detection through device tree.
+        */
+       int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
++      int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
+ };
+ struct pmic_wrapper {
+@@ -601,22 +602,6 @@ static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
+       } while (1);
+ }
+-static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
+-{
+-      int ret;
+-
+-      ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
+-      if (ret) {
+-              pwrap_leave_fsm_vldclr(wrp);
+-              return ret;
+-      }
+-
+-      pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
+-                      PWRAP_WACS2_CMD);
+-
+-      return 0;
+-}
+-
+ static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
+ {
+       int ret;
+@@ -673,6 +658,56 @@ static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
+       return wrp->slave->pwrap_read(wrp, adr, rdata);
+ }
++static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
++{
++      int ret;
++
++      ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
++      if (ret) {
++              pwrap_leave_fsm_vldclr(wrp);
++              return ret;
++      }
++
++      pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
++                   PWRAP_WACS2_CMD);
++
++      return 0;
++}
++
++static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
++{
++      int ret, msb, rdata;
++
++      for (msb = 0; msb < 2; msb++) {
++              ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
++              if (ret) {
++                      pwrap_leave_fsm_vldclr(wrp);
++                      return ret;
++              }
++
++              pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
++                           ((wdata >> (msb * 16)) & 0xffff),
++                           PWRAP_WACS2_CMD);
++
++              /*
++               * The pwrap_read operation is the requirement of hardware used
++               * for the synchronization between two successive 16-bit
++               * pwrap_writel operations composing one 32-bit bus writing.
++               * Otherwise, we'll find the result fails on the lower 16-bit
++               * pwrap writing.
++               */
++              if (!msb)
++                      pwrap_read(wrp, adr, &rdata);
++      }
++
++      return 0;
++}
++
++static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
++{
++      return wrp->slave->pwrap_write(wrp, adr, wdata);
++}
++
+ static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
+ {
+       return pwrap_read(context, adr, rdata);
+@@ -1082,18 +1117,21 @@ static const struct pwrap_slv_type pmic_mt6323 = {
+       .dew_regs = mt6323_regs,
+       .type = PMIC_MT6323,
+       .pwrap_read = pwrap_read16,
++      .pwrap_write = pwrap_write16,
+ };
+ static const struct pwrap_slv_type pmic_mt6380 = {
+       .dew_regs = NULL,
+       .type = PMIC_MT6380,
+       .pwrap_read = pwrap_read32,
++      .pwrap_write = pwrap_write32,
+ };
+ static const struct pwrap_slv_type pmic_mt6397 = {
+       .dew_regs = mt6397_regs,
+       .type = PMIC_MT6397,
+       .pwrap_read = pwrap_read16,
++      .pwrap_write = pwrap_write16,
+ };
+ static const struct of_device_id of_slave_match_tbl[] = {
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0119-soc-mediatek-pwrap-refactor-pwrap_init-for-the-vario.patch b/target/linux/mediatek/patches-4.14/0119-soc-mediatek-pwrap-refactor-pwrap_init-for-the-vario.patch
new file mode 100644 (file)
index 0000000..c730fb1
--- /dev/null
@@ -0,0 +1,232 @@
+From 16bebe4ad52083316907fb7149c797cd331f5948 Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Wed, 18 Oct 2017 16:28:45 +0800
+Subject: [PATCH 119/224] soc: mediatek: pwrap: refactor pwrap_init for the
+ various PMIC types
+
+pwrap initialization is highly associated with the base SoC and the
+target PMICs, so slight refactorization is made here for allowing
+pwrap_init to run on those PMICs with different capability from the
+previous MediaTek PMICs and the determination for the enablement of the
+pwrap capability depending on PMIC type. Apart from this, the patch
+makes the driver more extensible especially when more PMICs join into
+the pwrap driver.
+
+Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com>
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ drivers/soc/mediatek/mtk-pmic-wrap.c | 130 ++++++++++++++++++++++++-----------
+ 1 file changed, 90 insertions(+), 40 deletions(-)
+
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 2d3a8faae124..e3398e37a7a6 100644
+--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
++++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
+@@ -70,6 +70,12 @@
+                                         PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
+                                         PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
++/* Group of bits used for shown slave capability */
++#define PWRAP_SLV_CAP_SPI     BIT(0)
++#define PWRAP_SLV_CAP_DUALIO  BIT(1)
++#define PWRAP_SLV_CAP_SECURITY        BIT(2)
++#define HAS_CAP(_c, _x)       (((_c) & (_x)) == (_x))
++
+ /* defines for slave device wrapper registers */
+ enum dew_regs {
+       PWRAP_DEW_BASE,
+@@ -501,6 +507,8 @@ struct pmic_wrapper;
+ struct pwrap_slv_type {
+       const u32 *dew_regs;
+       enum pmic_type type;
++      /* Flags indicating the capability for the target slave */
++      u32 caps;
+       /*
+        * pwrap operations are highly associated with the PMIC types,
+        * so the pointers added increases flexibility allowing determination
+@@ -787,6 +795,37 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp)
+       return 0;
+ }
++static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
++{
++      int ret;
++      u32 rdata;
++
++      /* Enable dual IO mode */
++      pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
++
++      /* Check IDLE & INIT_DONE in advance */
++      ret = pwrap_wait_for_state(wrp,
++                                 pwrap_is_fsm_idle_and_sync_idle);
++      if (ret) {
++              dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
++              return ret;
++      }
++
++      pwrap_writel(wrp, 1, PWRAP_DIO_EN);
++
++      /* Read Test */
++      pwrap_read(wrp,
++                 wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
++      if (rdata != PWRAP_DEW_READ_TEST_VAL) {
++              dev_err(wrp->dev,
++                      "Read failed on DIO mode: 0x%04x!=0x%04x\n",
++                      PWRAP_DEW_READ_TEST_VAL, rdata);
++              return -EFAULT;
++      }
++
++      return 0;
++}
++
+ static int pwrap_mt8135_init_reg_clock(struct pmic_wrapper *wrp)
+ {
+       pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
+@@ -935,6 +974,30 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
+       return 0;
+ }
++static int pwrap_init_security(struct pmic_wrapper *wrp)
++{
++      int ret;
++
++      /* Enable encryption */
++      ret = pwrap_init_cipher(wrp);
++      if (ret)
++              return ret;
++
++      /* Signature checking - using CRC */
++      if (pwrap_write(wrp,
++                      wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
++              return -EFAULT;
++
++      pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
++      pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
++      pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
++                   PWRAP_SIG_ADR);
++      pwrap_writel(wrp,
++                   wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
++
++      return 0;
++}
++
+ static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
+ {
+       /* enable pwrap events and pwrap bridge in AP side */
+@@ -995,7 +1058,6 @@ static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
+ static int pwrap_init(struct pmic_wrapper *wrp)
+ {
+       int ret;
+-      u32 rdata;
+       reset_control_reset(wrp->rstc);
+       if (wrp->rstc_bridge)
+@@ -1007,10 +1069,12 @@ static int pwrap_init(struct pmic_wrapper *wrp)
+               pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
+       }
+-      /* Reset SPI slave */
+-      ret = pwrap_reset_spislave(wrp);
+-      if (ret)
+-              return ret;
++      if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
++              /* Reset SPI slave */
++              ret = pwrap_reset_spislave(wrp);
++              if (ret)
++                      return ret;
++      }
+       pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
+@@ -1022,45 +1086,26 @@ static int pwrap_init(struct pmic_wrapper *wrp)
+       if (ret)
+               return ret;
+-      /* Setup serial input delay */
+-      ret = pwrap_init_sidly(wrp);
+-      if (ret)
+-              return ret;
+-
+-      /* Enable dual IO mode */
+-      pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
+-
+-      /* Check IDLE & INIT_DONE in advance */
+-      ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
+-      if (ret) {
+-              dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
+-              return ret;
++      if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
++              /* Setup serial input delay */
++              ret = pwrap_init_sidly(wrp);
++              if (ret)
++                      return ret;
+       }
+-      pwrap_writel(wrp, 1, PWRAP_DIO_EN);
+-
+-      /* Read Test */
+-      pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
+-      if (rdata != PWRAP_DEW_READ_TEST_VAL) {
+-              dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
+-                              PWRAP_DEW_READ_TEST_VAL, rdata);
+-              return -EFAULT;
++      if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
++              /* Enable dual I/O mode */
++              ret = pwrap_init_dual_io(wrp);
++              if (ret)
++                      return ret;
+       }
+-      /* Enable encryption */
+-      ret = pwrap_init_cipher(wrp);
+-      if (ret)
+-              return ret;
+-
+-      /* Signature checking - using CRC */
+-      if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
+-              return -EFAULT;
+-
+-      pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
+-      pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
+-      pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
+-                   PWRAP_SIG_ADR);
+-      pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
++      if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
++              /* Enable security on bus */
++              ret = pwrap_init_security(wrp);
++              if (ret)
++                      return ret;
++      }
+       if (wrp->master->type == PWRAP_MT8135)
+               pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
+@@ -1116,6 +1161,8 @@ static const struct regmap_config pwrap_regmap_config = {
+ static const struct pwrap_slv_type pmic_mt6323 = {
+       .dew_regs = mt6323_regs,
+       .type = PMIC_MT6323,
++      .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
++              PWRAP_SLV_CAP_SECURITY,
+       .pwrap_read = pwrap_read16,
+       .pwrap_write = pwrap_write16,
+ };
+@@ -1123,6 +1170,7 @@ static const struct pwrap_slv_type pmic_mt6323 = {
+ static const struct pwrap_slv_type pmic_mt6380 = {
+       .dew_regs = NULL,
+       .type = PMIC_MT6380,
++      .caps = 0,
+       .pwrap_read = pwrap_read32,
+       .pwrap_write = pwrap_write32,
+ };
+@@ -1130,6 +1178,8 @@ static const struct pwrap_slv_type pmic_mt6380 = {
+ static const struct pwrap_slv_type pmic_mt6397 = {
+       .dew_regs = mt6397_regs,
+       .type = PMIC_MT6397,
++      .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
++              PWRAP_SLV_CAP_SECURITY,
+       .pwrap_read = pwrap_read16,
+       .pwrap_write = pwrap_write16,
+ };
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0120-soc-mediatek-pwrap-add-MediaTek-MT6380-as-one-slave-.patch b/target/linux/mediatek/patches-4.14/0120-soc-mediatek-pwrap-add-MediaTek-MT6380-as-one-slave-.patch
new file mode 100644 (file)
index 0000000..532c42c
--- /dev/null
@@ -0,0 +1,103 @@
+From 81c54afc5bc918ea3ed65cc356236b302b1f21ca Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Wed, 18 Oct 2017 16:28:46 +0800
+Subject: [PATCH 120/224] soc: mediatek: pwrap: add MediaTek MT6380 as one
+ slave of pwrap
+
+Add MediaTek MT6380 regulator becoming one of PMIC wrapper slave
+and also add extra new regmap_config of 32-bit mode for MT6380
+since old regmap_config of 16-bit mode can't be fit into the need.
+
+Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com>
+Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ drivers/soc/mediatek/mtk-pmic-wrap.c | 24 +++++++++++++++++++++---
+ 1 file changed, 21 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index e3398e37a7a6..45c3e44d8f40 100644
+--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
++++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
+@@ -507,6 +507,7 @@ struct pmic_wrapper;
+ struct pwrap_slv_type {
+       const u32 *dew_regs;
+       enum pmic_type type;
++      const struct regmap_config *regmap;
+       /* Flags indicating the capability for the target slave */
+       u32 caps;
+       /*
+@@ -1149,7 +1150,7 @@ static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
+       return IRQ_HANDLED;
+ }
+-static const struct regmap_config pwrap_regmap_config = {
++static const struct regmap_config pwrap_regmap_config16 = {
+       .reg_bits = 16,
+       .val_bits = 16,
+       .reg_stride = 2,
+@@ -1158,9 +1159,19 @@ static const struct regmap_config pwrap_regmap_config = {
+       .max_register = 0xffff,
+ };
++static const struct regmap_config pwrap_regmap_config32 = {
++      .reg_bits = 32,
++      .val_bits = 32,
++      .reg_stride = 4,
++      .reg_read = pwrap_regmap_read,
++      .reg_write = pwrap_regmap_write,
++      .max_register = 0xffff,
++};
++
+ static const struct pwrap_slv_type pmic_mt6323 = {
+       .dew_regs = mt6323_regs,
+       .type = PMIC_MT6323,
++      .regmap = &pwrap_regmap_config16,
+       .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
+               PWRAP_SLV_CAP_SECURITY,
+       .pwrap_read = pwrap_read16,
+@@ -1170,6 +1181,7 @@ static const struct pwrap_slv_type pmic_mt6323 = {
+ static const struct pwrap_slv_type pmic_mt6380 = {
+       .dew_regs = NULL,
+       .type = PMIC_MT6380,
++      .regmap = &pwrap_regmap_config32,
+       .caps = 0,
+       .pwrap_read = pwrap_read32,
+       .pwrap_write = pwrap_write32,
+@@ -1178,6 +1190,7 @@ static const struct pwrap_slv_type pmic_mt6380 = {
+ static const struct pwrap_slv_type pmic_mt6397 = {
+       .dew_regs = mt6397_regs,
+       .type = PMIC_MT6397,
++      .regmap = &pwrap_regmap_config16,
+       .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
+               PWRAP_SLV_CAP_SECURITY,
+       .pwrap_read = pwrap_read16,
+@@ -1189,9 +1202,14 @@ static const struct of_device_id of_slave_match_tbl[] = {
+               .compatible = "mediatek,mt6323",
+               .data = &pmic_mt6323,
+       }, {
++              /* The MT6380 PMIC only implements a regulator, so we bind it
++               * directly instead of using a MFD.
++               */
++              .compatible = "mediatek,mt6380-regulator",
++              .data = &pmic_mt6380,
++      }, {
+               .compatible = "mediatek,mt6397",
+               .data = &pmic_mt6397,
+-      }, {
+               /* sentinel */
+       }
+ };
+@@ -1372,7 +1390,7 @@ static int pwrap_probe(struct platform_device *pdev)
+       if (ret)
+               goto err_out2;
+-      wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, &pwrap_regmap_config);
++      wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap);
+       if (IS_ERR(wrp->regmap)) {
+               ret = PTR_ERR(wrp->regmap);
+               goto err_out2;
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0121-soc-mediatek-pwrap-add-common-way-for-setup-CS-timin.patch b/target/linux/mediatek/patches-4.14/0121-soc-mediatek-pwrap-add-common-way-for-setup-CS-timin.patch
new file mode 100644 (file)
index 0000000..cab2178
--- /dev/null
@@ -0,0 +1,124 @@
+From 442c890727e0f585154662b0908fbe3a7986052a Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Wed, 18 Oct 2017 16:28:47 +0800
+Subject: [PATCH 121/224] soc: mediatek: pwrap: add common way for setup CS
+ timing extenstion
+
+Multiple platforms would always use their own way handling CS timing
+extension on the bus which leads to a little bit code duplication.
+Therefore, the patch groups the similar logic to handle CS timing
+extension into the common function which allows the following SoCs
+have more reusability for configing CS timing.
+
+Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com>
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ drivers/soc/mediatek/mtk-pmic-wrap.c | 59 ++++++++++++++++++++++--------------
+ 1 file changed, 37 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 45c3e44d8f40..cbc3f0e82337 100644
+--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
++++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
+@@ -827,23 +827,44 @@ static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
+       return 0;
+ }
+-static int pwrap_mt8135_init_reg_clock(struct pmic_wrapper *wrp)
++/*
++ * pwrap_init_chip_select_ext is used to configure CS extension time for each
++ * phase during data transactions on the pwrap bus.
++ */
++static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
++                                     u8 hext_read, u8 lext_start,
++                                     u8 lext_end)
+ {
+-      pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
+-      pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
+-      pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
+-      pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
+-      pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
++      /*
++       * After finishing a write and read transaction, extends CS high time
++       * to be at least xT of BUS CLK as hext_write and hext_read specifies
++       * respectively.
++       */
++      pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
++      pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
+-      return 0;
++      /*
++       * Extends CS low time after CSL and before CSH command to be at
++       * least xT of BUS CLK as lext_start and lext_end specifies
++       * respectively.
++       */
++      pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
++      pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
+ }
+-static int pwrap_mt8173_init_reg_clock(struct pmic_wrapper *wrp)
++static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
+ {
+-      pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
+-      pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
+-      pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
+-      pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
++      switch (wrp->master->type) {
++      case PWRAP_MT8173:
++              pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
++              break;
++      case PWRAP_MT8135:
++              pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
++              pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
++              break;
++      default:
++              break;
++      }
+       return 0;
+ }
+@@ -853,20 +874,14 @@ static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
+       switch (wrp->slave->type) {
+       case PMIC_MT6397:
+               pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
+-              pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_WRITE);
+-              pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
+-              pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
+-              pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
++              pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
+               break;
+       case PMIC_MT6323:
+               pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
+               pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
+                           0x8);
+-              pwrap_writel(wrp, 0x5, PWRAP_CSHEXT_WRITE);
+-              pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
+-              pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
+-              pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
++              pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
+               break;
+       default:
+               break;
+@@ -1235,7 +1250,7 @@ static const struct pmic_wrapper_type pwrap_mt8135 = {
+       .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
+       .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
+       .has_bridge = 1,
+-      .init_reg_clock = pwrap_mt8135_init_reg_clock,
++      .init_reg_clock = pwrap_common_init_reg_clock,
+       .init_soc_specific = pwrap_mt8135_init_soc_specific,
+ };
+@@ -1247,7 +1262,7 @@ static const struct pmic_wrapper_type pwrap_mt8173 = {
+       .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
+       .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
+       .has_bridge = 0,
+-      .init_reg_clock = pwrap_mt8173_init_reg_clock,
++      .init_reg_clock = pwrap_common_init_reg_clock,
+       .init_soc_specific = pwrap_mt8173_init_soc_specific,
+ };
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0122-soc-mediatek-pwrap-add-support-for-MT7622-SoC.patch b/target/linux/mediatek/patches-4.14/0122-soc-mediatek-pwrap-add-support-for-MT7622-SoC.patch
new file mode 100644 (file)
index 0000000..6556444
--- /dev/null
@@ -0,0 +1,242 @@
+From 87996dabef0d83bbd2ed5264b83b01224bc42968 Mon Sep 17 00:00:00 2001
+From: Chenglin Xu <chenglin.xu@mediatek.com>
+Date: Wed, 18 Oct 2017 16:28:48 +0800
+Subject: [PATCH 122/224] soc: mediatek: pwrap: add support for MT7622 SoC
+
+Add the registers, callbacks and data structures required to make the
+PMIC wrapper work on MT7622.
+
+Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com>
+Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ drivers/soc/mediatek/mtk-pmic-wrap.c | 170 +++++++++++++++++++++++++++++++++++
+ 1 file changed, 170 insertions(+)
+
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index cbc3f0e82337..5d61d127e1d7 100644
+--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
++++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
+@@ -214,6 +214,36 @@ enum pwrap_regs {
+       PWRAP_ADC_RDATA_ADDR1,
+       PWRAP_ADC_RDATA_ADDR2,
++      /* MT7622 only regs */
++      PWRAP_EINT_STA0_ADR,
++      PWRAP_EINT_STA1_ADR,
++      PWRAP_STA,
++      PWRAP_CLR,
++      PWRAP_DVFS_ADR8,
++      PWRAP_DVFS_WDATA8,
++      PWRAP_DVFS_ADR9,
++      PWRAP_DVFS_WDATA9,
++      PWRAP_DVFS_ADR10,
++      PWRAP_DVFS_WDATA10,
++      PWRAP_DVFS_ADR11,
++      PWRAP_DVFS_WDATA11,
++      PWRAP_DVFS_ADR12,
++      PWRAP_DVFS_WDATA12,
++      PWRAP_DVFS_ADR13,
++      PWRAP_DVFS_WDATA13,
++      PWRAP_DVFS_ADR14,
++      PWRAP_DVFS_WDATA14,
++      PWRAP_DVFS_ADR15,
++      PWRAP_DVFS_WDATA15,
++      PWRAP_EXT_CK,
++      PWRAP_ADC_RDATA_ADDR,
++      PWRAP_GPS_STA,
++      PWRAP_SW_RST,
++      PWRAP_DVFS_STEP_CTRL0,
++      PWRAP_DVFS_STEP_CTRL1,
++      PWRAP_DVFS_STEP_CTRL2,
++      PWRAP_SPI2_CTRL,
++
+       /* MT8135 only regs */
+       PWRAP_CSHEXT,
+       PWRAP_EVENT_IN_EN,
+@@ -336,6 +366,118 @@ static int mt2701_regs[] = {
+       [PWRAP_ADC_RDATA_ADDR2] =       0x154,
+ };
++static int mt7622_regs[] = {
++      [PWRAP_MUX_SEL] =               0x0,
++      [PWRAP_WRAP_EN] =               0x4,
++      [PWRAP_DIO_EN] =                0x8,
++      [PWRAP_SIDLY] =                 0xC,
++      [PWRAP_RDDMY] =                 0x10,
++      [PWRAP_SI_CK_CON] =             0x14,
++      [PWRAP_CSHEXT_WRITE] =          0x18,
++      [PWRAP_CSHEXT_READ] =           0x1C,
++      [PWRAP_CSLEXT_START] =          0x20,
++      [PWRAP_CSLEXT_END] =            0x24,
++      [PWRAP_STAUPD_PRD] =            0x28,
++      [PWRAP_STAUPD_GRPEN] =          0x2C,
++      [PWRAP_EINT_STA0_ADR] =         0x30,
++      [PWRAP_EINT_STA1_ADR] =         0x34,
++      [PWRAP_STA] =                   0x38,
++      [PWRAP_CLR] =                   0x3C,
++      [PWRAP_STAUPD_MAN_TRIG] =       0x40,
++      [PWRAP_STAUPD_STA] =            0x44,
++      [PWRAP_WRAP_STA] =              0x48,
++      [PWRAP_HARB_INIT] =             0x4C,
++      [PWRAP_HARB_HPRIO] =            0x50,
++      [PWRAP_HIPRIO_ARB_EN] =         0x54,
++      [PWRAP_HARB_STA0] =             0x58,
++      [PWRAP_HARB_STA1] =             0x5C,
++      [PWRAP_MAN_EN] =                0x60,
++      [PWRAP_MAN_CMD] =               0x64,
++      [PWRAP_MAN_RDATA] =             0x68,
++      [PWRAP_MAN_VLDCLR] =            0x6C,
++      [PWRAP_WACS0_EN] =              0x70,
++      [PWRAP_INIT_DONE0] =            0x74,
++      [PWRAP_WACS0_CMD] =             0x78,
++      [PWRAP_WACS0_RDATA] =           0x7C,
++      [PWRAP_WACS0_VLDCLR] =          0x80,
++      [PWRAP_WACS1_EN] =              0x84,
++      [PWRAP_INIT_DONE1] =            0x88,
++      [PWRAP_WACS1_CMD] =             0x8C,
++      [PWRAP_WACS1_RDATA] =           0x90,
++      [PWRAP_WACS1_VLDCLR] =          0x94,
++      [PWRAP_WACS2_EN] =              0x98,
++      [PWRAP_INIT_DONE2] =            0x9C,
++      [PWRAP_WACS2_CMD] =             0xA0,
++      [PWRAP_WACS2_RDATA] =           0xA4,
++      [PWRAP_WACS2_VLDCLR] =          0xA8,
++      [PWRAP_INT_EN] =                0xAC,
++      [PWRAP_INT_FLG_RAW] =           0xB0,
++      [PWRAP_INT_FLG] =               0xB4,
++      [PWRAP_INT_CLR] =               0xB8,
++      [PWRAP_SIG_ADR] =               0xBC,
++      [PWRAP_SIG_MODE] =              0xC0,
++      [PWRAP_SIG_VALUE] =             0xC4,
++      [PWRAP_SIG_ERRVAL] =            0xC8,
++      [PWRAP_CRC_EN] =                0xCC,
++      [PWRAP_TIMER_EN] =              0xD0,
++      [PWRAP_TIMER_STA] =             0xD4,
++      [PWRAP_WDT_UNIT] =              0xD8,
++      [PWRAP_WDT_SRC_EN] =            0xDC,
++      [PWRAP_WDT_FLG] =               0xE0,
++      [PWRAP_DEBUG_INT_SEL] =         0xE4,
++      [PWRAP_DVFS_ADR0] =             0xE8,
++      [PWRAP_DVFS_WDATA0] =           0xEC,
++      [PWRAP_DVFS_ADR1] =             0xF0,
++      [PWRAP_DVFS_WDATA1] =           0xF4,
++      [PWRAP_DVFS_ADR2] =             0xF8,
++      [PWRAP_DVFS_WDATA2] =           0xFC,
++      [PWRAP_DVFS_ADR3] =             0x100,
++      [PWRAP_DVFS_WDATA3] =           0x104,
++      [PWRAP_DVFS_ADR4] =             0x108,
++      [PWRAP_DVFS_WDATA4] =           0x10C,
++      [PWRAP_DVFS_ADR5] =             0x110,
++      [PWRAP_DVFS_WDATA5] =           0x114,
++      [PWRAP_DVFS_ADR6] =             0x118,
++      [PWRAP_DVFS_WDATA6] =           0x11C,
++      [PWRAP_DVFS_ADR7] =             0x120,
++      [PWRAP_DVFS_WDATA7] =           0x124,
++      [PWRAP_DVFS_ADR8] =             0x128,
++      [PWRAP_DVFS_WDATA8] =           0x12C,
++      [PWRAP_DVFS_ADR9] =             0x130,
++      [PWRAP_DVFS_WDATA9] =           0x134,
++      [PWRAP_DVFS_ADR10] =            0x138,
++      [PWRAP_DVFS_WDATA10] =          0x13C,
++      [PWRAP_DVFS_ADR11] =            0x140,
++      [PWRAP_DVFS_WDATA11] =          0x144,
++      [PWRAP_DVFS_ADR12] =            0x148,
++      [PWRAP_DVFS_WDATA12] =          0x14C,
++      [PWRAP_DVFS_ADR13] =            0x150,
++      [PWRAP_DVFS_WDATA13] =          0x154,
++      [PWRAP_DVFS_ADR14] =            0x158,
++      [PWRAP_DVFS_WDATA14] =          0x15C,
++      [PWRAP_DVFS_ADR15] =            0x160,
++      [PWRAP_DVFS_WDATA15] =          0x164,
++      [PWRAP_SPMINF_STA] =            0x168,
++      [PWRAP_CIPHER_KEY_SEL] =        0x16C,
++      [PWRAP_CIPHER_IV_SEL] =         0x170,
++      [PWRAP_CIPHER_EN] =             0x174,
++      [PWRAP_CIPHER_RDY] =            0x178,
++      [PWRAP_CIPHER_MODE] =           0x17C,
++      [PWRAP_CIPHER_SWRST] =          0x180,
++      [PWRAP_DCM_EN] =                0x184,
++      [PWRAP_DCM_DBC_PRD] =           0x188,
++      [PWRAP_EXT_CK] =                0x18C,
++      [PWRAP_ADC_CMD_ADDR] =          0x190,
++      [PWRAP_PWRAP_ADC_CMD] =         0x194,
++      [PWRAP_ADC_RDATA_ADDR] =        0x198,
++      [PWRAP_GPS_STA] =               0x19C,
++      [PWRAP_SW_RST] =                0x1A0,
++      [PWRAP_DVFS_STEP_CTRL0] =       0x238,
++      [PWRAP_DVFS_STEP_CTRL1] =       0x23C,
++      [PWRAP_DVFS_STEP_CTRL2] =       0x240,
++      [PWRAP_SPI2_CTRL] =             0x244,
++};
++
+ static int mt8173_regs[] = {
+       [PWRAP_MUX_SEL] =               0x0,
+       [PWRAP_WRAP_EN] =               0x4,
+@@ -499,6 +641,7 @@ enum pmic_type {
+ enum pwrap_type {
+       PWRAP_MT2701,
++      PWRAP_MT7622,
+       PWRAP_MT8135,
+       PWRAP_MT8173,
+ };
+@@ -927,6 +1070,9 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
+       case PWRAP_MT8173:
+               pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
+               break;
++      case PWRAP_MT7622:
++              pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
++              break;
+       }
+       /* Config cipher mode @PMIC */
+@@ -1071,6 +1217,15 @@ static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
+       return 0;
+ }
++static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
++{
++      pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
++      /* enable 2wire SPI master */
++      pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
++
++      return 0;
++}
++
+ static int pwrap_init(struct pmic_wrapper *wrp)
+ {
+       int ret;
+@@ -1242,6 +1397,18 @@ static const struct pmic_wrapper_type pwrap_mt2701 = {
+       .init_soc_specific = pwrap_mt2701_init_soc_specific,
+ };
++static const struct pmic_wrapper_type pwrap_mt7622 = {
++      .regs = mt7622_regs,
++      .type = PWRAP_MT7622,
++      .arb_en_all = 0xff,
++      .int_en_all = ~(u32)BIT(31),
++      .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
++      .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
++      .has_bridge = 0,
++      .init_reg_clock = pwrap_common_init_reg_clock,
++      .init_soc_specific = pwrap_mt7622_init_soc_specific,
++};
++
+ static const struct pmic_wrapper_type pwrap_mt8135 = {
+       .regs = mt8135_regs,
+       .type = PWRAP_MT8135,
+@@ -1271,6 +1438,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
+               .compatible = "mediatek,mt2701-pwrap",
+               .data = &pwrap_mt2701,
+       }, {
++              .compatible = "mediatek,mt7622-pwrap",
++              .data = &pwrap_mt7622,
++      }, {
+               .compatible = "mediatek,mt8135-pwrap",
+               .data = &pwrap_mt8135,
+       }, {
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0123-soc-mediatek-place-Kconfig-for-all-SoC-drivers-under.patch b/target/linux/mediatek/patches-4.14/0123-soc-mediatek-place-Kconfig-for-all-SoC-drivers-under.patch
new file mode 100644 (file)
index 0000000..4735f84
--- /dev/null
@@ -0,0 +1,62 @@
+From 21501b17e017cb10f1a64a73e62e3e2e91a52efa Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Thu, 5 Oct 2017 11:17:49 +0800
+Subject: [PATCH 123/224] soc: mediatek: place Kconfig for all SoC drivers
+ under menu
+
+Add cleanup for placing all Kconfig for all MediaTek SoC drivers under
+the independent menu as other SoCs vendor usually did. Since the menu
+would be shown depending on "ARCH_MEDIATEK || COMPILE_TEST" selected and
+MTK_PMIC_WRAP is still safe compiling with the case of "COMPILE_TEST"
+only, the superfluous dependency for those items under the menu also is
+also being removed for the sake of simplicity.
+
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Reviewed-by: Jean Delvare <jdelvare@suse.de>
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ drivers/soc/mediatek/Kconfig | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
+index 609bb3424c14..a7d0667338f2 100644
+--- a/drivers/soc/mediatek/Kconfig
++++ b/drivers/soc/mediatek/Kconfig
+@@ -1,9 +1,11 @@
+ #
+ # MediaTek SoC drivers
+ #
++menu "MediaTek SoC drivers"
++      depends on ARCH_MEDIATEK || COMPILE_TEST
++
+ config MTK_INFRACFG
+       bool "MediaTek INFRACFG Support"
+-      depends on ARCH_MEDIATEK || COMPILE_TEST
+       select REGMAP
+       help
+         Say yes here to add support for the MediaTek INFRACFG controller. The
+@@ -12,7 +14,6 @@ config MTK_INFRACFG
+ config MTK_PMIC_WRAP
+       tristate "MediaTek PMIC Wrapper Support"
+-      depends on ARCH_MEDIATEK
+       depends on RESET_CONTROLLER
+       select REGMAP
+       help
+@@ -22,7 +23,6 @@ config MTK_PMIC_WRAP
+ config MTK_SCPSYS
+       bool "MediaTek SCPSYS Support"
+-      depends on ARCH_MEDIATEK || COMPILE_TEST
+       default ARCH_MEDIATEK
+       select REGMAP
+       select MTK_INFRACFG
+@@ -30,3 +30,5 @@ config MTK_SCPSYS
+       help
+         Say yes here to add support for the MediaTek SCPSYS power domain
+         driver.
++
++endmenu
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0124-arm64-mediatek-cleanup-message-for-platform-selectio.patch b/target/linux/mediatek/patches-4.14/0124-arm64-mediatek-cleanup-message-for-platform-selectio.patch
new file mode 100644 (file)
index 0000000..0e7fa9c
--- /dev/null
@@ -0,0 +1,39 @@
+From f9bea440dd8dbf1eda8644e4b1d76503053f17b6 Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Thu, 19 Oct 2017 17:52:54 +0800
+Subject: [PATCH 124/224] arm64: mediatek: cleanup message for platform
+ selection
+
+The latest kernel tree already can support more MediaTek platforms such as
+MT2712 and MT7622, so additional descriptions for those platforms are added
+and certain cleanups are also being made here.
+
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/Kconfig.platforms | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
+index 6b54ee8c1262..ab69f5fce261 100644
+--- a/arch/arm64/Kconfig.platforms
++++ b/arch/arm64/Kconfig.platforms
+@@ -91,12 +91,13 @@ config ARCH_HISI
+         This enables support for Hisilicon ARMv8 SoC family
+ config ARCH_MEDIATEK
+-      bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
++      bool "MediaTek SoC Family"
+       select ARM_GIC
+       select PINCTRL
+       select MTK_TIMER
+       help
+-        Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
++        This enables support for MediaTek MT27xx, MT65xx, MT76xx
++        & MT81xx ARMv8 SoCs
+ config ARCH_MESON
+       bool "Amlogic Platforms"
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0125-phy-phy-mtk-tphy-add-set_mode-callback.patch b/target/linux/mediatek/patches-4.14/0125-phy-phy-mtk-tphy-add-set_mode-callback.patch
new file mode 100644 (file)
index 0000000..75b3908
--- /dev/null
@@ -0,0 +1,91 @@
+From d42ebed1aa669c5a897ec0aa5e1ede8d9069894a Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Thu, 21 Sep 2017 18:31:49 +0800
+Subject: [PATCH 125/224] phy: phy-mtk-tphy: add set_mode callback
+
+This is used to force PHY with USB OTG function to enter a specific
+mode, and override OTG IDPIN(or IDDIG) signal.
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+---
+ drivers/phy/mediatek/phy-mtk-tphy.c | 39 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 39 insertions(+)
+
+diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
+index 721a2a1c97ef..402385f2562a 100644
+--- a/drivers/phy/mediatek/phy-mtk-tphy.c
++++ b/drivers/phy/mediatek/phy-mtk-tphy.c
+@@ -96,9 +96,11 @@
+ #define U3P_U2PHYDTM1         0x06C
+ #define P2C_RG_UART_EN                        BIT(16)
++#define P2C_FORCE_IDDIG               BIT(9)
+ #define P2C_RG_VBUSVALID              BIT(5)
+ #define P2C_RG_SESSEND                        BIT(4)
+ #define P2C_RG_AVALID                 BIT(2)
++#define P2C_RG_IDDIG                  BIT(1)
+ #define U3P_U3_CHIP_GPIO_CTLD         0x0c
+ #define P3C_REG_IP_SW_RST             BIT(31)
+@@ -585,6 +587,31 @@ static void u2_phy_instance_exit(struct mtk_tphy *tphy,
+       }
+ }
++static void u2_phy_instance_set_mode(struct mtk_tphy *tphy,
++                                   struct mtk_phy_instance *instance,
++                                   enum phy_mode mode)
++{
++      struct u2phy_banks *u2_banks = &instance->u2_banks;
++      u32 tmp;
++
++      tmp = readl(u2_banks->com + U3P_U2PHYDTM1);
++      switch (mode) {
++      case PHY_MODE_USB_DEVICE:
++              tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG;
++              break;
++      case PHY_MODE_USB_HOST:
++              tmp |= P2C_FORCE_IDDIG;
++              tmp &= ~P2C_RG_IDDIG;
++              break;
++      case PHY_MODE_USB_OTG:
++              tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG);
++              break;
++      default:
++              return;
++      }
++      writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
++}
++
+ static void pcie_phy_instance_init(struct mtk_tphy *tphy,
+       struct mtk_phy_instance *instance)
+ {
+@@ -881,6 +908,17 @@ static int mtk_phy_exit(struct phy *phy)
+       return 0;
+ }
++static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode)
++{
++      struct mtk_phy_instance *instance = phy_get_drvdata(phy);
++      struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
++
++      if (instance->type == PHY_TYPE_USB2)
++              u2_phy_instance_set_mode(tphy, instance, mode);
++
++      return 0;
++}
++
+ static struct phy *mtk_phy_xlate(struct device *dev,
+                                       struct of_phandle_args *args)
+ {
+@@ -931,6 +969,7 @@ static const struct phy_ops mtk_tphy_ops = {
+       .exit           = mtk_phy_exit,
+       .power_on       = mtk_phy_power_on,
+       .power_off      = mtk_phy_power_off,
++      .set_mode       = mtk_phy_set_mode,
+       .owner          = THIS_MODULE,
+ };
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0126-usb-xhci-mtk-use-dma_set_mask_and_coherent-in-probe-.patch b/target/linux/mediatek/patches-4.14/0126-usb-xhci-mtk-use-dma_set_mask_and_coherent-in-probe-.patch
new file mode 100644 (file)
index 0000000..70ed474
--- /dev/null
@@ -0,0 +1,40 @@
+From 9f617ce19c5dab429a539d411204ae220b5b8cd6 Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 16:26:33 +0800
+Subject: [PATCH 126/224] usb: xhci-mtk: use dma_set_mask_and_coherent() in
+ probe function
+
+This patch uses the simpler dma_set_mask_and_coherent() instead of
+doing these as separate steps
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/usb/host/xhci-mtk.c | 7 +------
+ 1 file changed, 1 insertion(+), 6 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
+index 8fb60657ed4f..c197a6d9e157 100644
+--- a/drivers/usb/host/xhci-mtk.c
++++ b/drivers/usb/host/xhci-mtk.c
+@@ -606,15 +606,10 @@ static int xhci_mtk_probe(struct platform_device *pdev)
+       }
+       /* Initialize dma_mask and coherent_dma_mask to 32-bits */
+-      ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
++      ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
+       if (ret)
+               goto disable_clk;
+-      if (!dev->dma_mask)
+-              dev->dma_mask = &dev->coherent_dma_mask;
+-      else
+-              dma_set_mask(dev, DMA_BIT_MASK(32));
+-
+       hcd = usb_create_hcd(driver, dev, dev_name(dev));
+       if (!hcd) {
+               ret = -ENOMEM;
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0127-usb-xhci-mtk-use-ports-count-from-xhci-in-xhci_mtk_s.patch b/target/linux/mediatek/patches-4.14/0127-usb-xhci-mtk-use-ports-count-from-xhci-in-xhci_mtk_s.patch
new file mode 100644 (file)
index 0000000..67fc84e
--- /dev/null
@@ -0,0 +1,60 @@
+From f97aa71fe34135e7fc8da6231e61ee06f79d739d Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 16:26:34 +0800
+Subject: [PATCH 127/224] usb: xhci-mtk: use ports count from xhci in
+ xhci_mtk_sch_init()
+
+Make use of ports count from xhci but not from ippc in
+xhci_mtk_sch_init()
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/usb/host/xhci-mtk-sch.c | 3 ++-
+ drivers/usb/host/xhci-mtk.c     | 3 ---
+ 2 files changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-mtk-sch.c b/drivers/usb/host/xhci-mtk-sch.c
+index 6e7ddf6cafae..bfc51bc902b8 100644
+--- a/drivers/usb/host/xhci-mtk-sch.c
++++ b/drivers/usb/host/xhci-mtk-sch.c
+@@ -287,12 +287,13 @@ static bool need_bw_sch(struct usb_host_endpoint *ep,
+ int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk)
+ {
++      struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
+       struct mu3h_sch_bw_info *sch_array;
+       int num_usb_bus;
+       int i;
+       /* ss IN and OUT are separated */
+-      num_usb_bus = mtk->num_u3_ports * 2 + mtk->num_u2_ports;
++      num_usb_bus = xhci->num_usb3_ports * 2 + xhci->num_usb2_ports;
+       sch_array = kcalloc(num_usb_bus, sizeof(*sch_array), GFP_KERNEL);
+       if (sch_array == NULL)
+diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
+index c197a6d9e157..9502ca408f01 100644
+--- a/drivers/usb/host/xhci-mtk.c
++++ b/drivers/usb/host/xhci-mtk.c
+@@ -492,7 +492,6 @@ static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
+ /* called during probe() after chip reset completes */
+ static int xhci_mtk_setup(struct usb_hcd *hcd)
+ {
+-      struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+       struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
+       int ret;
+@@ -507,8 +506,6 @@ static int xhci_mtk_setup(struct usb_hcd *hcd)
+               return ret;
+       if (usb_hcd_is_primary_hcd(hcd)) {
+-              mtk->num_u3_ports = xhci->num_usb3_ports;
+-              mtk->num_u2_ports = xhci->num_usb2_ports;
+               ret = xhci_mtk_sch_init(mtk);
+               if (ret)
+                       return ret;
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0128-usb-xhci-mtk-check-clock-stability-of-U3_MAC.patch b/target/linux/mediatek/patches-4.14/0128-usb-xhci-mtk-check-clock-stability-of-U3_MAC.patch
new file mode 100644 (file)
index 0000000..d046574
--- /dev/null
@@ -0,0 +1,41 @@
+From 4422c4efeed2a8b9fa745c6e529623d89c0be75e Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 16:26:35 +0800
+Subject: [PATCH 128/224] usb: xhci-mtk: check clock stability of U3_MAC
+
+This is useful to find out the root cause when the Super Speed doesn't
+work. Such as when the T-PHY is switched to PCIe or SATA, and affects
+Super Speed function, the check will fail.
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/usb/host/xhci-mtk.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
+index 9502ca408f01..7a92bb782e5c 100644
+--- a/drivers/usb/host/xhci-mtk.c
++++ b/drivers/usb/host/xhci-mtk.c
+@@ -43,6 +43,7 @@
+ /* ip_pw_sts1 register */
+ #define STS1_IP_SLEEP_STS     BIT(30)
++#define STS1_U3_MAC_RST       BIT(16)
+ #define STS1_XHCI_RST         BIT(11)
+ #define STS1_SYS125_RST       BIT(10)
+ #define STS1_REF_RST          BIT(8)
+@@ -125,6 +126,9 @@ static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
+       check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
+                       STS1_SYS125_RST | STS1_XHCI_RST;
++      if (mtk->num_u3_ports)
++              check_val |= STS1_U3_MAC_RST;
++
+       ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
+                         (check_val == (value & check_val)), 100, 20000);
+       if (ret) {
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0129-usb-xhci-mtk-support-option-to-disable-usb3-ports.patch b/target/linux/mediatek/patches-4.14/0129-usb-xhci-mtk-support-option-to-disable-usb3-ports.patch
new file mode 100644 (file)
index 0000000..90e2aed
--- /dev/null
@@ -0,0 +1,92 @@
+From 13a1b2e927893cbb046a1ec5a55ec3516873a3f6 Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 16:26:36 +0800
+Subject: [PATCH 129/224] usb: xhci-mtk: support option to disable usb3 ports
+
+Add support to disable specific usb3 ports, it's useful when
+usb3 phy is shared with PCIe or SATA, because we should disable
+the corresponding usb3 port if the phy is used by PCIe or SATA.
+Sometimes it's helpful to analyse and solve problems.
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/usb/host/xhci-mtk.c | 18 +++++++++++++++---
+ drivers/usb/host/xhci-mtk.h |  1 +
+ 2 files changed, 16 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
+index 7a92bb782e5c..97ba51e4e149 100644
+--- a/drivers/usb/host/xhci-mtk.c
++++ b/drivers/usb/host/xhci-mtk.c
+@@ -92,6 +92,7 @@ static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
+ {
+       struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
+       u32 value, check_val;
++      int u3_ports_disabed = 0;
+       int ret;
+       int i;
+@@ -103,8 +104,13 @@ static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
+       value &= ~CTRL1_IP_HOST_PDN;
+       writel(value, &ippc->ip_pw_ctr1);
+-      /* power on and enable all u3 ports */
++      /* power on and enable u3 ports except skipped ones */
+       for (i = 0; i < mtk->num_u3_ports; i++) {
++              if ((0x1 << i) & mtk->u3p_dis_msk) {
++                      u3_ports_disabed++;
++                      continue;
++              }
++
+               value = readl(&ippc->u3_ctrl_p[i]);
+               value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
+               value |= CTRL_U3_PORT_HOST_SEL;
+@@ -126,7 +132,7 @@ static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
+       check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
+                       STS1_SYS125_RST | STS1_XHCI_RST;
+-      if (mtk->num_u3_ports)
++      if (mtk->num_u3_ports > u3_ports_disabed)
+               check_val |= STS1_U3_MAC_RST;
+       ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
+@@ -149,8 +155,11 @@ static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
+       if (!mtk->has_ippc)
+               return 0;
+-      /* power down all u3 ports */
++      /* power down u3 ports except skipped ones */
+       for (i = 0; i < mtk->num_u3_ports; i++) {
++              if ((0x1 << i) & mtk->u3p_dis_msk)
++                      continue;
++
+               value = readl(&ippc->u3_ctrl_p[i]);
+               value |= CTRL_U3_PORT_PDN;
+               writel(value, &ippc->u3_ctrl_p[i]);
+@@ -573,6 +582,9 @@ static int xhci_mtk_probe(struct platform_device *pdev)
+       }
+       mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
++      /* optional property, ignore the error if it does not exist */
++      of_property_read_u32(node, "mediatek,u3p-dis-msk",
++                           &mtk->u3p_dis_msk);
+       ret = usb_wakeup_of_property_parse(mtk, node);
+       if (ret)
+diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
+index 3aa5e1d25064..db55a12f1585 100644
+--- a/drivers/usb/host/xhci-mtk.h
++++ b/drivers/usb/host/xhci-mtk.h
+@@ -121,6 +121,7 @@ struct xhci_hcd_mtk {
+       bool has_ippc;
+       int num_u2_ports;
+       int num_u3_ports;
++      int u3p_dis_msk;
+       struct regulator *vusb33;
+       struct regulator *vbus;
+       struct clk *sys_clk;    /* sys and mac clock */
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0130-usb-xhci-mtk-remove-dummy-wakeup-debounce-clocks.patch b/target/linux/mediatek/patches-4.14/0130-usb-xhci-mtk-remove-dummy-wakeup-debounce-clocks.patch
new file mode 100644 (file)
index 0000000..cb595ff
--- /dev/null
@@ -0,0 +1,93 @@
+From 25adaf94e0fcbf6c1b47cb610edb7f5c23c53139 Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 16:26:37 +0800
+Subject: [PATCH 130/224] usb: xhci-mtk: remove dummy wakeup debounce clocks
+
+The wakeup debounce clocks for each ports in fact are not
+needed, so remove them.
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/usb/host/xhci-mtk.c | 33 ---------------------------------
+ drivers/usb/host/xhci-mtk.h |  2 --
+ 2 files changed, 35 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
+index 97ba51e4e149..d60463c07c54 100644
+--- a/drivers/usb/host/xhci-mtk.c
++++ b/drivers/usb/host/xhci-mtk.c
+@@ -237,25 +237,8 @@ static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
+               goto sys_clk_err;
+       }
+-      if (mtk->wakeup_src) {
+-              ret = clk_prepare_enable(mtk->wk_deb_p0);
+-              if (ret) {
+-                      dev_err(mtk->dev, "failed to enable wk_deb_p0\n");
+-                      goto usb_p0_err;
+-              }
+-
+-              ret = clk_prepare_enable(mtk->wk_deb_p1);
+-              if (ret) {
+-                      dev_err(mtk->dev, "failed to enable wk_deb_p1\n");
+-                      goto usb_p1_err;
+-              }
+-      }
+       return 0;
+-usb_p1_err:
+-      clk_disable_unprepare(mtk->wk_deb_p0);
+-usb_p0_err:
+-      clk_disable_unprepare(mtk->sys_clk);
+ sys_clk_err:
+       clk_disable_unprepare(mtk->ref_clk);
+ ref_clk_err:
+@@ -264,10 +247,6 @@ static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
+ static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
+ {
+-      if (mtk->wakeup_src) {
+-              clk_disable_unprepare(mtk->wk_deb_p1);
+-              clk_disable_unprepare(mtk->wk_deb_p0);
+-      }
+       clk_disable_unprepare(mtk->sys_clk);
+       clk_disable_unprepare(mtk->ref_clk);
+ }
+@@ -371,18 +350,6 @@ static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
+       if (!mtk->wakeup_src)
+               return 0;
+-      mtk->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0");
+-      if (IS_ERR(mtk->wk_deb_p0)) {
+-              dev_err(dev, "fail to get wakeup_deb_p0\n");
+-              return PTR_ERR(mtk->wk_deb_p0);
+-      }
+-
+-      mtk->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1");
+-      if (IS_ERR(mtk->wk_deb_p1)) {
+-              dev_err(dev, "fail to get wakeup_deb_p1\n");
+-              return PTR_ERR(mtk->wk_deb_p1);
+-      }
+-
+       mtk->pericfg = syscon_regmap_lookup_by_phandle(dn,
+                                               "mediatek,syscon-wakeup");
+       if (IS_ERR(mtk->pericfg)) {
+diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
+index db55a12f1585..67783a7af509 100644
+--- a/drivers/usb/host/xhci-mtk.h
++++ b/drivers/usb/host/xhci-mtk.h
+@@ -126,8 +126,6 @@ struct xhci_hcd_mtk {
+       struct regulator *vbus;
+       struct clk *sys_clk;    /* sys and mac clock */
+       struct clk *ref_clk;
+-      struct clk *wk_deb_p0;  /* port0's wakeup debounce clock */
+-      struct clk *wk_deb_p1;
+       struct regmap *pericfg;
+       struct phy **phys;
+       int num_phys;
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0131-usb-xhci-mtk-add-optional-mcu-and-dma-bus-clocks.patch b/target/linux/mediatek/patches-4.14/0131-usb-xhci-mtk-add-optional-mcu-and-dma-bus-clocks.patch
new file mode 100644 (file)
index 0000000..a533826
--- /dev/null
@@ -0,0 +1,146 @@
+From 9dce908d64ffb8b0ab71cb3a4b79db398d2e6dc3 Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 16:26:38 +0800
+Subject: [PATCH 131/224] usb: xhci-mtk: add optional mcu and dma bus clocks
+
+There are mcu_bus and dma_bus clocks needed to be controlled by
+driver on some SoCs, so add them as optional ones
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/usb/host/xhci-mtk.c | 79 ++++++++++++++++++++++++++++++++++-----------
+ drivers/usb/host/xhci-mtk.h |  2 ++
+ 2 files changed, 62 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
+index d60463c07c54..e5caabe7eebe 100644
+--- a/drivers/usb/host/xhci-mtk.c
++++ b/drivers/usb/host/xhci-mtk.c
+@@ -221,6 +221,44 @@ static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
+       return xhci_mtk_host_enable(mtk);
+ }
++/* ignore the error if the clock does not exist */
++static struct clk *optional_clk_get(struct device *dev, const char *id)
++{
++      struct clk *opt_clk;
++
++      opt_clk = devm_clk_get(dev, id);
++      /* ignore error number except EPROBE_DEFER */
++      if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER))
++              opt_clk = NULL;
++
++      return opt_clk;
++}
++
++static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
++{
++      struct device *dev = mtk->dev;
++
++      mtk->sys_clk = devm_clk_get(dev, "sys_ck");
++      if (IS_ERR(mtk->sys_clk)) {
++              dev_err(dev, "fail to get sys_ck\n");
++              return PTR_ERR(mtk->sys_clk);
++      }
++
++      mtk->ref_clk = optional_clk_get(dev, "ref_ck");
++      if (IS_ERR(mtk->ref_clk))
++              return PTR_ERR(mtk->ref_clk);
++
++      mtk->mcu_clk = optional_clk_get(dev, "mcu_ck");
++      if (IS_ERR(mtk->mcu_clk))
++              return PTR_ERR(mtk->mcu_clk);
++
++      mtk->dma_clk = optional_clk_get(dev, "dma_ck");
++      if (IS_ERR(mtk->dma_clk))
++              return PTR_ERR(mtk->dma_clk);
++
++      return 0;
++}
++
+ static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
+ {
+       int ret;
+@@ -237,16 +275,34 @@ static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
+               goto sys_clk_err;
+       }
++      ret = clk_prepare_enable(mtk->mcu_clk);
++      if (ret) {
++              dev_err(mtk->dev, "failed to enable mcu_clk\n");
++              goto mcu_clk_err;
++      }
++
++      ret = clk_prepare_enable(mtk->dma_clk);
++      if (ret) {
++              dev_err(mtk->dev, "failed to enable dma_clk\n");
++              goto dma_clk_err;
++      }
++
+       return 0;
++dma_clk_err:
++      clk_disable_unprepare(mtk->mcu_clk);
++mcu_clk_err:
++      clk_disable_unprepare(mtk->sys_clk);
+ sys_clk_err:
+       clk_disable_unprepare(mtk->ref_clk);
+ ref_clk_err:
+-      return -EINVAL;
++      return ret;
+ }
+ static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
+ {
++      clk_disable_unprepare(mtk->dma_clk);
++      clk_disable_unprepare(mtk->mcu_clk);
+       clk_disable_unprepare(mtk->sys_clk);
+       clk_disable_unprepare(mtk->ref_clk);
+ }
+@@ -529,24 +585,9 @@ static int xhci_mtk_probe(struct platform_device *pdev)
+               return PTR_ERR(mtk->vusb33);
+       }
+-      mtk->sys_clk = devm_clk_get(dev, "sys_ck");
+-      if (IS_ERR(mtk->sys_clk)) {
+-              dev_err(dev, "fail to get sys_ck\n");
+-              return PTR_ERR(mtk->sys_clk);
+-      }
+-
+-      /*
+-       * reference clock is usually a "fixed-clock", make it optional
+-       * for backward compatibility and ignore the error if it does
+-       * not exist.
+-       */
+-      mtk->ref_clk = devm_clk_get(dev, "ref_ck");
+-      if (IS_ERR(mtk->ref_clk)) {
+-              if (PTR_ERR(mtk->ref_clk) == -EPROBE_DEFER)
+-                      return -EPROBE_DEFER;
+-
+-              mtk->ref_clk = NULL;
+-      }
++      ret = xhci_mtk_clks_get(mtk);
++      if (ret)
++              return ret;
+       mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
+       /* optional property, ignore the error if it does not exist */
+diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
+index 67783a7af509..45ff5c67efb5 100644
+--- a/drivers/usb/host/xhci-mtk.h
++++ b/drivers/usb/host/xhci-mtk.h
+@@ -126,6 +126,8 @@ struct xhci_hcd_mtk {
+       struct regulator *vbus;
+       struct clk *sys_clk;    /* sys and mac clock */
+       struct clk *ref_clk;
++      struct clk *mcu_clk;
++      struct clk *dma_clk;
+       struct regmap *pericfg;
+       struct phy **phys;
+       int num_phys;
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0132-usb-host-modify-description-for-MTK-xHCI-config.patch b/target/linux/mediatek/patches-4.14/0132-usb-host-modify-description-for-MTK-xHCI-config.patch
new file mode 100644 (file)
index 0000000..87e1b3d
--- /dev/null
@@ -0,0 +1,37 @@
+From d975bd8976c4d19fbfbaafe269dd466e281a2e3e Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 16:26:39 +0800
+Subject: [PATCH 132/224] usb: host: modify description for MTK xHCI config
+
+Due to all MediaTek SoCs with xHCI host controller use this
+driver, remove limitation for specific SoCs
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/usb/host/Kconfig | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
+index fa5692dec832..bc09a2e4faeb 100644
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -45,12 +45,12 @@ config USB_XHCI_PLATFORM
+         If unsure, say N.
+ config USB_XHCI_MTK
+-      tristate "xHCI support for Mediatek MT65xx/MT7621"
++      tristate "xHCI support for MediaTek SoCs"
+       select MFD_SYSCON
+       depends on (MIPS && SOC_MT7621) || ARCH_MEDIATEK || COMPILE_TEST
+       ---help---
+         Say 'Y' to enable the support for the xHCI host controller
+-        found in Mediatek MT65xx SoCs.
++        found in MediaTek SoCs.
+         If unsure, say N.
+ config USB_XHCI_MVEBU
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0133-dt-bindings-usb-mtk-xhci-add-a-optional-property-to-.patch b/target/linux/mediatek/patches-4.14/0133-dt-bindings-usb-mtk-xhci-add-a-optional-property-to-.patch
new file mode 100644 (file)
index 0000000..e59f46a
--- /dev/null
@@ -0,0 +1,30 @@
+From 3a2dce7d84793ec60cff173e17e3669acaade8c9 Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 16:26:40 +0800
+Subject: [PATCH 133/224] dt-bindings: usb: mtk-xhci: add a optional property
+ to disable u3ports
+
+Add a new optional property to disable u3ports
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
+index 5611a2e4ddf0..2d9b459bd890 100644
+--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
++++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
+@@ -38,6 +38,8 @@ Optional properties:
+       mode;
+  - mediatek,syscon-wakeup : phandle to syscon used to access USB wakeup
+       control register, it depends on "mediatek,wakeup-src".
++ - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
++      bit1 for u3port1, ... etc;
+  - vbus-supply : reference to the VBUS regulator;
+  - usb3-lpm-capable : supports USB3.0 LPM
+  - pinctrl-names : a pinctrl state named "default" must be defined
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0134-dt-bindings-usb-mtk-xhci-remove-dummy-clocks-and-add.patch b/target/linux/mediatek/patches-4.14/0134-dt-bindings-usb-mtk-xhci-remove-dummy-clocks-and-add.patch
new file mode 100644 (file)
index 0000000..9d196ab
--- /dev/null
@@ -0,0 +1,63 @@
+From a96468412cac8abd66667c322fbcda756cc3abc9 Mon Sep 17 00:00:00 2001
+From: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Date: Fri, 13 Oct 2017 16:26:41 +0800
+Subject: [PATCH 134/224] dt-bindings: usb: mtk-xhci: remove dummy clocks and
+ add optional ones
+
+Remove dummy clocks for usb wakeup and add optional ones for
+MCU_BUS_CK and DMA_BUS_CK.
+
+Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ .../devicetree/bindings/usb/mediatek,mtk-xhci.txt      | 18 ++++++++----------
+ 1 file changed, 8 insertions(+), 10 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
+index 2d9b459bd890..30595964876a 100644
+--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
++++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
+@@ -26,10 +26,11 @@ Required properties:
+  - clocks : a list of phandle + clock-specifier pairs, one for each
+       entry in clock-names
+  - clock-names : must contain
+-      "sys_ck": for clock of xHCI MAC
+-      "ref_ck": for reference clock of xHCI MAC
+-      "wakeup_deb_p0": for USB wakeup debounce clock of port0
+-      "wakeup_deb_p1": for USB wakeup debounce clock of port1
++      "sys_ck": controller clock used by normal mode,
++      the following ones are optional:
++      "ref_ck": reference clock used by low power mode etc,
++      "mcu_ck": mcu_bus clock for register access,
++      "dma_ck": dma_bus clock for data transfer by DMA
+  - phys : a list of phandle + phy specifier pairs
+@@ -57,9 +58,7 @@ usb30: usb@11270000 {
+       clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>,
+                <&pericfg CLK_PERI_USB0>,
+                <&pericfg CLK_PERI_USB1>;
+-      clock-names = "sys_ck", "ref_ck",
+-                    "wakeup_deb_p0",
+-                    "wakeup_deb_p1";
++      clock-names = "sys_ck", "ref_ck";
+       phys = <&phy_port0 PHY_TYPE_USB3>,
+              <&phy_port1 PHY_TYPE_USB2>;
+       vusb33-supply = <&mt6397_vusb_reg>;
+@@ -91,9 +90,8 @@ Required properties:
+  - clocks : a list of phandle + clock-specifier pairs, one for each
+       entry in clock-names
+- - clock-names : must be
+-      "sys_ck": for clock of xHCI MAC
+-      "ref_ck": for reference clock of xHCI MAC
++ - clock-names : must contain "sys_ck", and the following ones are optional:
++      "ref_ck", "mcu_ck" and "dma_ck"
+ Optional properties:
+  - vbus-supply : reference to the VBUS regulator;
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0135-dt-bindings-mtd-add-new-compatible-strings-and-impro.patch b/target/linux/mediatek/patches-4.14/0135-dt-bindings-mtd-add-new-compatible-strings-and-impro.patch
new file mode 100644 (file)
index 0000000..4c69986
--- /dev/null
@@ -0,0 +1,47 @@
+From 2af9a8582cb28e786a8cbd913f41e6db9adcf3dc Mon Sep 17 00:00:00 2001
+From: Guochun Mao <guochun.mao@mediatek.com>
+Date: Thu, 21 Sep 2017 20:45:05 +0800
+Subject: [PATCH 135/224] dt-bindings: mtd: add new compatible strings and
+ improve description
+
+Add "mediatak,mt2712-nor" and "mediatek,mt7622-nor"
+for nor flash node's compatible strings.
+Explicate the fallback compatible.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Guochun Mao <guochun.mao@mediatek.com>
+Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
+---
+ Documentation/devicetree/bindings/mtd/mtk-quadspi.txt | 15 +++++++++------
+ 1 file changed, 9 insertions(+), 6 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt b/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt
+index 840f9405dcf0..56d3668e2c50 100644
+--- a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt
++++ b/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt
+@@ -1,13 +1,16 @@
+ * Serial NOR flash controller for MTK MT81xx (and similar)
+ Required properties:
+-- compatible:           The possible values are:
+-                "mediatek,mt2701-nor"
+-                "mediatek,mt7623-nor"
++- compatible:           For mt8173, compatible should be "mediatek,mt8173-nor",
++                and it's the fallback compatible for other Soc.
++                For every other SoC, should contain both the SoC-specific compatible
++                string and "mediatek,mt8173-nor".
++                The possible values are:
++                "mediatek,mt2701-nor", "mediatek,mt8173-nor"
++                "mediatek,mt2712-nor", "mediatek,mt8173-nor"
++                "mediatek,mt7622-nor", "mediatek,mt8173-nor"
++                "mediatek,mt7623-nor", "mediatek,mt8173-nor"
+                 "mediatek,mt8173-nor"
+-                For mt8173, compatible should be "mediatek,mt8173-nor".
+-                For every other SoC, should contain both the SoC-specific compatible string
+-                and "mediatek,mt8173-nor".
+ - reg:                  physical base address and length of the controller's register
+ - clocks:       the phandle of the clocks needed by the nor controller
+ - clock-names:          the names of the clocks
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0136-mtd-mtk-nor-add-suspend-resume-support.patch b/target/linux/mediatek/patches-4.14/0136-mtd-mtk-nor-add-suspend-resume-support.patch
new file mode 100644 (file)
index 0000000..248e195
--- /dev/null
@@ -0,0 +1,133 @@
+From 8947f8cd407a55db816cd03fc03b59096210978e Mon Sep 17 00:00:00 2001
+From: Guochun Mao <guochun.mao@mediatek.com>
+Date: Thu, 21 Sep 2017 20:45:06 +0800
+Subject: [PATCH 136/224] mtd: mtk-nor: add suspend/resume support
+
+Abstract functions of clock setting, to avoid duplicated code,
+these functions been used in new feature.
+Implement suspend/resume functions.
+
+Signed-off-by: Guochun Mao <guochun.mao@mediatek.com>
+Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
+---
+ drivers/mtd/spi-nor/mtk-quadspi.c | 70 ++++++++++++++++++++++++++++++++-------
+ 1 file changed, 58 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/mtd/spi-nor/mtk-quadspi.c b/drivers/mtd/spi-nor/mtk-quadspi.c
+index c258c7adf1c5..abe455ccd68b 100644
+--- a/drivers/mtd/spi-nor/mtk-quadspi.c
++++ b/drivers/mtd/spi-nor/mtk-quadspi.c
+@@ -404,6 +404,29 @@ static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
+       return ret;
+ }
++static void mt8173_nor_disable_clk(struct mt8173_nor *mt8173_nor)
++{
++      clk_disable_unprepare(mt8173_nor->spi_clk);
++      clk_disable_unprepare(mt8173_nor->nor_clk);
++}
++
++static int mt8173_nor_enable_clk(struct mt8173_nor *mt8173_nor)
++{
++      int ret;
++
++      ret = clk_prepare_enable(mt8173_nor->spi_clk);
++      if (ret)
++              return ret;
++
++      ret = clk_prepare_enable(mt8173_nor->nor_clk);
++      if (ret) {
++              clk_disable_unprepare(mt8173_nor->spi_clk);
++              return ret;
++      }
++
++      return 0;
++}
++
+ static int mtk_nor_init(struct mt8173_nor *mt8173_nor,
+                       struct device_node *flash_node)
+ {
+@@ -468,15 +491,11 @@ static int mtk_nor_drv_probe(struct platform_device *pdev)
+               return PTR_ERR(mt8173_nor->nor_clk);
+       mt8173_nor->dev = &pdev->dev;
+-      ret = clk_prepare_enable(mt8173_nor->spi_clk);
++
++      ret = mt8173_nor_enable_clk(mt8173_nor);
+       if (ret)
+               return ret;
+-      ret = clk_prepare_enable(mt8173_nor->nor_clk);
+-      if (ret) {
+-              clk_disable_unprepare(mt8173_nor->spi_clk);
+-              return ret;
+-      }
+       /* only support one attached flash */
+       flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
+       if (!flash_np) {
+@@ -487,10 +506,9 @@ static int mtk_nor_drv_probe(struct platform_device *pdev)
+       ret = mtk_nor_init(mt8173_nor, flash_np);
+ nor_free:
+-      if (ret) {
+-              clk_disable_unprepare(mt8173_nor->spi_clk);
+-              clk_disable_unprepare(mt8173_nor->nor_clk);
+-      }
++      if (ret)
++              mt8173_nor_disable_clk(mt8173_nor);
++
+       return ret;
+ }
+@@ -498,11 +516,38 @@ static int mtk_nor_drv_remove(struct platform_device *pdev)
+ {
+       struct mt8173_nor *mt8173_nor = platform_get_drvdata(pdev);
+-      clk_disable_unprepare(mt8173_nor->spi_clk);
+-      clk_disable_unprepare(mt8173_nor->nor_clk);
++      mt8173_nor_disable_clk(mt8173_nor);
++
++      return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int mtk_nor_suspend(struct device *dev)
++{
++      struct mt8173_nor *mt8173_nor = dev_get_drvdata(dev);
++
++      mt8173_nor_disable_clk(mt8173_nor);
++
+       return 0;
+ }
++static int mtk_nor_resume(struct device *dev)
++{
++      struct mt8173_nor *mt8173_nor = dev_get_drvdata(dev);
++
++      return mt8173_nor_enable_clk(mt8173_nor);
++}
++
++static const struct dev_pm_ops mtk_nor_dev_pm_ops = {
++      .suspend = mtk_nor_suspend,
++      .resume = mtk_nor_resume,
++};
++
++#define MTK_NOR_DEV_PM_OPS    (&mtk_nor_dev_pm_ops)
++#else
++#define MTK_NOR_DEV_PM_OPS    NULL
++#endif
++
+ static const struct of_device_id mtk_nor_of_ids[] = {
+       { .compatible = "mediatek,mt8173-nor"},
+       { /* sentinel */ }
+@@ -514,6 +559,7 @@ static struct platform_driver mtk_nor_driver = {
+       .remove = mtk_nor_drv_remove,
+       .driver = {
+               .name = "mtk-nor",
++              .pm = MTK_NOR_DEV_PM_OPS,
+               .of_match_table = mtk_nor_of_ids,
+       },
+ };
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0137-dt-bindings-rtc-mediatek-add-bindings-for-MediaTek-S.patch b/target/linux/mediatek/patches-4.14/0137-dt-bindings-rtc-mediatek-add-bindings-for-MediaTek-S.patch
new file mode 100644 (file)
index 0000000..2488276
--- /dev/null
@@ -0,0 +1,47 @@
+From 3254edde244fcbcce3bf4da1ade9db2db558ae28 Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Mon, 23 Oct 2017 15:16:44 +0800
+Subject: [PATCH 137/224] dt-bindings: rtc: mediatek: add bindings for MediaTek
+ SoC based RTC
+
+Add device-tree binding for MediaTek SoC based RTC
+
+Cc: devicetree@vger.kernel.org
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
+---
+ .../devicetree/bindings/rtc/rtc-mt7622.txt          | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/rtc/rtc-mt7622.txt
+
+diff --git a/Documentation/devicetree/bindings/rtc/rtc-mt7622.txt b/Documentation/devicetree/bindings/rtc/rtc-mt7622.txt
+new file mode 100644
+index 000000000000..09fe8f51476f
+--- /dev/null
++++ b/Documentation/devicetree/bindings/rtc/rtc-mt7622.txt
+@@ -0,0 +1,21 @@
++Device-Tree bindings for MediaTek SoC based RTC
++
++Required properties:
++- compatible      : Should be
++                      "mediatek,mt7622-rtc", "mediatek,soc-rtc" : for MT7622 SoC
++- reg                     : Specifies base physical address and size of the registers;
++- interrupts      : Should contain the interrupt for RTC alarm;
++- clocks          : Specifies list of clock specifiers, corresponding to
++                    entries in clock-names property;
++- clock-names     : Should contain "rtc" entries
++
++Example:
++
++rtc: rtc@10212800 {
++      compatible = "mediatek,mt7622-rtc",
++                   "mediatek,soc-rtc";
++      reg = <0 0x10212800 0 0x200>;
++      interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
++      clocks = <&topckgen CLK_TOP_RTC>;
++      clock-names = "rtc";
++};
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0138-rtc-mediatek-add-driver-for-RTC-on-MT7622-SoC.patch b/target/linux/mediatek/patches-4.14/0138-rtc-mediatek-add-driver-for-RTC-on-MT7622-SoC.patch
new file mode 100644 (file)
index 0000000..6be78ac
--- /dev/null
@@ -0,0 +1,481 @@
+From 4cf0b74c175cb5cb751e449223c0baafc2f98499 Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Mon, 23 Oct 2017 15:16:45 +0800
+Subject: [PATCH 138/224] rtc: mediatek: add driver for RTC on MT7622 SoC
+
+This patch introduces the driver for the RTC on MT7622 SoC.
+
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
+Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
+---
+ drivers/rtc/Kconfig      |  10 ++
+ drivers/rtc/Makefile     |   1 +
+ drivers/rtc/rtc-mt7622.c | 422 +++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 433 insertions(+)
+ create mode 100644 drivers/rtc/rtc-mt7622.c
+
+diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
+index e0e58f3b1420..322752ebc5a7 100644
+--- a/drivers/rtc/Kconfig
++++ b/drivers/rtc/Kconfig
+@@ -1715,6 +1715,16 @@ config RTC_DRV_MT6397
+         If you want to use Mediatek(R) RTC interface, select Y or M here.
++config RTC_DRV_MT7622
++      tristate "MediaTek SoC based RTC"
++      depends on ARCH_MEDIATEK || COMPILE_TEST
++      help
++        This enables support for the real time clock built in the MediaTek
++        SoCs.
++
++        This drive can also be built as a module. If so, the module
++        will be called rtc-mt7622.
++
+ config RTC_DRV_XGENE
+       tristate "APM X-Gene RTC"
+       depends on HAS_IOMEM
+diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
+index 7230014c92af..5ec891a81f4f 100644
+--- a/drivers/rtc/Makefile
++++ b/drivers/rtc/Makefile
+@@ -102,6 +102,7 @@ obj-$(CONFIG_RTC_DRV_MPC5121)      += rtc-mpc5121.o
+ obj-$(CONFIG_RTC_DRV_VRTC)    += rtc-mrst.o
+ obj-$(CONFIG_RTC_DRV_MSM6242) += rtc-msm6242.o
+ obj-$(CONFIG_RTC_DRV_MT6397)  += rtc-mt6397.o
++obj-$(CONFIG_RTC_DRV_MT7622)  += rtc-mt7622.o
+ obj-$(CONFIG_RTC_DRV_MV)      += rtc-mv.o
+ obj-$(CONFIG_RTC_DRV_MXC)     += rtc-mxc.o
+ obj-$(CONFIG_RTC_DRV_NUC900)  += rtc-nuc900.o
+diff --git a/drivers/rtc/rtc-mt7622.c b/drivers/rtc/rtc-mt7622.c
+new file mode 100644
+index 000000000000..d79b9ae4d237
+--- /dev/null
++++ b/drivers/rtc/rtc-mt7622.c
+@@ -0,0 +1,422 @@
++/*
++ * Driver for MediaTek SoC based RTC
++ *
++ * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/rtc.h>
++
++#define MTK_RTC_DEV KBUILD_MODNAME
++
++#define MTK_RTC_PWRCHK1               0x4
++#define       RTC_PWRCHK1_MAGIC       0xc6
++
++#define MTK_RTC_PWRCHK2               0x8
++#define       RTC_PWRCHK2_MAGIC       0x9a
++
++#define MTK_RTC_KEY           0xc
++#define       RTC_KEY_MAGIC           0x59
++
++#define MTK_RTC_PROT1         0x10
++#define       RTC_PROT1_MAGIC         0xa3
++
++#define MTK_RTC_PROT2         0x14
++#define       RTC_PROT2_MAGIC         0x57
++
++#define MTK_RTC_PROT3         0x18
++#define       RTC_PROT3_MAGIC         0x67
++
++#define MTK_RTC_PROT4         0x1c
++#define       RTC_PROT4_MAGIC         0xd2
++
++#define MTK_RTC_CTL           0x20
++#define       RTC_RC_STOP             BIT(0)
++
++#define MTK_RTC_DEBNCE                0x2c
++#define       RTC_DEBNCE_MASK         GENMASK(2, 0)
++
++#define MTK_RTC_INT           0x30
++#define RTC_INT_AL_STA                BIT(4)
++
++/*
++ * Ranges from 0x40 to 0x78 provide RTC time setup for year, month,
++ * day of month, day of week, hour, minute and second.
++ */
++#define MTK_RTC_TREG(_t, _f)  (0x40 + (0x4 * (_f)) + ((_t) * 0x20))
++
++#define MTK_RTC_AL_CTL                0x7c
++#define       RTC_AL_EN               BIT(0)
++#define       RTC_AL_ALL              GENMASK(7, 0)
++
++/*
++ * The offset is used in the translation for the year between in struct
++ * rtc_time and in hardware register MTK_RTC_TREG(x,MTK_YEA)
++ */
++#define MTK_RTC_TM_YR_OFFSET  100
++
++/*
++ * The lowest value for the valid tm_year. RTC hardware would take incorrectly
++ * tm_year 100 as not a leap year and thus it is also required being excluded
++ * from the valid options.
++ */
++#define MTK_RTC_TM_YR_L               (MTK_RTC_TM_YR_OFFSET + 1)
++
++/*
++ * The most year the RTC can hold is 99 and the next to 99 in year register
++ * would be wraparound to 0, for MT7622.
++ */
++#define MTK_RTC_HW_YR_LIMIT   99
++
++/* The highest value for the valid tm_year */
++#define MTK_RTC_TM_YR_H               (MTK_RTC_TM_YR_OFFSET + MTK_RTC_HW_YR_LIMIT)
++
++/* Simple macro helps to check whether the hardware supports the tm_year */
++#define MTK_RTC_TM_YR_VALID(_y)       ((_y) >= MTK_RTC_TM_YR_L && \
++                               (_y) <= MTK_RTC_TM_YR_H)
++
++/* Types of the function the RTC provides are time counter and alarm. */
++enum {
++      MTK_TC,
++      MTK_AL,
++};
++
++/* Indexes are used for the pointer to relevant registers in MTK_RTC_TREG */
++enum {
++      MTK_YEA,
++      MTK_MON,
++      MTK_DOM,
++      MTK_DOW,
++      MTK_HOU,
++      MTK_MIN,
++      MTK_SEC
++};
++
++struct mtk_rtc {
++      struct rtc_device *rtc;
++      void __iomem *base;
++      int irq;
++      struct clk *clk;
++};
++
++static void mtk_w32(struct mtk_rtc *rtc, u32 reg, u32 val)
++{
++      writel_relaxed(val, rtc->base + reg);
++}
++
++static u32 mtk_r32(struct mtk_rtc *rtc, u32 reg)
++{
++      return readl_relaxed(rtc->base + reg);
++}
++
++static void mtk_rmw(struct mtk_rtc *rtc, u32 reg, u32 mask, u32 set)
++{
++      u32 val;
++
++      val = mtk_r32(rtc, reg);
++      val &= ~mask;
++      val |= set;
++      mtk_w32(rtc, reg, val);
++}
++
++static void mtk_set(struct mtk_rtc *rtc, u32 reg, u32 val)
++{
++      mtk_rmw(rtc, reg, 0, val);
++}
++
++static void mtk_clr(struct mtk_rtc *rtc, u32 reg, u32 val)
++{
++      mtk_rmw(rtc, reg, val, 0);
++}
++
++static void mtk_rtc_hw_init(struct mtk_rtc *hw)
++{
++      /* The setup of the init sequence is for allowing RTC got to work */
++      mtk_w32(hw, MTK_RTC_PWRCHK1, RTC_PWRCHK1_MAGIC);
++      mtk_w32(hw, MTK_RTC_PWRCHK2, RTC_PWRCHK2_MAGIC);
++      mtk_w32(hw, MTK_RTC_KEY, RTC_KEY_MAGIC);
++      mtk_w32(hw, MTK_RTC_PROT1, RTC_PROT1_MAGIC);
++      mtk_w32(hw, MTK_RTC_PROT2, RTC_PROT2_MAGIC);
++      mtk_w32(hw, MTK_RTC_PROT3, RTC_PROT3_MAGIC);
++      mtk_w32(hw, MTK_RTC_PROT4, RTC_PROT4_MAGIC);
++      mtk_rmw(hw, MTK_RTC_DEBNCE, RTC_DEBNCE_MASK, 0);
++      mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
++}
++
++static void mtk_rtc_get_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
++                                    int time_alarm)
++{
++      u32 year, mon, mday, wday, hour, min, sec;
++
++      /*
++       * Read again until the field of the second is not changed which
++       * ensures all fields in the consistent state. Note that MTK_SEC must
++       * be read first. In this way, it guarantees the others remain not
++       * changed when the results for two MTK_SEC consecutive reads are same.
++       */
++      do {
++              sec = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC));
++              min = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN));
++              hour = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU));
++              wday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW));
++              mday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM));
++              mon = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MON));
++              year = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA));
++      } while (sec != mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC)));
++
++      tm->tm_sec  = sec;
++      tm->tm_min  = min;
++      tm->tm_hour = hour;
++      tm->tm_wday = wday;
++      tm->tm_mday = mday;
++      tm->tm_mon  = mon - 1;
++
++      /* Rebase to the absolute year which userspace queries */
++      tm->tm_year = year + MTK_RTC_TM_YR_OFFSET;
++}
++
++static void mtk_rtc_set_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
++                                    int time_alarm)
++{
++      u32 year;
++
++      /* Rebase to the relative year which RTC hardware requires */
++      year = tm->tm_year - MTK_RTC_TM_YR_OFFSET;
++
++      mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA), year);
++      mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MON), tm->tm_mon + 1);
++      mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW), tm->tm_wday);
++      mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM), tm->tm_mday);
++      mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU), tm->tm_hour);
++      mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN), tm->tm_min);
++      mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC), tm->tm_sec);
++}
++
++static irqreturn_t mtk_rtc_alarmirq(int irq, void *id)
++{
++      struct mtk_rtc *hw = (struct mtk_rtc *)id;
++      u32 irq_sta;
++
++      irq_sta = mtk_r32(hw, MTK_RTC_INT);
++      if (irq_sta & RTC_INT_AL_STA) {
++              /* Stop alarm also implicitly disables the alarm interrupt */
++              mtk_w32(hw, MTK_RTC_AL_CTL, 0);
++              rtc_update_irq(hw->rtc, 1, RTC_IRQF | RTC_AF);
++
++              /* Ack alarm interrupt status */
++              mtk_w32(hw, MTK_RTC_INT, RTC_INT_AL_STA);
++              return IRQ_HANDLED;
++      }
++
++      return IRQ_NONE;
++}
++
++static int mtk_rtc_gettime(struct device *dev, struct rtc_time *tm)
++{
++      struct mtk_rtc *hw = dev_get_drvdata(dev);
++
++      mtk_rtc_get_alarm_or_time(hw, tm, MTK_TC);
++
++      return rtc_valid_tm(tm);
++}
++
++static int mtk_rtc_settime(struct device *dev, struct rtc_time *tm)
++{
++      struct mtk_rtc *hw = dev_get_drvdata(dev);
++
++      if (!MTK_RTC_TM_YR_VALID(tm->tm_year))
++              return -EINVAL;
++
++      /* Stop time counter before setting a new one*/
++      mtk_set(hw, MTK_RTC_CTL, RTC_RC_STOP);
++
++      mtk_rtc_set_alarm_or_time(hw, tm, MTK_TC);
++
++      /* Restart the time counter */
++      mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
++
++      return 0;
++}
++
++static int mtk_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
++{
++      struct mtk_rtc *hw = dev_get_drvdata(dev);
++      struct rtc_time *alrm_tm = &wkalrm->time;
++
++      mtk_rtc_get_alarm_or_time(hw, alrm_tm, MTK_AL);
++
++      wkalrm->enabled = !!(mtk_r32(hw, MTK_RTC_AL_CTL) & RTC_AL_EN);
++      wkalrm->pending = !!(mtk_r32(hw, MTK_RTC_INT) & RTC_INT_AL_STA);
++
++      return 0;
++}
++
++static int mtk_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
++{
++      struct mtk_rtc *hw = dev_get_drvdata(dev);
++      struct rtc_time *alrm_tm = &wkalrm->time;
++
++      if (!MTK_RTC_TM_YR_VALID(alrm_tm->tm_year))
++              return -EINVAL;
++
++      /*
++       * Stop the alarm also implicitly including disables interrupt before
++       * setting a new one.
++       */
++      mtk_clr(hw, MTK_RTC_AL_CTL, RTC_AL_EN);
++
++      /*
++       * Avoid contention between mtk_rtc_setalarm and IRQ handler so that
++       * disabling the interrupt and awaiting for pending IRQ handler to
++       * complete.
++       */
++      synchronize_irq(hw->irq);
++
++      mtk_rtc_set_alarm_or_time(hw, alrm_tm, MTK_AL);
++
++      /* Restart the alarm with the new setup */
++      mtk_w32(hw, MTK_RTC_AL_CTL, RTC_AL_ALL);
++
++      return 0;
++}
++
++static const struct rtc_class_ops mtk_rtc_ops = {
++      .read_time              = mtk_rtc_gettime,
++      .set_time               = mtk_rtc_settime,
++      .read_alarm             = mtk_rtc_getalarm,
++      .set_alarm              = mtk_rtc_setalarm,
++};
++
++static const struct of_device_id mtk_rtc_match[] = {
++      { .compatible = "mediatek,mt7622-rtc" },
++      { .compatible = "mediatek,soc-rtc" },
++      {},
++};
++
++static int mtk_rtc_probe(struct platform_device *pdev)
++{
++      struct mtk_rtc *hw;
++      struct resource *res;
++      int ret;
++
++      hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
++      if (!hw)
++              return -ENOMEM;
++
++      platform_set_drvdata(pdev, hw);
++
++      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++      hw->base = devm_ioremap_resource(&pdev->dev, res);
++      if (IS_ERR(hw->base))
++              return PTR_ERR(hw->base);
++
++      hw->clk = devm_clk_get(&pdev->dev, "rtc");
++      if (IS_ERR(hw->clk)) {
++              dev_err(&pdev->dev, "No clock\n");
++              return PTR_ERR(hw->clk);
++      }
++
++      ret = clk_prepare_enable(hw->clk);
++      if (ret)
++              return ret;
++
++      hw->irq = platform_get_irq(pdev, 0);
++      if (hw->irq < 0) {
++              dev_err(&pdev->dev, "No IRQ resource\n");
++              ret = hw->irq;
++              goto err;
++      }
++
++      ret = devm_request_irq(&pdev->dev, hw->irq, mtk_rtc_alarmirq,
++                             0, dev_name(&pdev->dev), hw);
++      if (ret) {
++              dev_err(&pdev->dev, "Can't request IRQ\n");
++              goto err;
++      }
++
++      mtk_rtc_hw_init(hw);
++
++      device_init_wakeup(&pdev->dev, true);
++
++      hw->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
++                                         &mtk_rtc_ops, THIS_MODULE);
++      if (IS_ERR(hw->rtc)) {
++              ret = PTR_ERR(hw->rtc);
++              dev_err(&pdev->dev, "Unable to register device\n");
++              goto err;
++      }
++
++      return 0;
++err:
++      clk_disable_unprepare(hw->clk);
++
++      return ret;
++}
++
++static int mtk_rtc_remove(struct platform_device *pdev)
++{
++      struct mtk_rtc *hw = platform_get_drvdata(pdev);
++
++      clk_disable_unprepare(hw->clk);
++
++      return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int mtk_rtc_suspend(struct device *dev)
++{
++      struct mtk_rtc *hw = dev_get_drvdata(dev);
++
++      if (device_may_wakeup(dev))
++              enable_irq_wake(hw->irq);
++
++      return 0;
++}
++
++static int mtk_rtc_resume(struct device *dev)
++{
++      struct mtk_rtc *hw = dev_get_drvdata(dev);
++
++      if (device_may_wakeup(dev))
++              disable_irq_wake(hw->irq);
++
++      return 0;
++}
++
++static SIMPLE_DEV_PM_OPS(mtk_rtc_pm_ops, mtk_rtc_suspend, mtk_rtc_resume);
++
++#define MTK_RTC_PM_OPS (&mtk_rtc_pm_ops)
++#else /* CONFIG_PM */
++#define MTK_RTC_PM_OPS NULL
++#endif        /* CONFIG_PM */
++
++static struct platform_driver mtk_rtc_driver = {
++      .probe  = mtk_rtc_probe,
++      .remove = mtk_rtc_remove,
++      .driver = {
++              .name = MTK_RTC_DEV,
++              .of_match_table = mtk_rtc_match,
++              .pm = MTK_RTC_PM_OPS,
++      },
++};
++
++module_platform_driver(mtk_rtc_driver);
++
++MODULE_DESCRIPTION("MediaTek SoC based RTC Driver");
++MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
++MODULE_LICENSE("GPL");
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0139-rtc-mediatek-enhance-the-description-for-MediaTek-PM.patch b/target/linux/mediatek/patches-4.14/0139-rtc-mediatek-enhance-the-description-for-MediaTek-PM.patch
new file mode 100644 (file)
index 0000000..d492731
--- /dev/null
@@ -0,0 +1,44 @@
+From ff4f8c2c894f1e6b5b5551571e22b2f947545bff Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Mon, 23 Oct 2017 15:16:46 +0800
+Subject: [PATCH 139/224] rtc: mediatek: enhance the description for MediaTek
+ PMIC based RTC
+
+Give a better description for original MediaTek RTC driver as PMIC based
+RTC in order to distinguish SoC based RTC. Also turning all words with
+Mediatek to MediaTek here.
+
+Cc: Eddie Huang <eddie.huang@mediatek.com>
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Acked-by: Eddie Huang <eddie.huang@mediatek.com>
+Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
+---
+ drivers/rtc/Kconfig | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
+index 322752ebc5a7..616fe53c788e 100644
+--- a/drivers/rtc/Kconfig
++++ b/drivers/rtc/Kconfig
+@@ -1706,14 +1706,14 @@ config RTC_DRV_MOXART
+          will be called rtc-moxart
+ config RTC_DRV_MT6397
+-      tristate "Mediatek Real Time Clock driver"
++      tristate "MediaTek PMIC based RTC"
+       depends on MFD_MT6397 || (COMPILE_TEST && IRQ_DOMAIN)
+       help
+-        This selects the Mediatek(R) RTC driver. RTC is part of Mediatek
++        This selects the MediaTek(R) RTC driver. RTC is part of MediaTek
+         MT6397 PMIC. You should enable MT6397 PMIC MFD before select
+-        Mediatek(R) RTC driver.
++        MediaTek(R) RTC driver.
+-        If you want to use Mediatek(R) RTC interface, select Y or M here.
++        If you want to use MediaTek(R) RTC interface, select Y or M here.
+ config RTC_DRV_MT7622
+       tristate "MediaTek SoC based RTC"
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0140-mtd-nand-mtk-change-the-compile-sequence-of-mtk_nand.patch b/target/linux/mediatek/patches-4.14/0140-mtd-nand-mtk-change-the-compile-sequence-of-mtk_nand.patch
new file mode 100644 (file)
index 0000000..6a31a60
--- /dev/null
@@ -0,0 +1,36 @@
+From 71f568692a6d0a746d72c32d46a1bc09486b9dbb Mon Sep 17 00:00:00 2001
+From: Xiaolei Li <xiaolei.li@mediatek.com>
+Date: Sat, 28 Oct 2017 14:52:23 +0800
+Subject: [PATCH 140/224] mtd: nand: mtk: change the compile sequence of
+ mtk_nand.o and mtk_ecc.o
+
+There will get mtk ecc handler during mtk nand probe now.
+If mtk ecc module is not initialized, then mtk nand probe will return
+-EPROBE_DEFER, and retry later.
+
+Change the compile sequence of mtk_nand.o and mtk_ecc.o, initialize mtk
+ecc module before mtk nand module. This makes mtk nand module initialized
+as soon as possible.
+
+Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+---
+ drivers/mtd/nand/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
+index ade5fc4c3819..57f4cdedf137 100644
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -58,7 +58,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI)         += sunxi_nand.o
+ obj-$(CONFIG_MTD_NAND_HISI504)                += hisi504_nand.o
+ obj-$(CONFIG_MTD_NAND_BRCMNAND)               += brcmnand/
+ obj-$(CONFIG_MTD_NAND_QCOM)           += qcom_nandc.o
+-obj-$(CONFIG_MTD_NAND_MTK)            += mtk_nand.o mtk_ecc.o
++obj-$(CONFIG_MTD_NAND_MTK)            += mtk_ecc.o mtk_nand.o
+ nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
+ nand-objs += nand_amd.o
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0142-mmc-dt-bindings-Add-reg-source_cg-latch-ck-for-Media.patch b/target/linux/mediatek/patches-4.14/0142-mmc-dt-bindings-Add-reg-source_cg-latch-ck-for-Media.patch
new file mode 100644 (file)
index 0000000..77190ab
--- /dev/null
@@ -0,0 +1,65 @@
+From 9ff279fef1a47a152993bf23f8d75fd233c27015 Mon Sep 17 00:00:00 2001
+From: Chaotian Jing <chaotian.jing@mediatek.com>
+Date: Mon, 16 Oct 2017 09:46:28 +0800
+Subject: [PATCH 142/224] mmc: dt-bindings: Add reg/source_cg/latch-ck for
+ Mediatek MMC bindings
+
+Change the comptiable for support of multi-platform
+Make compatible explicit, as MMC host of mt8173 has difference with
+mt8135(mt8173 supports hs400 and hs400_tune),so that need separate
+mt8173/mt8135 compatible name.
+Add description for reg
+Add description for source_cg
+Add description for mediatek,latch-ck
+Note that source_cg and mediatek,latch-ck are optional for some projects,
+eg, MT2701 do not have source_cg, and MT2712 do not need
+mediatek,latch-ck
+
+Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Tested-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ Documentation/devicetree/bindings/mmc/mtk-sd.txt | 18 +++++++++++++++---
+ 1 file changed, 15 insertions(+), 3 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
+index 4182ea36ca5b..72d2a734ab85 100644
+--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
++++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
+@@ -7,10 +7,18 @@ This file documents differences between the core properties in mmc.txt
+ and the properties used by the msdc driver.
+ Required properties:
+-- compatible: Should be "mediatek,mt8173-mmc","mediatek,mt8135-mmc"
++- compatible: value should be either of the following.
++      "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
++      "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
++      "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
++      "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
++- reg: physical base address of the controller and length
+ - interrupts: Should contain MSDC interrupt number
+-- clocks: MSDC source clock, HCLK
+-- clock-names: "source", "hclk"
++- clocks: Should contain phandle for the clock feeding the MMC controller
++- clock-names: Should contain the following:
++      "source" - source clock (required)
++      "hclk" - HCLK which used for host (required)
++      "source_cg" - independent source clock gate (required for MT2712)
+ - pinctrl-names: should be "default", "state_uhs"
+ - pinctrl-0: should contain default/high speed pin ctrl
+ - pinctrl-1: should contain uhs mode pin ctrl
+@@ -30,6 +38,10 @@ Optional properties:
+ - mediatek,hs400-cmd-resp-sel-rising:  HS400 command response sample selection
+                                      If present,HS400 command responses are sampled on rising edges.
+                                      If not present,HS400 command responses are sampled on falling edges.
++- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc
++                   error caused by stop clock(fifo full)
++                   Valid range = [0:0x7]. if not present, default value is 0.
++                   applied to compatible "mediatek,mt2701-mmc".
+ Examples:
+ mmc0: mmc@11230000 {
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0143-mmc-mediatek-add-support-of-mt2701-mt2712.patch b/target/linux/mediatek/patches-4.14/0143-mmc-mediatek-add-support-of-mt2701-mt2712.patch
new file mode 100644 (file)
index 0000000..d315eda
--- /dev/null
@@ -0,0 +1,192 @@
+From 8119f3e147deaf97a66e953fecf3d2b0edbb07fd Mon Sep 17 00:00:00 2001
+From: Chaotian Jing <chaotian.jing@mediatek.com>
+Date: Mon, 16 Oct 2017 09:46:29 +0800
+Subject: [PATCH 143/224] mmc: mediatek: add support of mt2701/mt2712
+
+mt2701/mt2712 has 12bit clock div, which is not compatible with
+mt8135/mt8173. and, some additional features will be added in
+mt2701/mt2712, so that need distinguish it by comatibale name.
+
+Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
+Tested-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/mmc/host/mtk-sd.c | 82 +++++++++++++++++++++++++++++++++++++++--------
+ 1 file changed, 69 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
+index 267f7ab08420..643c795f1bdd 100644
+--- a/drivers/mmc/host/mtk-sd.c
++++ b/drivers/mmc/host/mtk-sd.c
+@@ -95,6 +95,9 @@
+ #define MSDC_CFG_CKDIV          (0xff << 8)   /* RW */
+ #define MSDC_CFG_CKMOD          (0x3 << 16)   /* RW */
+ #define MSDC_CFG_HS400_CK_MODE  (0x1 << 18)   /* RW */
++#define MSDC_CFG_HS400_CK_MODE_EXTRA  (0x1 << 22)     /* RW */
++#define MSDC_CFG_CKDIV_EXTRA    (0xfff << 8)  /* RW */
++#define MSDC_CFG_CKMOD_EXTRA    (0x3 << 20)   /* RW */
+ /* MSDC_IOCON mask */
+ #define MSDC_IOCON_SDR104CKS    (0x1 << 0)    /* RW */
+@@ -295,6 +298,10 @@ struct msdc_save_para {
+       u32 emmc50_cfg0;
+ };
++struct mtk_mmc_compatible {
++      u8 clk_div_bits;
++};
++
+ struct msdc_tune_para {
+       u32 iocon;
+       u32 pad_tune;
+@@ -309,6 +316,7 @@ struct msdc_delay_phase {
+ struct msdc_host {
+       struct device *dev;
++      const struct mtk_mmc_compatible *dev_comp;
+       struct mmc_host *mmc;   /* mmc structure */
+       int cmd_rsp;
+@@ -350,6 +358,31 @@ struct msdc_host {
+       struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
+ };
++static const struct mtk_mmc_compatible mt8135_compat = {
++      .clk_div_bits = 8,
++};
++
++static const struct mtk_mmc_compatible mt8173_compat = {
++      .clk_div_bits = 8,
++};
++
++static const struct mtk_mmc_compatible mt2701_compat = {
++      .clk_div_bits = 12,
++};
++
++static const struct mtk_mmc_compatible mt2712_compat = {
++      .clk_div_bits = 12,
++};
++
++static const struct of_device_id msdc_of_ids[] = {
++      { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
++      { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
++      { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
++      { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
++      {}
++};
++MODULE_DEVICE_TABLE(of, msdc_of_ids);
++
+ static void sdr_set_bits(void __iomem *reg, u32 bs)
+ {
+       u32 val = readl(reg);
+@@ -509,7 +542,12 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
+               timeout = (ns + clk_ns - 1) / clk_ns + clks;
+               /* in 1048576 sclk cycle unit */
+               timeout = (timeout + (0x1 << 20) - 1) >> 20;
+-              sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode);
++              if (host->dev_comp->clk_div_bits == 8)
++                      sdr_get_field(host->base + MSDC_CFG,
++                                    MSDC_CFG_CKMOD, &mode);
++              else
++                      sdr_get_field(host->base + MSDC_CFG,
++                                    MSDC_CFG_CKMOD_EXTRA, &mode);
+               /*DDR mode will double the clk cycles for data timeout */
+               timeout = mode >= 2 ? timeout * 2 : timeout;
+               timeout = timeout > 1 ? timeout - 1 : 0;
+@@ -548,7 +586,11 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
+       flags = readl(host->base + MSDC_INTEN);
+       sdr_clr_bits(host->base + MSDC_INTEN, flags);
+-      sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
++      if (host->dev_comp->clk_div_bits == 8)
++              sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
++      else
++              sdr_clr_bits(host->base + MSDC_CFG,
++                           MSDC_CFG_HS400_CK_MODE_EXTRA);
+       if (timing == MMC_TIMING_UHS_DDR50 ||
+           timing == MMC_TIMING_MMC_DDR52 ||
+           timing == MMC_TIMING_MMC_HS400) {
+@@ -568,8 +610,12 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
+               if (timing == MMC_TIMING_MMC_HS400 &&
+                   hz >= (host->src_clk_freq >> 1)) {
+-                      sdr_set_bits(host->base + MSDC_CFG,
+-                                   MSDC_CFG_HS400_CK_MODE);
++                      if (host->dev_comp->clk_div_bits == 8)
++                              sdr_set_bits(host->base + MSDC_CFG,
++                                           MSDC_CFG_HS400_CK_MODE);
++                      else
++                              sdr_set_bits(host->base + MSDC_CFG,
++                                           MSDC_CFG_HS400_CK_MODE_EXTRA);
+                       sclk = host->src_clk_freq >> 1;
+                       div = 0; /* div is ignore when bit18 is set */
+               }
+@@ -587,8 +633,15 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
+                       sclk = (host->src_clk_freq >> 2) / div;
+               }
+       }
+-      sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
+-                    (mode << 8) | div);
++      if (host->dev_comp->clk_div_bits == 8)
++              sdr_set_field(host->base + MSDC_CFG,
++                            MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
++                            (mode << 8) | div);
++      else
++              sdr_set_field(host->base + MSDC_CFG,
++                            MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
++                            (mode << 12) | div);
++
+       sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
+       while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
+               cpu_relax();
+@@ -1617,12 +1670,17 @@ static int msdc_drv_probe(struct platform_device *pdev)
+       struct mmc_host *mmc;
+       struct msdc_host *host;
+       struct resource *res;
++      const struct of_device_id *of_id;
+       int ret;
+       if (!pdev->dev.of_node) {
+               dev_err(&pdev->dev, "No DT found\n");
+               return -EINVAL;
+       }
++
++      of_id = of_match_node(msdc_of_ids, pdev->dev.of_node);
++      if (!of_id)
++              return -EINVAL;
+       /* Allocate MMC host for this device */
+       mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
+       if (!mmc)
+@@ -1686,11 +1744,15 @@ static int msdc_drv_probe(struct platform_device *pdev)
+       msdc_of_property_parse(pdev, host);
+       host->dev = &pdev->dev;
++      host->dev_comp = of_id->data;
+       host->mmc = mmc;
+       host->src_clk_freq = clk_get_rate(host->src_clk);
+       /* Set host parameters to mmc */
+       mmc->ops = &mt_msdc_ops;
+-      mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
++      if (host->dev_comp->clk_div_bits == 8)
++              mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
++      else
++              mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
+       mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
+       /* MMC core transfer sizes tunable parameters */
+@@ -1839,12 +1901,6 @@ static const struct dev_pm_ops msdc_dev_pm_ops = {
+       SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
+ };
+-static const struct of_device_id msdc_of_ids[] = {
+-      {   .compatible = "mediatek,mt8135-mmc", },
+-      {}
+-};
+-MODULE_DEVICE_TABLE(of, msdc_of_ids);
+-
+ static struct platform_driver mt_msdc_driver = {
+       .probe = msdc_drv_probe,
+       .remove = msdc_drv_remove,
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0144-dt-bindings-ARM-Mediatek-Document-bindings-for-MT271.patch b/target/linux/mediatek/patches-4.14/0144-dt-bindings-ARM-Mediatek-Document-bindings-for-MT271.patch
new file mode 100644 (file)
index 0000000..901e675
--- /dev/null
@@ -0,0 +1,226 @@
+From 815d90faddd22e05f05623086a9c42187fbfb1d8 Mon Sep 17 00:00:00 2001
+From: "weiyi.lu@mediatek.com" <weiyi.lu@mediatek.com>
+Date: Mon, 23 Oct 2017 12:10:32 +0800
+Subject: [PATCH 144/224] dt-bindings: ARM: Mediatek: Document bindings for
+ MT2712
+
+This patch adds the binding documentation for apmixedsys, bdpsys,
+imgsys, imgsys, infracfg, mcucfg, mfgcfg, mmsys, pericfg, topckgen,
+vdecsys and vencsys for Mediatek MT2712.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+---
+ .../bindings/arm/mediatek/mediatek,apmixedsys.txt  |  1 +
+ .../bindings/arm/mediatek/mediatek,bdpsys.txt      |  1 +
+ .../bindings/arm/mediatek/mediatek,imgsys.txt      |  1 +
+ .../bindings/arm/mediatek/mediatek,infracfg.txt    |  1 +
+ .../bindings/arm/mediatek/mediatek,jpgdecsys.txt   | 22 ++++++++++++++++++++++
+ .../bindings/arm/mediatek/mediatek,mcucfg.txt      | 22 ++++++++++++++++++++++
+ .../bindings/arm/mediatek/mediatek,mfgcfg.txt      | 22 ++++++++++++++++++++++
+ .../bindings/arm/mediatek/mediatek,mmsys.txt       |  1 +
+ .../bindings/arm/mediatek/mediatek,pericfg.txt     |  1 +
+ .../bindings/arm/mediatek/mediatek,topckgen.txt    |  1 +
+ .../bindings/arm/mediatek/mediatek,vdecsys.txt     |  1 +
+ .../bindings/arm/mediatek/mediatek,vencsys.txt     |  1 +
+ 12 files changed, 75 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt
+ create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt
+ create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
+
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+index cd977db7630c..19fc116346d6 100644
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+@@ -7,6 +7,7 @@ Required Properties:
+ - compatible: Should be one of:
+       - "mediatek,mt2701-apmixedsys"
++      - "mediatek,mt2712-apmixedsys", "syscon"
+       - "mediatek,mt6797-apmixedsys"
+       - "mediatek,mt8135-apmixedsys"
+       - "mediatek,mt8173-apmixedsys"
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
+index 4137196dd686..4010e37c53a0 100644
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
+@@ -7,6 +7,7 @@ Required Properties:
+ - compatible: Should be:
+       - "mediatek,mt2701-bdpsys", "syscon"
++      - "mediatek,mt2712-bdpsys", "syscon"
+ - #clock-cells: Must be 1
+ The bdpsys controller uses the common clk binding from
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
+index 047b11ae5f45..868bd51a98be 100644
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
+@@ -7,6 +7,7 @@ Required Properties:
+ - compatible: Should be one of:
+       - "mediatek,mt2701-imgsys", "syscon"
++      - "mediatek,mt2712-imgsys", "syscon"
+       - "mediatek,mt6797-imgsys", "syscon"
+       - "mediatek,mt8173-imgsys", "syscon"
+ - #clock-cells: Must be 1
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+index 58d58e2006b8..a3430cd96d0f 100644
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+@@ -8,6 +8,7 @@ Required Properties:
+ - compatible: Should be one of:
+       - "mediatek,mt2701-infracfg", "syscon"
++      - "mediatek,mt2712-infracfg", "syscon"
+       - "mediatek,mt6797-infracfg", "syscon"
+       - "mediatek,mt8135-infracfg", "syscon"
+       - "mediatek,mt8173-infracfg", "syscon"
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt
+new file mode 100644
+index 000000000000..2df799cd06a7
+--- /dev/null
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt
+@@ -0,0 +1,22 @@
++Mediatek jpgdecsys controller
++============================
++
++The Mediatek jpgdecsys controller provides various clocks to the system.
++
++Required Properties:
++
++- compatible: Should be:
++      - "mediatek,mt2712-jpgdecsys", "syscon"
++- #clock-cells: Must be 1
++
++The jpgdecsys controller uses the common clk binding from
++Documentation/devicetree/bindings/clock/clock-bindings.txt
++The available clocks are defined in dt-bindings/clock/mt*-clk.h.
++
++Example:
++
++jpgdecsys: syscon@19000000 {
++      compatible = "mediatek,mt2712-jpgdecsys", "syscon";
++      reg = <0 0x19000000 0 0x1000>;
++      #clock-cells = <1>;
++};
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt
+new file mode 100644
+index 000000000000..b8fb03f3613e
+--- /dev/null
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt
+@@ -0,0 +1,22 @@
++Mediatek mcucfg controller
++============================
++
++The Mediatek mcucfg controller provides various clocks to the system.
++
++Required Properties:
++
++- compatible: Should be one of:
++      - "mediatek,mt2712-mcucfg", "syscon"
++- #clock-cells: Must be 1
++
++The mcucfg controller uses the common clk binding from
++Documentation/devicetree/bindings/clock/clock-bindings.txt
++The available clocks are defined in dt-bindings/clock/mt*-clk.h.
++
++Example:
++
++mcucfg: syscon@10220000 {
++      compatible = "mediatek,mt2712-mcucfg", "syscon";
++      reg = <0 0x10220000 0 0x1000>;
++      #clock-cells = <1>;
++};
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
+new file mode 100644
+index 000000000000..859e67b416d5
+--- /dev/null
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
+@@ -0,0 +1,22 @@
++Mediatek mfgcfg controller
++============================
++
++The Mediatek mfgcfg controller provides various clocks to the system.
++
++Required Properties:
++
++- compatible: Should be one of:
++      - "mediatek,mt2712-mfgcfg", "syscon"
++- #clock-cells: Must be 1
++
++The mfgcfg controller uses the common clk binding from
++Documentation/devicetree/bindings/clock/clock-bindings.txt
++The available clocks are defined in dt-bindings/clock/mt*-clk.h.
++
++Example:
++
++mfgcfg: syscon@13000000 {
++      compatible = "mediatek,mt2712-mfgcfg", "syscon";
++      reg = <0 0x13000000 0 0x1000>;
++      #clock-cells = <1>;
++};
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+index 70529e0b58e9..4eb8bbe15c01 100644
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+@@ -7,6 +7,7 @@ Required Properties:
+ - compatible: Should be one of:
+       - "mediatek,mt2701-mmsys", "syscon"
++      - "mediatek,mt2712-mmsys", "syscon"
+       - "mediatek,mt6797-mmsys", "syscon"
+       - "mediatek,mt8173-mmsys", "syscon"
+ - #clock-cells: Must be 1
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
+index e494366782aa..d9f092eb3550 100644
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
+@@ -8,6 +8,7 @@ Required Properties:
+ - compatible: Should be one of:
+       - "mediatek,mt2701-pericfg", "syscon"
++      - "mediatek,mt2712-pericfg", "syscon"
+       - "mediatek,mt8135-pericfg", "syscon"
+       - "mediatek,mt8173-pericfg", "syscon"
+ - #clock-cells: Must be 1
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+index ec93ecbb9f3c..2024fc909d69 100644
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+@@ -7,6 +7,7 @@ Required Properties:
+ - compatible: Should be one of:
+       - "mediatek,mt2701-topckgen"
++      - "mediatek,mt2712-topckgen", "syscon"
+       - "mediatek,mt6797-topckgen"
+       - "mediatek,mt8135-topckgen"
+       - "mediatek,mt8173-topckgen"
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
+index d150104f928a..ea40d05089f8 100644
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
+@@ -7,6 +7,7 @@ Required Properties:
+ - compatible: Should be one of:
+       - "mediatek,mt2701-vdecsys", "syscon"
++      - "mediatek,mt2712-vdecsys", "syscon"
+       - "mediatek,mt6797-vdecsys", "syscon"
+       - "mediatek,mt8173-vdecsys", "syscon"
+ - #clock-cells: Must be 1
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
+index 8a93be643647..851545357e94 100644
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
+@@ -6,6 +6,7 @@ The Mediatek vencsys controller provides various clocks to the system.
+ Required Properties:
+ - compatible: Should be one of:
++      - "mediatek,mt2712-vencsys", "syscon"
+       - "mediatek,mt6797-vencsys", "syscon"
+       - "mediatek,mt8173-vencsys", "syscon"
+ - #clock-cells: Must be 1
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0145-clk-mediatek-Add-dt-bindings-for-MT2712-clocks.patch b/target/linux/mediatek/patches-4.14/0145-clk-mediatek-Add-dt-bindings-for-MT2712-clocks.patch
new file mode 100644 (file)
index 0000000..9405732
--- /dev/null
@@ -0,0 +1,452 @@
+From 8a64bf0c04a4b7670cf56be5b0ae63fe9d6ecd56 Mon Sep 17 00:00:00 2001
+From: "weiyi.lu@mediatek.com" <weiyi.lu@mediatek.com>
+Date: Mon, 23 Oct 2017 12:10:33 +0800
+Subject: [PATCH 145/224] clk: mediatek: Add dt-bindings for MT2712 clocks
+
+Add MT2712 clock dt-bindings, include topckgen, apmixedsys,
+infracfg, pericfg, mcucfg and subsystem clocks.
+
+Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+---
+ include/dt-bindings/clock/mt2712-clk.h | 427 +++++++++++++++++++++++++++++++++
+ 1 file changed, 427 insertions(+)
+ create mode 100644 include/dt-bindings/clock/mt2712-clk.h
+
+diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bindings/clock/mt2712-clk.h
+new file mode 100644
+index 000000000000..48a8e797a617
+--- /dev/null
++++ b/include/dt-bindings/clock/mt2712-clk.h
+@@ -0,0 +1,427 @@
++/*
++ * Copyright (c) 2017 MediaTek Inc.
++ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _DT_BINDINGS_CLK_MT2712_H
++#define _DT_BINDINGS_CLK_MT2712_H
++
++/* APMIXEDSYS */
++
++#define CLK_APMIXED_MAINPLL           0
++#define CLK_APMIXED_UNIVPLL           1
++#define CLK_APMIXED_VCODECPLL         2
++#define CLK_APMIXED_VENCPLL           3
++#define CLK_APMIXED_APLL1             4
++#define CLK_APMIXED_APLL2             5
++#define CLK_APMIXED_LVDSPLL           6
++#define CLK_APMIXED_LVDSPLL2          7
++#define CLK_APMIXED_MSDCPLL           8
++#define CLK_APMIXED_MSDCPLL2          9
++#define CLK_APMIXED_TVDPLL            10
++#define CLK_APMIXED_MMPLL             11
++#define CLK_APMIXED_ARMCA35PLL                12
++#define CLK_APMIXED_ARMCA72PLL                13
++#define CLK_APMIXED_ETHERPLL          14
++#define CLK_APMIXED_NR_CLK            15
++
++/* TOPCKGEN */
++
++#define CLK_TOP_ARMCA35PLL            0
++#define CLK_TOP_ARMCA35PLL_600M               1
++#define CLK_TOP_ARMCA35PLL_400M               2
++#define CLK_TOP_ARMCA72PLL            3
++#define CLK_TOP_SYSPLL                        4
++#define CLK_TOP_SYSPLL_D2             5
++#define CLK_TOP_SYSPLL1_D2            6
++#define CLK_TOP_SYSPLL1_D4            7
++#define CLK_TOP_SYSPLL1_D8            8
++#define CLK_TOP_SYSPLL1_D16           9
++#define CLK_TOP_SYSPLL_D3             10
++#define CLK_TOP_SYSPLL2_D2            11
++#define CLK_TOP_SYSPLL2_D4            12
++#define CLK_TOP_SYSPLL_D5             13
++#define CLK_TOP_SYSPLL3_D2            14
++#define CLK_TOP_SYSPLL3_D4            15
++#define CLK_TOP_SYSPLL_D7             16
++#define CLK_TOP_SYSPLL4_D2            17
++#define CLK_TOP_SYSPLL4_D4            18
++#define CLK_TOP_UNIVPLL                       19
++#define CLK_TOP_UNIVPLL_D7            20
++#define CLK_TOP_UNIVPLL_D26           21
++#define CLK_TOP_UNIVPLL_D52           22
++#define CLK_TOP_UNIVPLL_D104          23
++#define CLK_TOP_UNIVPLL_D208          24
++#define CLK_TOP_UNIVPLL_D2            25
++#define CLK_TOP_UNIVPLL1_D2           26
++#define CLK_TOP_UNIVPLL1_D4           27
++#define CLK_TOP_UNIVPLL1_D8           28
++#define CLK_TOP_UNIVPLL_D3            29
++#define CLK_TOP_UNIVPLL2_D2           30
++#define CLK_TOP_UNIVPLL2_D4           31
++#define CLK_TOP_UNIVPLL2_D8           32
++#define CLK_TOP_UNIVPLL_D5            33
++#define CLK_TOP_UNIVPLL3_D2           34
++#define CLK_TOP_UNIVPLL3_D4           35
++#define CLK_TOP_UNIVPLL3_D8           36
++#define CLK_TOP_F_MP0_PLL1            37
++#define CLK_TOP_F_MP0_PLL2            38
++#define CLK_TOP_F_BIG_PLL1            39
++#define CLK_TOP_F_BIG_PLL2            40
++#define CLK_TOP_F_BUS_PLL1            41
++#define CLK_TOP_F_BUS_PLL2            42
++#define CLK_TOP_APLL1                 43
++#define CLK_TOP_APLL1_D2              44
++#define CLK_TOP_APLL1_D4              45
++#define CLK_TOP_APLL1_D8              46
++#define CLK_TOP_APLL1_D16             47
++#define CLK_TOP_APLL2                 48
++#define CLK_TOP_APLL2_D2              49
++#define CLK_TOP_APLL2_D4              50
++#define CLK_TOP_APLL2_D8              51
++#define CLK_TOP_APLL2_D16             52
++#define CLK_TOP_LVDSPLL                       53
++#define CLK_TOP_LVDSPLL_D2            54
++#define CLK_TOP_LVDSPLL_D4            55
++#define CLK_TOP_LVDSPLL_D8            56
++#define CLK_TOP_LVDSPLL2              57
++#define CLK_TOP_LVDSPLL2_D2           58
++#define CLK_TOP_LVDSPLL2_D4           59
++#define CLK_TOP_LVDSPLL2_D8           60
++#define CLK_TOP_ETHERPLL_125M         61
++#define CLK_TOP_ETHERPLL_50M          62
++#define CLK_TOP_CVBS                  63
++#define CLK_TOP_CVBS_D2                       64
++#define CLK_TOP_SYS_26M                       65
++#define CLK_TOP_MMPLL                 66
++#define CLK_TOP_MMPLL_D2              67
++#define CLK_TOP_VENCPLL                       68
++#define CLK_TOP_VENCPLL_D2            69
++#define CLK_TOP_VCODECPLL             70
++#define CLK_TOP_VCODECPLL_D2          71
++#define CLK_TOP_TVDPLL                        72
++#define CLK_TOP_TVDPLL_D2             73
++#define CLK_TOP_TVDPLL_D4             74
++#define CLK_TOP_TVDPLL_D8             75
++#define CLK_TOP_TVDPLL_429M           76
++#define CLK_TOP_TVDPLL_429M_D2                77
++#define CLK_TOP_TVDPLL_429M_D4                78
++#define CLK_TOP_MSDCPLL                       79
++#define CLK_TOP_MSDCPLL_D2            80
++#define CLK_TOP_MSDCPLL_D4            81
++#define CLK_TOP_MSDCPLL2              82
++#define CLK_TOP_MSDCPLL2_D2           83
++#define CLK_TOP_MSDCPLL2_D4           84
++#define CLK_TOP_CLK26M_D2             85
++#define CLK_TOP_D2A_ULCLK_6P5M                86
++#define CLK_TOP_VPLL3_DPIX            87
++#define CLK_TOP_VPLL_DPIX             88
++#define CLK_TOP_LTEPLL_FS26M          89
++#define CLK_TOP_DMPLL                 90
++#define CLK_TOP_DSI0_LNTC             91
++#define CLK_TOP_DSI1_LNTC             92
++#define CLK_TOP_LVDSTX3_CLKDIG_CTS    93
++#define CLK_TOP_LVDSTX_CLKDIG_CTS     94
++#define CLK_TOP_CLKRTC_EXT            95
++#define CLK_TOP_CLKRTC_INT            96
++#define CLK_TOP_CSI0                  97
++#define CLK_TOP_CVBSPLL                       98
++#define CLK_TOP_AXI_SEL                       99
++#define CLK_TOP_MEM_SEL                       100
++#define CLK_TOP_MM_SEL                        101
++#define CLK_TOP_PWM_SEL                       102
++#define CLK_TOP_VDEC_SEL              103
++#define CLK_TOP_VENC_SEL              104
++#define CLK_TOP_MFG_SEL                       105
++#define CLK_TOP_CAMTG_SEL             106
++#define CLK_TOP_UART_SEL              107
++#define CLK_TOP_SPI_SEL                       108
++#define CLK_TOP_USB20_SEL             109
++#define CLK_TOP_USB30_SEL             110
++#define CLK_TOP_MSDC50_0_HCLK_SEL     111
++#define CLK_TOP_MSDC50_0_SEL          112
++#define CLK_TOP_MSDC30_1_SEL          113
++#define CLK_TOP_MSDC30_2_SEL          114
++#define CLK_TOP_MSDC30_3_SEL          115
++#define CLK_TOP_AUDIO_SEL             116
++#define CLK_TOP_AUD_INTBUS_SEL                117
++#define CLK_TOP_PMICSPI_SEL           118
++#define CLK_TOP_DPILVDS1_SEL          119
++#define CLK_TOP_ATB_SEL                       120
++#define CLK_TOP_NR_SEL                        121
++#define CLK_TOP_NFI2X_SEL             122
++#define CLK_TOP_IRDA_SEL              123
++#define CLK_TOP_CCI400_SEL            124
++#define CLK_TOP_AUD_1_SEL             125
++#define CLK_TOP_AUD_2_SEL             126
++#define CLK_TOP_MEM_MFG_IN_AS_SEL     127
++#define CLK_TOP_AXI_MFG_IN_AS_SEL     128
++#define CLK_TOP_SCAM_SEL              129
++#define CLK_TOP_NFIECC_SEL            130
++#define CLK_TOP_PE2_MAC_P0_SEL                131
++#define CLK_TOP_PE2_MAC_P1_SEL                132
++#define CLK_TOP_DPILVDS_SEL           133
++#define CLK_TOP_MSDC50_3_HCLK_SEL     134
++#define CLK_TOP_HDCP_SEL              135
++#define CLK_TOP_HDCP_24M_SEL          136
++#define CLK_TOP_RTC_SEL                       137
++#define CLK_TOP_SPINOR_SEL            138
++#define CLK_TOP_APLL_SEL              139
++#define CLK_TOP_APLL2_SEL             140
++#define CLK_TOP_A1SYS_HP_SEL          141
++#define CLK_TOP_A2SYS_HP_SEL          142
++#define CLK_TOP_ASM_L_SEL             143
++#define CLK_TOP_ASM_M_SEL             144
++#define CLK_TOP_ASM_H_SEL             145
++#define CLK_TOP_I2SO1_SEL             146
++#define CLK_TOP_I2SO2_SEL             147
++#define CLK_TOP_I2SO3_SEL             148
++#define CLK_TOP_TDMO0_SEL             149
++#define CLK_TOP_TDMO1_SEL             150
++#define CLK_TOP_I2SI1_SEL             151
++#define CLK_TOP_I2SI2_SEL             152
++#define CLK_TOP_I2SI3_SEL             153
++#define CLK_TOP_ETHER_125M_SEL                154
++#define CLK_TOP_ETHER_50M_SEL         155
++#define CLK_TOP_JPGDEC_SEL            156
++#define CLK_TOP_SPISLV_SEL            157
++#define CLK_TOP_ETHER_50M_RMII_SEL    158
++#define CLK_TOP_CAM2TG_SEL            159
++#define CLK_TOP_DI_SEL                        160
++#define CLK_TOP_TVD_SEL                       161
++#define CLK_TOP_I2C_SEL                       162
++#define CLK_TOP_PWM_INFRA_SEL         163
++#define CLK_TOP_MSDC0P_AES_SEL                164
++#define CLK_TOP_CMSYS_SEL             165
++#define CLK_TOP_GCPU_SEL              166
++#define CLK_TOP_AUD_APLL1_SEL         167
++#define CLK_TOP_AUD_APLL2_SEL         168
++#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL        169
++#define CLK_TOP_APLL_DIV0             170
++#define CLK_TOP_APLL_DIV1             171
++#define CLK_TOP_APLL_DIV2             172
++#define CLK_TOP_APLL_DIV3             173
++#define CLK_TOP_APLL_DIV4             174
++#define CLK_TOP_APLL_DIV5             175
++#define CLK_TOP_APLL_DIV6             176
++#define CLK_TOP_APLL_DIV7             177
++#define CLK_TOP_APLL_DIV_PDN0         178
++#define CLK_TOP_APLL_DIV_PDN1         179
++#define CLK_TOP_APLL_DIV_PDN2         180
++#define CLK_TOP_APLL_DIV_PDN3         181
++#define CLK_TOP_APLL_DIV_PDN4         182
++#define CLK_TOP_APLL_DIV_PDN5         183
++#define CLK_TOP_APLL_DIV_PDN6         184
++#define CLK_TOP_APLL_DIV_PDN7         185
++#define CLK_TOP_NR_CLK                        186
++
++/* INFRACFG */
++
++#define CLK_INFRA_DBGCLK              0
++#define CLK_INFRA_GCE                 1
++#define CLK_INFRA_M4U                 2
++#define CLK_INFRA_KP                  3
++#define CLK_INFRA_AO_SPI0             4
++#define CLK_INFRA_AO_SPI1             5
++#define CLK_INFRA_AO_UART5            6
++#define CLK_INFRA_NR_CLK              7
++
++/* PERICFG */
++
++#define CLK_PERI_NFI                  0
++#define CLK_PERI_THERM                        1
++#define CLK_PERI_PWM0                 2
++#define CLK_PERI_PWM1                 3
++#define CLK_PERI_PWM2                 4
++#define CLK_PERI_PWM3                 5
++#define CLK_PERI_PWM4                 6
++#define CLK_PERI_PWM5                 7
++#define CLK_PERI_PWM6                 8
++#define CLK_PERI_PWM7                 9
++#define CLK_PERI_PWM                  10
++#define CLK_PERI_AP_DMA                       11
++#define CLK_PERI_MSDC30_0             12
++#define CLK_PERI_MSDC30_1             13
++#define CLK_PERI_MSDC30_2             14
++#define CLK_PERI_MSDC30_3             15
++#define CLK_PERI_UART0                        16
++#define CLK_PERI_UART1                        17
++#define CLK_PERI_UART2                        18
++#define CLK_PERI_UART3                        19
++#define CLK_PERI_I2C0                 20
++#define CLK_PERI_I2C1                 21
++#define CLK_PERI_I2C2                 22
++#define CLK_PERI_I2C3                 23
++#define CLK_PERI_I2C4                 24
++#define CLK_PERI_AUXADC                       25
++#define CLK_PERI_SPI0                 26
++#define CLK_PERI_SPI                  27
++#define CLK_PERI_I2C5                 28
++#define CLK_PERI_SPI2                 29
++#define CLK_PERI_SPI3                 30
++#define CLK_PERI_SPI5                 31
++#define CLK_PERI_UART4                        32
++#define CLK_PERI_SFLASH                       33
++#define CLK_PERI_GMAC                 34
++#define CLK_PERI_PCIE0                        35
++#define CLK_PERI_PCIE1                        36
++#define CLK_PERI_GMAC_PCLK            37
++#define CLK_PERI_MSDC50_0_EN          38
++#define CLK_PERI_MSDC30_1_EN          39
++#define CLK_PERI_MSDC30_2_EN          40
++#define CLK_PERI_MSDC30_3_EN          41
++#define CLK_PERI_MSDC50_0_HCLK_EN     42
++#define CLK_PERI_MSDC50_3_HCLK_EN     43
++#define CLK_PERI_NR_CLK                       44
++
++/* MCUCFG */
++
++#define CLK_MCU_MP0_SEL                       0
++#define CLK_MCU_MP2_SEL                       1
++#define CLK_MCU_BUS_SEL                       2
++#define CLK_MCU_NR_CLK                        3
++
++/* MFGCFG */
++
++#define CLK_MFG_BG3D                  0
++#define CLK_MFG_NR_CLK                        1
++
++/* MMSYS */
++
++#define CLK_MM_SMI_COMMON             0
++#define CLK_MM_SMI_LARB0              1
++#define CLK_MM_CAM_MDP                        2
++#define CLK_MM_MDP_RDMA0              3
++#define CLK_MM_MDP_RDMA1              4
++#define CLK_MM_MDP_RSZ0                       5
++#define CLK_MM_MDP_RSZ1                       6
++#define CLK_MM_MDP_RSZ2                       7
++#define CLK_MM_MDP_TDSHP0             8
++#define CLK_MM_MDP_TDSHP1             9
++#define CLK_MM_MDP_CROP                       10
++#define CLK_MM_MDP_WDMA                       11
++#define CLK_MM_MDP_WROT0              12
++#define CLK_MM_MDP_WROT1              13
++#define CLK_MM_FAKE_ENG                       14
++#define CLK_MM_MUTEX_32K              15
++#define CLK_MM_DISP_OVL0              16
++#define CLK_MM_DISP_OVL1              17
++#define CLK_MM_DISP_RDMA0             18
++#define CLK_MM_DISP_RDMA1             19
++#define CLK_MM_DISP_RDMA2             20
++#define CLK_MM_DISP_WDMA0             21
++#define CLK_MM_DISP_WDMA1             22
++#define CLK_MM_DISP_COLOR0            23
++#define CLK_MM_DISP_COLOR1            24
++#define CLK_MM_DISP_AAL                       25
++#define CLK_MM_DISP_GAMMA             26
++#define CLK_MM_DISP_UFOE              27
++#define CLK_MM_DISP_SPLIT0            28
++#define CLK_MM_DISP_OD                        29
++#define CLK_MM_DISP_PWM0_MM           30
++#define CLK_MM_DISP_PWM0_26M          31
++#define CLK_MM_DISP_PWM1_MM           32
++#define CLK_MM_DISP_PWM1_26M          33
++#define CLK_MM_DSI0_ENGINE            34
++#define CLK_MM_DSI0_DIGITAL           35
++#define CLK_MM_DSI1_ENGINE            36
++#define CLK_MM_DSI1_DIGITAL           37
++#define CLK_MM_DPI_PIXEL              38
++#define CLK_MM_DPI_ENGINE             39
++#define CLK_MM_DPI1_PIXEL             40
++#define CLK_MM_DPI1_ENGINE            41
++#define CLK_MM_LVDS_PIXEL             42
++#define CLK_MM_LVDS_CTS                       43
++#define CLK_MM_SMI_LARB4              44
++#define CLK_MM_SMI_COMMON1            45
++#define CLK_MM_SMI_LARB5              46
++#define CLK_MM_MDP_RDMA2              47
++#define CLK_MM_MDP_TDSHP2             48
++#define CLK_MM_DISP_OVL2              49
++#define CLK_MM_DISP_WDMA2             50
++#define CLK_MM_DISP_COLOR2            51
++#define CLK_MM_DISP_AAL1              52
++#define CLK_MM_DISP_OD1                       53
++#define CLK_MM_LVDS1_PIXEL            54
++#define CLK_MM_LVDS1_CTS              55
++#define CLK_MM_SMI_LARB7              56
++#define CLK_MM_MDP_RDMA3              57
++#define CLK_MM_MDP_WROT2              58
++#define CLK_MM_DSI2                   59
++#define CLK_MM_DSI2_DIGITAL           60
++#define CLK_MM_DSI3                   61
++#define CLK_MM_DSI3_DIGITAL           62
++#define CLK_MM_NR_CLK                 63
++
++/* IMGSYS */
++
++#define CLK_IMG_SMI_LARB2             0
++#define CLK_IMG_SENINF_SCAM_EN                1
++#define CLK_IMG_SENINF_CAM_EN         2
++#define CLK_IMG_CAM_SV_EN             3
++#define CLK_IMG_CAM_SV1_EN            4
++#define CLK_IMG_CAM_SV2_EN            5
++#define CLK_IMG_NR_CLK                        6
++
++/* BDPSYS */
++
++#define CLK_BDP_BRIDGE_B              0
++#define CLK_BDP_BRIDGE_DRAM           1
++#define CLK_BDP_LARB_DRAM             2
++#define CLK_BDP_WR_CHANNEL_VDI_PXL    3
++#define CLK_BDP_WR_CHANNEL_VDI_DRAM   4
++#define CLK_BDP_WR_CHANNEL_VDI_B      5
++#define CLK_BDP_MT_B                  6
++#define CLK_BDP_DISPFMT_27M           7
++#define CLK_BDP_DISPFMT_27M_VDOUT     8
++#define CLK_BDP_DISPFMT_27_74_74      9
++#define CLK_BDP_DISPFMT_2FS           10
++#define CLK_BDP_DISPFMT_2FS_2FS74_148 11
++#define CLK_BDP_DISPFMT_B             12
++#define CLK_BDP_VDO_DRAM              13
++#define CLK_BDP_VDO_2FS                       14
++#define CLK_BDP_VDO_B                 15
++#define CLK_BDP_WR_CHANNEL_DI_PXL     16
++#define CLK_BDP_WR_CHANNEL_DI_DRAM    17
++#define CLK_BDP_WR_CHANNEL_DI_B               18
++#define CLK_BDP_NR_AGENT              19
++#define CLK_BDP_NR_DRAM                       20
++#define CLK_BDP_NR_B                  21
++#define CLK_BDP_BRIDGE_RT_B           22
++#define CLK_BDP_BRIDGE_RT_DRAM                23
++#define CLK_BDP_LARB_RT_DRAM          24
++#define CLK_BDP_TVD_TDC                       25
++#define CLK_BDP_TVD_54                        26
++#define CLK_BDP_TVD_CBUS              27
++#define CLK_BDP_NR_CLK                        28
++
++/* VDECSYS */
++
++#define CLK_VDEC_CKEN                 0
++#define CLK_VDEC_LARB1_CKEN           1
++#define CLK_VDEC_IMGRZ_CKEN           2
++#define CLK_VDEC_NR_CLK                       3
++
++/* VENCSYS */
++
++#define CLK_VENC_SMI_COMMON_CON               0
++#define CLK_VENC_VENC                 1
++#define CLK_VENC_SMI_LARB6            2
++#define CLK_VENC_NR_CLK                       3
++
++/* JPGDECSYS */
++
++#define CLK_JPGDEC_JPGDEC1            0
++#define CLK_JPGDEC_JPGDEC             1
++#define CLK_JPGDEC_NR_CLK             2
++
++#endif /* _DT_BINDINGS_CLK_MT2712_H */
+-- 
+2.11.0
+
diff --git a/target/linux/mediatek/patches-4.14/0146-clk-mediatek-Add-MT2712-clock-support.patch b/target/linux/mediatek/patches-4.14/0146-clk-mediatek-Add-MT2712-clock-support.patch
new file mode 100644 (file)
index 0000000..5876541
--- /dev/null
@@ -0,0 +1,2331 @@
+From ec5192303a3938d0972fde3b1f2526d8d6dd02d7 Mon Sep 17 00:00:00 2001
+From: "weiyi.lu@mediatek.com" <weiyi.lu@mediatek.com>
+Date: Mon, 23 Oct 2017 12:10:34 +0800
+Subject: [PATCH 146/224] clk: mediatek: Add MT2712 clock support
+
+Add MT2712 clock support, include topckgen, apmixedsys,
+infracfg, pericfg, mcucfg and subsystem clocks.
+
+Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
+[sboyd@codeaurora.org: Static on top_clk_data]
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+---
+ drivers/clk/mediatek/Kconfig             |   50 ++
+ drivers/clk/mediatek/Makefile            |    8 +
+ drivers/clk/mediatek/clk-mt2712-bdp.c    |  102 +++
+ drivers/clk/mediatek/clk-mt2712-img.c    |   80 ++
+ drivers/clk/mediatek/clk-mt2712-jpgdec.c |   76 ++
+ drivers/clk/mediatek/clk-mt2712-mfg.c    |   75 ++
+ drivers/clk/mediatek/clk-mt2712-mm.c     |  170 ++++
+ drivers/clk/mediatek/clk-mt2712-vdec.c   |   94 ++
+ drivers/clk/mediatek/clk-mt2712-venc.c   |   77 ++
+ drivers/clk/mediatek/clk-mt2712.c        | 1435 ++++++++++++++++++++++++++++++
+ drivers/clk/mediatek/clk-mtk.h           |    2 +
+ drivers/clk/mediatek/clk-pll.c           |   13 +-
+ 12 files changed, 2180 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/clk/mediatek/clk-mt2712-bdp.c
+ create mode 100644 drivers/clk/mediatek/clk-mt2712-img.c
+ create mode 100644 drivers/clk/mediatek/clk-mt2712-jpgdec.c
+ create mode 100644 drivers/clk/mediatek/clk-mt2712-mfg.c
+ create mode 100644 drivers/clk/mediatek/clk-mt2712-mm.c
+ create mode 100644 drivers/clk/mediatek/clk-mt2712-vdec.c
+ create mode 100644 drivers/clk/mediatek/clk-mt2712-venc.c
+ create mode 100644 drivers/clk/mediatek/clk-mt2712.c
+
+diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
+index 28739a9a6e37..300dbb551bf7 100644
+--- a/drivers/clk/mediatek/Kconfig
++++ b/drivers/clk/mediatek/Kconfig
+@@ -50,6 +50,56 @@ config COMMON_CLK_MT2701_BDPSYS
+       ---help---
+         This driver supports Mediatek MT2701 bdpsys clocks.
++config COMMON_CLK_MT2712
++      bool "Clock driver for Mediatek MT2712"
++      depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
++      select COMMON_CLK_MEDIATEK
++      default ARCH_MEDIATEK && ARM64
++      ---help---
++        This driver supports Mediatek MT2712 basic clocks.
++
++config COMMON_CLK_MT2712_BDPSYS
++      bool "Clock driver for Mediatek MT2712 bdpsys"
++      depends on COMMON_CLK_MT2712
++      ---help---
++        This driver supports Mediatek MT2712 bdpsys clocks.
++
++config COMMON_CLK_MT2712_IMGSYS
++      bool "Clock driver for Mediatek MT2712 imgsys"
++      depends on COMMON_CLK_MT2712
++      ---help---
++        This driver supports Mediatek MT2712 imgsys clocks.
++
++config COMMON_CLK_MT2712_JPGDECSYS
++      bool "Clock driver for Mediatek MT2712 jpgdecsys"
++      depends on COMMON_CLK_MT2712
++      ---help---
++        This driver supports Mediatek MT2712 jpgdecsys clocks.
++
++config COMMON_CLK_MT2712_MFGCFG
++      bool "Clock driver for Mediatek MT2712 mfgcfg"
++      depends on COMMON_CLK_MT2712
++      ---help---
++        This driver supports Mediatek MT2712 mfgcfg clocks.
++
++config COMMON_CLK_MT2712_MMSYS
++      bool "Clock driver for Mediatek MT2712 mmsys"
++      depends on COMMON_CLK_MT2712
++      ---help---
++        This driver supports Mediatek MT2712 mmsys clocks.
++
++config COMMON_CLK_MT2712_VDECSYS
++      bool "Clock driver for Mediatek MT2712 vdecsys"
++      depends on COMMON_CLK_MT2712
++      ---help---
++        This driver supports Mediatek MT2712 vdecsys clocks.
++
++config COMMON_CLK_MT2712_VENCSYS
++      bool "Clock driver for Mediatek MT2712 vencsys"
++      depends on COMMON_CLK_MT2712
++      ---help---
++        This driver supports Mediatek MT2712 vencsys clocks.
++
+ config COMMON_CLK_MT6797
+        bool "Clock driver for Mediatek MT6797"
+        depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
+index 2a755b5fb51b..a4e5c47c73a4 100644
+--- a/drivers/clk/mediatek/Makefile
++++ b/drivers/clk/mediatek/Makefile
+@@ -12,5 +12,13 @@ obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
+ obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
+ obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
+ obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o
++obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712.o
++obj-$(CONFIG_COMMON_CLK_MT2712_BDPSYS) += clk-mt2712-bdp.o
++obj-$(CONFIG_COMMON_CLK_MT2712_IMGSYS) += clk-mt2712-img.o
++obj-$(CONFIG_COMMON_CLK_MT2712_JPGDECSYS) += clk-mt2712-jpgdec.o
++obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) += clk-mt2712-mfg.o
++obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o
++obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o
++obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o
+ obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
+ obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
+diff --git a/drivers/clk/mediatek/clk-mt2712-bdp.c b/drivers/clk/mediatek/clk-mt2712-bdp.c
+new file mode 100644
+index 000000000000..5fe4728c076e
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt2712-bdp.c
+@@ -0,0 +1,102 @@
++/*
++ * Copyright (c) 2017 MediaTek Inc.
++ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/platform_device.h>
++
++#include "clk-mtk.h"
++#include "clk-gate.h"
++
++#include <dt-bindings/clock/mt2712-clk.h>
++
++static const struct mtk_gate_regs bdp_cg_regs = {
++      .set_ofs = 0x100,
++      .clr_ofs = 0x100,
++      .sta_ofs = 0x100,
++};
++
++#define GATE_BDP(_id, _name, _parent, _shift) {       \
++              .id = _id,                              \
++              .name = _name,                          \
++              .parent_name = _parent,                 \
++              .regs = &bdp_cg_regs,                   \
++              .shift = _shift,                        \
++              .ops = &mtk_clk_gate_ops_no_setclr,     \
++      }
++
++static const struct mtk_gate bdp_clks[] = {
++      GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0),
++      GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1),
++      GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2),
++      GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3),
++      GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4),
++      GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5),
++      GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9),
++      GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10),
++      GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11),
++      GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12),
++      GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13),
++      GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14),
++      GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15),
++      GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16),
++      GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17),
++      GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18),
++      GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),
++      GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20),
++      GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21),
++      GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22),
++      GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23),
++      GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24),
++      GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25),
++      GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26),
++      GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27),
++      GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28),
++      GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29),
++      GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30),
++};
++
++static int clk_mt2712_bdp_probe(struct platform_device *pdev)
++{
++      struct clk_onecell_data *clk_data;
++      int r;
++      struct device_node *node = pdev->dev.of_node;
++
++      clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK);
++
++      mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
++                      clk_data);
++
++      r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
++
++      if (r != 0)
++              pr_err("%s(): could not register clock provider: %d\n",
++                      __func__, r);
++
++      return r;
++}
++
++static const struct of_device_id of_match_clk_mt2712_bdp[] = {
++      { .compatible = "mediatek,mt2712-bdpsys", },
++      {}
++};
++
++static struct platform_driver clk_mt2712_bdp_drv = {
++      .probe = clk_mt2712_bdp_probe,
++      .driver = {
++              .name = "clk-mt2712-bdp",
++              .of_match_table = of_match_clk_mt2712_bdp,
++      },
++};
++
++builtin_platform_driver(clk_mt2712_bdp_drv);
+diff --git a/drivers/clk/mediatek/clk-mt2712-img.c b/drivers/clk/mediatek/clk-mt2712-img.c
+new file mode 100644
+index 000000000000..139ff55d495e
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt2712-img.c
+@@ -0,0 +1,80 @@
++/*
++ * Copyright (c) 2017 MediaTek Inc.
++ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/platform_device.h>
++
++#include "clk-mtk.h"
++#include "clk-gate.h"
++
++#include <dt-bindings/clock/mt2712-clk.h>
++
++static const struct mtk_gate_regs img_cg_regs = {
++      .set_ofs = 0x0,
++      .clr_ofs = 0x0,
++      .sta_ofs = 0x0,
++};
++
++#define GATE_IMG(_id, _name, _parent, _shift) {       \
++              .id = _id,                              \
++              .name = _name,                          \
++              .parent_name = _parent,                 \
++              .regs = &img_cg_regs,                   \
++              .shift = _shift,                        \
++              .ops = &mtk_clk_gate_ops_no_setclr,     \
++      }
++
++static const struct mtk_gate img_clks[] = {
++      GATE_IMG(CLK_IMG_SMI_LARB2, "img_smi_larb2", "mm_sel", 0),
++      GATE_IMG(CLK_IMG_SENINF_SCAM_EN, "img_scam_en", "csi0", 3),
++      GATE_IMG(CLK_IMG_SENINF_CAM_EN, "img_cam_en", "mm_sel", 8),
++      GATE_IMG(CLK_IMG_CAM_SV_EN, "img_cam_sv_en", "mm_sel", 9),
++      GATE_IMG(CLK_IMG_CAM_SV1_EN, "img_cam_sv1_en", "mm_sel", 10),
++      GATE_IMG(CLK_IMG_CAM_SV2_EN, "img_cam_sv2_en", "mm_sel", 11),
++};
++
++static int clk_mt2712_img_probe(struct platform_device *pdev)
++{
++      struct clk_onecell_data *clk_data;
++      int r;
++      struct device_node *node = pdev->dev.of_node;
++
++      clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
++
++      mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
++                      clk_data);
++
++      r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
++
++      if (r != 0)
++              pr_err("%s(): could not register clock provider: %d\n",
++                      __func__, r);
++
++      return r;
++}
++
++static const struct of_device_id of_match_clk_mt2712_img[] = {
++      { .compatible = "mediatek,mt2712-imgsys", },
++      {}
++};
++
++static struct platform_driver clk_mt2712_img_drv = {
++      .probe = clk_mt2712_img_probe,
++      .driver = {
++              .name = "clk-mt2712-img",
++              .of_match_table = of_match_clk_mt2712_img,
++      },
++};
++
++builtin_platform_driver(clk_mt2712_img_drv);
+diff --git a/drivers/clk/mediatek/clk-mt2712-jpgdec.c b/drivers/clk/mediatek/clk-mt2712-jpgdec.c
+new file mode 100644
+index 000000000000..c7d4aada4892
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt2712-jpgdec.c
+@@ -0,0 +1,76 @@
++/*
++ * Copyright (c) 2017 MediaTek Inc.
++ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/platform_device.h>
++
++#include "clk-mtk.h"
++#include "clk-gate.h"
++
++#include <dt-bindings/clock/mt2712-clk.h>
++
++static const struct mtk_gate_regs jpgdec_cg_regs = {
++      .set_ofs = 0x4,
++      .clr_ofs = 0x8,
++      .sta_ofs = 0x0,
++};
++
++#define GATE_JPGDEC(_id, _name, _parent, _shift) {    \
++              .id = _id,                              \
++              .name = _name,                          \
++              .parent_name = _parent,                 \
++              .regs = &jpgdec_cg_regs,                        \
++              .shift = _shift,                        \
++              .ops = &mtk_clk_gate_ops_setclr_inv,    \
++      }
++
++static const struct mtk_gate jpgdec_clks[] = {
++      GATE_JPGDEC(CLK_JPGDEC_JPGDEC1, "jpgdec_jpgdec1", "jpgdec_sel", 0),
++      GATE_JPGDEC(CLK_JPGDEC_JPGDEC, "jpgdec_jpgdec", "jpgdec_sel", 4),
++};
++
++static int clk_mt2712_jpgdec_probe(struct platform_device *pdev)
++{
++      struct clk_onecell_data *clk_data;
++      int r;
++      struct device_node *node = pdev->dev.of_node;
++
++      clk_data = mtk_alloc_clk_data(CLK_JPGDEC_NR_CLK);
++
++      mtk_clk_register_gates(node, jpgdec_clks, ARRAY_SIZE(jpgdec_clks),
++                      clk_data);
++
++      r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
++
++      if (r != 0)
++              pr_err("%s(): could not register clock provider: %d\n",
++                      __func__, r);
++
++      return r;
++}
++
++static const struct of_device_id of_match_clk_mt2712_jpgdec[] = {
++      { .compatible = "mediatek,mt2712-jpgdecsys", },
++      {}
++};
++
++static struct platform_driver clk_mt2712_jpgdec_drv = {
++      .probe = clk_mt2712_jpgdec_probe,
++      .driver = {
++              .name = "clk-mt2712-jpgdec",
++              .of_match_table = of_match_clk_mt2712_jpgdec,
++      },
++};
++
++builtin_platform_driver(clk_mt2712_jpgdec_drv);
+diff --git a/drivers/clk/mediatek/clk-mt2712-mfg.c b/drivers/clk/mediatek/clk-mt2712-mfg.c
+new file mode 100644
+index 000000000000..570f72d48d4d
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt2712-mfg.c
+@@ -0,0 +1,75 @@
++/*
++ * Copyright (c) 2017 MediaTek Inc.
++ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/platform_device.h>
++
++#include "clk-mtk.h"
++#include "clk-gate.h"
++
++#include <dt-bindings/clock/mt2712-clk.h>
++
++static const struct mtk_gate_regs mfg_cg_regs = {
++      .set_ofs = 0x4,
++      .clr_ofs = 0x8,
++      .sta_ofs = 0x0,
++};
++
++#define GATE_MFG(_id, _name, _parent, _shift) {       \
++              .id = _id,                              \
++              .name = _name,                          \
++              .parent_name = _parent,                 \
++              .regs = &mfg_cg_regs,                   \
++              .shift = _shift,                        \
++              .ops = &mtk_clk_gate_ops_setclr,        \
++      }
++
++static const struct mtk_gate mfg_clks[] = {
++      GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
++};
++
++static int clk_mt2712_mfg_probe(struct platform_device *pdev)
++{
++      struct clk_onecell_data *clk_data;
++      int r;
++      struct device_node *node = pdev->dev.of_node;
++
++      clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
++
++      mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
++                      clk_data);
++
++      r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
++
++      if (r != 0)
++              pr_err("%s(): could not register clock provider: %d\n",
++                      __func__, r);
++
++      return r;
++}
++
++static const struct of_device_id of_match_clk_mt2712_mfg[] = {
++      { .compatible = "mediatek,mt2712-mfgcfg", },
++      {}
++};
++
++static struct platform_driver clk_mt2712_mfg_drv = {
++      .probe = clk_mt2712_mfg_probe,
++      .driver = {
++              .name = "clk-mt2712-mfg",
++              .of_match_table = of_match_clk_mt2712_mfg,
++      },
++};
++
++builtin_platform_driver(clk_mt2712_mfg_drv);
+diff --git a/drivers/clk/mediatek/clk-mt2712-mm.c b/drivers/clk/mediatek/clk-mt2712-mm.c
+new file mode 100644
+index 000000000000..a8b4b6d42488
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt2712-mm.c
+@@ -0,0 +1,170 @@
++/*
++ * Copyright (c) 2017 MediaTek Inc.
++ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/platform_device.h>
++
++#include "clk-mtk.h"
++#include "clk-gate.h"
++
++#include <dt-bindings/clock/mt2712-clk.h>
++
++static const struct mtk_gate_regs mm0_cg_regs = {
++      .set_ofs = 0x104,
++      .clr_ofs = 0x108,
++      .sta_ofs = 0x100,
++};
++
++static const struct mtk_gate_regs mm1_cg_regs = {
++      .set_ofs = 0x114,
++      .clr_ofs = 0x118,
++      .sta_ofs = 0x110,
++};
++
++static const struct mtk_gate_regs mm2_cg_regs = {
++      .set_ofs = 0x224,
++      .clr_ofs = 0x228,
++      .sta_ofs = 0x220,
++};
++
++#define GATE_MM0(_id, _name, _parent, _shift) {       \
++              .id = _id,                              \
++              .name = _name,                          \
++              .parent_name = _parent,                 \
++              .regs = &mm0_cg_regs,                   \
++              .shift = _shift,                        \
++              .ops = &mtk_clk_gate_ops_setclr,        \
++      }
++
++#define GATE_MM1(_id, _name, _parent, _shift) {       \
++              .id = _id,                              \
++              .name = _name,                          \
++              .parent_name = _parent,                 \
++              .regs = &mm1_cg_regs,                   \
++              .shift = _shift,                        \
++              .ops = &mtk_clk_gate_ops_setclr,        \
++      }
++
++#define GATE_MM2(_id, _name, _parent, _shift) {       \
++              .id = _id,                              \
++              .name = _name,                          \
++              .parent_name = _parent,                 \
++              .regs = &mm2_cg_regs,                   \
++              .shift = _shift,                        \
++              .ops = &mtk_clk_gate_ops_setclr,        \
++      }
++
++static const struct mtk_gate mm_clks[] = {
++      /* MM0 */
++      GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
++      GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
++      GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
++      GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
++      GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
++      GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
++      GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
++      GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
++      GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
++      GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
++      GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10),
++      GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
++      GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
++      GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
++      GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
++      GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15),
++      GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
++      GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
++      GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
++      GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
++      GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
++      GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
++      GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
++      GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
++      GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
++      GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
++      GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
++      GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
++      GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
++      GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
++      /* MM1 */
++      GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0),
++      GATE_MM1(CLK_MM_DISP_PWM0_26M, "mm_pwm0_26m", "pwm_sel", 1),
++      GATE_MM1(CLK_MM_DISP_PWM1_MM, "mm_pwm1_mm", "mm_sel", 2),
++      GATE_MM1(CLK_MM_DISP_PWM1_26M, "mm_pwm1_26m", "pwm_sel", 3),
++      GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
++      GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_lntc", 5),
++      GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
++      GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_lntc", 7),
++      GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "vpll_dpix", 8),
++      GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
++      GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "vpll3_dpix", 10),
++      GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
++      GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "vpll_dpix", 16),
++      GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx", 17),
++      GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
++      GATE_MM1(CLK_MM_SMI_COMMON1, "mm_smi_common1", "mm_sel", 21),
++      GATE_MM1(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 22),
++      GATE_MM1(CLK_MM_MDP_RDMA2, "mm_mdp_rdma2", "mm_sel", 23),
++      GATE_MM1(CLK_MM_MDP_TDSHP2, "mm_mdp_tdshp2", "mm_sel", 24),
++      GATE_MM1(CLK_MM_DISP_OVL2, "mm_disp_ovl2", "mm_sel", 25),
++      GATE_MM1(CLK_MM_DISP_WDMA2, "mm_disp_wdma2", "mm_sel", 26),
++      GATE_MM1(CLK_MM_DISP_COLOR2, "mm_disp_color2", "mm_sel", 27),
++      GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1", "mm_sel", 28),
++      GATE_MM1(CLK_MM_DISP_OD1, "mm_disp_od1", "mm_sel", 29),
++      GATE_MM1(CLK_MM_LVDS1_PIXEL, "mm_lvds1_pixel", "vpll3_dpix", 30),
++      GATE_MM1(CLK_MM_LVDS1_CTS, "mm_lvds1_cts", "lvdstx3", 31),
++      /* MM2 */
++      GATE_MM2(CLK_MM_SMI_LARB7, "mm_smi_larb7", "mm_sel", 0),
++      GATE_MM2(CLK_MM_MDP_RDMA3, "mm_mdp_rdma3", "mm_sel", 1),
++      GATE_MM2(CLK_MM_MDP_WROT2, "mm_mdp_wrot2", "mm_sel", 2),
++      GATE_MM2(CLK_MM_DSI2, "mm_dsi2", "mm_sel", 3),
++      GATE_MM2(CLK_MM_DSI2_DIGITAL, "mm_dsi2_digital", "dsi0_lntc", 4),
++      GATE_MM2(CLK_MM_DSI3, "mm_dsi3", "mm_sel", 5),
++      GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6),
++};
++
++static int clk_mt2712_mm_probe(struct platform_device *pdev)
++{
++      struct clk_onecell_data *clk_data;
++      int r;
++      struct device_node *node = pdev->dev.of_node;
++
++      clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
++
++      mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
++                      clk_data);
++
++      r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
++
++      if (r != 0)
++              pr_err("%s(): could not register clock provider: %d\n",
++                      __func__, r);
++
++      return r;
++}
++
++static const struct of_device_id of_match_clk_mt2712_mm[] = {
++      { .compatible = "mediatek,mt2712-mmsys", },
++      {}
++};
++
++static struct platform_driver clk_mt2712_mm_drv = {
++      .probe = clk_mt2712_mm_probe,
++      .driver = {
++              .name = "clk-mt2712-mm",
++              .of_match_table = of_match_clk_mt2712_mm,
++      },
++};
++
++builtin_platform_driver(clk_mt2712_mm_drv);
+diff --git a/drivers/clk/mediatek/clk-mt2712-vdec.c b/drivers/clk/mediatek/clk-mt2712-vdec.c
+new file mode 100644
+index 000000000000..55c64ee8cc91
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt2712-vdec.c
+@@ -0,0 +1,94 @@
++/*
++ * Copyright (c) 2017 MediaTek Inc.
++ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/platform_device.h>
++
++#include "clk-mtk.h"
++#include "clk-gate.h"
++
++#include <dt-bindings/clock/mt2712-clk.h>
++
++static const struct mtk_gate_regs vdec0_cg_regs = {
++      .set_ofs = 0x0,
++      .clr_ofs = 0x4,
++      .sta_ofs = 0x0,
++};
++
++static const struct mtk_gate_regs vdec1_cg_regs = {
++      .set_ofs = 0x8,
++      .clr_ofs = 0xc,
++      .sta_ofs = 0x8,
++};
++
++#define GATE_VDEC0(_id, _name, _parent, _shift) {     \
++              .id = _id,                              \
++              .name = _name,                          \
++              .parent_name = _parent,                 \
++              .regs = &vdec0_cg_regs,                 \
++              .shift = _shift,                        \
++              .ops = &mtk_clk_gate_ops_setclr_inv,    \
++      }
++
++#define GATE_VDEC1(_id, _name, _parent, _shift) {     \
++              .id = _id,                              \
++              .name = _name,                          \
++              .parent_name = _parent,                 \
++              .regs = &vdec1_cg_regs,                 \
++              .shift = _shift,                        \
++              .ops = &mtk_clk_gate_ops_setclr_inv,    \
++      }
++
++static const struct mtk_gate vdec_clks[] = {
++      /* VDEC0 */
++      GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
++      /* VDEC1 */
++      GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0),
++      GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1),
++};
++
++static int clk_mt2712_vdec_probe(struct platform_device *pdev)
++{
++      struct clk_onecell_data *clk_data;
++      int r;
++      struct device_node *node = pdev->dev.of_node;
++
++      clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
++
++      mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
++                      clk_data);
++
++      r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
++
++      if (r != 0)
++              pr_err("%s(): could not register clock provider: %d\n",
++                      __func__, r);
++
++      return r;
++}
++
++static const struct of_device_id of_match_clk_mt2712_vdec[] = {
++      { .compatible = "mediatek,mt2712-vdecsys", },
++      {}
++};
++
++static struct platform_driver clk_mt2712_vdec_drv = {
++      .probe = clk_mt2712_vdec_probe,
++      .driver = {
++              .name = "clk-mt2712-vdec",
++              .of_match_table = of_match_clk_mt2712_vdec,
++      },
++};
++
++builtin_platform_driver(clk_mt2712_vdec_drv);
+diff --git a/drivers/clk/mediatek/clk-mt2712-venc.c b/drivers/clk/mediatek/clk-mt2712-venc.c
+new file mode 100644
+index 000000000000..ccbfe98777c8
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt2712-venc.c
+@@ -0,0 +1,77 @@
++/*
++ * Copyright (c) 2017 MediaTek Inc.
++ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/platform_device.h>
++
++#include "clk-mtk.h"
++#include "clk-gate.h"
++
++#include <dt-bindings/clock/mt2712-clk.h>
++
++static const struct mtk_gate_regs venc_cg_regs = {
++      .set_ofs = 0x4,
++      .clr_ofs = 0x8,
++      .sta_ofs = 0x0,
++};
++
++#define GATE_VENC(_id, _name, _parent, _shift) {      \
++              .id = _id,                              \
++              .name = _name,                          \
++              .parent_name = _parent,                 \
++              .regs = &venc_cg_regs,                  \
++              .shift = _shift,                        \
++              .ops = &mtk_clk_gate_ops_setclr_inv,    \
++      }
++
++static const struct mtk_gate venc_clks[] = {
++      GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0),
++      GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
++      GATE_VENC(CLK_VENC_SMI_LARB6, "venc_smi_larb6", "jpgdec_sel", 12),
++};
++
++static int clk_mt2712_venc_probe(struct platform_device *pdev)
++{
++      struct clk_onecell_data *clk_data;
++      int r;
++      struct device_node *node = pdev->dev.of_node;
++
++      clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
++
++      mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
++                      clk_data);
++
++      r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
++
++      if (r != 0)
++              pr_err("%s(): could not register clock provider: %d\n",
++                      __func__, r);
++
++      return r;
++}
++
++static const struct of_device_id of_match_clk_mt2712_venc[] = {
++      { .compatible = "mediatek,mt2712-vencsys", },
++      {}
++};
++
++static struct platform_driver clk_mt2712_venc_drv = {
++      .probe = clk_mt2712_venc_probe,
++      .driver = {
++              .name = "clk-mt2712-venc",
++              .of_match_table = of_match_clk_mt2712_venc,
++      },
++};
++
++builtin_platform_driver(clk_mt2712_venc_drv);
+diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
+new file mode 100644
+index 000000000000..498d13799388
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt2712.c
+@@ -0,0 +1,1435 @@
++/*
++ * Copyright (c) 2017 MediaTek Inc.
++ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/mfd/syscon.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++
++#include "clk-mtk.h"
++#include "clk-gate.h"
++
++#include <dt-bindings/clock/mt2712-clk.h>
++
++static DEFINE_SPINLOCK(mt2712_clk_lock);
++
++static const struct mtk_fixed_clk top_fixed_clks[] = {
++      FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000),
++      FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000),
++      FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000),
++      FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000),
++      FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000),
++      FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000),
++      FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000),
++      FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000),
++      FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768),
++      FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747),
++      FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000),
++      FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000),
++};
++
++static const struct mtk_fixed_factor top_early_divs[] = {
++      FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1,
++              1),
++      FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1,
++              2),
++};
++
++static const struct mtk_fixed_factor top_divs[] = {
++      FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1,
++              1),
++      FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1,
++              2),
++      FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1,
++              3),
++      FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1,
++              1),
++      FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1,
++              1),
++      FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
++              2),
++      FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1,
++              2),
++      FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1,
++              4),
++      FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1,
++              8),
++      FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1,
++              16),
++      FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1,
++              3),
++      FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1,
++              2),
++      FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1,
++              4),
++      FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1,
++              5),
++      FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
++              2),
++      FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1,
++              4),
++      FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1,
++              7),
++      FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1,
++              2),
++      FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1,
++              4),
++      FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1,
++              1),
++      FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1,
++              7),
++      FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1,
++              26),
++      FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1,
++              52),
++      FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1,
++              104),
++      FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1,
++              208),
++      FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
++              2),
++      FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1,
++              2),
++      FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1,
++              4),
++      FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1,
++              8),
++      FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1,
++              3),
++      FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1,
++              2),
++      FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
++              4),
++      FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1,
++              8),
++      FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1,
++              5),
++      FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1,
++              2),
++      FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1,
++              4),
++      FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1,
++              8),
++      FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1,
++              1),
++      FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1,
++              1),
++      FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1,
++              1),
++      FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1,
++              1),
++      FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1,
++              1),
++      FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1,
++              1),
++      FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1,
++              1),
++      FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1,
++              2),
++      FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1,
++              4),
++      FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1,
++              8),
++      FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1,
++              16),
++      FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1,
++              1),
++      FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1,
++              2),
++      FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1,
++              4),
++      FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1,
++              8),
++      FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1,
++              16),
++      FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1,
++              1),
++      FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1,
++              2),
++      FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1,
++              4),
++      FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1,
++              8),
++      FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1,
++              1),
++      FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1,
++              2),
++      FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1,
++              4),
++      FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1,
++              8),
++      FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1,
++              1),
++      FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1,
++              1),
++      FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1,
++              1),
++      FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1,
++              2),
++      FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1,
++              1),
++      FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1,
++              2),
++      FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1,
++              1),
++      FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1,
++              2),
++      FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1,
++              1),
++      FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1,
++              2),
++      FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1,
++              1),
++      FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
++              2),
++      FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1,
++              4),
++      FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1,
++              8),
++      FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1,
++              1),
++      FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1,
++              2),
++      FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1,
++              4),
++      FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1,
++              1),
++      FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1,
++              2),
++      FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1,
++              4),
++      FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1,
++              1),
++      FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1,
++              2),
++      FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1,
++              4),
++      FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1,
++              4),
++};
++
++static const char * const axi_parents[] = {
++      "clk26m",
++      "syspll1_d2",
++      "syspll_d5",
++      "syspll1_d4",
++      "univpll_d5",
++      "univpll2_d2",
++      "msdcpll2_ck"
++};
++
++static const char * const mem_parents[] = {
++      "clk26m",
++      "dmpll_ck"
++};
++
++static const char * const mm_parents[] = {
++      "clk26m",
++      "vencpll_ck",
++      "syspll_d3",
++      "syspll1_d2",
++      "syspll_d5",
++      "syspll1_d4",
++      "univpll1_d2",
++      "univpll2_d2"
++};
++
++static const char * const pwm_parents[] = {
++      "clk26m",
++      "univpll2_d4",
++      "univpll3_d2",
++      "univpll1_d4"
++};
++
++static const char * const vdec_parents[] = {
++      "clk26m",
++      "vcodecpll_ck",
++      "tvdpll_429m",
++      "univpll_d3",
++      "vencpll_ck",
++      "syspll_d3",
++      "univpll1_d2",
++      "mmpll_d2",
++      "syspll3_d2",
++      "tvdpll_ck"
++};
++
++static const char * const venc_parents[] = {
++      "clk26m",
++      "univpll1_d2",
++      "mmpll_d2",
++      "tvdpll_d2",
++      "syspll1_d2",
++      "univpll_d5",
++      "vcodecpll_d2",
++      "univpll2_d2",
++      "syspll3_d2"
++};
++
++static const char * const mfg_parents[] = {
++      "clk26m",
++      "mmpll_ck",
++      "univpll_d3",
++      "clk26m",
++      "clk26m",
++      "clk26m",
++      "clk26m",
++      "clk26m",
++      "clk26m",
++      "syspll_d3",
++      "syspll1_d2",
++      "syspll_d5",
++      "univpll_d3",
++      "univpll1_d2",
++      "univpll_d5",
++      "univpll2_d2"
++};
++
++static const char * const camtg_parents[] = {
++      "clk26m",
++      "univpll_d52",
++      "univpll_d208",
++      "univpll_d104",
++      "clk26m_d2",
++      "univpll_d26",
++      "univpll2_d8",
++      "syspll3_d4",
++      "syspll3_d2",
++      "univpll1_d4",
++      "univpll2_d2"
++};
++
++static const char * const uart_parents[] = {
++      "clk26m",
++      "univpll2_d8"
++};
++
++static const char * const spi_parents[] = {
++      "clk26m",
++      "univpll2_d4",
++      "univpll1_d4",
++      "univpll2_d2",
++      "univpll3_d2",
++      "univpll1_d8"
++};
++
++static const char * const usb20_parents[] = {
++      "clk26m",
++      "univpll1_d8",
++      "univpll3_d4"
++};
++
++static const char * const usb30_parents[] = {
++      "clk26m",
++      "univpll3_d2",
++      "univpll3_d4",
++      "univpll2_d4"
++};
++
++static const char * const msdc50_0_h_parents[] = {
++      "clk26m",
++      "syspll1_d2",
++      "syspll2_d2",
++      "syspll4_d2",
++      "univpll_d5",
++      "univpll1_d4"
++};
++
++static const char * const msdc50_0_parents[] = {
++      "clk26m",
++      "msdcpll_ck",
++      "msdcpll_d2",
++      "univpll1_d4",
++      "syspll2_d2",
++      "msdcpll_d4",
++      "vencpll_d2",
++      "univpll1_d2",
++      "msdcpll2_ck",
++      "msdcpll2_d2",
++      "msdcpll2_d4"
++};
++
++static const char * const msdc30_1_parents[] = {
++      "clk26m",
++      "univpll2_d2",
++      "msdcpll_d2",
++      "univpll1_d4",
++      "syspll2_d2",
++      "univpll_d7",
++      "vencpll_d2"
++};
++
++static const char * const msdc30_3_parents[] = {
++      "clk26m",
++      "msdcpll2_ck",
++      "msdcpll2_d2",
++      "univpll2_d2",
++      "msdcpll2_d4",
++      "univpll1_d4",
++      "syspll2_d2",
++      "syspll_d7",
++      "univpll_d7",
++      "vencpll_d2",
++      "msdcpll_ck",
++      "msdcpll_d2",
++      "msdcpll_d4"
++};
++
++static const char * const audio_parents[] = {
++      "clk26m",
++      "syspll3_d4",
++      "syspll4_d4",
++      "syspll1_d16"
++};
++
++static const char * const aud_intbus_parents[] = {
++      "clk26m",
++      "syspll1_d4",
++      "syspll4_d2",
++      "univpll3_d2",
++      "univpll2_d8",
++      "syspll3_d2",
++      "syspll3_d4"
++};
++
++static const char * const pmicspi_parents[] = {
++      "clk26m",
++      "syspll1_d8",
++      "syspll3_d4",
++      "syspll1_d16",
++      "univpll3_d4",
++      "univpll_d26",
++      "syspll3_d4"
++};
++
++static const char * const dpilvds1_parents[] = {
++      "clk26m",
++      "lvdspll2_ck",
++      "lvdspll2_d2",
++      "lvdspll2_d4",
++      "lvdspll2_d8",
++      "clkfpc"
++};
++
++static const char * const atb_parents[] = {
++      "clk26m",
++      "syspll1_d2",
++      "univpll_d5",
++      "syspll_d5"
++};
++
++static const char * const nr_parents[] = {
++      "clk26m",
++      "univpll1_d4",
++      "syspll2_d2",
++      "syspll1_d4",
++      "univpll1_d8",
++      "univpll3_d2",
++      "univpll2_d2",
++      "syspll_d5"
++};
++
++static const char * const nfi2x_parents[] = {
++      "clk26m",
++      "syspll4_d4",
++      "univpll3_d4",
++      "univpll1_d8",
++      "syspll2_d4",
++      "univpll3_d2",
++      "syspll_d7",
++      "syspll2_d2",
++      "univpll2_d2",
++      "syspll_d5",
++      "syspll1_d2"
++};
++
++static const char * const irda_parents[] = {
++      "clk26m",
++      "univpll2_d4",
++      "syspll2_d4",
++      "univpll2_d8"
++};
++
++static const char * const cci400_parents[] = {
++      "clk26m",
++      "vencpll_ck",
++      "armca35pll_600m",
++      "armca35pll_400m",
++      "univpll_d2",
++      "syspll_d2",
++      "msdcpll_ck",
++      "univpll_d3"
++};
++
++static const char * const aud_1_parents[] = {
++      "clk26m",
++      "apll1_ck",
++      "univpll2_d4",
++      "univpll2_d8"
++};
++
++static const char * const aud_2_parents[] = {
++      "clk26m",
++      "apll2_ck",
++      "univpll2_d4",
++      "univpll2_d8"
++};
++
++static const char * const mem_mfg_parents[] = {
++      "clk26m",
++      "mmpll_ck",
++      "univpll_d3"
++};
++
++static const char * const axi_mfg_parents[] = {
++      "clk26m",
++      "axi_sel",
++      "univpll_d5"
++};
++
++static const char * const scam_parents[] = {
++      "clk26m",
++      "syspll3_d2",
++      "univpll2_d4",
++      "syspll2_d4"
++};
++
++static const char * const nfiecc_parents[] = {
++      "clk26m",
++      "nfi2x_sel",
++      "syspll_d7",
++      "syspll2_d2",
++      "univpll2_d2",
++      "univpll_d5",
++      "syspll1_d2"
++};
++
++static const char * const pe2_mac_p0_parents[] = {
++      "clk26m",
++      "syspll1_d8",
++      "syspll4_d2",
++      "syspll2_d4",
++      "univpll2_d4",
++      "syspll3_d2"
++};
++
++static const char * const dpilvds_parents[] = {
++      "clk26m",
++      "lvdspll_ck",
++      "lvdspll_d2",
++      "lvdspll_d4",
++      "lvdspll_d8",
++      "clkfpc"
++};
++
++static const char * const hdcp_parents[] = {
++      "clk26m",
++      "syspll4_d2",
++      "syspll3_d4",
++      "univpll2_d4"
++};
++
++static const char * const hdcp_24m_parents[] = {
++      "clk26m",
++      "univpll_d26",
++      "univpll_d52",
++      "univpll2_d8"
++};
++
++static const char * const rtc_parents[] = {
++      "clkrtc_int",
++      "clkrtc_ext",
++      "clk26m",
++      "univpll3_d8"
++};
++
++static const char * const spinor_parents[] = {
++      "clk26m",
++      "clk26m_d2",
++      "syspll4_d4",
++      "univpll2_d8",
++      "univpll3_d4",
++      "syspll4_d2",
++      "syspll2_d4",
++      "univpll2_d4",
++      "etherpll_125m",
++      "syspll1_d4"
++};
++
++static const char * const apll_parents[] = {
++      "clk26m",
++      "apll1_ck",
++      "apll1_d2",
++      "apll1_d4",
++      "apll1_d8",
++      "apll1_d16",
++      "apll2_ck",
++      "apll2_d2",
++      "apll2_d4",
++      "apll2_d8",
++      "apll2_d16",
++      "clk26m",
++      "clk26m"
++};
++
++static const char * const a1sys_hp_parents[] = {
++      "clk26m",
++      "apll1_ck",
++      "apll1_d2",
++      "apll1_d4",
++      "apll1_d8"
++};
++
++static const char * const a2sys_hp_parents[] = {
++      "clk26m",
++      "apll2_ck",
++      "apll2_d2",
++      "apll2_d4",
++      "apll2_d8"
++};
++
++static const char * const asm_l_parents[] = {
++      "clk26m",
++      "univpll2_d4",
++      "univpll2_d2",
++      "syspll_d5"
++};
++
++static const char * const i2so1_parents[] = {
++      "clk26m",
++      "apll1_ck",
++      "apll2_ck"
++};
++
++static const char * const ether_125m_parents[] = {
++      "clk26m",
++      "etherpll_125m",
++      "univpll3_d2"
++};
++
++static const char * const ether_50m_parents[] = {
++      "clk26m",
++      "etherpll_50m",
++      "univpll_d26",
++      "univpll3_d4"
++};
++
++static const char * const jpgdec_parents[] = {
++      "clk26m",
++      "univpll_d3",
++      "tvdpll_429m",
++      "vencpll_ck",
++      "syspll_d3",
++      "vcodecpll_ck",
++      "univpll1_d2",
++      "armca35pll_400m",
++      "tvdpll_429m_d2",
++      "tvdpll_429m_d4"
++};
++
++static const char * const spislv_parents[] = {
++      "clk26m",
++      "univpll2_d4",
++      "univpll1_d4",
++      "univpll2_d2",
++      "univpll3_d2",
++      "univpll1_d8",
++      "univpll1_d2",
++      "univpll_d5"
++};
++
++static const char * const ether_parents[] = {
++      "clk26m",
++      "etherpll_50m",
++      "univpll_d26"
++};
++
++static const char * const di_parents[] = {
++      "clk26m",
++      "tvdpll_d2",
++      "tvdpll_d4",
++      "tvdpll_d8",
++      "vencpll_ck",
++      "vencpll_d2",
++      "cvbs",
++      "cvbs_d2"
++};
++
++static const char * const tvd_parents[] = {
++      "clk26m",
++      "cvbs_d2",
++      "univpll2_d8"
++};
++
++static const char * const i2c_parents[] = {
++      "clk26m",
++      "univpll_d26",
++      "univpll2_d4",
++      "univpll3_d2",
++      "univpll1_d4"
++};
++
++static const char * const msdc0p_aes_parents[] = {
++      "clk26m",
++      "msdcpll_ck",
++      "univpll_d3",
++      "vcodecpll_ck"
++};
++
++static const char * const cmsys_parents[] = {
++      "clk26m",
++      "univpll_d3",
++      "syspll_d3",
++      "syspll1_d2",
++      "syspll2_d2"
++};
++
++static const char * const gcpu_parents[] = {
++      "clk26m",
++      "syspll_d3",
++      "syspll1_d2",
++      "univpll1_d2",
++      "univpll_d5",
++      "univpll3_d2",
++      "univpll_d3"
++};
++
++static const char * const aud_apll1_parents[] = {
++      "apll1",
++      "clkaud_ext_i_1"
++};
++
++static const char * const aud_apll2_parents[] = {
++      "apll2",
++      "clkaud_ext_i_2"
++};
++
++static const char * const audull_vtx_parents[] = {
++      "d2a_ulclk_6p5m",
++      "clkaud_ext_i_0"
++};
++
++static struct mtk_composite top_muxes[] = {
++      /* CLK_CFG_0 */
++      MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
++              7, CLK_IS_CRITICAL),
++      MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
++              15, CLK_IS_CRITICAL),
++      MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",
++              mm_parents, 0x040, 24, 3, 31),
++      /* CLK_CFG_1 */
++      MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel",
++              pwm_parents, 0x050, 0, 2, 7),
++      MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel",
++              vdec_parents, 0x050, 8, 4, 15),
++      MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel",
++              venc_parents, 0x050, 16, 4, 23),
++      MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel",
++              mfg_parents, 0x050, 24, 4, 31),
++      /* CLK_CFG_2 */
++      MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel",
++              camtg_parents, 0x060, 0, 4, 7),
++      MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
++              uart_parents, 0x060, 8, 1, 15),
++      MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",
++              spi_parents, 0x060, 16, 3, 23),
++      MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel",
++              usb20_parents, 0x060, 24, 2, 31),
++      /* CLK_CFG_3 */
++      MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel",
++              usb30_parents, 0x070, 0, 2, 7),
++      MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel",
++              msdc50_0_h_parents, 0x070, 8, 3, 15),
++      MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
++              msdc50_0_parents, 0x070, 16, 4, 23),
++      MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
++              msdc30_1_parents, 0x070, 24, 3, 31),
++      /* CLK_CFG_4 */
++      MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
++              msdc30_1_parents, 0x080, 0, 3, 7),
++      MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel",
++              msdc30_3_parents, 0x080, 8, 4, 15),
++      MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel",
++              audio_parents, 0x080, 16, 2, 23),
++      MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
++              aud_intbus_parents, 0x080, 24, 3, 31),
++      /* CLK_CFG_5 */
++      MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel",
++              pmicspi_parents, 0x090, 0, 3, 7),
++      MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel",
++              dpilvds1_parents, 0x090, 8, 3, 15),
++      MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel",
++              atb_parents, 0x090, 16, 2, 23),
++      MUX_GATE(CLK_TOP_NR_SEL, "nr_sel",
++              nr_parents, 0x090, 24, 3, 31),
++      /* CLK_CFG_6 */
++      MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel",
++              nfi2x_parents, 0x0a0, 0, 4, 7),
++      MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel",
++              irda_parents, 0x0a0, 8, 2, 15),
++      MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel",
++              cci400_parents, 0x0a0, 16, 3, 23),
++      MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel",
++              aud_1_parents, 0x0a0, 24, 2, 31),
++      /* CLK_CFG_7 */
++      MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel",
++              aud_2_parents, 0x0b0, 0, 2, 7),
++      MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel",
++              mem_mfg_parents, 0x0b0, 8, 2, 15),
++      MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel",
++              axi_mfg_parents, 0x0b0, 16, 2, 23),
++      MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel",
++              scam_parents, 0x0b0, 24, 2, 31),
++      /* CLK_CFG_8 */
++      MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel",
++              nfiecc_parents, 0x0c0, 0, 3, 7),
++      MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel",
++              pe2_mac_p0_parents, 0x0c0, 8, 3, 15),
++      MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel",
++              pe2_mac_p0_parents, 0x0c0, 16, 3, 23),
++      MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel",
++              dpilvds_parents, 0x0c0, 24, 3, 31),
++      /* CLK_CFG_9 */
++      MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel",
++              msdc50_0_h_parents, 0x0d0, 0, 3, 7),
++      MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel",
++              hdcp_parents, 0x0d0, 8, 2, 15),
++      MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel",
++              hdcp_24m_parents, 0x0d0, 16, 2, 23),
++      MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2,
++              31, CLK_IS_CRITICAL),
++      /* CLK_CFG_10 */
++      MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel",
++              spinor_parents, 0x500, 0, 4, 7),
++      MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel",
++              apll_parents, 0x500, 8, 4, 15),
++      MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel",
++              apll_parents, 0x500, 16, 4, 23),
++      MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel",
++              a1sys_hp_parents, 0x500, 24, 3, 31),
++      /* CLK_CFG_11 */
++      MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel",
++              a2sys_hp_parents, 0x510, 0, 3, 7),
++      MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel",
++              asm_l_parents, 0x510, 8, 2, 15),
++      MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel",
++              asm_l_parents, 0x510, 16, 2, 23),
++      MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel",
++              asm_l_parents, 0x510, 24, 2, 31),
++      /* CLK_CFG_12 */
++      MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel",
++              i2so1_parents, 0x520, 0, 2, 7),
++      MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel",
++              i2so1_parents, 0x520, 8, 2, 15),
++      MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel",
++              i2so1_parents, 0x520, 16, 2, 23),
++      MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel",
++              i2so1_parents, 0x520, 24, 2, 31),
++      /* CLK_CFG_13 */
++      MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel",
++              i2so1_parents, 0x530, 0, 2, 7),
++      MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel",
++              i2so1_parents, 0x530, 8, 2, 15),
++      MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel",
++              i2so1_parents, 0x530, 16, 2, 23),
++      MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel",
++              i2so1_parents, 0x530, 24, 2, 31),
++      /* CLK_CFG_14 */
++      MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel",
++              ether_125m_parents, 0x540, 0, 2, 7),
++      MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel",
++              ether_50m_parents, 0x540, 8, 2, 15),
++      MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel",
++              jpgdec_parents, 0x540, 16, 4, 23),
++      MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel",
++              spislv_parents, 0x540, 24, 3, 31),
++      /* CLK_CFG_15 */
++      MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel",
++              ether_parents, 0x550, 0, 2, 7),
++      MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel",
++              camtg_parents, 0x550, 8, 4, 15),
++      MUX_GATE(CLK_TOP_DI_SEL, "di_sel",
++              di_parents, 0x550, 16, 3, 23),
++      MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel",
++              tvd_parents, 0x550, 24, 2, 31),
++      /* CLK_CFG_16 */
++      MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel",
++              i2c_parents, 0x560, 0, 3, 7),
++      MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel",
++              pwm_parents, 0x560, 8, 2, 15),
++      MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel",
++              msdc0p_aes_parents, 0x560, 16, 2, 23),
++      MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel",
++              cmsys_parents, 0x560, 24, 3, 31),
++      /* CLK_CFG_17 */
++      MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel",
++              gcpu_parents, 0x570, 0, 3, 7),
++      /* CLK_AUDDIV_4 */
++      MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel",
++              aud_apll1_parents, 0x134, 0, 1),
++      MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel",
++              aud_apll2_parents, 0x134, 1, 1),
++      MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel",
++              audull_vtx_parents, 0x134, 31, 1),
++};
++
++static const char * const mcu_mp0_parents[] = {
++      "clk26m",
++      "armca35pll_ck",
++      "f_mp0_pll1_ck",
++      "f_mp0_pll2_ck"
++};
++
++static const char * const mcu_mp2_parents[] = {
++      "clk26m",
++      "armca72pll_ck",
++      "f_big_pll1_ck",
++      "f_big_pll2_ck"
++};
++
++static const char * const mcu_bus_parents[] = {
++      "clk26m",
++      "cci400_sel",
++      "f_bus_pll1_ck",
++      "f_bus_pll2_ck"
++};
++
++static struct mtk_composite mcu_muxes[] = {
++      /* mp0_pll_divider_cfg */
++      MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0,
++              9, 2, -1, CLK_IS_CRITICAL),
++      /* mp2_pll_divider_cfg */
++      MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8,
++              9, 2, -1, CLK_IS_CRITICAL),
++      /* bus_pll_divider_cfg */
++      MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
++              9, 2, -1, CLK_IS_CRITICAL),
++};
++
++static const struct mtk_clk_divider top_adj_divs[] = {
++      DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8),
++      DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8),
++      DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8),
++      DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8),
++      DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8),
++      DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8),
++      DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8),
++      DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8),
++};
++
++static const struct mtk_gate_regs top_cg_regs = {
++      .set_ofs = 0x120,
++      .clr_ofs = 0x120,
++      .sta_ofs = 0x120,
++};
++
++#define GATE_TOP(_id, _name, _parent, _shift) {       \
++              .id = _id,                              \
++              .name = _name,                          \
++              .parent_name = _parent,                 \
++              .regs = &top_cg_regs,                   \
++              .shift = _shift,                        \
++              .ops = &mtk_clk_gate_ops_no_setclr,     \
++      }
++
++static const struct mtk_gate top_clks[] = {
++      GATE_TOP(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
++      GATE_TOP(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
++      GATE_TOP(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
++      GATE_TOP(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
++      GATE_TOP(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
++      GATE_TOP(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
++      GATE_TOP(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
++      GATE_TOP(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
++};
++
++static const struct mtk_gate_regs infra_cg_regs = {
++      .set_ofs = 0x40,
++      .clr_ofs = 0x44,
++      .sta_ofs = 0x40,
++};
++
++#define GATE_INFRA(_id, _name, _parent, _shift) {     \
++              .id = _id,                              \
++              .name = _name,                          \
++              .parent_name = _parent,                 \
++              .regs = &infra_cg_regs,                 \
++              .shift = _shift,                        \
++              .ops = &mtk_clk_gate_ops_setclr,        \
++      }
++
++static const struct mtk_gate infra_clks[] = {
++      GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
++      GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
++      GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
++      GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
++      GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24),
++      GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25),
++      GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26),
++};
++
++static const struct mtk_gate_regs peri0_cg_regs = {
++      .set_ofs = 0x8,
++      .clr_ofs = 0x10,
++      .sta_ofs = 0x18,
++};
++
++static const struct mtk_gate_regs peri1_cg_regs = {
++      .set_ofs = 0xc,
++      .clr_ofs = 0x14,
++      .sta_ofs = 0x1c,
++};
++
++static const struct mtk_gate_regs peri2_cg_regs = {
++      .set_ofs = 0x42c,
++      .clr_ofs = 0x42c,
++      .sta_ofs = 0x42c,
++};
++
++#define GATE_PERI0(_id, _name, _parent, _shift) {     \
++              .id = _id,                              \
++              .name = _name,                          \
++              .parent_name = _parent,                 \
++              .regs = &peri0_cg_regs,                 \
++              .shift = _shift,