ramips: drop linux 4.9 support
authorFelix Fietkau <nbd@nbd.name>
Fri, 6 Apr 2018 16:20:46 +0000 (18:20 +0200)
committerFelix Fietkau <nbd@nbd.name>
Fri, 6 Apr 2018 16:21:45 +0000 (18:21 +0200)
4.14 has been tested a lot by a number of users, and we want to use it
for the release.

Signed-off-by: Felix Fietkau <nbd@nbd.name>
85 files changed:
target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/Kconfig [deleted file]
target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/Makefile [deleted file]
target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/board.h [deleted file]
target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/dbg.c [deleted file]
target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/dbg.h [deleted file]
target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/mt6575_sd.h [deleted file]
target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/sd.c [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/Kconfig [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/Makefile [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/esw_rt3050.c [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/esw_rt3050.h [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/ethtool.c [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/ethtool.h [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/gsw_mt7620.c [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/gsw_mt7620.h [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/gsw_mt7621.c [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mdio.c [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mdio.h [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mdio_mt7620.c [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mdio_rt2880.c [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mdio_rt2880.h [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mt7530.c [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mt7530.h [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mtk_eth_soc.c [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mtk_eth_soc.h [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/soc_mt7620.c [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/soc_mt7621.c [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/soc_rt2880.c [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/soc_rt3050.c [deleted file]
target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/soc_rt3883.c [deleted file]
target/linux/ramips/mt7620/config-4.9 [deleted file]
target/linux/ramips/mt7621/config-4.9 [deleted file]
target/linux/ramips/mt76x8/config-4.9 [deleted file]
target/linux/ramips/patches-4.9/0004-MIPS-ralink-add-MT7621-pcie-driver.patch [deleted file]
target/linux/ramips/patches-4.9/0005-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch [deleted file]
target/linux/ramips/patches-4.9/0006-MIPS-ralink-add-cpu-frequency-scaling.patch [deleted file]
target/linux/ramips/patches-4.9/0007-MIPS-ralink-copy-the-commandline-from-the-devicetree.patch [deleted file]
target/linux/ramips/patches-4.9/0009-PCI-MIPS-enable-PCIe-on-MT7688.patch [deleted file]
target/linux/ramips/patches-4.9/0013-owrt-hack-fix-mt7688-cache-issue.patch [deleted file]
target/linux/ramips/patches-4.9/0015-arch-mips-do-not-select-illegal-access-driver-by-def.patch [deleted file]
target/linux/ramips/patches-4.9/0024-GPIO-add-named-gpio-exports.patch [deleted file]
target/linux/ramips/patches-4.9/0025-pinctrl-ralink-add-pinctrl-driver.patch [deleted file]
target/linux/ramips/patches-4.9/0026-DT-Add-documentation-for-gpio-ralink.patch [deleted file]
target/linux/ramips/patches-4.9/0027-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch [deleted file]
target/linux/ramips/patches-4.9/0028-GPIO-ralink-add-mt7621-gpio-controller.patch [deleted file]
target/linux/ramips/patches-4.9/0029-phy-usb-add-ralink-phy.patch [deleted file]
target/linux/ramips/patches-4.9/0031-uvc-add-iPassion-iP2970-support.patch [deleted file]
target/linux/ramips/patches-4.9/0032-USB-dwc2-add-device_reset.patch [deleted file]
target/linux/ramips/patches-4.9/0034-NET-multi-phy-support.patch [deleted file]
target/linux/ramips/patches-4.9/0036-mtd-fix-cfi-cmdset-0002-erase-status-check.patch [deleted file]
target/linux/ramips/patches-4.9/0037-mtd-cfi-cmdset-0002-force-word-write.patch [deleted file]
target/linux/ramips/patches-4.9/0039-mtd-add-mt7621-nand-support.patch [deleted file]
target/linux/ramips/patches-4.9/0040-nand-hack.patch [deleted file]
target/linux/ramips/patches-4.9/0041-DT-Add-documentation-for-spi-rt2880.patch [deleted file]
target/linux/ramips/patches-4.9/0042-SPI-ralink-add-Ralink-SoC-spi-driver.patch [deleted file]
target/linux/ramips/patches-4.9/0043-spi-add-mt7621-support.patch [deleted file]
target/linux/ramips/patches-4.9/0044-i2c-MIPS-adds-ralink-I2C-driver.patch [deleted file]
target/linux/ramips/patches-4.9/0045-i2c-add-mt7621-driver.patch [deleted file]
target/linux/ramips/patches-4.9/0046-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch [deleted file]
target/linux/ramips/patches-4.9/0047-DMA-ralink-add-rt2880-dma-engine.patch [deleted file]
target/linux/ramips/patches-4.9/0048-asoc-add-mt7620-support.patch [deleted file]
target/linux/ramips/patches-4.9/0051-serial-add-ugly-custom-baud-rate-hack.patch [deleted file]
target/linux/ramips/patches-4.9/0052-pwm-add-mediatek-support.patch [deleted file]
target/linux/ramips/patches-4.9/0053-mtd-spi-nor-add-w25q256-3b-mode-switch.patch [deleted file]
target/linux/ramips/patches-4.9/0054-mtd-add-chunked-read-io-to-m25p80.patch [deleted file]
target/linux/ramips/patches-4.9/0064-add_clk_round_rate.patch [deleted file]
target/linux/ramips/patches-4.9/0066-mt7621-enable-highmem.patch [deleted file]
target/linux/ramips/patches-4.9/0069-awake-rt305x-dwc2-controller.patch [deleted file]
target/linux/ramips/patches-4.9/0070-weak_reordering.patch [deleted file]
target/linux/ramips/patches-4.9/0090-ethernet.patch [deleted file]
target/linux/ramips/patches-4.9/0098-disable_cm.patch [deleted file]
target/linux/ramips/patches-4.9/0099-pci-mt7620.patch [deleted file]
target/linux/ramips/patches-4.9/0100-prom_fixes.patch [deleted file]
target/linux/ramips/patches-4.9/0101-MIPS-ralink-allow-NULL-clock-for-clk_get_rate.patch [deleted file]
target/linux/ramips/patches-4.9/0105-set_mt7621_soc_type.patch [deleted file]
target/linux/ramips/patches-4.9/0200-linkit_bootstrap.patch [deleted file]
target/linux/ramips/patches-4.9/0700-pinctrl-mt7620-mdio-as-refclk.patch [deleted file]
target/linux/ramips/patches-4.9/0720-arch-mips-ralink-add-i2c-clocks.patch [deleted file]
target/linux/ramips/patches-4.9/0901-spansion_nand_id_fix.patch [deleted file]
target/linux/ramips/patches-4.9/100-mt7621-core-detect-hack.patch [deleted file]
target/linux/ramips/patches-4.9/101-mt7621-timer.patch [deleted file]
target/linux/ramips/patches-4.9/999-fix-pci-init-mt7620.patch [deleted file]
target/linux/ramips/rt288x/config-4.9 [deleted file]
target/linux/ramips/rt305x/config-4.9 [deleted file]
target/linux/ramips/rt3883/config-4.9 [deleted file]

diff --git a/target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/Kconfig b/target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/Kconfig
deleted file mode 100644 (file)
index a58b0f3..0000000
+++ /dev/null
@@ -1,16 +0,0 @@
-config MTK_MMC
-       tristate "MTK SD/MMC"
-       depends on !MTD_NAND_RALINK
-
-config MTK_AEE_KDUMP
-       bool "MTK AEE KDUMP"
-       depends on MTK_MMC
-
-config MTK_MMC_CD_POLL
-       bool "Card Detect with Polling"
-       depends on MTK_MMC
-
-config MTK_MMC_EMMC_8BIT
-       bool "eMMC 8-bit support"
-       depends on MTK_MMC && RALINK_MT7628
-
diff --git a/target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/Makefile b/target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/Makefile
deleted file mode 100644 (file)
index caead0b..0000000
+++ /dev/null
@@ -1,42 +0,0 @@
-# Copyright Statement:
-#
-# This software/firmware and related documentation ("MediaTek Software") are
-# protected under relevant copyright laws. The information contained herein
-# is confidential and proprietary to MediaTek Inc. and/or its licensors.
-# Without the prior written permission of MediaTek inc. and/or its licensors,
-# any reproduction, modification, use or disclosure of MediaTek Software,
-# and information contained herein, in whole or in part, shall be strictly prohibited.
-#
-# MediaTek Inc. (C) 2010. All rights reserved.
-#
-# BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
-# THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
-# RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
-# AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
-# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
-# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
-# NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
-# SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
-# SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
-# THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
-# THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
-# CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
-# SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
-# STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
-# CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
-# AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
-# OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
-# MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
-#
-# The following software/firmware and/or related documentation ("MediaTek Software")
-# have been modified by MediaTek Inc. All revisions are subject to any receiver's
-# applicable license agreements with MediaTek Inc.
-
-obj-$(CONFIG_MTK_MMC) += mtk_sd.o
-mtk_sd-objs := sd.o dbg.o
-ifeq ($(CONFIG_MTK_AEE_KDUMP),y)
-EXTRA_CFLAGS           += -DMT6575_SD_DEBUG
-endif
-
-clean:
-       @rm -f *.o modules.order .*.cmd
diff --git a/target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/board.h b/target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/board.h
deleted file mode 100644 (file)
index 33bfc7b..0000000
+++ /dev/null
@@ -1,137 +0,0 @@
-/* Copyright Statement:
- *
- * This software/firmware and related documentation ("MediaTek Software") are
- * protected under relevant copyright laws. The information contained herein
- * is confidential and proprietary to MediaTek Inc. and/or its licensors.
- * Without the prior written permission of MediaTek inc. and/or its licensors,
- * any reproduction, modification, use or disclosure of MediaTek Software,
- * and information contained herein, in whole or in part, shall be strictly prohibited.
- */
-/* MediaTek Inc. (C) 2010. All rights reserved.
- *
- * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
- * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
- * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
- * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
- * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
- * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
- * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
- * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
- * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
- * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
- * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
- * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
- * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
- * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
- * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
- * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
- *
- * The following software/firmware and/or related documentation ("MediaTek Software")
- * have been modified by MediaTek Inc. All revisions are subject to any receiver's
- * applicable license agreements with MediaTek Inc.
- */
-
-#ifndef __ARCH_ARM_MACH_BOARD_H
-#define __ARCH_ARM_MACH_BOARD_H
-
-#include <generated/autoconf.h>
-#include <linux/pm.h>
-/* --- chhung */
-// #include <mach/mt6575.h>
-// #include <board-custom.h>
-/* end of chhung */
-
-typedef void (*sdio_irq_handler_t)(void*);  /* external irq handler */
-typedef void (*pm_callback_t)(pm_message_t state, void *data);
-
-#define MSDC_CD_PIN_EN      (1 << 0)  /* card detection pin is wired   */
-#define MSDC_WP_PIN_EN      (1 << 1)  /* write protection pin is wired */
-#define MSDC_RST_PIN_EN     (1 << 2)  /* emmc reset pin is wired       */
-#define MSDC_SDIO_IRQ       (1 << 3)  /* use internal sdio irq (bus)   */
-#define MSDC_EXT_SDIO_IRQ   (1 << 4)  /* use external sdio irq         */
-#define MSDC_REMOVABLE      (1 << 5)  /* removable slot                */
-#define MSDC_SYS_SUSPEND    (1 << 6)  /* suspended by system           */
-#define MSDC_HIGHSPEED      (1 << 7)  /* high-speed mode support       */
-#define MSDC_UHS1           (1 << 8)  /* uhs-1 mode support            */
-#define MSDC_DDR            (1 << 9)  /* ddr mode support              */
-
-
-#define MSDC_SMPL_RISING    (0)
-#define MSDC_SMPL_FALLING   (1)
-
-#define MSDC_CMD_PIN        (0)
-#define MSDC_DAT_PIN        (1)
-#define MSDC_CD_PIN         (2)
-#define MSDC_WP_PIN         (3)
-#define MSDC_RST_PIN        (4)
-
-enum {
-    MSDC_CLKSRC_48MHZ = 0,
-//    MSDC_CLKSRC_26MHZ = 0,
-//    MSDC_CLKSRC_197MHZ = 1,
-//    MSDC_CLKSRC_208MHZ = 2
-};
-
-struct msdc_hw {
-    unsigned char  clk_src;          /* host clock source */
-    unsigned char  cmd_edge;         /* command latch edge */
-    unsigned char  data_edge;        /* data latch edge */
-    unsigned char  clk_drv;          /* clock pad driving */
-    unsigned char  cmd_drv;          /* command pad driving */
-    unsigned char  dat_drv;          /* data pad driving */
-    unsigned long  flags;            /* hardware capability flags */
-    unsigned long  data_pins;        /* data pins */
-    unsigned long  data_offset;      /* data address offset */
-
-    /* config gpio pull mode */
-    void (*config_gpio_pin)(int type, int pull);
-
-    /* external power control for card */
-    void (*ext_power_on)(void);
-    void (*ext_power_off)(void);
-
-    /* external sdio irq operations */
-    void (*request_sdio_eirq)(sdio_irq_handler_t sdio_irq_handler, void *data);
-    void (*enable_sdio_eirq)(void);
-    void (*disable_sdio_eirq)(void);
-
-    /* external cd irq operations */
-    void (*request_cd_eirq)(sdio_irq_handler_t cd_irq_handler, void *data);
-    void (*enable_cd_eirq)(void);
-    void (*disable_cd_eirq)(void);
-    int  (*get_cd_status)(void);
-    
-    /* power management callback for external module */
-    void (*register_pm)(pm_callback_t pm_cb, void *data);
-};
-
-extern struct msdc_hw msdc0_hw;
-extern struct msdc_hw msdc1_hw;
-extern struct msdc_hw msdc2_hw;
-extern struct msdc_hw msdc3_hw;
-
-/*GPS driver*/
-#define GPS_FLAG_FORCE_OFF  0x0001
-struct mt3326_gps_hardware {
-    int (*ext_power_on)(int);
-    int (*ext_power_off)(int);
-};
-extern struct mt3326_gps_hardware mt3326_gps_hw;
-
-/* NAND driver */
-struct mt6575_nand_host_hw {
-    unsigned int nfi_bus_width;                    /* NFI_BUS_WIDTH */ 
-       unsigned int nfi_access_timing;         /* NFI_ACCESS_TIMING */  
-       unsigned int nfi_cs_num;                        /* NFI_CS_NUM */
-       unsigned int nand_sec_size;                     /* NAND_SECTOR_SIZE */
-       unsigned int nand_sec_shift;            /* NAND_SECTOR_SHIFT */
-       unsigned int nand_ecc_size;
-       unsigned int nand_ecc_bytes;
-       unsigned int nand_ecc_mode;
-};
-extern struct mt6575_nand_host_hw mt6575_nand_hw;
-
-#endif /* __ARCH_ARM_MACH_BOARD_H */
-
diff --git a/target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/dbg.c b/target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/dbg.c
deleted file mode 100644 (file)
index ae4ef0f..0000000
+++ /dev/null
@@ -1,348 +0,0 @@
-/* Copyright Statement:
- *
- * This software/firmware and related documentation ("MediaTek Software") are
- * protected under relevant copyright laws. The information contained herein
- * is confidential and proprietary to MediaTek Inc. and/or its licensors.
- * Without the prior written permission of MediaTek inc. and/or its licensors,
- * any reproduction, modification, use or disclosure of MediaTek Software,
- * and information contained herein, in whole or in part, shall be strictly prohibited.
- *
- * MediaTek Inc. (C) 2010. All rights reserved.
- *
- * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
- * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
- * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
- * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
- * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
- * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
- * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
- * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
- * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
- * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
- * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
- * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
- * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
- * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
- * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
- * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
- *
- * The following software/firmware and/or related documentation ("MediaTek Software")
- * have been modified by MediaTek Inc. All revisions are subject to any receiver's
- * applicable license agreements with MediaTek Inc.
- */
-#include <linux/version.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/kthread.h>
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/proc_fs.h>
-#include <linux/string.h>
-#include <linux/uaccess.h>
-// #include <mach/mt6575_gpt.h> /* --- by chhung */
-#include "dbg.h"
-#include "mt6575_sd.h"
-#include <linux/seq_file.h>
-
-/* mode select */
-u32 dma_size[4]={
-       512,
-       512,
-       512,
-       512
-};
-msdc_mode drv_mode[4]={
-       MODE_SIZE_DEP, /* using DMA or not depend on the size */
-       MODE_SIZE_DEP,
-       MODE_SIZE_DEP,
-       MODE_SIZE_DEP
-};
-
-#if defined (MT6575_SD_DEBUG)
-static char cmd_buf[256];
-
-/* for debug zone */
-static unsigned int sd_debug_zone[4]={
-       0,
-       0,
-       0,
-       0
-};
-
-
-/* for driver profile */
-#define TICKS_ONE_MS  (13000)
-u32 gpt_enable = 0;
-u32 sdio_pro_enable = 0;   /* make sure gpt is enabled */
-u32 sdio_pro_time = 0;     /* no more than 30s */
-struct sdio_profile sdio_perfomance = {0};  
-
-#if 0 /* --- chhung */
-void msdc_init_gpt(void)
-{
-    GPT_CONFIG config; 
-    
-    config.num  = GPT6;
-    config.mode = GPT_FREE_RUN;
-    config.clkSrc = GPT_CLK_SRC_SYS;
-    config.clkDiv = GPT_CLK_DIV_1;   /* 13MHz GPT6 */
-            
-    if (GPT_Config(config) == FALSE )
-        return;                       
-        
-    GPT_Start(GPT6);   
-}
-#endif /* end of --- */
-
-u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32)
-{
-    u32 ret = 0; 
-    
-    if (new_H32 == old_H32) {
-        ret = new_L32 - old_L32;
-    } else if(new_H32 == (old_H32 + 1)) {
-        if (new_L32 > old_L32) {       
-            printk("msdc old_L<0x%x> new_L<0x%x>\n", old_L32, new_L32);        
-        }
-        ret = (0xffffffff - old_L32);                
-        ret += new_L32; 
-    } else {
-        printk("msdc old_H<0x%x> new_H<0x%x>\n", old_H32, new_H32);            
-    }
-
-    return ret;                
-}
-
-void msdc_sdio_profile(struct sdio_profile* result)
-{
-    struct cmd_profile*  cmd;
-    u32 i;     
-    
-    printk("sdio === performance dump ===\n");
-    printk("sdio === total execute tick<%d> time<%dms> Tx<%dB> Rx<%dB>\n", 
-                    result->total_tc, result->total_tc / TICKS_ONE_MS, 
-                    result->total_tx_bytes, result->total_rx_bytes);    
-
-    /* CMD52 Dump */
-    cmd = &result->cmd52_rx; 
-    printk("sdio === CMD52 Rx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc, 
-                    cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);     
-    cmd = &result->cmd52_tx; 
-    printk("sdio === CMD52 Tx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc, 
-                    cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);   
-                    
-    /* CMD53 Rx bytes + block mode */
-    for (i=0; i<512; i++) {
-        cmd = &result->cmd53_rx_byte[i];
-        if (cmd->count) {
-            printk("sdio<%6d><%3dB>_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc, 
-                             cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
-                             cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));                               
-        }      
-    }  
-    for (i=0; i<100; i++) {
-        cmd = &result->cmd53_rx_blk[i];
-        if (cmd->count) {
-            printk("sdio<%6d><%3d>B_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc, 
-                             cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
-                             cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));                               
-        }      
-    }
-
-    /* CMD53 Tx bytes + block mode */
-    for (i=0; i<512; i++) {
-        cmd = &result->cmd53_tx_byte[i];
-        if (cmd->count) {
-            printk("sdio<%6d><%3dB>_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc, 
-                             cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
-                             cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));                               
-        }      
-    }          
-    for (i=0; i<100; i++) {
-        cmd = &result->cmd53_tx_blk[i];
-        if (cmd->count) {
-            printk("sdio<%6d><%3d>B_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc, 
-                             cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
-                             cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));                               
-        }      
-    }     
-    
-    printk("sdio === performance dump done ===\n");      
-}
-
-//========= sdio command table ===========
-void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks)
-{
-    struct sdio_profile* result = &sdio_perfomance; 
-    struct cmd_profile*  cmd; 
-    u32 block;         
-
-    if (sdio_pro_enable == 0) {
-        return;
-    }
-
-    if (opcode == 52) {
-        cmd = bRx ?  &result->cmd52_rx : &result->cmd52_tx;    
-    } else if (opcode == 53) {
-        if (sizes < 512) {
-            cmd = bRx ?  &result->cmd53_rx_byte[sizes] : &result->cmd53_tx_byte[sizes];        
-        } else {
-            block = sizes / 512; 
-            if (block >= 99) {
-               printk("cmd53 error blocks\n"); 
-               while(1);       
-            }
-            cmd = bRx ?  &result->cmd53_rx_blk[block] : &result->cmd53_tx_blk[block];          
-        }      
-    } else {
-        return;        
-    }
-        
-    /* update the members */
-    if (ticks > cmd->max_tc){
-        cmd->max_tc = ticks;   
-    }
-    if (cmd->min_tc == 0 || ticks < cmd->min_tc) {
-        cmd->min_tc = ticks;     
-    }
-    cmd->tot_tc += ticks;
-    cmd->tot_bytes += sizes; 
-    cmd->count ++; 
-    
-    if (bRx) {
-        result->total_rx_bytes += sizes;       
-    } else {
-        result->total_tx_bytes += sizes;       
-    }
-    result->total_tc += ticks; 
-    
-    /* dump when total_tc > 30s */
-    if (result->total_tc >= sdio_pro_time * TICKS_ONE_MS * 1000) {
-        msdc_sdio_profile(result);       
-        memset(result, 0 , sizeof(struct sdio_profile));                                             
-    }
-}
-
-//========== driver proc interface ===========
-static int msdc_debug_proc_read(struct seq_file *s, void *p)
-{
-       seq_printf(s, "\n=========================================\n");
-       seq_printf(s, "Index<0> + Id + Zone\n");
-       seq_printf(s, "-> PWR<9> WRN<8> | FIO<7> OPS<6> FUN<5> CFG<4> | INT<3> RSP<2> CMD<1> DMA<0>\n");
-       seq_printf(s, "-> echo 0 3 0x3ff >msdc_bebug -> host[3] debug zone set to 0x3ff\n");
-       seq_printf(s, "-> MSDC[0] Zone: 0x%.8x\n", sd_debug_zone[0]);
-       seq_printf(s, "-> MSDC[1] Zone: 0x%.8x\n", sd_debug_zone[1]);
-       seq_printf(s, "-> MSDC[2] Zone: 0x%.8x\n", sd_debug_zone[2]);
-       seq_printf(s, "-> MSDC[3] Zone: 0x%.8x\n", sd_debug_zone[3]);
-
-       seq_printf(s, "Index<1> + ID:4|Mode:4 + DMA_SIZE\n");
-       seq_printf(s, "-> 0)PIO 1)DMA 2)SIZE\n");
-       seq_printf(s, "-> echo 1 22 0x200 >msdc_bebug -> host[2] size mode, dma when >= 512\n");
-       seq_printf(s, "-> MSDC[0] mode<%d> size<%d>\n", drv_mode[0], dma_size[0]);
-       seq_printf(s, "-> MSDC[1] mode<%d> size<%d>\n", drv_mode[1], dma_size[1]);
-       seq_printf(s, "-> MSDC[2] mode<%d> size<%d>\n", drv_mode[2], dma_size[2]);
-       seq_printf(s, "-> MSDC[3] mode<%d> size<%d>\n", drv_mode[3], dma_size[3]);
-
-       seq_printf(s, "Index<3> + SDIO_PROFILE + TIME\n");
-       seq_printf(s, "-> echo 3 1 0x1E >msdc_bebug -> enable sdio_profile, 30s\n");
-       seq_printf(s, "-> SDIO_PROFILE<%d> TIME<%ds>\n", sdio_pro_enable, sdio_pro_time);
-       seq_printf(s, "=========================================\n\n");
-
-       return 0;
-}
-
-static ssize_t msdc_debug_proc_write(struct file *file, 
-                       const char __user *buf, size_t count, loff_t *data)
-{
-       int ret;
-       
-       int cmd, p1, p2;   
-       int id, zone;
-       int mode, size;  
-  
-       if (count == 0)return -1;
-       if(count > 255)count = 255;
-
-       ret = copy_from_user(cmd_buf, buf, count);
-       if (ret < 0)return -1;
-       
-       cmd_buf[count] = '\0';
-       printk("msdc Write %s\n", cmd_buf);
-
-       sscanf(cmd_buf, "%x %x %x", &cmd, &p1, &p2);
-       
-       if(cmd == SD_TOOL_ZONE) {
-               id = p1; zone = p2; zone &= 0x3ff;              
-               printk("msdc host_id<%d> zone<0x%.8x>\n", id, zone);
-               if(id >=0 && id<=3){
-                       sd_debug_zone[id] = zone;
-               }
-               else if(id == 4){
-                       sd_debug_zone[0] = sd_debug_zone[1] = zone;
-                       sd_debug_zone[2] = sd_debug_zone[3] = zone;
-               }
-               else{
-                       printk("msdc host_id error when set debug zone\n");
-               }
-       } else if (cmd == SD_TOOL_DMA_SIZE) {
-               id = p1>>4;  mode = (p1&0xf); size = p2; 
-               if(id >=0 && id<=3){
-                       drv_mode[id] = mode;
-                       dma_size[id] = p2; 
-               }
-               else if(id == 4){
-                       drv_mode[0] = drv_mode[1] = mode;
-                       drv_mode[2] = drv_mode[3] = mode;
-                       dma_size[0] = dma_size[1] = p2; 
-                       dma_size[2] = dma_size[3] = p2;
-               }
-               else{
-                       printk("msdc host_id error when select mode\n");
-               }       
-       } else if (cmd == SD_TOOL_SDIO_PROFILE) {
-               if (p1 == 1) { /* enable profile */
-                       if (gpt_enable == 0) {
-                               // msdc_init_gpt(); /* --- by chhung */
-                               gpt_enable = 1;
-                       } 
-                       sdio_pro_enable = 1;
-                       if (p2 == 0) p2 = 1; if (p2 >= 30) p2 = 30;                             
-                       sdio_pro_time = p2 ; 
-               }       else if (p1 == 0) {
-                       /* todo */
-                       sdio_pro_enable = 0;
-               }                       
-       }
-       
-       return count;
-}
-
-static int msdc_debug_show(struct inode *inode, struct file *file)
-{
-       return single_open(file, msdc_debug_proc_read, NULL);
-}
-
-static const struct file_operations msdc_debug_fops = {
-       .owner          = THIS_MODULE,
-       .open           = msdc_debug_show,
-       .read           = seq_read,
-       .write          = msdc_debug_proc_write,
-       .llseek         = seq_lseek,
-       .release        = single_release,
-};
-
-int msdc_debug_proc_init(void) 
-{      
-    struct proc_dir_entry *de = proc_create("msdc_debug", 0667, NULL, &msdc_debug_fops);
-
-    if (!de || IS_ERR(de))
-       printk("!! Create MSDC debug PROC fail !!\n");
-    
-    return 0 ;
-}
-EXPORT_SYMBOL_GPL(msdc_debug_proc_init);
-#endif
diff --git a/target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/dbg.h b/target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/dbg.h
deleted file mode 100644 (file)
index e58c431..0000000
+++ /dev/null
@@ -1,156 +0,0 @@
-/* Copyright Statement:
- *
- * This software/firmware and related documentation ("MediaTek Software") are
- * protected under relevant copyright laws. The information contained herein
- * is confidential and proprietary to MediaTek Inc. and/or its licensors.
- * Without the prior written permission of MediaTek inc. and/or its licensors,
- * any reproduction, modification, use or disclosure of MediaTek Software,
- * and information contained herein, in whole or in part, shall be strictly prohibited.
- *
- * MediaTek Inc. (C) 2010. All rights reserved.
- *
- * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
- * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
- * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
- * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
- * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
- * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
- * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
- * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
- * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
- * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
- * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
- * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
- * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
- * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
- * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
- * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
- *
- * The following software/firmware and/or related documentation ("MediaTek Software")
- * have been modified by MediaTek Inc. All revisions are subject to any receiver's
- * applicable license agreements with MediaTek Inc.
- */
-#ifndef __MT_MSDC_DEUBG__
-#define __MT_MSDC_DEUBG__
-
-//==========================
-extern u32 sdio_pro_enable;
-/* for a type command, e.g. CMD53, 2 blocks */
-struct cmd_profile {
-    u32 max_tc;    /* Max tick count */
-    u32 min_tc;        
-    u32 tot_tc;    /* total tick count */
-    u32 tot_bytes;  
-    u32 count;     /* the counts of the command */
-};
-
-/* dump when total_tc and total_bytes */
-struct sdio_profile {
-    u32 total_tc;         /* total tick count of CMD52 and CMD53 */
-    u32 total_tx_bytes;   /* total bytes of CMD53 Tx */
-    u32 total_rx_bytes;   /* total bytes of CMD53 Rx */
-    
-    /*CMD52*/
-    struct cmd_profile cmd52_tx; 
-    struct cmd_profile cmd52_rx; 
-
-    /*CMD53 in byte unit */
-    struct cmd_profile cmd53_tx_byte[512]; 
-    struct cmd_profile cmd53_rx_byte[512];             
-    
-    /*CMD53 in block unit */
-    struct cmd_profile cmd53_tx_blk[100]; 
-    struct cmd_profile cmd53_rx_blk[100];         
-};
-
-//==========================
-typedef enum {
-    SD_TOOL_ZONE = 0, 
-    SD_TOOL_DMA_SIZE  = 1,     
-    SD_TOOL_PM_ENABLE = 2,
-    SD_TOOL_SDIO_PROFILE = 3,     
-} msdc_dbg;    
-
-typedef enum {
-    MODE_PIO = 0,
-    MODE_DMA = 1,
-    MODE_SIZE_DEP = 2,
-} msdc_mode;
-extern msdc_mode drv_mode[4];
-extern u32 dma_size[4];
-
-/* Debug message event */
-#define DBG_EVT_NONE        (0)       /* No event */
-#define DBG_EVT_DMA         (1 << 0)  /* DMA related event */
-#define DBG_EVT_CMD         (1 << 1)  /* MSDC CMD related event */
-#define DBG_EVT_RSP         (1 << 2)  /* MSDC CMD RSP related event */
-#define DBG_EVT_INT         (1 << 3)  /* MSDC INT event */
-#define DBG_EVT_CFG         (1 << 4)  /* MSDC CFG event */
-#define DBG_EVT_FUC         (1 << 5)  /* Function event */
-#define DBG_EVT_OPS         (1 << 6)  /* Read/Write operation event */
-#define DBG_EVT_FIO         (1 << 7)  /* FIFO operation event */
-#define DBG_EVT_WRN         (1 << 8)  /* Warning event */
-#define DBG_EVT_PWR         (1 << 9)  /* Power event */
-#define DBG_EVT_ALL         (0xffffffff)
-
-#define DBG_EVT_MASK        (DBG_EVT_ALL)
-
-extern unsigned int sd_debug_zone[4];
-#define TAG "msdc"
-#if 0 /* +++ chhung */
-#define BUG_ON(x) \
-do { \
-       if (x) { \
-               printk("[BUG] %s LINE:%d FILE:%s\n", #x, __LINE__, __FILE__); \
-               while(1); \
-       } \
-}while(0)
-#endif /* end of +++ */
-
-#define N_MSG(evt, fmt, args...)
-/*
-do {    \
-    if ((DBG_EVT_##evt) & sd_debug_zone[host->id]) { \
-        printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
-            host->id,  ##args , __FUNCTION__, __LINE__, current->comm, current->pid);  \
-    } \
-} while(0)
-*/
-
-#define ERR_MSG(fmt, args...) \
-do { \
-    printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
-        host->id,  ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
-} while(0); 
-
-#if 1
-//defined CONFIG_MTK_MMC_CD_POLL        
-#define INIT_MSG(fmt, args...)
-#define IRQ_MSG(fmt, args...) 
-#else
-#define INIT_MSG(fmt, args...) \
-do { \
-    printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
-        host->id,  ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
-} while(0);
-
-/* PID in ISR in not corrent */
-#define IRQ_MSG(fmt, args...) \
-do { \
-    printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d>\n", \
-        host->id,  ##args , __FUNCTION__, __LINE__); \
-} while(0);
-#endif
-
-int msdc_debug_proc_init(void); 
-
-#if 0 /* --- chhung */
-void msdc_init_gpt(void);
-extern void GPT_GetCounter64(UINT32 *cntL32, UINT32 *cntH32);
-#endif /* end of --- */
-u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32);
-void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks);   
-
-#endif
diff --git a/target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/mt6575_sd.h b/target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/mt6575_sd.h
deleted file mode 100644 (file)
index e90c4f1..0000000
+++ /dev/null
@@ -1,1001 +0,0 @@
-/* Copyright Statement:
- *
- * This software/firmware and related documentation ("MediaTek Software") are
- * protected under relevant copyright laws. The information contained herein
- * is confidential and proprietary to MediaTek Inc. and/or its licensors.
- * Without the prior written permission of MediaTek inc. and/or its licensors,
- * any reproduction, modification, use or disclosure of MediaTek Software,
- * and information contained herein, in whole or in part, shall be strictly prohibited.
- */
-/* MediaTek Inc. (C) 2010. All rights reserved.
- *
- * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
- * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
- * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
- * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
- * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
- * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
- * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
- * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
- * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
- * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
- * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
- * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
- * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
- * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
- * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
- * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
- *
- * The following software/firmware and/or related documentation ("MediaTek Software")
- * have been modified by MediaTek Inc. All revisions are subject to any receiver's
- * applicable license agreements with MediaTek Inc.
- */
-
-#ifndef MT6575_SD_H
-#define MT6575_SD_H
-
-#include <linux/bitops.h>
-#include <linux/mmc/host.h>
-
-// #include <mach/mt6575_reg_base.h> /* --- by chhung */
-
-/*--------------------------------------------------------------------------*/
-/* Common Macro                                                             */
-/*--------------------------------------------------------------------------*/
-#define REG_ADDR(x)                 ((volatile u32*)(base + OFFSET_##x))
-
-/*--------------------------------------------------------------------------*/
-/* Common Definition                                                        */
-/*--------------------------------------------------------------------------*/
-#define MSDC_FIFO_SZ            (128)
-#define MSDC_FIFO_THD           (64)  // (128)
-#define MSDC_NUM                (4)
-
-#define MSDC_MS                 (0)
-#define MSDC_SDMMC              (1)
-
-#define MSDC_MODE_UNKNOWN       (0)
-#define MSDC_MODE_PIO           (1)
-#define MSDC_MODE_DMA_BASIC     (2)
-#define MSDC_MODE_DMA_DESC      (3)
-#define MSDC_MODE_DMA_ENHANCED  (4)
-#define MSDC_MODE_MMC_STREAM    (5)
-
-#define MSDC_BUS_1BITS          (0)
-#define MSDC_BUS_4BITS          (1)
-#define MSDC_BUS_8BITS          (2)
-
-#define MSDC_BRUST_8B           (3)
-#define MSDC_BRUST_16B          (4)
-#define MSDC_BRUST_32B          (5)
-#define MSDC_BRUST_64B          (6)
-
-#define MSDC_PIN_PULL_NONE      (0)
-#define MSDC_PIN_PULL_DOWN      (1)
-#define MSDC_PIN_PULL_UP        (2)
-#define MSDC_PIN_KEEP           (3)
-
-#define MSDC_MAX_SCLK           (48000000) /* +/- by chhung */
-#define MSDC_MIN_SCLK           (260000)
-
-#define MSDC_AUTOCMD12          (0x0001)
-#define MSDC_AUTOCMD23          (0x0002)
-#define MSDC_AUTOCMD19          (0x0003)
-
-#define MSDC_EMMC_BOOTMODE0     (0)     /* Pull low CMD mode */
-#define MSDC_EMMC_BOOTMODE1     (1)     /* Reset CMD mode */
-
-enum {
-    RESP_NONE = 0,
-    RESP_R1,
-    RESP_R2,
-    RESP_R3,
-    RESP_R4,
-    RESP_R5,
-    RESP_R6,
-    RESP_R7,
-    RESP_R1B
-};
-
-/*--------------------------------------------------------------------------*/
-/* Register Offset                                                          */
-/*--------------------------------------------------------------------------*/
-#define OFFSET_MSDC_CFG         (0x0)
-#define OFFSET_MSDC_IOCON       (0x04)
-#define OFFSET_MSDC_PS          (0x08)
-#define OFFSET_MSDC_INT         (0x0c)
-#define OFFSET_MSDC_INTEN       (0x10)
-#define OFFSET_MSDC_FIFOCS      (0x14)
-#define OFFSET_MSDC_TXDATA      (0x18)
-#define OFFSET_MSDC_RXDATA      (0x1c)
-#define OFFSET_SDC_CFG          (0x30)
-#define OFFSET_SDC_CMD          (0x34)
-#define OFFSET_SDC_ARG          (0x38)
-#define OFFSET_SDC_STS          (0x3c)
-#define OFFSET_SDC_RESP0        (0x40)
-#define OFFSET_SDC_RESP1        (0x44)
-#define OFFSET_SDC_RESP2        (0x48)
-#define OFFSET_SDC_RESP3        (0x4c)
-#define OFFSET_SDC_BLK_NUM      (0x50)
-#define OFFSET_SDC_CSTS         (0x58)
-#define OFFSET_SDC_CSTS_EN      (0x5c)
-#define OFFSET_SDC_DCRC_STS     (0x60)
-#define OFFSET_EMMC_CFG0        (0x70)
-#define OFFSET_EMMC_CFG1        (0x74)
-#define OFFSET_EMMC_STS         (0x78)
-#define OFFSET_EMMC_IOCON       (0x7c)
-#define OFFSET_SDC_ACMD_RESP    (0x80)
-#define OFFSET_SDC_ACMD19_TRG   (0x84)
-#define OFFSET_SDC_ACMD19_STS   (0x88)
-#define OFFSET_MSDC_DMA_SA      (0x90)
-#define OFFSET_MSDC_DMA_CA      (0x94)
-#define OFFSET_MSDC_DMA_CTRL    (0x98)
-#define OFFSET_MSDC_DMA_CFG     (0x9c)
-#define OFFSET_MSDC_DBG_SEL     (0xa0)
-#define OFFSET_MSDC_DBG_OUT     (0xa4)
-#define OFFSET_MSDC_PATCH_BIT   (0xb0)
-#define OFFSET_MSDC_PATCH_BIT1  (0xb4)
-#define OFFSET_MSDC_PAD_CTL0    (0xe0)
-#define OFFSET_MSDC_PAD_CTL1    (0xe4)
-#define OFFSET_MSDC_PAD_CTL2    (0xe8)
-#define OFFSET_MSDC_PAD_TUNE    (0xec)
-#define OFFSET_MSDC_DAT_RDDLY0  (0xf0)
-#define OFFSET_MSDC_DAT_RDDLY1  (0xf4)
-#define OFFSET_MSDC_HW_DBG      (0xf8)
-#define OFFSET_MSDC_VERSION     (0x100)
-#define OFFSET_MSDC_ECO_VER     (0x104)
-
-/*--------------------------------------------------------------------------*/
-/* Register Address                                                         */
-/*--------------------------------------------------------------------------*/
-
-/* common register */
-#define MSDC_CFG                REG_ADDR(MSDC_CFG)
-#define MSDC_IOCON              REG_ADDR(MSDC_IOCON)
-#define MSDC_PS                 REG_ADDR(MSDC_PS)
-#define MSDC_INT                REG_ADDR(MSDC_INT)
-#define MSDC_INTEN              REG_ADDR(MSDC_INTEN)
-#define MSDC_FIFOCS             REG_ADDR(MSDC_FIFOCS)
-#define MSDC_TXDATA             REG_ADDR(MSDC_TXDATA)
-#define MSDC_RXDATA             REG_ADDR(MSDC_RXDATA)
-#define MSDC_PATCH_BIT0         REG_ADDR(MSDC_PATCH_BIT)
-
-/* sdmmc register */
-#define SDC_CFG                 REG_ADDR(SDC_CFG)
-#define SDC_CMD                 REG_ADDR(SDC_CMD)
-#define SDC_ARG                 REG_ADDR(SDC_ARG)
-#define SDC_STS                 REG_ADDR(SDC_STS)
-#define SDC_RESP0               REG_ADDR(SDC_RESP0)
-#define SDC_RESP1               REG_ADDR(SDC_RESP1)
-#define SDC_RESP2               REG_ADDR(SDC_RESP2)
-#define SDC_RESP3               REG_ADDR(SDC_RESP3)
-#define SDC_BLK_NUM             REG_ADDR(SDC_BLK_NUM)
-#define SDC_CSTS                REG_ADDR(SDC_CSTS)
-#define SDC_CSTS_EN             REG_ADDR(SDC_CSTS_EN)
-#define SDC_DCRC_STS            REG_ADDR(SDC_DCRC_STS)
-
-/* emmc register*/
-#define EMMC_CFG0               REG_ADDR(EMMC_CFG0)
-#define EMMC_CFG1               REG_ADDR(EMMC_CFG1)
-#define EMMC_STS                REG_ADDR(EMMC_STS)
-#define EMMC_IOCON              REG_ADDR(EMMC_IOCON)
-
-/* auto command register */
-#define SDC_ACMD_RESP           REG_ADDR(SDC_ACMD_RESP)
-#define SDC_ACMD19_TRG          REG_ADDR(SDC_ACMD19_TRG)
-#define SDC_ACMD19_STS          REG_ADDR(SDC_ACMD19_STS)
-
-/* dma register */
-#define MSDC_DMA_SA             REG_ADDR(MSDC_DMA_SA)
-#define MSDC_DMA_CA             REG_ADDR(MSDC_DMA_CA)
-#define MSDC_DMA_CTRL           REG_ADDR(MSDC_DMA_CTRL)
-#define MSDC_DMA_CFG            REG_ADDR(MSDC_DMA_CFG)
-
-/* pad ctrl register */
-#define MSDC_PAD_CTL0           REG_ADDR(MSDC_PAD_CTL0)
-#define MSDC_PAD_CTL1           REG_ADDR(MSDC_PAD_CTL1)
-#define MSDC_PAD_CTL2           REG_ADDR(MSDC_PAD_CTL2)
-
-/* data read delay */
-#define MSDC_DAT_RDDLY0         REG_ADDR(MSDC_DAT_RDDLY0)
-#define MSDC_DAT_RDDLY1         REG_ADDR(MSDC_DAT_RDDLY1)
-
-/* debug register */
-#define MSDC_DBG_SEL            REG_ADDR(MSDC_DBG_SEL)
-#define MSDC_DBG_OUT            REG_ADDR(MSDC_DBG_OUT)
-
-/* misc register */
-#define MSDC_PATCH_BIT          REG_ADDR(MSDC_PATCH_BIT)
-#define MSDC_PATCH_BIT1         REG_ADDR(MSDC_PATCH_BIT1)
-#define MSDC_PAD_TUNE           REG_ADDR(MSDC_PAD_TUNE)
-#define MSDC_HW_DBG             REG_ADDR(MSDC_HW_DBG)
-#define MSDC_VERSION            REG_ADDR(MSDC_VERSION)
-#define MSDC_ECO_VER            REG_ADDR(MSDC_ECO_VER) /* ECO Version */
-
-/*--------------------------------------------------------------------------*/
-/* Register Mask                                                            */
-/*--------------------------------------------------------------------------*/
-
-/* MSDC_CFG mask */
-#define MSDC_CFG_MODE           (0x1  << 0)     /* RW */
-#define MSDC_CFG_CKPDN          (0x1  << 1)     /* RW */
-#define MSDC_CFG_RST            (0x1  << 2)     /* RW */
-#define MSDC_CFG_PIO            (0x1  << 3)     /* RW */
-#define MSDC_CFG_CKDRVEN        (0x1  << 4)     /* RW */
-#define MSDC_CFG_BV18SDT        (0x1  << 5)     /* RW */
-#define MSDC_CFG_BV18PSS        (0x1  << 6)     /* R  */
-#define MSDC_CFG_CKSTB          (0x1  << 7)     /* R  */
-#define MSDC_CFG_CKDIV          (0xff << 8)     /* RW */
-#define MSDC_CFG_CKMOD          (0x3  << 16)    /* RW */
-
-/* MSDC_IOCON mask */
-#define MSDC_IOCON_SDR104CKS    (0x1  << 0)     /* RW */
-#define MSDC_IOCON_RSPL         (0x1  << 1)     /* RW */
-#define MSDC_IOCON_DSPL         (0x1  << 2)     /* RW */
-#define MSDC_IOCON_DDLSEL       (0x1  << 3)     /* RW */
-#define MSDC_IOCON_DDR50CKD     (0x1  << 4)     /* RW */
-#define MSDC_IOCON_DSPLSEL      (0x1  << 5)     /* RW */
-#define MSDC_IOCON_D0SPL        (0x1  << 16)    /* RW */
-#define MSDC_IOCON_D1SPL        (0x1  << 17)    /* RW */
-#define MSDC_IOCON_D2SPL        (0x1  << 18)    /* RW */
-#define MSDC_IOCON_D3SPL        (0x1  << 19)    /* RW */
-#define MSDC_IOCON_D4SPL        (0x1  << 20)    /* RW */
-#define MSDC_IOCON_D5SPL        (0x1  << 21)    /* RW */
-#define MSDC_IOCON_D6SPL        (0x1  << 22)    /* RW */
-#define MSDC_IOCON_D7SPL        (0x1  << 23)    /* RW */
-#define MSDC_IOCON_RISCSZ       (0x3  << 24)    /* RW */
-
-/* MSDC_PS mask */
-#define MSDC_PS_CDEN            (0x1  << 0)     /* RW */
-#define MSDC_PS_CDSTS           (0x1  << 1)     /* R  */
-#define MSDC_PS_CDDEBOUNCE      (0xf  << 12)    /* RW */
-#define MSDC_PS_DAT             (0xff << 16)    /* R  */
-#define MSDC_PS_CMD             (0x1  << 24)    /* R  */
-#define MSDC_PS_WP              (0x1UL<< 31)    /* R  */
-
-/* MSDC_INT mask */
-#define MSDC_INT_MMCIRQ         (0x1  << 0)     /* W1C */
-#define MSDC_INT_CDSC           (0x1  << 1)     /* W1C */
-#define MSDC_INT_ACMDRDY        (0x1  << 3)     /* W1C */
-#define MSDC_INT_ACMDTMO        (0x1  << 4)     /* W1C */
-#define MSDC_INT_ACMDCRCERR     (0x1  << 5)     /* W1C */
-#define MSDC_INT_DMAQ_EMPTY     (0x1  << 6)     /* W1C */
-#define MSDC_INT_SDIOIRQ        (0x1  << 7)     /* W1C */
-#define MSDC_INT_CMDRDY         (0x1  << 8)     /* W1C */
-#define MSDC_INT_CMDTMO         (0x1  << 9)     /* W1C */
-#define MSDC_INT_RSPCRCERR      (0x1  << 10)    /* W1C */
-#define MSDC_INT_CSTA           (0x1  << 11)    /* R */
-#define MSDC_INT_XFER_COMPL     (0x1  << 12)    /* W1C */
-#define MSDC_INT_DXFER_DONE     (0x1  << 13)    /* W1C */
-#define MSDC_INT_DATTMO         (0x1  << 14)    /* W1C */
-#define MSDC_INT_DATCRCERR      (0x1  << 15)    /* W1C */
-#define MSDC_INT_ACMD19_DONE    (0x1  << 16)    /* W1C */
-
-/* MSDC_INTEN mask */
-#define MSDC_INTEN_MMCIRQ       (0x1  << 0)     /* RW */
-#define MSDC_INTEN_CDSC         (0x1  << 1)     /* RW */
-#define MSDC_INTEN_ACMDRDY      (0x1  << 3)     /* RW */
-#define MSDC_INTEN_ACMDTMO      (0x1  << 4)     /* RW */
-#define MSDC_INTEN_ACMDCRCERR   (0x1  << 5)     /* RW */
-#define MSDC_INTEN_DMAQ_EMPTY   (0x1  << 6)     /* RW */
-#define MSDC_INTEN_SDIOIRQ      (0x1  << 7)     /* RW */
-#define MSDC_INTEN_CMDRDY       (0x1  << 8)     /* RW */
-#define MSDC_INTEN_CMDTMO       (0x1  << 9)     /* RW */
-#define MSDC_INTEN_RSPCRCERR    (0x1  << 10)    /* RW */
-#define MSDC_INTEN_CSTA         (0x1  << 11)    /* RW */
-#define MSDC_INTEN_XFER_COMPL   (0x1  << 12)    /* RW */
-#define MSDC_INTEN_DXFER_DONE   (0x1  << 13)    /* RW */
-#define MSDC_INTEN_DATTMO       (0x1  << 14)    /* RW */
-#define MSDC_INTEN_DATCRCERR    (0x1  << 15)    /* RW */
-#define MSDC_INTEN_ACMD19_DONE  (0x1  << 16)    /* RW */
-
-/* MSDC_FIFOCS mask */
-#define MSDC_FIFOCS_RXCNT       (0xff << 0)     /* R */
-#define MSDC_FIFOCS_TXCNT       (0xff << 16)    /* R */
-#define MSDC_FIFOCS_CLR         (0x1UL<< 31)    /* RW */
-
-/* SDC_CFG mask */
-#define SDC_CFG_SDIOINTWKUP     (0x1  << 0)     /* RW */
-#define SDC_CFG_INSWKUP         (0x1  << 1)     /* RW */
-#define SDC_CFG_BUSWIDTH        (0x3  << 16)    /* RW */
-#define SDC_CFG_SDIO            (0x1  << 19)    /* RW */
-#define SDC_CFG_SDIOIDE         (0x1  << 20)    /* RW */      
-#define SDC_CFG_INTATGAP        (0x1  << 21)    /* RW */
-#define SDC_CFG_DTOC            (0xffUL << 24)  /* RW */
-
-/* SDC_CMD mask */
-#define SDC_CMD_OPC             (0x3f << 0)     /* RW */
-#define SDC_CMD_BRK             (0x1  << 6)     /* RW */
-#define SDC_CMD_RSPTYP          (0x7  << 7)     /* RW */
-#define SDC_CMD_DTYP            (0x3  << 11)    /* RW */
-#define SDC_CMD_DTYP            (0x3  << 11)    /* RW */
-#define SDC_CMD_RW              (0x1  << 13)    /* RW */
-#define SDC_CMD_STOP            (0x1  << 14)    /* RW */
-#define SDC_CMD_GOIRQ           (0x1  << 15)    /* RW */
-#define SDC_CMD_BLKLEN          (0xfff<< 16)    /* RW */
-#define SDC_CMD_AUTOCMD         (0x3  << 28)    /* RW */
-#define SDC_CMD_VOLSWTH         (0x1  << 30)    /* RW */
-
-/* SDC_STS mask */
-#define SDC_STS_SDCBUSY         (0x1  << 0)     /* RW */
-#define SDC_STS_CMDBUSY         (0x1  << 1)     /* RW */
-#define SDC_STS_SWR_COMPL       (0x1  << 31)    /* RW */
-
-/* SDC_DCRC_STS mask */
-#define SDC_DCRC_STS_NEG        (0xf  << 8)     /* RO */
-#define SDC_DCRC_STS_POS        (0xff << 0)     /* RO */
-
-/* EMMC_CFG0 mask */
-#define EMMC_CFG0_BOOTSTART     (0x1  << 0)     /* W */
-#define EMMC_CFG0_BOOTSTOP      (0x1  << 1)     /* W */
-#define EMMC_CFG0_BOOTMODE      (0x1  << 2)     /* RW */
-#define EMMC_CFG0_BOOTACKDIS    (0x1  << 3)     /* RW */
-#define EMMC_CFG0_BOOTWDLY      (0x7  << 12)    /* RW */
-#define EMMC_CFG0_BOOTSUPP      (0x1  << 15)    /* RW */
-
-/* EMMC_CFG1 mask */
-#define EMMC_CFG1_BOOTDATTMC    (0xfffff << 0)  /* RW */
-#define EMMC_CFG1_BOOTACKTMC    (0xfffUL << 20) /* RW */
-
-/* EMMC_STS mask */
-#define EMMC_STS_BOOTCRCERR     (0x1  << 0)     /* W1C */
-#define EMMC_STS_BOOTACKERR     (0x1  << 1)     /* W1C */
-#define EMMC_STS_BOOTDATTMO     (0x1  << 2)     /* W1C */
-#define EMMC_STS_BOOTACKTMO     (0x1  << 3)     /* W1C */
-#define EMMC_STS_BOOTUPSTATE    (0x1  << 4)     /* R */
-#define EMMC_STS_BOOTACKRCV     (0x1  << 5)     /* W1C */
-#define EMMC_STS_BOOTDATRCV     (0x1  << 6)     /* R */
-
-/* EMMC_IOCON mask */
-#define EMMC_IOCON_BOOTRST      (0x1  << 0)     /* RW */
-
-/* SDC_ACMD19_TRG mask */
-#define SDC_ACMD19_TRG_TUNESEL  (0xf  << 0)     /* RW */
-
-/* MSDC_DMA_CTRL mask */
-#define MSDC_DMA_CTRL_START     (0x1  << 0)     /* W */
-#define MSDC_DMA_CTRL_STOP      (0x1  << 1)     /* W */
-#define MSDC_DMA_CTRL_RESUME    (0x1  << 2)     /* W */
-#define MSDC_DMA_CTRL_MODE      (0x1  << 8)     /* RW */
-#define MSDC_DMA_CTRL_LASTBUF   (0x1  << 10)    /* RW */
-#define MSDC_DMA_CTRL_BRUSTSZ   (0x7  << 12)    /* RW */
-#define MSDC_DMA_CTRL_XFERSZ    (0xffffUL << 16)/* RW */
-
-/* MSDC_DMA_CFG mask */
-#define MSDC_DMA_CFG_STS        (0x1  << 0)     /* R */
-#define MSDC_DMA_CFG_DECSEN     (0x1  << 1)     /* RW */
-#define MSDC_DMA_CFG_BDCSERR    (0x1  << 4)     /* R */
-#define MSDC_DMA_CFG_GPDCSERR   (0x1  << 5)     /* R */
-
-/* MSDC_PATCH_BIT mask */
-#define MSDC_PATCH_BIT_WFLSMODE (0x1  << 0)     /* RW */
-#define MSDC_PATCH_BIT_ODDSUPP  (0x1  << 1)     /* RW */
-#define MSDC_PATCH_BIT_CKGEN_CK (0x1  << 6)     /* E2: Fixed to 1 */
-#define MSDC_PATCH_BIT_IODSSEL  (0x1  << 16)    /* RW */
-#define MSDC_PATCH_BIT_IOINTSEL (0x1  << 17)    /* RW */
-#define MSDC_PATCH_BIT_BUSYDLY  (0xf  << 18)    /* RW */
-#define MSDC_PATCH_BIT_WDOD     (0xf  << 22)    /* RW */
-#define MSDC_PATCH_BIT_IDRTSEL  (0x1  << 26)    /* RW */
-#define MSDC_PATCH_BIT_CMDFSEL  (0x1  << 27)    /* RW */
-#define MSDC_PATCH_BIT_INTDLSEL (0x1  << 28)    /* RW */
-#define MSDC_PATCH_BIT_SPCPUSH  (0x1  << 29)    /* RW */
-#define MSDC_PATCH_BIT_DECRCTMO (0x1  << 30)    /* RW */
-
-/* MSDC_PATCH_BIT1 mask */
-#define MSDC_PATCH_BIT1_WRDAT_CRCS  (0x7 << 3)
-#define MSDC_PATCH_BIT1_CMD_RSP     (0x7 << 0)
-
-/* MSDC_PAD_CTL0 mask */
-#define MSDC_PAD_CTL0_CLKDRVN   (0x7  << 0)     /* RW */
-#define MSDC_PAD_CTL0_CLKDRVP   (0x7  << 4)     /* RW */
-#define MSDC_PAD_CTL0_CLKSR     (0x1  << 8)     /* RW */
-#define MSDC_PAD_CTL0_CLKPD     (0x1  << 16)    /* RW */
-#define MSDC_PAD_CTL0_CLKPU     (0x1  << 17)    /* RW */
-#define MSDC_PAD_CTL0_CLKSMT    (0x1  << 18)    /* RW */
-#define MSDC_PAD_CTL0_CLKIES    (0x1  << 19)    /* RW */
-#define MSDC_PAD_CTL0_CLKTDSEL  (0xf  << 20)    /* RW */
-#define MSDC_PAD_CTL0_CLKRDSEL  (0xffUL<< 24)   /* RW */
-
-/* MSDC_PAD_CTL1 mask */
-#define MSDC_PAD_CTL1_CMDDRVN   (0x7  << 0)     /* RW */
-#define MSDC_PAD_CTL1_CMDDRVP   (0x7  << 4)     /* RW */
-#define MSDC_PAD_CTL1_CMDSR     (0x1  << 8)     /* RW */
-#define MSDC_PAD_CTL1_CMDPD     (0x1  << 16)    /* RW */
-#define MSDC_PAD_CTL1_CMDPU     (0x1  << 17)    /* RW */
-#define MSDC_PAD_CTL1_CMDSMT    (0x1  << 18)    /* RW */
-#define MSDC_PAD_CTL1_CMDIES    (0x1  << 19)    /* RW */
-#define MSDC_PAD_CTL1_CMDTDSEL  (0xf  << 20)    /* RW */
-#define MSDC_PAD_CTL1_CMDRDSEL  (0xffUL<< 24)   /* RW */
-
-/* MSDC_PAD_CTL2 mask */
-#define MSDC_PAD_CTL2_DATDRVN   (0x7  << 0)     /* RW */
-#define MSDC_PAD_CTL2_DATDRVP   (0x7  << 4)     /* RW */
-#define MSDC_PAD_CTL2_DATSR     (0x1  << 8)     /* RW */
-#define MSDC_PAD_CTL2_DATPD     (0x1  << 16)    /* RW */
-#define MSDC_PAD_CTL2_DATPU     (0x1  << 17)    /* RW */
-#define MSDC_PAD_CTL2_DATIES    (0x1  << 19)    /* RW */
-#define MSDC_PAD_CTL2_DATSMT    (0x1  << 18)    /* RW */
-#define MSDC_PAD_CTL2_DATTDSEL  (0xf  << 20)    /* RW */
-#define MSDC_PAD_CTL2_DATRDSEL  (0xffUL<< 24)   /* RW */
-
-/* MSDC_PAD_TUNE mask */
-#define MSDC_PAD_TUNE_DATWRDLY  (0x1F << 0)     /* RW */
-#define MSDC_PAD_TUNE_DATRRDLY  (0x1F << 8)     /* RW */
-#define MSDC_PAD_TUNE_CMDRDLY   (0x1F << 16)    /* RW */
-#define MSDC_PAD_TUNE_CMDRRDLY  (0x1FUL << 22)  /* RW */
-#define MSDC_PAD_TUNE_CLKTXDLY  (0x1FUL << 27)  /* RW */
-
-/* MSDC_DAT_RDDLY0/1 mask */
-#define MSDC_DAT_RDDLY0_D0      (0x1F << 0)     /* RW */
-#define MSDC_DAT_RDDLY0_D1      (0x1F << 8)     /* RW */
-#define MSDC_DAT_RDDLY0_D2      (0x1F << 16)    /* RW */
-#define MSDC_DAT_RDDLY0_D3      (0x1F << 24)    /* RW */
-
-#define MSDC_DAT_RDDLY1_D4      (0x1F << 0)     /* RW */
-#define MSDC_DAT_RDDLY1_D5      (0x1F << 8)     /* RW */
-#define MSDC_DAT_RDDLY1_D6      (0x1F << 16)    /* RW */
-#define MSDC_DAT_RDDLY1_D7      (0x1F << 24)    /* RW */
-
-#define MSDC_CKGEN_MSDC_DLY_SEL   (0x1F<<10)
-#define MSDC_INT_DAT_LATCH_CK_SEL  (0x7<<7)
-#define MSDC_CKGEN_MSDC_CK_SEL     (0x1<<6)
-#define CARD_READY_FOR_DATA             (1<<8)
-#define CARD_CURRENT_STATE(x)           ((x&0x00001E00)>>9)
-
-/*--------------------------------------------------------------------------*/
-/* Descriptor Structure                                                     */
-/*--------------------------------------------------------------------------*/
-typedef struct {
-    u32  hwo:1; /* could be changed by hw */
-    u32  bdp:1;
-    u32  rsv0:6;
-    u32  chksum:8;
-    u32  intr:1;
-    u32  rsv1:15;
-    void *next;
-    void *ptr;
-    u32  buflen:16;
-    u32  extlen:8;
-    u32  rsv2:8;
-    u32  arg;
-    u32  blknum;
-    u32  cmd;
-} gpd_t;
-
-typedef struct {
-    u32  eol:1;
-    u32  rsv0:7;
-    u32  chksum:8;
-    u32  rsv1:1;
-    u32  blkpad:1;
-    u32  dwpad:1;
-    u32  rsv2:13;
-    void *next;
-    void *ptr;
-    u32  buflen:16;
-    u32  rsv3:16;
-} bd_t;
-
-/*--------------------------------------------------------------------------*/
-/* Register Debugging Structure                                             */
-/*--------------------------------------------------------------------------*/
-
-typedef struct {
-    u32 msdc:1;
-    u32 ckpwn:1;
-    u32 rst:1;
-    u32 pio:1;
-    u32 ckdrven:1;
-    u32 start18v:1;
-    u32 pass18v:1;
-    u32 ckstb:1;
-    u32 ckdiv:8;
-    u32 ckmod:2;
-    u32 pad:14;                
-} msdc_cfg_reg;
-typedef struct {
-    u32 sdr104cksel:1;
-    u32 rsmpl:1;
-    u32 dsmpl:1;
-    u32 ddlysel:1;
-    u32 ddr50ckd:1;
-    u32 dsplsel:1;
-    u32 pad1:10;
-    u32 d0spl:1;
-    u32 d1spl:1;
-    u32 d2spl:1;
-    u32 d3spl:1;
-    u32 d4spl:1;
-    u32 d5spl:1;
-    u32 d6spl:1;
-    u32 d7spl:1;
-    u32 riscsz:1;
-    u32 pad2:7;
-} msdc_iocon_reg;
-typedef struct {
-    u32 cden:1;
-    u32 cdsts:1;
-    u32 pad1:10;
-    u32 cddebounce:4;
-    u32 dat:8;
-    u32 cmd:1;
-    u32 pad2:6;
-    u32 wp:1;
-} msdc_ps_reg;
-typedef struct {
-    u32 mmcirq:1;
-    u32 cdsc:1;
-    u32 pad1:1;
-    u32 atocmdrdy:1;
-    u32 atocmdtmo:1;
-    u32 atocmdcrc:1;
-    u32 dmaqempty:1;
-    u32 sdioirq:1;
-    u32 cmdrdy:1;
-    u32 cmdtmo:1;
-    u32 rspcrc:1;
-    u32 csta:1;
-    u32 xfercomp:1;
-    u32 dxferdone:1;
-    u32 dattmo:1;
-    u32 datcrc:1;
-    u32 atocmd19done:1;
-    u32 pad2:15;
-} msdc_int_reg;
-typedef struct {
-    u32 mmcirq:1;
-    u32 cdsc:1;
-    u32 pad1:1;
-    u32 atocmdrdy:1;
-    u32 atocmdtmo:1;
-    u32 atocmdcrc:1;
-    u32 dmaqempty:1;
-    u32 sdioirq:1;
-    u32 cmdrdy:1;
-    u32 cmdtmo:1;
-    u32 rspcrc:1;
-    u32 csta:1;
-    u32 xfercomp:1;
-    u32 dxferdone:1;
-    u32 dattmo:1;
-    u32 datcrc:1;
-    u32 atocmd19done:1;
-    u32 pad2:15;
-} msdc_inten_reg;
-typedef struct {
-    u32 rxcnt:8;
-    u32 pad1:8;
-    u32 txcnt:8;
-    u32 pad2:7;
-    u32 clr:1;
-} msdc_fifocs_reg;
-typedef struct {
-    u32 val;
-} msdc_txdat_reg;
-typedef struct {
-    u32 val;
-} msdc_rxdat_reg;
-typedef struct {
-    u32 sdiowkup:1;
-    u32 inswkup:1;
-    u32 pad1:14;
-    u32 buswidth:2;
-    u32 pad2:1;
-    u32 sdio:1;
-    u32 sdioide:1;
-    u32 intblkgap:1;
-    u32 pad4:2;
-    u32 dtoc:8;
-} sdc_cfg_reg;
-typedef struct {
-    u32 cmd:6;
-    u32 brk:1;
-    u32 rsptyp:3;
-    u32 pad1:1;
-    u32 dtype:2;
-    u32 rw:1;
-    u32 stop:1;
-    u32 goirq:1;    
-    u32 blklen:12;
-    u32 atocmd:2;
-    u32 volswth:1;
-    u32 pad2:1;
-} sdc_cmd_reg;
-typedef struct {
-    u32 arg;
-} sdc_arg_reg;
-typedef struct {
-    u32 sdcbusy:1;
-    u32 cmdbusy:1;
-    u32 pad:29;
-    u32 swrcmpl:1;
-} sdc_sts_reg;
-typedef struct {
-    u32 val;
-} sdc_resp0_reg;
-typedef struct {
-    u32 val;   
-} sdc_resp1_reg;
-typedef struct {
-    u32 val;   
-} sdc_resp2_reg;
-typedef struct {
-    u32 val;   
-} sdc_resp3_reg;
-typedef struct {
-    u32 num;   
-} sdc_blknum_reg;
-typedef struct {
-    u32 sts;
-} sdc_csts_reg;
-typedef struct {
-    u32 sts;
-} sdc_cstsen_reg;
-typedef struct {
-    u32 datcrcsts:8;
-    u32 ddrcrcsts:4;
-    u32 pad:20;
-} sdc_datcrcsts_reg;
-typedef struct {
-    u32 bootstart:1;
-    u32 bootstop:1;
-    u32 bootmode:1;
-    u32 pad1:9;
-    u32 bootwaidly:3;
-    u32 bootsupp:1;
-    u32 pad2:16;
-} emmc_cfg0_reg;
-typedef struct {
-    u32 bootcrctmc:16;
-    u32 pad:4;
-    u32 bootacktmc:12;
-} emmc_cfg1_reg;
-typedef struct {
-    u32 bootcrcerr:1;
-    u32 bootackerr:1;
-    u32 bootdattmo:1;
-    u32 bootacktmo:1;
-    u32 bootupstate:1;
-    u32 bootackrcv:1;
-    u32 bootdatrcv:1;
-    u32 pad:25;
-} emmc_sts_reg;
-typedef struct {
-    u32 bootrst:1;
-    u32 pad:31;
-} emmc_iocon_reg;
-typedef struct {
-    u32 val;
-} msdc_acmd_resp_reg;
-typedef struct {
-    u32 tunesel:4;
-    u32 pad:28;
-} msdc_acmd19_trg_reg;
-typedef struct {
-    u32 val;
-} msdc_acmd19_sts_reg;
-typedef struct {
-    u32 addr;
-} msdc_dma_sa_reg;
-typedef struct {
-    u32 addr;
-} msdc_dma_ca_reg;
-typedef struct {
-    u32 start:1;
-    u32 stop:1;
-    u32 resume:1;
-    u32 pad1:5;
-    u32 mode:1;
-    u32 pad2:1;
-    u32 lastbuf:1;
-    u32 pad3:1;
-    u32 brustsz:3;
-    u32 pad4:1;
-    u32 xfersz:16;
-} msdc_dma_ctrl_reg;
-typedef struct {
-    u32 status:1;
-    u32 decsen:1;
-    u32 pad1:2;
-    u32 bdcsen:1;
-    u32 gpdcsen:1;
-    u32 pad2:26;
-} msdc_dma_cfg_reg;
-typedef struct {
-    u32 sel:16;
-    u32 pad2:16;
-} msdc_dbg_sel_reg;
-typedef struct {
-    u32 val;
-} msdc_dbg_out_reg;
-typedef struct {
-    u32 clkdrvn:3;
-    u32 rsv0:1;
-    u32 clkdrvp:3;
-    u32 rsv1:1;
-    u32 clksr:1;
-    u32 rsv2:7;
-    u32 clkpd:1;    
-    u32 clkpu:1;
-    u32 clksmt:1;
-    u32 clkies:1;
-    u32 clktdsel:4;
-    u32 clkrdsel:8;
-} msdc_pad_ctl0_reg;
-typedef struct {
-    u32 cmddrvn:3;
-    u32 rsv0:1;    
-    u32 cmddrvp:3;
-    u32 rsv1:1;
-    u32 cmdsr:1;
-    u32 rsv2:7;
-    u32 cmdpd:1;    
-    u32 cmdpu:1;
-    u32 cmdsmt:1;
-    u32 cmdies:1;
-    u32 cmdtdsel:4;
-    u32 cmdrdsel:8;
-} msdc_pad_ctl1_reg;
-typedef struct {
-    u32 datdrvn:3;
-    u32 rsv0:1;
-    u32 datdrvp:3;
-    u32 rsv1:1;
-    u32 datsr:1;
-    u32 rsv2:7;
-    u32 datpd:1;    
-    u32 datpu:1;
-    u32 datsmt:1;
-    u32 daties:1;
-    u32 dattdsel:4;
-    u32 datrdsel:8;
-} msdc_pad_ctl2_reg;
-typedef struct {
-    u32 wrrxdly:3;
-    u32 pad1:5;
-    u32 rdrxdly:8;
-    u32 pad2:16;
-} msdc_pad_tune_reg;
-typedef struct {
-    u32 dat0:5;
-    u32 rsv0:3;
-    u32 dat1:5;
-    u32 rsv1:3;
-    u32 dat2:5;
-    u32 rsv2:3;
-    u32 dat3:5;
-    u32 rsv3:3;    
-} msdc_dat_rddly0;
-typedef struct {
-    u32 dat4:5;
-    u32 rsv4:3;
-    u32 dat5:5;
-    u32 rsv5:3;
-    u32 dat6:5;
-    u32 rsv6:3;
-    u32 dat7:5;
-    u32 rsv7:3;
-} msdc_dat_rddly1;
-typedef struct {
-    u32 dbg0sel:8;
-    u32 dbg1sel:6;
-    u32 pad1:2;
-    u32 dbg2sel:6;
-    u32 pad2:2;
-    u32 dbg3sel:6;
-    u32 pad3:2;
-} msdc_hw_dbg_reg;
-typedef struct {
-    u32 val;
-} msdc_version_reg;
-typedef struct {
-    u32 val;
-} msdc_eco_ver_reg;
-
-struct msdc_regs {
-    msdc_cfg_reg        msdc_cfg;      /* base+0x00h */
-    msdc_iocon_reg      msdc_iocon;    /* base+0x04h */
-    msdc_ps_reg         msdc_ps;       /* base+0x08h */
-    msdc_int_reg        msdc_int;      /* base+0x0ch */
-    msdc_inten_reg      msdc_inten;    /* base+0x10h */
-    msdc_fifocs_reg     msdc_fifocs;   /* base+0x14h */
-    msdc_txdat_reg      msdc_txdat;    /* base+0x18h */
-    msdc_rxdat_reg      msdc_rxdat;    /* base+0x1ch */
-    u32                 rsv1[4];
-    sdc_cfg_reg         sdc_cfg;       /* base+0x30h */
-    sdc_cmd_reg         sdc_cmd;       /* base+0x34h */
-    sdc_arg_reg         sdc_arg;       /* base+0x38h */
-    sdc_sts_reg         sdc_sts;       /* base+0x3ch */
-    sdc_resp0_reg       sdc_resp0;     /* base+0x40h */
-    sdc_resp1_reg       sdc_resp1;     /* base+0x44h */
-    sdc_resp2_reg       sdc_resp2;     /* base+0x48h */
-    sdc_resp3_reg       sdc_resp3;     /* base+0x4ch */
-    sdc_blknum_reg      sdc_blknum;    /* base+0x50h */
-    u32                 rsv2[1];
-    sdc_csts_reg        sdc_csts;      /* base+0x58h */
-    sdc_cstsen_reg      sdc_cstsen;    /* base+0x5ch */
-    sdc_datcrcsts_reg   sdc_dcrcsta;   /* base+0x60h */
-    u32                 rsv3[3];
-    emmc_cfg0_reg       emmc_cfg0;     /* base+0x70h */
-    emmc_cfg1_reg       emmc_cfg1;     /* base+0x74h */
-    emmc_sts_reg        emmc_sts;      /* base+0x78h */
-    emmc_iocon_reg      emmc_iocon;    /* base+0x7ch */
-    msdc_acmd_resp_reg  acmd_resp;     /* base+0x80h */
-    msdc_acmd19_trg_reg acmd19_trg;    /* base+0x84h */
-    msdc_acmd19_sts_reg acmd19_sts;    /* base+0x88h */
-    u32                 rsv4[1];
-    msdc_dma_sa_reg     dma_sa;        /* base+0x90h */
-    msdc_dma_ca_reg     dma_ca;        /* base+0x94h */
-    msdc_dma_ctrl_reg   dma_ctrl;      /* base+0x98h */
-    msdc_dma_cfg_reg    dma_cfg;       /* base+0x9ch */
-    msdc_dbg_sel_reg    dbg_sel;       /* base+0xa0h */
-    msdc_dbg_out_reg    dbg_out;       /* base+0xa4h */
-    u32                 rsv5[2];
-    u32                 patch0;        /* base+0xb0h */
-    u32                 patch1;        /* base+0xb4h */
-    u32                 rsv6[10];
-    msdc_pad_ctl0_reg   pad_ctl0;      /* base+0xe0h */
-    msdc_pad_ctl1_reg   pad_ctl1;      /* base+0xe4h */
-    msdc_pad_ctl2_reg   pad_ctl2;      /* base+0xe8h */
-    msdc_pad_tune_reg   pad_tune;      /* base+0xech */
-    msdc_dat_rddly0     dat_rddly0;    /* base+0xf0h */
-    msdc_dat_rddly1     dat_rddly1;    /* base+0xf4h */
-    msdc_hw_dbg_reg     hw_dbg;        /* base+0xf8h */
-    u32                 rsv7[1];       
-    msdc_version_reg    version;       /* base+0x100h */
-    msdc_eco_ver_reg    eco_ver;       /* base+0x104h */
-};
-
-struct scatterlist_ex {
-    u32 cmd;
-    u32 arg;
-    u32 sglen;
-    struct scatterlist *sg;
-};
-
-#define DMA_FLAG_NONE       (0x00000000)
-#define DMA_FLAG_EN_CHKSUM  (0x00000001)
-#define DMA_FLAG_PAD_BLOCK  (0x00000002)
-#define DMA_FLAG_PAD_DWORD  (0x00000004)
-
-struct msdc_dma {
-    u32 flags;                   /* flags */
-    u32 xfersz;                  /* xfer size in bytes */
-    u32 sglen;                   /* size of scatter list */
-    u32 blklen;                  /* block size */
-    struct scatterlist *sg;      /* I/O scatter list */
-    struct scatterlist_ex *esg;  /* extended I/O scatter list */
-    u8  mode;                    /* dma mode        */
-    u8  burstsz;                 /* burst size      */
-    u8  intr;                    /* dma done interrupt */
-    u8  padding;                 /* padding */
-    u32 cmd;                     /* enhanced mode command */
-    u32 arg;                     /* enhanced mode arg */
-    u32 rsp;                     /* enhanced mode command response */
-    u32 autorsp;                 /* auto command response */
-
-    gpd_t *gpd;                  /* pointer to gpd array */
-    bd_t  *bd;                   /* pointer to bd array */
-    dma_addr_t gpd_addr;         /* the physical address of gpd array */
-    dma_addr_t bd_addr;          /* the physical address of bd array */
-    u32 used_gpd;                /* the number of used gpd elements */
-    u32 used_bd;                 /* the number of used bd elements */
-};
-
-struct msdc_host
-{
-    struct msdc_hw              *hw;
-
-    struct mmc_host             *mmc;           /* mmc structure */
-    struct mmc_command          *cmd;
-    struct mmc_data             *data;
-    struct mmc_request          *mrq; 
-    int                         cmd_rsp;
-    int                         cmd_rsp_done;
-    int                         cmd_r1b_done;
-
-    int                         error; 
-    spinlock_t                  lock;           /* mutex */
-    struct semaphore            sem; 
-
-    u32                         blksz;          /* host block size */
-    u32                         base;           /* host base address */    
-    int                         id;             /* host id */
-    int                         pwr_ref;        /* core power reference count */
-
-    u32                         xfer_size;      /* total transferred size */
-
-    struct msdc_dma             dma;            /* dma channel */
-    u32                         dma_addr;       /* dma transfer address */
-    u32                         dma_left_size;  /* dma transfer left size */
-    u32                         dma_xfer_size;  /* dma transfer size in bytes */
-    int                         dma_xfer;       /* dma transfer mode */
-
-    u32                         timeout_ns;     /* data timeout ns */
-    u32                         timeout_clks;   /* data timeout clks */
-
-    atomic_t                    abort;          /* abort transfer */
-
-    int                         irq;            /* host interrupt */
-
-    struct tasklet_struct       card_tasklet;
-#if 0
-    struct work_struct         card_workqueue;
-#else
-    struct delayed_work        card_delaywork;
-#endif
-
-    struct completion           cmd_done;
-    struct completion           xfer_done;
-    struct pm_message           pm_state;
-
-    u32                         mclk;           /* mmc subsystem clock */
-    u32                         hclk;           /* host clock speed */         
-    u32                         sclk;           /* SD/MS clock speed */
-    u8                          core_clkon;     /* Host core clock on ? */
-    u8                          card_clkon;     /* Card clock on ? */
-    u8                          core_power;     /* core power */    
-    u8                          power_mode;     /* host power mode */
-    u8                          card_inserted;  /* card inserted ? */
-    u8                          suspend;        /* host suspended ? */    
-    u8                          reserved;
-    u8                          app_cmd;        /* for app command */     
-    u32                         app_cmd_arg;    
-    u64                         starttime;
-};
-
-static inline unsigned int uffs(unsigned int x)
-{
-    unsigned int r = 1;
-
-    if (!x)
-        return 0;
-    if (!(x & 0xffff)) {
-        x >>= 16;
-        r += 16;
-    }
-    if (!(x & 0xff)) {
-        x >>= 8;
-        r += 8;
-    }
-    if (!(x & 0xf)) {
-        x >>= 4;
-        r += 4;
-    }
-    if (!(x & 3)) {
-        x >>= 2;
-        r += 2;
-    }
-    if (!(x & 1)) {
-        x >>= 1;
-        r += 1;
-    }
-    return r;
-}
-#define sdr_read8(reg)           __raw_readb(reg)
-#define sdr_read16(reg)          __raw_readw(reg)
-#define sdr_read32(reg)          __raw_readl(reg)
-#define sdr_write8(reg,val)      __raw_writeb(val,reg)
-#define sdr_write16(reg,val)     __raw_writew(val,reg)
-#define sdr_write32(reg,val)     __raw_writel(val,reg)
-
-#define sdr_set_bits(reg,bs)     ((*(volatile u32*)(reg)) |= (u32)(bs))
-#define sdr_clr_bits(reg,bs)     ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
-
-#define sdr_set_field(reg,field,val) \
-    do {       \
-        volatile unsigned int tv = sdr_read32(reg);    \
-        tv &= ~(field); \
-        tv |= ((val) << (uffs((unsigned int)field) - 1)); \
-        sdr_write32(reg,tv); \
-    } while(0)
-#define sdr_get_field(reg,field,val) \
-    do {       \
-        volatile unsigned int tv = sdr_read32(reg);    \
-        val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
-    } while(0)
-
-#endif
-
diff --git a/target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/sd.c b/target/linux/ramips/files-4.9/drivers/mmc/host/mtk-mmc/sd.c
deleted file mode 100644 (file)
index 3a146f6..0000000
+++ /dev/null
@@ -1,3056 +0,0 @@
-/* Copyright Statement:
- *
- * This software/firmware and related documentation ("MediaTek Software") are
- * protected under relevant copyright laws. The information contained herein
- * is confidential and proprietary to MediaTek Inc. and/or its licensors.
- * Without the prior written permission of MediaTek inc. and/or its licensors,
- * any reproduction, modification, use or disclosure of MediaTek Software,
- * and information contained herein, in whole or in part, shall be strictly prohibited.
- *
- * MediaTek Inc. (C) 2010. All rights reserved.
- *
- * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
- * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
- * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
- * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
- * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
- * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
- * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
- * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
- * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
- * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
- * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
- * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
- * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
- * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
- * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
- * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
- *
- * The following software/firmware and/or related documentation ("MediaTek Software")
- * have been modified by MediaTek Inc. All revisions are subject to any receiver's
- * applicable license agreements with MediaTek Inc.
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/timer.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/blkdev.h>
-#include <linux/slab.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/card.h>
-#include <linux/mmc/core.h>
-#include <linux/mmc/mmc.h>
-#include <linux/mmc/sd.h>
-#include <linux/mmc/sdio.h>
-#include <linux/dma-mapping.h>
-
-/* +++ by chhung */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/version.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-
-#define MSDC_SMPL_FALLING   (1)
-#define MSDC_CD_PIN_EN      (1 << 0)  /* card detection pin is wired   */
-#define MSDC_WP_PIN_EN      (1 << 1)  /* write protection pin is wired */
-#define MSDC_REMOVABLE      (1 << 5)  /* removable slot                */
-#define MSDC_SYS_SUSPEND    (1 << 6)  /* suspended by system           */
-#define MSDC_HIGHSPEED      (1 << 7)
-
-//#define IRQ_SDC 14   //MT7620 /*FIXME*/
-#ifdef CONFIG_SOC_MT7621
-#define RALINK_SYSCTL_BASE             0xbe000000
-#define RALINK_MSDC_BASE               0xbe130000
-#else
-#define RALINK_SYSCTL_BASE             0xb0000000
-#define RALINK_MSDC_BASE               0xb0130000
-#endif
-#define IRQ_SDC                        22      /*FIXME*/
-
-#include <asm/dma.h>
-/* end of +++ */
-
-
-#include <asm/mach-ralink/ralink_regs.h>
-
-#if 0 /* --- by chhung */
-#include <mach/board.h>
-#include <mach/mt6575_devs.h>
-#include <mach/mt6575_typedefs.h>
-#include <mach/mt6575_clock_manager.h>
-#include <mach/mt6575_pm_ldo.h>
-//#include <mach/mt6575_pll.h>
-//#include <mach/mt6575_gpio.h>
-//#include <mach/mt6575_gpt_sw.h>
-#include <asm/tcm.h>
-// #include <mach/mt6575_gpt.h>
-#endif /* end of --- */
-
-#include "mt6575_sd.h"
-#include "dbg.h"
-
-/* +++ by chhung */
-#include "board.h"
-/* end of +++ */
-
-#if 0 /* --- by chhung */
-#define isb() __asm__ __volatile__ ("" : : : "memory")
-#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
-                                   : : "r" (0) : "memory")
-#define dmb() __asm__ __volatile__ ("" : : : "memory")
-#endif /* end of --- */
-
-#define DRV_NAME            "mtk-sd"
-
-#define HOST_MAX_NUM        (1) /* +/- by chhung */
-
-#if defined (CONFIG_SOC_MT7620)
-#define HOST_MAX_MCLK       (48000000) /* +/- by chhung */
-#elif defined (CONFIG_SOC_MT7621)
-#define HOST_MAX_MCLK       (50000000) /* +/- by chhung */
-#endif
-#define HOST_MIN_MCLK       (260000)
-
-#define HOST_MAX_BLKSZ      (2048)
-
-#define MSDC_OCR_AVAIL      (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
-
-#define GPIO_PULL_DOWN      (0)
-#define GPIO_PULL_UP        (1)
-
-#if 0 /* --- by chhung */
-#define MSDC_CLKSRC_REG     (0xf100000C)
-#define PDN_REG           (0xF1000010) 
-#endif /* end of --- */
-
-#define DEFAULT_DEBOUNCE    (8)       /* 8 cycles */
-#define DEFAULT_DTOC        (40)      /* data timeout counter. 65536x40 sclk. */
-
-#define CMD_TIMEOUT         (HZ/10)     /* 100ms */
-#define DAT_TIMEOUT         (HZ/2 * 5)  /* 500ms x5 */
-
-#define MAX_DMA_CNT         (64 * 1024 - 512)   /* a single transaction for WIFI may be 50K*/
-
-#define MAX_GPD_NUM         (1 + 1)  /* one null gpd */
-#define MAX_BD_NUM          (1024)
-#define MAX_BD_PER_GPD      (MAX_BD_NUM)
-
-#define MAX_HW_SGMTS        (MAX_BD_NUM)
-#define MAX_PHY_SGMTS       (MAX_BD_NUM)
-#define MAX_SGMT_SZ         (MAX_DMA_CNT)
-#define MAX_REQ_SZ          (MAX_SGMT_SZ * 8)  
-
-static int mtk_sw_poll;
-
-static int cd_active_low = 1;
-
-//=================================
-#define PERI_MSDC0_PDN      (15)
-//#define PERI_MSDC1_PDN    (16)
-//#define PERI_MSDC2_PDN    (17)
-//#define PERI_MSDC3_PDN    (18)
-
-#if 0 /* --- by chhung */
-/* gate means clock power down */
-static int g_clk_gate = 0; 
-#define msdc_gate_clock(id) \
-    do { \
-        g_clk_gate &= ~(1 << ((id) + PERI_MSDC0_PDN)); \
-    } while(0)
-/* not like power down register. 1 means clock on. */
-#define msdc_ungate_clock(id) \
-    do { \
-        g_clk_gate |= 1 << ((id) + PERI_MSDC0_PDN); \
-    } while(0)
-
-// do we need sync object or not 
-void msdc_clk_status(int * status)
-{
-    *status = g_clk_gate;      
-}
-#endif /* end of --- */
-
-/* +++ by chhung */
-struct msdc_hw msdc0_hw = {
-       .clk_src        = 0,
-       .cmd_edge       = MSDC_SMPL_FALLING,
-       .data_edge      = MSDC_SMPL_FALLING,
-       .clk_drv        = 4,
-       .cmd_drv        = 4,
-       .dat_drv        = 4,
-       .data_pins      = 4,
-       .data_offset    = 0,
-       .flags          = MSDC_SYS_SUSPEND | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
-//     .flags          = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,
-};
-
-static struct resource mtk_sd_resources[] = {
-       [0] = {
-               .start  = RALINK_MSDC_BASE,
-               .end    = RALINK_MSDC_BASE+0x3fff,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = IRQ_SDC,      /*FIXME*/
-               .end    = IRQ_SDC,      /*FIXME*/
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device mtk_sd_device = {
-       .name           = "mtk-sd",
-       .id             = 0,
-       .num_resources  = ARRAY_SIZE(mtk_sd_resources),
-       .resource       = mtk_sd_resources,
-};
-/* end of +++ */
-
-static int msdc_rsp[] = {
-    0,  /* RESP_NONE */
-    1,  /* RESP_R1 */
-    2,  /* RESP_R2 */
-    3,  /* RESP_R3 */
-    4,  /* RESP_R4 */
-    1,  /* RESP_R5 */
-    1,  /* RESP_R6 */
-    1,  /* RESP_R7 */
-    7,  /* RESP_R1b */
-};
-
-/* For Inhanced DMA */
-#define msdc_init_gpd_ex(gpd,extlen,cmd,arg,blknum) \
-    do { \
-        ((gpd_t*)gpd)->extlen = extlen; \
-        ((gpd_t*)gpd)->cmd    = cmd; \
-        ((gpd_t*)gpd)->arg    = arg; \
-        ((gpd_t*)gpd)->blknum = blknum; \
-    }while(0)
-    
-#define msdc_init_bd(bd, blkpad, dwpad, dptr, dlen) \
-    do { \
-        BUG_ON(dlen > 0xFFFFUL); \
-        ((bd_t*)bd)->blkpad = blkpad; \
-        ((bd_t*)bd)->dwpad  = dwpad; \
-        ((bd_t*)bd)->ptr    = (void*)dptr; \
-        ((bd_t*)bd)->buflen = dlen; \
-    }while(0)
-
-#define msdc_txfifocnt()   ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
-#define msdc_rxfifocnt()   ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
-#define msdc_fifo_write32(v)   sdr_write32(MSDC_TXDATA, (v))
-#define msdc_fifo_write8(v)    sdr_write8(MSDC_TXDATA, (v))
-#define msdc_fifo_read32()   sdr_read32(MSDC_RXDATA)
-#define msdc_fifo_read8()    sdr_read8(MSDC_RXDATA)    
-
-
-#define msdc_dma_on()        sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)
-#define msdc_dma_off()       sdr_set_bits(MSDC_CFG, MSDC_CFG_PIO)
-
-#define msdc_retry(expr,retry,cnt) \
-    do { \
-        int backup = cnt; \
-        while (retry) { \
-            if (!(expr)) break; \
-            if (cnt-- == 0) { \
-                retry--; mdelay(1); cnt = backup; \
-            } \
-        } \
-        WARN_ON(retry == 0); \
-    } while(0)
-
-#if 0 /* --- by chhung */
-#define msdc_reset() \
-    do { \
-        int retry = 3, cnt = 1000; \
-        sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
-        dsb(); \
-        msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
-    } while(0)
-#else
-#define msdc_reset() \
-    do { \
-        int retry = 3, cnt = 1000; \
-        sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
-        msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
-    } while(0)
-#endif /* end of +/- */
-
-#define msdc_clr_int() \
-    do { \
-        volatile u32 val = sdr_read32(MSDC_INT); \
-        sdr_write32(MSDC_INT, val); \
-    } while(0)
-
-#define msdc_clr_fifo() \
-    do { \
-        int retry = 3, cnt = 1000; \
-        sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
-        msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \
-    } while(0)
-
-#define msdc_irq_save(val) \
-    do { \
-        val = sdr_read32(MSDC_INTEN); \
-        sdr_clr_bits(MSDC_INTEN, val); \
-    } while(0)
-       
-#define msdc_irq_restore(val) \
-    do { \
-        sdr_set_bits(MSDC_INTEN, val); \
-    } while(0)
-
-/* clock source for host: global */
-#if defined (CONFIG_SOC_MT7620)
-static u32 hclks[] = {48000000}; /* +/- by chhung */
-#elif defined (CONFIG_SOC_MT7621)
-static u32 hclks[] = {50000000}; /* +/- by chhung */
-#endif
-
-//============================================
-// the power for msdc host controller: global
-//    always keep the VMC on. 
-//============================================
-#define msdc_vcore_on(host) \
-    do { \
-        INIT_MSG("[+]VMC ref. count<%d>", ++host->pwr_ref); \
-        (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
-    } while (0)
-#define msdc_vcore_off(host) \
-    do { \
-        INIT_MSG("[-]VMC ref. count<%d>", --host->pwr_ref); \
-        (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
-    } while (0)
-
-//====================================
-// the vdd output for card: global 
-//   always keep the VMCH on. 
-//==================================== 
-#define msdc_vdd_on(host) \
-    do { \
-        (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
-    } while (0)   
-#define msdc_vdd_off(host) \
-    do { \
-        (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
-    } while (0)      
-
-#define sdc_is_busy()          (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)
-#define sdc_is_cmd_busy()      (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)
-
-#define sdc_send_cmd(cmd,arg) \
-    do { \
-        sdr_write32(SDC_ARG, (arg)); \
-        sdr_write32(SDC_CMD, (cmd)); \
-    } while(0)
-
-// can modify to read h/w register.
-//#define is_card_present(h)   ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1);
-#define is_card_present(h)     (((struct msdc_host*)(h))->card_inserted)
-
-/* +++ by chhung */
-#ifndef __ASSEMBLY__
-#define PHYSADDR(a)             (((unsigned long)(a)) & 0x1fffffff)
-#else
-#define PHYSADDR(a)             ((a) & 0x1fffffff)
-#endif
-/* end of +++ */
-static unsigned int msdc_do_command(struct msdc_host   *host, 
-                                      struct mmc_command *cmd,
-                                      int                 tune,
-                                      unsigned long       timeout);  
-                                     
-static int msdc_tune_cmdrsp(struct msdc_host*host,struct mmc_command *cmd);
-
-#ifdef MT6575_SD_DEBUG
-static void msdc_dump_card_status(struct msdc_host *host, u32 status)
-{
-    static char *state[] = {
-        "Idle",                        /* 0 */
-        "Ready",               /* 1 */
-        "Ident",               /* 2 */
-        "Stby",                        /* 3 */
-        "Tran",                        /* 4 */
-        "Data",                        /* 5 */
-        "Rcv",                 /* 6 */
-        "Prg",                 /* 7 */
-        "Dis",                 /* 8 */
-        "Reserved",            /* 9 */
-        "Reserved",            /* 10 */
-        "Reserved",            /* 11 */
-        "Reserved",            /* 12 */
-        "Reserved",            /* 13 */
-        "Reserved",            /* 14 */
-        "I/O mode",            /* 15 */
-    };
-    if (status & R1_OUT_OF_RANGE)
-        N_MSG(RSP, "[CARD_STATUS] Out of Range");
-    if (status & R1_ADDRESS_ERROR)
-        N_MSG(RSP, "[CARD_STATUS] Address Error");
-    if (status & R1_BLOCK_LEN_ERROR)
-        N_MSG(RSP, "[CARD_STATUS] Block Len Error");
-    if (status & R1_ERASE_SEQ_ERROR)
-        N_MSG(RSP, "[CARD_STATUS] Erase Seq Error");
-    if (status & R1_ERASE_PARAM)
-        N_MSG(RSP, "[CARD_STATUS] Erase Param");
-    if (status & R1_WP_VIOLATION)
-        N_MSG(RSP, "[CARD_STATUS] WP Violation");
-    if (status & R1_CARD_IS_LOCKED)
-        N_MSG(RSP, "[CARD_STATUS] Card is Locked");
-    if (status & R1_LOCK_UNLOCK_FAILED)
-        N_MSG(RSP, "[CARD_STATUS] Lock/Unlock Failed");
-    if (status & R1_COM_CRC_ERROR)
-        N_MSG(RSP, "[CARD_STATUS] Command CRC Error");
-    if (status & R1_ILLEGAL_COMMAND)
-        N_MSG(RSP, "[CARD_STATUS] Illegal Command");
-    if (status & R1_CARD_ECC_FAILED)
-        N_MSG(RSP, "[CARD_STATUS] Card ECC Failed");
-    if (status & R1_CC_ERROR)
-        N_MSG(RSP, "[CARD_STATUS] CC Error");
-    if (status & R1_ERROR)
-        N_MSG(RSP, "[CARD_STATUS] Error");
-    if (status & R1_UNDERRUN)
-        N_MSG(RSP, "[CARD_STATUS] Underrun");
-    if (status & R1_OVERRUN)
-        N_MSG(RSP, "[CARD_STATUS] Overrun");
-    if (status & R1_CID_CSD_OVERWRITE)
-        N_MSG(RSP, "[CARD_STATUS] CID/CSD Overwrite");
-    if (status & R1_WP_ERASE_SKIP)
-        N_MSG(RSP, "[CARD_STATUS] WP Eraser Skip");
-    if (status & R1_CARD_ECC_DISABLED)
-        N_MSG(RSP, "[CARD_STATUS] Card ECC Disabled");
-    if (status & R1_ERASE_RESET)
-        N_MSG(RSP, "[CARD_STATUS] Erase Reset");
-    if (status & R1_READY_FOR_DATA)
-        N_MSG(RSP, "[CARD_STATUS] Ready for Data");
-    if (status & R1_SWITCH_ERROR)
-        N_MSG(RSP, "[CARD_STATUS] Switch error");
-    if (status & R1_APP_CMD)
-        N_MSG(RSP, "[CARD_STATUS] App Command");
-    
-    N_MSG(RSP, "[CARD_STATUS] '%s' State", state[R1_CURRENT_STATE(status)]);
-}
-
-static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)
-{
-    if (resp & (1 << 7))
-        N_MSG(RSP, "[OCR] Low Voltage Range");
-    if (resp & (1 << 15))
-        N_MSG(RSP, "[OCR] 2.7-2.8 volt");
-    if (resp & (1 << 16))
-        N_MSG(RSP, "[OCR] 2.8-2.9 volt");
-    if (resp & (1 << 17))
-        N_MSG(RSP, "[OCR] 2.9-3.0 volt");
-    if (resp & (1 << 18))
-        N_MSG(RSP, "[OCR] 3.0-3.1 volt");
-    if (resp & (1 << 19))
-        N_MSG(RSP, "[OCR] 3.1-3.2 volt");
-    if (resp & (1 << 20))
-        N_MSG(RSP, "[OCR] 3.2-3.3 volt");
-    if (resp & (1 << 21))
-        N_MSG(RSP, "[OCR] 3.3-3.4 volt");
-    if (resp & (1 << 22))
-        N_MSG(RSP, "[OCR] 3.4-3.5 volt");
-    if (resp & (1 << 23))
-        N_MSG(RSP, "[OCR] 3.5-3.6 volt");
-    if (resp & (1 << 24))
-        N_MSG(RSP, "[OCR] Switching to 1.8V Accepted (S18A)");
-    if (resp & (1 << 30))
-        N_MSG(RSP, "[OCR] Card Capacity Status (CCS)");
-    if (resp & (1 << 31))
-        N_MSG(RSP, "[OCR] Card Power Up Status (Idle)");
-    else
-        N_MSG(RSP, "[OCR] Card Power Up Status (Busy)");
-}
-
-static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)
-{
-    u32 status = (((resp >> 15) & 0x1) << 23) |
-                 (((resp >> 14) & 0x1) << 22) |
-                 (((resp >> 13) & 0x1) << 19) |
-                   (resp & 0x1fff);
-    
-    N_MSG(RSP, "[RCA] 0x%.4x", resp >> 16);
-    msdc_dump_card_status(host, status);       
-}
-
-static void msdc_dump_io_resp(struct msdc_host *host, u32 resp)
-{
-    u32 flags = (resp >> 8) & 0xFF;
-    char *state[] = {"DIS", "CMD", "TRN", "RFU"};
-    
-    if (flags & (1 << 7))
-        N_MSG(RSP, "[IO] COM_CRC_ERR");
-    if (flags & (1 << 6))
-        N_MSG(RSP, "[IO] Illgal command");   
-    if (flags & (1 << 3))
-        N_MSG(RSP, "[IO] Error");
-    if (flags & (1 << 2))
-        N_MSG(RSP, "[IO] RFU");
-    if (flags & (1 << 1))
-        N_MSG(RSP, "[IO] Function number error");
-    if (flags & (1 << 0))
-        N_MSG(RSP, "[IO] Out of range");
-
-    N_MSG(RSP, "[IO] State: %s, Data:0x%x", state[(resp >> 12) & 0x3], resp & 0xFF);
-}
-#endif
-
-static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
-{
-    u32 base = host->base;
-    u32 timeout, clk_ns;
-
-    host->timeout_ns   = ns;
-    host->timeout_clks = clks;
-
-    clk_ns  = 1000000000UL / host->sclk;
-    timeout = ns / clk_ns + clks;
-    timeout = timeout >> 16; /* in 65536 sclk cycle unit */
-    timeout = timeout > 1 ? timeout - 1 : 0;
-    timeout = timeout > 255 ? 255 : timeout;
-
-    sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout);
-
-    N_MSG(OPS, "Set read data timeout: %dns %dclks -> %d x 65536 cycles",
-        ns, clks, timeout + 1);
-}
-
-/* msdc_eirq_sdio() will be called when EIRQ(for WIFI) */
-static void msdc_eirq_sdio(void *data)
-{
-    struct msdc_host *host = (struct msdc_host *)data;
-
-    N_MSG(INT, "SDIO EINT");
-
-    mmc_signal_sdio_irq(host->mmc);
-}
-
-/* msdc_eirq_cd will not be used!  We not using EINT for card detection. */
-static void msdc_eirq_cd(void *data)
-{
-    struct msdc_host *host = (struct msdc_host *)data;
-
-    N_MSG(INT, "CD EINT");
-
-#if 0
-    tasklet_hi_schedule(&host->card_tasklet);
-#else
-    schedule_delayed_work(&host->card_delaywork, HZ);
-#endif
-}
-
-#if 0
-static void msdc_tasklet_card(unsigned long arg)
-{
-    struct msdc_host *host = (struct msdc_host *)arg;
-#else
-static void msdc_tasklet_card(struct work_struct *work)
-{
-    struct msdc_host *host = (struct msdc_host *)container_of(work, 
-                               struct msdc_host, card_delaywork.work);
-#endif
-    struct msdc_hw *hw = host->hw;
-    u32 base = host->base;
-    u32 inserted;      
-    u32 status = 0;
-    //u32 change = 0;
-
-    spin_lock(&host->lock);
-
-    if (hw->get_cd_status) { // NULL
-       inserted = hw->get_cd_status();
-    } else {
-        status = sdr_read32(MSDC_PS);
-        if (cd_active_low)
-               inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
-       else
-               inserted = (status & MSDC_PS_CDSTS) ? 1 : 0;
-    }
-    if (host->mmc->caps & MMC_CAP_NEEDS_POLL)
-        inserted = 1;
-
-#if 0
-    change = host->card_inserted ^ inserted;
-    host->card_inserted = inserted;
-       
-    if (change && !host->suspend) {
-        if (inserted) {
-            host->mmc->f_max = HOST_MAX_MCLK;  // work around                  
-        }      
-        mmc_detect_change(host->mmc, msecs_to_jiffies(20));
-    }
-#else  /* Make sure: handle the last interrupt */
-    host->card_inserted = inserted;    
-    
-    if (!host->suspend) {
-        host->mmc->f_max = HOST_MAX_MCLK;      
-        mmc_detect_change(host->mmc, msecs_to_jiffies(20));
-    }   
-    
-    IRQ_MSG("card found<%s>", inserted ? "inserted" : "removed");      
-#endif
-
-    spin_unlock(&host->lock);
-}
-
-#if 0 /* --- by chhung */
-/* For E2 only */
-static u8 clk_src_bit[4] = {
-   0, 3, 5, 7          
-};
-
-static void msdc_select_clksrc(struct msdc_host* host, unsigned char clksrc)
-{
-    u32 val; 
-    u32 base = host->base;
-        
-    BUG_ON(clksrc > 3);        
-    INIT_MSG("set clock source to <%d>", clksrc);      
-
-    val = sdr_read32(MSDC_CLKSRC_REG);      
-    if (sdr_read32(MSDC_ECO_VER) >= 4) {
-        val &= ~(0x3  << clk_src_bit[host->id]); 
-        val |= clksrc << clk_src_bit[host->id];                        
-    } else {        
-        val &= ~0x3; val |= clksrc;
-    }    
-    sdr_write32(MSDC_CLKSRC_REG, val);
-            
-    host->hclk = hclks[clksrc];     
-    host->hw->clk_src = clksrc;
-}
-#endif /* end of --- */
-
-static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
-{
-    //struct msdc_hw *hw = host->hw;
-    u32 base = host->base;
-    u32 mode;
-    u32 flags;
-    u32 div;
-    u32 sclk;
-    u32 hclk = host->hclk;
-    //u8  clksrc = hw->clk_src;
-
-    if (!hz) { // set mmc system clock to 0 ?
-        //ERR_MSG("set mclk to 0!!!");
-        msdc_reset();
-        return;
-    }
-
-    msdc_irq_save(flags);
-    
-#if defined (CONFIG_MT7621_FPGA) || defined (CONFIG_MT7628_FPGA)
-    mode = 0x0; /* use divisor */
-    if (hz >= (hclk >> 1)) {
-           div  = 0;         /* mean div = 1/2 */
-           sclk = hclk >> 1; /* sclk = clk / 2 */
-    } else {
-           div  = (hclk + ((hz << 2) - 1)) / (hz << 2);
-           sclk = (hclk >> 2) / div;
-    }
-#else
-    if (ddr) {
-        mode = 0x2; /* ddr mode and use divisor */
-        if (hz >= (hclk >> 2)) {
-               div  = 1;         /* mean div = 1/4 */
-               sclk = hclk >> 2; /* sclk = clk / 4 */
-        } else {
-               div  = (hclk + ((hz << 2) - 1)) / (hz << 2);
-               sclk = (hclk >> 2) / div;
-        }
-    } else if (hz >= hclk) { /* bug fix */
-        mode = 0x1; /* no divisor and divisor is ignored */
-        div  = 0;
-        sclk = hclk; 
-    } else {
-        mode = 0x0; /* use divisor */
-        if (hz >= (hclk >> 1)) {
-               div  = 0;         /* mean div = 1/2 */
-               sclk = hclk >> 1; /* sclk = clk / 2 */
-        } else {
-               div  = (hclk + ((hz << 2) - 1)) / (hz << 2);
-               sclk = (hclk >> 2) / div;
-        }
-    }    
-#endif
-    /* set clock mode and divisor */
-    sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode);
-    sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div);
-   
-    /* wait clock stable */
-    while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB));
-
-    host->sclk = sclk;
-    host->mclk = hz;
-    msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); // need?
-     
-    INIT_MSG("================");  
-    INIT_MSG("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>", hz/1000, hclk/1000, sclk/1000); 
-    INIT_MSG("================");
-
-    msdc_irq_restore(flags);
-}
-
-/* Fix me. when need to abort */
-static void msdc_abort_data(struct msdc_host *host)
-{
-         u32 base = host->base;
-         struct mmc_command *stop = host->mrq->stop;
-
-    ERR_MSG("Need to Abort. dma<%d>", host->dma_xfer);
-    
-    msdc_reset();
-    msdc_clr_fifo();        
-    msdc_clr_int();
-
-    // need to check FIFO count 0 ?
-    
-    if (stop) {  /* try to stop, but may not success */
-        ERR_MSG("stop when abort CMD<%d>", stop->opcode);      
-        (void)msdc_do_command(host, stop, 0, CMD_TIMEOUT);
-    }
-    
-    //if (host->mclk >= 25000000) {
-    //      msdc_set_mclk(host, 0, host->mclk >> 1);
-    //}
-}
-
-#if 0 /* --- by chhung */
-static void msdc_pin_config(struct msdc_host *host, int mode)
-{
-    struct msdc_hw *hw = host->hw;
-    u32 base = host->base;
-    int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
-
-    /* Config WP pin */
-    if (hw->flags & MSDC_WP_PIN_EN) {
-        if (hw->config_gpio_pin) /* NULL */
-            hw->config_gpio_pin(MSDC_WP_PIN, pull);
-    }
-
-    switch (mode) {
-    case MSDC_PIN_PULL_UP:
-        //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 1); /* Check & FIXME */
-        //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
-        sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 1);
-        sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
-        sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 1);
-        sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
-        break;
-    case MSDC_PIN_PULL_DOWN:
-        //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
-        //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 1); /* Check & FIXME */
-        sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
-        sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 1);
-        sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
-        sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 1);
-        break;
-    case MSDC_PIN_PULL_NONE:
-    default:
-        //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
-        //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
-        sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
-        sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
-        sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
-        sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
-        break;
-    }
-    
-    N_MSG(CFG, "Pins mode(%d), down(%d), up(%d)", 
-        mode, MSDC_PIN_PULL_DOWN, MSDC_PIN_PULL_UP);
-}
-
-void msdc_pin_reset(struct msdc_host *host, int mode)
-{
-    struct msdc_hw *hw = (struct msdc_hw *)host->hw;
-    u32 base = host->base;
-    int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
-
-    /* Config reset pin */
-    if (hw->flags & MSDC_RST_PIN_EN) {
-        if (hw->config_gpio_pin) /* NULL */
-            hw->config_gpio_pin(MSDC_RST_PIN, pull);
-
-        if (mode == MSDC_PIN_PULL_UP) {
-            sdr_clr_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
-        } else {
-            sdr_set_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
-        }
-    }
-}
-
-static void msdc_core_power(struct msdc_host *host, int on)
-{
-    N_MSG(CFG, "Turn %s %s power (copower: %d -> %d)", 
-        on ? "on" : "off", "core", host->core_power, on);
-
-    if (on && host->core_power == 0) {
-        msdc_vcore_on(host);
-        host->core_power = 1;
-        msleep(1);
-    } else if (!on && host->core_power == 1) {
-        msdc_vcore_off(host);
-        host->core_power = 0;
-        msleep(1);
-    }
-}
-
-static void msdc_host_power(struct msdc_host *host, int on)
-{
-    N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "host");
-
-    if (on) {
-        //msdc_core_power(host, 1); // need do card detection. 
-        msdc_pin_reset(host, MSDC_PIN_PULL_UP);
-    } else {
-        msdc_pin_reset(host, MSDC_PIN_PULL_DOWN);
-        //msdc_core_power(host, 0);
-    }
-}
-
-static void msdc_card_power(struct msdc_host *host, int on)
-{
-    N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "card");
-
-    if (on) {
-        msdc_pin_config(host, MSDC_PIN_PULL_UP);    
-        if (host->hw->ext_power_on) {
-            host->hw->ext_power_on();
-        } else {
-            //msdc_vdd_on(host);  // need todo card detection.
-        }
-        msleep(1);
-    } else {
-        if (host->hw->ext_power_off) {
-            host->hw->ext_power_off();
-        } else {
-            //msdc_vdd_off(host);
-        }
-        msdc_pin_config(host, MSDC_PIN_PULL_DOWN);
-        msleep(1);
-    }
-}
-
-static void msdc_set_power_mode(struct msdc_host *host, u8 mode)
-{
-    N_MSG(CFG, "Set power mode(%d)", mode);
-
-    if (host->power_mode == MMC_POWER_OFF && mode != MMC_POWER_OFF) {
-        msdc_host_power(host, 1);
-        msdc_card_power(host, 1);
-    } else if (host->power_mode != MMC_POWER_OFF && mode == MMC_POWER_OFF) {
-        msdc_card_power(host, 0);
-        msdc_host_power(host, 0);
-    }
-    host->power_mode = mode;
-}
-#endif /* end of --- */
-
-#ifdef CONFIG_PM
-/*
-   register as callback function of WIFI(combo_sdio_register_pm) .    
-   can called by msdc_drv_suspend/resume too. 
-*/
-static void msdc_pm(pm_message_t state, void *data)
-{
-    struct msdc_host *host = (struct msdc_host *)data;
-    int evt = state.event;
-
-    if (evt == PM_EVENT_USER_RESUME || evt == PM_EVENT_USER_SUSPEND) {
-        INIT_MSG("USR_%s: suspend<%d> power<%d>", 
-                   evt == PM_EVENT_USER_RESUME ? "EVENT_USER_RESUME" : "EVENT_USER_SUSPEND", 
-                   host->suspend, host->power_mode);           
-    }
-
-    if (evt == PM_EVENT_SUSPEND || evt == PM_EVENT_USER_SUSPEND) {
-        if (host->suspend) /* already suspend */  /* default 0*/
-            return;
-
-        /* for memory card. already power off by mmc */
-        if (evt == PM_EVENT_SUSPEND && host->power_mode == MMC_POWER_OFF)  
-            return;
-
-        host->suspend = 1;
-        host->pm_state = state;  /* default PMSG_RESUME */
-        
-        INIT_MSG("%s Suspend", evt == PM_EVENT_SUSPEND ? "PM" : "USR");                        
-        if(host->hw->flags & MSDC_SYS_SUSPEND) /* set for card */
-            (void)mmc_suspend_host(host->mmc);
-        else { 
-            // host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY;  /* just for double confirm */ /* --- by chhung */
-            mmc_remove_host(host->mmc);
-        }
-    } else if (evt == PM_EVENT_RESUME || evt == PM_EVENT_USER_RESUME) {
-        if (!host->suspend){
-            //ERR_MSG("warning: already resume");      
-            return;
-        }
-
-        /* No PM resume when USR suspend */
-        if (evt == PM_EVENT_RESUME && host->pm_state.event == PM_EVENT_USER_SUSPEND) {
-            ERR_MSG("PM Resume when in USR Suspend");          /* won't happen. */
-            return;
-        }
-        
-        host->suspend = 0;
-        host->pm_state = state;
-        
-        INIT_MSG("%s Resume", evt == PM_EVENT_RESUME ? "PM" : "USR");                
-        if(host->hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
-            (void)mmc_resume_host(host->mmc);
-        }
-        else { 
-            // host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* --- by chhung */
-            mmc_add_host(host->mmc);
-        }
-    }
-}
-#endif
-
-/*--------------------------------------------------------------------------*/
-/* mmc_host_ops members                                                      */
-/*--------------------------------------------------------------------------*/
-static unsigned int msdc_command_start(struct msdc_host   *host, 
-                                      struct mmc_command *cmd,
-                                      int                 tune,   /* not used */
-                                      unsigned long       timeout)
-{
-    u32 base = host->base;
-    u32 opcode = cmd->opcode;
-    u32 rawcmd;
-    u32 wints = MSDC_INT_CMDRDY  | MSDC_INT_RSPCRCERR  | MSDC_INT_CMDTMO  |  
-                MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | 
-                MSDC_INT_ACMD19_DONE;  
-                   
-    u32 resp;  
-    unsigned long tmo;
-
-    /* Protocol layer does not provide response type, but our hardware needs 
-     * to know exact type, not just size!
-     */
-    if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND)
-        resp = RESP_R3;
-    else if (opcode == MMC_SET_RELATIVE_ADDR || opcode == SD_SEND_RELATIVE_ADDR)
-        resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
-    else if (opcode == MMC_FAST_IO)
-        resp = RESP_R4;
-    else if (opcode == MMC_GO_IRQ_STATE)
-        resp = RESP_R5;
-    else if (opcode == MMC_SELECT_CARD)
-        resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
-    else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED)
-        resp = RESP_R1; /* SDIO workaround. */
-    else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR))
-        resp = RESP_R1;
-    else {
-        switch (mmc_resp_type(cmd)) {
-        case MMC_RSP_R1:
-            resp = RESP_R1;
-            break;
-        case MMC_RSP_R1B:
-            resp = RESP_R1B;
-            break;
-        case MMC_RSP_R2:
-            resp = RESP_R2;
-            break;
-        case MMC_RSP_R3:
-            resp = RESP_R3;
-            break;
-        case MMC_RSP_NONE:
-        default:
-            resp = RESP_NONE;              
-            break;
-        }
-    }
-
-    cmd->error = 0;
-    /* rawcmd :
-     * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 
-     * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
-     */    
-    rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
-    
-    if (opcode == MMC_READ_MULTIPLE_BLOCK) {
-        rawcmd |= (2 << 11);
-    } else if (opcode == MMC_READ_SINGLE_BLOCK) {
-        rawcmd |= (1 << 11);
-    } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
-        rawcmd |= ((2 << 11) | (1 << 13));
-    } else if (opcode == MMC_WRITE_BLOCK) {
-        rawcmd |= ((1 << 11) | (1 << 13));
-    } else if (opcode == SD_IO_RW_EXTENDED) {
-        if (cmd->data->flags & MMC_DATA_WRITE)
-            rawcmd |= (1 << 13);
-        if (cmd->data->blocks > 1)
-            rawcmd |= (2 << 11);
-        else
-            rawcmd |= (1 << 11);
-    } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
-        rawcmd |= (1 << 14);
-    } else if ((opcode == SD_APP_SEND_SCR) || 
-        (opcode == SD_APP_SEND_NUM_WR_BLKS) ||
-        (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
-        (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
-        (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
-        rawcmd |= (1 << 11);
-    } else if (opcode == MMC_STOP_TRANSMISSION) {
-        rawcmd |= (1 << 14);
-        rawcmd &= ~(0x0FFF << 16);
-    }
-
-    N_MSG(CMD, "CMD<%d><0x%.8x> Arg<0x%.8x>", opcode , rawcmd, cmd->arg);
-
-    tmo = jiffies + timeout;
-
-    if (opcode == MMC_SEND_STATUS) {
-        for (;;) {
-            if (!sdc_is_cmd_busy())
-                break;
-                
-            if (time_after(jiffies, tmo)) {
-                ERR_MSG("XXX cmd_busy timeout: before CMD<%d>", opcode);       
-                cmd->error = (unsigned int)-ETIMEDOUT;
-                msdc_reset();
-                goto end;
-            } 
-        }
-    }else {
-        for (;;) {      
-            if (!sdc_is_busy())
-                break;
-            if (time_after(jiffies, tmo)) {
-                ERR_MSG("XXX sdc_busy timeout: before CMD<%d>", opcode);       
-                cmd->error = (unsigned int)-ETIMEDOUT;
-                msdc_reset();
-                goto end;      
-            }   
-        }    
-    }   
-    
-    //BUG_ON(in_interrupt());
-    host->cmd     = cmd;
-    host->cmd_rsp = resp;              
-    
-    init_completion(&host->cmd_done);     
-
-    sdr_set_bits(MSDC_INTEN, wints);          
-    sdc_send_cmd(rawcmd, cmd->arg);        
-      
-end:           
-    return cmd->error;
-}
-
-static unsigned int msdc_command_resp(struct msdc_host   *host, 
-                                      struct mmc_command *cmd,
-                                      int                 tune,
-                                      unsigned long       timeout)
-{
-    u32 base = host->base;
-    u32 opcode = cmd->opcode;
-    //u32 rawcmd;
-    u32 resp;
-    u32 wints = MSDC_INT_CMDRDY  | MSDC_INT_RSPCRCERR  | MSDC_INT_CMDTMO  |  
-                MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | 
-                MSDC_INT_ACMD19_DONE;     
-    
-    resp = host->cmd_rsp;
-
-    BUG_ON(in_interrupt());
-    //init_completion(&host->cmd_done);
-    //sdr_set_bits(MSDC_INTEN, wints);
-        
-    spin_unlock(&host->lock);   
-    if(!wait_for_completion_timeout(&host->cmd_done, 10*timeout)){       
-        ERR_MSG("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>", opcode, cmd->arg);
-        cmd->error = (unsigned int)-ETIMEDOUT;
-        msdc_reset();
-    }    
-    spin_lock(&host->lock);
-
-    sdr_clr_bits(MSDC_INTEN, wints);
-    host->cmd = NULL;
-
-//end:
-#ifdef MT6575_SD_DEBUG
-    switch (resp) {
-    case RESP_NONE:
-        N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)", opcode, cmd->error, resp);
-        break;
-    case RESP_R2:
-        N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= %.8x %.8x %.8x %.8x", 
-            opcode, cmd->error, resp, cmd->resp[0], cmd->resp[1], 
-            cmd->resp[2], cmd->resp[3]);          
-        break;
-    default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
-        N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= 0x%.8x", 
-            opcode, cmd->error, resp, cmd->resp[0]);
-        if (cmd->error == 0) {
-            switch (resp) {
-            case RESP_R1:
-            case RESP_R1B:
-                msdc_dump_card_status(host, cmd->resp[0]);
-                break;
-            case RESP_R3:
-                msdc_dump_ocr_reg(host, cmd->resp[0]);
-                break;
-            case RESP_R5:
-                msdc_dump_io_resp(host, cmd->resp[0]);
-                break;
-            case RESP_R6:
-                msdc_dump_rca_resp(host, cmd->resp[0]);
-                break;
-            }
-        }
-        break;
-    }
-#endif
-
-    /* do we need to save card's RCA when SD_SEND_RELATIVE_ADDR */   
-
-    if (!tune) {
-        return cmd->error;     
-    }
-
-    /* memory card CRC */     
-    if(host->hw->flags & MSDC_REMOVABLE && cmd->error == (unsigned int)(-EIO) ) {          
-        if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */ 
-            msdc_abort_data(host);
-        } else {
-            /* do basic: reset*/       
-            msdc_reset();
-            msdc_clr_fifo();        
-            msdc_clr_int();            
-        } 
-        cmd->error = msdc_tune_cmdrsp(host,cmd); 
-    }
-
-    //  check DAT0 
-    /* if (resp == RESP_R1B) {
-        while ((sdr_read32(MSDC_PS) & 0x10000) != 0x10000);       
-    } */ 
-    /* CMD12 Error Handle */
-                       
-    return cmd->error;
-}                                   
-
-static unsigned int msdc_do_command(struct msdc_host   *host, 
-                                      struct mmc_command *cmd,
-                                      int                 tune,
-                                      unsigned long       timeout)
-{
-    if (msdc_command_start(host, cmd, tune, timeout)) 
-        goto end;      
-
-    if (msdc_command_resp(host, cmd, tune, timeout)) 
-        goto end;          
-                   
-end:   
-
-    N_MSG(CMD, "        return<%d> resp<0x%.8x>", cmd->error, cmd->resp[0]);   
-    return cmd->error;
-}
-    
-/* The abort condition when PIO read/write 
-   tmo: 
-*/
-static int msdc_pio_abort(struct msdc_host *host, struct mmc_data *data, unsigned long tmo)
-{
-    int  ret = 0;      
-    u32  base = host->base;
-    
-    if (atomic_read(&host->abort)) {   
-        ret = 1;
-    }    
-
-    if (time_after(jiffies, tmo)) {
-        data->error = (unsigned int)-ETIMEDOUT;
-        ERR_MSG("XXX PIO Data Timeout: CMD<%d>", host->mrq->cmd->opcode);
-        ret = 1;               
-    }      
-    
-    if(ret) {
-        msdc_reset();
-        msdc_clr_fifo();        
-        msdc_clr_int();        
-        ERR_MSG("msdc pio find abort");      
-    }
-    return ret; 
-}
-
-/*
-   Need to add a timeout, or WDT timeout, system reboot.      
-*/
-// pio mode data read/write
-static int msdc_pio_read(struct msdc_host *host, struct mmc_data *data)
-{
-    struct scatterlist *sg = data->sg;
-    u32  base = host->base;
-    u32  num = data->sg_len;
-    u32 *ptr;
-    u8  *u8ptr;
-    u32  left = 0;
-    u32  count, size = 0;
-    u32  wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;     
-    unsigned long tmo = jiffies + DAT_TIMEOUT;  
-          
-    sdr_set_bits(MSDC_INTEN, wints);
-    while (num) {
-        left = sg_dma_len(sg);
-        ptr = sg_virt(sg);
-        while (left) {
-            if ((left >=  MSDC_FIFO_THD) && (msdc_rxfifocnt() >= MSDC_FIFO_THD)) {
-                count = MSDC_FIFO_THD >> 2;
-                do {
-                    *ptr++ = msdc_fifo_read32();
-                } while (--count);
-                left -= MSDC_FIFO_THD;
-            } else if ((left < MSDC_FIFO_THD) && msdc_rxfifocnt() >= left) {
-                while (left > 3) {
-                    *ptr++ = msdc_fifo_read32();
-                    left -= 4;
-                }
-                 
-                u8ptr = (u8 *)ptr; 
-                while(left) {
-                    * u8ptr++ = msdc_fifo_read8();
-                    left--;      
-                }
-            }
-            
-            if (msdc_pio_abort(host, data, tmo)) {
-                goto end;      
-            }
-        }
-        size += sg_dma_len(sg);
-        sg = sg_next(sg); num--;
-    }
-end:
-    data->bytes_xfered += size;
-    N_MSG(FIO, "        PIO Read<%d>bytes", size);
-        
-    sdr_clr_bits(MSDC_INTEN, wints);    
-    if(data->error) ERR_MSG("read pio data->error<%d> left<%d> size<%d>", data->error, left, size);
-    return data->error;
-}
-
-/* please make sure won't using PIO when size >= 512 
-   which means, memory card block read/write won't using pio
-   then don't need to handle the CMD12 when data error. 
-*/
-static int msdc_pio_write(struct msdc_host* host, struct mmc_data *data)
-{
-    u32  base = host->base;
-    struct scatterlist *sg = data->sg;
-    u32  num = data->sg_len;
-    u32 *ptr;
-    u8  *u8ptr;
-    u32  left;
-    u32  count, size = 0;
-    u32  wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;      
-    unsigned long tmo = jiffies + DAT_TIMEOUT;  
-    
-    sdr_set_bits(MSDC_INTEN, wints);    
-    while (num) {
-        left = sg_dma_len(sg);
-        ptr = sg_virt(sg);
-
-        while (left) {
-            if (left >= MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
-                count = MSDC_FIFO_SZ >> 2;
-                do {
-                    msdc_fifo_write32(*ptr); ptr++;
-                } while (--count);
-                left -= MSDC_FIFO_SZ;
-            } else if (left < MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
-                while (left > 3) {
-                    msdc_fifo_write32(*ptr); ptr++;
-                    left -= 4;
-                } 
-                
-                u8ptr = (u8*)ptr; 
-                while(left){
-                    msdc_fifo_write8(*u8ptr);  u8ptr++;
-                    left--;
-                }
-            }
-            
-            if (msdc_pio_abort(host, data, tmo)) {
-                goto end;      
-            }                   
-        }
-        size += sg_dma_len(sg);
-        sg = sg_next(sg); num--;
-    }
-end:    
-    data->bytes_xfered += size;
-    N_MSG(FIO, "        PIO Write<%d>bytes", size);
-    if(data->error) ERR_MSG("write pio data->error<%d>", data->error);
-       
-    sdr_clr_bits(MSDC_INTEN, wints);  
-    return data->error;        
-}
-
-#if 0 /* --- by chhung */
-// DMA resume / start / stop 
-static void msdc_dma_resume(struct msdc_host *host)
-{
-    u32 base = host->base;
-
-    sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1);
-
-    N_MSG(DMA, "DMA resume");
-}
-#endif /* end of --- */
-
-static void msdc_dma_start(struct msdc_host *host)
-{
-    u32 base = host->base;
-    u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ; 
-           
-    sdr_set_bits(MSDC_INTEN, wints);
-    //dsb(); /* --- by chhung */
-    sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
-
-    N_MSG(DMA, "DMA start");
-}
-
-static void msdc_dma_stop(struct msdc_host *host)
-{
-    u32 base = host->base;
-    //u32 retries=500;
-    u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ; 
-    
-    N_MSG(DMA, "DMA status: 0x%.8x",sdr_read32(MSDC_DMA_CFG));
-    //while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
-
-    sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
-    while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
-
-    //dsb(); /* --- by chhung */
-    sdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */
-
-    N_MSG(DMA, "DMA stop");
-}
-
-#if 0 /* --- by chhung */
-/* dump a gpd list */
-static void msdc_dma_dump(struct msdc_host *host, struct msdc_dma *dma)
-{
-    gpd_t *gpd = dma->gpd; 
-    bd_t   *bd = dma->bd;              
-    bd_t   *ptr; 
-    int i = 0; 
-    int p_to_v; 
-    
-    if (dma->mode != MSDC_MODE_DMA_DESC) {
-        return;        
-    }    
-
-    ERR_MSG("try to dump gpd and bd");
-
-    /* dump gpd */
-    ERR_MSG(".gpd<0x%.8x> gpd_phy<0x%.8x>", (int)gpd, (int)dma->gpd_addr);
-    ERR_MSG("...hwo   <%d>", gpd->hwo );
-    ERR_MSG("...bdp   <%d>", gpd->bdp );
-    ERR_MSG("...chksum<0x%.8x>", gpd->chksum );
-    //ERR_MSG("...intr  <0x%.8x>", gpd->intr );
-    ERR_MSG("...next  <0x%.8x>", (int)gpd->next );
-    ERR_MSG("...ptr   <0x%.8x>", (int)gpd->ptr );
-    ERR_MSG("...buflen<0x%.8x>", gpd->buflen );
-    //ERR_MSG("...extlen<0x%.8x>", gpd->extlen );
-    //ERR_MSG("...arg   <0x%.8x>", gpd->arg );
-    //ERR_MSG("...blknum<0x%.8x>", gpd->blknum );    
-    //ERR_MSG("...cmd   <0x%.8x>", gpd->cmd );      
-
-    /* dump bd */
-    ERR_MSG(".bd<0x%.8x> bd_phy<0x%.8x> gpd_ptr<0x%.8x>", (int)bd, (int)dma->bd_addr, (int)gpd->ptr);  
-    ptr = bd; 
-    p_to_v = ((u32)bd - (u32)dma->bd_addr);
-    while (1) {
-        ERR_MSG(".bd[%d]", i); i++;            
-        ERR_MSG("...eol   <%d>", ptr->eol );
-        ERR_MSG("...chksum<0x%.8x>", ptr->chksum );
-        //ERR_MSG("...blkpad<0x%.8x>", ptr->blkpad );
-        //ERR_MSG("...dwpad <0x%.8x>", ptr->dwpad );
-        ERR_MSG("...next  <0x%.8x>", (int)ptr->next );
-        ERR_MSG("...ptr   <0x%.8x>", (int)ptr->ptr );
-        ERR_MSG("...buflen<0x%.8x>", (int)ptr->buflen );
-        
-        if (ptr->eol == 1) {
-            break;     
-        }
-                            
-        /* find the next bd, virtual address of ptr->next */
-        /* don't need to enable when use malloc */
-        //BUG_ON( (ptr->next + p_to_v)!=(ptr+1) );             
-        //ERR_MSG(".next bd<0x%.8x><0x%.8x>", (ptr->next + p_to_v), (ptr+1));
-        ptr++;               
-    }    
-    
-    ERR_MSG("dump gpd and bd finished");
-}
-#endif /* end of --- */
-
-/* calc checksum */
-static u8 msdc_dma_calcs(u8 *buf, u32 len)
-{
-    u32 i, sum = 0;
-    for (i = 0; i < len; i++) {
-        sum += buf[i];
-    }
-    return 0xFF - (u8)sum;
-}
-
-/* gpd bd setup + dma registers */
-static int msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma)
-{
-    u32 base = host->base;
-    u32 sglen = dma->sglen;
-    //u32 i, j, num, bdlen, arg, xfersz;
-    u32 j, num, bdlen;
-    u8  blkpad, dwpad, chksum;
-    struct scatterlist *sg = dma->sg;
-    gpd_t *gpd;
-    bd_t *bd;
-
-    switch (dma->mode) {
-    case MSDC_MODE_DMA_BASIC:
-        BUG_ON(dma->xfersz > 65535);
-        BUG_ON(dma->sglen != 1);
-        sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg)));
-        sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
-//#if defined (CONFIG_RALINK_MT7620)
-       if (ralink_soc == MT762X_SOC_MT7620A)
-               sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg));
-//#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
-        else
-               sdr_write32((volatile u32*)(RALINK_MSDC_BASE+0xa8), sg_dma_len(sg));
-//#endif
-        sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
-        sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
-        break;
-    case MSDC_MODE_DMA_DESC:
-        blkpad = (dma->flags & DMA_FLAG_PAD_BLOCK) ? 1 : 0;
-        dwpad  = (dma->flags & DMA_FLAG_PAD_DWORD) ? 1 : 0;
-        chksum = (dma->flags & DMA_FLAG_EN_CHKSUM) ? 1 : 0;
-
-        /* calculate the required number of gpd */
-        num = (sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;        
-        BUG_ON(num !=1 );        
-        
-        gpd = dma->gpd; 
-        bd  = dma->bd; 
-        bdlen = sglen; 
-
-        /* modify gpd*/
-        //gpd->intr = 0; 
-        gpd->hwo = 1;  /* hw will clear it */
-        gpd->bdp = 1;     
-        gpd->chksum = 0;  /* need to clear first. */   
-        gpd->chksum = (chksum ? msdc_dma_calcs((u8 *)gpd, 16) : 0);
-        
-        /* modify bd*/          
-        for (j = 0; j < bdlen; j++) {
-            msdc_init_bd(&bd[j], blkpad, dwpad, sg_dma_address(sg), sg_dma_len(sg));            
-            if(j == bdlen - 1) {
-            bd[j].eol = 1;             /* the last bd */
-            } else {
-                bd[j].eol = 0;         
-            }
-            bd[j].chksum = 0; /* checksume need to clear first */
-            bd[j].chksum = (chksum ? msdc_dma_calcs((u8 *)(&bd[j]), 16) : 0);         
-            sg++;
-        }
-                
-        dma->used_gpd += 2;
-        dma->used_bd += bdlen;  
-
-        sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, chksum);
-        sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
-        sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
-
-        sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr));               
-        break;
-
-    default:
-        break;
-    }
-    
-    N_MSG(DMA, "DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
-    N_MSG(DMA, "DMA_CFG  = 0x%x", sdr_read32(MSDC_DMA_CFG));
-    N_MSG(DMA, "DMA_SA   = 0x%x", sdr_read32(MSDC_DMA_SA));
-
-    return 0;
-} 
-
-static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 
-    struct scatterlist *sg, unsigned int sglen)
-{ 
-    BUG_ON(sglen > MAX_BD_NUM); /* not support currently */
-
-    dma->sg = sg;
-    dma->flags = DMA_FLAG_EN_CHKSUM;
-    //dma->flags = DMA_FLAG_NONE; /* CHECKME */
-    dma->sglen = sglen;
-    dma->xfersz = host->xfer_size;
-    dma->burstsz = MSDC_BRUST_64B;
-    
-    if (sglen == 1 && sg_dma_len(sg) <= MAX_DMA_CNT)
-        dma->mode = MSDC_MODE_DMA_BASIC;
-    else
-        dma->mode = MSDC_MODE_DMA_DESC;
-
-    N_MSG(DMA, "DMA mode<%d> sglen<%d> xfersz<%d>", dma->mode, dma->sglen, dma->xfersz);
-
-    msdc_dma_config(host, dma);
-    
-    /*if (dma->mode == MSDC_MODE_DMA_DESC) {
-        //msdc_dma_dump(host, dma);
-    } */
-}
-
-/* set block number before send command */
-static void msdc_set_blknum(struct msdc_host *host, u32 blknum)
-{
-    u32 base = host->base;
-
-    sdr_write32(SDC_BLK_NUM, blknum);
-}
-
-static int msdc_do_request(struct mmc_host*mmc, struct mmc_request*mrq)
-{
-    struct msdc_host *host = mmc_priv(mmc);
-    struct mmc_command *cmd;
-    struct mmc_data *data;
-    u32 base = host->base;
-    //u32 intsts = 0;     
-         unsigned int left=0;
-    int dma = 0, read = 1, dir = DMA_FROM_DEVICE, send_type=0;
-    
-    #define SND_DAT 0
-    #define SND_CMD 1
-
-    BUG_ON(mmc == NULL);
-    BUG_ON(mrq == NULL);    
-
-    host->error = 0;
-    atomic_set(&host->abort, 0);
-    
-    cmd  = mrq->cmd;
-    data = mrq->cmd->data;
-   
-#if 0 /* --- by chhung */
-    //if(host->id ==1){
-    N_MSG(OPS, "enable clock!");
-    msdc_ungate_clock(host->id);       
-               //}
-#endif /* end of --- */
-               
-    if (!data) {
-        send_type=SND_CMD;     
-        if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) {
-            goto done;         
-        }
-    } else {
-        BUG_ON(data->blksz > HOST_MAX_BLKSZ);
-        send_type=SND_DAT;
-
-        data->error = 0;
-        read = data->flags & MMC_DATA_READ ? 1 : 0;
-        host->data = data;
-        host->xfer_size = data->blocks * data->blksz;
-        host->blksz = data->blksz;
-
-        /* deside the transfer mode */
-        if (drv_mode[host->id] == MODE_PIO) {
-            host->dma_xfer = dma = 0;
-        } else if (drv_mode[host->id] == MODE_DMA) {
-            host->dma_xfer = dma = 1;          
-        } else if (drv_mode[host->id] == MODE_SIZE_DEP) {
-            host->dma_xfer = dma = ((host->xfer_size >= dma_size[host->id]) ? 1 : 0);  
-        }      
-
-        if (read) {
-            if ((host->timeout_ns != data->timeout_ns) ||
-                (host->timeout_clks != data->timeout_clks)) {
-                msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
-            }
-        }
-        
-        msdc_set_blknum(host, data->blocks);
-        //msdc_clr_fifo();  /* no need */
-
-        if (dma) {
-            msdc_dma_on();  /* enable DMA mode first!! */
-            init_completion(&host->xfer_done);
-            
-            /* start the command first*/               
-            if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0)
-                goto done;            
-
-            dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
-            (void)dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
-            msdc_dma_setup(host, &host->dma, data->sg, data->sg_len);            
-                        
-            /* then wait command done */
-            if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
-                goto done;            
-
-            /* for read, the data coming too fast, then CRC error 
-               start DMA no business with CRC. */
-            //init_completion(&host->xfer_done);           
-            msdc_dma_start(host);
-                       
-            spin_unlock(&host->lock);
-            if(!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)){
-                ERR_MSG("XXX CMD<%d> wait xfer_done<%d> timeout!!", cmd->opcode, data->blocks * data->blksz);
-                ERR_MSG("    DMA_SA   = 0x%x", sdr_read32(MSDC_DMA_SA));
-                ERR_MSG("    DMA_CA   = 0x%x", sdr_read32(MSDC_DMA_CA));        
-                ERR_MSG("    DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
-                ERR_MSG("    DMA_CFG  = 0x%x", sdr_read32(MSDC_DMA_CFG));           
-                data->error = (unsigned int)-ETIMEDOUT;
-                
-                msdc_reset();
-                msdc_clr_fifo();        
-                msdc_clr_int(); 
-            }
-            spin_lock(&host->lock);
-            msdc_dma_stop(host);             
-        } else {
-            /* Firstly: send command */
-            if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) {
-                goto done;
-            }
-                                             
-            /* Secondly: pio data phase */           
-            if (read) {
-                if (msdc_pio_read(host, data)){
-                    goto done;         
-                }
-            } else {
-                if (msdc_pio_write(host, data)) {
-                    goto done;                 
-                }
-            }
-
-            /* For write case: make sure contents in fifo flushed to device */           
-            if (!read) {               
-                while (1) {
-                    left=msdc_txfifocnt();                    
-                    if (left == 0) {
-                        break; 
-                    }  
-                    if (msdc_pio_abort(host, data, jiffies + DAT_TIMEOUT)) {
-                        break;
-                        /* Fix me: what about if data error, when stop ? how to? */
-                    }                                    
-                }
-            } else {
-                /* Fix me: read case: need to check CRC error */       
-            }
-
-            /* For write case: SDCBUSY and Xfer_Comp will assert when DAT0 not busy. 
-               For read case : SDCBUSY and Xfer_Comp will assert when last byte read out from FIFO.
-            */                             
-            
-            /* try not to wait xfer_comp interrupt. 
-               the next command will check SDC_BUSY. 
-               SDC_BUSY means xfer_comp assert 
-            */ 
-                      
-        } // PIO mode 
-        
-        /* Last: stop transfer */
-        if (data->stop){ 
-            if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0) {
-                goto done; 
-            }
-        } 
-    }
-
-done:
-    if (data != NULL) {
-        host->data = NULL;
-        host->dma_xfer = 0;    
-        if (dma != 0) {
-            msdc_dma_off();     
-            host->dma.used_bd  = 0;
-            host->dma.used_gpd = 0;
-            dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
-        }
-        host->blksz = 0;  
-                
-#if 0 // don't stop twice!
-        if(host->hw->flags & MSDC_REMOVABLE && data->error) {          
-            msdc_abort_data(host);
-            /* reset in IRQ, stop command has issued. -> No need */
-        } 
-#endif  
-
-        N_MSG(OPS, "CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>",cmd->opcode, (dma? "dma":"pio"), 
-                (read ? "read ":"write") ,data->blksz, data->blocks, data->error);                
-    }
-
-#if 0 /* --- by chhung */
-#if 1    
-    //if(host->id==1) {
-    if(send_type==SND_CMD) {
-        if(cmd->opcode == MMC_SEND_STATUS) {
-            if((cmd->resp[0] & CARD_READY_FOR_DATA) ||(CARD_CURRENT_STATE(cmd->resp[0]) != 7)){
-                N_MSG(OPS,"disable clock, CMD13 IDLE");
-                msdc_gate_clock(host->id); 
-            } 
-        } else {
-            N_MSG(OPS,"disable clock, CMD<%d>", cmd->opcode);  
-            msdc_gate_clock(host->id);         
-        }
-    } else {
-        if(read) {
-                               N_MSG(OPS,"disable clock!!! Read CMD<%d>",cmd->opcode);
-            msdc_gate_clock(host->id); 
-        }
-    }
-    //}
-#else
-    msdc_gate_clock(host->id); 
-#endif
-#endif /* end of --- */
-        
-    if (mrq->cmd->error) host->error = 0x001;
-    if (mrq->data && mrq->data->error) host->error |= 0x010;     
-    if (mrq->stop && mrq->stop->error) host->error |= 0x100; 
-
-    //if (host->error) ERR_MSG("host->error<%d>", host->error);     
-
-    return host->error;
-}
-
-static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
-{
-    struct mmc_command cmd;    
-    struct mmc_request mrq;
-    u32 err; 
-
-    memset(&cmd, 0, sizeof(struct mmc_command));    
-    cmd.opcode = MMC_APP_CMD;    
-#if 0   /* bug: we meet mmc->card is null when ACMD6 */   
-    cmd.arg = mmc->card->rca << 16;
-#else 
-    cmd.arg = host->app_cmd_arg;     
-#endif    
-    cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
-
-    memset(&mrq, 0, sizeof(struct mmc_request));
-    mrq.cmd = &cmd; cmd.mrq = &mrq;
-    cmd.data = NULL;        
-
-    err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);     
-    return err;        
-}
-
-static int msdc_tune_cmdrsp(struct msdc_host*host, struct mmc_command *cmd)
-{
-    int result = -1;
-    u32 base = host->base;
-    u32 rsmpl, cur_rsmpl, orig_rsmpl;
-    u32 rrdly, cur_rrdly = 0xffffffff, orig_rrdly;
-    u32 skip = 1;
-    
-    /* ==== don't support 3.0 now ====
-           1: R_SMPL[1] 
-           2: PAD_CMD_RESP_RXDLY[26:22] 
-           ==========================*/
-
-    // save the previous tune result 
-    sdr_get_field(MSDC_IOCON,    MSDC_IOCON_RSPL,        orig_rsmpl);
-    sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, orig_rrdly);
-
-    rrdly = 0; 
-    do {
-        for (rsmpl = 0; rsmpl < 2; rsmpl++) {
-            /* Lv1: R_SMPL[1] */       
-            cur_rsmpl = (orig_rsmpl + rsmpl) % 2;         
-            if (skip == 1) {
-                skip = 0;      
-                continue;      
-            }
-            sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl); 
-
-            if (host->app_cmd) {
-                result = msdc_app_cmd(host->mmc, host);        
-                if (result) {
-                    ERR_MSG("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>", 
-                         host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);
-                    continue;
-                } 
-            }          
-            result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.             
-            ERR_MSG("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>", cmd->opcode,
-                       (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl);
-                               
-            if (result == 0) {
-                return 0;      
-            }                          
-            if (result != (unsigned int)(-EIO)) { 
-                ERR_MSG("TUNE_CMD<%d> Error<%d> not -EIO", cmd->opcode, result);       
-                return result;  
-            }
-
-            /* should be EIO */
-            if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */ 
-                msdc_abort_data(host);
-            }
-        }
-               
-        /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */                   
-        cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
-        sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);               
-    }while (++rrdly < 32);
-       
-    return result;
-}
-
-/* Support SD2.0 Only */
-static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
-{
-    struct msdc_host *host = mmc_priv(mmc);
-    u32 base = host->base;
-    u32 ddr=0; 
-    u32 dcrc=0;
-    u32 rxdly, cur_rxdly0, cur_rxdly1;
-    u32 dsmpl, cur_dsmpl,  orig_dsmpl;
-    u32 cur_dat0,  cur_dat1,  cur_dat2,  cur_dat3;
-    u32 cur_dat4,  cur_dat5,  cur_dat6,  cur_dat7;
-    u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
-    u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
-    int result = -1;
-    u32 skip = 1;
-
-    sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl);
-       
-    /* Tune Method 2. */
-    sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
-
-    rxdly = 0; 
-    do {
-        for (dsmpl = 0; dsmpl < 2; dsmpl++) {
-            cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
-            if (skip == 1) {
-                skip = 0;      
-                continue;      
-            }             
-            sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
-
-            if (host->app_cmd) {
-                result = msdc_app_cmd(host->mmc, host);        
-                if (result) {
-                    ERR_MSG("TUNE_BREAD app_cmd<%d> failed", host->mrq->cmd->opcode);  
-                    continue;
-                } 
-            } 
-            result = msdc_do_request(mmc,mrq);
-            
-            sdr_get_field(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc); /* RO */
-            if (!ddr) dcrc &= ~SDC_DCRC_STS_NEG;
-            ERR_MSG("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>",
-                        (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc,
-                        sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl);
-
-            /* Fix me: result is 0, but dcrc is still exist */
-            if (result == 0 && dcrc == 0) {
-                goto done;
-            } else {
-                /* there is a case: command timeout, and data phase not processed */
-                if (mrq->data->error != 0 && mrq->data->error != (unsigned int)(-EIO)) {
-                    ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>", 
-                               result, mrq->cmd->error, mrq->data->error);     
-                    goto done;         
-                }
-            }
-        }    
-
-        cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
-        cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1);
-
-        /* E1 ECO. YD: Reverse */
-        if (sdr_read32(MSDC_ECO_VER) >= 4) {
-            orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
-            orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
-            orig_dat2 = (cur_rxdly0 >>  8) & 0x1F;
-            orig_dat3 = (cur_rxdly0 >>  0) & 0x1F;
-            orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
-            orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
-            orig_dat6 = (cur_rxdly1 >>  8) & 0x1F;
-            orig_dat7 = (cur_rxdly1 >>  0) & 0x1F;
-        } else {   
-            orig_dat0 = (cur_rxdly0 >>  0) & 0x1F;
-            orig_dat1 = (cur_rxdly0 >>  8) & 0x1F;
-            orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
-            orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
-            orig_dat4 = (cur_rxdly1 >>  0) & 0x1F;
-            orig_dat5 = (cur_rxdly1 >>  8) & 0x1F;
-            orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
-            orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
-        }
-                
-        if (ddr) {
-            cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8))  ? ((orig_dat0 + 1) % 32) : orig_dat0;
-            cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9))  ? ((orig_dat1 + 1) % 32) : orig_dat1;
-            cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
-            cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
-        } else {
-            cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
-            cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
-            cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
-            cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
-        }
-        cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
-        cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
-        cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
-        cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
-
-        cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
-        cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
-
-        sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
-        sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1);
-
-    } while (++rxdly < 32);   
-          
-done:
-    return result;
-}
-
-static int msdc_tune_bwrite(struct mmc_host *mmc,struct mmc_request *mrq)
-{
-         struct msdc_host *host = mmc_priv(mmc);
-    u32 base = host->base;
-
-    u32 wrrdly, cur_wrrdly = 0xffffffff, orig_wrrdly;
-    u32 dsmpl,  cur_dsmpl,  orig_dsmpl;
-    u32 rxdly,  cur_rxdly0;
-    u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
-    u32 cur_dat0,  cur_dat1,  cur_dat2,  cur_dat3;
-    int result = -1;
-    u32 skip = 1;
-
-    // MSDC_IOCON_DDR50CKD need to check. [Fix me] 
-    
-    sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, orig_wrrdly);
-    sdr_get_field(MSDC_IOCON,    MSDC_IOCON_DSPL,        orig_dsmpl );
-
-    /* Tune Method 2. just DAT0 */  
-    sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
-    cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
-    
-    /* E1 ECO. YD: Reverse */
-    if (sdr_read32(MSDC_ECO_VER) >= 4) {
-        orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
-        orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
-        orig_dat2 = (cur_rxdly0 >>  8) & 0x1F;
-        orig_dat3 = (cur_rxdly0 >>  0) & 0x1F;
-    } else {
-        orig_dat0 = (cur_rxdly0 >>  0) & 0x1F;
-        orig_dat1 = (cur_rxdly0 >>  8) & 0x1F;
-        orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
-        orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
-    }
-
-    rxdly = 0;
-    do {
-        wrrdly = 0;
-        do {    
-            for (dsmpl = 0; dsmpl < 2; dsmpl++) {
-                cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
-                if (skip == 1) {
-                    skip = 0;
-                    continue;  
-                }    
-                sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
-                
-                if (host->app_cmd) {
-                    result = msdc_app_cmd(host->mmc, host);    
-                    if (result) {
-                        ERR_MSG("TUNE_BWRITE app_cmd<%d> failed", host->mrq->cmd->opcode);     
-                        continue;
-                    } 
-                }             
-                result = msdc_do_request(mmc,mrq);
-            
-                ERR_MSG("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>", 
-                          result == 0 ? "PASS" : "FAIL", 
-                          cur_dsmpl, cur_wrrdly, cur_rxdly0);
-            
-                if (result == 0) {
-                    goto done;
-                }
-                else {
-                    /* there is a case: command timeout, and data phase not processed */
-                    if (mrq->data->error != (unsigned int)(-EIO)) {
-                        ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>", 
-                                   result, mrq->cmd->error, mrq->data->error); 
-                        goto done;             
-                    }
-                }       
-            }
-            cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
-            sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);             
-        } while (++wrrdly < 32); 
-        
-        cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */
-        cur_dat1 = orig_dat1;
-        cur_dat2 = orig_dat2;
-        cur_dat3 = orig_dat3;                    
-    
-        cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);       
-        sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);    
-    } while (++rxdly < 32); 
-
-done:
-    return result;
-}
-
-static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
-{
-    struct mmc_command cmd;    
-    struct mmc_request mrq;
-    u32 err; 
-
-    memset(&cmd, 0, sizeof(struct mmc_command));    
-    cmd.opcode = MMC_SEND_STATUS;    
-    if (mmc->card) {
-        cmd.arg = mmc->card->rca << 16;
-    } else {
-        ERR_MSG("cmd13 mmc card is null");             
-        cmd.arg = host->app_cmd_arg;           
-    }
-    cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
-
-    memset(&mrq, 0, sizeof(struct mmc_request));
-    mrq.cmd = &cmd; cmd.mrq = &mrq;
-    cmd.data = NULL;        
-
-    err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);        
-    
-    if (status) {
-        *status = cmd.resp[0];
-    }    
-    
-    return err;                        
-}
-
-static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
-{
-    u32 err = 0; 
-    u32 status = 0;
-    
-    do {
-        err = msdc_get_card_status(mmc, host, &status);
-        if (err) return err;
-        /* need cmd12? */       
-        ERR_MSG("cmd<13> resp<0x%x>", status);
-    } while (R1_CURRENT_STATE(status) == 7);   
-    
-    return err;        
-}
-
-/* failed when msdc_do_request */
-static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
-{
-    struct msdc_host *host = mmc_priv(mmc);
-    struct mmc_command *cmd;
-    struct mmc_data *data;
-    //u32 base = host->base;
-         int ret=0, read; 
-         
-    cmd  = mrq->cmd;
-    data = mrq->cmd->data;
-    
-    read = data->flags & MMC_DATA_READ ? 1 : 0;
-
-    if (read) {
-        if (data->error == (unsigned int)(-EIO)) {             
-            ret = msdc_tune_bread(mmc,mrq);            
-        }
-    } else {
-        ret = msdc_check_busy(mmc, host);      
-        if (ret){
-            ERR_MSG("XXX cmd13 wait program done failed");
-            return ret;
-        }
-        /* CRC and TO */       
-        /* Fix me: don't care card status? */
-        ret = msdc_tune_bwrite(mmc,mrq);       
-    }
-
-    return ret;
-}
-
-/* ops.request */
-static void msdc_ops_request(struct mmc_host *mmc,struct mmc_request *mrq)
-{   
-    struct msdc_host *host = mmc_priv(mmc);
-
-    //=== for sdio profile ===
-#if 0 /* --- by chhung */
-    u32 old_H32, old_L32, new_H32, new_L32;
-    u32 ticks = 0, opcode = 0, sizes = 0, bRx = 0; 
-#endif /* end of --- */
-      
-    if(host->mrq){
-        ERR_MSG("XXX host->mrq<0x%.8x>", (int)host->mrq);   
-        BUG(); 
-    }           
-      
-    if (!is_card_present(host) || host->power_mode == MMC_POWER_OFF) {
-        ERR_MSG("cmd<%d> card<%d> power<%d>", mrq->cmd->opcode, is_card_present(host), host->power_mode);
-        mrq->cmd->error = (unsigned int)-ENOMEDIUM; 
-        
-#if 1        
-        mrq->done(mrq);         // call done directly.
-#else
-        mrq->cmd->retries = 0;  // please don't retry.
-        mmc_request_done(mmc, mrq);
-#endif
-
-        return;
-    }
-    
-    /* start to process */
-    spin_lock(&host->lock); 
-#if 0 /* --- by chhung */
-    if (sdio_pro_enable) {  //=== for sdio profile ===  
-        if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {    
-            GPT_GetCounter64(&old_L32, &old_H32); 
-        }
-    }
-#endif /* end of --- */
-    
-    host->mrq = mrq;    
-
-    if (msdc_do_request(mmc,mrq)) {    
-        if(host->hw->flags & MSDC_REMOVABLE && ralink_soc == MT762X_SOC_MT7621AT && mrq->data && mrq->data->error) {
-            msdc_tune_request(mmc,mrq);                                        
-        }              
-    }
-
-    /* ==== when request done, check if app_cmd ==== */
-    if (mrq->cmd->opcode == MMC_APP_CMD) {
-        host->app_cmd = 1;       
-        host->app_cmd_arg = mrq->cmd->arg;  /* save the RCA */
-    } else {
-        host->app_cmd = 0;      
-        //host->app_cmd_arg = 0;       
-    }
-        
-    host->mrq = NULL; 
-
-#if 0 /* --- by chhung */
-    //=== for sdio profile ===
-    if (sdio_pro_enable) {  
-        if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {     
-            GPT_GetCounter64(&new_L32, &new_H32);
-            ticks = msdc_time_calc(old_L32, old_H32, new_L32, new_H32);
-            
-            opcode = mrq->cmd->opcode;    
-            if (mrq->cmd->data) {
-                sizes = mrq->cmd->data->blocks * mrq->cmd->data->blksz;        
-                bRx = mrq->cmd->data->flags & MMC_DATA_READ ? 1 : 0 ;
-            } else {
-                bRx = mrq->cmd->arg    & 0x80000000 ? 1 : 0;  
-            }
-            
-            if (!mrq->cmd->error) {
-                msdc_performance(opcode, sizes, bRx, ticks);
-            }
-        }    
-    } 
-#endif /* end of --- */
-    spin_unlock(&host->lock);
-        
-    mmc_request_done(mmc, mrq);
-     
-   return;
-}
-
-/* called by ops.set_ios */
-static void msdc_set_buswidth(struct msdc_host *host, u32 width)
-{
-    u32 base = host->base;
-    u32 val = sdr_read32(SDC_CFG);
-    
-    val &= ~SDC_CFG_BUSWIDTH;
-    
-    switch (width) {
-    default:
-    case MMC_BUS_WIDTH_1:
-        width = 1;
-        val |= (MSDC_BUS_1BITS << 16);
-        break;
-    case MMC_BUS_WIDTH_4:
-        val |= (MSDC_BUS_4BITS << 16);
-        break;
-    case MMC_BUS_WIDTH_8:
-        val |= (MSDC_BUS_8BITS << 16);
-        break;
-    }
-    
-    sdr_write32(SDC_CFG, val);
-
-    N_MSG(CFG, "Bus Width = %d", width);
-}
-
-/* ops.set_ios */
-static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
-{
-    struct msdc_host *host = mmc_priv(mmc);
-    struct msdc_hw *hw=host->hw;
-    u32 base = host->base;
-    u32 ddr = 0;
-
-#ifdef MT6575_SD_DEBUG
-    static char *vdd[] = {
-        "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
-        "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
-        "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
-        "3.40v", "3.50v", "3.60v"              
-    };
-    static char *power_mode[] = {
-        "OFF", "UP", "ON"
-    };
-    static char *bus_mode[] = {
-        "UNKNOWN", "OPENDRAIN", "PUSHPULL"
-    };
-    static char *timing[] = {
-        "LEGACY", "MMC_HS", "SD_HS"
-    };
-
-    printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)",
-        ios->clock / 1000, bus_mode[ios->bus_mode],
-        (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
-        power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);
-#endif
-
-    msdc_set_buswidth(host, ios->bus_width);
-    
-    /* Power control ??? */
-    switch (ios->power_mode) {
-    case MMC_POWER_OFF:
-    case MMC_POWER_UP:
-    // msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */
-        break;
-    case MMC_POWER_ON:
-        host->power_mode = MMC_POWER_ON;
-        break;
-    default:
-        break;
-    }
-
-    /* Clock control */
-    if (host->mclk != ios->clock) {
-        if(ios->clock > 25000000) {    
-            //if (!(host->hw->flags & MSDC_REMOVABLE)) {               
-            INIT_MSG("SD data latch edge<%d>", hw->data_edge);            
-            sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, hw->cmd_edge);
-            sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, hw->data_edge);
-            //} /* for tuning debug */
-        } else { /* default value */
-            sdr_write32(MSDC_IOCON,      0x00000000);
-            // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
-            sdr_write32(MSDC_DAT_RDDLY0, 0x10101010);          // for MT7620 E2 and afterward
-            sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);            
-            // sdr_write32(MSDC_PAD_TUNE,   0x00000000);
-            sdr_write32(MSDC_PAD_TUNE,   0x84101010);          // for MT7620 E2 and afterward
-        }
-        msdc_set_mclk(host, ddr, ios->clock);
-    }
-}
-
-/* ops.get_ro */
-static int msdc_ops_get_ro(struct mmc_host *mmc)
-{
-    struct msdc_host *host = mmc_priv(mmc);
-    u32 base = host->base;
-    unsigned long flags;
-    int ro = 0;
-
-    if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */
-        spin_lock_irqsave(&host->lock, flags);
-        ro = (sdr_read32(MSDC_PS) >> 31);
-        spin_unlock_irqrestore(&host->lock, flags);
-    }
-    return ro;
-}
-
-/* ops.get_cd */
-static int msdc_ops_get_cd(struct mmc_host *mmc)
-{
-    struct msdc_host *host = mmc_priv(mmc);
-    u32 base = host->base;    
-    unsigned long flags;
-    int present = 1;
-
-    /* for sdio, MSDC_REMOVABLE not set, always return 1 */
-    if (!(host->hw->flags & MSDC_REMOVABLE)) {
-        /* For sdio, read H/W always get<1>, but may timeout some times */                     
-#if 1
-        host->card_inserted = 1;       
-        return 1;
-#else
-        host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0; 
-        INIT_MSG("sdio ops_get_cd<%d>", host->card_inserted);
-        return host->card_inserted; 
-#endif
-    }
-
-    /* MSDC_CD_PIN_EN set for card */
-    if (host->hw->flags & MSDC_CD_PIN_EN) {
-        spin_lock_irqsave(&host->lock, flags);
-#if 0        
-        present = host->card_inserted;  /* why not read from H/W: Fix me*/
-#else
-        // CD
-       if (cd_active_low)
-               present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1; 
-        else
-               present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 1 : 0; 
-   if (host->mmc->caps & MMC_CAP_NEEDS_POLL)
-       present = 1;
-        host->card_inserted = present;  
-#endif        
-        spin_unlock_irqrestore(&host->lock, flags);
-    } else {
-        present = 0; /* TODO? Check DAT3 pins for card detection */
-    }
-
-    INIT_MSG("ops_get_cd return<%d>", present);
-    return present;
-}
-
-/* ops.enable_sdio_irq */
-static void msdc_ops_enable_sdio_irq(struct mmc_host *mmc, int enable)
-{
-    struct msdc_host *host = mmc_priv(mmc);
-    struct msdc_hw *hw = host->hw;
-    u32 base = host->base;
-    u32 tmp;
-
-    if (hw->flags & MSDC_EXT_SDIO_IRQ) { /* yes for sdio */
-        if (enable) {
-            hw->enable_sdio_eirq();  /* combo_sdio_enable_eirq */
-        } else {
-            hw->disable_sdio_eirq(); /* combo_sdio_disable_eirq */
-        }
-    } else { 
-         ERR_MSG("XXX ");  /* so never enter here */
-        tmp = sdr_read32(SDC_CFG);
-        /* FIXME. Need to interrupt gap detection */
-        if (enable) {
-            tmp |= (SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);           
-        } else {
-            tmp &= ~(SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
-        }
-        sdr_write32(SDC_CFG, tmp);      
-    }
-}
-
-static struct mmc_host_ops mt_msdc_ops = {
-    .request         = msdc_ops_request,
-    .set_ios         = msdc_ops_set_ios,
-    .get_ro          = msdc_ops_get_ro,
-    .get_cd          = msdc_ops_get_cd,
-    .enable_sdio_irq = msdc_ops_enable_sdio_irq,
-};
-
-/*--------------------------------------------------------------------------*/
-/* interrupt handler                                                    */
-/*--------------------------------------------------------------------------*/
-static irqreturn_t msdc_irq(int irq, void *dev_id)
-{
-    struct msdc_host  *host = (struct msdc_host *)dev_id;
-    struct mmc_data   *data = host->data;
-    struct mmc_command *cmd = host->cmd;
-    u32 base = host->base;
-        
-    u32 cmdsts = MSDC_INT_RSPCRCERR  | MSDC_INT_CMDTMO  | MSDC_INT_CMDRDY  |
-                 MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
-                 MSDC_INT_ACMD19_DONE;                 
-    u32 datsts = MSDC_INT_DATCRCERR  |MSDC_INT_DATTMO;
-
-    u32 intsts = sdr_read32(MSDC_INT);
-    u32 inten  = sdr_read32(MSDC_INTEN); inten &= intsts; 
-
-    sdr_write32(MSDC_INT, intsts);  /* clear interrupts */
-    /* MSG will cause fatal error */
-        
-    /* card change interrupt */
-    if (intsts & MSDC_INT_CDSC){
-       if (mtk_sw_poll)
-               return IRQ_HANDLED;
-       IRQ_MSG("MSDC_INT_CDSC irq<0x%.8x>", intsts); 
-#if 0 /* ---/+++ by chhung: fix slot mechanical bounce issue */
-        tasklet_hi_schedule(&host->card_tasklet);
-#else
-       schedule_delayed_work(&host->card_delaywork, HZ);
-#endif
-        /* tuning when plug card ? */
-    }
-    
-    /* sdio interrupt */
-    if (intsts & MSDC_INT_SDIOIRQ){
-        IRQ_MSG("XXX MSDC_INT_SDIOIRQ");  /* seems not sdio irq */
-        //mmc_signal_sdio_irq(host->mmc);
-    }
-
-    /* transfer complete interrupt */
-    if (data != NULL) {
-        if (inten & MSDC_INT_XFER_COMPL) {             
-            data->bytes_xfered = host->dma.xfersz;
-            complete(&host->xfer_done);           
-        } 
-        
-        if (intsts & datsts) {         
-            /* do basic reset, or stop command will sdc_busy */
-            msdc_reset();
-            msdc_clr_fifo();        
-            msdc_clr_int();             
-            atomic_set(&host->abort, 1);  /* For PIO mode exit */
-            
-            if (intsts & MSDC_INT_DATTMO){
-                       IRQ_MSG("XXX CMD<%d> MSDC_INT_DATTMO", host->mrq->cmd->opcode);
-                       data->error = (unsigned int)-ETIMEDOUT;
-            }
-            else if (intsts & MSDC_INT_DATCRCERR){
-                IRQ_MSG("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS));
-                data->error = (unsigned int)-EIO;
-            }
-                                    
-            //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {  
-            if (host->dma_xfer) {
-                complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */
-            } /* PIO mode can't do complete, because not init */
-        }
-    }
-
-    /* command interrupts */
-    if ((cmd != NULL) && (intsts & cmdsts)) {
-        if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) || 
-            (intsts & MSDC_INT_ACMD19_DONE)) {
-            u32 *rsp = &cmd->resp[0];
-            
-            switch (host->cmd_rsp) {
-            case RESP_NONE:
-                break;
-            case RESP_R2:
-                *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2);
-                *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0);
-                break;
-            default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
-                if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE)) {
-                    *rsp = sdr_read32(SDC_ACMD_RESP);
-                } else {
-                    *rsp = sdr_read32(SDC_RESP0);    
-                }
-                break;
-            }
-        } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
-            if(intsts & MSDC_INT_ACMDCRCERR){
-                IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDCRCERR",cmd->opcode);
-            } 
-            else {
-                IRQ_MSG("XXX CMD<%d> MSDC_INT_RSPCRCERR",cmd->opcode);
-            }
-            cmd->error = (unsigned int)-EIO;
-        } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
-            if(intsts & MSDC_INT_ACMDTMO){
-                IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDTMO",cmd->opcode);
-            }
-            else {
-                IRQ_MSG("XXX CMD<%d> MSDC_INT_CMDTMO",cmd->opcode);
-            }
-            cmd->error = (unsigned int)-ETIMEDOUT;
-            msdc_reset();
-            msdc_clr_fifo();        
-            msdc_clr_int();            
-        }
-        complete(&host->cmd_done);
-    }
-
-    /* mmc irq interrupts */
-    if (intsts & MSDC_INT_MMCIRQ) {
-        printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS));    
-    }
-    
-#ifdef MT6575_SD_DEBUG
-    {
-        msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;
-        N_MSG(INT, "IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)", 
-            intsts,
-            int_reg->mmcirq,
-            int_reg->cdsc,
-            int_reg->atocmdrdy,
-            int_reg->atocmdtmo,
-            int_reg->atocmdcrc,
-            int_reg->atocmd19done);
-        N_MSG(INT, "IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)", 
-            intsts,
-            int_reg->sdioirq,
-            int_reg->cmdrdy,
-            int_reg->cmdtmo,
-            int_reg->rspcrc,
-            int_reg->csta);
-        N_MSG(INT, "IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)", 
-            intsts,
-            int_reg->xfercomp,
-            int_reg->dxferdone,
-            int_reg->dattmo,
-            int_reg->datcrc,
-            int_reg->dmaqempty);
-
-    }
-#endif
-    
-    return IRQ_HANDLED;
-}
-
-/*--------------------------------------------------------------------------*/
-/* platform_driver members                                                      */
-/*--------------------------------------------------------------------------*/
-/* called by msdc_drv_probe/remove */
-static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
-{
-       struct msdc_hw *hw = host->hw;
-       u32 base = host->base;
-
-       /* for sdio, not set */
-       if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
-               /* Pull down card detection pin since it is not avaiable */
-               /*
-                  if (hw->config_gpio_pin) 
-                  hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
-                  */
-               sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
-               sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
-               sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
-               return;
-       }
-
-       N_MSG(CFG, "CD IRQ Eanable(%d)", enable);
-
-       if (enable) {
-           if (hw->enable_cd_eirq) { /* not set, never enter */
-                   hw->enable_cd_eirq();
-           } else {
-                   /* card detection circuit relies on the core power so that the core power 
-                    * shouldn't be turned off. Here adds a reference count to keep 
-                    * the core power alive.
-                    */
-                   //msdc_vcore_on(host); //did in msdc_init_hw()
-
-                   if (hw->config_gpio_pin) /* NULL */
-                           hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
-
-                   sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE);
-                   sdr_set_bits(MSDC_PS, MSDC_PS_CDEN);
-                   sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
-                   sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP);  /* not in document! Fix me */
-           }
-    } else {
-           if (hw->disable_cd_eirq) {
-                   hw->disable_cd_eirq();
-           } else {
-                   if (hw->config_gpio_pin) /* NULL */
-                           hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
-
-                   sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
-                   sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
-                   sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
-
-                   /* Here decreases a reference count to core power since card 
-                    * detection circuit is shutdown.
-                    */
-                   //msdc_vcore_off(host);
-           }
-    }
-}
-
-/* called by msdc_drv_probe */
-static void msdc_init_hw(struct msdc_host *host)
-{
-    u32 base = host->base;
-    struct msdc_hw *hw = host->hw;
-
-    /* Power on */
-#if 0 /* --- by chhung */
-    msdc_vcore_on(host);
-    msdc_pin_reset(host, MSDC_PIN_PULL_UP);
-    msdc_select_clksrc(host, hw->clk_src);
-    enable_clock(PERI_MSDC0_PDN + host->id, "SD");
-    msdc_vdd_on(host);
-#endif /* end of --- */
-    /* Configure to MMC/SD mode */
-    sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC); 
-       
-    /* Reset */
-    msdc_reset();
-    msdc_clr_fifo();
-
-    /* Disable card detection */
-    sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
-
-    /* Disable and clear all interrupts */
-    sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
-    sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
-    
-#if 1
-       /* reset tuning parameter */
-    sdr_write32(MSDC_PAD_CTL0,   0x00090000);
-    sdr_write32(MSDC_PAD_CTL1,   0x000A0000);
-    sdr_write32(MSDC_PAD_CTL2,   0x000A0000);
-    // sdr_write32(MSDC_PAD_TUNE,   0x00000000);
-    sdr_write32(MSDC_PAD_TUNE,   0x84101010);          // for MT7620 E2 and afterward
-    // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
-    sdr_write32(MSDC_DAT_RDDLY0, 0x10101010);          // for MT7620 E2 and afterward
-    sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
-    sdr_write32(MSDC_IOCON,      0x00000000);
-#if 0 // use MT7620 default value: 0x403c004f
-    sdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/
-#endif
-
-    if (sdr_read32(MSDC_ECO_VER) >= 4) { 
-        if (host->id == 1) {   
-            sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1); 
-            sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP,    1);
-            
-            /* internal clock: latch read data */  
-            sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK);  
-        }              
-    }   
-#endif    
-
-    /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in 
-       pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
-       set when kernel driver wants to use SDIO bus interrupt */
-    /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
-    sdr_set_bits(SDC_CFG, SDC_CFG_SDIO);
-
-    /* disable detect SDIO device interupt function */
-    sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE);
-
-    /* eneable SMT for glitch filter */
-    sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
-    sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
-    sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
-
-#if 1
-    /* set clk, cmd, dat pad driving */
-    sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, hw->clk_drv);
-    sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, hw->clk_drv);
-    sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, hw->cmd_drv);
-    sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, hw->cmd_drv);
-    sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, hw->dat_drv);
-    sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, hw->dat_drv);
-#else 
-    sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
-    sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
-    sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
-    sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
-    sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
-    sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
-#endif
-
-    /* set sampling edge */
-
-    /* write crc timeout detection */
-    sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1);
-
-    /* Configure to default data timeout */
-    sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
-
-    msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
-
-    N_MSG(FUC, "init hardware done!");
-}
-
-/* called by msdc_drv_remove */
-static void msdc_deinit_hw(struct msdc_host *host)
-{
-    u32 base = host->base;
-
-    /* Disable and clear all interrupts */
-    sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
-    sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
-
-    /* Disable card detection */
-    msdc_enable_cd_irq(host, 0);
-    // msdc_set_power_mode(host, MMC_POWER_OFF);   /* make sure power down */ /* --- by chhung */
-}
-
-/* init gpd and bd list in msdc_drv_probe */
-static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
-{
-    gpd_t *gpd = dma->gpd; 
-    bd_t  *bd  = dma->bd;      
-    bd_t  *ptr, *prev;
-    
-    /* we just support one gpd */     
-    int bdlen = MAX_BD_PER_GPD;        
-
-    /* init the 2 gpd */
-    memset(gpd, 0, sizeof(gpd_t) * 2);
-    //gpd->next = (void *)virt_to_phys(gpd + 1); /* pointer to a null gpd, bug! kmalloc <-> virt_to_phys */  
-    //gpd->next = (dma->gpd_addr + 1);    /* bug */
-    gpd->next = (void *)((u32)dma->gpd_addr + sizeof(gpd_t));    
-
-    //gpd->intr = 0;
-    gpd->bdp  = 1;   /* hwo, cs, bd pointer */      
-    //gpd->ptr  = (void*)virt_to_phys(bd); 
-    gpd->ptr = (void *)dma->bd_addr; /* physical address */
-    
-    memset(bd, 0, sizeof(bd_t) * bdlen);
-    ptr = bd + bdlen - 1;
-    //ptr->eol  = 1;  /* 0 or 1 [Fix me]*/
-    //ptr->next = 0;    
-    
-    while (ptr != bd) {
-        prev = ptr - 1;
-        prev->next = (void *)(dma->bd_addr + sizeof(bd_t) *(ptr - bd));
-        ptr = prev;
-    }
-}
-
-static int msdc_drv_probe(struct platform_device *pdev)
-{
-    struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-    __iomem void *base;
-    struct mmc_host *mmc;
-    struct resource *mem;
-    struct msdc_host *host;
-    struct msdc_hw *hw;
-    int ret, irq;
-    pdev->dev.platform_data = &msdc0_hw;
-   if (of_property_read_bool(pdev->dev.of_node, "mtk,wp-en"))
-       msdc0_hw.flags |= MSDC_WP_PIN_EN;
-  
-    /* Allocate MMC host for this device */
-    mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
-    if (!mmc) return -ENOMEM;
-
-    hw   = (struct msdc_hw*)pdev->dev.platform_data;
-    mem  = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-    irq  = platform_get_irq(pdev, 0);
-
-    //BUG_ON((!hw) || (!mem) || (irq < 0)); /* --- by chhung */
-    
-    base = devm_ioremap_resource(&pdev->dev, res);
-    if (IS_ERR(base))
-        return PTR_ERR(base);
-
-    /* Set host parameters to mmc */
-    mmc->ops        = &mt_msdc_ops;
-    mmc->f_min      = HOST_MIN_MCLK;
-    mmc->f_max      = HOST_MAX_MCLK;
-    mmc->ocr_avail  = MSDC_OCR_AVAIL;
-    
-    /* For sd card: MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED, 
-       For sdio   : MSDC_EXT_SDIO_IRQ | MSDC_HIGHSPEED */
-    if (hw->flags & MSDC_HIGHSPEED) {
-        mmc->caps   = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
-    }
-    if (hw->data_pins == 4) { /* current data_pins are all 4*/
-        mmc->caps  |= MMC_CAP_4_BIT_DATA;
-    } else if (hw->data_pins == 8) {
-        mmc->caps  |= MMC_CAP_8_BIT_DATA;
-    }
-    if ((hw->flags & MSDC_SDIO_IRQ) || (hw->flags & MSDC_EXT_SDIO_IRQ))
-        mmc->caps |= MMC_CAP_SDIO_IRQ;  /* yes for sdio */
-
-    cd_active_low = !of_property_read_bool(pdev->dev.of_node, "mediatek,cd-high");
-    mtk_sw_poll = of_property_read_bool(pdev->dev.of_node, "mediatek,cd-poll");
-
-    if (mtk_sw_poll)
-        mmc->caps |= MMC_CAP_NEEDS_POLL;
-
-    /* MMC core transfer sizes tunable parameters */
-#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0)
-    mmc->max_segs      = MAX_HW_SGMTS;
-#else
-    mmc->max_hw_segs   = MAX_HW_SGMTS;
-    mmc->max_phys_segs = MAX_PHY_SGMTS;
-#endif
-    mmc->max_seg_size  = MAX_SGMT_SZ;
-    mmc->max_blk_size  = HOST_MAX_BLKSZ;
-    mmc->max_req_size  = MAX_REQ_SZ; 
-    mmc->max_blk_count = mmc->max_req_size;
-
-    host = mmc_priv(mmc);
-    host->hw        = hw;
-    host->mmc       = mmc;
-    host->id        = 0;
-    host->error     = 0;
-    host->irq       = irq;    
-    host->base      = (unsigned long) base;
-    host->mclk      = 0;                   /* mclk: the request clock of mmc sub-system */
-    host->hclk      = hclks[hw->clk_src];  /* hclk: clock of clock source to msdc controller */
-    host->sclk      = 0;                   /* sclk: the really clock after divition */
-    host->pm_state  = PMSG_RESUME;
-    host->suspend   = 0;
-    host->core_clkon = 0;
-    host->card_clkon = 0;    
-    host->core_power = 0;
-    host->power_mode = MMC_POWER_OFF;
-//    host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
-    host->timeout_ns = 0;
-    host->timeout_clks = DEFAULT_DTOC * 65536;
-  
-    host->mrq = NULL; 
-    //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
-   
-    host->dma.used_gpd = 0;
-    host->dma.used_bd = 0;
-    mmc_dev(mmc)->dma_mask = NULL;
-
-    /* using dma_alloc_coherent*/  /* todo: using 1, for all 4 slots */
-    host->dma.gpd = dma_alloc_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), &host->dma.gpd_addr, GFP_KERNEL); 
-    host->dma.bd =  dma_alloc_coherent(NULL, MAX_BD_NUM  * sizeof(bd_t),  &host->dma.bd_addr,  GFP_KERNEL); 
-    BUG_ON((!host->dma.gpd) || (!host->dma.bd));    
-    msdc_init_gpd_bd(host, &host->dma);
-    
-#if 0
-    tasklet_init(&host->card_tasklet, msdc_tasklet_card, (ulong)host);
-#else
-    INIT_DELAYED_WORK(&host->card_delaywork, msdc_tasklet_card);
-#endif
-    spin_lock_init(&host->lock);
-    msdc_init_hw(host);
-
-       if (ralink_soc == MT762X_SOC_MT7621AT)
-               ret = request_irq((unsigned int)irq, msdc_irq, 0, dev_name(&pdev->dev), host);
-       else 
-               ret = request_irq((unsigned int)irq, msdc_irq, IRQF_TRIGGER_LOW, dev_name(&pdev->dev), host);
-
-    if (ret) goto release;
-    // mt65xx_irq_unmask(irq); /* --- by chhung */
-    
-    if (hw->flags & MSDC_CD_PIN_EN) { /* not set for sdio */
-        if (hw->request_cd_eirq) { /* not set for MT6575 */
-            hw->request_cd_eirq(msdc_eirq_cd, (void*)host); /* msdc_eirq_cd will not be used! */
-        }
-    }
-
-    if (hw->request_sdio_eirq) /* set to combo_sdio_request_eirq() for WIFI */
-        hw->request_sdio_eirq(msdc_eirq_sdio, (void*)host); /* msdc_eirq_sdio() will be called when EIRQ */
-
-    if (hw->register_pm) {/* yes for sdio */
-#ifdef CONFIG_PM
-        hw->register_pm(msdc_pm, (void*)host);  /* combo_sdio_register_pm() */
-#endif
-        if(hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
-            ERR_MSG("MSDC_SYS_SUSPEND and register_pm both set");
-        }
-        //mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* pm not controlled by system but by client. */ /* --- by chhung */
-    }
-    
-    platform_set_drvdata(pdev, mmc);
-
-    ret = mmc_add_host(mmc);
-    if (ret) goto free_irq;
-
-    /* Config card detection pin and enable interrupts */
-    if (hw->flags & MSDC_CD_PIN_EN) {  /* set for card */
-        msdc_enable_cd_irq(host, 1);
-    } else {
-        msdc_enable_cd_irq(host, 0);
-    }  
-
-    return 0;
-
-free_irq:
-    free_irq(irq, host);
-release:
-    platform_set_drvdata(pdev, NULL);
-    msdc_deinit_hw(host);
-
-#if 0
-    tasklet_kill(&host->card_tasklet);
-#else
-    cancel_delayed_work_sync(&host->card_delaywork);
-#endif
-
-    if (mem)
-        release_mem_region(mem->start, mem->end - mem->start + 1);
-
-    mmc_free_host(mmc);
-
-    return ret;
-}
-
-/* 4 device share one driver, using "drvdata" to show difference */
-static int msdc_drv_remove(struct platform_device *pdev)
-{
-    struct mmc_host *mmc;
-    struct msdc_host *host;
-    struct resource *mem;
-
-    mmc  = platform_get_drvdata(pdev);
-    BUG_ON(!mmc);
-    
-    host = mmc_priv(mmc);   
-    BUG_ON(!host);
-
-    ERR_MSG("removed !!!");
-
-    platform_set_drvdata(pdev, NULL);
-    mmc_remove_host(host->mmc);
-    msdc_deinit_hw(host);
-
-#if 0
-    tasklet_kill(&host->card_tasklet);
-#else
-    cancel_delayed_work_sync(&host->card_delaywork);
-#endif
-    free_irq(host->irq, host);
-
-    dma_free_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), host->dma.gpd, host->dma.gpd_addr);
-    dma_free_coherent(NULL, MAX_BD_NUM  * sizeof(bd_t),  host->dma.bd,  host->dma.bd_addr);
-
-    mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-
-    if (mem)
-        release_mem_region(mem->start, mem->end - mem->start + 1);
-
-    mmc_free_host(host->mmc);
-
-    return 0;
-}
-
-/* Fix me: Power Flow */
-#ifdef CONFIG_PM
-static int msdc_drv_suspend(struct platform_device *pdev, pm_message_t state)
-{
-    int ret = 0;
-    struct mmc_host *mmc = platform_get_drvdata(pdev);
-    struct msdc_host *host = mmc_priv(mmc);
-
-    if (mmc && state.event == PM_EVENT_SUSPEND && (host->hw->flags & MSDC_SYS_SUSPEND)) { /* will set for card */
-        msdc_pm(state, (void*)host);
-    }
-    
-    return ret;
-}
-
-static int msdc_drv_resume(struct platform_device *pdev)
-{
-    int ret = 0;
-    struct mmc_host *mmc = platform_get_drvdata(pdev);
-    struct msdc_host *host = mmc_priv(mmc);
-    struct pm_message state;
-
-    state.event = PM_EVENT_RESUME;
-    if (mmc && (host->hw->flags & MSDC_SYS_SUSPEND)) {/* will set for card */
-        msdc_pm(state, (void*)host);
-    }
-
-    /* This mean WIFI not controller by PM */
-    
-    return ret;
-}
-#endif
-
-static const struct of_device_id mt7620_sdhci_match[] = {
-       { .compatible = "ralink,mt7620-sdhci" },
-       {},
-};
-MODULE_DEVICE_TABLE(of, mt7620_sdhci_match);
-
-static struct platform_driver mt_msdc_driver = {
-    .probe   = msdc_drv_probe,
-    .remove  = msdc_drv_remove,
-#ifdef CONFIG_PM
-    .suspend = msdc_drv_suspend,
-    .resume  = msdc_drv_resume,
-#endif
-    .driver  = {
-        .name  = DRV_NAME,
-       .of_match_table = mt7620_sdhci_match,
-    },
-};
-
-/*--------------------------------------------------------------------------*/
-/* module init/exit                                                      */
-/*--------------------------------------------------------------------------*/
-static int __init mt_msdc_init(void)
-{
-    int ret;
-/* +++ by chhung */
-    u32 reg;
-
-#if defined (CONFIG_MTD_ANY_RALINK)
-    extern int ra_check_flash_type(void);
-    if(ra_check_flash_type() == 2) { /* NAND */
-           printk("%s: !!!!! SDXC Module Initialize Fail !!!!!", __func__);
-           return 0;
-    }
-#endif
-    printk("MTK MSDC device init.\n");
-    mtk_sd_device.dev.platform_data = &msdc0_hw;
-if (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7621AT) {
-//#if defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
-    reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3<<18);
-//#if defined (CONFIG_RALINK_MT7620)
-       if (ralink_soc == MT762X_SOC_MT7620A)
-               reg |= 0x1<<18;
-//#endif
-} else {
-//#elif defined (CONFIG_RALINK_MT7628)
-    /* TODO: maybe omitted when RAether already toggle AGPIO_CFG */
-    reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x3c));
-    reg |= 0x1e << 16;
-    sdr_write32((volatile u32*)(RALINK_SYSCTL_BASE + 0x3c), reg);
-
-    reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3<<10);
-#if defined (CONFIG_MTK_MMC_EMMC_8BIT)
-    reg |= 0x3<<26 | 0x3<<28 | 0x3<<30;
-    msdc0_hw.data_pins      = 8,
-#endif
-//#endif
-}
-    sdr_write32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60), reg);
-    //platform_device_register(&mtk_sd_device);
-/* end of +++ */
-
-    ret = platform_driver_register(&mt_msdc_driver);
-    if (ret) {
-        printk(KERN_ERR DRV_NAME ": Can't register driver");
-        return ret;
-    }
-    printk(KERN_INFO DRV_NAME ": MediaTek MT6575 MSDC Driver\n");
-
-#if defined (MT6575_SD_DEBUG)
-    msdc_debug_proc_init();
-#endif
-    return 0;
-}
-
-static void __exit mt_msdc_exit(void)
-{
-//    platform_device_unregister(&mtk_sd_device);
-    platform_driver_unregister(&mt_msdc_driver);
-}
-
-module_init(mt_msdc_init);
-module_exit(mt_msdc_exit);
-MODULE_LICENSE("GPL");
diff --git a/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/Kconfig b/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/Kconfig
deleted file mode 100644 (file)
index cf883c4..0000000
+++ /dev/null
@@ -1,62 +0,0 @@
-config NET_VENDOR_MEDIATEK
-       tristate "Mediatek/Ralink ethernet driver"
-       depends on RALINK
-       help
-         This driver supports the ethernet mac inside the Mediatek and Ralink WiSoCs
-
-config NET_MEDIATEK_SOC
-       def_tristate NET_VENDOR_MEDIATEK
-
-if NET_MEDIATEK_SOC
-choice
-       prompt "MAC type"
-
-config NET_MEDIATEK_RT2880
-       bool "RT2882"
-       depends on MIPS && SOC_RT288X
-
-config NET_MEDIATEK_RT3050
-       bool "RT3050/MT7628"
-       depends on MIPS && (SOC_RT305X || SOC_MT7620)
-
-config NET_MEDIATEK_RT3883
-       bool "RT3883"
-       depends on MIPS && SOC_RT3883
-
-config NET_MEDIATEK_MT7620
-       bool "MT7620"
-       depends on MIPS && SOC_MT7620
-
-config NET_MEDIATEK_MT7621
-       bool "MT7621"
-       depends on MIPS && SOC_MT7621
-
-endchoice
-
-config NET_MEDIATEK_MDIO
-       def_bool NET_MEDIATEK_SOC
-       depends on (NET_MEDIATEK_RT2880 || NET_MEDIATEK_RT3883 || NET_MEDIATEK_MT7620 || NET_MEDIATEK_MT7621)
-       select PHYLIB
-
-config NET_MEDIATEK_MDIO_RT2880
-       def_bool NET_MEDIATEK_SOC
-       depends on (NET_MEDIATEK_RT2880 || NET_MEDIATEK_RT3883)
-       select NET_MEDIATEK_MDIO
-
-config NET_MEDIATEK_MDIO_MT7620
-       def_bool NET_MEDIATEK_SOC
-       depends on (NET_MEDIATEK_MT7620 || NET_MEDIATEK_MT7621)
-       select NET_MEDIATEK_MDIO
-
-config NET_MEDIATEK_ESW_RT3050
-       def_tristate NET_MEDIATEK_SOC
-       depends on NET_MEDIATEK_RT3050
-
-config NET_MEDIATEK_GSW_MT7620
-       def_tristate NET_MEDIATEK_SOC
-       depends on NET_MEDIATEK_MT7620
-
-config NET_MEDIATEK_GSW_MT7621
-       def_tristate NET_MEDIATEK_SOC
-       depends on NET_MEDIATEK_MT7621
-endif
diff --git a/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/Makefile b/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/Makefile
deleted file mode 100644 (file)
index 07ba4c2..0000000
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# Makefile for the Ralink SoCs built-in ethernet macs
-#
-
-mtk-eth-soc-y                                  += mtk_eth_soc.o ethtool.o
-
-mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MDIO)                += mdio.o
-mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MDIO_RT2880) += mdio_rt2880.o
-mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MDIO_MT7620) += mdio_mt7620.o
-
-mtk-eth-soc-$(CONFIG_NET_MEDIATEK_RT2880)      += soc_rt2880.o
-mtk-eth-soc-$(CONFIG_NET_MEDIATEK_RT3050)      += soc_rt3050.o
-mtk-eth-soc-$(CONFIG_NET_MEDIATEK_RT3883)      += soc_rt3883.o
-mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MT7620)      += soc_mt7620.o
-mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MT7621)      += soc_mt7621.o
-
-obj-$(CONFIG_NET_MEDIATEK_ESW_RT3050)          += esw_rt3050.o
-obj-$(CONFIG_NET_MEDIATEK_GSW_MT7620)          += gsw_mt7620.o mt7530.o
-obj-$(CONFIG_NET_MEDIATEK_GSW_MT7621)          += gsw_mt7621.o mt7530.o
-obj-$(CONFIG_NET_MEDIATEK_SOC)                 += mtk-eth-soc.o
diff --git a/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/esw_rt3050.c b/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/esw_rt3050.c
deleted file mode 100644 (file)
index 6cad585..0000000
+++ /dev/null
@@ -1,1461 +0,0 @@
-/*   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; version 2 of the License
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
- *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
- *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
- *   Copyright (C) 2016 Vittorio Gambaletta <openwrt@vittgam.net>
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <asm/mach-ralink/ralink_regs.h>
-#include <linux/of_irq.h>
-
-#include <linux/switch.h>
-
-#include "mtk_eth_soc.h"
-
-/* HW limitations for this switch:
- * - No large frame support (PKT_MAX_LEN at most 1536)
- * - Can't have untagged vlan and tagged vlan on one port at the same time,
- *   though this might be possible using the undocumented PPE.
- */
-
-#define RT305X_ESW_REG_ISR             0x00
-#define RT305X_ESW_REG_IMR             0x04
-#define RT305X_ESW_REG_FCT0            0x08
-#define RT305X_ESW_REG_PFC1            0x14
-#define RT305X_ESW_REG_ATS             0x24
-#define RT305X_ESW_REG_ATS0            0x28
-#define RT305X_ESW_REG_ATS1            0x2c
-#define RT305X_ESW_REG_ATS2            0x30
-#define RT305X_ESW_REG_PVIDC(_n)       (0x40 + 4 * (_n))
-#define RT305X_ESW_REG_VLANI(_n)       (0x50 + 4 * (_n))
-#define RT305X_ESW_REG_VMSC(_n)                (0x70 + 4 * (_n))
-#define RT305X_ESW_REG_POA             0x80
-#define RT305X_ESW_REG_FPA             0x84
-#define RT305X_ESW_REG_SOCPC           0x8c
-#define RT305X_ESW_REG_POC0            0x90
-#define RT305X_ESW_REG_POC1            0x94
-#define RT305X_ESW_REG_POC2            0x98
-#define RT305X_ESW_REG_SGC             0x9c
-#define RT305X_ESW_REG_STRT            0xa0
-#define RT305X_ESW_REG_PCR0            0xc0
-#define RT305X_ESW_REG_PCR1            0xc4
-#define RT305X_ESW_REG_FPA2            0xc8
-#define RT305X_ESW_REG_FCT2            0xcc
-#define RT305X_ESW_REG_SGC2            0xe4
-#define RT305X_ESW_REG_P0LED           0xa4
-#define RT305X_ESW_REG_P1LED           0xa8
-#define RT305X_ESW_REG_P2LED           0xac
-#define RT305X_ESW_REG_P3LED           0xb0
-#define RT305X_ESW_REG_P4LED           0xb4
-#define RT305X_ESW_REG_PXPC(_x)                (0xe8 + (4 * _x))
-#define RT305X_ESW_REG_P1PC            0xec
-#define RT305X_ESW_REG_P2PC            0xf0
-#define RT305X_ESW_REG_P3PC            0xf4
-#define RT305X_ESW_REG_P4PC            0xf8
-#define RT305X_ESW_REG_P5PC            0xfc
-
-#define RT305X_ESW_LED_LINK            0
-#define RT305X_ESW_LED_100M            1
-#define RT305X_ESW_LED_DUPLEX          2
-#define RT305X_ESW_LED_ACTIVITY                3
-#define RT305X_ESW_LED_COLLISION       4
-#define RT305X_ESW_LED_LINKACT         5
-#define RT305X_ESW_LED_DUPLCOLL                6
-#define RT305X_ESW_LED_10MACT          7
-#define RT305X_ESW_LED_100MACT         8
-/* Additional led states not in datasheet: */
-#define RT305X_ESW_LED_BLINK           10
-#define RT305X_ESW_LED_ON              12
-
-#define RT305X_ESW_LINK_S              25
-#define RT305X_ESW_DUPLEX_S            9
-#define RT305X_ESW_SPD_S               0
-
-#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
-#define RT305X_ESW_PCR0_WT_PHY_CMD     BIT(13)
-#define RT305X_ESW_PCR0_CPU_PHY_REG_S  8
-
-#define RT305X_ESW_PCR1_WT_DONE                BIT(0)
-
-#define RT305X_ESW_ATS_TIMEOUT         (5 * HZ)
-#define RT305X_ESW_PHY_TIMEOUT         (5 * HZ)
-
-#define RT305X_ESW_PVIDC_PVID_M                0xfff
-#define RT305X_ESW_PVIDC_PVID_S                12
-
-#define RT305X_ESW_VLANI_VID_M         0xfff
-#define RT305X_ESW_VLANI_VID_S         12
-
-#define RT305X_ESW_VMSC_MSC_M          0xff
-#define RT305X_ESW_VMSC_MSC_S          8
-
-#define RT305X_ESW_SOCPC_DISUN2CPU_S   0
-#define RT305X_ESW_SOCPC_DISMC2CPU_S   8
-#define RT305X_ESW_SOCPC_DISBC2CPU_S   16
-#define RT305X_ESW_SOCPC_CRC_PADDING   BIT(25)
-
-#define RT305X_ESW_POC0_EN_BP_S                0
-#define RT305X_ESW_POC0_EN_FC_S                8
-#define RT305X_ESW_POC0_DIS_RMC2CPU_S  16
-#define RT305X_ESW_POC0_DIS_PORT_M     0x7f
-#define RT305X_ESW_POC0_DIS_PORT_S     23
-
-#define RT305X_ESW_POC2_UNTAG_EN_M     0xff
-#define RT305X_ESW_POC2_UNTAG_EN_S     0
-#define RT305X_ESW_POC2_ENAGING_S      8
-#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
-
-#define RT305X_ESW_SGC2_DOUBLE_TAG_M   0x7f
-#define RT305X_ESW_SGC2_DOUBLE_TAG_S   0
-#define RT305X_ESW_SGC2_LAN_PMAP_M     0x3f
-#define RT305X_ESW_SGC2_LAN_PMAP_S     24
-
-#define RT305X_ESW_PFC1_EN_VLAN_M      0xff
-#define RT305X_ESW_PFC1_EN_VLAN_S      16
-#define RT305X_ESW_PFC1_EN_TOS_S       24
-
-#define RT305X_ESW_VLAN_NONE           0xfff
-
-#define RT305X_ESW_GSC_BC_STROM_MASK   0x3
-#define RT305X_ESW_GSC_BC_STROM_SHIFT  4
-
-#define RT305X_ESW_GSC_LED_FREQ_MASK   0x3
-#define RT305X_ESW_GSC_LED_FREQ_SHIFT  23
-
-#define RT305X_ESW_POA_LINK_MASK       0x1f
-#define RT305X_ESW_POA_LINK_SHIFT      25
-
-#define RT305X_ESW_PORT_ST_CHG         BIT(26)
-#define RT305X_ESW_PORT0               0
-#define RT305X_ESW_PORT1               1
-#define RT305X_ESW_PORT2               2
-#define RT305X_ESW_PORT3               3
-#define RT305X_ESW_PORT4               4
-#define RT305X_ESW_PORT5               5
-#define RT305X_ESW_PORT6               6
-
-#define RT305X_ESW_PORTS_NONE          0
-
-#define RT305X_ESW_PMAP_LLLLLL         0x3f
-#define RT305X_ESW_PMAP_LLLLWL         0x2f
-#define RT305X_ESW_PMAP_WLLLLL         0x3e
-
-#define RT305X_ESW_PORTS_INTERNAL                                      \
-               (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |        \
-                BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |        \
-                BIT(RT305X_ESW_PORT4))
-
-#define RT305X_ESW_PORTS_NOCPU                                         \
-               (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
-
-#define RT305X_ESW_PORTS_CPU   BIT(RT305X_ESW_PORT6)
-
-#define RT305X_ESW_PORTS_ALL                                           \
-               (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
-
-#define RT305X_ESW_NUM_VLANS           16
-#define RT305X_ESW_NUM_VIDS            4096
-#define RT305X_ESW_NUM_PORTS           7
-#define RT305X_ESW_NUM_LANWAN          6
-#define RT305X_ESW_NUM_LEDS            5
-
-#define RT5350_ESW_REG_PXTPC(_x)       (0x150 + (4 * _x))
-#define RT5350_EWS_REG_LED_POLARITY    0x168
-#define RT5350_RESET_EPHY              BIT(24)
-
-enum {
-       /* Global attributes. */
-       RT305X_ESW_ATTR_ENABLE_VLAN,
-       RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
-       RT305X_ESW_ATTR_BC_STATUS,
-       RT305X_ESW_ATTR_LED_FREQ,
-       /* Port attributes. */
-       RT305X_ESW_ATTR_PORT_DISABLE,
-       RT305X_ESW_ATTR_PORT_DOUBLETAG,
-       RT305X_ESW_ATTR_PORT_UNTAG,
-       RT305X_ESW_ATTR_PORT_LED,
-       RT305X_ESW_ATTR_PORT_LAN,
-       RT305X_ESW_ATTR_PORT_RECV_BAD,
-       RT305X_ESW_ATTR_PORT_RECV_GOOD,
-       RT5350_ESW_ATTR_PORT_TR_BAD,
-       RT5350_ESW_ATTR_PORT_TR_GOOD,
-};
-
-struct esw_port {
-       bool    disable;
-       bool    doubletag;
-       bool    untag;
-       u8      led;
-       u16     pvid;
-};
-
-struct esw_vlan {
-       u8      ports;
-       u16     vid;
-};
-
-enum {
-       RT305X_ESW_VLAN_CONFIG_NONE = 0,
-       RT305X_ESW_VLAN_CONFIG_LLLLW,
-       RT305X_ESW_VLAN_CONFIG_WLLLL,
-};
-
-struct rt305x_esw {
-       struct device           *dev;
-       void __iomem            *base;
-       int                     irq;
-
-       /* Protects against concurrent register r/w operations. */
-       spinlock_t              reg_rw_lock;
-
-       unsigned char           port_map;
-       unsigned char           port_disable;
-       unsigned int            reg_initval_fct2;
-       unsigned int            reg_initval_fpa2;
-       unsigned int            reg_led_polarity;
-
-       struct switch_dev       swdev;
-       bool                    global_vlan_enable;
-       bool                    alt_vlan_disable;
-       int                     bc_storm_protect;
-       int                     led_frequency;
-       struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
-       struct esw_port ports[RT305X_ESW_NUM_PORTS];
-
-};
-
-static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
-{
-       __raw_writel(val, esw->base + reg);
-}
-
-static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
-{
-       return __raw_readl(esw->base + reg);
-}
-
-static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg,
-                              unsigned long mask, unsigned long val)
-{
-       unsigned long t;
-
-       t = __raw_readl(esw->base + reg) & ~mask;
-       __raw_writel(t | val, esw->base + reg);
-}
-
-static void esw_rmw(struct rt305x_esw *esw, unsigned reg,
-                   unsigned long mask, unsigned long val)
-{
-       unsigned long flags;
-
-       spin_lock_irqsave(&esw->reg_rw_lock, flags);
-       esw_rmw_raw(esw, reg, mask, val);
-       spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
-}
-
-static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr,
-                           u32 phy_register, u32 write_data)
-{
-       unsigned long t_start = jiffies;
-       int ret = 0;
-
-       while (1) {
-               if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
-                     RT305X_ESW_PCR1_WT_DONE))
-                       break;
-               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
-                       ret = 1;
-                       goto out;
-               }
-       }
-
-       write_data &= 0xffff;
-       esw_w32(esw, (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
-                     (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
-                     (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
-               RT305X_ESW_REG_PCR0);
-
-       t_start = jiffies;
-       while (1) {
-               if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
-                           RT305X_ESW_PCR1_WT_DONE)
-                       break;
-
-               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
-                       ret = 1;
-                       break;
-               }
-       }
-out:
-       if (ret)
-               dev_err(esw->dev, "ramips_eth: MDIO timeout\n");
-       return ret;
-}
-
-static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
-{
-       unsigned s;
-       unsigned val;
-
-       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
-       val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
-       val = (val >> s) & RT305X_ESW_VLANI_VID_M;
-
-       return val;
-}
-
-static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
-{
-       unsigned s;
-
-       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
-       esw_rmw(esw,
-                      RT305X_ESW_REG_VLANI(vlan / 2),
-                      RT305X_ESW_VLANI_VID_M << s,
-                      (vid & RT305X_ESW_VLANI_VID_M) << s);
-}
-
-static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
-{
-       unsigned s, val;
-
-       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
-       val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
-       return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
-}
-
-static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
-{
-       unsigned s;
-
-       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
-       esw_rmw(esw,
-                      RT305X_ESW_REG_PVIDC(port / 2),
-                      RT305X_ESW_PVIDC_PVID_M << s,
-                      (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
-}
-
-static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
-{
-       unsigned s, val;
-
-       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
-       val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
-       val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
-
-       return val;
-}
-
-static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
-{
-       unsigned s;
-
-       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
-       esw_rmw(esw,
-                      RT305X_ESW_REG_VMSC(vlan / 4),
-                      RT305X_ESW_VMSC_MSC_M << s,
-                      (msc & RT305X_ESW_VMSC_MSC_M) << s);
-}
-
-static unsigned esw_get_port_disable(struct rt305x_esw *esw)
-{
-       unsigned reg;
-
-       reg = esw_r32(esw, RT305X_ESW_REG_POC0);
-       return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
-              RT305X_ESW_POC0_DIS_PORT_M;
-}
-
-static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
-{
-       unsigned old_mask;
-       unsigned enable_mask;
-       unsigned changed;
-       int i;
-
-       old_mask = esw_get_port_disable(esw);
-       changed = old_mask ^ disable_mask;
-       enable_mask = old_mask & disable_mask;
-
-       /* enable before writing to MII */
-       esw_rmw(esw, RT305X_ESW_REG_POC0,
-                      (RT305X_ESW_POC0_DIS_PORT_M <<
-                       RT305X_ESW_POC0_DIS_PORT_S),
-                      enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
-
-       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
-               if (!(changed & (1 << i)))
-                       continue;
-               if (disable_mask & (1 << i)) {
-                       /* disable */
-                       rt305x_mii_write(esw, i, MII_BMCR,
-                                        BMCR_PDOWN);
-               } else {
-                       /* enable */
-                       rt305x_mii_write(esw, i, MII_BMCR,
-                                        BMCR_FULLDPLX |
-                                        BMCR_ANENABLE |
-                                        BMCR_ANRESTART |
-                                        BMCR_SPEED100);
-               }
-       }
-
-       /* disable after writing to MII */
-       esw_rmw(esw, RT305X_ESW_REG_POC0,
-                      (RT305X_ESW_POC0_DIS_PORT_M <<
-                       RT305X_ESW_POC0_DIS_PORT_S),
-                      disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
-}
-
-static void esw_set_gsc(struct rt305x_esw *esw)
-{
-       esw_rmw(esw, RT305X_ESW_REG_SGC,
-               RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
-               esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
-       esw_rmw(esw, RT305X_ESW_REG_SGC,
-               RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
-               esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
-}
-
-static int esw_apply_config(struct switch_dev *dev);
-
-static void esw_hw_init(struct rt305x_esw *esw)
-{
-       int i;
-       u8 port_disable = 0;
-       u8 port_map = RT305X_ESW_PMAP_LLLLLL;
-
-       /* vodoo from original driver */
-       esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
-       esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
-       /* Port priority 1 for all ports, vlan enabled. */
-       esw_w32(esw, 0x00005555 |
-                    (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
-               RT305X_ESW_REG_PFC1);
-
-       /* Enable all ports, Back Pressure and Flow Control */
-       esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
-                     (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
-               RT305X_ESW_REG_POC0);
-
-       /* Enable Aging, and VLAN TAG removal */
-       esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
-                     (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
-               RT305X_ESW_REG_POC2);
-
-       if (esw->reg_initval_fct2)
-               esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
-       else
-               esw_w32(esw, 0x0002500c, RT305X_ESW_REG_FCT2);
-
-       /* 300s aging timer, max packet len 1536, broadcast storm prevention
-        * disabled, disable collision abort, mac xor48 hash, 10 packet back
-        * pressure jam, GMII disable was_transmit, back pressure disabled,
-        * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
-        * ports.
-        */
-       esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
-
-       /* Setup SoC Port control register */
-       esw_w32(esw,
-               (RT305X_ESW_SOCPC_CRC_PADDING |
-               (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
-               (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
-               (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
-               RT305X_ESW_REG_SOCPC);
-
-       /* ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
-        * turbo mii off, rgmi 3.3v off
-        * port5: disabled
-        * port6: enabled, gige, full-duplex, rx/tx-flow-control
-        */
-       if (esw->reg_initval_fpa2)
-               esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
-       else
-               esw_w32(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
-       esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
-
-       /* Force Link/Activity on ports */
-       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
-       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
-       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
-       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
-       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
-
-       /* Copy disabled port configuration from device tree setup */
-       port_disable = esw->port_disable;
-
-       /* Disable nonexistent ports by reading the switch config
-        * after having enabled all possible ports above
-        */
-       port_disable |= esw_get_port_disable(esw);
-
-       for (i = 0; i < 6; i++)
-               esw->ports[i].disable = (port_disable & (1 << i)) != 0;
-
-       if (ralink_soc == RT305X_SOC_RT3352) {
-               /* reset EPHY */
-               fe_reset(RT5350_RESET_EPHY);
-
-               rt305x_mii_write(esw, 0, 31, 0x8000);
-               for (i = 0; i < 5; i++) {
-                       if (esw->ports[i].disable) {
-                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
-                       } else {
-                               rt305x_mii_write(esw, i, MII_BMCR,
-                                                BMCR_FULLDPLX |
-                                                BMCR_ANENABLE |
-                                                BMCR_SPEED100);
-                       }
-                       /* TX10 waveform coefficient LSB=0 disable PHY */
-                       rt305x_mii_write(esw, i, 26, 0x1601);
-                       /* TX100/TX10 AD/DA current bias */
-                       rt305x_mii_write(esw, i, 29, 0x7016);
-                       /* TX100 slew rate control */
-                       rt305x_mii_write(esw, i, 30, 0x0038);
-               }
-
-               /* select global register */
-               rt305x_mii_write(esw, 0, 31, 0x0);
-               /* enlarge agcsel threshold 3 and threshold 2 */
-               rt305x_mii_write(esw, 0, 1, 0x4a40);
-               /* enlarge agcsel threshold 5 and threshold 4 */
-               rt305x_mii_write(esw, 0, 2, 0x6254);
-               /* enlarge agcsel threshold  */
-               rt305x_mii_write(esw, 0, 3, 0xa17f);
-               rt305x_mii_write(esw, 0, 12, 0x7eaa);
-               /* longer TP_IDL tail length */
-               rt305x_mii_write(esw, 0, 14, 0x65);
-               /* increased squelch pulse count threshold. */
-               rt305x_mii_write(esw, 0, 16, 0x0684);
-               /* set TX10 signal amplitude threshold to minimum */
-               rt305x_mii_write(esw, 0, 17, 0x0fe0);
-               /* set squelch amplitude to higher threshold */
-               rt305x_mii_write(esw, 0, 18, 0x40ba);
-               /* tune TP_IDL tail and head waveform, enable power
-                * down slew rate control
-                */
-               rt305x_mii_write(esw, 0, 22, 0x253f);
-               /* set PLL/Receive bias current are calibrated */
-               rt305x_mii_write(esw, 0, 27, 0x2fda);
-               /* change PLL/Receive bias current to internal(RT3350) */
-               rt305x_mii_write(esw, 0, 28, 0xc410);
-               /* change PLL bias current to internal(RT3052_MP3) */
-               rt305x_mii_write(esw, 0, 29, 0x598b);
-               /* select local register */
-               rt305x_mii_write(esw, 0, 31, 0x8000);
-       } else if (ralink_soc == RT305X_SOC_RT5350) {
-               /* reset EPHY */
-               fe_reset(RT5350_RESET_EPHY);
-
-               /* set the led polarity */
-               esw_w32(esw, esw->reg_led_polarity & 0x1F,
-                       RT5350_EWS_REG_LED_POLARITY);
-
-               /* local registers */
-               rt305x_mii_write(esw, 0, 31, 0x8000);
-               for (i = 0; i < 5; i++) {
-                       if (esw->ports[i].disable) {
-                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
-                       } else {
-                               rt305x_mii_write(esw, i, MII_BMCR,
-                                                BMCR_FULLDPLX |
-                                                BMCR_ANENABLE |
-                                                BMCR_SPEED100);
-                       }
-                       /* TX10 waveform coefficient LSB=0 disable PHY */
-                       rt305x_mii_write(esw, i, 26, 0x1601);
-                       /* TX100/TX10 AD/DA current bias */
-                       rt305x_mii_write(esw, i, 29, 0x7015);
-                       /* TX100 slew rate control */
-                       rt305x_mii_write(esw, i, 30, 0x0038);
-               }
-
-               /* global registers */
-               rt305x_mii_write(esw, 0, 31, 0x0);
-               /* enlarge agcsel threshold 3 and threshold 2 */
-               rt305x_mii_write(esw, 0, 1, 0x4a40);
-               /* enlarge agcsel threshold 5 and threshold 4 */
-               rt305x_mii_write(esw, 0, 2, 0x6254);
-               /* enlarge agcsel threshold 6 */
-               rt305x_mii_write(esw, 0, 3, 0xa17f);
-               rt305x_mii_write(esw, 0, 12, 0x7eaa);
-               /* longer TP_IDL tail length */
-               rt305x_mii_write(esw, 0, 14, 0x65);
-               /* increased squelch pulse count threshold. */
-               rt305x_mii_write(esw, 0, 16, 0x0684);
-               /* set TX10 signal amplitude threshold to minimum */
-               rt305x_mii_write(esw, 0, 17, 0x0fe0);
-               /* set squelch amplitude to higher threshold */
-               rt305x_mii_write(esw, 0, 18, 0x40ba);
-               /* tune TP_IDL tail and head waveform, enable power
-                * down slew rate control
-                */
-               rt305x_mii_write(esw, 0, 22, 0x253f);
-               /* set PLL/Receive bias current are calibrated */
-               rt305x_mii_write(esw, 0, 27, 0x2fda);
-               /* change PLL/Receive bias current to internal(RT3350) */
-               rt305x_mii_write(esw, 0, 28, 0xc410);
-               /* change PLL bias current to internal(RT3052_MP3) */
-               rt305x_mii_write(esw, 0, 29, 0x598b);
-               /* select local register */
-               rt305x_mii_write(esw, 0, 31, 0x8000);
-       } else if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {
-               int i;
-
-               /* reset EPHY */
-               fe_reset(RT5350_RESET_EPHY);
-
-               rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */
-               rt305x_mii_write(esw, 0, 26, 0x0020);
-
-               for (i = 0; i < 5; i++) {
-                       rt305x_mii_write(esw, i, 31, 0x8000);
-                       rt305x_mii_write(esw, i,  0, 0x3100);
-                       rt305x_mii_write(esw, i, 30, 0xa000);
-                       rt305x_mii_write(esw, i, 31, 0xa000);
-                       rt305x_mii_write(esw, i, 16, 0x0606);
-                       rt305x_mii_write(esw, i, 23, 0x0f0e);
-                       rt305x_mii_write(esw, i, 24, 0x1610);
-                       rt305x_mii_write(esw, i, 30, 0x1f15);
-                       rt305x_mii_write(esw, i, 28, 0x6111);
-                       rt305x_mii_write(esw, i, 31, 0x2000);
-                       rt305x_mii_write(esw, i, 26, 0x0000);
-               }
-
-               /* 100Base AOI setting */
-               rt305x_mii_write(esw, 0, 31, 0x5000);
-               rt305x_mii_write(esw, 0, 19, 0x004a);
-               rt305x_mii_write(esw, 0, 20, 0x015a);
-               rt305x_mii_write(esw, 0, 21, 0x00ee);
-               rt305x_mii_write(esw, 0, 22, 0x0033);
-               rt305x_mii_write(esw, 0, 23, 0x020a);
-               rt305x_mii_write(esw, 0, 24, 0x0000);
-               rt305x_mii_write(esw, 0, 25, 0x024a);
-               rt305x_mii_write(esw, 0, 26, 0x035a);
-               rt305x_mii_write(esw, 0, 27, 0x02ee);
-               rt305x_mii_write(esw, 0, 28, 0x0233);
-               rt305x_mii_write(esw, 0, 29, 0x000a);
-               rt305x_mii_write(esw, 0, 30, 0x0000);
-       } else {
-               rt305x_mii_write(esw, 0, 31, 0x8000);
-               for (i = 0; i < 5; i++) {
-                       if (esw->ports[i].disable) {
-                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
-                       } else {
-                               rt305x_mii_write(esw, i, MII_BMCR,
-                                                BMCR_FULLDPLX |
-                                                BMCR_ANENABLE |
-                                                BMCR_SPEED100);
-                       }
-                       /* TX10 waveform coefficient */
-                       rt305x_mii_write(esw, i, 26, 0x1601);
-                       /* TX100/TX10 AD/DA current bias */
-                       rt305x_mii_write(esw, i, 29, 0x7058);
-                       /* TX100 slew rate control */
-                       rt305x_mii_write(esw, i, 30, 0x0018);
-               }
-
-               /* PHY IOT */
-               /* select global register */
-               rt305x_mii_write(esw, 0, 31, 0x0);
-               /* tune TP_IDL tail and head waveform */
-               rt305x_mii_write(esw, 0, 22, 0x052f);
-               /* set TX10 signal amplitude threshold to minimum */
-               rt305x_mii_write(esw, 0, 17, 0x0fe0);
-               /* set squelch amplitude to higher threshold */
-               rt305x_mii_write(esw, 0, 18, 0x40ba);
-               /* longer TP_IDL tail length */
-               rt305x_mii_write(esw, 0, 14, 0x65);
-               /* select local register */
-               rt305x_mii_write(esw, 0, 31, 0x8000);
-       }
-
-       if (esw->port_map)
-               port_map = esw->port_map;
-       else
-               port_map = RT305X_ESW_PMAP_LLLLLL;
-
-       /* Unused HW feature, but still nice to be consistent here...
-        * This is also exported to userspace ('lan' attribute) so it's
-        * conveniently usable to decide which ports go into the wan vlan by
-        * default.
-        */
-       esw_rmw(esw, RT305X_ESW_REG_SGC2,
-               RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
-               port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
-
-       /* make the switch leds blink */
-       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
-               esw->ports[i].led = 0x05;
-
-       /* Apply the empty config. */
-       esw_apply_config(&esw->swdev);
-
-       /* Only unmask the port change interrupt */
-       esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
-}
-
-static irqreturn_t esw_interrupt(int irq, void *_esw)
-{
-       struct rt305x_esw *esw = (struct rt305x_esw *)_esw;
-       u32 status;
-
-       status = esw_r32(esw, RT305X_ESW_REG_ISR);
-       if (status & RT305X_ESW_PORT_ST_CHG) {
-               u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
-
-               link >>= RT305X_ESW_POA_LINK_SHIFT;
-               link &= RT305X_ESW_POA_LINK_MASK;
-               dev_info(esw->dev, "link changed 0x%02X\n", link);
-       }
-       esw_w32(esw, status, RT305X_ESW_REG_ISR);
-
-       return IRQ_HANDLED;
-}
-
-static int esw_apply_config(struct switch_dev *dev)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-       int i;
-       u8 disable = 0;
-       u8 doubletag = 0;
-       u8 en_vlan = 0;
-       u8 untag = 0;
-
-       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
-               u32 vid, vmsc;
-               if (esw->global_vlan_enable) {
-                       vid = esw->vlans[i].vid;
-                       vmsc = esw->vlans[i].ports;
-               } else {
-                       vid = RT305X_ESW_VLAN_NONE;
-                       vmsc = RT305X_ESW_PORTS_NONE;
-               }
-               esw_set_vlan_id(esw, i, vid);
-               esw_set_vmsc(esw, i, vmsc);
-       }
-
-       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
-               u32 pvid;
-               disable |= esw->ports[i].disable << i;
-               if (esw->global_vlan_enable) {
-                       doubletag |= esw->ports[i].doubletag << i;
-                       en_vlan   |= 1                       << i;
-                       untag     |= esw->ports[i].untag     << i;
-                       pvid       = esw->ports[i].pvid;
-               } else {
-                       int x = esw->alt_vlan_disable ? 0 : 1;
-                       doubletag |= x << i;
-                       en_vlan   |= x << i;
-                       untag     |= x << i;
-                       pvid       = 0;
-               }
-               esw_set_pvid(esw, i, pvid);
-               if (i < RT305X_ESW_NUM_LEDS)
-                       esw_w32(esw, esw->ports[i].led,
-                                     RT305X_ESW_REG_P0LED + 4*i);
-       }
-
-       esw_set_gsc(esw);
-       esw_set_port_disable(esw, disable);
-       esw_rmw(esw, RT305X_ESW_REG_SGC2,
-                      (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
-                       RT305X_ESW_SGC2_DOUBLE_TAG_S),
-                      doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
-       esw_rmw(esw, RT305X_ESW_REG_PFC1,
-                      RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
-                      en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
-       esw_rmw(esw, RT305X_ESW_REG_POC2,
-                      RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
-                      untag << RT305X_ESW_POC2_UNTAG_EN_S);
-
-       if (!esw->global_vlan_enable) {
-               /*
-                * Still need to put all ports into vlan 0 or they'll be
-                * isolated.
-                * NOTE: vlan 0 is special, no vlan tag is prepended
-                */
-               esw_set_vlan_id(esw, 0, 0);
-               esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
-       }
-
-       return 0;
-}
-
-static int esw_reset_switch(struct switch_dev *dev)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-
-       esw->global_vlan_enable = 0;
-       memset(esw->ports, 0, sizeof(esw->ports));
-       memset(esw->vlans, 0, sizeof(esw->vlans));
-       esw_hw_init(esw);
-
-       return 0;
-}
-
-static int esw_get_vlan_enable(struct switch_dev *dev,
-                          const struct switch_attr *attr,
-                          struct switch_val *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-
-       val->value.i = esw->global_vlan_enable;
-
-       return 0;
-}
-
-static int esw_set_vlan_enable(struct switch_dev *dev,
-                          const struct switch_attr *attr,
-                          struct switch_val *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-
-       esw->global_vlan_enable = val->value.i != 0;
-
-       return 0;
-}
-
-static int esw_get_alt_vlan_disable(struct switch_dev *dev,
-                               const struct switch_attr *attr,
-                               struct switch_val *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-
-       val->value.i = esw->alt_vlan_disable;
-
-       return 0;
-}
-
-static int esw_set_alt_vlan_disable(struct switch_dev *dev,
-                               const struct switch_attr *attr,
-                               struct switch_val *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-
-       esw->alt_vlan_disable = val->value.i != 0;
-
-       return 0;
-}
-
-static int
-rt305x_esw_set_bc_status(struct switch_dev *dev,
-                       const struct switch_attr *attr,
-                       struct switch_val *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-
-       esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
-
-       return 0;
-}
-
-static int
-rt305x_esw_get_bc_status(struct switch_dev *dev,
-                       const struct switch_attr *attr,
-                       struct switch_val *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-
-       val->value.i = esw->bc_storm_protect;
-
-       return 0;
-}
-
-static int
-rt305x_esw_set_led_freq(struct switch_dev *dev,
-                       const struct switch_attr *attr,
-                       struct switch_val *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-
-       esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
-
-       return 0;
-}
-
-static int
-rt305x_esw_get_led_freq(struct switch_dev *dev,
-                       const struct switch_attr *attr,
-                       struct switch_val *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-
-       val->value.i = esw->led_frequency;
-
-       return 0;
-}
-
-static int esw_get_port_link(struct switch_dev *dev,
-                        int port,
-                        struct switch_port_link *link)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-       u32 speed, poa;
-
-       if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
-               return -EINVAL;
-
-       poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
-
-       link->link = (poa >> RT305X_ESW_LINK_S) & 1;
-       link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
-       if (port < RT305X_ESW_NUM_LEDS) {
-               speed = (poa >> RT305X_ESW_SPD_S) & 1;
-       } else {
-               if (port == RT305X_ESW_NUM_PORTS - 1)
-                       poa >>= 1;
-               speed = (poa >> RT305X_ESW_SPD_S) & 3;
-       }
-       switch (speed) {
-       case 0:
-               link->speed = SWITCH_PORT_SPEED_10;
-               break;
-       case 1:
-               link->speed = SWITCH_PORT_SPEED_100;
-               break;
-       case 2:
-       case 3: /* forced gige speed can be 2 or 3 */
-               link->speed = SWITCH_PORT_SPEED_1000;
-               break;
-       default:
-               link->speed = SWITCH_PORT_SPEED_UNKNOWN;
-               break;
-       }
-
-       return 0;
-}
-
-static int esw_get_port_bool(struct switch_dev *dev,
-                        const struct switch_attr *attr,
-                        struct switch_val *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-       int idx = val->port_vlan;
-       u32 x, reg, shift;
-
-       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
-               return -EINVAL;
-
-       switch (attr->id) {
-       case RT305X_ESW_ATTR_PORT_DISABLE:
-               reg = RT305X_ESW_REG_POC0;
-               shift = RT305X_ESW_POC0_DIS_PORT_S;
-               break;
-       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
-               reg = RT305X_ESW_REG_SGC2;
-               shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
-               break;
-       case RT305X_ESW_ATTR_PORT_UNTAG:
-               reg = RT305X_ESW_REG_POC2;
-               shift = RT305X_ESW_POC2_UNTAG_EN_S;
-               break;
-       case RT305X_ESW_ATTR_PORT_LAN:
-               reg = RT305X_ESW_REG_SGC2;
-               shift = RT305X_ESW_SGC2_LAN_PMAP_S;
-               if (idx >= RT305X_ESW_NUM_LANWAN)
-                       return -EINVAL;
-               break;
-       default:
-               return -EINVAL;
-       }
-
-       x = esw_r32(esw, reg);
-       val->value.i = (x >> (idx + shift)) & 1;
-
-       return 0;
-}
-
-static int esw_set_port_bool(struct switch_dev *dev,
-                        const struct switch_attr *attr,
-                        struct switch_val *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-       int idx = val->port_vlan;
-
-       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
-           val->value.i < 0 || val->value.i > 1)
-               return -EINVAL;
-
-       switch (attr->id) {
-       case RT305X_ESW_ATTR_PORT_DISABLE:
-               esw->ports[idx].disable = val->value.i;
-               break;
-       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
-               esw->ports[idx].doubletag = val->value.i;
-               break;
-       case RT305X_ESW_ATTR_PORT_UNTAG:
-               esw->ports[idx].untag = val->value.i;
-               break;
-       default:
-               return -EINVAL;
-       }
-
-       return 0;
-}
-
-static int esw_get_port_recv_badgood(struct switch_dev *dev,
-                                const struct switch_attr *attr,
-                                struct switch_val *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-       int idx = val->port_vlan;
-       int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
-       u32 reg;
-
-       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
-               return -EINVAL;
-       reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
-       val->value.i = (reg >> shift) & 0xffff;
-
-       return 0;
-}
-
-static int
-esw_get_port_tr_badgood(struct switch_dev *dev,
-                                const struct switch_attr *attr,
-                                struct switch_val *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-
-       int idx = val->port_vlan;
-       int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
-       u32 reg;
-
-       if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN) && (ralink_soc != MT762X_SOC_MT7688))
-               return -EINVAL;
-
-       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
-               return -EINVAL;
-
-       reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
-       val->value.i = (reg >> shift) & 0xffff;
-
-       return 0;
-}
-
-static int esw_get_port_led(struct switch_dev *dev,
-                       const struct switch_attr *attr,
-                       struct switch_val *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-       int idx = val->port_vlan;
-
-       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
-           idx >= RT305X_ESW_NUM_LEDS)
-               return -EINVAL;
-
-       val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
-
-       return 0;
-}
-
-static int esw_set_port_led(struct switch_dev *dev,
-                       const struct switch_attr *attr,
-                       struct switch_val *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-       int idx = val->port_vlan;
-
-       if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
-               return -EINVAL;
-
-       esw->ports[idx].led = val->value.i;
-
-       return 0;
-}
-
-static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-
-       if (port >= RT305X_ESW_NUM_PORTS)
-               return -EINVAL;
-
-       *val = esw_get_pvid(esw, port);
-
-       return 0;
-}
-
-static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-
-       if (port >= RT305X_ESW_NUM_PORTS)
-               return -EINVAL;
-
-       esw->ports[port].pvid = val;
-
-       return 0;
-}
-
-static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-       u32 vmsc, poc2;
-       int vlan_idx = -1;
-       int i;
-
-       val->len = 0;
-
-       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
-               return -EINVAL;
-
-       /* valid vlan? */
-       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
-               if (esw_get_vlan_id(esw, i) == val->port_vlan &&
-                   esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
-                       vlan_idx = i;
-                       break;
-               }
-       }
-
-       if (vlan_idx == -1)
-               return -EINVAL;
-
-       vmsc = esw_get_vmsc(esw, vlan_idx);
-       poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
-
-       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
-               struct switch_port *p;
-               int port_mask = 1 << i;
-
-               if (!(vmsc & port_mask))
-                       continue;
-
-               p = &val->value.ports[val->len++];
-               p->id = i;
-               if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
-                       p->flags = 0;
-               else
-                       p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
-       }
-
-       return 0;
-}
-
-static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
-{
-       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
-       int ports;
-       int vlan_idx = -1;
-       int i;
-
-       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
-           val->len > RT305X_ESW_NUM_PORTS)
-               return -EINVAL;
-
-       /* one of the already defined vlans? */
-       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
-               if (esw->vlans[i].vid == val->port_vlan &&
-                   esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
-                       vlan_idx = i;
-                       break;
-               }
-       }
-
-       /* select a free slot */
-       for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
-               if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
-                       vlan_idx = i;
-       }
-
-       /* bail if all slots are in use */
-       if (vlan_idx == -1)
-               return -EINVAL;
-
-       ports = RT305X_ESW_PORTS_NONE;
-       for (i = 0; i < val->len; i++) {
-               struct switch_port *p = &val->value.ports[i];
-               int port_mask = 1 << p->id;
-               bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
-
-               if (p->id >= RT305X_ESW_NUM_PORTS)
-                       return -EINVAL;
-
-               ports |= port_mask;
-               esw->ports[p->id].untag = untagged;
-       }
-       esw->vlans[vlan_idx].ports = ports;
-       if (ports == RT305X_ESW_PORTS_NONE)
-               esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
-       else
-               esw->vlans[vlan_idx].vid = val->port_vlan;
-
-       return 0;
-}
-
-static const struct switch_attr esw_global[] = {
-       {
-               .type = SWITCH_TYPE_INT,
-               .name = "enable_vlan",
-               .description = "VLAN mode (1:enabled)",
-               .max = 1,
-               .id = RT305X_ESW_ATTR_ENABLE_VLAN,
-               .get = esw_get_vlan_enable,
-               .set = esw_set_vlan_enable,
-       },
-       {
-               .type = SWITCH_TYPE_INT,
-               .name = "alternate_vlan_disable",
-               .description = "Use en_vlan instead of doubletag to disable"
-                               " VLAN mode",
-               .max = 1,
-               .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
-               .get = esw_get_alt_vlan_disable,
-               .set = esw_set_alt_vlan_disable,
-       },
-       {
-               .type = SWITCH_TYPE_INT,
-               .name = "bc_storm_protect",
-               .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
-               .max = 3,
-               .id = RT305X_ESW_ATTR_BC_STATUS,
-               .get = rt305x_esw_get_bc_status,
-               .set = rt305x_esw_set_bc_status,
-       },
-       {
-               .type = SWITCH_TYPE_INT,
-               .name = "led_frequency",
-               .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
-               .max = 3,
-               .id = RT305X_ESW_ATTR_LED_FREQ,
-               .get = rt305x_esw_get_led_freq,
-               .set = rt305x_esw_set_led_freq,
-       }
-};
-
-static const struct switch_attr esw_port[] = {
-       {
-               .type = SWITCH_TYPE_INT,
-               .name = "disable",
-               .description = "Port state (1:disabled)",
-               .max = 1,
-               .id = RT305X_ESW_ATTR_PORT_DISABLE,
-               .get = esw_get_port_bool,
-               .set = esw_set_port_bool,
-       },
-       {
-               .type = SWITCH_TYPE_INT,
-               .name = "doubletag",
-               .description = "Double tagging for incoming vlan packets "
-                               "(1:enabled)",
-               .max = 1,
-               .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
-               .get = esw_get_port_bool,
-               .set = esw_set_port_bool,
-       },
-       {
-               .type = SWITCH_TYPE_INT,
-               .name = "untag",
-               .description = "Untag (1:strip outgoing vlan tag)",
-               .max = 1,
-               .id = RT305X_ESW_ATTR_PORT_UNTAG,
-               .get = esw_get_port_bool,
-               .set = esw_set_port_bool,
-       },
-       {
-               .type = SWITCH_TYPE_INT,
-               .name = "led",
-               .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
-                               " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
-                               " 8:100mact, 10:blink, 11:off, 12:on)",
-               .max = 15,
-               .id = RT305X_ESW_ATTR_PORT_LED,
-               .get = esw_get_port_led,
-               .set = esw_set_port_led,
-       },
-       {
-               .type = SWITCH_TYPE_INT,
-               .name = "lan",
-               .description = "HW port group (0:wan, 1:lan)",
-               .max = 1,
-               .id = RT305X_ESW_ATTR_PORT_LAN,
-               .get = esw_get_port_bool,
-       },
-       {
-               .type = SWITCH_TYPE_INT,
-               .name = "recv_bad",
-               .description = "Receive bad packet counter",
-               .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
-               .get = esw_get_port_recv_badgood,
-       },
-       {
-               .type = SWITCH_TYPE_INT,
-               .name = "recv_good",
-               .description = "Receive good packet counter",
-               .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
-               .get = esw_get_port_recv_badgood,
-       },
-       {
-               .type = SWITCH_TYPE_INT,
-               .name = "tr_bad",
-
-               .description = "Transmit bad packet counter. rt5350 only",
-               .id = RT5350_ESW_ATTR_PORT_TR_BAD,
-               .get = esw_get_port_tr_badgood,
-       },
-       {
-               .type = SWITCH_TYPE_INT,
-               .name = "tr_good",
-
-               .description = "Transmit good packet counter. rt5350 only",
-               .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
-               .get = esw_get_port_tr_badgood,
-       },
-};
-
-static const struct switch_attr esw_vlan[] = {
-};
-
-static const struct switch_dev_ops esw_ops = {
-       .attr_global = {
-               .attr = esw_global,
-               .n_attr = ARRAY_SIZE(esw_global),
-       },
-       .attr_port = {
-               .attr = esw_port,
-               .n_attr = ARRAY_SIZE(esw_port),
-       },
-       .attr_vlan = {
-               .attr = esw_vlan,
-               .n_attr = ARRAY_SIZE(esw_vlan),
-       },
-       .get_vlan_ports = esw_get_vlan_ports,
-       .set_vlan_ports = esw_set_vlan_ports,
-       .get_port_pvid = esw_get_port_pvid,
-       .set_port_pvid = esw_set_port_pvid,
-       .get_port_link = esw_get_port_link,
-       .apply_config = esw_apply_config,
-       .reset_switch = esw_reset_switch,
-};
-
-static int esw_probe(struct platform_device *pdev)
-{
-       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-       struct device_node *np = pdev->dev.of_node;
-       const __be32 *port_map, *port_disable, *reg_init;
-       struct switch_dev *swdev;
-       struct rt305x_esw *esw;
-       int ret;
-
-       esw = devm_kzalloc(&pdev->dev, sizeof(*esw), GFP_KERNEL);
-       if (!esw)
-               return -ENOMEM;
-
-       esw->dev = &pdev->dev;
-       esw->irq = irq_of_parse_and_map(np, 0);
-       esw->base = devm_ioremap_resource(&pdev->dev, res);
-       if (!esw->base)
-               return -EADDRNOTAVAIL;
-
-       port_map = of_get_property(np, "mediatek,portmap", NULL);
-       if (port_map)
-               esw->port_map = be32_to_cpu(*port_map);
-
-       port_disable = of_get_property(np, "mediatek,portdisable", NULL);
-       if (port_disable)
-               esw->port_disable = be32_to_cpu(*port_disable);
-
-       reg_init = of_get_property(np, "ralink,fct2", NULL);
-       if (reg_init)
-               esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
-
-       reg_init = of_get_property(np, "ralink,fpa2", NULL);
-       if (reg_init)
-               esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
-
-       reg_init = of_get_property(np, "mediatek,led_polarity", NULL);
-       if (reg_init)
-               esw->reg_led_polarity = be32_to_cpu(*reg_init);
-
-       swdev = &esw->swdev;
-       swdev->of_node = pdev->dev.of_node;
-       swdev->name = "rt305x-esw";
-       swdev->alias = "rt305x";
-       swdev->cpu_port = RT305X_ESW_PORT6;
-       swdev->ports = RT305X_ESW_NUM_PORTS;
-       swdev->vlans = RT305X_ESW_NUM_VIDS;
-       swdev->ops = &esw_ops;
-
-       ret = register_switch(swdev, NULL);
-       if (ret < 0) {
-               dev_err(&pdev->dev, "register_switch failed\n");
-               return ret;
-       }
-
-       platform_set_drvdata(pdev, esw);
-
-       spin_lock_init(&esw->reg_rw_lock);
-
-       esw_hw_init(esw);
-
-       reg_init = of_get_property(np, "ralink,rgmii", NULL);
-       if (reg_init && be32_to_cpu(*reg_init) == 1) {
-               /* 
-                * External switch connected to RGMII interface. 
-                * Unregister the switch device after initialization. 
-                */
-               dev_err(&pdev->dev, "RGMII mode, not exporting switch device.\n");
-               unregister_switch(&esw->swdev);
-               platform_set_drvdata(pdev, NULL);
-               return -ENODEV;
-       }
-
-       ret = devm_request_irq(&pdev->dev, esw->irq, esw_interrupt, 0, "esw",
-                              esw);
-
-       if (!ret) {
-               esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
-               esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
-       }
-
-       return ret;
-}
-
-static int esw_remove(struct platform_device *pdev)
-{
-       struct rt305x_esw *esw = platform_get_drvdata(pdev);
-
-       if (esw) {
-               esw_w32(esw, ~0, RT305X_ESW_REG_IMR);
-               platform_set_drvdata(pdev, NULL);
-       }
-
-       return 0;
-}
-
-static const struct of_device_id ralink_esw_match[] = {
-       { .compatible = "ralink,rt3050-esw" },
-       {},
-};
-MODULE_DEVICE_TABLE(of, ralink_esw_match);
-
-static struct platform_driver esw_driver = {
-       .probe = esw_probe,
-       .remove = esw_remove,
-       .driver = {
-               .name = "rt3050-esw",
-               .owner = THIS_MODULE,
-               .of_match_table = ralink_esw_match,
-       },
-};
-
-module_platform_driver(esw_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-MODULE_DESCRIPTION("Switch driver for RT305X SoC");
-MODULE_VERSION(MTK_FE_DRV_VERSION);
diff --git a/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/esw_rt3050.h b/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/esw_rt3050.h
deleted file mode 100644 (file)
index b757e5d..0000000
+++ /dev/null
@@ -1,29 +0,0 @@
-/*   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; version 2 of the License
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
- *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
- *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
- */
-
-#ifndef _RALINK_ESW_RT3052_H__
-#define _RALINK_ESW_RT3052_H__
-
-#ifdef CONFIG_NET_MEDIATEK_ESW_RT3052
-
-int __init mtk_switch_init(void);
-void mtk_switch_exit(void);
-
-#else
-
-static inline int __init mtk_switch_init(void) { return 0; }
-static inline void mtk_switch_exit(void) { }
-
-#endif
-#endif
diff --git a/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/ethtool.c b/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/ethtool.c
deleted file mode 100644 (file)
index 9e65d5e..0000000
+++ /dev/null
@@ -1,233 +0,0 @@
-/*   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; version 2 of the License
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
- *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
- *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
- */
-
-#include "mtk_eth_soc.h"
-
-static const char fe_gdma_str[][ETH_GSTRING_LEN] = {
-#define _FE(x...)      # x,
-FE_STAT_REG_DECLARE
-#undef _FE
-};
-
-static int fe_get_settings(struct net_device *dev,
-                          struct ethtool_cmd *cmd)
-{
-       struct fe_priv *priv = netdev_priv(dev);
-       int err;
-
-       if (!priv->phy_dev)
-               goto out_gset;
-
-       if (priv->phy_flags == FE_PHY_FLAG_ATTACH) {
-               err = phy_read_status(priv->phy_dev);
-               if (err)
-                       goto out_gset;
-       }
-
-       return phy_ethtool_gset(priv->phy_dev, cmd);
-
-out_gset:
-       return -ENODEV;
-}
-
-static int fe_set_settings(struct net_device *dev,
-                          struct ethtool_cmd *cmd)
-{
-       struct fe_priv *priv = netdev_priv(dev);
-
-       if (!priv->phy_dev)
-               goto out_sset;
-
-       if (cmd->phy_address != priv->phy_dev->mdio.addr) {
-               if (priv->phy->phy_node[cmd->phy_address]) {
-                       priv->phy_dev = priv->phy->phy[cmd->phy_address];
-                       priv->phy_flags = FE_PHY_FLAG_PORT;
-               } else if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, cmd->phy_address)) {
-                       priv->phy_dev = mdiobus_get_phy(priv->mii_bus, cmd->phy_address);
-                       priv->phy_flags = FE_PHY_FLAG_ATTACH;
-               } else {
-                       goto out_sset;
-               }
-       }
-
-       return phy_ethtool_sset(priv->phy_dev, cmd);
-
-out_sset:
-       return -ENODEV;
-}
-
-static void fe_get_drvinfo(struct net_device *dev,
-                          struct ethtool_drvinfo *info)
-{
-       struct fe_priv *priv = netdev_priv(dev);
-       struct fe_soc_data *soc = priv->soc;
-
-       strlcpy(info->driver, priv->device->driver->name, sizeof(info->driver));
-       strlcpy(info->version, MTK_FE_DRV_VERSION, sizeof(info->version));
-       strlcpy(info->bus_info, dev_name(priv->device), sizeof(info->bus_info));
-
-       if (soc->reg_table[FE_REG_FE_COUNTER_BASE])
-               info->n_stats = ARRAY_SIZE(fe_gdma_str);
-}
-
-static u32 fe_get_msglevel(struct net_device *dev)
-{
-       struct fe_priv *priv = netdev_priv(dev);
-
-       return priv->msg_enable;
-}
-
-static void fe_set_msglevel(struct net_device *dev, u32 value)
-{
-       struct fe_priv *priv = netdev_priv(dev);
-
-       priv->msg_enable = value;
-}
-
-static int fe_nway_reset(struct net_device *dev)
-{
-       struct fe_priv *priv = netdev_priv(dev);
-
-       if (!priv->phy_dev)
-               goto out_nway_reset;
-
-       return genphy_restart_aneg(priv->phy_dev);
-
-out_nway_reset:
-       return -EOPNOTSUPP;
-}
-
-static u32 fe_get_link(struct net_device *dev)
-{
-       struct fe_priv *priv = netdev_priv(dev);
-       int err;
-
-       if (!priv->phy_dev)
-               goto out_get_link;
-
-       if (priv->phy_flags == FE_PHY_FLAG_ATTACH) {
-               err = genphy_update_link(priv->phy_dev);
-               if (err)
-                       goto out_get_link;
-       }
-
-       return priv->phy_dev->link;
-
-out_get_link:
-       return ethtool_op_get_link(dev);
-}
-
-static int fe_set_ringparam(struct net_device *dev,
-                           struct ethtool_ringparam *ring)
-{
-       struct fe_priv *priv = netdev_priv(dev);
-
-       if ((ring->tx_pending < 2) ||
-           (ring->rx_pending < 2) ||
-           (ring->rx_pending > MAX_DMA_DESC) ||
-           (ring->tx_pending > MAX_DMA_DESC))
-               return -EINVAL;
-
-       dev->netdev_ops->ndo_stop(dev);
-
-       priv->tx_ring.tx_ring_size = BIT(fls(ring->tx_pending) - 1);
-       priv->rx_ring.rx_ring_size = BIT(fls(ring->rx_pending) - 1);
-
-       dev->netdev_ops->ndo_open(dev);
-
-       return 0;
-}
-
-static void fe_get_ringparam(struct net_device *dev,
-                            struct ethtool_ringparam *ring)
-{
-       struct fe_priv *priv = netdev_priv(dev);
-
-       ring->rx_max_pending = MAX_DMA_DESC;
-       ring->tx_max_pending = MAX_DMA_DESC;
-       ring->rx_pending = priv->rx_ring.rx_ring_size;
-       ring->tx_pending = priv->tx_ring.tx_ring_size;
-}
-
-static void fe_get_strings(struct net_device *dev, u32 stringset, u8 *data)
-{
-       switch (stringset) {
-       case ETH_SS_STATS:
-               memcpy(data, *fe_gdma_str, sizeof(fe_gdma_str));
-               break;
-       }
-}
-
-static int fe_get_sset_count(struct net_device *dev, int sset)
-{
-       switch (sset) {
-       case ETH_SS_STATS:
-               return ARRAY_SIZE(fe_gdma_str);
-       default:
-               return -EOPNOTSUPP;
-       }
-}
-
-static void fe_get_ethtool_stats(struct net_device *dev,
-                                struct ethtool_stats *stats, u64 *data)
-{
-       struct fe_priv *priv = netdev_priv(dev);
-       struct fe_hw_stats *hwstats = priv->hw_stats;
-       u64 *data_src, *data_dst;
-       unsigned int start;
-       int i;
-
-       if (netif_running(dev) && netif_device_present(dev)) {
-               if (spin_trylock(&hwstats->stats_lock)) {
-                       fe_stats_update(priv);
-                       spin_unlock(&hwstats->stats_lock);
-               }
-       }
-
-       do {
-               data_src = &hwstats->tx_bytes;
-               data_dst = data;
-               start = u64_stats_fetch_begin_irq(&hwstats->syncp);
-
-               for (i = 0; i < ARRAY_SIZE(fe_gdma_str); i++)
-                       *data_dst++ = *data_src++;
-
-       } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
-}
-
-static struct ethtool_ops fe_ethtool_ops = {
-       .get_settings           = fe_get_settings,
-       .set_settings           = fe_set_settings,
-       .get_drvinfo            = fe_get_drvinfo,
-       .get_msglevel           = fe_get_msglevel,
-       .set_msglevel           = fe_set_msglevel,
-       .nway_reset             = fe_nway_reset,
-       .get_link               = fe_get_link,
-       .set_ringparam          = fe_set_ringparam,
-       .get_ringparam          = fe_get_ringparam,
-};
-
-void fe_set_ethtool_ops(struct net_device *netdev)
-{
-       struct fe_priv *priv = netdev_priv(netdev);
-       struct fe_soc_data *soc = priv->soc;
-
-       if (soc->reg_table[FE_REG_FE_COUNTER_BASE]) {
-               fe_ethtool_ops.get_strings = fe_get_strings;
-               fe_ethtool_ops.get_sset_count = fe_get_sset_count;
-               fe_ethtool_ops.get_ethtool_stats = fe_get_ethtool_stats;
-       }
-
-       netdev->ethtool_ops = &fe_ethtool_ops;
-}
diff --git a/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/ethtool.h b/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/ethtool.h
deleted file mode 100644 (file)
index 6fd16f0..0000000
+++ /dev/null
@@ -1,22 +0,0 @@
-/*   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; version 2 of the License
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
- *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
- *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
- */
-
-#ifndef FE_ETHTOOL_H
-#define FE_ETHTOOL_H
-
-#include <linux/ethtool.h>
-
-void fe_set_ethtool_ops(struct net_device *netdev);
-
-#endif /* FE_ETHTOOL_H */
diff --git a/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/gsw_mt7620.c b/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/gsw_mt7620.c
deleted file mode 100644 (file)
index 4093f09..0000000
+++ /dev/null
@@ -1,260 +0,0 @@
-/*   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; version 2 of the License
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
- *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
- *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/platform_device.h>
-#include <linux/of_device.h>
-#include <linux/of_irq.h>
-
-#include <ralink_regs.h>
-
-#include "mtk_eth_soc.h"
-#include "gsw_mt7620.h"
-
-void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
-{
-       iowrite32(val, gsw->base + reg);
-}
-
-u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
-{
-       return ioread32(gsw->base + reg);
-}
-
-static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
-{
-       struct fe_priv *priv = (struct fe_priv *)_priv;
-       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
-       u32 status;
-       int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
-
-       status = mtk_switch_r32(gsw, GSW_REG_ISR);
-       if (status & PORT_IRQ_ST_CHG)
-               for (i = 0; i <= max; i++) {
-                       u32 status = mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i));
-                       int link = status & 0x1;
-
-                       if (link != priv->link[i])
-                               mt7620_print_link_state(priv, i, link,
-                                                       (status >> 2) & 3,
-                                                       (status & 0x2));
-
-                       priv->link[i] = link;
-               }
-       mt7620_handle_carrier(priv);
-       mtk_switch_w32(gsw, status, GSW_REG_ISR);
-
-       return IRQ_HANDLED;
-}
-
-static void mt7620_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
-{
-       u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
-
-       rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
-       mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
-
-       /* Enable MIB stats */
-       mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
-
-       if (of_property_read_bool(np, "mediatek,mt7530")) {
-               u32 val;
-
-               /* turn off ephy and set phy base addr to 12 */
-               mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
-                       (0x1f << 24) | (0xc << 16),
-                       GSW_REG_GPC1);
-
-               /* set MT7530 central align */
-               val = mt7530_mdio_r32(gsw, 0x7830);
-               val &= ~BIT(0);
-               val |= BIT(1);
-               mt7530_mdio_w32(gsw, 0x7830, val);
-
-               val = mt7530_mdio_r32(gsw, 0x7a40);
-               val &= ~BIT(30);
-               mt7530_mdio_w32(gsw, 0x7a40, val);
-
-               mt7530_mdio_w32(gsw, 0x7a78, 0x855);
-       } else {
-               /* global page 4 */
-               _mt7620_mii_write(gsw, 1, 31, 0x4000);
-
-               _mt7620_mii_write(gsw, 1, 17, 0x7444);
-               if (is_BGA)
-                       _mt7620_mii_write(gsw, 1, 19, 0x0114);
-               else
-                       _mt7620_mii_write(gsw, 1, 19, 0x0117);
-
-               _mt7620_mii_write(gsw, 1, 22, 0x10cf);
-               _mt7620_mii_write(gsw, 1, 25, 0x6212);
-               _mt7620_mii_write(gsw, 1, 26, 0x0777);
-               _mt7620_mii_write(gsw, 1, 29, 0x4000);
-               _mt7620_mii_write(gsw, 1, 28, 0xc077);
-               _mt7620_mii_write(gsw, 1, 24, 0x0000);
-
-               /* global page 3 */
-               _mt7620_mii_write(gsw, 1, 31, 0x3000);
-               _mt7620_mii_write(gsw, 1, 17, 0x4838);
-
-               /* global page 2 */
-               _mt7620_mii_write(gsw, 1, 31, 0x2000);
-               if (is_BGA) {
-                       _mt7620_mii_write(gsw, 1, 21, 0x0515);
-                       _mt7620_mii_write(gsw, 1, 22, 0x0053);
-                       _mt7620_mii_write(gsw, 1, 23, 0x00bf);
-                       _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
-                       _mt7620_mii_write(gsw, 1, 25, 0x0fad);
-                       _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
-               } else {
-                       _mt7620_mii_write(gsw, 1, 21, 0x0517);
-                       _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
-                       _mt7620_mii_write(gsw, 1, 23, 0x00bf);
-                       _mt7620_mii_write(gsw, 1, 24, 0x0aab);
-                       _mt7620_mii_write(gsw, 1, 25, 0x00ae);
-                       _mt7620_mii_write(gsw, 1, 26, 0x0fff);
-               }
-               /* global page 1 */
-               _mt7620_mii_write(gsw, 1, 31, 0x1000);
-               _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
-       }
-
-       /* global page 0 */
-       _mt7620_mii_write(gsw, 1, 31, 0x8000);
-       _mt7620_mii_write(gsw, 0, 30, 0xa000);
-       _mt7620_mii_write(gsw, 1, 30, 0xa000);
-       _mt7620_mii_write(gsw, 2, 30, 0xa000);
-       _mt7620_mii_write(gsw, 3, 30, 0xa000);
-
-       _mt7620_mii_write(gsw, 0, 4, 0x05e1);
-       _mt7620_mii_write(gsw, 1, 4, 0x05e1);
-       _mt7620_mii_write(gsw, 2, 4, 0x05e1);
-       _mt7620_mii_write(gsw, 3, 4, 0x05e1);
-
-       /* global page 2 */
-       _mt7620_mii_write(gsw, 1, 31, 0xa000);
-       _mt7620_mii_write(gsw, 0, 16, 0x1111);
-       _mt7620_mii_write(gsw, 1, 16, 0x1010);
-       _mt7620_mii_write(gsw, 2, 16, 0x1515);
-       _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
-
-       /* CPU Port6 Force Link 1G, FC ON */
-       mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
-
-       /* Set Port 6 as CPU Port */
-       mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
-
-       /* setup port 4 */
-       if (gsw->port4 == PORT4_EPHY) {
-               u32 val = rt_sysc_r32(SYSC_REG_CFG1);
-
-               val |= 3 << 14;
-               rt_sysc_w32(val, SYSC_REG_CFG1);
-               _mt7620_mii_write(gsw, 4, 30, 0xa000);
-               _mt7620_mii_write(gsw, 4, 4, 0x05e1);
-               _mt7620_mii_write(gsw, 4, 16, 0x1313);
-               _mt7620_mii_write(gsw, 4, 0, 0x3100);
-               pr_info("gsw: setting port4 to ephy mode\n");
-       }
-}
-
-static const struct of_device_id mediatek_gsw_match[] = {
-       { .compatible = "mediatek,mt7620-gsw" },
-       {},
-};
-MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
-
-int mtk_gsw_init(struct fe_priv *priv)
-{
-       struct device_node *np = priv->switch_np;
-       struct platform_device *pdev = of_find_device_by_node(np);
-       struct mt7620_gsw *gsw;
-
-       if (!pdev)
-               return -ENODEV;
-
-       if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
-               return -EINVAL;
-
-       gsw = platform_get_drvdata(pdev);
-       priv->soc->swpriv = gsw;
-
-       mt7620_hw_init(gsw, np);
-
-       if (gsw->irq) {
-               request_irq(gsw->irq, gsw_interrupt_mt7620, 0,
-                           "gsw", priv);
-               mtk_switch_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
-       }
-
-       return 0;
-}
-
-static int mt7620_gsw_probe(struct platform_device *pdev)
-{
-       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-       const char *port4 = NULL;
-       struct mt7620_gsw *gsw;
-       struct device_node *np = pdev->dev.of_node;
-
-       gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
-       if (!gsw)
-               return -ENOMEM;
-
-       gsw->base = devm_ioremap_resource(&pdev->dev, res);
-       if (!gsw->base)
-               return -EADDRNOTAVAIL;
-
-       gsw->dev = &pdev->dev;
-
-       of_property_read_string(np, "mediatek,port4", &port4);
-       if (port4 && !strcmp(port4, "ephy"))
-               gsw->port4 = PORT4_EPHY;
-       else if (port4 && !strcmp(port4, "gmac"))
-               gsw->port4 = PORT4_EXT;
-       else
-               gsw->port4 = PORT4_EPHY;
-
-       gsw->irq = platform_get_irq(pdev, 0);
-
-       platform_set_drvdata(pdev, gsw);
-
-       return 0;
-}
-
-static int mt7620_gsw_remove(struct platform_device *pdev)
-{
-       platform_set_drvdata(pdev, NULL);
-
-       return 0;
-}
-
-static struct platform_driver gsw_driver = {
-       .probe = mt7620_gsw_probe,
-       .remove = mt7620_gsw_remove,
-       .driver = {
-               .name = "mt7620-gsw",
-               .owner = THIS_MODULE,
-               .of_match_table = mediatek_gsw_match,
-       },
-};
-
-module_platform_driver(gsw_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC");
-MODULE_VERSION(MTK_FE_DRV_VERSION);
diff --git a/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/gsw_mt7620.h b/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/gsw_mt7620.h
deleted file mode 100644 (file)
index ae0b6de..0000000
+++ /dev/null
@@ -1,127 +0,0 @@
-/*   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; version 2 of the License
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
- *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
- *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
- */
-
-#ifndef _RALINK_GSW_MT7620_H__
-#define _RALINK_GSW_MT7620_H__
-
-#define GSW_REG_PHY_TIMEOUT    (5 * HZ)
-
-#ifdef CONFIG_SOC_MT7621
-#define MT7620A_GSW_REG_PIAC   0x0004
-#else
-#define MT7620A_GSW_REG_PIAC   0x7004
-#endif
-
-#define GSW_NUM_VLANS          16
-#define GSW_NUM_VIDS           4096
-#define GSW_NUM_PORTS          7
-#define GSW_PORT6              6
-
-#define GSW_MDIO_ACCESS                BIT(31)
-#define GSW_MDIO_READ          BIT(19)
-#define GSW_MDIO_WRITE         BIT(18)
-#define GSW_MDIO_START         BIT(16)
-#define GSW_MDIO_ADDR_SHIFT    20
-#define GSW_MDIO_REG_SHIFT     25
-
-#define GSW_REG_MIB_CNT_EN     0x4000
-
-#define GSW_REG_PORT_PMCR(x)   (0x3000 + (x * 0x100))
-#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
-#define GSW_REG_SMACCR0                0x3fE4
-#define GSW_REG_SMACCR1                0x3fE8
-#define GSW_REG_CKGCR          0x3ff0
-
-#define GSW_REG_IMR            0x7008
-#define GSW_REG_ISR            0x700c
-#define GSW_REG_GPC1           0x7014
-
-#define GSW_REG_MAC_P0_MCR     0x100
-#define GSW_REG_MAC_P1_MCR     0x200
-
-// Global MAC control register
-#define GSW_REG_GMACCR         0x30E0
-
-#define SYSC_REG_CHIP_REV_ID   0x0c
-#define SYSC_REG_CFG1          0x14
-#define RST_CTRL_MCM           BIT(2)
-#define SYSC_PAD_RGMII2_MDIO   0x58
-#define SYSC_GPIO_MODE         0x60
-
-#define PORT_IRQ_ST_CHG                0x7f
-
-#ifdef CONFIG_SOC_MT7621
-#define ESW_PHY_POLLING                0x0000
-#else
-#define ESW_PHY_POLLING                0x7000
-#endif
-
-#define        PMCR_IPG                BIT(18)
-#define        PMCR_MAC_MODE           BIT(16)
-#define        PMCR_FORCE              BIT(15)
-#define        PMCR_TX_EN              BIT(14)
-#define        PMCR_RX_EN              BIT(13)
-#define        PMCR_BACKOFF            BIT(9)
-#define        PMCR_BACKPRES           BIT(8)
-#define        PMCR_RX_FC              BIT(5)
-#define        PMCR_TX_FC              BIT(4)
-#define        PMCR_SPEED(_x)          (_x << 2)
-#define        PMCR_DUPLEX             BIT(1)
-#define        PMCR_LINK               BIT(0)
-
-#define PHY_AN_EN              BIT(31)
-#define PHY_PRE_EN             BIT(30)
-#define PMY_MDC_CONF(_x)       ((_x & 0x3f) << 24)
-
-
-enum {
-       /* Global attributes. */
-       GSW_ATTR_ENABLE_VLAN,
-       /* Port attributes. */
-       GSW_ATTR_PORT_UNTAG,
-};
-
-enum {
-       PORT4_EPHY = 0,
-       PORT4_EXT,
-};
-
-struct mt7620_gsw {
-       struct device           *dev;
-       void __iomem            *base;
-       int                     irq;
-       int                     port4;
-       unsigned long int       autopoll;
-};
-
-void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg);
-u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg);
-int mtk_gsw_init(struct fe_priv *priv);
-
-int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
-int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
-void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
-int mt7620_has_carrier(struct fe_priv *priv);
-void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
-                            int speed, int duplex);
-
-void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);
-u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);
-
-u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
-                            u32 phy_register, u32 write_data);
-u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg);
-void mt7620_handle_carrier(struct fe_priv *priv);
-
-#endif
diff --git a/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/gsw_mt7621.c b/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/gsw_mt7621.c
deleted file mode 100644 (file)
index 3adad48..0000000
+++ /dev/null
@@ -1,288 +0,0 @@
-/*   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; version 2 of the License
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
- *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
- *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/platform_device.h>
-#include <linux/of_device.h>
-#include <linux/of_irq.h>
-
-#include <ralink_regs.h>
-
-#include "mtk_eth_soc.h"
-#include "gsw_mt7620.h"
-
-void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
-{
-       iowrite32(val, gsw->base + reg);
-}
-
-u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
-{
-       return ioread32(gsw->base + reg);
-}
-
-static irqreturn_t gsw_interrupt_mt7621(int irq, void *_priv)
-{
-       struct fe_priv *priv = (struct fe_priv *)_priv;
-       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
-       u32 reg, i;
-
-       reg = mt7530_mdio_r32(gsw, 0x700c);
-
-       for (i = 0; i < 5; i++)
-               if (reg & BIT(i)) {
-                       unsigned int link;
-
-                       link = mt7530_mdio_r32(gsw,
-                                              0x3008 + (i * 0x100)) & 0x1;
-
-                       if (link != priv->link[i]) {
-                               priv->link[i] = link;
-                               if (link)
-                                       netdev_info(priv->netdev,
-                                                   "port %d link up\n", i);
-                               else
-                                       netdev_info(priv->netdev,
-                                                   "port %d link down\n", i);
-                       }
-               }
-
-       mt7620_handle_carrier(priv);
-       mt7530_mdio_w32(gsw, 0x700c, 0x1f);
-
-       return IRQ_HANDLED;
-}
-
-static void mt7621_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
-{
-       u32 i;
-       u32 val;
-
-       /* wardware reset the switch */
-       fe_reset(RST_CTRL_MCM);
-       mdelay(10);
-
-       /* reduce RGMII2 PAD driving strength */
-       rt_sysc_m32(3 << 4, 0, SYSC_PAD_RGMII2_MDIO);
-
-       /* gpio mux - RGMII1=Normal mode */
-       rt_sysc_m32(BIT(14), 0, SYSC_GPIO_MODE);
-
-       /* set GMAC1 RGMII mode */
-       rt_sysc_m32(3 << 12, 0, SYSC_REG_CFG1);
-
-       /* enable MDIO to control MT7530 */
-       rt_sysc_m32(3 << 12, 0, SYSC_GPIO_MODE);
-
-       /* turn off all PHYs */
-       for (i = 0; i <= 4; i++) {
-               val = _mt7620_mii_read(gsw, i, 0x0);
-               val |= BIT(11);
-               _mt7620_mii_write(gsw, i, 0x0, val);
-       }
-
-       /* reset the switch */
-       mt7530_mdio_w32(gsw, 0x7000, 0x3);
-       usleep_range(10, 20);
-
-       if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
-               /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
-               mtk_switch_w32(gsw, 0x2305e30b, GSW_REG_MAC_P0_MCR);
-               mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
-       } else {
-               /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
-               mtk_switch_w32(gsw, 0x2305e33b, GSW_REG_MAC_P0_MCR);
-               mt7530_mdio_w32(gsw, 0x3600, 0x5e33b);
-       }
-
-       /* (GE2, Link down) */
-       mtk_switch_w32(gsw, 0x8000, GSW_REG_MAC_P1_MCR);
-
-       /* Set switch max RX frame length to 2k */
-       mt7530_mdio_w32(gsw, GSW_REG_GMACCR, 0x3F0B);
-
-       /* Enable Port 6, P5 as GMAC5, P5 disable */
-       val = mt7530_mdio_r32(gsw, 0x7804);
-       val &= ~BIT(8);
-       val |= BIT(6) | BIT(13) | BIT(16);
-       mt7530_mdio_w32(gsw, 0x7804, val);
-
-       val = rt_sysc_r32(0x10);
-       val = (val >> 6) & 0x7;
-       if (val >= 6) {
-               /* 25Mhz Xtal - do nothing */
-       } else if (val >= 3) {
-               /* 40Mhz */
-
-               /* disable MT7530 core clock */
-               _mt7620_mii_write(gsw, 0, 13, 0x1f);
-               _mt7620_mii_write(gsw, 0, 14, 0x410);
-               _mt7620_mii_write(gsw, 0, 13, 0x401f);
-               _mt7620_mii_write(gsw, 0, 14, 0x0);
-
-               /* disable MT7530 PLL */
-               _mt7620_mii_write(gsw, 0, 13, 0x1f);
-               _mt7620_mii_write(gsw, 0, 14, 0x40d);
-               _mt7620_mii_write(gsw, 0, 13, 0x401f);
-               _mt7620_mii_write(gsw, 0, 14, 0x2020);
-
-               /* for MT7530 core clock = 500Mhz */
-               _mt7620_mii_write(gsw, 0, 13, 0x1f);
-               _mt7620_mii_write(gsw, 0, 14, 0x40e);
-               _mt7620_mii_write(gsw, 0, 13, 0x401f);
-               _mt7620_mii_write(gsw, 0, 14, 0x119);
-
-               /* enable MT7530 PLL */
-               _mt7620_mii_write(gsw, 0, 13, 0x1f);
-               _mt7620_mii_write(gsw, 0, 14, 0x40d);
-               _mt7620_mii_write(gsw, 0, 13, 0x401f);
-               _mt7620_mii_write(gsw, 0, 14, 0x2820);
-
-               usleep_range(20, 40);
-
-               /* enable MT7530 core clock */
-               _mt7620_mii_write(gsw, 0, 13, 0x1f);
-               _mt7620_mii_write(gsw, 0, 14, 0x410);
-               _mt7620_mii_write(gsw, 0, 13, 0x401f);
-       } else {
-               /* 20Mhz Xtal - TODO */
-       }
-
-       /* RGMII */
-       _mt7620_mii_write(gsw, 0, 14, 0x1);
-
-       /* set MT7530 central align */
-       val = mt7530_mdio_r32(gsw, 0x7830);
-       val &= ~BIT(0);
-       val |= BIT(1);
-       mt7530_mdio_w32(gsw, 0x7830, val);
-       val = mt7530_mdio_r32(gsw, 0x7a40);
-       val &= ~BIT(30);
-       mt7530_mdio_w32(gsw, 0x7a40, val);
-       mt7530_mdio_w32(gsw, 0x7a78, 0x855);
-
-       /* delay setting for 10/1000M */
-       mt7530_mdio_w32(gsw, 0x7b00, 0x102);
-       mt7530_mdio_w32(gsw, 0x7b04, 0x14);
-
-       /* lower Tx Driving*/
-       mt7530_mdio_w32(gsw, 0x7a54, 0x44);
-       mt7530_mdio_w32(gsw, 0x7a5c, 0x44);
-       mt7530_mdio_w32(gsw, 0x7a64, 0x44);
-       mt7530_mdio_w32(gsw, 0x7a6c, 0x44);
-       mt7530_mdio_w32(gsw, 0x7a74, 0x44);
-       mt7530_mdio_w32(gsw, 0x7a7c, 0x44);
-
-       /* turn on all PHYs */
-       for (i = 0; i <= 4; i++) {
-               val = _mt7620_mii_read(gsw, i, 0);
-               val &= ~BIT(11);
-               _mt7620_mii_write(gsw, i, 0, val);
-       }
-
-       /* enable irq */
-       val = mt7530_mdio_r32(gsw, 0x7808);
-       val |= 3 << 16;
-       mt7530_mdio_w32(gsw, 0x7808, val);
-}
-
-static const struct of_device_id mediatek_gsw_match[] = {
-       { .compatible = "mediatek,mt7621-gsw" },
-       {},
-};
-MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
-
-int mtk_gsw_init(struct fe_priv *priv)
-{
-       struct device_node *np = priv->switch_np;
-       struct platform_device *pdev = of_find_device_by_node(np);
-       struct mt7620_gsw *gsw;
-
-       if (!pdev)
-               return -ENODEV;
-
-       if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
-               return -EINVAL;
-
-       gsw = platform_get_drvdata(pdev);
-       priv->soc->swpriv = gsw;
-
-       mt7621_hw_init(gsw, np);
-
-       if (gsw->irq) {
-               request_irq(gsw->irq, gsw_interrupt_mt7621, 0,
-                           "gsw", priv);
-               mt7530_mdio_w32(gsw, 0x7008, 0x1f);
-       }
-
-       return 0;
-}
-
-static int mt7621_gsw_probe(struct platform_device *pdev)
-{
-       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-       const char *port4 = NULL;
-       struct mt7620_gsw *gsw;
-       struct device_node *np;
-
-       gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
-       if (!gsw)
-               return -ENOMEM;
-
-       gsw->base = devm_ioremap_resource(&pdev->dev, res);
-       if (!gsw->base)
-               return -EADDRNOTAVAIL;
-
-       gsw->dev = &pdev->dev;
-
-       of_property_read_string(np, "mediatek,port4", &port4);
-       if (port4 && !strcmp(port4, "ephy"))
-               gsw->port4 = PORT4_EPHY;
-       else if (port4 && !strcmp(port4, "gmac"))
-               gsw->port4 = PORT4_EXT;
-       else
-               gsw->port4 = PORT4_EPHY;
-
-       gsw->irq = platform_get_irq(pdev, 0);
-
-       platform_set_drvdata(pdev, gsw);
-
-       return 0;
-}
-
-static int mt7621_gsw_remove(struct platform_device *pdev)
-{
-       platform_set_drvdata(pdev, NULL);
-
-       return 0;
-}
-
-static struct platform_driver gsw_driver = {
-       .probe = mt7621_gsw_probe,
-       .remove = mt7621_gsw_remove,
-       .driver = {
-               .name = "mt7621-gsw",
-               .owner = THIS_MODULE,
-               .of_match_table = mediatek_gsw_match,
-       },
-};
-
-module_platform_driver(gsw_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7621 SoC");
-MODULE_VERSION(MTK_FE_DRV_VERSION);
diff --git a/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mdio.c b/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mdio.c
deleted file mode 100644 (file)
index d3798bb..0000000
+++ /dev/null
@@ -1,259 +0,0 @@
-/*   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; version 2 of the License
- *
- *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
- *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
- *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/phy.h>
-#include <linux/of_net.h>
-#include <linux/of_mdio.h>
-
-#include "mtk_eth_soc.h"
-#include "mdio.h"
-
-static int fe_mdio_reset(struct mii_bus *bus)
-{
-       /* TODO */
-       return 0;
-}
-
-static void fe_phy_link_adjust(struct net_device *dev)
-{
-       struct fe_priv *priv = netdev_priv(dev);
-       unsigned long flags;
-       int i;
-
-       spin_lock_irqsave(&priv->phy->lock, flags);
-       for (i = 0; i < 8; i++) {
-               if (priv->phy->phy_node[i]) {
-                       struct phy_device *phydev = priv->phy->phy[i];
-                       int status_change = 0;
-
-                       if (phydev->link)
-                               if (priv->phy->duplex[i] != phydev->duplex ||
-                                   priv->phy->speed[i] != phydev->speed)
-                                       status_change = 1;
-
-                       if (phydev->link != priv->link[i])
-                               status_change = 1;
-
-                       switch (phydev->speed) {
-                       case SPEED_1000:
-                       case SPEED_100:
-                       case SPEED_10:
-                               priv->link[i] = phydev->link;
-                               priv->phy->duplex[i] = phydev->duplex;
-                               priv->phy->speed[i] = phydev->speed;
-
-                               if (status_change &&
-                                   priv->soc->mdio_adjust_link)
-                                       priv->soc->mdio_adjust_link(priv, i);
-                               break;
-                       }
-               }
-       }
-}
-
-int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
-{
-       const __be32 *_port = NULL;
-       struct phy_device *phydev;
-       int phy_mode, port;
-
-       _port = of_get_property(phy_node, "reg", NULL);
-
-       if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
-               pr_err("%s: invalid port id\n", phy_node->name);
-               return -EINVAL;
-       }
-       port = be32_to_cpu(*_port);
-       phy_mode = of_get_phy_mode(phy_node);
-       if (phy_mode < 0) {
-               dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
-               priv->phy->phy_node[port] = NULL;
-               return -EINVAL;
-       }
-
-       phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
-                               0, phy_mode);
-       if (IS_ERR(phydev)) {
-               dev_err(priv->device, "could not connect to PHY\n");
-               priv->phy->phy_node[port] = NULL;
-               return PTR_ERR(phydev);
-       }
-
-       phydev->supported &= PHY_GBIT_FEATURES;
-       phydev->advertising = phydev->supported;
-       phydev->no_auto_carrier_off = 1;
-
-       dev_info(priv->device,
-                "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
-                port, dev_name(&phydev->mdio.dev), phydev->phy_id,
-                phydev->drv->name);
-
-       priv->phy->phy[port] = phydev;
-       priv->link[port] = 0;
-
-       return 0;
-}
-
-static void phy_init(struct fe_priv *priv, struct phy_device *phy)
-{
-       phy_attach(priv->netdev, dev_name(&phy->mdio.dev), PHY_INTERFACE_MODE_MII);
-
-       phy->autoneg = AUTONEG_ENABLE;
-       phy->speed = 0;
-       phy->duplex = 0;
-       phy->supported &= PHY_BASIC_FEATURES;
-       phy->advertising = phy->supported | ADVERTISED_Autoneg;
-
-       phy_start_aneg(phy);
-}
-
-static int fe_phy_connect(struct fe_priv *priv)
-{
-       int i;
-
-       for (i = 0; i < 8; i++) {
-               if (priv->phy->phy_node[i]) {
-                       if (!priv->phy_dev) {
-                               priv->phy_dev = priv->phy->phy[i];
-                               priv->phy_flags = FE_PHY_FLAG_PORT;
-                       }
-               } else if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, i)) {
-                       phy_init(priv, mdiobus_get_phy(priv->mii_bus, i));
-                       if (!priv->phy_dev) {
-                               priv->phy_dev = mdiobus_get_phy(priv->mii_bus, i);
-                               priv->phy_flags = FE_PHY_FLAG_ATTACH;
-                       }
-               }
-       }
-
-       return 0;
-}
-
-static void fe_phy_disconnect(struct fe_priv *priv)
-{
-       unsigned long flags;
-       int i;
-
-       for (i = 0; i < 8; i++)
-               if (priv->phy->phy_fixed[i]) {
-                       spin_lock_irqsave(&priv->phy->lock, flags);
-                       priv->link[i] = 0;
-                       if (priv->soc->mdio_adjust_link)
-                               priv->soc->mdio_adjust_link(priv, i);
-                       spin_unlock_irqrestore(&priv->phy->lock, flags);
-               } else if (priv->phy->phy[i]) {
-                       phy_disconnect(priv->phy->phy[i]);
-               } else if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, i)) {
-                       phy_detach(mdiobus_get_phy(priv->mii_bus, i));
-               }
-}
-
-static void fe_phy_start(struct fe_priv *priv)
-{
-       unsigned long flags;
-       int i;
-
-       for (i = 0; i < 8; i++) {
-               if (priv->phy->phy_fixed[i]) {
-                       spin_lock_irqsave(&priv->phy->lock, flags);
-                       priv->link[i] = 1;
-                       if (priv->soc->mdio_adjust_link)
-                               priv->soc->mdio_adjust_link(priv, i);
-                       spin_unlock_irqrestore(&priv->phy->lock, flags);
-               } else if (priv->phy->phy[i]) {
-                       phy_start(priv->phy->phy[i]);
-               }
-       }
-}
-
-static void fe_phy_stop(struct fe_priv *priv)
-{
-       unsigned long flags;
-       int i;
-
-       for (i = 0; i < 8; i++)
-               if (priv->phy->phy_fixed[i]) {
-                       spin_lock_irqsave(&priv->phy->lock, flags);
-                       priv->link[i] = 0;
-                       if (priv->soc->mdio_adjust_link)
-                               priv->soc->mdio_adjust_link(priv, i);
-                       spin_unlock_irqrestore(&priv->phy->lock, flags);
-               } else if (priv->phy->phy[i]) {
-                       phy_stop(priv->phy->phy[i]);
-               }
-}
-
-static struct fe_phy phy_ralink = {
-       .connect = fe_phy_connect,
-       .disconnect = fe_phy_disconnect,
-       .start = fe_phy_start,
-       .stop = fe_phy_stop,
-};
-
-int fe_mdio_init(struct fe_priv *priv)
-{
-       struct device_node *mii_np;
-       int err;
-
-       if (!priv->soc->mdio_read || !priv->soc->mdio_write)
-               return 0;
-
-       spin_lock_init(&phy_ralink.lock);
-       priv->phy = &phy_ralink;
-
-       mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
-       if (!mii_np) {
-               dev_err(priv->device, "no %s child node found", "mdio-bus");
-               return -ENODEV;
-       }
-
-       if (!of_device_is_available(mii_np)) {
-               err = 0;
-               goto err_put_node;
-       }
-
-       priv->mii_bus = mdiobus_alloc();
-       if (!priv->mii_bus) {
-               err = -ENOMEM;
-               goto err_put_node;
-       }
-
-       priv->mii_bus->name = "mdio";
-       priv->mii_bus->read = priv->soc->mdio_read;
-       priv->mii_bus->write = priv->soc->mdio_write;
-       priv->mii_bus->reset = fe_mdio_reset;
-       priv->mii_bus->priv = priv;
-       priv->mii_bus->parent = priv->device;
-
-       snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
-       err = of_mdiobus_register(priv->mii_bus, mii_np);
-       if (err)
-               goto err_free_bus;
-
-       return 0;
-
-err_free_bus:
-       kfree(priv->mii_bus);
-err_put_node:
-       of_node_put(mii_np);
-       priv->mii_bus = NULL;
-       return err;
-}
-
-void fe_mdio_cleanup(struct fe_priv *priv)
-{
-       if (!priv->mii_bus)
-               return;
-
-       mdiobus_unregister(priv->mii_bus);
-       of_node_put(priv->mii_bus->dev.of_node);
-       kfree(priv->mii_bus);
-}
diff --git a/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mdio.h b/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mdio.h
deleted file mode 100644 (file)
index 498cf14..0000000
+++ /dev/null
@@ -1,27 +0,0 @@
-/*   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; version 2 of the License
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
- *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
- *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
- */
-
-#ifndef _RALINK_MDIO_H__
-#define _RALINK_MDIO_H__
-
-#ifdef CONFIG_NET_MEDIATEK_MDIO
-int fe_mdio_init(struct fe_priv *priv);
-void fe_mdio_cleanup(struct fe_priv *priv);
-int fe_connect_phy_node(struct fe_priv *priv,
-                       struct device_node *phy_node);
-#else
-static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
-static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
-#endif
-#endif
diff --git a/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mdio_mt7620.c b/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mdio_mt7620.c
deleted file mode 100644 (file)
index 9efe789..0000000
+++ /dev/null
@@ -1,168 +0,0 @@
-/*   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; version 2 of the License
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
- *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
- *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-#include "mtk_eth_soc.h"
-#include "gsw_mt7620.h"
-#include "mdio.h"
-
-static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
-{
-       unsigned long t_start = jiffies;
-
-       while (1) {
-               if (!(mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
-                       return 0;
-               if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT))
-                       break;
-       }
-
-       dev_err(gsw->dev, "mdio: MDIO timeout\n");
-       return -1;
-}
-
-u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
-                            u32 phy_register, u32 write_data)
-{
-       if (mt7620_mii_busy_wait(gsw))
-               return -1;
-
-       write_data &= 0xffff;
-
-       mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
-               (phy_register << GSW_MDIO_REG_SHIFT) |
-               (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
-               MT7620A_GSW_REG_PIAC);
-
-       if (mt7620_mii_busy_wait(gsw))
-               return -1;
-
-       return 0;
-}
-
-u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
-{
-       u32 d;
-
-       if (mt7620_mii_busy_wait(gsw))
-               return 0xffff;
-
-       mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
-               (phy_reg << GSW_MDIO_REG_SHIFT) |
-               (phy_addr << GSW_MDIO_ADDR_SHIFT),
-               MT7620A_GSW_REG_PIAC);
-
-       if (mt7620_mii_busy_wait(gsw))
-               return 0xffff;
-
-       d = mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
-
-       return d;
-}
-
-int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
-{
-       struct fe_priv *priv = bus->priv;
-       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
-
-       return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
-}
-
-int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
-{
-       struct fe_priv *priv = bus->priv;
-       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
-
-       return _mt7620_mii_read(gsw, phy_addr, phy_reg);
-}
-
-void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val)
-{
-       _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
-       _mt7620_mii_write(gsw, 0x1f, (reg >> 2) & 0xf,  val & 0xffff);
-       _mt7620_mii_write(gsw, 0x1f, 0x10, val >> 16);
-}
-
-u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg)
-{
-       u16 high, low;
-
-       _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
-       low = _mt7620_mii_read(gsw, 0x1f, (reg >> 2) & 0xf);
-       high = _mt7620_mii_read(gsw, 0x1f, 0x10);
-
-       return (high << 16) | (low & 0xffff);
-}
-
-static unsigned char *fe_speed_str(int speed)
-{
-       switch (speed) {
-       case 2:
-       case SPEED_1000:
-               return "1000";
-       case 1:
-       case SPEED_100:
-               return "100";
-       case 0:
-       case SPEED_10:
-               return "10";
-       }
-
-       return "? ";
-}
-
-int mt7620_has_carrier(struct fe_priv *priv)
-{
-       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
-       int i;
-
-       for (i = 0; i < GSW_PORT6; i++)
-               if (mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
-                       return 1;
-       return 0;
-}
-
-
-void mt7620_handle_carrier(struct fe_priv *priv)
-{
-       if (!priv->phy)
-               return;
-
-       if (mt7620_has_carrier(priv))
-               netif_carrier_on(priv->netdev);
-       else
-               netif_carrier_off(priv->netdev);
-}
-
-void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
-                            int speed, int duplex)
-{
-       if (link)
-               netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
-                           port, fe_speed_str(speed),
-                           (duplex) ? "Full" : "Half");
-       else
-               netdev_info(priv->netdev, "port %d link down\n", port);
-}
-
-void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
-{
-       mt7620_print_link_state(priv, port, priv->link[port],
-                               priv->phy->speed[port],
-                               (priv->phy->duplex[port] == DUPLEX_FULL));
-       mt7620_handle_carrier(priv);
-}
diff --git a/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mdio_rt2880.c b/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mdio_rt2880.c
deleted file mode 100644 (file)
index e72f8c7..0000000
+++ /dev/null
@@ -1,222 +0,0 @@
-/*   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; version 2 of the License
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
- *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
- *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/of_net.h>
-#include <linux/of_mdio.h>
-
-#include "mtk_eth_soc.h"
-#include "mdio_rt2880.h"
-#include "mdio.h"
-
-#define FE_MDIO_RETRY  1000
-
-static unsigned char *rt2880_speed_str(struct fe_priv *priv)
-{
-       switch (priv->phy->speed[0]) {
-       case SPEED_1000:
-               return "1000";
-       case SPEED_100:
-               return "100";
-       case SPEED_10:
-               return "10";
-       }
-
-       return "?";
-}
-
-void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
-{
-       u32 mdio_cfg;
-
-       if (!priv->link[0]) {
-               netif_carrier_off(priv->netdev);
-               netdev_info(priv->netdev, "link down\n");
-               return;
-       }
-
-       mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
-                  FE_MDIO_CFG_RX_CLK_SKEW_200 |
-                  FE_MDIO_CFG_GP1_FRC_EN;
-
-       if (priv->phy->duplex[0] == DUPLEX_FULL)
-               mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
-
-       if (priv->phy->tx_fc[0])
-               mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
-
-       if (priv->phy->rx_fc[0])
-               mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
-
-       switch (priv->phy->speed[0]) {
-       case SPEED_10:
-               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
-               break;
-       case SPEED_100:
-               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
-               break;
-       case SPEED_1000:
-               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
-               break;
-       default:
-               BUG();
-       }
-
-       fe_w32(mdio_cfg, FE_MDIO_CFG);
-
-       netif_carrier_on(priv->netdev);
-       netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
-                   rt2880_speed_str(priv),
-                   (priv->phy->duplex[0] == DUPLEX_FULL) ? "Full" : "Half");
-}
-
-static int rt2880_mdio_wait_ready(struct fe_priv *priv)
-{
-       int retries;
-
-       retries = FE_MDIO_RETRY;
-       while (1) {
-               u32 t;
-
-               t = fe_r32(FE_MDIO_ACCESS);
-               if ((t & BIT(31)) == 0)
-                       return 0;
-
-               if (retries-- == 0)
-                       break;
-
-               udelay(1);
-       }
-
-       dev_err(priv->device, "MDIO operation timed out\n");
-       return -ETIMEDOUT;
-}
-
-int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
-{
-       struct fe_priv *priv = bus->priv;
-       int err;
-       u32 t;
-
-       err = rt2880_mdio_wait_ready(priv);
-       if (err)
-               return 0xffff;
-
-       t = (phy_addr << 24) | (phy_reg << 16);
-       fe_w32(t, FE_MDIO_ACCESS);
-       t |= BIT(31);
-       fe_w32(t, FE_MDIO_ACCESS);
-
-       err = rt2880_mdio_wait_ready(priv);
-       if (err)
-               return 0xffff;
-
-       pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
-                phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
-
-       return fe_r32(FE_MDIO_ACCESS) & 0xffff;
-}
-
-int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
-{
-       struct fe_priv *priv = bus->priv;
-       int err;
-       u32 t;
-
-       pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
-                phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
-
-       err = rt2880_mdio_wait_ready(priv);
-       if (err)
-               return err;
-
-       t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
-       fe_w32(t, FE_MDIO_ACCESS);
-       t |= BIT(31);
-       fe_w32(t, FE_MDIO_ACCESS);
-
-       return rt2880_mdio_wait_ready(priv);
-}
-
-void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
-{
-       const __be32 *id = of_get_property(np, "reg", NULL);
-       const __be32 *link;
-       int size;
-       int phy_mode;
-
-       if (!id || (be32_to_cpu(*id) != 0)) {
-               pr_err("%s: invalid port id\n", np->name);
-               return;
-       }
-
-       priv->phy->phy_fixed[0] = of_get_property(np,
-                                                 "mediatek,fixed-link", &size);
-       if (priv->phy->phy_fixed[0] &&
-           (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
-               pr_err("%s: invalid fixed link property\n", np->name);
-               priv->phy->phy_fixed[0] = NULL;
-               return;
-       }
-
-       phy_mode = of_get_phy_mode(np);
-       switch (phy_mode) {
-       case PHY_INTERFACE_MODE_RGMII:
-               break;
-       case PHY_INTERFACE_MODE_MII:
-               break;
-       case PHY_INTERFACE_MODE_RMII:
-               break;
-       default:
-               if (!priv->phy->phy_fixed[0])
-                       dev_err(priv->device, "port %d - invalid phy mode\n",
-                               priv->phy->speed[0]);
-               break;
-       }
-
-       priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
-       if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
-               return;
-
-       if (priv->phy->phy_fixed[0]) {
-               link = priv->phy->phy_fixed[0];
-               priv->phy->speed[0] = be32_to_cpup(link++);
-               priv->phy->duplex[0] = be32_to_cpup(link++);
-               priv->phy->tx_fc[0] = be32_to_cpup(link++);
-               priv->phy->rx_fc[0] = be32_to_cpup(link++);
-
-               priv->link[0] = 1;
-               switch (priv->phy->speed[0]) {
-               case SPEED_10:
-                       break;
-               case SPEED_100:
-                       break;
-               case SPEED_1000:
-                       break;
-               default:
-                       dev_err(priv->device, "invalid link speed: %d\n",
-                               priv->phy->speed[0]);
-                       priv->phy->phy_fixed[0] = 0;
-                       return;
-               }
-               dev_info(priv->device, "using fixed link parameters\n");
-               rt2880_mdio_link_adjust(priv, 0);
-               return;
-       }
-
-       if (priv->phy->phy_node[0] && mdiobus_get_phy(priv->mii_bus, 0))
-               fe_connect_phy_node(priv, priv->phy->phy_node[0]);
-}
diff --git a/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mdio_rt2880.h b/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mdio_rt2880.h
deleted file mode 100644 (file)
index 70e3442..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-/*   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; version 2 of the License
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
- *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
- *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
- */
-
-#ifndef _RALINK_MDIO_RT2880_H__
-#define _RALINK_MDIO_RT2880_H__
-
-void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
-int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
-int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
-void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
-
-#endif
diff --git a/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mt7530.c b/target/linux/ramips/files-4.9/drivers/net/ethernet/mtk/mt7530.c
deleted file mode 100644 (file)
index 5216cb5..0000000
+++ /dev/null
@@ -1,979 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
- * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
- */
-
-#include <linux/if.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/if_ether.h>
-#include <linux/skbuff.h>
-#include <linux/netdevice.h>
-#include <linux/netlink.h>
-#include <linux/bitops.h>
-#include <net/genetlink.h>
-#include <linux/switch.h>
-#include <linux/delay.h>
-#include <linux/phy.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/lockdep.h>
-#include <linux/workqueue.h>
-#include <linux/of_device.h>
-
-#include "mt7530.h"
-
-#define MT7530_CPU_PORT                6
-#define MT7530_NUM_PORTS       8
-#ifdef CONFIG_SOC_MT7621
-#define MT7530_NUM_VLANS       4095
-#else
-#define MT7530_NUM_VLANS       16
-#endif
-#define MT7530_MAX_VID         4095
-#define MT7530_MIN_VID         0
-
-#define MT7530_PORT_MIB_TXB_ID 2       /* TxGOC */
-#define MT7530_PORT_MIB_RXB_ID 6       /* RxGOC */
-
-#define MT7621_PORT_MIB_TXB_ID 18      /* TxByte */
-#define MT7621_PORT_MIB_RXB_ID 37      /* RxByte */
-
-/* registers */
-#define REG_ESW_VLAN_VTCR              0x90
-#define REG_ESW_VLAN_VAWD1             0x94
-#define REG_ESW_VLAN_VAWD2             0x98
-#define REG_ESW_VLAN_VTIM(x)   (0x100 + 4 * ((x) / 2))
-
-#define REG_ESW_VLAN_VAWD1_IVL_MAC     BIT(30)
-#define REG_ESW_VLAN_VAWD1_VTAG_EN     BIT(28)
-#define REG_ESW_VLAN_VAWD1_VALID       BIT(0)
-
-/* vlan egress mode */
-enum {
-       ETAG_CTRL_UNTAG = 0,
-       ETAG_CTRL_TAG   = 2,
-       ETAG_CTRL_SWAP  = 1,
-       ETAG_CTRL_STACK = 3,
-};
-
-#define REG_ESW_PORT_PCR(x)    (0x2004 | ((x) << 8))
-#define REG_ESW_PORT_PVC(x)    (0x2010 | ((x) << 8))
-#define REG_ESW_PORT_PPBV1(x)  (0x2014 | ((x) << 8))
-
-#define REG_HWTRAP             0x7804
-
-#define MIB_DESC(_s , _o, _n)   \
-       {                       \
-               .size = (_s),   \
-               .offset = (_o), \
-               .name = (_n),   \
-       }
-
-struct mt7xxx_mib_desc {
-       unsigned int size;
-       unsigned int offset;
-       const char *name;
-};
-
-static const struct mt7xxx_mib_desc mt7620_mibs[] = {
-       MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT0, "PPE_AC_BCNT0"),
-       MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT0, "PPE_AC_PCNT0"),
-       MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT63, "PPE_AC_BCNT63"),
-       MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT63, "PPE_AC_PCNT63"),
-       MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT0, "PPE_MTR_CNT0"),
-       MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT63, "PPE_MTR_CNT63"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GBCNT, "GDM1_TX_GBCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GPCNT, "GDM1_TX_GPCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_SKIPCNT, "GDM1_TX_SKIPCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_COLCNT, "GDM1_TX_COLCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GBCNT1, "GDM1_RX_GBCNT1"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GPCNT1, "GDM1_RX_GPCNT1"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_OERCNT, "GDM1_RX_OERCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FERCNT, "GDM1_RX_FERCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_SERCNT, "GDM1_RX_SERCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_LERCNT, "GDM1_RX_LERCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_CERCNT, "GDM1_RX_CERCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FCCNT, "GDM1_RX_FCCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GBCNT, "GDM2_TX_GBCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GPCNT, "GDM2_TX_GPCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_SKIPCNT, "GDM2_TX_SKIPCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_COLCNT, "GDM2_TX_COLCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GBCNT, "GDM2_RX_GBCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GPCNT, "GDM2_RX_GPCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_OERCNT, "GDM2_RX_OERCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FERCNT, "GDM2_RX_FERCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_SERCNT, "GDM2_RX_SERCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_LERCNT, "GDM2_RX_LERCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_CERCNT, "GDM2_RX_CERCNT"),
-       MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FCCNT, "GDM2_RX_FCCNT")
-};
-
-static const struct mt7xxx_mib_desc mt7620_port_mibs[] = {
-       MIB_DESC(1, MT7620_MIB_STATS_PORT_TGPCN,  "TxGPC"),
-       MIB_DESC(1, MT7620_MIB_STATS_PORT_TBOCN,  "TxBOC"),
-       MIB_DESC(1, MT7620_MIB_STATS_PORT_TGOCN,  "TxGOC"),
-       MIB_DESC(1, MT7620_MIB_STATS_PORT_TEPCN,  "TxEPC"),
-       MIB_DESC(1, MT7620_MIB_STATS_PORT_RGPCN,  "RxGPC"),
-       MIB_DESC(1, MT7620_MIB_STATS_PORT_RBOCN,  "RxBOC"),
-       MIB_DESC(1, MT7620_MIB_STATS_PORT_RGOCN,  "RxGOC"),
-       MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC1N, "RxEPC1"),
-       MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC2N, "RxEPC2")
-};
-
-static const struct mt7xxx_mib_desc mt7621_mibs[] = {
-       MIB_DESC(1, MT7621_STATS_TDPC, "TxDrop"),
-       MIB_DESC(1, MT7621_STATS_TCRC, "TxCRC"),
-       MIB_DESC(1, MT7621_STATS_TUPC, "TxUni"),
-       MIB_DESC(1, MT7621_STATS_TMPC, "TxMulti"),
-       MIB_DESC(1, MT7621_STATS_TBPC, "TxBroad"),
-       MIB_DESC(1, MT7621_STATS_TCEC, "TxCollision"),
-       MIB_DESC(1, MT7621_STATS_TSCEC, "TxSingleCol"),
-       MIB_DESC(1, MT7621_STATS_TMCEC, "TxMultiCol"),
-       MIB_DESC(1, MT7621_STATS_TDEC, "TxDefer"),
-       MIB_DESC(1, MT7621_STATS_TLCEC, "TxLateCol"),
-       MIB_DESC(1, MT7621_STATS_TXCEC, "TxExcCol"),
-       MIB_DESC(1, MT7621_STATS_TPPC, "TxPause"),
-       MIB_DESC(1, MT7621_STATS_TL64PC, "Tx64Byte"),
-       MIB_DESC(1, MT7621_STATS_TL65PC, "Tx65Byte"),
-       MIB_DESC(1, MT7621_STATS_TL128PC, "Tx128Byte"),
-       MIB_DESC(1, MT7621_STATS_TL256PC, "Tx256Byte"),
-       MIB_DESC(1, MT7621_STATS_TL512PC, "Tx512Byte"),
-       MIB_DESC(1, MT7621_STATS_TL1024PC, "Tx1024Byte"),
-       MIB_DESC(2, MT7621_STATS_TOC, "TxByte"),
-       MIB_DESC(1, MT7621_STATS_RDPC, "RxDrop"),
-       MIB_DESC(1, MT7621_STATS_RFPC, "RxFiltered"),
-       MIB_DESC(1, MT7621_STATS_RUPC, "RxUni"),
-       MIB_DESC(1, MT7621_STATS_RMPC, "RxMulti"),
-       MIB_DESC(1, MT7621_STATS_RBPC, "RxBroad"),
-       MIB_DESC(1, MT7621_STATS_RAEPC, "RxAlignErr"),
-       MIB_DESC(1, MT7621_STATS_RCEPC, "RxCRC"),
-       MIB_DESC(1, MT7621_STATS_RUSPC, "RxUnderSize"),
-       MIB_DESC(1, MT7621_STATS_RFEPC, "RxFragment"),
-       MIB_DESC(1, MT7621_STATS_ROSPC, "RxOverSize"),
-       MIB_DESC(1, MT7621_STATS_RJEPC, "RxJabber"),
-       MIB_DESC(1, MT7621_STATS_RPPC, "RxPause"),
-       MIB_DESC(1, MT7621_STATS_RL64PC, "Rx64Byte"),
-       MIB_DESC(1, MT7621_STATS_RL65PC, "Rx65Byte"),
-       MIB_DESC(1, MT7621_STATS_RL128PC, "Rx128Byte"),
-       MIB_DESC(1, MT7621_STATS_RL256PC, "Rx256Byte"),
-       MIB_DESC(1, MT7621_STATS_RL512PC, "Rx512Byte"),
-       MIB_DESC(1, MT7621_STATS_RL1024PC, "Rx1024Byte"),
-       MIB_DESC(2, MT7621_STATS_ROC, "RxByte"),
-       MIB_DESC(1, MT7621_STATS_RDPC_CTRL, "RxCtrlDrop"),
-       MIB_DESC(1, MT7621_STATS_RDPC_ING, "RxIngDrop"),
-       MIB_DESC(1, MT7621_STATS_RDPC_ARL, "RxARLDrop")
-};
-
-enum {
-       /* Global attributes. */
-       MT7530_ATTR_ENABLE_VLAN,
-};
-
-struct mt7530_port_entry {
-       u16     pvid;
-};
-
-struct mt7530_vlan_entry {
-       u16     vid;
-       u8      member;
-       u8      etags;
-};
-
-struct mt7530_priv {
-       void __iomem            *base;
-       struct mii_bus          *bus;
-       struct switch_dev       swdev;
-
-       bool                    global_vlan_enable;
-       struct mt7530_vlan_entry        vlan_entries[MT7530_NUM_VLANS];
-       struct mt7530_port_entry        port_entries[MT7530_NUM_PORTS];
-};
-
-struct mt7530_mapping {
-       char    *name;
-       u16     pvids[MT7530_NUM_PORTS];
-       u8      members[MT7530_NUM_VLANS];
-       u8      etags[MT7530_NUM_VLANS];
-       u16     vids[MT7530_NUM_VLANS];
-} mt7530_defaults[] = {
-       {
-               .name = "llllw",
-               .pvids = { 1, 1, 1, 1, 2, 1, 1 },
-               .members = { 0, 0x6f, 0x50 },
-               .etags = { 0, 0x40, 0x40 },
-               .vids = { 0, 1, 2 },
-       }, {
-               .name = "wllll",
-               .pvids = { 2, 1, 1, 1, 1, 1, 1 },
-               .members = { 0, 0x7e, 0x41 },
-               .etags = { 0, 0x40, 0x40 },
-               .vids = { 0, 1, 2 },
-       }, {
-               .name = "lwlll",
-               .pvids = { 1, 2, 1, 1, 1, 1, 1 },
-               .members = { 0, 0x7d, 0x42 },
-               .etags = { 0, 0x40, 0x40 },
-               .vids = { 0, 1, 2 },
-       },
-};
-
-struct mt7530_mapping*
-mt7530_find_mapping(struct device_node *np)
-{
-       const char *map;
-       int i;
-
-       if (of_property_read_string(np, "mediatek,portmap", &map))
-               return NULL;
-
-       for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
-               if (!strcmp(map, mt7530_defaults[i].name))
-                       return &mt7530_defaults[i];
-
-       return NULL;
-}
-
-static void
-mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
-{
-       int i = 0;
-
-       for (i = 0; i < MT7530_NUM_PORTS; i++)
-               mt7530->port_entries[i].pvid = map->pvids[i];
-
-       for (i = 0; i < MT7530_NUM_VLANS; i++) {
-      &n