+++ /dev/null
-menu "Configuration"
- depends on PACKAGE_kmod-ifxmips-dsl-api
-
-choice
- prompt "Firmware"
- default IFXMIPS_ANNEX_B
- help
- This option controls which firmware is loaded
-
-config IFXMIPS_ANNEX_A
- bool "Annex-A"
- help
- Annex-A
-
-config IFXMIPS_ANNEX_B
- bool "Annex-B"
- help
- Annex-B
-
-endchoice
-
-#config IFXMIPS_DSL_FIRMWARE
-# bool "ifxmips-dsl firmware extractor"
-# default y
-# help
-# Say Y, if you need ifxmips-dsl to auto extract the firmware for you from the a800 firmware image
-
-config IFXMIPS_DSL_DEBUG
- bool "ifxmips-dsl debugging"
- help
- Say Y, if you need ifxmips-dsl to display debug messages.
-
-endmenu
+++ /dev/null
-#
-# Copyright (C) 2009-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-# ralph / blogic
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_NAME:=ifxmips-dsl-api
-PKG_BASE_NAME:=drv_dsl_cpe_api_danube
-PKG_VERSION:=3.24.4.4
-PKG_RELEASE:=2
-PKG_SOURCE:=$(PKG_BASE_NAME)-$(PKG_VERSION).tar.gz
-PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/drv_dsl_cpe_api-$(PKG_VERSION)
-PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources/
-PKG_MD5SUM:=c45bc531c1ed2ac80f68fb986b63bb87
-
-ifeq ($(DUMP),)
- STAMP_CONFIGURED:=$(strip $(STAMP_CONFIGURED))_$(shell $(SH_FUNC) grep '^CONFIG_IFXMIPS_DSL_' $(TOPDIR)/.config | md5s)
-endif
-
-FW_BASE_NAME:=dsl_danube_firmware_adsl
-FW_A_VER:=02.04.04.00.00.01
-FW_B_VER:=02.04.01.07.00.02
-FW_A_FILE_VER:=244001
-FW_B_FILE_VER:=241702
-FW_A_MD5:=f717db3067a0049a26e233ab11238710
-FW_B_MD5:=349de7cd20368f4ac9b7e8322114a512
-
-PATCH_DIR ?= ./patches$(if $(wildcard ./patches-$(KERNEL_PATCHVER)),-$(KERNEL_PATCHVER))
-
-include $(INCLUDE_DIR)/package.mk
-
-define KernelPackage/ifxmips-dsl-api
- SECTION:=sys
- CATEGORY:=Kernel modules
- SUBMENU:=Network Devices
- TITLE:=DSL CPE API driver
- URL:=http://www.infineon.com/
- MAINTAINER:=Infineon Technologies AG / Lantiq / John Crispin <blogic@openwrt.org>
- DEPENDS:=@TARGET_ifxmips +kmod-atm
- FILES:=$(PKG_BUILD_DIR)/src/mei/ifxmips_mei.ko \
- $(PKG_BUILD_DIR)/src/drv_dsl_cpe_api.ko \
- $(PKG_BUILD_DIR)/src/mei/ifxmips_atm.ko
- AUTOLOAD:=$(call AutoLoad,50,ifxmips_mei drv_dsl_cpe_api ifxmips_atm)
- MENU:=1
-endef
-
-define KernelPackage/ifxmips-dsl-api/description
- Infineon DSL CPE API for Amazon SE, Danube and Vinax.
-
- This package contains the DSL CPE API driver for Amazon SE & Danube.
-
- Supported Devices:
- - Amazon SE
- - Danube
-
- This package was kindly contributed to openwrt by Infineon/Lantiq
-endef
-
-define KernelPackage/ifxmips-dsl-api/config
- source "$(SOURCE)/Config.in"
-endef
-
-ifeq ($(CONFIG_IFXMIPS_DSL_FIRMWARE),y)
-FW_FILE:=arcor_A800_452CPW_FW_1.02.206(20081201).bin
-define Download/firmware
- URL:=http://www.arcor.de/hilfe/files/pdf/
- FILE=$(FW_FILE)
- MD5SUM:=19d9af4e369287a0f0abaed415cdac10
-endef
-$(eval $(call Download,firmware))
-
-else
-
-define Download/annex-a
- FILE:=$(FW_BASE_NAME)_a-$(FW_A_VER).tar.gz
- URL:=http://mirror2.openwrt.org/sources/
- MD5SUM:=$(FW_A_MD5)
-endef
-$(eval $(call Download,annex-a))
-
-define Download/annex-b
- FILE:=$(FW_BASE_NAME)_b-$(FW_B_VER).tar.gz
- URL:=http://mirror2.openwrt.org/sources/
- MD5SUM:=$(FW_B_MD5)
-endef
-$(eval $(call Download,annex-b))
-endif
-
-IFX_DSL_MAX_DEVICE=1
-IFX_DSL_LINES_PER_DEVICE=1
-IFX_DSL_CHANNELS_PER_LINE=1
-
-CONFIGURE_ARGS += --enable-kernel-include="$(LINUX_DIR)/include" \
- --with-max-device="$(IFX_DSL_MAX_DEVICE)" \
- --with-lines-per-device="$(IFX_DSL_LINES_PER_DEVICE)" \
- --with-channels-per-line="$(IFX_DSL_CHANNELS_PER_LINE)" \
- --enable-danube \
- --enable-add-drv-cflags="-DMODULE" \
- --disable-dsl-delt-static \
- --disable-adsl-led \
- --enable-dsl-ceoc \
- --enable-dsl-pm \
- --enable-dsl-pm-total \
- --enable-dsl-pm-history \
- --enable-dsl-pm-showtime \
- --enable-dsl-pm-channel-counters \
- --enable-dsl-pm-datapath-counters \
- --enable-dsl-pm-line-counters \
- --enable-dsl-pm-channel-thresholds \
- --enable-dsl-pm-datapath-thresholds \
- --enable-dsl-pm-line-thresholds \
- --enable-dsl-pm-optional-parameters \
- --enable-linux-26 \
- --enable-kernelbuild="$(LINUX_DIR)" \
- ARCH=$(LINUX_KARCH)
-
-EXTRA_CFLAGS = -fno-pic -mno-abicalls -mlong-calls -G 0
-
-ifeq ($(CONFIG_IFXMIPS_DSL_DEBUG),y)
-CONFIGURE_ARGS += \
- --enable-debug=yes \
- --enable-debug-prints=yes
-EXTRA_CFLAGS += -DDEBUG
-endif
-
-define Build/Prepare
- $(PKG_UNPACK)
- $(INSTALL_DIR) $(PKG_BUILD_DIR)/src/mei/
- $(CP) ./src/* $(PKG_BUILD_DIR)/src/mei/
- $(Build/Patch)
-ifeq ($(CONFIG_IFXMIPS_DSL_FIRMWARE),)
- $(TAR) -C $(PKG_BUILD_DIR) -xzf $(DL_DIR)/$(FW_BASE_NAME)_a-$(FW_A_VER).tar.gz
- $(TAR) -C $(PKG_BUILD_DIR) -xzf $(DL_DIR)/$(FW_BASE_NAME)_b-$(FW_B_VER).tar.gz
-endif
-endef
-
-define Build/Configure
- (cd $(PKG_BUILD_DIR); aclocal && autoconf && automake)
- $(call Build/Configure/Default)
-endef
-
-define Build/Compile
- cd $(LINUX_DIR); \
- ARCH=mips CROSS_COMPILE="$(KERNEL_CROSS)" \
- $(MAKE) M=$(PKG_BUILD_DIR)/src/mei/ V=1 modules
- $(call Build/Compile/Default)
-endef
-
-define Build/InstallDev
- $(INSTALL_DIR) $(1)/usr/include
- $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api.h $(1)/usr/include
- $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_ioctl.h $(1)/usr/include
- $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_adslmib.h $(1)/usr/include
- $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_adslmib_ioctl.h $(1)/usr/include
- $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_g997.h $(1)/usr/include
- $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_types.h $(1)/usr/include
- $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_pm.h $(1)/usr/include
- $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_error.h $(1)/usr/include
- $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_danube_ctx.h $(1)/usr/include
- $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_cmv_danube.h $(1)/usr/include
-endef
-
-define KernelPackage/ifxmips-dsl-api/install
- $(INSTALL_DIR) $(1)/lib/firmware/
-ifeq ($(CONFIG_IFXMIPS_DSL_FIRMWARE),y)
- $(PLATFORM_DIR)/extract.sh $(DL_DIR) '$(FW_FILE)'
- $(CP) $(DL_DIR)/dsl_$(if $(CONFIG_IFXMIPS_ANNEX_A),a,b).bin $(1)/lib/firmware/ModemHWE.bin
-else
- $(CP) $(PKG_BUILD_DIR)/$(FW_BASE_NAME)_$(if $(CONFIG_IFXMIPS_ANNEX_A),a_$(FW_A_FILE_VER),b_$(FW_B_FILE_VER)).bin $(1)/lib/firmware/ModemHWE.bin
-endif
-endef
-
-$(eval $(call KernelPackage,ifxmips-dsl-api))
+++ /dev/null
---- a/src/include/drv_dsl_cpe_device_danube.h
-+++ b/src/include/drv_dsl_cpe_device_danube.h
-@@ -24,7 +24,7 @@
- #include "drv_dsl_cpe_simulator_danube.h"
- #else
- /* Include for the low level driver interface header file */
--#include "asm/ifx/ifx_mei_bsp.h"
-+#include "mei/ifxmips_mei_interface.h"
- #endif /* defined(DSL_CPE_SIMULATOR_DRIVER) && defined(WIN32)*/
-
- #define DSL_MAX_LINE_NUMBER 1
---- a/src/common/drv_dsl_cpe_os_linux.c
-+++ b/src/common/drv_dsl_cpe_os_linux.c
-@@ -11,6 +11,7 @@
- #ifdef __LINUX__
-
- #define DSL_INTERN
-+#include <linux/device.h>
-
- #include "drv_dsl_cpe_api.h"
- #include "drv_dsl_cpe_api_ioctl.h"
-@@ -1058,6 +1059,7 @@ static void DSL_DRV_DebugInit(void)
- /* Entry point of driver */
- int __init DSL_ModuleInit(void)
- {
-+ struct class *dsl_class;
- DSL_int_t i;
-
- printk(DSL_DRV_CRLF DSL_DRV_CRLF "Infineon CPE API Driver version: %s" DSL_DRV_CRLF,
-@@ -1104,7 +1106,8 @@ int __init DSL_ModuleInit(void)
- }
-
- DSL_DRV_DevNodeInit();
--
-+ dsl_class = class_create(THIS_MODULE, "dsl_cpe_api");
-+ device_create(dsl_class, NULL, MKDEV(DRV_DSL_CPE_API_DEV_MAJOR, 0), NULL, "dsl_cpe_api");
- return 0;
- }
-
---- a/src/include/drv_dsl_cpe_os_linux.h
-+++ b/src/include/drv_dsl_cpe_os_linux.h
-@@ -17,17 +17,17 @@
- #endif
-
- #include <asm/ioctl.h>
--#include <linux/autoconf.h>
-+#include <generated/autoconf.h>
- #include <linux/module.h>
- #include <linux/kernel.h>
- #include <linux/init.h>
- #include <linux/ctype.h>
- #include <linux/version.h>
- #include <linux/spinlock.h>
--
-+#include <linux/sched.h>
-
- #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
-- #include <linux/utsrelease.h>
-+ #include <generated/utsrelease.h>
- #endif
-
- #include <linux/types.h>
---- a/src/mei/ifxmips_mei.c
-+++ b/src/mei/ifxmips_mei.c
-@@ -29,7 +29,7 @@
- #include <linux/kernel.h>
- #include <linux/module.h>
- #include <linux/version.h>
--#include <linux/utsrelease.h>
-+#include <generated/utsrelease.h>
- #include <linux/types.h>
- #include <linux/fs.h>
- #include <linux/mm.h>
+++ /dev/null
---- a/src/mei/ifxmips_mei.c
-+++ b/src/mei/ifxmips_mei.c
-@@ -41,18 +41,20 @@
- #include <linux/init.h>
- #include <linux/ioport.h>
- #include <linux/delay.h>
-+#include <linux/device.h>
-+#include <linux/sched.h>
- #include <asm/uaccess.h>
- #include <asm/hardirq.h>
--#include <asm/ifx/ifx_regs.h>
--#include <asm/ifx/irq.h>
--#include <asm/ifx/ifx_gpio.h>
--//#include <asm/ifx/ifx_led.h>
--#include <asm/ifx/ifx_pmu.h>
--#include <asm/ifx/ifx_atm.h>
-+
-+#include <ifxmips.h>
-+#include <ifxmips_irq.h>
-+#include <ifxmips_gpio.h>
-+#include <ifxmips_pmu.h>
-+#include "ifxmips_atm.h"
- #define IFX_MEI_BSP
- #include "ifxmips_mei_interface.h"
-
--#define IFXMIPS_RCU_RST IFX_RCU_RST_REQ
-+/*#define IFXMIPS_RCU_RST IFX_RCU_RST_REQ
- #define IFXMIPS_RCU_RST_REQ_ARC_JTAG IFX_RCU_RST_REQ_ARC_JTAG
- #define IFXMIPS_RCU_RST_REQ_DFE IFX_RCU_RST_REQ_DFE
- #define IFXMIPS_RCU_RST_REQ_AFE IFX_RCU_RST_REQ_AFE
-@@ -76,7 +78,7 @@
- #define ifxmips_r32(reg) __raw_readl(reg)
- #define ifxmips_w32(val, reg) __raw_writel(val, reg)
- #define ifxmips_w32_mask(clear, set, reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg)
--
-+*/
- #define IFX_MEI_EMSG(fmt, args...) printk(KERN_ERR "[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args)
- #define IFX_MEI_DMSG(fmt, args...) printk(KERN_INFO "[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args)
-
-@@ -173,7 +175,8 @@ static u32 *mei_arc_swap_buff = NULL; //
- extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);
- #define MEI_MASK_AND_ACK_IRQ ifxmips_mask_and_ack_irq
-
--static int dev_major = 105;
-+#define MEI_MAJOR 105
-+static int dev_major = MEI_MAJOR;
-
- static struct file_operations bsp_mei_operations = {
- owner:THIS_MODULE,
-@@ -2294,10 +2297,10 @@ IFX_MEI_InitDevice (int num)
- IFX_MEI_EMSG ("request_irq %d failed!\n", pDev->nIrq[IFX_DFEIR]);
- return -1;
- }
-- if (request_irq (pDev->nIrq[IFX_DYING_GASP], IFX_MEI_Dying_Gasp_IrqHandle, 0, "DYING_GASP", pDev) != 0) {
-+ /*if (request_irq (pDev->nIrq[IFX_DYING_GASP], IFX_MEI_Dying_Gasp_IrqHandle, 0, "DYING_GASP", pDev) != 0) {
- IFX_MEI_EMSG ("request_irq %d failed!\n", pDev->nIrq[IFX_DYING_GASP]);
- return -1;
-- }
-+ }*/
- // IFX_MEI_DMSG("Device %d initialized. IER %#x\n", num, bsp_get_irq_ier(pDev->nIrq[IFX_DYING_GASP]));
- return 0;
- }
-@@ -2922,6 +2925,7 @@ int __init
- IFX_MEI_ModuleInit (void)
- {
- int i = 0;
-+ static struct class *dsl_class;
-
- printk ("IFX MEI Version %ld.%02ld.%02ld", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision);
-
-@@ -2935,14 +2939,15 @@ IFX_MEI_ModuleInit (void)
- IFX_MEI_InitProcFS (i);
- #endif
- }
-- for (i = 0; i <= DSL_BSP_CB_LAST ; i++)
-+ for (i = 0; i <= DSL_BSP_CB_LAST ; i++)
- dsl_bsp_event_callback[i].function = NULL;
-
- #ifdef CONFIG_IFXMIPS_MEI_FW_LOOPBACK
- printk(KERN_INFO "[%s %s %d]: Start loopback test...\n", __FILE__, __func__, __LINE__);
- DFE_Loopback_Test ();
- #endif
--
-+ dsl_class = class_create(THIS_MODULE, "ifx_mei");
-+ device_create(dsl_class, NULL, MKDEV(MEI_MAJOR, 0), NULL, "ifx_mei");
- return 0;
- }
-
-@@ -2996,3 +3001,5 @@ EXPORT_SYMBOL (DSL_BSP_EventCBUnregister
-
- module_init (IFX_MEI_ModuleInit);
- module_exit (IFX_MEI_ModuleExit);
-+
-+MODULE_LICENSE("Dual BSD/GPL");
+++ /dev/null
---- a/src/mei/ifxmips_atm_core.c
-+++ b/src/mei/ifxmips_atm_core.c
-@@ -58,9 +58,8 @@
- /*
- * Chip Specific Head File
- */
--#include <asm/ifx/ifx_types.h>
--#include <asm/ifx/ifx_regs.h>
--#include <asm/ifx/common_routines.h>
-+#include <ifxmips.h>
-+#include <ifxmips_cgu.h>
- #include "ifxmips_atm_core.h"
-
-
-@@ -1146,7 +1145,7 @@ static INLINE void mailbox_signal(unsign
-
- static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue)
- {
-- unsigned int qsb_clk = ifx_get_fpi_hz();
-+ unsigned int qsb_clk = ifxmips_get_fpi_hz();
- unsigned int qsb_qid = queue + FIRST_QSB_QID;
- union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
- union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
-@@ -1318,7 +1317,7 @@ static void set_qsb(struct atm_vcc *vcc,
-
- static void qsb_global_set(void)
- {
-- unsigned int qsb_clk = ifx_get_fpi_hz();
-+ unsigned int qsb_clk = ifxmips_get_fpi_hz();
- int i;
- unsigned int tmp1, tmp2, tmp3;
-
-@@ -2505,3 +2504,4 @@ static void __exit ifx_atm_exit(void)
-
- module_init(ifx_atm_init);
- module_exit(ifx_atm_exit);
-+MODULE_LICENSE("Dual BSD/GPL");
---- a/src/mei/ifxmips_atm_ppe_common.h
-+++ b/src/mei/ifxmips_atm_ppe_common.h
-@@ -1,9 +1,10 @@
- #ifndef IFXMIPS_ATM_PPE_COMMON_H
- #define IFXMIPS_ATM_PPE_COMMON_H
-
--
--
--#if defined(CONFIG_DANUBE)
-+#if defined(CONFIG_IFXMIPS)
-+ #include "ifxmips_atm_ppe_danube.h"
-+ #define CONFIG_DANUBE
-+#elif defined(CONFIG_DANUBE)
- #include "ifxmips_atm_ppe_danube.h"
- #elif defined(CONFIG_AMAZON_SE)
- #include "ifxmips_atm_ppe_amazon_se.h"
-@@ -16,7 +17,6 @@
- #endif
-
-
--
- /*
- * Code/Data Memory (CDM) Interface Configuration Register
- */
---- a/src/mei/ifxmips_atm_core.h
-+++ b/src/mei/ifxmips_atm_core.h
-@@ -25,8 +25,8 @@
- #define IFXMIPS_ATM_CORE_H
-
-
--
--#include <asm/ifx/ifx_atm.h>
-+#include "ifxmips_compat.h"
-+#include "ifx_atm.h"
- #include "ifxmips_atm_ppe_common.h"
- #include "ifxmips_atm_fw_regs_common.h"
-
---- /dev/null
-+++ b/src/mei/ifxmips_compat.h
-@@ -0,0 +1,43 @@
-+#ifndef _IFXMIPS_COMPAT_H__
-+#define _IFXMIPS_COMPAT_H__
-+
-+#define IFX_SUCCESS 0
-+#define IFX_ERROR (-1)
-+
-+#define ATM_VBR_NRT ATM_VBR
-+#define ATM_VBR_RT 6
-+#define ATM_UBR_PLUS 7
-+#define ATM_GFR 8
-+
-+#define NUM_ENTITY(x) (sizeof(x) / sizeof(*(x)))
-+
-+#define SET_BITS(x, msb, lsb, value) \
-+ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
-+
-+
-+#define IFX_PMU_ENABLE 1
-+#define IFX_PMU_DISABLE 0
-+
-+#define IFX_PMU_MODULE_DSL_DFE (1 << 9)
-+#define IFX_PMU_MODULE_AHBS (1 << 13)
-+#define IFX_PMU_MODULE_PPE_QSB (1 << 18)
-+#define IFX_PMU_MODULE_PPE_SLL01 (1 << 19)
-+#define IFX_PMU_MODULE_PPE_TC (1 << 21)
-+#define IFX_PMU_MODULE_PPE_EMA (1 << 22)
-+#define IFX_PMU_MODULE_PPE_TOP (1 << 29)
-+
-+#define ifx_pmu_set(a,b) {if(a == IFX_PMU_ENABLE) ifxmips_pmu_enable(b); else ifxmips_pmu_disable(b);}
-+
-+#define PPE_TOP_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TOP, (__x))
-+#define PPE_SLL01_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_SLL01, (__x))
-+#define PPE_TC_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TC, (__x))
-+#define PPE_EMA_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_EMA, (__x))
-+#define PPE_QSB_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_QSB, (__x))
-+#define PPE_TPE_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_AHBS, (__x))
-+#define DSL_DFE_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DSL_DFE, (__x))
-+
-+#define IFX_REG_W32(_v, _r) __raw_writel((_v), (_r))
-+
-+#define CONFIG_IFXMIPS_DSL_CPE_MEI y
-+
-+#endif
---- a/src/mei/ifxmips_atm_ppe_danube.h
-+++ b/src/mei/ifxmips_atm_ppe_danube.h
-@@ -1,7 +1,7 @@
- #ifndef IFXMIPS_ATM_PPE_DANUBE_H
- #define IFXMIPS_ATM_PPE_DANUBE_H
-
--
-+#include <ifxmips_irq.h>
-
- /*
- * FPI Configuration Bus Register and Memory Address Mapping
-@@ -93,7 +93,7 @@
- /*
- * Mailbox IGU1 Interrupt
- */
--#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
-+#define PPE_MAILBOX_IGU1_INT IFXMIPS_PPE_MBOX_INT
-
-
-
---- a/src/mei/ifxmips_atm_danube.c
-+++ b/src/mei/ifxmips_atm_danube.c
-@@ -45,10 +45,9 @@
- /*
- * Chip Specific Head File
- */
--#include <asm/ifx/ifx_types.h>
--#include <asm/ifx/ifx_regs.h>
--#include <asm/ifx/common_routines.h>
--#include <asm/ifx/ifx_pmu.h>
-+#include <ifxmips.h>
-+#include <ifxmips_pmu.h>
-+#include "ifxmips_compat.h"
- #include "ifxmips_atm_core.h"
- #include "ifxmips_atm_fw_danube.h"
-
+++ /dev/null
---- a/src/mei/ifxmips_mei.c
-+++ b/src/mei/ifxmips_mei.c
-@@ -79,8 +79,8 @@
- #define ifxmips_w32(val, reg) __raw_writel(val, reg)
- #define ifxmips_w32_mask(clear, set, reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg)
- */
--#define IFX_MEI_EMSG(fmt, args...) printk(KERN_ERR "[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args)
--#define IFX_MEI_DMSG(fmt, args...) printk(KERN_INFO "[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args)
-+#define IFX_MEI_EMSG(fmt, args...) pr_err("[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args)
-+#define IFX_MEI_DMSG(fmt, args...) pr_debug("[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args)
-
- #ifdef CONFIG_IFXMIPS_MEI_FW_LOOPBACK
- //#define DFE_MEM_TEST
-@@ -1301,7 +1301,7 @@ IFX_MEI_RunAdslModem (DSL_DEV_Device_t *
- IFX_MEI_EMSG (">>> malloc fail for codeswap buff!!! <<<\n");
- return DSL_DEV_MEI_ERR_FAILURE;
- }
-- printk("allocate %dKB swap buff memory at: 0x%p\n", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff);
-+ IFX_MEI_DMSG("allocate %dKB swap buff memory at: 0x%p\n", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff);
- }
-
- DSL_DEV_PRIVATE(pDev)->img_hdr =
-@@ -1476,7 +1476,7 @@ IFX_MEI_DFEMemoryFree (DSL_DEV_Device_t
- }
-
- if(mei_arc_swap_buff != NULL){
-- printk("free %dKB swap buff memory at: 0x%p\n", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff);
-+ IFX_MEI_DMSG("free %dKB swap buff memory at: 0x%p\n", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff);
- kfree(mei_arc_swap_buff);
- mei_arc_swap_buff=NULL;
- }
-@@ -1496,7 +1496,7 @@ IFX_MEI_DFEMemoryAlloc (DSL_DEV_Device_t
- // DSL_DEV_PRIVATE(pDev)->adsl_mem_info;
- int allocate_size = SDRAM_SEGMENT_SIZE;
-
-- printk(KERN_INFO "[%s %d]: image_size = %ld\n", __func__, __LINE__, size);
-+ IFX_MEI_DMSG("image_size = %ld\n", size);
- // Alloc Swap Pages
- for (idx = 0; size > 0 && idx < MAX_BAR_REGISTERS; idx++) {
- // skip bar15 for XDATA usage.
-@@ -1596,7 +1596,7 @@ DSL_BSP_FWDownload (DSL_DEV_Device_t * p
- ssize_t retval = -ENOMEM;
- int idx = 0;
-
-- printk("\n%s\n", __func__);
-+ IFX_MEI_DMSG("\n");
-
- if (*loff == 0) {
- if (size < sizeof (img_hdr_tmp)) {
-@@ -1648,7 +1648,7 @@ DSL_BSP_FWDownload (DSL_DEV_Device_t * p
- goto error;
- }
- adsl_mem_info[XDATA_REGISTER].type = FREE_RELOAD;
-- printk(KERN_INFO "[%s %d] -> IFX_MEI_BarUpdate()\n", __func__, __LINE__);
-+ IFX_MEI_DMSG("-> IFX_MEI_BarUpdate()\n");
- IFX_MEI_BarUpdate (pDev, (DSL_DEV_PRIVATE(pDev)->nBar));
- }
- else if (DSL_DEV_PRIVATE(pDev)-> image_size == 0) {
-@@ -1927,7 +1927,7 @@ static void
- WriteMbox (u32 * mboxarray, u32 size)
- {
- IFX_MEI_DebugWrite (&dsl_devices[0], IMBOX_BASE, mboxarray, size);
-- printk ("write to %X\n", IMBOX_BASE);
-+ IFX_MEI_DMSG("write to %X\n", IMBOX_BASE);
- IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ME2ARC_INT, MEI_TO_ARC_MSGAV);
- }
-
-@@ -1936,7 +1936,7 @@ static void
- ReadMbox (u32 * mboxarray, u32 size)
- {
- IFX_MEI_DebugRead (&dsl_devices[0], OMBOX_BASE, mboxarray, size);
-- printk ("read from %X\n", OMBOX_BASE);
-+ IFX_MEI_DMSG("read from %X\n", OMBOX_BASE);
- }
-
- static void
-@@ -1966,7 +1966,7 @@ arc_code_page_download (uint32_t arc_cod
- {
- int count;
-
-- printk ("try to download pages,size=%d\n", arc_code_length);
-+ IFX_MEI_DMSG("try to download pages,size=%d\n", arc_code_length);
- IFX_MEI_ControlModeSet (&dsl_devices[0], MEI_MASTER_MODE);
- IFX_MEI_HaltArc (&dsl_devices[0]);
- IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_DX_AD, 0);
-@@ -2005,21 +2005,21 @@ dfe_loopback_irq_handler (DSL_DEV_Device
- memset (&rd_mbox[0], 0, 10 * 4);
- ReadMbox (&rd_mbox[0], 6);
- if (rd_mbox[0] == 0x0) {
-- printk ("Get ARC_ACK\n");
-+ FX_MEI_DMSG("Get ARC_ACK\n");
- got_int = 1;
- }
- else if (rd_mbox[0] == 0x5) {
-- printk ("Get ARC_BUSY\n");
-+ IFX_MEI_DMSG("Get ARC_BUSY\n");
- got_int = 2;
- }
- else if (rd_mbox[0] == 0x3) {
-- printk ("Get ARC_EDONE\n");
-+ IFX_MEI_DMSG("Get ARC_EDONE\n");
- if (rd_mbox[1] == 0x0) {
- got_int = 3;
-- printk ("Get E_MEMTEST\n");
-+ IFX_MEI_DMSG("Get E_MEMTEST\n");
- if (rd_mbox[2] != 0x1) {
- got_int = 4;
-- printk ("Get Result %X\n", rd_mbox[2]);
-+ IFX_MEI_DMSG("Get Result %X\n", rd_mbox[2]);
- }
- }
- }
-@@ -2037,21 +2037,21 @@ wait_mem_test_result (void)
- uint32_t mbox[5];
- mbox[0] = 0;
-
-- printk ("Waiting Starting\n");
-+ IFX_MEI_DMSG("Waiting Starting\n");
- while (mbox[0] == 0) {
- ReadMbox (&mbox[0], 5);
- }
-- printk ("Try to get mem test result.\n");
-+ IFX_MEI_DMSG("Try to get mem test result.\n");
- ReadMbox (&mbox[0], 5);
- if (mbox[0] == 0xA) {
-- printk ("Success.\n");
-+ IFX_MEI_DMSG("Success.\n");
- }
- else if (mbox[0] == 0xA) {
-- printk ("Fail,address %X,except data %X,receive data %X\n",
-+ IFX_MEI_EMSG("Fail,address %X,except data %X,receive data %X\n",
- mbox[1], mbox[2], mbox[3]);
- }
- else {
-- printk ("Fail\n");
-+ IFX_MEI_EMSG("Fail\n");
- }
- }
-
-@@ -2067,7 +2067,7 @@ arc_ping_testing (DSL_DEV_Device_t *pDev
- rd_mbox[i] = 0;
- }
-
-- printk ("send ping msg\n");
-+ FX_MEI_DMSG("send ping msg\n");
- wr_mbox[0] = MEI_PING;
- WriteMbox (&wr_mbox[0], 10);
-
-@@ -2075,7 +2075,7 @@ arc_ping_testing (DSL_DEV_Device_t *pDev
- MEI_WAIT (100);
- }
-
-- printk ("send start event\n");
-+ IFX_MEI_DMSG("send start event\n");
- got_int = 0;
-
- wr_mbox[0] = 0x4;
-@@ -2094,14 +2094,14 @@ arc_ping_testing (DSL_DEV_Device_t *pDev
- IFX_MEI_LongWordWriteOffset (&dsl_devices[0],
- (u32) ME_ME2ARC_INT,
- MEI_TO_ARC_MSGAV);
-- printk ("sleeping\n");
-+ IFX_MEI_DMSG("sleeping\n");
- while (1) {
- if (got_int > 0) {
-
- if (got_int > 3)
-- printk ("got_int >>>> 3\n");
-+ IFX_MEI_DMSG("got_int >>>> 3\n");
- else
-- printk ("got int = %d\n", got_int);
-+ IFX_MEI_DMSG("got int = %d\n", got_int);
- got_int = 0;
- //schedule();
- DSL_ENABLE_IRQ (pDev->nIrq[IFX_DFEIR]);
-@@ -2152,7 +2152,7 @@ DFE_Loopback_Test (void)
- DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].type = FREE_RELOAD;
- IFX_MEI_WRITE_REGISTER_L ((((uint32_t) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address) & 0x0fffffff),
- IFXMIPS_MEI_BASE_ADDR + ME_XMEM_BAR_BASE + idx * 4);
-- printk ("bar%d(%X)=%X\n", idx,
-+ IFX_MEI_DMSG("bar%d(%X)=%X\n", idx,
- IFXMIPS_MEI_BASE_ADDR + ME_XMEM_BAR_BASE +
- idx * 4, (((uint32_t)
- ((ifx_mei_device_private_t *)
-@@ -2169,20 +2169,20 @@ DFE_Loopback_Test (void)
- return DSL_DEV_MEI_ERR_FAILURE;
- }
- //WriteARCreg(AUX_IC_CTRL,2);
-- printk(KERN_INFO "[%s %s %d]: Setting MEI_MASTER_MODE..\n", __FILE__, __func__, __LINE__);
-+ IFX_MEI_DMSG("Setting MEI_MASTER_MODE..\n");
- IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
- #define AUX_IC_CTRL 0x11
- _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,
- AUX_IC_CTRL, 2);
-- printk(KERN_INFO "[%s %s %d]: Setting JTAG_MASTER_MODE..\n", __FILE__, __func__, __LINE__);
-+ IFX_MEI_DMSG("Setting JTAG_MASTER_MODE..\n");
- IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
-
-- printk(KERN_INFO "[%s %s %d]: Halting ARC...\n", __FILE__, __func__, __LINE__);
-+ IFX_MEI_DMSG("Halting ARC...\n");
- IFX_MEI_HaltArc (&dsl_devices[0]);
-
- #ifdef DFE_PING_TEST
-
-- printk ("ping test image size=%d\n", sizeof (arc_ahb_access_code));
-+ IFX_MEI_DMSG("ping test image size=%d\n", sizeof (arc_ahb_access_code));
- memcpy ((u8 *) (DSL_DEV_PRIVATE(pDev)->
- adsl_mem_info[0].address + 0x1004),
- &arc_ahb_access_code[0], sizeof (arc_ahb_access_code));
-@@ -2190,13 +2190,13 @@ DFE_Loopback_Test (void)
-
- #endif //DFE_PING_TEST
-
-- printk ("ARC ping test code download complete\n");
-+ IFX_MEI_DMSG("ARC ping test code download complete\n");
- #endif //defined( DFE_PING_TEST )|| defined( DFE_ATM_LOOPBACK)
- #ifdef DFE_MEM_TEST
- IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ARC2ME_MASK, MSGAV_EN);
-
- arc_code_page_download (1537, &code_array[0]);
-- printk ("ARC mem test code download complete\n");
-+ IFX_MEI_DMSG("ARC mem test code download complete\n");
- #endif //DFE_MEM_TEST
- #ifdef DFE_ATM_LOOPBACK
- arc_debug_data = 0xf;
-@@ -2215,7 +2215,7 @@ DFE_Loopback_Test (void)
- IFX_MEI_DebugWrite (&dsl_devices[0], 0x32010, &arc_debug_data, 1);
- #endif //DFE_ATM_LOOPBACK
- IFX_MEI_IRQEnable (pDev);
-- printk(KERN_INFO "[%s %s %d]: run ARC...\n", __FILE__, __func__, __LINE__);
-+ IFX_MEI_DMSG("run ARC...\n");
- IFX_MEI_RunArc (&dsl_devices[0]);
-
- #ifdef DFE_PING_TEST
-@@ -2526,7 +2526,7 @@ IFX_MEI_Ioctls (DSL_DEV_Device_t * pDev,
- break;
-
- case DSL_FIO_BSP_DSL_START:
-- printk("\n%s: DSL_FIO_BSP_DSL_START\n",__func__);
-+ IFX_MEI_DMSG("DSL_FIO_BSP_DSL_START\n");
- if ((meierr = IFX_MEI_RunAdslModem (pDev)) != DSL_DEV_MEI_ERR_SUCCESS) {
- IFX_MEI_EMSG ("IFX_MEI_RunAdslModem() error...");
- meierr = DSL_DEV_MEI_ERR_FAILURE;
-@@ -2927,11 +2927,11 @@ IFX_MEI_ModuleInit (void)
- int i = 0;
- static struct class *dsl_class;
-
-- printk ("IFX MEI Version %ld.%02ld.%02ld", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision);
-+ pr_info("IFX MEI Version %ld.%02ld.%02ld", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision);
-
- for (i = 0; i < BSP_MAX_DEVICES; i++) {
- if (IFX_MEI_InitDevice (i) != 0) {
-- printk ("%s: Init device fail!\n", __FUNCTION__);
-+ IFX_MEI_EMSG("Init device fail!\n");
- return -EIO;
- }
- IFX_MEI_InitDevNode (i);
-@@ -2943,7 +2943,7 @@ IFX_MEI_ModuleInit (void)
- dsl_bsp_event_callback[i].function = NULL;
-
- #ifdef CONFIG_IFXMIPS_MEI_FW_LOOPBACK
-- printk(KERN_INFO "[%s %s %d]: Start loopback test...\n", __FILE__, __func__, __LINE__);
-+ IFX_MEI_DMSG("Start loopback test...\n");
- DFE_Loopback_Test ();
- #endif
- dsl_class = class_create(THIS_MODULE, "ifx_mei");
---- a/src/mei/ifxmips_atm_core.c
-+++ b/src/mei/ifxmips_atm_core.c
-@@ -2335,7 +2335,7 @@ static int atm_showtime_enter(struct por
- IFX_REG_W32(0x0F, UTP_CFG);
- #endif
-
-- printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n", g_atm_priv_data.port[0].tx_max_cell_rate, g_atm_priv_data.port[1].tx_max_cell_rate, (unsigned int)g_xdata_addr);
-+ pr_debug("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n", g_atm_priv_data.port[0].tx_max_cell_rate, g_atm_priv_data.port[1].tx_max_cell_rate, (unsigned int)g_xdata_addr);
-
- return IFX_SUCCESS;
- }
-@@ -2351,7 +2351,7 @@ static int atm_showtime_exit(void)
- // TODO: ReTX clean state
- g_xdata_addr = NULL;
-
-- printk("leave showtime\n");
-+ pr_debug("leave showtime\n");
-
- return IFX_SUCCESS;
- }
+++ /dev/null
-Index: drv_dsl_cpe_api-3.24.4.4/configure.in
-===================================================================
---- drv_dsl_cpe_api-3.24.4.4.orig/configure.in 2009-08-13 13:39:21.000000000 +0200
-+++ drv_dsl_cpe_api-3.24.4.4/configure.in 2010-11-01 12:58:37.000000000 +0100
-@@ -310,7 +310,7 @@
- AC_ARG_ENABLE(kernelbuild,
- AC_HELP_STRING(--enable-kernel-build=x,Set the target kernel build path),
- [
-- if test -e $enableval/include/linux/autoconf.h; then
-+ if test -e $enableval/include/linux/autoconf.h -o -e $enableval/include/generated/autoconf.h; then
- AC_SUBST([KERNEL_BUILD_PATH],[$enableval])
- else
- AC_MSG_ERROR([The kernel build directory is not valid or not configured!])
-@@ -333,12 +333,12 @@
- echo Set the lib_ifxos include path $enableval
- AC_SUBST([IFXOS_INCLUDE_PATH],[$enableval])
- else
-- echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
-+ echo Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
- AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH])
- fi
- ],
- [
-- echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
-+ echo Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
- AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH])
- ]
- )
-@@ -1702,73 +1702,73 @@
- AC_SUBST([DISTCHECK_CONFIGURE_PARAMS],[$CONFIGURE_OPTIONS])
-
- AC_CONFIG_COMMANDS_PRE([
--echo -e "------------------------------------------------------------------------"
--echo -e " Configuration for drv_dsl_cpe_api:"
--echo -e " Configure model type: $DSL_CONFIG_MODEL_TYPE"
--echo -e " Source code location: $srcdir"
--echo -e " Compiler: $CC"
--echo -e " Compiler c-flags: $CFLAGS"
--echo -e " Extra compiler c-flags: $EXTRA_DRV_CFLAGS"
--echo -e " Host System Type: $host"
--echo -e " Install path: $prefix"
--echo -e " Linux kernel include path: $KERNEL_INCL_PATH"
--echo -e " Linux kernel build path: $KERNEL_BUILD_PATH"
--echo -e " Linux kernel architecture: $KERNEL_ARCH"
--echo -e " Include IFXOS: $INCLUDE_DSL_CPE_API_IFXOS_SUPPORT"
--echo -e " IFXOS include path: $IFXOS_INCLUDE_PATH"
--echo -e " Driver Include Path $DSL_DRIVER_INCL_PATH"
--echo -e " DSL device: $DSL_DEVICE_NAME"
--echo -e " Max device number: $DSL_DRV_MAX_DEVICE_NUMBER"
--echo -e " Channels per line: $DSL_CHANNELS_PER_LINE"
--echo -e " Build lib (only for kernel 2.6) $DSL_CPE_API_LIBRARY_BUILD_2_6"
--echo -e " DSL data led flash frequency: $DSL_DATA_LED_FLASH_FREQUENCY Hz"
--echo -e " Disable debug prints: $DSL_DEBUG_DISABLE"
--echo -e " Preselection of max. debug level: $DSL_DBG_MAX_LEVEL_SET"
--echo -e " Preselected max. debug level: $DSL_DBG_MAX_LEVEL_PRE"
--echo -e " Include deprecated functions: $INCLUDE_DEPRECATED"
--echo -e " Include Device Exception Codes: $INCLUDE_DEVICE_EXCEPTION_CODES"
--echo -e " Include FW request support: $INCLUDE_FW_REQUEST_SUPPORT"
--echo -e " Include ADSL trace buffer: $INCLUDE_DSL_CPE_TRACE_BUFFER"
--echo -e " Include ADSL MIB: $INCLUDE_DSL_ADSL_MIB"
--echo -e " Include ADSL LED: $INCLUDE_ADSL_LED"
--echo -e " Include CEOC: $INCLUDE_DSL_CEOC"
--echo -e " Include config get support: $INCLUDE_DSL_CONFIG_GET"
--echo -e " Include System i/f configuration: $INCLUDE_DSL_SYSTEM_INTERFACE"
--echo -e " Include Resource Statistics: $INCLUDE_DSL_RESOURCE_STATISTICS"
--echo -e " Include Framing Parameters: $INCLUDE_DSL_FRAMING_PARAMETERS"
--echo -e " Include G997 Line Inventory: $INCLUDE_DSL_G997_LINE_INVENTORY"
--echo -e " Include G997 Framing Parameters: $INCLUDE_DSL_G997_FRAMING_PARAMETERS"
--echo -e " Include G997 per tone data: $INCLUDE_DSL_G997_PER_TONE"
--echo -e " Include G997 status: $INCLUDE_DSL_G997_STATUS"
--echo -e " Include G997 alarm: $INCLUDE_DSL_G997_ALARM"
--echo -e " Include DSL Bonding: $INCLUDE_DSL_BONDING"
--echo -e " Include Misc Line Status $INCLUDE_DSL_CPE_MISC_LINE_STATUS"
--echo -e " Include DELT: $INCLUDE_DSL_DELT"
--echo -e " Include DELT data static storage: $DSL_CPE_STATIC_DELT_DATA"
--echo -e " Include PM: $INCLUDE_DSL_PM"
--echo -e " Include PM config: $INCLUDE_DSL_CPE_PM_CONFIG"
--echo -e " Include PM total: $INCLUDE_DSL_CPE_PM_TOTAL_COUNTERS"
--echo -e " Include PM history: $INCLUDE_DSL_CPE_PM_HISTORY"
--echo -e " Include PM showtime: $INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS"
--echo -e " Include PM optional: $INCLUDE_DSL_CPE_PM_OPTIONAL_PARAMETERS"
--echo -e " Include PM line: $INCLUDE_DSL_CPE_PM_LINE_COUNTERS"
--echo -e " Include PM line event showtime: $INCLUDE_DSL_CPE_PM_LINE_EVENT_SHOWTIME_COUNTERS"
--echo -e " Include PM channel: $INCLUDE_DSL_CPE_PM_CHANNEL_COUNTERS"
--echo -e " Include PM channel extended: $INCLUDE_DSL_CPE_PM_CHANNEL_EXT_COUNTERS"
--echo -e " Include PM data path: $INCLUDE_DSL_CPE_PM_DATA_PATH_COUNTERS"
--echo -e " Include PM data path failure: $INCLUDE_DSL_CPE_PM_DATA_PATH_FAILURE_COUNTERS"
--echo -e " Include PM ReTx: $INCLUDE_DSL_CPE_PM_RETX_COUNTERS"
--echo -e " Include PM line threshold: $INCLUDE_DSL_CPE_PM_LINE_THRESHOLDS"
--echo -e " Include PM channel threshold: $INCLUDE_DSL_CPE_PM_CHANNEL_THRESHOLDS"
--echo -e " Include PM data path threshold: $INCLUDE_DSL_CPE_PM_DATA_PATH_THRESHOLDS"
--echo -e " Include PM ReTx threshold: $INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS"
--echo -e " Include FW memory free support: $INCLUDE_DSL_FIRMWARE_MEMORY_FREE"
--echo -e "----------------------- deprectated ! ----------------------------------"
--echo -e " Include PM line failure: $INCLUDE_DSL_CPE_PM_LINE_FAILURE_COUNTERS"
--echo -e ""
--echo -e " Settings:"
--echo -e " Configure options: $CONFIGURE_OPTIONS"
--echo -e "------------------------------------------------------------------------"
-+echo "------------------------------------------------------------------------"
-+echo " Configuration for drv_dsl_cpe_api:"
-+echo " Configure model type: $DSL_CONFIG_MODEL_TYPE"
-+echo " Source code location: $srcdir"
-+echo " Compiler: $CC"
-+echo " Compiler c-flags: $CFLAGS"
-+echo " Extra compiler c-flags: $EXTRA_DRV_CFLAGS"
-+echo " Host System Type: $host"
-+echo " Install path: $prefix"
-+echo " Linux kernel include path: $KERNEL_INCL_PATH"
-+echo " Linux kernel build path: $KERNEL_BUILD_PATH"
-+echo " Linux kernel architecture: $KERNEL_ARCH"
-+echo " Include IFXOS: $INCLUDE_DSL_CPE_API_IFXOS_SUPPORT"
-+echo " IFXOS include path: $IFXOS_INCLUDE_PATH"
-+echo " Driver Include Path $DSL_DRIVER_INCL_PATH"
-+echo " DSL device: $DSL_DEVICE_NAME"
-+echo " Max device number: $DSL_DRV_MAX_DEVICE_NUMBER"
-+echo " Channels per line: $DSL_CHANNELS_PER_LINE"
-+echo " Build lib (only for kernel 2.6) $DSL_CPE_API_LIBRARY_BUILD_2_6"
-+echo " DSL data led flash frequency: $DSL_DATA_LED_FLASH_FREQUENCY Hz"
-+echo " Disable debug prints: $DSL_DEBUG_DISABLE"
-+echo " Preselection of max. debug level: $DSL_DBG_MAX_LEVEL_SET"
-+echo " Preselected max. debug level: $DSL_DBG_MAX_LEVEL_PRE"
-+echo " Include deprecated functions: $INCLUDE_DEPRECATED"
-+echo " Include Device Exception Codes: $INCLUDE_DEVICE_EXCEPTION_CODES"
-+echo " Include FW request support: $INCLUDE_FW_REQUEST_SUPPORT"
-+echo " Include ADSL trace buffer: $INCLUDE_DSL_CPE_TRACE_BUFFER"
-+echo " Include ADSL MIB: $INCLUDE_DSL_ADSL_MIB"
-+echo " Include ADSL LED: $INCLUDE_ADSL_LED"
-+echo " Include CEOC: $INCLUDE_DSL_CEOC"
-+echo " Include config get support: $INCLUDE_DSL_CONFIG_GET"
-+echo " Include System i/f configuration: $INCLUDE_DSL_SYSTEM_INTERFACE"
-+echo " Include Resource Statistics: $INCLUDE_DSL_RESOURCE_STATISTICS"
-+echo " Include Framing Parameters: $INCLUDE_DSL_FRAMING_PARAMETERS"
-+echo " Include G997 Line Inventory: $INCLUDE_DSL_G997_LINE_INVENTORY"
-+echo " Include G997 Framing Parameters: $INCLUDE_DSL_G997_FRAMING_PARAMETERS"
-+echo " Include G997 per tone data: $INCLUDE_DSL_G997_PER_TONE"
-+echo " Include G997 status: $INCLUDE_DSL_G997_STATUS"
-+echo " Include G997 alarm: $INCLUDE_DSL_G997_ALARM"
-+echo " Include DSL Bonding: $INCLUDE_DSL_BONDING"
-+echo " Include Misc Line Status $INCLUDE_DSL_CPE_MISC_LINE_STATUS"
-+echo " Include DELT: $INCLUDE_DSL_DELT"
-+echo " Include DELT data static storage: $DSL_CPE_STATIC_DELT_DATA"
-+echo " Include PM: $INCLUDE_DSL_PM"
-+echo " Include PM config: $INCLUDE_DSL_CPE_PM_CONFIG"
-+echo " Include PM total: $INCLUDE_DSL_CPE_PM_TOTAL_COUNTERS"
-+echo " Include PM history: $INCLUDE_DSL_CPE_PM_HISTORY"
-+echo " Include PM showtime: $INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS"
-+echo " Include PM optional: $INCLUDE_DSL_CPE_PM_OPTIONAL_PARAMETERS"
-+echo " Include PM line: $INCLUDE_DSL_CPE_PM_LINE_COUNTERS"
-+echo " Include PM line event showtime: $INCLUDE_DSL_CPE_PM_LINE_EVENT_SHOWTIME_COUNTERS"
-+echo " Include PM channel: $INCLUDE_DSL_CPE_PM_CHANNEL_COUNTERS"
-+echo " Include PM channel extended: $INCLUDE_DSL_CPE_PM_CHANNEL_EXT_COUNTERS"
-+echo " Include PM data path: $INCLUDE_DSL_CPE_PM_DATA_PATH_COUNTERS"
-+echo " Include PM data path failure: $INCLUDE_DSL_CPE_PM_DATA_PATH_FAILURE_COUNTERS"
-+echo " Include PM ReTx: $INCLUDE_DSL_CPE_PM_RETX_COUNTERS"
-+echo " Include PM line threshold: $INCLUDE_DSL_CPE_PM_LINE_THRESHOLDS"
-+echo " Include PM channel threshold: $INCLUDE_DSL_CPE_PM_CHANNEL_THRESHOLDS"
-+echo " Include PM data path threshold: $INCLUDE_DSL_CPE_PM_DATA_PATH_THRESHOLDS"
-+echo " Include PM ReTx threshold: $INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS"
-+echo " Include FW memory free support: $INCLUDE_DSL_FIRMWARE_MEMORY_FREE"
-+echo "----------------------- deprectated ! ----------------------------------"
-+echo " Include PM line failure: $INCLUDE_DSL_CPE_PM_LINE_FAILURE_COUNTERS"
-+echo ""
-+echo " Settings:"
-+echo " Configure options: $CONFIGURE_OPTIONS"
-+echo "------------------------------------------------------------------------"
- ])
-
- AC_CONFIG_FILES([Makefile src/Makefile])
-Index: drv_dsl_cpe_api-3.24.4.4/src/Makefile.am
-===================================================================
---- drv_dsl_cpe_api-3.24.4.4.orig/src/Makefile.am 2009-07-03 14:06:34.000000000 +0200
-+++ drv_dsl_cpe_api-3.24.4.4/src/Makefile.am 2010-11-01 12:58:37.000000000 +0100
-@@ -303,7 +303,7 @@
- drv_dsl_cpe_api_OBJS = "$(subst .c,.o,$(filter %.c,$(drv_dsl_cpe_api_SOURCES)))"
-
- drv_dsl_cpe_api.ko: $(drv_dsl_cpe_api_SOURCES)
-- @echo -e "drv_dsl_cpe_api: Making Linux 2.6.x kernel object"
-+ @echo "drv_dsl_cpe_api: Making Linux 2.6.x kernel object"
- if test ! -e common/drv_dsl_cpe_api.c ; then \
- echo "copy source files (as links only!)"; \
- for f in $(filter %.c,$(drv_dsl_cpe_api_SOURCES)); do \
-@@ -311,10 +311,10 @@
- cp -s $(addprefix @abs_srcdir@/,$$f) $(PWD)/`dirname $$f`/ ; \
- done \
- fi
-- @echo -e "# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
-- @echo -e "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild
-- @echo -e "$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)" >> $(PWD)/Kbuild
-- @echo -e "EXTRA_CFLAGS := $(CFLAGS) -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include" >> $(PWD)/Kbuild
-+ @echo "# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
-+ @echo "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild
-+ @echo "$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)" >> $(PWD)/Kbuild
-+ @echo "EXTRA_CFLAGS := $(CFLAGS) -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include" >> $(PWD)/Kbuild
- $(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules
-
- clean-generic:
+++ /dev/null
-obj-m = ifxmips_mei.o ifxmips_atm.o
-
-ifxmips_atm-objs := ifxmips_atm_core.o ifxmips_atm_danube.o
+++ /dev/null
-/******************************************************************************
-**
-** FILE NAME : ifx_atm.h
-** PROJECT : UEIP
-** MODULES : ATM
-**
-** DATE : 17 Jun 2009
-** AUTHOR : Xu Liang
-** DESCRIPTION : Global ATM driver header file
-** COPYRIGHT : Copyright (c) 2006
-** Infineon Technologies AG
-** Am Campeon 1-12, 85579 Neubiberg, Germany
-**
-** This program is free software; you can redistribute it and/or modify
-** it under the terms of the GNU General Public License as published by
-** the Free Software Foundation; either version 2 of the License, or
-** (at your option) any later version.
-**
-** HISTORY
-** $Date $Author $Comment
-** 07 JUL 2009 Xu Liang Init Version
-*******************************************************************************/
-
-#ifndef IFX_ATM_H
-#define IFX_ATM_H
-
-
-
-/*!
- \defgroup IFX_ATM UEIP Project - ATM driver module
- \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
- */
-
-/*!
- \defgroup IFX_ATM_IOCTL IOCTL Commands
- \ingroup IFX_ATM
- \brief IOCTL Commands used by user application.
- */
-
-/*!
- \defgroup IFX_ATM_STRUCT Structures
- \ingroup IFX_ATM
- \brief Structures used by user application.
- */
-
-/*!
- \file ifx_atm.h
- \ingroup IFX_ATM
- \brief ATM driver header file
- */
-
-
-
-/*
- * ####################################
- * Definition
- * ####################################
- */
-
-/*!
- \addtogroup IFX_ATM_STRUCT
- */
-/*@{*/
-
-/*
- * ATM MIB
- */
-
-typedef struct {
- __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
- __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
- __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
- __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
- __u32 ifInErrors; /*!< counter of error ingress cells */
- __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
- __u32 ifOutErrors; /*!< counter of error egress cells */
-} atm_cell_ifEntry_t;
-
-typedef struct {
- __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
- __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
- __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
- __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
- __u32 ifInUcastPkts; /*!< counter of ingress packets */
- __u32 ifOutUcastPkts; /*!< counter of egress packets */
- __u32 ifInErrors; /*!< counter of error ingress packets */
- __u32 ifInDiscards; /*!< counter of dropped ingress packets */
- __u32 ifOutErros; /*!< counter of error egress packets */
- __u32 ifOutDiscards; /*!< counter of dropped egress packets */
-} atm_aal5_ifEntry_t;
-
-typedef struct {
- __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
- __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
- __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
-} atm_aal5_vcc_t;
-
-typedef struct {
- int vpi; /*!< VPI of the VCC to get MIB counters */
- int vci; /*!< VCI of the VCC to get MIB counters */
- atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
-} atm_aal5_vcc_x_t;
-
-/*@}*/
-
-
-
-/*
- * ####################################
- * IOCTL
- * ####################################
- */
-
-/*!
- \addtogroup IFX_ATM_IOCTL
- */
-/*@{*/
-
-/*
- * ioctl Command
- */
-/*!
- \brief ATM IOCTL Magic Number
- */
-#define PPE_ATM_IOC_MAGIC 'o'
-/*!
- \brief ATM IOCTL Command - Get Cell Level MIB Counters
-
- This command is obsolete. User can get cell level MIB from DSL API.
- This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
- */
-#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
-/*!
- \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
-
- Get AAL5 packet counters.
- This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
- */
-#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
-/*!
- \brief ATM IOCTL Command - Get Per PVC MIB Counters
-
- Get AAL5 packet counters for each PVC.
- This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
- */
-#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
-/*!
- \brief Total Number of ATM IOCTL Commands
- */
-#define PPE_ATM_IOC_MAXNR 3
-
-/*@}*/
-
-
-
-/*
- * ####################################
- * API
- * ####################################
- */
-
-#ifdef __KERNEL__
-struct port_cell_info {
- unsigned int port_num;
- unsigned int tx_link_rate[2];
-};
-#endif
-
-
-
-#endif // IFX_ATM_H
-
+++ /dev/null
-/******************************************************************************
-**
-** FILE NAME : ifx_atm.h
-** PROJECT : UEIP
-** MODULES : ATM
-**
-** DATE : 17 Jun 2009
-** AUTHOR : Xu Liang
-** DESCRIPTION : Global ATM driver header file
-** COPYRIGHT : Copyright (c) 2006
-** Infineon Technologies AG
-** Am Campeon 1-12, 85579 Neubiberg, Germany
-**
-** This program is free software; you can redistribute it and/or modify
-** it under the terms of the GNU General Public License as published by
-** the Free Software Foundation; either version 2 of the License, or
-** (at your option) any later version.
-**
-** HISTORY
-** $Date $Author $Comment
-** 07 JUL 2009 Xu Liang Init Version
-*******************************************************************************/
-
-#ifndef IFX_ATM_H
-#define IFX_ATM_H
-
-
-
-/*!
- \defgroup IFX_ATM UEIP Project - ATM driver module
- \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
- */
-
-/*!
- \defgroup IFX_ATM_IOCTL IOCTL Commands
- \ingroup IFX_ATM
- \brief IOCTL Commands used by user application.
- */
-
-/*!
- \defgroup IFX_ATM_STRUCT Structures
- \ingroup IFX_ATM
- \brief Structures used by user application.
- */
-
-/*!
- \file ifx_atm.h
- \ingroup IFX_ATM
- \brief ATM driver header file
- */
-
-
-
-/*
- * ####################################
- * Definition
- * ####################################
- */
-
-/*!
- \addtogroup IFX_ATM_STRUCT
- */
-/*@{*/
-
-/*
- * ATM MIB
- */
-
-typedef struct {
- __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
- __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
- __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
- __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
- __u32 ifInErrors; /*!< counter of error ingress cells */
- __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
- __u32 ifOutErrors; /*!< counter of error egress cells */
-} atm_cell_ifEntry_t;
-
-typedef struct {
- __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
- __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
- __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
- __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
- __u32 ifInUcastPkts; /*!< counter of ingress packets */
- __u32 ifOutUcastPkts; /*!< counter of egress packets */
- __u32 ifInErrors; /*!< counter of error ingress packets */
- __u32 ifInDiscards; /*!< counter of dropped ingress packets */
- __u32 ifOutErros; /*!< counter of error egress packets */
- __u32 ifOutDiscards; /*!< counter of dropped egress packets */
-} atm_aal5_ifEntry_t;
-
-typedef struct {
- __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
- __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
- __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
-} atm_aal5_vcc_t;
-
-typedef struct {
- int vpi; /*!< VPI of the VCC to get MIB counters */
- int vci; /*!< VCI of the VCC to get MIB counters */
- atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
-} atm_aal5_vcc_x_t;
-
-/*@}*/
-
-
-
-/*
- * ####################################
- * IOCTL
- * ####################################
- */
-
-/*!
- \addtogroup IFX_ATM_IOCTL
- */
-/*@{*/
-
-/*
- * ioctl Command
- */
-/*!
- \brief ATM IOCTL Magic Number
- */
-#define PPE_ATM_IOC_MAGIC 'o'
-/*!
- \brief ATM IOCTL Command - Get Cell Level MIB Counters
-
- This command is obsolete. User can get cell level MIB from DSL API.
- This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
- */
-#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
-/*!
- \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
-
- Get AAL5 packet counters.
- This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
- */
-#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
-/*!
- \brief ATM IOCTL Command - Get Per PVC MIB Counters
-
- Get AAL5 packet counters for each PVC.
- This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
- */
-#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
-/*!
- \brief Total Number of ATM IOCTL Commands
- */
-#define PPE_ATM_IOC_MAXNR 3
-
-/*@}*/
-
-
-
-/*
- * ####################################
- * API
- * ####################################
- */
-
-#ifdef __KERNEL__
-struct port_cell_info {
- unsigned int port_num;
- unsigned int tx_link_rate[2];
-};
-#endif
-
-
-
-#endif // IFX_ATM_H
-
+++ /dev/null
-/******************************************************************************
-**
-** FILE NAME : ifxmips_atm_core.c
-** PROJECT : UEIP
-** MODULES : ATM
-**
-** DATE : 7 Jul 2009
-** AUTHOR : Xu Liang
-** DESCRIPTION : ATM driver common source file (core functions)
-** COPYRIGHT : Copyright (c) 2006
-** Infineon Technologies AG
-** Am Campeon 1-12, 85579 Neubiberg, Germany
-**
-** This program is free software; you can redistribute it and/or modify
-** it under the terms of the GNU General Public License as published by
-** the Free Software Foundation; either version 2 of the License, or
-** (at your option) any later version.
-**
-** HISTORY
-** $Date $Author $Comment
-** 07 JUL 2009 Xu Liang Init Version
-*******************************************************************************/
-
-
-
-/*
- * ####################################
- * Version No.
- * ####################################
- */
-
-#define IFX_ATM_VER_MAJOR 1
-#define IFX_ATM_VER_MID 0
-#define IFX_ATM_VER_MINOR 8
-
-
-
-/*
- * ####################################
- * Head File
- * ####################################
- */
-
-/*
- * Common Head File
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/proc_fs.h>
-#include <linux/init.h>
-#include <linux/ioctl.h>
-#include <linux/atmdev.h>
-#include <linux/atm.h>
-
-/*
- * Chip Specific Head File
- */
-#include <asm/ifx/ifx_types.h>
-#include <asm/ifx/ifx_regs.h>
-#include <asm/ifx/common_routines.h>
-#include "ifxmips_atm_core.h"
-
-
-
-/*
- * ####################################
- * Kernel Version Adaption
- * ####################################
- */
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
- #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0)
- #define MODULE_PARM(a, b) module_param(a, int, 0)
-#else
- #define MODULE_PARM_ARRAY(a, b) MODULE_PARM(a, b)
-#endif
-
-
-
-/*!
- \addtogroup IFXMIPS_ATM_MODULE_PARAMS
- */
-/*@{*/
-/*
- * ####################################
- * Parameters to Configure PPE
- * ####################################
- */
-/*!
- \brief QSB cell delay variation due to concurrency
- */
-static int qsb_tau = 1; /* QSB cell delay variation due to concurrency */
-/*!
- \brief QSB scheduler burst length
- */
-static int qsb_srvm = 0x0F; /* QSB scheduler burst length */
-/*!
- \brief QSB time step, all legal values are 1, 2, 4
- */
-static int qsb_tstep = 4 ; /* QSB time step, all legal values are 1, 2, 4 */
-
-/*!
- \brief Write descriptor delay
- */
-static int write_descriptor_delay = 0x20; /* Write descriptor delay */
-
-/*!
- \brief AAL5 padding byte ('~')
- */
-static int aal5_fill_pattern = 0x007E; /* AAL5 padding byte ('~') */
-/*!
- \brief Max frame size for RX
- */
-static int aal5r_max_packet_size = 0x0700; /* Max frame size for RX */
-/*!
- \brief Min frame size for RX
- */
-static int aal5r_min_packet_size = 0x0000; /* Min frame size for RX */
-/*!
- \brief Max frame size for TX
- */
-static int aal5s_max_packet_size = 0x0700; /* Max frame size for TX */
-/*!
- \brief Min frame size for TX
- */
-static int aal5s_min_packet_size = 0x0000; /* Min frame size for TX */
-/*!
- \brief Drop error packet in RX path
- */
-static int aal5r_drop_error_packet = 1; /* Drop error packet in RX path */
-
-/*!
- \brief Number of descriptors per DMA RX channel
- */
-static int dma_rx_descriptor_length = 128; /* Number of descriptors per DMA RX channel */
-/*!
- \brief Number of descriptors per DMA TX channel
- */
-static int dma_tx_descriptor_length = 64; /* Number of descriptors per DMA TX channel */
-/*!
- \brief PPE core clock cycles between descriptor write and effectiveness in external RAM
- */
-static int dma_rx_clp1_descriptor_threshold = 38;
-/*@}*/
-
-MODULE_PARM(qsb_tau, "i");
-MODULE_PARM_DESC(qsb_tau, "Cell delay variation. Value must be > 0");
-MODULE_PARM(qsb_srvm, "i");
-MODULE_PARM_DESC(qsb_srvm, "Maximum burst size");
-MODULE_PARM(qsb_tstep, "i");
-MODULE_PARM_DESC(qsb_tstep, "n*32 cycles per sbs cycles n=1,2,4");
-
-MODULE_PARM(write_descriptor_delay, "i");
-MODULE_PARM_DESC(write_descriptor_delay, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
-
-MODULE_PARM(aal5_fill_pattern, "i");
-MODULE_PARM_DESC(aal5_fill_pattern, "Filling pattern (PAD) for AAL5 frames");
-MODULE_PARM(aal5r_max_packet_size, "i");
-MODULE_PARM_DESC(aal5r_max_packet_size, "Max packet size in byte for downstream AAL5 frames");
-MODULE_PARM(aal5r_min_packet_size, "i");
-MODULE_PARM_DESC(aal5r_min_packet_size, "Min packet size in byte for downstream AAL5 frames");
-MODULE_PARM(aal5s_max_packet_size, "i");
-MODULE_PARM_DESC(aal5s_max_packet_size, "Max packet size in byte for upstream AAL5 frames");
-MODULE_PARM(aal5s_min_packet_size, "i");
-MODULE_PARM_DESC(aal5s_min_packet_size, "Min packet size in byte for upstream AAL5 frames");
-MODULE_PARM(aal5r_drop_error_packet, "i");
-MODULE_PARM_DESC(aal5r_drop_error_packet, "Non-zero value to drop error packet for downstream");
-
-MODULE_PARM(dma_rx_descriptor_length, "i");
-MODULE_PARM_DESC(dma_rx_descriptor_length, "Number of descriptor assigned to DMA RX channel (>16)");
-MODULE_PARM(dma_tx_descriptor_length, "i");
-MODULE_PARM_DESC(dma_tx_descriptor_length, "Number of descriptor assigned to DMA TX channel (>16)");
-MODULE_PARM(dma_rx_clp1_descriptor_threshold, "i");
-MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold, "Descriptor threshold for cells with cell loss priority 1");
-
-
-
-/*
- * ####################################
- * Definition
- * ####################################
- */
-
-#define DUMP_SKB_LEN ~0
-
-
-
-/*
- * ####################################
- * Declaration
- * ####################################
- */
-
-/*
- * Network Operations
- */
-static int ppe_ioctl(struct atm_dev *, unsigned int, void *);
-static int ppe_open(struct atm_vcc *);
-static void ppe_close(struct atm_vcc *);
-static int ppe_send(struct atm_vcc *, struct sk_buff *);
-static int ppe_send_oam(struct atm_vcc *, void *, int);
-static int ppe_change_qos(struct atm_vcc *, struct atm_qos *, int);
-
-/*
- * ADSL LED
- */
-static INLINE int adsl_led_flash(void);
-
-/*
- * 64-bit operation used by MIB calculation
- */
-static INLINE void u64_add_u32(ppe_u64_t, unsigned int, ppe_u64_t *);
-
-/*
- * buffer manage functions
- */
-static INLINE struct sk_buff* alloc_skb_rx(void);
-static INLINE struct sk_buff* alloc_skb_tx(unsigned int);
-struct sk_buff* atm_alloc_tx(struct atm_vcc *, unsigned int);
-static INLINE void atm_free_tx_skb_vcc(struct sk_buff *, struct atm_vcc *);
-static INLINE struct sk_buff *get_skb_rx_pointer(unsigned int);
-static INLINE int get_tx_desc(unsigned int);
-
-/*
- * mailbox handler and signal function
- */
-static INLINE void mailbox_oam_rx_handler(void);
-static INLINE void mailbox_aal_rx_handler(void);
-#if defined(ENABLE_TASKLET) && ENABLE_TASKLET
- static void do_ppe_tasklet(unsigned long);
-#endif
-static irqreturn_t mailbox_irq_handler(int, void *);
-static INLINE void mailbox_signal(unsigned int, int);
-
-/*
- * QSB & HTU setting functions
- */
-static void set_qsb(struct atm_vcc *, struct atm_qos *, unsigned int);
-static void qsb_global_set(void);
-static INLINE void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int);
-static INLINE void clear_htu_entry(unsigned int);
-static void validate_oam_htu_entry(void);
-static void invalidate_oam_htu_entry(void);
-
-/*
- * look up for connection ID
- */
-static INLINE int find_vpi(unsigned int);
-static INLINE int find_vpivci(unsigned int, unsigned int);
-static INLINE int find_vcc(struct atm_vcc *);
-
-/*
- * Debug Functions
- */
-#if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB
- static void dump_skb(struct sk_buff *, u32, char *, int, int, int);
-#else
- #define dump_skb(skb, len, title, port, ch, is_tx) do {} while (0)
-#endif
-
-/*
- * Proc File Functions
- */
-static INLINE void proc_file_create(void);
-static INLINE void proc_file_delete(void);
-static int proc_read_version(char *, char **, off_t, int, int *, void *);
-static int proc_read_mib(char *, char **, off_t, int, int *, void *);
-static int proc_write_mib(struct file *, const char *, unsigned long, void *);
-#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
- static int proc_read_dbg(char *, char **, off_t, int, int *, void *);
- static int proc_write_dbg(struct file *, const char *, unsigned long, void *);
-#endif
-#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
- static int proc_read_htu(char *, char **, off_t, int, int *, void *);
- static int proc_read_txq(char *, char **, off_t, int, int *, void *);
-#endif
-
-/*
- * Proc Help Functions
- */
-static int stricmp(const char *, const char *);
-#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
- static int strincmp(const char *, const char *, int);
-#endif
-static INLINE int ifx_atm_version(char *);
-//static INLINE int print_reset_domain(char *, int);
-//static INLINE int print_reset_handler(char *, int, ifx_rcu_handler_t *);
-
-/*
- * Init & clean-up functions
- */
-#ifdef MODULE
- static INLINE void reset_ppe(void);
-#endif
-static INLINE void check_parameters(void);
-static INLINE int init_priv_data(void);
-static INLINE void clear_priv_data(void);
-static INLINE void init_rx_tables(void);
-static INLINE void init_tx_tables(void);
-
-/*
- * Exteranl Function
- */
-#if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE)
- extern void ifx_push_oam(unsigned char *);
-#else
- static inline void ifx_push_oam(unsigned char *dummy) {}
-#endif
-#if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
- extern int ifx_mei_atm_led_blink(void);
- extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);
-#else
- static inline int ifx_mei_atm_led_blink(void) { return IFX_SUCCESS; }
- static inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)
- {
- if ( is_showtime != NULL )
- *is_showtime = 0;
- return IFX_SUCCESS;
- }
-#endif
-
-/*
- * External variable
- */
-extern struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int);
-#if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
- extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);
- extern int (*ifx_mei_atm_showtime_exit)(void);
-#else
- int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
- EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);
- int (*ifx_mei_atm_showtime_exit)(void) = NULL;
- EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);
-#endif
-
-
-
-/*
- * ####################################
- * Local Variable
- * ####################################
- */
-
-static struct atm_priv_data g_atm_priv_data;
-
-static struct atmdev_ops g_ifx_atm_ops = {
- .open = ppe_open,
- .close = ppe_close,
- .ioctl = ppe_ioctl,
- .send = ppe_send,
- .send_oam = ppe_send_oam,
- .change_qos = ppe_change_qos,
- .owner = THIS_MODULE,
-};
-
-#if defined(ENABLE_TASKLET) && ENABLE_TASKLET
- DECLARE_TASKLET(g_dma_tasklet, do_ppe_tasklet, 0);
-#endif
-
-static int g_showtime = 0;
-static void *g_xdata_addr = NULL;
-
-unsigned int ifx_atm_dbg_enable = 0;
-
-static struct proc_dir_entry* g_atm_dir = NULL;
-
-
-
-/*
- * ####################################
- * Local Function
- * ####################################
- */
-
-static int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg)
-{
- int ret = 0;
- atm_cell_ifEntry_t mib_cell;
- atm_aal5_ifEntry_t mib_aal5;
- atm_aal5_vcc_x_t mib_vcc;
- unsigned int value;
- int conn;
-
- if ( _IOC_TYPE(cmd) != PPE_ATM_IOC_MAGIC
- || _IOC_NR(cmd) >= PPE_ATM_IOC_MAXNR )
- return -ENOTTY;
-
- if ( _IOC_DIR(cmd) & _IOC_READ )
- ret = !access_ok(VERIFY_WRITE, arg, _IOC_SIZE(cmd));
- else if ( _IOC_DIR(cmd) & _IOC_WRITE )
- ret = !access_ok(VERIFY_READ, arg, _IOC_SIZE(cmd));
- if ( ret )
- return -EFAULT;
-
- switch ( cmd )
- {
- case PPE_ATM_MIB_CELL: /* cell level MIB */
- /* These MIB should be read at ARC side, now put zero only. */
- mib_cell.ifHCInOctets_h = 0;
- mib_cell.ifHCInOctets_l = 0;
- mib_cell.ifHCOutOctets_h = 0;
- mib_cell.ifHCOutOctets_l = 0;
- mib_cell.ifInErrors = 0;
- mib_cell.ifInUnknownProtos = WAN_MIB_TABLE->wrx_drophtu_cell;
- mib_cell.ifOutErrors = 0;
-
- ret = sizeof(mib_cell) - copy_to_user(arg, &mib_cell, sizeof(mib_cell));
- break;
-
- case PPE_ATM_MIB_AAL5: /* AAL5 MIB */
- value = WAN_MIB_TABLE->wrx_total_byte;
- u64_add_u32(g_atm_priv_data.wrx_total_byte, value - g_atm_priv_data.prev_wrx_total_byte, &g_atm_priv_data.wrx_total_byte);
- g_atm_priv_data.prev_wrx_total_byte = value;
- mib_aal5.ifHCInOctets_h = g_atm_priv_data.wrx_total_byte.h;
- mib_aal5.ifHCInOctets_l = g_atm_priv_data.wrx_total_byte.l;
-
- value = WAN_MIB_TABLE->wtx_total_byte;
- u64_add_u32(g_atm_priv_data.wtx_total_byte, value - g_atm_priv_data.prev_wtx_total_byte, &g_atm_priv_data.wtx_total_byte);
- g_atm_priv_data.prev_wtx_total_byte = value;
- mib_aal5.ifHCOutOctets_h = g_atm_priv_data.wtx_total_byte.h;
- mib_aal5.ifHCOutOctets_l = g_atm_priv_data.wtx_total_byte.l;
-
- mib_aal5.ifInUcastPkts = g_atm_priv_data.wrx_pdu;
- mib_aal5.ifOutUcastPkts = WAN_MIB_TABLE->wtx_total_pdu;
- mib_aal5.ifInErrors = WAN_MIB_TABLE->wrx_err_pdu;
- mib_aal5.ifInDiscards = WAN_MIB_TABLE->wrx_dropdes_pdu + g_atm_priv_data.wrx_drop_pdu;
- mib_aal5.ifOutErros = g_atm_priv_data.wtx_err_pdu;
- mib_aal5.ifOutDiscards = g_atm_priv_data.wtx_drop_pdu;
-
- ret = sizeof(mib_aal5) - copy_to_user(arg, &mib_aal5, sizeof(mib_aal5));
- break;
-
- case PPE_ATM_MIB_VCC: /* VCC related MIB */
- copy_from_user(&mib_vcc, arg, sizeof(mib_vcc));
- conn = find_vpivci(mib_vcc.vpi, mib_vcc.vci);
- if ( conn >= 0 )
- {
- mib_vcc.mib_vcc.aal5VccCrcErrors = g_atm_priv_data.conn[conn].aal5_vcc_crc_err;
- mib_vcc.mib_vcc.aal5VccOverSizedSDUs = g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu;
- mib_vcc.mib_vcc.aal5VccSarTimeOuts = 0; /* no timer support */
- ret = sizeof(mib_vcc) - copy_to_user(arg, &mib_vcc, sizeof(mib_vcc));
- }
- else
- ret = -EINVAL;
- break;
-
- default:
- ret = -ENOIOCTLCMD;
- }
-
- return ret;
-}
-
-static int ppe_open(struct atm_vcc *vcc)
-{
- int ret;
- short vpi = vcc->vpi;
- int vci = vcc->vci;
- struct port *port = &g_atm_priv_data.port[(int)vcc->dev->dev_data];
- int conn;
- int f_enable_irq = 0;
-#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
- int sys_flag;
-#endif
-
- if ( vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0 )
- return -EPROTONOSUPPORT;
-
- /* check bandwidth */
- if ( (vcc->qos.txtp.traffic_class == ATM_CBR && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
- || (vcc->qos.txtp.traffic_class == ATM_VBR_RT && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
- || (vcc->qos.txtp.traffic_class == ATM_VBR_NRT && vcc->qos.txtp.scr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
- || (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS && vcc->qos.txtp.min_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) )
- {
- ret = -EINVAL;
- goto PPE_OPEN_EXIT;
- }
-
- /* check existing vpi,vci */
- conn = find_vpivci(vpi, vci);
- if ( conn >= 0 ) {
- ret = -EADDRINUSE;
- goto PPE_OPEN_EXIT;
- }
-
- /* check whether it need to enable irq */
- if ( g_atm_priv_data.conn_table == 0 )
- f_enable_irq = 1;
-
- /* allocate connection */
- for ( conn = 0; conn < MAX_PVC_NUMBER; conn++ ) {
- if ( test_and_set_bit(conn, &g_atm_priv_data.conn_table) == 0 ) {
- g_atm_priv_data.conn[conn].vcc = vcc;
- break;
- }
- }
- if ( conn == MAX_PVC_NUMBER )
- {
- ret = -EINVAL;
- goto PPE_OPEN_EXIT;
- }
-
- /* reserve bandwidth */
- switch ( vcc->qos.txtp.traffic_class ) {
- case ATM_CBR:
- case ATM_VBR_RT:
- port->tx_current_cell_rate += vcc->qos.txtp.max_pcr;
- break;
- case ATM_VBR_NRT:
- port->tx_current_cell_rate += vcc->qos.txtp.scr;
- break;
- case ATM_UBR_PLUS:
- port->tx_current_cell_rate += vcc->qos.txtp.min_pcr;
- break;
- }
-
- /* set qsb */
- set_qsb(vcc, &vcc->qos, conn);
-
- /* update atm_vcc structure */
- vcc->itf = (int)vcc->dev->dev_data;
- vcc->vpi = vpi;
- vcc->vci = vci;
- set_bit(ATM_VF_READY, &vcc->flags);
-
- /* enable irq */
- if (f_enable_irq ) {
- ifx_atm_alloc_tx = atm_alloc_tx;
-
- *MBOX_IGU1_ISRC = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
- *MBOX_IGU1_IER = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
-
- enable_irq(PPE_MAILBOX_IGU1_INT);
- }
-
- /* set port */
- WTX_QUEUE_CONFIG(conn)->sbid = (int)vcc->dev->dev_data;
-
- /* set htu entry */
- set_htu_entry(vpi, vci, conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 0);
-
-#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
- // ReTX: occupy second QID
- local_irq_save(sys_flag);
- if ( g_retx_htu && vcc->qos.aal == ATM_AAL5 )
- {
- int retx_conn = (conn + 8) % 16; // ReTX queue
-
- if ( retx_conn < MAX_PVC_NUMBER && test_and_set_bit(retx_conn, &g_atm_priv_data.conn_table) == 0 ) {
- g_atm_priv_data.conn[retx_conn].vcc = vcc;
- set_htu_entry(vpi, vci, retx_conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 1);
- }
- }
- local_irq_restore(sys_flag);
-#endif
-
- ret = 0;
-
-PPE_OPEN_EXIT:
- return ret;
-}
-
-static void ppe_close(struct atm_vcc *vcc)
-{
- int conn;
- struct port *port;
- struct connection *connection;
-
- if ( vcc == NULL )
- return;
-
- /* get connection id */
- conn = find_vcc(vcc);
- if ( conn < 0 ) {
- err("can't find vcc");
- goto PPE_CLOSE_EXIT;
- }
- connection = &g_atm_priv_data.conn[conn];
- port = &g_atm_priv_data.port[connection->port];
-
- /* clear htu */
- clear_htu_entry(conn);
-
- /* release connection */
- clear_bit(conn, &g_atm_priv_data.conn_table);
- connection->vcc = NULL;
- connection->aal5_vcc_crc_err = 0;
- connection->aal5_vcc_oversize_sdu = 0;
-
- /* disable irq */
- if ( g_atm_priv_data.conn_table == 0 ) {
- disable_irq(PPE_MAILBOX_IGU1_INT);
- ifx_atm_alloc_tx = NULL;
- }
-
- /* release bandwidth */
- switch ( vcc->qos.txtp.traffic_class )
- {
- case ATM_CBR:
- case ATM_VBR_RT:
- port->tx_current_cell_rate -= vcc->qos.txtp.max_pcr;
- break;
- case ATM_VBR_NRT:
- port->tx_current_cell_rate -= vcc->qos.txtp.scr;
- break;
- case ATM_UBR_PLUS:
- port->tx_current_cell_rate -= vcc->qos.txtp.min_pcr;
- break;
- }
-
-PPE_CLOSE_EXIT:
- return;
-}
-
-static int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb)
-{
- int ret;
- int conn;
- int desc_base;
- struct tx_descriptor reg_desc = {0};
-
- if ( vcc == NULL || skb == NULL )
- return -EINVAL;
-
- skb_get(skb);
- atm_free_tx_skb_vcc(skb, vcc);
-
- conn = find_vcc(vcc);
- if ( conn < 0 ) {
- ret = -EINVAL;
- goto FIND_VCC_FAIL;
- }
-
- if ( !g_showtime ) {
- err("not in showtime");
- ret = -EIO;
- goto PPE_SEND_FAIL;
- }
-
- if ( vcc->qos.aal == ATM_AAL5 ) {
- int byteoff;
- int datalen;
- struct tx_inband_header *header;
-
- datalen = skb->len;
- byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
-
- if ( skb_headroom(skb) < byteoff + TX_INBAND_HEADER_LENGTH ) {
- struct sk_buff *new_skb;
-
- new_skb = alloc_skb_tx(datalen);
- if ( new_skb == NULL ) {
- err("ALLOC_SKB_TX_FAIL");
- ret = -ENOMEM;
- goto PPE_SEND_FAIL;
- }
- skb_put(new_skb, datalen);
- memcpy(new_skb->data, skb->data, datalen);
- dev_kfree_skb_any(skb);
- skb = new_skb;
- byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
- }
-
- skb_push(skb, byteoff + TX_INBAND_HEADER_LENGTH);
-
- header = (struct tx_inband_header *)skb->data;
-
- /* setup inband trailer */
- header->uu = 0;
- header->cpi = 0;
- header->pad = aal5_fill_pattern;
- header->res1 = 0;
-
- /* setup cell header */
- header->clp = (vcc->atm_options & ATM_ATMOPT_CLP) ? 1 : 0;
- header->pti = ATM_PTI_US0;
- header->vci = vcc->vci;
- header->vpi = vcc->vpi;
- header->gfc = 0;
-
- /* setup descriptor */
- reg_desc.dataptr = (unsigned int)skb->data >> 2;
- reg_desc.datalen = datalen;
- reg_desc.byteoff = byteoff;
- reg_desc.iscell = 0;
- }
- else {
- /* if data pointer is not aligned, allocate new sk_buff */
- if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 ) {
- struct sk_buff *new_skb;
-
- err("skb->data not aligned");
-
- new_skb = alloc_skb_tx(skb->len);
- if ( new_skb == NULL ) {
- err("ALLOC_SKB_TX_FAIL");
- ret = -ENOMEM;
- goto PPE_SEND_FAIL;
- }
- skb_put(new_skb, skb->len);
- memcpy(new_skb->data, skb->data, skb->len);
- dev_kfree_skb_any(skb);
- skb = new_skb;
- }
-
- reg_desc.dataptr = (unsigned int)skb->data >> 2;
- reg_desc.datalen = skb->len;
- reg_desc.byteoff = 0;
- reg_desc.iscell = 1;
- }
-
- reg_desc.own = 1;
- reg_desc.c = 1;
- reg_desc.sop = reg_desc.eop = 1;
-
- desc_base = get_tx_desc(conn);
- if ( desc_base < 0 ) {
- err("ALLOC_TX_CONNECTION_FAIL");
- ret = -EIO;
- goto PPE_SEND_FAIL;
- }
-
- if ( vcc->stats )
- atomic_inc(&vcc->stats->tx);
- if ( vcc->qos.aal == ATM_AAL5 )
- g_atm_priv_data.wtx_pdu++;
-
- /* update descriptor send pointer */
- if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
- dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
- g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
-
- /* write discriptor to memory and write back cache */
- g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
- dma_cache_wback((unsigned long)skb->data, skb->len);
-
- dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, 0, conn, 1);
-
- mailbox_signal(conn, 1);
-
- adsl_led_flash();
-
- return 0;
-
-FIND_VCC_FAIL:
- err("FIND_VCC_FAIL");
- g_atm_priv_data.wtx_err_pdu++;
- dev_kfree_skb_any(skb);
- return ret;
-
-PPE_SEND_FAIL:
- if ( vcc->qos.aal == ATM_AAL5 )
- g_atm_priv_data.wtx_drop_pdu++;
- if ( vcc->stats )
- atomic_inc(&vcc->stats->tx_err);
- dev_kfree_skb_any(skb);
- return ret;
-}
-
-static int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags)
-{
- int conn;
- struct uni_cell_header *uni_cell_header = (struct uni_cell_header *)cell;
- int desc_base;
- struct sk_buff *skb;
- struct tx_descriptor reg_desc = {0};
-
- if ( ((uni_cell_header->pti == ATM_PTI_SEGF5 || uni_cell_header->pti == ATM_PTI_E2EF5)
- && find_vpivci(uni_cell_header->vpi, uni_cell_header->vci) < 0)
- || ((uni_cell_header->vci == 0x03 || uni_cell_header->vci == 0x04)
- && find_vpi(uni_cell_header->vpi) < 0) )
- return -EINVAL;
-
- if ( !g_showtime ) {
- err("not in showtime");
- return -EIO;
- }
-
- conn = find_vcc(vcc);
- if ( conn < 0 ) {
- err("FIND_VCC_FAIL");
- return -EINVAL;
- }
-
- skb = alloc_skb_tx(CELL_SIZE);
- if ( skb == NULL ) {
- err("ALLOC_SKB_TX_FAIL");
- return -ENOMEM;
- }
- memcpy(skb->data, cell, CELL_SIZE);
-
- reg_desc.dataptr = (unsigned int)skb->data >> 2;
- reg_desc.datalen = CELL_SIZE;
- reg_desc.byteoff = 0;
- reg_desc.iscell = 1;
-
- reg_desc.own = 1;
- reg_desc.c = 1;
- reg_desc.sop = reg_desc.eop = 1;
-
- desc_base = get_tx_desc(conn);
- if ( desc_base < 0 ) {
- dev_kfree_skb_any(skb);
- err("ALLOC_TX_CONNECTION_FAIL");
- return -EIO;
- }
-
- if ( vcc->stats )
- atomic_inc(&vcc->stats->tx);
-
- /* update descriptor send pointer */
- if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
- dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
- g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
-
- /* write discriptor to memory and write back cache */
- g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
- dma_cache_wback((unsigned long)skb->data, CELL_SIZE);
-
- dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, 0, conn, 1);
-
- mailbox_signal(conn, 1);
-
- adsl_led_flash();
-
- return 0;
-}
-
-static int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
-{
- int conn;
-
- if ( vcc == NULL || qos == NULL )
- return -EINVAL;
-
- conn = find_vcc(vcc);
- if ( conn < 0 )
- return -EINVAL;
-
- set_qsb(vcc, qos, conn);
-
- return 0;
-}
-
-static INLINE int adsl_led_flash(void)
-{
- return ifx_mei_atm_led_blink();
-}
-
-/*
- * Description:
- * Add a 32-bit value to 64-bit value, and put result in a 64-bit variable.
- * Input:
- * opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value
- * opt2 --- unsigned int, second operand, a 32-bit unsigned integer value
- * ret --- ppe_u64_t, pointer to a variable to hold result
- * Output:
- * none
- */
-static INLINE void u64_add_u32(ppe_u64_t opt1, unsigned int opt2, ppe_u64_t *ret)
-{
- ret->l = opt1.l + opt2;
- if ( ret->l < opt1.l || ret->l < opt2 )
- ret->h++;
-}
-
-static INLINE struct sk_buff* alloc_skb_rx(void)
-{
- struct sk_buff *skb;
-
- skb = dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
- if ( skb != NULL ) {
- /* must be burst length alignment */
- if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )
- skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
- /* pub skb in reserved area "skb->data - 4" */
- *((struct sk_buff **)skb->data - 1) = skb;
- /* write back and invalidate cache */
- dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));
- /* invalidate cache */
- dma_cache_inv((unsigned long)skb->data, (unsigned int)skb->end - (unsigned int)skb->data);
- }
-
- return skb;
-}
-
-static INLINE struct sk_buff* alloc_skb_tx(unsigned int size)
-{
- struct sk_buff *skb;
-
- /* allocate memory including header and padding */
- size += TX_INBAND_HEADER_LENGTH + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES;
- size &= ~(DATA_BUFFER_ALIGNMENT - 1);
- skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);
- /* must be burst length alignment */
- if ( skb != NULL )
- skb_reserve(skb, (~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1)) + TX_INBAND_HEADER_LENGTH);
- return skb;
-}
-
-struct sk_buff* atm_alloc_tx(struct atm_vcc *vcc, unsigned int size)
-{
- int conn;
- struct sk_buff *skb;
-
- /* oversize packet */
- if ( size > aal5s_max_packet_size ) {
- err("atm_alloc_tx: oversize packet");
- return NULL;
- }
- /* send buffer overflow */
- if ( atomic_read(&sk_atm(vcc)->sk_wmem_alloc) && !atm_may_send(vcc, size) ) {
- err("atm_alloc_tx: send buffer overflow");
- return NULL;
- }
- conn = find_vcc(vcc);
- if ( conn < 0 ) {
- err("atm_alloc_tx: unknown VCC");
- return NULL;
- }
-
- skb = dev_alloc_skb(size);
- if ( skb == NULL ) {
- err("atm_alloc_tx: sk buffer is used up");
- return NULL;
- }
-
- atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
-
- return skb;
-}
-
-static INLINE void atm_free_tx_skb_vcc(struct sk_buff *skb, struct atm_vcc *vcc)
-{
- if ( vcc->pop != NULL )
- vcc->pop(vcc, skb);
- else
- dev_kfree_skb_any(skb);
-}
-
-static INLINE struct sk_buff *get_skb_rx_pointer(unsigned int dataptr)
-{
- unsigned int skb_dataptr;
- struct sk_buff *skb;
-
- skb_dataptr = ((dataptr - 1) << 2) | KSEG1;
- skb = *(struct sk_buff **)skb_dataptr;
-
- ASSERT((unsigned int)skb >= KSEG0, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb, dataptr);
- ASSERT(((unsigned int)skb->data | KSEG1) == ((dataptr << 2) | KSEG1), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb, (unsigned int)skb->data, dataptr);
-
- return skb;
-}
-
-static INLINE int get_tx_desc(unsigned int conn)
-{
- int desc_base = -1;
- struct connection *p_conn = &g_atm_priv_data.conn[conn];
-
- if ( p_conn->tx_desc[p_conn->tx_desc_pos].own == 0 ) {
- desc_base = p_conn->tx_desc_pos;
- if ( ++(p_conn->tx_desc_pos) == dma_tx_descriptor_length )
- p_conn->tx_desc_pos = 0;
- }
-
- return desc_base;
-}
-
-static INLINE void mailbox_oam_rx_handler(void)
-{
- unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM)->vlddes;
- struct rx_descriptor reg_desc;
- struct uni_cell_header *header;
- int conn;
- struct atm_vcc *vcc;
- unsigned int i;
-
- for ( i = 0; i < vlddes; i++ ) {
- do {
- reg_desc = g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos];
- } while ( reg_desc.own || !reg_desc.c ); // keep test OWN and C bit until data is ready
-
- header = (struct uni_cell_header *)&g_atm_priv_data.oam_buf[g_atm_priv_data.oam_desc_pos * RX_DMA_CH_OAM_BUF_SIZE];
-
- if ( header->pti == ATM_PTI_SEGF5 || header->pti == ATM_PTI_E2EF5 )
- conn = find_vpivci(header->vpi, header->vci);
- else if ( header->vci == 0x03 || header->vci == 0x04 )
- conn = find_vpi(header->vpi);
- else
- conn = -1;
-
- if ( conn >= 0 && g_atm_priv_data.conn[conn].vcc != NULL ) {
- vcc = g_atm_priv_data.conn[conn].vcc;
-
- if ( vcc->push_oam != NULL )
- vcc->push_oam(vcc, header);
- else
- ifx_push_oam((unsigned char *)header);
-
- adsl_led_flash();
- }
-
- reg_desc.byteoff = 0;
- reg_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
- reg_desc.own = 1;
- reg_desc.c = 0;
-
- g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos] = reg_desc;
- if ( ++g_atm_priv_data.oam_desc_pos == RX_DMA_CH_OAM_DESC_LEN )
- g_atm_priv_data.oam_desc_pos = 0;
-
- mailbox_signal(RX_DMA_CH_OAM, 0);
- }
-}
-
-static INLINE void mailbox_aal_rx_handler(void)
-{
- unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL)->vlddes;
- struct rx_descriptor reg_desc;
- int conn;
- struct atm_vcc *vcc;
- struct sk_buff *skb, *new_skb;
- struct rx_inband_trailer *trailer;
- unsigned int i;
-
- for ( i = 0; i < vlddes; i++ ) {
- do {
- reg_desc = g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos];
- } while ( reg_desc.own || !reg_desc.c ); // keep test OWN and C bit until data is ready
-
- conn = reg_desc.id;
-
- if ( g_atm_priv_data.conn[conn].vcc != NULL ) {
- vcc = g_atm_priv_data.conn[conn].vcc;
-
- skb = get_skb_rx_pointer(reg_desc.dataptr);
-
- if ( reg_desc.err ) {
- if ( vcc->qos.aal == ATM_AAL5 ) {
- trailer = (struct rx_inband_trailer *)((unsigned int)skb->data + ((reg_desc.byteoff + reg_desc.datalen + MAX_RX_PACKET_PADDING_BYTES) & ~MAX_RX_PACKET_PADDING_BYTES));
- if ( trailer->stw_crc )
- g_atm_priv_data.conn[conn].aal5_vcc_crc_err++;
- if ( trailer->stw_ovz )
- g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu++;
- g_atm_priv_data.wrx_drop_pdu++;
- }
- if ( vcc->stats ) {
- atomic_inc(&vcc->stats->rx_drop);
- atomic_inc(&vcc->stats->rx_err);
- }
- }
- else if ( atm_charge(vcc, skb->truesize) ) {
- new_skb = alloc_skb_rx();
- if ( new_skb != NULL ) {
- skb_reserve(skb, reg_desc.byteoff);
- skb_put(skb, reg_desc.datalen);
- ATM_SKB(skb)->vcc = vcc;
-
- dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, 0, conn, 0);
-
- vcc->push(vcc, skb);
-
- if ( vcc->qos.aal == ATM_AAL5 )
- g_atm_priv_data.wrx_pdu++;
- if ( vcc->stats )
- atomic_inc(&vcc->stats->rx);
- adsl_led_flash();
-
- reg_desc.dataptr = (unsigned int)new_skb->data >> 2;
- }
- else {
- atm_return(vcc, skb->truesize);
- if ( vcc->qos.aal == ATM_AAL5 )
- g_atm_priv_data.wrx_drop_pdu++;
- if ( vcc->stats )
- atomic_inc(&vcc->stats->rx_drop);
- }
- }
- else {
- if ( vcc->qos.aal == ATM_AAL5 )
- g_atm_priv_data.wrx_drop_pdu++;
- if ( vcc->stats )
- atomic_inc(&vcc->stats->rx_drop);
- }
- }
- else {
- g_atm_priv_data.wrx_drop_pdu++;
- }
-
- reg_desc.byteoff = 0;
- reg_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
- reg_desc.own = 1;
- reg_desc.c = 0;
-
- g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos] = reg_desc;
- if ( ++g_atm_priv_data.aal_desc_pos == dma_rx_descriptor_length )
- g_atm_priv_data.aal_desc_pos = 0;
-
- mailbox_signal(RX_DMA_CH_AAL, 0);
- }
-}
-
-#if defined(ENABLE_TASKLET) && ENABLE_TASKLET
-static void do_ppe_tasklet(unsigned long arg)
-{
- *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR;
- mailbox_oam_rx_handler();
- mailbox_aal_rx_handler();
- if ( (*MBOX_IGU1_ISR & ((1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM))) != 0 )
- tasklet_schedule(&g_dma_tasklet);
- else
- enable_irq(PPE_MAILBOX_IGU1_INT);
-}
-#endif
-
-static irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
-{
- if ( !*MBOX_IGU1_ISR )
- return IRQ_HANDLED;
-
-#if defined(ENABLE_TASKLET) && ENABLE_TASKLET
- disable_irq(PPE_MAILBOX_IGU1_INT);
- tasklet_schedule(&g_dma_tasklet);
-#else
- *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR;
- mailbox_oam_rx_handler();
- mailbox_aal_rx_handler();
-#endif
-
- return IRQ_HANDLED;
-}
-
-static INLINE void mailbox_signal(unsigned int queue, int is_tx)
-{
- if ( is_tx ) {
- while ( MBOX_IGU3_ISR_ISR(queue + FIRST_QSB_QID + 16) );
- *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue + FIRST_QSB_QID + 16);
- }
- else {
- while ( MBOX_IGU3_ISR_ISR(queue) );
- *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue);
- }
-}
-
-static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue)
-{
- unsigned int qsb_clk = ifx_get_fpi_hz();
- unsigned int qsb_qid = queue + FIRST_QSB_QID;
- union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
- union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
- unsigned int tmp;
-
-#if defined(DEBUG_QOS) && DEBUG_QOS
- if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) ) {
- static char *str_traffic_class[9] = {
- "ATM_NONE",
- "ATM_UBR",
- "ATM_CBR",
- "ATM_VBR",
- "ATM_ABR",
- "ATM_ANYCLASS",
- "ATM_VBR_RT",
- "ATM_UBR_PLUS",
- "ATM_MAX_PCR"
- };
- printk(KERN_INFO "QoS Parameters:\n");
- printk(KERN_INFO "\tAAL : %d\n", qos->aal);
- printk(KERN_INFO "\tTX Traffic Class: %s\n", str_traffic_class[qos->txtp.traffic_class]);
- printk(KERN_INFO "\tTX Max PCR : %d\n", qos->txtp.max_pcr);
- printk(KERN_INFO "\tTX Min PCR : %d\n", qos->txtp.min_pcr);
- printk(KERN_INFO "\tTX PCR : %d\n", qos->txtp.pcr);
- printk(KERN_INFO "\tTX Max CDV : %d\n", qos->txtp.max_cdv);
- printk(KERN_INFO "\tTX Max SDU : %d\n", qos->txtp.max_sdu);
- printk(KERN_INFO "\tTX SCR : %d\n", qos->txtp.scr);
- printk(KERN_INFO "\tTX MBS : %d\n", qos->txtp.mbs);
- printk(KERN_INFO "\tTX CDV : %d\n", qos->txtp.cdv);
- printk(KERN_INFO "\tRX Traffic Class: %s\n", str_traffic_class[qos->rxtp.traffic_class]);
- printk(KERN_INFO "\tRX Max PCR : %d\n", qos->rxtp.max_pcr);
- printk(KERN_INFO "\tRX Min PCR : %d\n", qos->rxtp.min_pcr);
- printk(KERN_INFO "\tRX PCR : %d\n", qos->rxtp.pcr);
- printk(KERN_INFO "\tRX Max CDV : %d\n", qos->rxtp.max_cdv);
- printk(KERN_INFO "\tRX Max SDU : %d\n", qos->rxtp.max_sdu);
- printk(KERN_INFO "\tRX SCR : %d\n", qos->rxtp.scr);
- printk(KERN_INFO "\tRX MBS : %d\n", qos->rxtp.mbs);
- printk(KERN_INFO "\tRX CDV : %d\n", qos->rxtp.cdv);
- }
-#endif // defined(DEBUG_QOS) && DEBUG_QOS
-
- /*
- * Peak Cell Rate (PCR) Limiter
- */
- if ( qos->txtp.max_pcr == 0 )
- qsb_queue_parameter_table.bit.tp = 0; /* disable PCR limiter */
- else {
- /* peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */
- tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.max_pcr + 1;
- /* check if overflow takes place */
- qsb_queue_parameter_table.bit.tp = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
- }
-
- // A funny issue. Create two PVCs, one UBR and one UBR with max_pcr.
- // Send packets to these two PVCs at same time, it trigger strange behavior.
- // In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000.
- // In A4, PPE firmware keep emiting unknown cell and do not respond to driver.
- // To work around, create UBR always with max_pcr.
- // If user want to create UBR without max_pcr, we give a default one larger than line-rate.
- if ( qos->txtp.traffic_class == ATM_UBR && qsb_queue_parameter_table.bit.tp == 0 ) {
- int port = g_atm_priv_data.conn[queue].port;
- unsigned int max_pcr = g_atm_priv_data.port[port].tx_max_cell_rate + 1000;
-
- tmp = ((qsb_clk * qsb_tstep) >> 5) / max_pcr + 1;
- if ( tmp > QSB_TP_TS_MAX )
- tmp = QSB_TP_TS_MAX;
- else if ( tmp < 1 )
- tmp = 1;
- qsb_queue_parameter_table.bit.tp = tmp;
- }
-
- /*
- * Weighted Fair Queueing Factor (WFQF)
- */
- switch ( qos->txtp.traffic_class ) {
- case ATM_CBR:
- case ATM_VBR_RT:
- /* real time queue gets weighted fair queueing bypass */
- qsb_queue_parameter_table.bit.wfqf = 0;
- break;
- case ATM_VBR_NRT:
- case ATM_UBR_PLUS:
- /* WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates */
- /* WFQF is maximum cell rate / garenteed cell rate */
- /* wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate */
- if ( qos->txtp.min_pcr == 0 )
- qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
- else
- {
- tmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr;
- if ( tmp == 0 )
- qsb_queue_parameter_table.bit.wfqf = 1;
- else if ( tmp > QSB_WFQ_NONUBR_MAX )
- qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
- else
- qsb_queue_parameter_table.bit.wfqf = tmp;
- }
- break;
- default:
- case ATM_UBR:
- qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_UBR_BYPASS;
- }
-
- /*
- * Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1
- */
- if ( qos->txtp.traffic_class == ATM_VBR_RT || qos->txtp.traffic_class == ATM_VBR_NRT ) {
- if ( qos->txtp.scr == 0 ) {
- /* disable shaper */
- qsb_queue_vbr_parameter_table.bit.taus = 0;
- qsb_queue_vbr_parameter_table.bit.ts = 0;
- }
- else {
- /* Cell Loss Priority (CLP) */
- if ( (vcc->atm_options & ATM_ATMOPT_CLP) )
- /* CLP1 */
- qsb_queue_parameter_table.bit.vbr = 1;
- else
- /* CLP0 */
- qsb_queue_parameter_table.bit.vbr = 0;
- /* Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */
- tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.scr + 1;
- qsb_queue_vbr_parameter_table.bit.ts = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
- tmp = (qos->txtp.mbs - 1) * (qsb_queue_vbr_parameter_table.bit.ts - qsb_queue_parameter_table.bit.tp) / 64;
- if ( tmp == 0 )
- qsb_queue_vbr_parameter_table.bit.taus = 1;
- else if ( tmp > QSB_TAUS_MAX )
- qsb_queue_vbr_parameter_table.bit.taus = QSB_TAUS_MAX;
- else
- qsb_queue_vbr_parameter_table.bit.taus = tmp;
- }
- }
- else {
- qsb_queue_vbr_parameter_table.bit.taus = 0;
- qsb_queue_vbr_parameter_table.bit.ts = 0;
- }
-
- /* Queue Parameter Table (QPT) */
- *QSB_RTM = QSB_RTM_DM_SET(QSB_QPT_SET_MASK);
- *QSB_RTD = QSB_RTD_TTV_SET(qsb_queue_parameter_table.dword);
- *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
-#if defined(DEBUG_QOS) && DEBUG_QOS
- if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) )
- printk("QPT: QSB_RTM (%08X) = 0x%08X, QSB_RTD (%08X) = 0x%08X, QSB_RAMAC (%08X) = 0x%08X\n", (unsigned int)QSB_RTM, *QSB_RTM, (unsigned int)QSB_RTD, *QSB_RTD, (unsigned int)QSB_RAMAC, *QSB_RAMAC);
-#endif
- /* Queue VBR Paramter Table (QVPT) */
- *QSB_RTM = QSB_RTM_DM_SET(QSB_QVPT_SET_MASK);
- *QSB_RTD = QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table.dword);
- *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
-#if defined(DEBUG_QOS) && DEBUG_QOS
- if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) )
- printk("QVPT: QSB_RTM (%08X) = 0x%08X, QSB_RTD (%08X) = 0x%08X, QSB_RAMAC (%08X) = 0x%08X\n", (unsigned int)QSB_RTM, *QSB_RTM, (unsigned int)QSB_RTD, *QSB_RTD, (unsigned int)QSB_RAMAC, *QSB_RAMAC);
-#endif
-
-#if defined(DEBUG_QOS) && DEBUG_QOS
- if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) ) {
- printk("set_qsb\n");
- printk(" qsb_clk = %lu\n", (unsigned long)qsb_clk);
- printk(" qsb_queue_parameter_table.bit.tp = %d\n", (int)qsb_queue_parameter_table.bit.tp);
- printk(" qsb_queue_parameter_table.bit.wfqf = %d (0x%08X)\n", (int)qsb_queue_parameter_table.bit.wfqf, (int)qsb_queue_parameter_table.bit.wfqf);
- printk(" qsb_queue_parameter_table.bit.vbr = %d\n", (int)qsb_queue_parameter_table.bit.vbr);
- printk(" qsb_queue_parameter_table.dword = 0x%08X\n", (int)qsb_queue_parameter_table.dword);
- printk(" qsb_queue_vbr_parameter_table.bit.ts = %d\n", (int)qsb_queue_vbr_parameter_table.bit.ts);
- printk(" qsb_queue_vbr_parameter_table.bit.taus = %d\n", (int)qsb_queue_vbr_parameter_table.bit.taus);
- printk(" qsb_queue_vbr_parameter_table.dword = 0x%08X\n", (int)qsb_queue_vbr_parameter_table.dword);
- }
-#endif
-}
-
-static void qsb_global_set(void)
-{
- unsigned int qsb_clk = ifx_get_fpi_hz();
- int i;
- unsigned int tmp1, tmp2, tmp3;
-
- *QSB_ICDV = QSB_ICDV_TAU_SET(qsb_tau);
- *QSB_SBL = QSB_SBL_SBL_SET(qsb_srvm);
- *QSB_CFG = QSB_CFG_TSTEPC_SET(qsb_tstep >> 1);
-#if defined(DEBUG_QOS) && DEBUG_QOS
- if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) ) {
- printk("qsb_clk = %u\n", qsb_clk);
- printk("QSB_ICDV (%08X) = %d (%d), QSB_SBL (%08X) = %d (%d), QSB_CFG (%08X) = %d (%d)\n", (unsigned int)QSB_ICDV, *QSB_ICDV, QSB_ICDV_TAU_SET(qsb_tau), (unsigned int)QSB_SBL, *QSB_SBL, QSB_SBL_SBL_SET(qsb_srvm), (unsigned int)QSB_CFG, *QSB_CFG, QSB_CFG_TSTEPC_SET(qsb_tstep >> 1));
- }
-#endif
-
- /*
- * set SCT and SPT per port
- */
- for ( i = 0; i < ATM_PORT_NUMBER; i++ ) {
- if ( g_atm_priv_data.port[i].tx_max_cell_rate != 0 ) {
- tmp1 = ((qsb_clk * qsb_tstep) >> 1) / g_atm_priv_data.port[i].tx_max_cell_rate;
- tmp2 = tmp1 >> 6; /* integer value of Tsb */
- tmp3 = (tmp1 & ((1 << 6) - 1)) + 1; /* fractional part of Tsb */
- /* carry over to integer part (?) */
- if ( tmp3 == (1 << 6) )
- {
- tmp3 = 0;
- tmp2++;
- }
- if ( tmp2 == 0 )
- tmp2 = tmp3 = 1;
- /* 1. set mask */
- /* 2. write value to data transfer register */
- /* 3. start the tranfer */
- /* SCT (FracRate) */
- *QSB_RTM = QSB_RTM_DM_SET(QSB_SET_SCT_MASK);
- *QSB_RTD = QSB_RTD_TTV_SET(tmp3);
- *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(i & 0x01);
-#if defined(DEBUG_QOS) && DEBUG_QOS
- if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) )
- printk("SCT: QSB_RTM (%08X) = 0x%08X, QSB_RTD (%08X) = 0x%08X, QSB_RAMAC (%08X) = 0x%08X\n", (unsigned int)QSB_RTM, *QSB_RTM, (unsigned int)QSB_RTD, *QSB_RTD, (unsigned int)QSB_RAMAC, *QSB_RAMAC);
-#endif
- /* SPT (SBV + PN + IntRage) */
- *QSB_RTM = QSB_RTM_DM_SET(QSB_SET_SPT_MASK);
- *QSB_RTD = QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID | QSB_SPT_PN_SET(i & 0x01) | QSB_SPT_INTRATE_SET(tmp2));
- *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(i & 0x01);
-#if defined(DEBUG_QOS) && DEBUG_QOS
- if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) )
- printk("SPT: QSB_RTM (%08X) = 0x%08X, QSB_RTD (%08X) = 0x%08X, QSB_RAMAC (%08X) = 0x%08X\n", (unsigned int)QSB_RTM, *QSB_RTM, (unsigned int)QSB_RTD, *QSB_RTD, (unsigned int)QSB_RAMAC, *QSB_RAMAC);
-#endif
- }
- }
-}
-
-static INLINE void set_htu_entry(unsigned int vpi, unsigned int vci, unsigned int queue, int aal5, int is_retx)
-{
- struct htu_entry htu_entry = { res1: 0x00,
- clp: is_retx ? 0x01 : 0x00,
- pid: g_atm_priv_data.conn[queue].port & 0x01,
- vpi: vpi,
- vci: vci,
- pti: 0x00,
- vld: 0x01};
-
- struct htu_mask htu_mask = { set: 0x01,
-#if !defined(ENABLE_ATM_RETX) || !ENABLE_ATM_RETX
- clp: 0x01,
- pid_mask: 0x02,
-#else
- clp: g_retx_htu ? 0x00 : 0x01,
- pid_mask: RETX_MODE_CFG->retx_en ? 0x03 : 0x02,
-#endif
- vpi_mask: 0x00,
-#if !defined(ENABLE_ATM_RETX) || !ENABLE_ATM_RETX
- vci_mask: 0x0000,
-#else
- vci_mask: RETX_MODE_CFG->retx_en ? 0xFF00 : 0x0000,
-#endif
- pti_mask: 0x03, // 0xx, user data
- clear: 0x00};
-
- struct htu_result htu_result = {res1: 0x00,
- cellid: queue,
- res2: 0x00,
- type: aal5 ? 0x00 : 0x01,
- ven: 0x01,
- res3: 0x00,
- qid: queue};
-
- *HTU_RESULT(queue + OAM_HTU_ENTRY_NUMBER) = htu_result;
- *HTU_MASK(queue + OAM_HTU_ENTRY_NUMBER) = htu_mask;
- *HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER) = htu_entry;
-}
-
-static INLINE void clear_htu_entry(unsigned int queue)
-{
- HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)->vld = 0;
-}
-
-static void validate_oam_htu_entry(void)
-{
- HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 1;
- HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 1;
- HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 1;
-#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
- HTU_ENTRY(OAM_ARQ_HTU_ENTRY)->vld = 1;
-#endif
-}
-
-static void invalidate_oam_htu_entry(void)
-{
- HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 0;
- HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 0;
- HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 0;
-#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
- HTU_ENTRY(OAM_ARQ_HTU_ENTRY)->vld = 0;
-#endif
-}
-
-static INLINE int find_vpi(unsigned int vpi)
-{
- int i;
- unsigned int bit;
-
- for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
- if ( (g_atm_priv_data.conn_table & bit) != 0
- && g_atm_priv_data.conn[i].vcc != NULL
- && vpi == g_atm_priv_data.conn[i].vcc->vpi )
- return i;
- }
-
- return -1;
-}
-
-static INLINE int find_vpivci(unsigned int vpi, unsigned int vci)
-{
- int i;
- unsigned int bit;
-
- for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
- if ( (g_atm_priv_data.conn_table & bit) != 0
- && g_atm_priv_data.conn[i].vcc != NULL
- && vpi == g_atm_priv_data.conn[i].vcc->vpi
- && vci == g_atm_priv_data.conn[i].vcc->vci )
- return i;
- }
-
- return -1;
-}
-
-static INLINE int find_vcc(struct atm_vcc *vcc)
-{
- int i;
- unsigned int bit;
-
- for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
- if ( (g_atm_priv_data.conn_table & bit) != 0
- && g_atm_priv_data.conn[i].vcc == vcc )
- return i;
- }
-
- return -1;
-}
-
-#if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB
-static void dump_skb(struct sk_buff *skb, u32 len, char *title, int port, int ch, int is_tx)
-{
- int i;
-
- if ( !(ifx_atm_dbg_enable & (is_tx ? DBG_ENABLE_MASK_DUMP_SKB_TX : DBG_ENABLE_MASK_DUMP_SKB_RX)) )
- return;
-
- if ( skb->len < len )
- len = skb->len;
-
- if ( len > RX_DMA_CH_AAL_BUF_SIZE ) {
- printk("too big data length: skb = %08x, skb->data = %08x, skb->len = %d\n", (u32)skb, (u32)skb->data, skb->len);
- return;
- }
-
- if ( ch >= 0 )
- printk("%s (port %d, ch %d)\n", title, port, ch);
- else
- printk("%s\n", title);
- printk(" skb->data = %08X, skb->tail = %08X, skb->len = %d\n", (u32)skb->data, (u32)skb->tail, (int)skb->len);
- for ( i = 1; i <= len; i++ ) {
- if ( i % 16 == 1 )
- printk(" %4d:", i - 1);
- printk(" %02X", (int)(*((char*)skb->data + i - 1) & 0xFF));
- if ( i % 16 == 0 )
- printk("\n");
- }
- if ( (i - 1) % 16 != 0 )
- printk("\n");
-}
-#endif
-
-static INLINE void proc_file_create(void)
-{
-#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
- struct proc_dir_entry *res;
-#endif
-
- g_atm_dir = proc_mkdir("driver/ifx_atm", NULL);
-
- create_proc_read_entry("version",
- 0,
- g_atm_dir,
- proc_read_version,
- NULL);
-
- res = create_proc_entry("mib",
- 0,
- g_atm_dir);
- if ( res != NULL ) {
- res->read_proc = proc_read_mib;
- res->write_proc = proc_write_mib;
- }
-
-#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
- res = create_proc_entry("dbg",
- 0,
- g_atm_dir);
- if ( res != NULL ) {
- res->read_proc = proc_read_dbg;
- res->write_proc = proc_write_dbg;
- }
-#endif
-
-#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
- create_proc_read_entry("htu",
- 0,
- g_atm_dir,
- proc_read_htu,
- NULL);
-
- create_proc_read_entry("txq",
- 0,
- g_atm_dir,
- proc_read_txq,
- NULL);
-#endif
-}
-
-static INLINE void proc_file_delete(void)
-{
-#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
- remove_proc_entry("txq", g_atm_dir);
-
- remove_proc_entry("htu", g_atm_dir);
-#endif
-
-#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
- remove_proc_entry("dbg", g_atm_dir);
-#endif
-
- remove_proc_entry("version", g_atm_dir);
-
- remove_proc_entry("driver/ifx_atm", NULL);
-}
-
-static int proc_read_version(char *buf, char **start, off_t offset, int count, int *eof, void *data)
-{
- int len = 0;
-
- len += ifx_atm_version(buf + len);
-
- if ( offset >= len ) {
- *start = buf;
- *eof = 1;
- return 0;
- }
- *start = buf + offset;
- if ( (len -= offset) > count )
- return count;
- *eof = 1;
- return len;
-}
-
-static int proc_read_mib(char *page, char **start, off_t off, int count, int *eof, void *data)
-{
- int len = 0;
-
- len += sprintf(page + off + len, "Firmware\n");
- len += sprintf(page + off + len, " wrx_drophtu_cell = %u\n", WAN_MIB_TABLE->wrx_drophtu_cell);
- len += sprintf(page + off + len, " wrx_dropdes_pdu = %u\n", WAN_MIB_TABLE->wrx_dropdes_pdu);
- len += sprintf(page + off + len, " wrx_correct_pdu = %u\n", WAN_MIB_TABLE->wrx_correct_pdu);
- len += sprintf(page + off + len, " wrx_err_pdu = %u\n", WAN_MIB_TABLE->wrx_err_pdu);
- len += sprintf(page + off + len, " wrx_dropdes_cell = %u\n", WAN_MIB_TABLE->wrx_dropdes_cell);
- len += sprintf(page + off + len, " wrx_correct_cell = %u\n", WAN_MIB_TABLE->wrx_correct_cell);
- len += sprintf(page + off + len, " wrx_err_cell = %u\n", WAN_MIB_TABLE->wrx_err_cell);
- len += sprintf(page + off + len, " wrx_total_byte = %u\n", WAN_MIB_TABLE->wrx_total_byte);
- len += sprintf(page + off + len, " wtx_total_pdu = %u\n", WAN_MIB_TABLE->wtx_total_pdu);
- len += sprintf(page + off + len, " wtx_total_cell = %u\n", WAN_MIB_TABLE->wtx_total_cell);
- len += sprintf(page + off + len, " wtx_total_byte = %u\n", WAN_MIB_TABLE->wtx_total_byte);
- len += sprintf(page + off + len, "Driver\n");
- len += sprintf(page + off + len, " wrx_pdu = %u\n", g_atm_priv_data.wrx_pdu);
- len += sprintf(page + off + len, " wrx_drop_pdu = %u\n", g_atm_priv_data.wrx_drop_pdu);
- len += sprintf(page + off + len, " wtx_pdu = %u\n", g_atm_priv_data.wtx_pdu);
- len += sprintf(page + off + len, " wtx_err_pdu = %u\n", g_atm_priv_data.wtx_err_pdu);
- len += sprintf(page + off + len, " wtx_drop_pdu = %u\n", g_atm_priv_data.wtx_drop_pdu);
-
- *eof = 1;
-
- return len;
-}
-
-static int proc_write_mib(struct file *file, const char *buf, unsigned long count, void *data)
-{
- char str[2048];
- char *p;
- int len, rlen;
-
- len = count < sizeof(str) ? count : sizeof(str) - 1;
- rlen = len - copy_from_user(str, buf, len);
- while ( rlen && str[rlen - 1] <= ' ' )
- rlen--;
- str[rlen] = 0;
- for ( p = str; *p && *p <= ' '; p++, rlen-- );
- if ( !*p )
- return 0;
-
- if ( stricmp(p, "clear") == 0 || stricmp(p, "clear all") == 0
- || stricmp(p, "clean") == 0 || stricmp(p, "clean all") == 0 ) {
- memset(WAN_MIB_TABLE, 0, sizeof(*WAN_MIB_TABLE));
- g_atm_priv_data.wrx_pdu = 0;
- g_atm_priv_data.wrx_drop_pdu = 0;
- g_atm_priv_data.wtx_pdu = 0;
- g_atm_priv_data.wtx_err_pdu = 0;
- g_atm_priv_data.wtx_drop_pdu = 0;
- }
-
- return count;
-}
-
-#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
-
-static int proc_read_dbg(char *page, char **start, off_t off, int count, int *eof, void *data)
-{
- int len = 0;
-
- len += sprintf(page + off + len, "error print - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ERR) ? "enabled" : "disabled");
- len += sprintf(page + off + len, "debug print - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DEBUG_PRINT) ? "enabled" : "disabled");
- len += sprintf(page + off + len, "assert - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ASSERT) ? "enabled" : "disabled");
- len += sprintf(page + off + len, "dump rx skb - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_SKB_RX) ? "enabled" : "disabled");
- len += sprintf(page + off + len, "dump tx skb - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_SKB_TX) ? "enabled" : "disabled");
- len += sprintf(page + off + len, "qos - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) ? "enabled" : "disabled");
- len += sprintf(page + off + len, "dump init - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_INIT) ? "enabled" : "disabled");
-
- *eof = 1;
-
- return len;
-}
-
-static int proc_write_dbg(struct file *file, const char *buf, unsigned long count, void *data)
-{
- static const char *dbg_enable_mask_str[] = {
- " error print",
- " err",
- " debug print",
- " dbg",
- " assert",
- " assert",
- " dump rx skb",
- " rx",
- " dump tx skb",
- " tx",
- " dump qos",
- " qos",
- " dump init",
- " init",
- " all"
- };
- static const int dbg_enable_mask_str_len[] = {
- 12, 4,
- 12, 4,
- 7, 7,
- 12, 3,
- 12, 3,
- 9, 4,
- 10, 5,
- 4
- };
- u32 dbg_enable_mask[] = {
- DBG_ENABLE_MASK_ERR,
- DBG_ENABLE_MASK_DEBUG_PRINT,
- DBG_ENABLE_MASK_ASSERT,
- DBG_ENABLE_MASK_DUMP_SKB_RX,
- DBG_ENABLE_MASK_DUMP_SKB_TX,
- DBG_ENABLE_MASK_DUMP_QOS,
- DBG_ENABLE_MASK_DUMP_INIT,
- DBG_ENABLE_MASK_ALL
- };
-
- char str[2048];
- char *p;
-
- int len, rlen;
-
- int f_enable = 0;
- int i;
-
- len = count < sizeof(str) ? count : sizeof(str) - 1;
- rlen = len - copy_from_user(str, buf, len);
- while ( rlen && str[rlen - 1] <= ' ' )
- rlen--;
- str[rlen] = 0;
- for ( p = str; *p && *p <= ' '; p++, rlen-- );
- if ( !*p )
- return 0;
-
- if ( strincmp(p, "enable", 6) == 0 ) {
- p += 6;
- f_enable = 1;
- }
- else if ( strincmp(p, "disable", 7) == 0 ) {
- p += 7;
- f_enable = -1;
- }
- else if ( strincmp(p, "help", 4) == 0 || *p == '?' ) {
- printk("echo <enable/disable> [err/dbg/assert/rx/tx/init/all] > /proc/eth/dbg\n");
- }
-
- if ( f_enable ) {
- if ( *p == 0 ) {
- if ( f_enable > 0 )
- ifx_atm_dbg_enable |= DBG_ENABLE_MASK_ALL;
- else
- ifx_atm_dbg_enable &= ~DBG_ENABLE_MASK_ALL;
- }
- else {
- do {
- for ( i = 0; i < NUM_ENTITY(dbg_enable_mask_str); i++ )
- if ( strincmp(p, dbg_enable_mask_str[i], dbg_enable_mask_str_len[i]) == 0 ) {
- if ( f_enable > 0 )
- ifx_atm_dbg_enable |= dbg_enable_mask[i >> 1];
- else
- ifx_atm_dbg_enable &= ~dbg_enable_mask[i >> 1];
- p += dbg_enable_mask_str_len[i];
- break;
- }
- } while ( i < NUM_ENTITY(dbg_enable_mask_str) );
- }
- }
-
- return count;
-}
-
-#endif
-
-#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
-
-static INLINE int print_htu(char *buf, int i)
-{
- int len = 0;
-
- if ( HTU_ENTRY(i)->vld ) {
- len += sprintf(buf + len, "%2d. valid\n", i);
- len += sprintf(buf + len, " entry 0x%08x - pid %01x vpi %02x vci %04x pti %01x\n", *(u32*)HTU_ENTRY(i), HTU_ENTRY(i)->pid, HTU_ENTRY(i)->vpi, HTU_ENTRY(i)->vci, HTU_ENTRY(i)->pti);
- len += sprintf(buf + len, " mask 0x%08x - pid %01x vpi %02x vci %04x pti %01x\n", *(u32*)HTU_MASK(i), HTU_MASK(i)->pid_mask, HTU_MASK(i)->vpi_mask, HTU_MASK(i)->vci_mask, HTU_MASK(i)->pti_mask);
- len += sprintf(buf + len, " result 0x%08x - type: %s, qid: %d", *(u32*)HTU_RESULT(i), HTU_RESULT(i)->type ? "cell" : "AAL5", HTU_RESULT(i)->qid);
- if ( HTU_RESULT(i)->type )
- len += sprintf(buf + len, ", cell id: %d, verification: %s", HTU_RESULT(i)->cellid, HTU_RESULT(i)->ven ? "on" : "off");
- len += sprintf(buf + len, "\n");
- }
- else
- len += sprintf(buf + len, "%2d. invalid\n", i);
-
- return len;
-}
-
-static int proc_read_htu(char *page, char **start, off_t off, int count, int *eof, void *data)
-{
- int len = 0;
- int len_max = off + count;
- char *pstr;
- char str[1024];
- int llen;
-
- int htuts = *CFG_WRX_HTUTS;
- int i;
-
- pstr = *start = page;
-
- llen = sprintf(pstr, "HTU Table (Max %d):\n", htuts);
- pstr += llen;
- len += llen;
-
- for ( i = 0; i < htuts; i++ ) {
- llen = print_htu(str, i);
- if ( len <= off && len + llen > off ) {
- memcpy(pstr, str + off - len, len + llen - off);
- pstr += len + llen - off;
- }
- else if ( len > off ) {
- memcpy(pstr, str, llen);
- pstr += llen;
- }
- len += llen;
- if ( len >= len_max )
- goto PROC_READ_HTU_OVERRUN_END;
- }
-
- *eof = 1;
-
- return len - off;
-
-PROC_READ_HTU_OVERRUN_END:
-
- return len - llen - off;
-}
-
-static INLINE int print_tx_queue(char *buf, int i)
-{
- int len = 0;
-
- if ( (*WTX_DMACH_ON & (1 << i)) ) {
- len += sprintf(buf + len, "%2d. valid\n", i);
- len += sprintf(buf + len, " queue 0x%08x - sbid %u, qsb %s\n", *(u32*)WTX_QUEUE_CONFIG(i), (unsigned int)WTX_QUEUE_CONFIG(i)->sbid, WTX_QUEUE_CONFIG(i)->qsben ? "enable" : "disable");
- len += sprintf(buf + len, " dma 0x%08x - base %08x, len %u, vlddes %u\n", *(u32*)WTX_DMA_CHANNEL_CONFIG(i), WTX_DMA_CHANNEL_CONFIG(i)->desba, WTX_DMA_CHANNEL_CONFIG(i)->deslen, WTX_DMA_CHANNEL_CONFIG(i)->vlddes);
- }
- else
- len += sprintf(buf + len, "%2d. invalid\n", i);
-
- return len;
-}
-
-static int proc_read_txq(char *page, char **start, off_t off, int count, int *eof, void *data)
-{
- int len = 0;
- int len_max = off + count;
- char *pstr;
- char str[1024];
- int llen;
-
- int i;
-
- pstr = *start = page;
-
- llen = sprintf(pstr, "TX Queue Config (Max %d):\n", *CFG_WTX_DCHNUM);
- pstr += llen;
- len += llen;
-
- for ( i = 0; i < 16; i++ ) {
- llen = print_tx_queue(str, i);
- if ( len <= off && len + llen > off ) {
- memcpy(pstr, str + off - len, len + llen - off);
- pstr += len + llen - off;
- }
- else if ( len > off ) {
- memcpy(pstr, str, llen);
- pstr += llen;
- }
- len += llen;
- if ( len >= len_max )
- goto PROC_READ_HTU_OVERRUN_END;
- }
-
- *eof = 1;
-
- return len - off;
-
-PROC_READ_HTU_OVERRUN_END:
-
- return len - llen - off;
-}
-
-#endif
-
-static int stricmp(const char *p1, const char *p2)
-{
- int c1, c2;
-
- while ( *p1 && *p2 )
- {
- c1 = *p1 >= 'A' && *p1 <= 'Z' ? *p1 + 'a' - 'A' : *p1;
- c2 = *p2 >= 'A' && *p2 <= 'Z' ? *p2 + 'a' - 'A' : *p2;
- if ( (c1 -= c2) )
- return c1;
- p1++;
- p2++;
- }
-
- return *p1 - *p2;
-}
-
-#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
-static int strincmp(const char *p1, const char *p2, int n)
-{
- int c1 = 0, c2;
-
- while ( n && *p1 && *p2 )
- {
- c1 = *p1 >= 'A' && *p1 <= 'Z' ? *p1 + 'a' - 'A' : *p1;
- c2 = *p2 >= 'A' && *p2 <= 'Z' ? *p2 + 'a' - 'A' : *p2;
- if ( (c1 -= c2) )
- return c1;
- p1++;
- p2++;
- n--;
- }
-
- return n ? *p1 - *p2 : c1;
-}
-#endif
-
-static INLINE int ifx_atm_version(char *buf)
-{
- int len = 0;
- unsigned int major, minor;
-
- ifx_atm_get_fw_ver(&major, &minor);
-
- len += sprintf(buf + len, "Infineon Technologies ATM driver version %d.%d.%d\n", IFX_ATM_VER_MAJOR, IFX_ATM_VER_MID, IFX_ATM_VER_MINOR);
- len += sprintf(buf + len, "Infineon Technologies ATM (A1) firmware version %d.%d\n", major, minor);
-
- return len;
-}
-
-#ifdef MODULE
-static INLINE void reset_ppe(void)
-{
- // TODO:
-}
-#endif
-
-static INLINE void check_parameters(void)
-{
- /* Please refer to Amazon spec 15.4 for setting these values. */
- if ( qsb_tau < 1 )
- qsb_tau = 1;
- if ( qsb_tstep < 1 )
- qsb_tstep = 1;
- else if ( qsb_tstep > 4 )
- qsb_tstep = 4;
- else if ( qsb_tstep == 3 )
- qsb_tstep = 2;
-
- /* There is a delay between PPE write descriptor and descriptor is */
- /* really stored in memory. Host also has this delay when writing */
- /* descriptor. So PPE will use this value to determine if the write */
- /* operation makes effect. */
- if ( write_descriptor_delay < 0 )
- write_descriptor_delay = 0;
-
- if ( aal5_fill_pattern < 0 )
- aal5_fill_pattern = 0;
- else
- aal5_fill_pattern &= 0xFF;
-
- /* Because of the limitation of length field in descriptors, the packet */
- /* size could not be larger than 64K minus overhead size. */
- if ( aal5r_max_packet_size < 0 )
- aal5r_max_packet_size = 0;
- else if ( aal5r_max_packet_size >= 65535 - MAX_RX_FRAME_EXTRA_BYTES )
- aal5r_max_packet_size = 65535 - MAX_RX_FRAME_EXTRA_BYTES;
- if ( aal5r_min_packet_size < 0 )
- aal5r_min_packet_size = 0;
- else if ( aal5r_min_packet_size > aal5r_max_packet_size )
- aal5r_min_packet_size = aal5r_max_packet_size;
- if ( aal5s_max_packet_size < 0 )
- aal5s_max_packet_size = 0;
- else if ( aal5s_max_packet_size >= 65535 - MAX_TX_FRAME_EXTRA_BYTES )
- aal5s_max_packet_size = 65535 - MAX_TX_FRAME_EXTRA_BYTES;
- if ( aal5s_min_packet_size < 0 )
- aal5s_min_packet_size = 0;
- else if ( aal5s_min_packet_size > aal5s_max_packet_size )
- aal5s_min_packet_size = aal5s_max_packet_size;
-
- if ( dma_rx_descriptor_length < 2 )
- dma_rx_descriptor_length = 2;
- if ( dma_tx_descriptor_length < 2 )
- dma_tx_descriptor_length = 2;
- if ( dma_rx_clp1_descriptor_threshold < 0 )
- dma_rx_clp1_descriptor_threshold = 0;
- else if ( dma_rx_clp1_descriptor_threshold > dma_rx_descriptor_length )
- dma_rx_clp1_descriptor_threshold = dma_rx_descriptor_length;
-
- if ( dma_tx_descriptor_length < 2 )
- dma_tx_descriptor_length = 2;
-}
-
-static INLINE int init_priv_data(void)
-{
- void *p;
- int i;
- struct rx_descriptor rx_desc = {0};
- struct sk_buff *skb;
- volatile struct tx_descriptor *p_tx_desc;
- struct sk_buff **ppskb;
-
- // clear atm private data structure
- memset(&g_atm_priv_data, 0, sizeof(g_atm_priv_data));
-
- // allocate memory for RX (AAL) descriptors
- p = kzalloc(dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
- if ( p == NULL )
- return IFX_ERROR;
- dma_cache_wback_inv((unsigned long)p, dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
- g_atm_priv_data.aal_desc_base = p;
- p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
- g_atm_priv_data.aal_desc = (volatile struct rx_descriptor *)p;
-
- // allocate memory for RX (OAM) descriptors
- p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
- if ( p == NULL )
- return IFX_ERROR;
- dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
- g_atm_priv_data.oam_desc_base = p;
- p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
- g_atm_priv_data.oam_desc = (volatile struct rx_descriptor *)p;
-
- // allocate memory for RX (OAM) buffer
- p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT, GFP_KERNEL);
- if ( p == NULL )
- return IFX_ERROR;
- dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
- g_atm_priv_data.oam_buf_base = p;
- p = (void *)(((unsigned int)p + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1));
- g_atm_priv_data.oam_buf = p;
-
- // allocate memory for TX descriptors
- p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
- if ( p == NULL )
- return IFX_ERROR;
- dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT);
- g_atm_priv_data.tx_desc_base = p;
-
- // allocate memory for TX skb pointers
- p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4, GFP_KERNEL);
- if ( p == NULL )
- return IFX_ERROR;
- dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4);
- g_atm_priv_data.tx_skb_base = p;
-
- // setup RX (AAL) descriptors
- rx_desc.own = 1;
- rx_desc.c = 0;
- rx_desc.sop = 1;
- rx_desc.eop = 1;
- rx_desc.byteoff = 0;
- rx_desc.id = 0;
- rx_desc.err = 0;
- rx_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
- for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
- skb = alloc_skb_rx();
- if ( skb == NULL )
- return IFX_ERROR;
- rx_desc.dataptr = ((unsigned int)skb->data >> 2) & 0x0FFFFFFF;
- g_atm_priv_data.aal_desc[i] = rx_desc;
- }
-
- // setup RX (OAM) descriptors
- p = (void *)((unsigned int)g_atm_priv_data.oam_buf | KSEG1);
- rx_desc.own = 1;
- rx_desc.c = 0;
- rx_desc.sop = 1;
- rx_desc.eop = 1;
- rx_desc.byteoff = 0;
- rx_desc.id = 0;
- rx_desc.err = 0;
- rx_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
- for ( i = 0; i < RX_DMA_CH_OAM_DESC_LEN; i++ ) {
- rx_desc.dataptr = ((unsigned int)p >> 2) & 0x0FFFFFFF;
- g_atm_priv_data.oam_desc[i] = rx_desc;
- p = (void *)((unsigned int)p + RX_DMA_CH_OAM_BUF_SIZE);
- }
-
- // setup TX descriptors and skb pointers
- p_tx_desc = (volatile struct tx_descriptor *)((((unsigned int)g_atm_priv_data.tx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
- ppskb = (struct sk_buff **)(((unsigned int)g_atm_priv_data.tx_skb_base + 3) & ~3);
- for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
- g_atm_priv_data.conn[i].tx_desc = &p_tx_desc[i * dma_tx_descriptor_length];
- g_atm_priv_data.conn[i].tx_skb = &ppskb[i * dma_tx_descriptor_length];
- }
-
- for ( i = 0; i < ATM_PORT_NUMBER; i++ )
- g_atm_priv_data.port[i].tx_max_cell_rate = DEFAULT_TX_LINK_RATE;
-
- return IFX_SUCCESS;
-}
-
-static INLINE void clear_priv_data(void)
-{
- int i, j;
- struct sk_buff *skb;
-
- for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
- if ( g_atm_priv_data.conn[i].tx_skb != NULL ) {
- for ( j = 0; j < dma_tx_descriptor_length; j++ )
- if ( g_atm_priv_data.conn[i].tx_skb[j] != NULL )
- dev_kfree_skb_any(g_atm_priv_data.conn[i].tx_skb[j]);
- }
- }
-
- if ( g_atm_priv_data.tx_skb_base != NULL )
- kfree(g_atm_priv_data.tx_skb_base);
-
- if ( g_atm_priv_data.tx_desc_base != NULL )
- kfree(g_atm_priv_data.tx_desc_base);
-
- if ( g_atm_priv_data.oam_buf_base != NULL )
- kfree(g_atm_priv_data.oam_buf_base);
-
- if ( g_atm_priv_data.oam_desc_base != NULL )
- kfree(g_atm_priv_data.oam_desc_base);
-
- if ( g_atm_priv_data.aal_desc_base != NULL ) {
- for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
- if ( g_atm_priv_data.aal_desc[i].sop || g_atm_priv_data.aal_desc[i].eop ) { // descriptor initialized
- skb = get_skb_rx_pointer(g_atm_priv_data.aal_desc[i].dataptr);
- dev_kfree_skb_any(skb);
- }
- }
- kfree(g_atm_priv_data.aal_desc_base);
- }
-}
-
-static INLINE void init_rx_tables(void)
-{
- int i;
- struct wrx_queue_config wrx_queue_config = {0};
- struct wrx_dma_channel_config wrx_dma_channel_config = {0};
- struct htu_entry htu_entry = {0};
- struct htu_result htu_result = {0};
- struct htu_mask htu_mask = { set: 0x01,
- clp: 0x01,
- pid_mask: 0x00,
- vpi_mask: 0x00,
- vci_mask: 0x00,
- pti_mask: 0x00,
- clear: 0x00};
-
- /*
- * General Registers
- */
- *CFG_WRX_HTUTS = MAX_PVC_NUMBER + OAM_HTU_ENTRY_NUMBER;
- *CFG_WRX_QNUM = MAX_QUEUE_NUMBER;
- *CFG_WRX_DCHNUM = RX_DMA_CH_TOTAL;
- *WRX_DMACH_ON = (1 << RX_DMA_CH_TOTAL) - 1;
- *WRX_HUNT_BITTH = DEFAULT_RX_HUNT_BITTH;
-
- /*
- * WRX Queue Configuration Table
- */
- wrx_queue_config.uumask = 0;
- wrx_queue_config.cpimask = 0;
- wrx_queue_config.uuexp = 0;
- wrx_queue_config.cpiexp = 0;
- wrx_queue_config.mfs = aal5r_max_packet_size;
- wrx_queue_config.oversize = aal5r_max_packet_size;
- wrx_queue_config.undersize = aal5r_min_packet_size;
- wrx_queue_config.errdp = aal5r_drop_error_packet;
- wrx_queue_config.dmach = RX_DMA_CH_AAL;
- for ( i = 0; i < MAX_QUEUE_NUMBER; i++ )
- *WRX_QUEUE_CONFIG(i) = wrx_queue_config;
- WRX_QUEUE_CONFIG(OAM_RX_QUEUE)->dmach = RX_DMA_CH_OAM;
-
- /*
- * WRX DMA Channel Configuration Table
- */
- wrx_dma_channel_config.chrl = 0;
- wrx_dma_channel_config.clp1th = dma_rx_clp1_descriptor_threshold;
- wrx_dma_channel_config.mode = 0;
- wrx_dma_channel_config.rlcfg = 0;
-
- wrx_dma_channel_config.deslen = RX_DMA_CH_OAM_DESC_LEN;
- wrx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.oam_desc >> 2) & 0x0FFFFFFF;
- *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM) = wrx_dma_channel_config;
-
- wrx_dma_channel_config.deslen = dma_rx_descriptor_length;
- wrx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.aal_desc >> 2) & 0x0FFFFFFF;
- *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL) = wrx_dma_channel_config;
-
- /*
- * HTU Tables
- */
- for ( i = 0; i < MAX_PVC_NUMBER; i++ )
- {
- htu_result.qid = (unsigned int)i;
-
- *HTU_ENTRY(i + OAM_HTU_ENTRY_NUMBER) = htu_entry;
- *HTU_MASK(i + OAM_HTU_ENTRY_NUMBER) = htu_mask;
- *HTU_RESULT(i + OAM_HTU_ENTRY_NUMBER) = htu_result;
- }
- /* OAM HTU Entry */
- htu_entry.vci = 0x03;
- htu_mask.pid_mask = 0x03;
- htu_mask.vpi_mask = 0xFF;
- htu_mask.vci_mask = 0x0000;
- htu_mask.pti_mask = 0x07;
- htu_result.cellid = OAM_RX_QUEUE;
- htu_result.type = 1;
- htu_result.ven = 1;
- htu_result.qid = OAM_RX_QUEUE;
- *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY) = htu_result;
- *HTU_MASK(OAM_F4_SEG_HTU_ENTRY) = htu_mask;
- *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY) = htu_entry;
- htu_entry.vci = 0x04;
- htu_result.cellid = OAM_RX_QUEUE;
- htu_result.type = 1;
- htu_result.ven = 1;
- htu_result.qid = OAM_RX_QUEUE;
- *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY) = htu_result;
- *HTU_MASK(OAM_F4_TOT_HTU_ENTRY) = htu_mask;
- *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY) = htu_entry;
- htu_entry.vci = 0x00;
- htu_entry.pti = 0x04;
- htu_mask.vci_mask = 0xFFFF;
- htu_mask.pti_mask = 0x01;
- htu_result.cellid = OAM_RX_QUEUE;
- htu_result.type = 1;
- htu_result.ven = 1;
- htu_result.qid = OAM_RX_QUEUE;
- *HTU_RESULT(OAM_F5_HTU_ENTRY) = htu_result;
- *HTU_MASK(OAM_F5_HTU_ENTRY) = htu_mask;
- *HTU_ENTRY(OAM_F5_HTU_ENTRY) = htu_entry;
-#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
- htu_entry.pid = 0x0;
- htu_entry.vpi = 0x01;
- htu_entry.vci = 0x0001;
- htu_entry.pti = 0x00;
- htu_mask.pid_mask = 0x0;
- htu_mask.vpi_mask = 0x00;
- htu_mask.vci_mask = 0x0000;
- htu_mask.pti_mask = 0x3;
- htu_result.cellid = OAM_RX_QUEUE;
- htu_result.type = 1;
- htu_result.ven = 1;
- htu_result.qid = OAM_RX_QUEUE;
- *HTU_RESULT(OAM_ARQ_HTU_ENTRY) = htu_result;
- *HTU_MASK(OAM_ARQ_HTU_ENTRY) = htu_mask;
- *HTU_ENTRY(OAM_ARQ_HTU_ENTRY) = htu_entry;
-#endif
-}
-
-static INLINE void init_tx_tables(void)
-{
- int i;
- struct wtx_queue_config wtx_queue_config = {0};
- struct wtx_dma_channel_config wtx_dma_channel_config = {0};
- struct wtx_port_config wtx_port_config = { res1: 0,
- qid: 0,
- qsben: 1};
-
- /*
- * General Registers
- */
- *CFG_WTX_DCHNUM = MAX_TX_DMA_CHANNEL_NUMBER;
- *WTX_DMACH_ON = ((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1) ^ ((1 << FIRST_QSB_QID) - 1);
- *CFG_WRDES_DELAY = write_descriptor_delay;
-
- /*
- * WTX Port Configuration Table
- */
- for ( i = 0; i < ATM_PORT_NUMBER; i++ )
- *WTX_PORT_CONFIG(i) = wtx_port_config;
-
- /*
- * WTX Queue Configuration Table
- */
- wtx_queue_config.type = 0x0;
- wtx_queue_config.qsben = 1;
- wtx_queue_config.sbid = 0;
- for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ )
- *WTX_QUEUE_CONFIG(i) = wtx_queue_config;
-
- /*
- * WTX DMA Channel Configuration Table
- */
- wtx_dma_channel_config.mode = 0;
- wtx_dma_channel_config.deslen = 0;
- wtx_dma_channel_config.desba = 0;
- for ( i = 0; i < FIRST_QSB_QID; i++ )
- *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
- /* normal connection */
- wtx_dma_channel_config.deslen = dma_tx_descriptor_length;
- for ( ; i < MAX_TX_DMA_CHANNEL_NUMBER ; i++ ) {
- wtx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.conn[i - FIRST_QSB_QID].tx_desc >> 2) & 0x0FFFFFFF;
- *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
- }
-}
-
-
-
-/*
- * ####################################
- * Global Function
- * ####################################
- */
-
-static int atm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)
-{
- int i, j;
-
- ASSERT(port_cell != NULL, "port_cell is NULL");
- ASSERT(xdata_addr != NULL, "xdata_addr is NULL");
-
- for ( j = 0; j < ATM_PORT_NUMBER && j < port_cell->port_num; j++ )
- if ( port_cell->tx_link_rate[j] > 0 )
- break;
- for ( i = 0; i < ATM_PORT_NUMBER && i < port_cell->port_num; i++ )
- g_atm_priv_data.port[i].tx_max_cell_rate = port_cell->tx_link_rate[i] > 0 ? port_cell->tx_link_rate[i] : port_cell->tx_link_rate[j];
-
- qsb_global_set();
-
- for ( i = 0; i < MAX_PVC_NUMBER; i++ )
- if ( g_atm_priv_data.conn[i].vcc != NULL )
- set_qsb(g_atm_priv_data.conn[i].vcc, &g_atm_priv_data.conn[i].vcc->qos, i);
-
- // TODO: ReTX set xdata_addr
- g_xdata_addr = xdata_addr;
-
- g_showtime = 1;
-
-#if defined(CONFIG_VR9)
- IFX_REG_W32(0x0F, UTP_CFG);
-#endif
-
- printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n", g_atm_priv_data.port[0].tx_max_cell_rate, g_atm_priv_data.port[1].tx_max_cell_rate, (unsigned int)g_xdata_addr);
-
- return IFX_SUCCESS;
-}
-
-static int atm_showtime_exit(void)
-{
-#if defined(CONFIG_VR9)
- IFX_REG_W32(0x00, UTP_CFG);
-#endif
-
- g_showtime = 0;
-
- // TODO: ReTX clean state
- g_xdata_addr = NULL;
-
- printk("leave showtime\n");
-
- return IFX_SUCCESS;
-}
-
-
-
-/*
- * ####################################
- * Init/Cleanup API
- * ####################################
- */
-
-/*
- * Description:
- * Initialize global variables, PP32, comunication structures, register IRQ
- * and register device.
- * Input:
- * none
- * Output:
- * 0 --- successful
- * else --- failure, usually it is negative value of error code
- */
-static int __devinit ifx_atm_init(void)
-{
- int ret;
- int port_num;
- struct port_cell_info port_cell = {0};
- int i, j;
- char ver_str[256];
-
-#ifdef MODULE
- reset_ppe();
-#endif
-
- check_parameters();
-
- ret = init_priv_data();
- if ( ret != IFX_SUCCESS ) {
- err("INIT_PRIV_DATA_FAIL");
- goto INIT_PRIV_DATA_FAIL;
- }
-
- ifx_atm_init_chip();
- init_rx_tables();
- init_tx_tables();
-
- /* create devices */
- for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) {
- g_atm_priv_data.port[port_num].dev = atm_dev_register("ifxmips_atm", &g_ifx_atm_ops, -1, NULL);
- if ( !g_atm_priv_data.port[port_num].dev ) {
- err("failed to register atm device %d!", port_num);
- ret = -EIO;
- goto ATM_DEV_REGISTER_FAIL;
- }
- else {
- g_atm_priv_data.port[port_num].dev->ci_range.vpi_bits = 8;
- g_atm_priv_data.port[port_num].dev->ci_range.vci_bits = 16;
- g_atm_priv_data.port[port_num].dev->link_rate = g_atm_priv_data.port[port_num].tx_max_cell_rate;
- g_atm_priv_data.port[port_num].dev->dev_data = (void*)port_num;
- }
- }
-
- /* register interrupt handler */
- ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, IRQF_DISABLED, "atm_mailbox_isr", &g_atm_priv_data);
- if ( ret ) {
- if ( ret == -EBUSY ) {
- err("IRQ may be occupied by other driver, please reconfig to disable it.");
- }
- else {
- err("request_irq fail");
- }
- goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
- }
- disable_irq(PPE_MAILBOX_IGU1_INT);
-
- ret = ifx_pp32_start(0);
- if ( ret ) {
- err("ifx_pp32_start fail!");
- goto PP32_START_FAIL;
- }
-
- port_cell.port_num = ATM_PORT_NUMBER;
- ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);
- if ( g_showtime ) {
- for ( i = 0; i < ATM_PORT_NUMBER; i++ )
- if ( port_cell.tx_link_rate[i] != 0 )
- break;
- for ( j = 0; j < ATM_PORT_NUMBER; j++ )
- g_atm_priv_data.port[j].tx_max_cell_rate = port_cell.tx_link_rate[j] != 0 ? port_cell.tx_link_rate[j] : port_cell.tx_link_rate[i];
- }
-
- qsb_global_set();
- validate_oam_htu_entry();
-
- /* create proc file */
- proc_file_create();
-
- ifx_mei_atm_showtime_enter = atm_showtime_enter;
- ifx_mei_atm_showtime_exit = atm_showtime_exit;
-
- ifx_atm_version(ver_str);
- printk(KERN_INFO "%s", ver_str);
-
- printk("ifxmips_atm: ATM init succeed\n");
-
- return IFX_SUCCESS;
-
-PP32_START_FAIL:
- free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
-REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
-ATM_DEV_REGISTER_FAIL:
- while ( port_num-- > 0 )
- atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
-INIT_PRIV_DATA_FAIL:
- clear_priv_data();
- printk("ifxmips_atm: ATM init failed\n");
- return ret;
-}
-
-/*
- * Description:
- * Release memory, free IRQ, and deregister device.
- * Input:
- * none
- * Output:
- * none
- */
-static void __exit ifx_atm_exit(void)
-{
- int port_num;
-
- ifx_mei_atm_showtime_enter = NULL;
- ifx_mei_atm_showtime_exit = NULL;
-
- proc_file_delete();
-
- invalidate_oam_htu_entry();
-
- ifx_pp32_stop(0);
-
- free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
-
- for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
- atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
-
- ifx_atm_uninit_chip();
-
- clear_priv_data();
-}
-
-module_init(ifx_atm_init);
-module_exit(ifx_atm_exit);
+++ /dev/null
-/******************************************************************************
-**
-** FILE NAME : ifxmips_atm_core.h
-** PROJECT : UEIP
-** MODULES : ATM
-**
-** DATE : 7 Jul 2009
-** AUTHOR : Xu Liang
-** DESCRIPTION : ATM driver header file (core functions)
-** COPYRIGHT : Copyright (c) 2006
-** Infineon Technologies AG
-** Am Campeon 1-12, 85579 Neubiberg, Germany
-**
-** This program is free software; you can redistribute it and/or modify
-** it under the terms of the GNU General Public License as published by
-** the Free Software Foundation; either version 2 of the License, or
-** (at your option) any later version.
-**
-** HISTORY
-** $Date $Author $Comment
-** 17 JUN 2009 Xu Liang Init Version
-*******************************************************************************/
-
-#ifndef IFXMIPS_ATM_CORE_H
-#define IFXMIPS_ATM_CORE_H
-
-
-
-#include <asm/ifx/ifx_atm.h>
-#include "ifxmips_atm_ppe_common.h"
-#include "ifxmips_atm_fw_regs_common.h"
-
-
-
-/*
- * ####################################
- * Definition
- * ####################################
- */
-
-/*
- * Compile Options
- */
-
-#define ENABLE_DEBUG 1
-
-#define ENABLE_ASSERT 1
-
-#define INLINE
-
-#define DEBUG_DUMP_SKB 1
-
-#define DEBUG_QOS 1
-
-#define ENABLE_DBG_PROC 1
-
-#define ENABLE_FW_PROC 1
-
-#ifdef CONFIG_IFX_ATM_TASKLET
- #define ENABLE_TASKLET 1
-#endif
-
-
-/*
- * Debug/Assert/Error Message
- */
-
-#define DBG_ENABLE_MASK_ERR (1 << 0)
-#define DBG_ENABLE_MASK_DEBUG_PRINT (1 << 1)
-#define DBG_ENABLE_MASK_ASSERT (1 << 2)
-#define DBG_ENABLE_MASK_DUMP_SKB_RX (1 << 8)
-#define DBG_ENABLE_MASK_DUMP_SKB_TX (1 << 9)
-#define DBG_ENABLE_MASK_DUMP_QOS (1 << 10)
-#define DBG_ENABLE_MASK_DUMP_INIT (1 << 11)
-#define DBG_ENABLE_MASK_ALL (DBG_ENABLE_MASK_ERR | DBG_ENABLE_MASK_DEBUG_PRINT | DBG_ENABLE_MASK_ASSERT | DBG_ENABLE_MASK_DUMP_SKB_RX | DBG_ENABLE_MASK_DUMP_SKB_TX | DBG_ENABLE_MASK_DUMP_QOS | DBG_ENABLE_MASK_DUMP_INIT)
-
-#define err(format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ERR) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
-
-#if defined(ENABLE_DEBUG) && ENABLE_DEBUG
- #undef dbg
- #define dbg(format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DEBUG_PRINT) ) printk(KERN_WARNING __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
-#else
- #if !defined(dbg)
- #define dbg(format, arg...)
- #endif
-#endif
-
-#if defined(ENABLE_ASSERT) && ENABLE_ASSERT
- #define ASSERT(cond, format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ASSERT) && !(cond) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
-#else
- #define ASSERT(cond, format, arg...)
-#endif
-
-
-/*
- * Constants
- */
-#define DEFAULT_TX_LINK_RATE 3200 // in cells
-
-/*
- * ATM Port, QSB Queue, DMA RX/TX Channel Parameters
- */
-#define ATM_PORT_NUMBER 2
-#define MAX_QUEUE_NUMBER 16
-#define OAM_RX_QUEUE 15
-#define QSB_RESERVE_TX_QUEUE 0
-#define FIRST_QSB_QID 1
-#define MAX_PVC_NUMBER (MAX_QUEUE_NUMBER - FIRST_QSB_QID)
-#define MAX_RX_DMA_CHANNEL_NUMBER 8
-#define MAX_TX_DMA_CHANNEL_NUMBER 16
-#define DATA_BUFFER_ALIGNMENT EMA_ALIGNMENT
-#define DESC_ALIGNMENT 8
-#define DEFAULT_RX_HUNT_BITTH 4
-
-/*
- * RX DMA Channel Allocation
- */
-#define RX_DMA_CH_OAM 0
-#define RX_DMA_CH_AAL 1
-#define RX_DMA_CH_TOTAL 2
-#define RX_DMA_CH_OAM_DESC_LEN 32
-#define RX_DMA_CH_OAM_BUF_SIZE (CELL_SIZE & ~15)
-#define RX_DMA_CH_AAL_BUF_SIZE (2048 - 48)
-
-/*
- * OAM Constants
- */
-#define OAM_HTU_ENTRY_NUMBER 3
-#define OAM_F4_SEG_HTU_ENTRY 0
-#define OAM_F4_TOT_HTU_ENTRY 1
-#define OAM_F5_HTU_ENTRY 2
-#define OAM_F4_CELL_ID 0
-#define OAM_F5_CELL_ID 15
-//#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
-// #undef OAM_HTU_ENTRY_NUMBER
-// #define OAM_HTU_ENTRY_NUMBER 4
-// #define OAM_ARQ_HTU_ENTRY 3
-//#endif
-
-/*
- * RX Frame Definitions
- */
-#define MAX_RX_PACKET_ALIGN_BYTES 3
-#define MAX_RX_PACKET_PADDING_BYTES 3
-#define RX_INBAND_TRAILER_LENGTH 8
-#define MAX_RX_FRAME_EXTRA_BYTES (RX_INBAND_TRAILER_LENGTH + MAX_RX_PACKET_ALIGN_BYTES + MAX_RX_PACKET_PADDING_BYTES)
-
-/*
- * TX Frame Definitions
- */
-#define MAX_TX_HEADER_ALIGN_BYTES 12
-#define MAX_TX_PACKET_ALIGN_BYTES 3
-#define MAX_TX_PACKET_PADDING_BYTES 3
-#define TX_INBAND_HEADER_LENGTH 8
-#define MAX_TX_FRAME_EXTRA_BYTES (TX_INBAND_HEADER_LENGTH + MAX_TX_HEADER_ALIGN_BYTES + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES)
-
-/*
- * Cell Constant
- */
-#define CELL_SIZE ATM_AAL0_SDU
-
-
-
-/*
- * ####################################
- * Data Type
- * ####################################
- */
-
-typedef struct {
- unsigned int h;
- unsigned int l;
-} ppe_u64_t;
-
-struct port {
- unsigned int tx_max_cell_rate;
- unsigned int tx_current_cell_rate;
-
- struct atm_dev *dev;
-};
-
-struct connection {
- struct atm_vcc *vcc;
-
- volatile struct tx_descriptor
- *tx_desc;
- unsigned int tx_desc_pos;
- struct sk_buff **tx_skb;
-
- unsigned int aal5_vcc_crc_err; /* number of packets with CRC error */
- unsigned int aal5_vcc_oversize_sdu; /* number of packets with oversize error */
-
- unsigned int port;
-};
-
-struct atm_priv_data {
- unsigned long conn_table;
- struct connection conn[MAX_PVC_NUMBER];
-
- volatile struct rx_descriptor
- *aal_desc;
- unsigned int aal_desc_pos;
-
- volatile struct rx_descriptor
- *oam_desc;
- unsigned char *oam_buf;
- unsigned int oam_desc_pos;
-
- struct port port[ATM_PORT_NUMBER];
-
- unsigned int wrx_pdu; /* successfully received AAL5 packet */
- unsigned int wrx_drop_pdu; /* AAL5 packet dropped by driver on RX */
- unsigned int wtx_pdu; /* successfully tranmitted AAL5 packet */
- unsigned int wtx_err_pdu; /* error AAL5 packet */
- unsigned int wtx_drop_pdu; /* AAL5 packet dropped by driver on TX */
-
- ppe_u64_t wrx_total_byte;
- ppe_u64_t wtx_total_byte;
- unsigned int prev_wrx_total_byte;
- unsigned int prev_wtx_total_byte;
-
- void *aal_desc_base;
- void *oam_desc_base;
- void *oam_buf_base;
- void *tx_desc_base;
- void *tx_skb_base;
-};
-
-
-
-/*
- * ####################################
- * Declaration
- * ####################################
- */
-
-extern unsigned int ifx_atm_dbg_enable;
-
-extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor);
-
-extern void ifx_atm_init_chip(void);
-extern void ifx_atm_uninit_chip(void);
-
-extern int ifx_pp32_start(int pp32);
-extern void ifx_pp32_stop(int pp32);
-
-
-
-#endif // IFXMIPS_ATM_CORE_H
+++ /dev/null
-/******************************************************************************
-**
-** FILE NAME : ifxmips_atm_danube.c
-** PROJECT : UEIP
-** MODULES : ATM
-**
-** DATE : 7 Jul 2009
-** AUTHOR : Xu Liang
-** DESCRIPTION : ATM driver common source file (core functions)
-** COPYRIGHT : Copyright (c) 2006
-** Infineon Technologies AG
-** Am Campeon 1-12, 85579 Neubiberg, Germany
-**
-** This program is free software; you can redistribute it and/or modify
-** it under the terms of the GNU General Public License as published by
-** the Free Software Foundation; either version 2 of the License, or
-** (at your option) any later version.
-**
-** HISTORY
-** $Date $Author $Comment
-** 07 JUL 2009 Xu Liang Init Version
-*******************************************************************************/
-
-
-
-/*
- * ####################################
- * Head File
- * ####################################
- */
-
-/*
- * Common Head File
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/proc_fs.h>
-#include <linux/init.h>
-#include <linux/ioctl.h>
-#include <asm/delay.h>
-
-/*
- * Chip Specific Head File
- */
-#include <asm/ifx/ifx_types.h>
-#include <asm/ifx/ifx_regs.h>
-#include <asm/ifx/common_routines.h>
-#include <asm/ifx/ifx_pmu.h>
-#include "ifxmips_atm_core.h"
-#include "ifxmips_atm_fw_danube.h"
-
-
-
-/*
- * ####################################
- * Definition
- * ####################################
- */
-
-/*
- * EMA Settings
- */
-#define EMA_CMD_BUF_LEN 0x0040
-#define EMA_CMD_BASE_ADDR (0x00001580 << 2)
-#define EMA_DATA_BUF_LEN 0x0100
-#define EMA_DATA_BASE_ADDR (0x00001900 << 2)
-#define EMA_WRITE_BURST 0x2
-#define EMA_READ_BURST 0x2
-
-
-
-/*
- * ####################################
- * Declaration
- * ####################################
- */
-
-/*
- * Hardware Init/Uninit Functions
- */
-static inline void init_pmu(void);
-static inline void uninit_pmu(void);
-static inline void init_ema(void);
-static inline void init_mailbox(void);
-static inline void init_atm_tc(void);
-static inline void clear_share_buffer(void);
-
-
-
-/*
- * ####################################
- * Local Variable
- * ####################################
- */
-
-
-
-/*
- * ####################################
- * Local Function
- * ####################################
- */
-
-static inline void init_pmu(void)
-{
- //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
- PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
- PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
- PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
- PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
- PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
- PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
- DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
-}
-
-static inline void uninit_pmu(void)
-{
- PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
- PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
- PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
- PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
- PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
- DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
- PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
-}
-
-static inline void init_ema(void)
-{
- IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
- IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
- IFX_REG_W32(0x000000FF, EMA_IER);
- IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
-}
-
-static inline void init_mailbox(void)
-{
- IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
- IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
- IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
- IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
-}
-
-static inline void init_atm_tc(void)
-{
- // for ReTX expansion in future
- //*FFSM_CFG0 = SET_BITS(*FFSM_CFG0, 5, 0, 6); // pnum = 6
- //*FFSM_CFG1 = SET_BITS(*FFSM_CFG1, 5, 0, 6); // pnum = 6
-}
-
-static inline void clear_share_buffer(void)
-{
- volatile u32 *p = SB_RAM0_ADDR(0);
- unsigned int i;
-
- for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
- IFX_REG_W32(0, p++);
-}
-
-/*
- * Description:
- * Download PPE firmware binary code.
- * Input:
- * src --- u32 *, binary code buffer
- * dword_len --- unsigned int, binary code length in DWORD (32-bit)
- * Output:
- * int --- IFX_SUCCESS: Success
- * else: Error Code
- */
-static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
-{
- volatile u32 *dest;
-
- if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
- || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
- return IFX_ERROR;
-
- if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
- IFX_REG_W32(0x00, CDM_CFG);
- else
- IFX_REG_W32(0x02, CDM_CFG);
-
- /* copy code */
- dest = CDM_CODE_MEMORY(0, 0);
- while ( code_dword_len-- > 0 )
- IFX_REG_W32(*code_src++, dest++);
-
- /* copy data */
- dest = CDM_DATA_MEMORY(0, 0);
- while ( data_dword_len-- > 0 )
- IFX_REG_W32(*data_src++, dest++);
-
- return IFX_SUCCESS;
-}
-
-
-
-/*
- * ####################################
- * Global Function
- * ####################################
- */
-
-extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
-{
- ASSERT(major != NULL, "pointer is NULL");
- ASSERT(minor != NULL, "pointer is NULL");
-
- *major = ATM_FW_VER_MAJOR;
- *minor = ATM_FW_VER_MINOR;
-}
-
-void ifx_atm_init_chip(void)
-{
- init_pmu();
-
- init_ema();
-
- init_mailbox();
-
- init_atm_tc();
-
- clear_share_buffer();
-}
-
-void ifx_atm_uninit_chip(void)
-{
- uninit_pmu();
-}
-
-/*
- * Description:
- * Initialize and start up PP32.
- * Input:
- * none
- * Output:
- * int --- IFX_SUCCESS: Success
- * else: Error Code
- */
-int ifx_pp32_start(int pp32)
-{
- int ret;
-
- /* download firmware */
- ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
- if ( ret != IFX_SUCCESS )
- return ret;
-
- /* run PP32 */
- IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
-
- /* idle for a while to let PP32 init itself */
- udelay(10);
-
- return IFX_SUCCESS;
-}
-
-/*
- * Description:
- * Halt PP32.
- * Input:
- * none
- * Output:
- * none
- */
-void ifx_pp32_stop(int pp32)
-{
- /* halt PP32 */
- IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
-}
+++ /dev/null
-#ifndef IFXMIPS_ATM_FW_DANUBE_H
-#define IFXMIPS_ATM_FW_DANUBE_H
-
-
-/******************************************************************************
-**
-** FILE NAME : ifxmips_atm_fw_danube.h
-** PROJECT : Danube
-** MODULES : ATM (ADSL)
-**
-** DATE : 1 AUG 2005
-** AUTHOR : Xu Liang
-** DESCRIPTION : ATM Driver (PP32 Firmware)
-** COPYRIGHT : Copyright (c) 2006
-** Infineon Technologies AG
-** Am Campeon 1-12, 85579 Neubiberg, Germany
-**
-** This program is free software; you can redistribute it and/or modify
-** it under the terms of the GNU General Public License as published by
-** the Free Software Foundation; either version 2 of the License, or
-** (at your option) any later version.
-**
-** HISTORY
-** $Date $Author $Comment
-** 4 AUG 2005 Xu Liang Initiate Version
-** 23 OCT 2006 Xu Liang Add GPL header.
-*******************************************************************************/
-
-
-#define ATM_FW_VER_MAJOR 0
-#define ATM_FW_VER_MINOR 1
-
-
-static unsigned int firmware_binary_code[] = {
- 0x800004A0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000FFC8, 0x00000000, 0x00000000, 0x00000000,
- 0xC1000002, 0xD90C0000, 0xC2000002, 0xDA080001, 0x80004710, 0xC2000000, 0xDA080001, 0x80003D98,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x80003D50, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x80004F18, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x80003C50, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0xC0400000, 0xC0004840, 0xC8840000, 0x800043D0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0xC0400002, 0xC0004840, 0xC8840000, 0x80004350, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0xC3C00004, 0xDBC80001, 0xC10C0002, 0xD90C0000, 0x8000FEC8, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0xC10E0002, 0xD90C0000, 0xC0004808, 0xC8400000, 0x80004380, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0xC3E1FFFE, 0x597DFFFE, 0x593DFE14, 0x900004D9, 0x00000000, 0x00000000, 0x00000000, 0x90CC0481,
- 0x00000000, 0x00000000, 0x00000000, 0xC3C00000, 0xDBC80001, 0xC1400008, 0xC1900000, 0x71948000,
- 0x15000100, 0xC140000A, 0xC1900002, 0x71948000, 0x15000100, 0xC140000C, 0xC1900004, 0x71948000,
- 0x15000100, 0xC1400004, 0xC1900006, 0x71948000, 0x15000100, 0xC1400006, 0xC1900008, 0x71948000,
- 0x15000100, 0xC140000E, 0xC190000A, 0x71948000, 0x15000100, 0xC1400000, 0xC190000C, 0x71948000,
- 0x15000100, 0xC1400002, 0xC190000E, 0x71948000, 0x15000100, 0xC0400000, 0xC11C0000, 0xC000082C,
- 0xCD040E08, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0400002, 0xC11C0000, 0xC000082C, 0xCD040E08,
- 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0000824, 0x00000000, 0xCBC00001, 0xCB800001, 0xCB400001,
- 0xCB000000, 0xC0004878, 0x5BFC4000, 0xCFC00001, 0x5BB84000, 0xCF800001, 0x5B744000, 0xCF400001,
- 0x5B304000, 0xCF000000, 0xC0000A10, 0x00000000, 0xCBC00001, 0xCB800000, 0xC0004874, 0x5BFC4000,
- 0xCFC00001, 0x5BB84000, 0xCF800000, 0xC30001FE, 0xC000140A, 0xCF000000, 0xC3000000, 0x7F018000,
- 0xC000042E, 0xCF000000, 0xC000040E, 0xCF000000, 0xC3C1FFFE, 0xC000490E, 0xCFC00080, 0xC000492C,
- 0xCFC00080, 0xC0004924, 0xCFC00040, 0xC0004912, 0xCFC00040, 0xC0004966, 0xCFC00040, 0xC0004968,
- 0xCFC00080, 0xC000496A, 0xCFC00080, 0xC3C00000, 0xC2800020, 0xC3000000, 0x7F018000, 0x6FF88000,
- 0x6FD44000, 0x4395C000, 0x5BB84A00, 0x5838000A, 0xCF000000, 0x5BFC0002, 0xB7E8FFA8, 0x00000000,
- 0xC3C00000, 0xC2800010, 0x6FF86000, 0x47F9C000, 0x5BB84C80, 0xC3400000, 0x58380004, 0xCB420080,
- 0x00000000, 0x58380008, 0xCF400080, 0x5BFC0002, 0xB7E8FF90, 0x00000000, 0xC3C00000, 0xC2800020,
- 0xC348001E, 0xC3000000, 0x7F018000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20,
- 0x58380008, 0xCF400420, 0x5838000A, 0xCF000000, 0x5BFC0002, 0xB7E8FF90, 0x00000000, 0x00000000,
- 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x80000518, 0x00000000, 0x80002118, 0x00000000,
- 0x8000FFC8, 0xC0004958, 0xC8400000, 0x00000000, 0xC3C00002, 0x7BC42000, 0xCC400000, 0xC0004848,
- 0xCB840000, 0xC000495C, 0xCAC40000, 0xC0004844, 0xC8840000, 0x46F90000, 0x8400FF6A, 0xC000487C,
- 0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCA000000, 0xC0001624, 0xCB040000, 0xA63C005A,
- 0x00000000, 0x00000000, 0xA71EFF02, 0x00000000, 0xC0000824, 0xCA840000, 0x6CA08000, 0x6CA42000,
- 0x46610000, 0x42290000, 0xC35E0002, 0xC6340068, 0xC0001624, 0xCF440080, 0xC2000000, 0xC161FFFE,
- 0x5955FFFE, 0x15400000, 0x00000000, 0xC0004844, 0xC8840000, 0xC000082C, 0xCA040040, 0x00000000,
- 0x00000000, 0x58880002, 0xB608FFF8, 0x00000000, 0xC0800000, 0xC0004844, 0xCC840040, 0x5AEC0002,
- 0xC000495C, 0xCEC40000, 0x5E6C0006, 0x84000048, 0xC0004848, 0xCB840000, 0xC0000838, 0xC2500002,
- 0xCE440808, 0x5FB80002, 0xC0004848, 0xCF840000, 0x5EEC0002, 0xC000495C, 0xCEC40000, 0x00000000,
- 0xC121FFFE, 0x5911FE14, 0x15000000, 0x8000FD80, 0xC000495A, 0xC8400000, 0x00000000, 0xC3C00002,
- 0x7BC42000, 0xCC400000, 0xC0004960, 0xCAC40000, 0x00000000, 0x00000000, 0x5EEC0000, 0x840000F2,
- 0x00000000, 0xB6FC0030, 0xC0001600, 0xCA040000, 0x00000000, 0x00000000, 0xA61E00B2, 0x6FE90000,
- 0xC0000A28, 0xCE840808, 0xC2C00000, 0xC2800004, 0xB6E80080, 0xC0001604, 0xCA840000, 0xC0004960,
- 0xCEC40000, 0xA69EFCA2, 0x00000000, 0x6FE90000, 0xC0000A28, 0xCE840808, 0xC2C00002, 0xC0001600,
- 0xCA040000, 0x00000000, 0x00000000, 0xA61E000A, 0x6FE90000, 0xC0000A28, 0xCE840808, 0xC2C00000,
- 0xC0001604, 0xCA840000, 0xC0004960, 0xCEC40000, 0xA69EFC0A, 0xC2400000, 0xC0000A14, 0xCA440030,
- 0x00000000, 0x00000000, 0x46E52000, 0xA4400000, 0xC2800000, 0xDFEB0031, 0x8000FFF8, 0xDFEA0031,
- 0xB668FB82, 0x00000000, 0xC00048A0, 0xCB040000, 0xC0000A10, 0xCA840000, 0x6F208000, 0x6F242000,
- 0x46610000, 0x42A10000, 0xC2400000, 0xC0000A14, 0xCA440030, 0xC35E0002, 0xC6340068, 0xC0001604,
- 0xCF440080, 0x5B300002, 0xB670FFF8, 0x5AEC0002, 0xC3000000, 0xC00048A0, 0xCF040000, 0xC0004960,
- 0xCEC40000, 0x8000FAC0, 0xC0004918, 0xD2800000, 0xC2000000, 0xDF600040, 0x5E600080, 0x8400025A,
- 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000480A, 0xCA000000, 0xC0004912,
- 0xCA400000, 0xC0004924, 0xCA800000, 0xC0004966, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14,
- 0x15000000, 0x76610000, 0x76A10000, 0x76E10000, 0x840001B2, 0xC0004918, 0xCA400000, 0xC28001FE,
- 0x76A10000, 0x5A640002, 0x6A254010, 0x5EE80000, 0x84000002, 0x6AA54000, 0x8000FFF8, 0xC6280000,
- 0x62818008, 0xC0004918, 0xCF000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0004966,
- 0xCA400000, 0xC2000002, 0x6A310000, 0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE,
- 0x5911FE14, 0x15000000, 0x6F346000, 0x4735A000, 0x5B744C80, 0xC2800000, 0x58340006, 0xCA800080,
- 0xC2C00000, 0x58340000, 0xCAC000E0, 0xC2400000, 0x5834000A, 0xCA420080, 0x6EA82000, 0x42E9E000,
- 0x6F2CA000, 0x42E56000, 0x5AEC1400, 0xC3990040, 0xC7381C20, 0xC6F80068, 0x99005930, 0xDB980000,
- 0xDBD80001, 0x00000000, 0xDEA00000, 0x47210000, 0x8400FD68, 0xC0004958, 0xC8400000, 0x00000000,
- 0xC3C00002, 0x7BC42000, 0xCC400000, 0xC0004848, 0xCB840000, 0xC0004844, 0xC8840000, 0x5FB80000,
- 0x8400F7DA, 0xC0001A1C, 0xCA000000, 0xC2400002, 0x6A452000, 0x76610000, 0x8400F7AA, 0xC000487C,
- 0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCA000000, 0xC4240000, 0x00000000, 0xA63C17BA,
- 0x00000000, 0xC0004878, 0xC8040000, 0x6C908000, 0x44908000, 0x44908000, 0x40100000, 0xCA000000,
- 0xC4240000, 0x00000000, 0xC0004934, 0xCE000000, 0xC2800002, 0xC4681C10, 0xC62821D8, 0xC2600010,
- 0x5A650040, 0xC0004800, 0xCB400000, 0xC2200400, 0x5A200000, 0xC7601048, 0xC0001220, 0xCE800000,
- 0xC0001200, 0xCE400000, 0xC0001202, 0xCE000000, 0xC0001240, 0xCB400000, 0x00000000, 0x00000000,
- 0xA754FFC0, 0xC2000000, 0xC7600048, 0xA7520022, 0x00000000, 0x00000000, 0x990060A8, 0xC0004822,
- 0xC9400000, 0xC1800002, 0x80001668, 0x58204080, 0xC2000000, 0xCA000020, 0xC2400000, 0xCA414008,
- 0xC2800000, 0xCA812008, 0xC2C00000, 0xCAC20020, 0xC0004938, 0xCE000000, 0xC0004920, 0xCE400000,
- 0xC0004916, 0xCE800000, 0xC0004922, 0xCEC00000, 0xA6400520, 0x00000000, 0xC0004938, 0xCBC00000,
- 0x00000000, 0xC3800000, 0x6FF48000, 0x6FD44000, 0x4355A000, 0x5B744A00, 0x58340000, 0xCB802018,
- 0x00000000, 0xC2000000, 0x6FB46000, 0x47B5A000, 0x5B744C80, 0x5834000C, 0xCA000028, 0xC000491A,
- 0xCF800000, 0x5E200000, 0x84000452, 0xC2000000, 0xDF610050, 0x5E6001E8, 0x8800FFD0, 0xC2000002,
- 0xC2400466, 0xC2A00000, 0x5AA80000, 0xC0001006, 0xCE000000, 0xC0001008, 0xCE400000, 0xC000100A,
- 0xCE800000, 0x99005370, 0xC1A0FFFE, 0xC0000824, 0xC9840068, 0xC0004934, 0xCA400000, 0xC2000000,
- 0xC2800002, 0x990053B0, 0xDA980000, 0xC6140000, 0xC6580000, 0xC161FFFE, 0x5955FFFE, 0x15400000,
- 0x00000000, 0x99005498, 0xC000491A, 0xC9400000, 0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE14,
- 0x15000000, 0xC0004922, 0xCA001120, 0xC3C00000, 0xC3800000, 0xC0004930, 0xCE001120, 0xC0004932,
- 0xCBC000E0, 0xC2800000, 0xC000491E, 0xCFC00000, 0xC0004862, 0xCA800068, 0xC3A0001A, 0x5BB94000,
- 0xC6B80068, 0xC000491C, 0xCF800000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0x00000000,
- 0x00000000, 0x00000000, 0xA8E2FFC8, 0xC2000000, 0xC1220002, 0xD90C0000, 0xDF600040, 0x5E600080,
- 0x8400FFDA, 0xC000491C, 0xCA000000, 0xC000491E, 0xCA400000, 0x00000000, 0x00000000, 0x99005930,
- 0xDA180000, 0xDA580001, 0x00000000, 0xC2000000, 0xDF610050, 0x5E6001FE, 0x8800FFD0, 0xC0004916,
- 0xCA800000, 0xC2C00000, 0xDFEC0050, 0xC2400000, 0x46E52000, 0x84000032, 0x5EA80000, 0x84000022,
- 0xC2600002, 0x990060A8, 0xC000482E, 0xC9400000, 0xC1800002, 0x80000018, 0xC2600000, 0x990060A8,
- 0xC000482C, 0xC9400000, 0xC1800002, 0xC2000068, 0xC6240080, 0xC0004930, 0xCE400088, 0xC000491A,
- 0xC9800000, 0xC0004862, 0xC9400000, 0x6D9C6000, 0x459CE000, 0x59DC4C80, 0x99005790, 0xD9580000,
- 0xD9980001, 0xD9D40000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0xC2000000, 0xDF600040,
- 0x5E600080, 0x8400FFD2, 0x00000000, 0xC000491C, 0xCA000000, 0xC000491E, 0xCA400000, 0x00000000,
- 0x00000000, 0x99005930, 0xDA180000, 0xDA580001, 0x00000000, 0x800010D0, 0x00000000, 0x990060A8,
- 0xC000482A, 0xC9400000, 0xC1800002, 0x800010A0, 0xC0004938, 0xCBC00000, 0x00000000, 0x00000000,
- 0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0x58380008, 0xCA000000, 0x00000000, 0x00000000,
- 0xA6000362, 0x00000000, 0xC0004938, 0xCBC00000, 0xC3000000, 0x00000000, 0x6FF88000, 0x6FD44000,
- 0x4395C000, 0x5BB84A00, 0x58380000, 0xCB002018, 0xC2000000, 0x58380008, 0xCA020080, 0x5838000C,
- 0xCAC00000, 0x5838000E, 0xCA400000, 0xC000491A, 0xCF000000, 0xC0004930, 0xCEC00000, 0xC000493C,
- 0xCE000000, 0xC0004932, 0xCE400000, 0x5E200000, 0x84000108, 0xC2800000, 0xA6FE009A, 0x6F206000,
- 0x47210000, 0x5A204C80, 0x5820000C, 0xCA800028, 0x00000000, 0x00000000, 0x5EA80000, 0x840001DA,
- 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0x99005498, 0xC000491A, 0xC9400000,
- 0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0xC0004930, 0xCAC00000, 0xC0004932,
- 0xCA400000, 0xC7EC1120, 0xC0004930, 0xCEC00000, 0x5838000C, 0xCEC00000, 0x58000002, 0xCE400000,
- 0xC0004934, 0xCA000000, 0xC2400002, 0x6E642000, 0x6E642000, 0x76252000, 0x84000012, 0xC2400002,
- 0x6E684000, 0x58380008, 0xCE800208, 0xA6000000, 0x6E682000, 0x58380008, 0xCE800108, 0xC2400002,
- 0x6E642000, 0x76252000, 0x840000D2, 0x58380008, 0xCA000000, 0xC2800000, 0xC2400000, 0xA60200A0,
- 0xDBA80000, 0x6F386000, 0x4739C000, 0x5BB84C80, 0x58380004, 0xCA400080, 0x58380002, 0xCA800080,
- 0x00000000, 0xDEB80000, 0x46694000, 0x88000048, 0x00000000, 0xC0004824, 0xCA000000, 0xC2400002,
- 0x6E640000, 0x5A200002, 0xCE000000, 0x58380008, 0xCE400008, 0x80000000, 0x00000000, 0x80000030,
- 0xC0004934, 0xCA000000, 0x00000000, 0x00000000, 0xA6020C4A, 0x00000000, 0x00000000, 0x80000C80,
- 0xC2800000, 0xC2000200, 0xC240001A, 0xDF690050, 0x46A14000, 0x46694000, 0x8800FFBA, 0xC2000006,
- 0xC2600982, 0x5A643B6E, 0x5838000A, 0xCA800000, 0xC0001006, 0xCE000000, 0xC0001008, 0xCE400000,
- 0xC000100A, 0xCE800000, 0x99005370, 0xC1A0FFFE, 0xC0000824, 0xC9840068, 0xC2000000, 0xC0004930,
- 0xCA02E010, 0x58380026, 0xCA400000, 0x00000000, 0xC2800000, 0x990053B0, 0xDA980000, 0xC6140000,
- 0xC6580000, 0xC0004934, 0xCA000000, 0x00000000, 0x00000000, 0xA6020002, 0x00000000, 0x00000000,
- 0x80000300, 0xC0004938, 0xCBC00000, 0xC0004878, 0xC8040000, 0x6C908000, 0x44908000, 0x44908000,
- 0x40100000, 0xCA000000, 0xC4240000, 0x00000000, 0x58240018, 0xCA000000, 0x6FF88000, 0x6FD44000,
- 0x4395C000, 0x5BB84A00, 0xC3000000, 0xC3400002, 0xC2C00000, 0xC62C0080, 0xC6270040, 0xC0004940,
- 0xCE400040, 0xC6260040, 0xC0004942, 0xCE400040, 0xC000493C, 0xCA000000, 0x5EEC0000, 0x84000172,
- 0x5A6C0010, 0x46614000, 0x88000178, 0x5A600052, 0x466D4000, 0x88000160, 0x58380006, 0xCA800000,
- 0xC0004940, 0xCA000000, 0xC2400000, 0xC6A70040, 0x7E412000, 0x76252000, 0xC2000000, 0xC6A10040,
- 0x46610000, 0x84000120, 0xC0004942, 0xCA000000, 0xC2400000, 0xC6A60040, 0x7E412000, 0x76252000,
- 0xC2000000, 0xC6A00040, 0x58380002, 0xCA800000, 0x46610000, 0x840000D0, 0xC2400000, 0xC6A60080,
- 0x46E50000, 0x880000C2, 0xC2400000, 0xC6A40080, 0x58380008, 0xCA800000, 0x466D0000, 0x880000A2,
- 0x00000000, 0xA682FFF8, 0x00000000, 0xC7700B08, 0xA6840078, 0x00000000, 0xC7700A08, 0x80000068,
- 0xC7700208, 0xC000493C, 0xCAC00000, 0x80000048, 0xC7700308, 0xC000493C, 0xCAC00000, 0x80000028,
- 0xC7700908, 0x80000018, 0xC7700808, 0x80000008, 0xC7700708, 0x8000FFF8, 0xC7700508, 0xC0004944,
- 0xCF000000, 0xC000493E, 0xCEC00000, 0xC0004938, 0xCA400000, 0xC000493C, 0xCB800000, 0xC000493E,
- 0xCB400000, 0xC3000000, 0x6E608000, 0x6E544000, 0x42150000, 0x5A204A00, 0x5AA00008, 0x58200004,
- 0xCB000080, 0xC0004934, 0xCA000000, 0xC2400000, 0xC0004930, 0xCA42E010, 0xC3C00018, 0xA6020078,
- 0x00000000, 0x43656000, 0x46F90000, 0x88000038, 0x47AD6000, 0x6EE04010, 0x5BE00004, 0xC2000000,
- 0xC6E00010, 0x5E200000, 0x8400002A, 0x5BFC0002, 0x80000018, 0xC3C00004, 0x5A2C0008, 0x46390000,
- 0x8800FFFA, 0x5FB80008, 0x6FE04000, 0x42390000, 0x46312000, 0x88000050, 0xC2400000, 0xC0004930,
- 0xCA42E010, 0xC2060002, 0xC6800000, 0xCE000308, 0x6FE04000, 0x4631C000, 0x5F700010, 0x4675A000,
- 0xC2000000, 0xC6340010, 0xC25A000A, 0xC000491A, 0xCA401C20, 0xC2800000, 0xC0004932, 0xCA8000E0,
- 0xC0004862, 0xCA400068, 0x6FA04010, 0x42290000, 0xC000491E, 0xCE000000, 0xC7E41050, 0xC000491C,
- 0xCE400000, 0x6FE04000, 0x43A1C000, 0xC000493C, 0xCF800000, 0xC000493E, 0xCF400000, 0xC000493A,
- 0xCFC00000, 0x8000FFF0, 0x00000000, 0x00000000, 0x00000000, 0xC2000000, 0xDCE00000, 0xA622FFB8,
- 0xC1220002, 0xD90C0000, 0xC0004938, 0xCBC00000, 0xC0004944, 0xCB400000, 0xC0004862, 0xCB000000,
- 0xC0004934, 0xCA000000, 0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0xA6020248, 0xC2400000,
- 0x58380008, 0xCA406008, 0xDFE80000, 0xC2218E08, 0x5A21BAF6, 0x46294000, 0x8400000A, 0xC2080002,
- 0x7235A000, 0x80000040, 0x5E640000, 0x8400000A, 0xC20C0002, 0x7235A000, 0x80000018, 0xC2000000,
- 0xC760E718, 0xC7604220, 0x5E200000, 0x8400025A, 0xC2200002, 0xC0004930, 0xCE001008, 0x990060A8,
- 0xC0004828, 0xC9400000, 0xC1800002, 0x58380000, 0xCA000000, 0x00000000, 0x00000000, 0xA6000112,
- 0xC0004940, 0xCA800000, 0xC0004942, 0xCA400000, 0xC7600080, 0xC6A01840, 0xC6601040, 0xC000493A,
- 0xCA400000, 0xC0004934, 0xCA800000, 0xC0007200, 0x40300000, 0x40240000, 0x5C000004, 0x5EC07400,
- 0x8800FFFA, 0x5C000200, 0xCE000000, 0x58000002, 0x5EC07400, 0x8800FFFA, 0x5C000200, 0xCE800000,
- 0xC000493E, 0xCA000000, 0xC2400000, 0x5838000C, 0xCE400000, 0x990060A8, 0xC0004830, 0xC9400000,
- 0xC6180000, 0xC0004930, 0xC6100080, 0xCD000080, 0x80000090, 0xC2400002, 0x58380008, 0xCE400008,
- 0xC0004944, 0xCF400000, 0x80000260, 0xC000493C, 0xCA400000, 0xDFE80000, 0x5A300018, 0xC0007200,
- 0x40200000, 0xCA000000, 0x58380008, 0xC6501080, 0xCD001080, 0x5838000A, 0xCE800000, 0x58380026,
- 0xCE000000, 0xC0004944, 0xCF400000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0x80000020,
- 0x00000000, 0x990060A8, 0xC0004826, 0xC9400000, 0xC1800002, 0x8000FDC0, 0xC2000000, 0xC2400200,
- 0xDF600040, 0xB624FFCA, 0xC000491C, 0xCA400000, 0xC000491E, 0xCA800000, 0x99005930, 0xDA580000,
- 0xDA980001, 0x00000000, 0xC0004934, 0xCA000000, 0x00000000, 0xC2800000, 0xA6020140, 0xC2400004,
- 0xC2000200, 0xDF690050, 0x46A14000, 0x46694000, 0x8800FFC2, 0x00000000, 0xC000491A, 0xC9800000,
- 0xC0004862, 0xC9400000, 0x6D9C6000, 0x459CE000, 0x59DC4C80, 0x99005790, 0xD9580000, 0xD9980001,
- 0xD9D40000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0xC2000000, 0xC2400200, 0xDF600040,
- 0xB624FFCA, 0xC000491C, 0xCA400000, 0xC000491E, 0xCA800000, 0x99005930, 0xDA580000, 0xDA980001,
- 0x00000000, 0x58380008, 0xCA400000, 0xC2000000, 0xCE000020, 0xC2A1FFFE, 0x5AA9FFFE, 0xCE001080,
- 0x5838000A, 0xCE800000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0000838, 0xC2500002,
- 0xCE440808, 0xC0004848, 0xCB840000, 0xC2000000, 0xC000082C, 0xCA040030, 0x5FB80002, 0xC0004848,
- 0xCF840000, 0x58880002, 0xB608FFF8, 0x00000000, 0xC0800000, 0xC0004844, 0xCC840000, 0x00000000,
- 0xC121FFFE, 0x5911FE14, 0x15000000, 0x8000DEC0, 0xC2000000, 0xDF600040, 0x5E200080, 0x84000252,
- 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000480C, 0xCA000000, 0xC0004910,
- 0xCA400000, 0xC000492C, 0xCA800000, 0xC0004968, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14,
- 0x15000000, 0x76610000, 0x76A10000, 0x762D6000, 0x840001AA, 0xC0004926, 0xCA400000, 0xC201FFFE,
- 0x762D6000, 0x5A640002, 0x6AE50010, 0x5F200000, 0x84000002, 0x6A250000, 0x8000FFF8, 0xC6E00000,
- 0x62014008, 0xC0004926, 0xCE800000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0004968,
- 0xCA400000, 0xC2000002, 0x6A290000, 0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE,
- 0x5911FE14, 0x15000000, 0x6EB4A000, 0x6E944000, 0x4575A000, 0x46B5A000, 0x5B744E20, 0x58340002,
- 0xC2000000, 0xCA0000E0, 0x5834002E, 0xC2400000, 0xCA400080, 0x6EB0A000, 0x6EBC4000, 0x47F18000,
- 0x46B18000, 0x5B300E4E, 0x5B300004, 0x6E642000, 0x4225E000, 0xC39A8024, 0xC7380068, 0xC6B81C20,
- 0x99005930, 0xDB980000, 0xDBD80001, 0x00000000, 0xC2000000, 0xDF600040, 0x5E200080, 0x8400028A,
- 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA000000, 0xC000492A,
- 0xCA400000, 0xC000496A, 0xCB000000, 0xC0004956, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14,
- 0x15000000, 0x76318000, 0x76718000, 0x840001EA, 0xC201FFFE, 0x76318000, 0x5AEC0002, 0x6B2D0010,
- 0x5EA00000, 0x84000002, 0x6A2D0000, 0x8000FFF8, 0xC7200000, 0x62016008, 0xC0004956, 0xCEC00000,
- 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000496A, 0xCA400000, 0xC2000002, 0x6A2D0000,
- 0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x6EF4A000,
- 0x6ED44000, 0x4575A000, 0x46F5A000, 0x5B744E20, 0x5834000E, 0xC2000000, 0xCA0000E0, 0x58340008,
- 0xC2400000, 0xCA420080, 0x5834000C, 0xC2800000, 0xCA832018, 0x6E644010, 0x42250000, 0x4229E000,
- 0xC39A8008, 0x58340008, 0xCB809020, 0x58340008, 0xC2800000, 0xCA810018, 0x6EE0A000, 0x6EE44000,
- 0x46610000, 0x46E10000, 0x5A200008, 0x5A200E28, 0x42290000, 0xC6380068, 0xC6F81C20, 0x99005930,
- 0xDB980000, 0xDBD80001, 0x00000000, 0xC000495A, 0xC8400000, 0x00000000, 0xC3C00002, 0x7BC42000,
- 0xCC400000, 0xC0001A1C, 0xCA000000, 0xC2400008, 0x6A452000, 0x76610000, 0x8400D91A, 0xC0000A28,
- 0xC3800000, 0xCB840030, 0xC0000A14, 0xC3400000, 0xCB440030, 0xC0004880, 0xCB040000, 0xB7B4D8CA,
- 0x58041802, 0xCAC00000, 0xA7000018, 0x00000000, 0x00000000, 0xA6C8D898, 0xC2800000, 0xC6E80020,
- 0x80000030, 0xC2800000, 0xC7282020, 0xC000490E, 0xCA400000, 0x6BE9E000, 0x00000000, 0x77E52000,
- 0x8400D848, 0x6EA0A000, 0x6E944000, 0x45610000, 0x46A10000, 0x5A204E20, 0x5820000C, 0xCA000000,
- 0xC0004946, 0xCE800000, 0xA6220348, 0x00000000, 0xC2200060, 0xC0004948, 0xCE000010, 0xCE001040,
- 0xC240000A, 0xC000494A, 0xCE400000, 0xC2B60002, 0xC0004964, 0xCE801B08, 0x99005C00, 0xC00048A0,
- 0xC8840000, 0x00000000, 0xC0004946, 0xCBC00000, 0x00000000, 0x00000000, 0x6FF8A000, 0x6FD44000,
- 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x990059C0, 0xDBD80000, 0xDB980001, 0x00000000, 0x99005708,
- 0xC000491C, 0xC1400000, 0xC9420050, 0xC000491C, 0x99005BB8, 0xC9400001, 0xC9800000, 0x00000000,
- 0x99005930, 0xD9580000, 0xD9980001, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000,
- 0x990055F8, 0xDBD80000, 0xDB980001, 0xC7D80000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,
- 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x58380010, 0xCA000000, 0xC0004874,
- 0xC8040000, 0x6C908000, 0x44908000, 0x44908000, 0x40100000, 0xCA400000, 0xC4340000, 0x00000000,
- 0xC7400000, 0xCE000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA400000,
- 0xC2800002, 0x6ABD4000, 0x72A52000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,
- 0x990060A8, 0xC0004836, 0xC9400000, 0xC1800002, 0x00000000, 0x00000000, 0x00000000, 0xA8E2FFC8,
- 0x00000000, 0xC1220002, 0xD90C0000, 0xC2000000, 0xC0000A14, 0xCA040030, 0xC0000A28, 0xC2500002,
- 0xCE440808, 0x58880002, 0xB608FFF8, 0xC00048A0, 0xC0800000, 0xCC840000, 0x8000D498, 0xC0004946,
- 0xCBC00000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA400000, 0xC2800002,
- 0x6ABD4000, 0x72A52000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x6FF8A000,
- 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x58380008, 0xCA000000, 0x5838000C, 0xCA400000,
- 0xC3400000, 0xC6340008, 0xC000494E, 0xCF400000, 0xC2800000, 0xC62A0080, 0xC3000000, 0xC6308020,
- 0x6F304000, 0x43298000, 0xC000493C, 0xCF000000, 0xC2C00000, 0xC66C0080, 0xC0004950, 0xCEC00000,
- 0xC2800000, 0xC66AE028, 0xC0004954, 0xCE800000, 0x5F740000, 0x84000188, 0x5E300028, 0x462D2000,
- 0x84000152, 0x462D2000, 0x8800011A, 0x5E300018, 0x462D2000, 0x88000012, 0x462D2000, 0x8400002A,
- 0x00000000, 0x800000A8, 0x00000000, 0x99005D40, 0xDBD80000, 0xDB980001, 0xC7800000, 0xC3400002,
- 0xC000494E, 0xCF400000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA400000,
- 0xC2800002, 0x6ABD4000, 0x7E814000, 0x76A52000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14,
- 0x15000000, 0xC2200060, 0xC0004948, 0xCE001040, 0xC2000000, 0xC000494C, 0xCE000000, 0x80000068,
- 0x00000000, 0x99005D40, 0xDBD80000, 0xDB980001, 0xC7800000, 0x99005F40, 0xDBD80000, 0xDB980001,
- 0xC7800000, 0xC2200058, 0xC0004948, 0xCE001040, 0xC2000002, 0xC000494C, 0xCE000000, 0xC2000006,
- 0xC0001006, 0xCE000000, 0x5838000A, 0xCA400000, 0xC2200982, 0x5A203B6E, 0xC0001008, 0xCE000000,
- 0xC000100A, 0xCE400000, 0xC0004954, 0xCA800000, 0xC200000C, 0xC000494A, 0xCE000000, 0xC0004948,
- 0xCE800010, 0xC2B60000, 0xC0004964, 0xCE800000, 0x99005C00, 0xC00048A0, 0xC8840000, 0x00000000,
- 0xC0004946, 0xCBC00000, 0xC000494C, 0xCA000000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000,
- 0x5BB84E20, 0x5E200000, 0x840000E2, 0x00000000, 0x990059C0, 0xDBD80000, 0xDB980001, 0x00000000,
- 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0xC000491C, 0x99005BB8, 0xC9400001, 0xC9800000,
- 0x00000000, 0x99005930, 0xD9580000, 0xD9980001, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000,
- 0x00000000, 0x990055F8, 0xDBD80000, 0xDB980001, 0xC7D80000, 0x00000000, 0xC121FFFE, 0x5911FE14,
- 0x15000000, 0xC000493C, 0xCA800000, 0xC000494E, 0xCAC00000, 0xC3000018, 0xC3400006, 0x5E200000,
- 0x84000012, 0xC2800000, 0xC2C00000, 0xC300001E, 0xC3400000, 0xC6AC1080, 0xC72C0420, 0xC76C0818,
- 0x58380010, 0xCA800000, 0x58380008, 0xCEC00000, 0xC6280108, 0xC0004874, 0xC8040000, 0x6C908000,
- 0x44908000, 0x44908000, 0x40100000, 0xCB000000, 0xC4340000, 0x00000000, 0xC7400000, 0xCE800000,
- 0xC0004952, 0xCE800000, 0x00000000, 0x00000000, 0x00000000, 0xA8E2FFC8, 0x00000000, 0xC000494C,
- 0xCA000000, 0xC0004950, 0xCAC00000, 0x5E200000, 0x84000052, 0xDFE80000, 0x7E814000, 0x5834001A,
- 0xCE800000, 0x990060A8, 0xC0004834, 0xC9400000, 0xC1800002, 0x990060A8, 0xC0004838, 0xC9400000,
- 0xC6D80000, 0xC1220002, 0xD90C0000, 0x5E200000, 0x84000028, 0x5838002C, 0xCB000000, 0xDFE80000,
- 0x00000000, 0x58380014, 0xCF000000, 0x80000000, 0xC2A1FFFE, 0x5AA9FFFE, 0x5838000A, 0xCE800000,
- 0xC3000000, 0xC0000A14, 0xCB040030, 0xC2D00002, 0xC0000A28, 0xCEC40808, 0xC000494E, 0xCA800000,
- 0x58880002, 0xB4B0FFF8, 0xC00048A0, 0xC0800000, 0xCC840000, 0x5EA80000, 0x8400013A, 0x5E200000,
- 0x84000128, 0xC000493C, 0xCA800000, 0x00000000, 0x00000000, 0x5AA80060, 0xCE800000, 0x99005D40,
- 0xDBD80000, 0xDB980001, 0xC7800000, 0x99005F40, 0xDBD80000, 0xDB980001, 0xC7800000, 0xC0004952,
- 0xCAC00000, 0x58380000, 0xCA800000, 0xC30C0002, 0xC7F00020, 0xA6800078, 0x00000000, 0x00000000,
- 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0001800, 0xCA000000, 0x00000000, 0x00000000,
- 0xA60CFFCA, 0xC6F00508, 0xC6B0C408, 0xCF000000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,
- 0x8000CB48, 0xDCBC0001, 0x5FFC0000, 0x8400003A, 0xC3800002, 0xDB880001, 0x5FFC0004, 0x8400C4B2,
- 0xC3800000, 0xDB880001, 0xC3CE0002, 0xC0000800, 0xCFC00708, 0xC3E1FFFE, 0x597DFFFE, 0x593DFE14,
- 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0xC000487C, 0xC8040000, 0x00000000, 0x00000000,
- 0x40080000, 0xCBC00000, 0xC4380000, 0x00000000, 0xC000480E, 0xCA000000, 0xC0004858, 0xCB440000,
- 0x00000000, 0x00000000, 0x46350000, 0x88000098, 0x00000000, 0xA7C00028, 0xC0004854, 0xC1000002,
- 0xCD040000, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x800000C0, 0x00000000, 0xA7D20118, 0x00000000,
- 0xC7E14048, 0xC2400000, 0xC6246030, 0xC200006A, 0x46610000, 0xC6240038, 0xC0000810, 0xCE440038,
- 0x8000FF58, 0xC2000000, 0xC0000808, 0xCA040018, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x5A200002,
- 0x5E600010, 0x8400FFF8, 0xC2000000, 0xC0000808, 0xCE040018, 0xC3400000, 0x80000010, 0xC1200002,
- 0xC0000818, 0xCD041008, 0x5B740002, 0xC0004858, 0xCF440000, 0x99005348, 0xC0004848, 0xC9440000,
- 0xC1800000, 0xC11C0002, 0xC000082C, 0xCD040E08, 0x800005C8, 0x5B740002, 0xC0004858, 0xCF440000,
- 0xC7800000, 0xC13C0002, 0xCD001E08, 0xC0004848, 0xC9440000, 0xC1800000, 0xC000082C, 0xC9840030,
- 0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB4980540, 0x00000000, 0xC0800000, 0x80000530,
- 0xC000487C, 0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCBC00000, 0xC4280000, 0x00000000,
- 0xA7C00110, 0xC000484C, 0xCA040000, 0xC2400000, 0xC0001AEC, 0xCA440020, 0x5A200002, 0xC000484C,
- 0xCE040000, 0xB624006A, 0xC6800000, 0xC13C0002, 0xCD001E08, 0xC0004848, 0xC9440000, 0xC1800000,
- 0xC000082C, 0xC9840030, 0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB4980430, 0x00000000,
- 0xC0800000, 0x80000420, 0xC0004854, 0xC1000004, 0xCD040000, 0xC0000820, 0xC2000002, 0xCE040000,
- 0xC2000000, 0xC000484C, 0xCE040000, 0xC0004858, 0xCE040000, 0x8000FF10, 0xC0004854, 0xC1000000,
- 0xCD040000, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x99005348, 0xC0004848, 0xC9440000, 0xC1800000,
- 0xC1200000, 0xC0000818, 0xCD041008, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC2000000, 0xC000484C,
- 0xCE040000, 0x80000320, 0xC0001AC0, 0xCB840000, 0xC000487C, 0xC8040000, 0x00000000, 0x00000000,
- 0x40080000, 0xCBC00000, 0xC4280000, 0x00000000, 0xA780022A, 0x00000000, 0x00000000, 0xA7C001EA,
- 0x00000000, 0xC0001B00, 0xC2060006, 0xCE040310, 0xA7E801A2, 0x00000000, 0xC0004850, 0xCA040000,
- 0xC2400000, 0xC0001AEC, 0xCA448020, 0x5A200002, 0xC0004850, 0xCE040000, 0xB624008A, 0x00000000,
- 0xC6800000, 0xC13C0002, 0xCD001E08, 0xC0001ACC, 0xC2000002, 0xCE040008, 0xC0004848, 0xC9440000,
- 0xC1800000, 0xC000082C, 0xC9840030, 0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB49801A8,
- 0x00000000, 0xC0800000, 0x80000198, 0xC0004854, 0xC1000000, 0xCD040000, 0xC11C0000, 0xC000082C,
- 0xCD040E08, 0x99005348, 0xC0004848, 0xC9440000, 0xC1800000, 0xC2000000, 0xC0000820, 0xCE040000,
- 0xC1200000, 0xC0000818, 0xCD041008, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0004850, 0xCE040000,
- 0xC2000002, 0xC0001ACC, 0xCE040010, 0x800000D0, 0xC2000002, 0xC0004850, 0xCE040000, 0x8000FE70,
- 0xC2000000, 0xC0004850, 0xCE040000, 0xA7E60012, 0x00000000, 0xC2000002, 0xC0001B00, 0xCE040008,
- 0x8000FE58, 0x00000000, 0xA7860032, 0x00000000, 0xC6800000, 0xC13C0002, 0xCD001E08, 0xC2020002,
- 0xC7E2A548, 0xC0001B00, 0xCE040000, 0x8000FE00, 0xC2040002, 0xC0001B00, 0xCE040208, 0x8000FDE0,
- 0xC2C80002, 0x6AC56000, 0xDACC0000, 0xC0004854, 0xCB440000, 0xC0004848, 0xCB840000, 0xC0000838,
- 0xC3C00000, 0xCBC40030, 0x5EF40004, 0x8400000A, 0xC3000000, 0xC0001ACC, 0xCF040108, 0x47BD8000,
- 0x84000012, 0x47BD8000, 0x88000018, 0xC1006E8C, 0x8000B908, 0xC0004840, 0xCC840000, 0x8000F6B8,
- 0xC0001AC0, 0xCAC40000, 0xC0004854, 0xCB440000, 0xA6C0FBD2, 0x00000000, 0x5EF40000, 0x8400F712,
- 0x5EF40002, 0x8400F9A2, 0x5EF40004, 0x8400FBA2, 0xC1006CE8, 0x8000B880, 0x00000000, 0xC0800000,
- 0xDF4B0040, 0xC0004900, 0xCB800000, 0xC2000000, 0xC000490A, 0xA78000B0, 0xCBC00000, 0xC1000000,
- 0xD9000001, 0xC1000002, 0xD90C0000, 0x6FF46000, 0x47F5A000, 0x5B744C80, 0xC2400000, 0x58340004,
- 0xCA400080, 0xC0004900, 0xCE000008, 0x5A640002, 0x58340004, 0xC6500080, 0xCD000080, 0xC0004914,
- 0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000, 0xC0000408, 0xCE000000, 0xA78200B8,
- 0xC0004908, 0xCBC00000, 0xC1000000, 0xD9000001, 0xC1000002, 0xD90C0000, 0x6FF4A000, 0x6FD44000,
- 0x4575A000, 0x47F5A000, 0x5B744E20, 0xC2800000, 0x58340006, 0xCA800080, 0xC2000000, 0xC0004900,
- 0xCE000108, 0x5EA80002, 0x58340006, 0xC6900080, 0xCD000080, 0x5A7C0020, 0xC2000002, 0x6A250000,
- 0xC0000408, 0xCE000000, 0xDCA80001, 0x5EA80000, 0x8400B6F0, 0x00000000, 0xA4800210, 0x00000000,
- 0xC3C00000, 0xC000140E, 0xCBC00020, 0xC3400000, 0xC2400000, 0x6FF86000, 0x47F9C000, 0x5BB84C80,
- 0x58380008, 0xCB400080, 0x58380006, 0xCA400080, 0x5F740002, 0x58380008, 0xC7500080, 0xCD000080,
- 0xC2000000, 0x58380004, 0xCA020080, 0xC3000000, 0x5838000C, 0xCB000028, 0x5A640002, 0x46250000,
- 0x8400FFF8, 0xC2400000, 0x58380006, 0xC6500080, 0xCD000080, 0xC2000000, 0x5838000A, 0xCA020080,
- 0x5B300002, 0x5838000C, 0xC7100028, 0xCD000028, 0xC2420020, 0x5A200004, 0x46612000, 0x8400FFF8,
- 0xC2000000, 0x5838000A, 0xC6101080, 0xCD001080, 0xC0004966, 0xCA400000, 0xC2000002, 0x6A3D0000,
- 0x72252000, 0xCE400000, 0x5F740000, 0x84000028, 0xC0004912, 0xCA000000, 0xC2C00002, 0x6AFD6000,
- 0x7EC16000, 0x76E10000, 0xCE000000, 0x5F300020, 0x84000028, 0xC0004924, 0xCA000000, 0xC2C00002,
- 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0xA4820050, 0xC2400000, 0xC000140E, 0xCA408020,
- 0xC2000002, 0xC0004900, 0xCE000008, 0xC000490A, 0xCE400000, 0xC1000000, 0xD9000001, 0xD8400080,
- 0xC1000004, 0xD9000001, 0xA4840288, 0x00000000, 0xC3C00000, 0xC000140E, 0xCBC10020, 0xC2800000,
- 0xC2000000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x5838002E, 0xCA800080,
- 0x58380006, 0xCA020080, 0xC3400000, 0x5838002E, 0xCB420080, 0x5AA80002, 0x46290000, 0x8400FFF8,
- 0xC2800000, 0x5838002E, 0xC6900080, 0xCD000080, 0x5F740002, 0x5838002E, 0xC7501080, 0xCD001080,
- 0xC0004968, 0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000, 0xC000492A, 0xCA800000,
- 0x5E740000, 0x84000028, 0xC0004910, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000,
- 0xCE000000, 0x6ABD4010, 0xA68000D2, 0x00000000, 0xC0004910, 0xCA000000, 0xC2C00002, 0x6AFD6000,
- 0x7EC16000, 0x76E10000, 0xCE000000, 0x58380032, 0xCA000000, 0x58000002, 0xCA400000, 0x5838000C,
- 0x00000000, 0xCE000001, 0xCE400000, 0xC000492A, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x72E10000,
- 0xCE000000, 0xC000492C, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x72E10000, 0xCE000000, 0x80000028,
- 0xC000492C, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0xA4880100,
- 0xC2C00000, 0xC000140E, 0xCAC20020, 0xC000490E, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x7E010000,
- 0x76252000, 0xCE400000, 0xC000496A, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000,
- 0x6EF0A000, 0x6ED44000, 0x45718000, 0x46F18000, 0x5B304E20, 0x58300000, 0xCA000000, 0x00000000,
- 0xC2400002, 0x76252000, 0x84000032, 0xC24C0002, 0xC6E40020, 0xC624C408, 0x58300010, 0xCA400508,
- 0x00000000, 0xC0001800, 0xCE400000, 0xA4860050, 0xC2400000, 0xC000140E, 0xCA418020, 0xC2020002,
- 0xC0004900, 0xCE000108, 0xC0004908, 0xCE400000, 0xC1000000, 0xD9000001, 0xD8400080, 0xC1000004,
- 0xD9000001, 0xC0001408, 0xCC800000, 0xC10E0002, 0xD90C0000, 0x8000EDA8, 0xDFBC0001, 0xC000496E,
- 0x99006050, 0xC9400000, 0xC7D80000, 0x00000000, 0xC5700000, 0x5EF00020, 0x88000130, 0x6F346000,
- 0x4735A000, 0x5B744C80, 0x58340008, 0xC2400000, 0xCA400080, 0x00000000, 0xC2000000, 0x5A640002,
- 0xCE400080, 0x58340004, 0xCA000080, 0x00000000, 0x00000000, 0x5E200002, 0xCE000080, 0xC0004912,
- 0xCA800000, 0xC2400002, 0x6A712000, 0x72694000, 0xCE800000, 0x5E200000, 0x8400003A, 0xC000480A,
- 0xCA000000, 0xC0000408, 0xCA800000, 0x76610000, 0x00000000, 0x72294000, 0xCE800000, 0x80000020,
- 0xC0004914, 0xCA000000, 0x7E412000, 0x00000000, 0x76610000, 0xCE000000, 0x800000B8, 0x6EF4A000,
- 0x6ED44000, 0x4575A000, 0x46F5A000, 0x5B744E20, 0x5834002E, 0xC2400000, 0xCA420080, 0x00000000,
- 0xC2000000, 0x5A640002, 0xC6501080, 0xCD001080, 0x58340006, 0xCA000080, 0x00000000, 0x00000000,
- 0x5A200002, 0xCE000080, 0xC0004910, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000,
- 0xC2000002, 0x6A310000, 0xC000042A, 0xCE000000, 0xC1040002, 0xD90C0000, 0x00000000, 0x8000EB18,
- 0x00000000, 0xC4980930, 0x9D000000, 0xC5580030, 0xC0000838, 0xCD840000, 0xC1440200, 0xC1C03200,
- 0xC55C1078, 0xC000100E, 0x9D000000, 0xCD800000, 0xC000100C, 0xCDC00000, 0xC0004862, 0xC9C00000,
- 0x00000000, 0x00000000, 0xD9D80001, 0xC0007200, 0x401C0000, 0x5DC07400, 0x8800FFFA, 0x5C000200,
- 0xCD800000, 0xC1F0000A, 0x71D4A000, 0xDD980000, 0xDD9C0001, 0x41D8E000, 0xC5D40268, 0xC0001010,
- 0xCD400000, 0x6C9C8000, 0x449CE000, 0x449CE000, 0x59DC0004, 0xC1601260, 0xC5D40268, 0x9D000000,
- 0xC0001012, 0xCD400000, 0x00000000, 0x00000000, 0xD9580000, 0x6D586000, 0x4558C000, 0x59984C80,
- 0xD9980001, 0x5818000A, 0xC1800000, 0xC9800080, 0xC0005400, 0x6D5CA000, 0x401C0000, 0x40180000,
- 0xC9400000, 0x58000002, 0x00000000, 0xC9C00000, 0xC0004930, 0xCD400000, 0xC0004932, 0xCDC00000,
- 0x59980004, 0xC1C20020, 0xB59CFFF8, 0x00000000, 0xC1800000, 0xDD9C0001, 0x581C000A, 0xCD800080,
- 0x581C000C, 0xC1800000, 0xC9800028, 0xC1C00002, 0xDD940000, 0x69D4E000, 0x5D980002, 0xCD800028,
- 0xC0004924, 0xC9800000, 0x00000000, 0x9D000000, 0x00000000, 0x71D8C000, 0xCD800000, 0xC000492A,
- 0xC9400000, 0xC1C00002, 0x69D8E000, 0x7DC0C000, 0x7594A000, 0xCD400000, 0xC000492C, 0xC9400000,
- 0xDD800001, 0x58000032, 0x75D4A000, 0x84000078, 0xC9400001, 0xC9800000, 0xDD800001, 0x5800000C,
- 0x00000000, 0xCD400001, 0xCD800000, 0xC000492C, 0xC9400000, 0xC000492A, 0xC9800000, 0x71D4A000,
- 0xC000492C, 0xCD400000, 0x71D8C000, 0xC000492A, 0xCD800000, 0x9D000000, 0x00000000, 0x00000000,
- 0x00000000, 0xC0004862, 0xC9800000, 0x00000000, 0xC1C00200, 0x4194C000, 0x45D8E000, 0x8800FFFA,
- 0xC5D80000, 0xC0004862, 0xCD800000, 0xC0001406, 0xC9800000, 0xC1C00002, 0x9D000000, 0xC5D80A08,
- 0xC5581050, 0xCD800000, 0xC0004930, 0xC9800000, 0xC0004932, 0xC9C00000, 0xC140000E, 0xC5581C20,
- 0xDD940000, 0xC0007200, 0x40140000, 0x5D407400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0x58000002,
- 0x5D407400, 0x8800FFFA, 0x5C000200, 0xCDC00000, 0xDD540000, 0xC1C00000, 0x58140006, 0xC9C20080,
- 0xC1800000, 0x58140000, 0xC98000E0, 0x6DDC2000, 0xC000491E, 0x41D8E000, 0xCDC00000, 0xDD980000,
- 0xC1C00022, 0xC5D80D78, 0xDD940001, 0xC5581C20, 0xC000491C, 0xCD800000, 0xDD540000, 0xC1C00000,
- 0x58140006, 0xC9C20080, 0xC1800000, 0x58140004, 0xC9820080, 0x00000000, 0x59DC0002, 0x459CC000,
- 0x8400FFF8, 0xC1C00000, 0x9D000000, 0x58140006, 0xC5D81080, 0xCD801080, 0xC0004860, 0xC9400000,
- 0xC1800100, 0xC1D00002, 0x58146B00, 0xD5800000, 0x58000002, 0xD5800001, 0x59540004, 0xB558FFF8,
- 0xC0004860, 0xC1400000, 0xCD400000, 0xDD980001, 0x9D000000, 0xDD940000, 0xC0001404, 0xCDC00808,
- 0xC1C00000, 0xC1800200, 0x5D980004, 0xDF5D0050, 0x45D8A000, 0x8800FFDA, 0xDD800001, 0x5800000C,
- 0x00000000, 0xC9400001, 0xC9800000, 0xC1C00002, 0xC5D43F08, 0xC5D81E08, 0xC0004862, 0xC9C00000,
- 0x00000000, 0x00000000, 0x581C7200, 0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD400000, 0x58000002,
- 0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0xC0004862, 0xC9C00000, 0x00000000, 0xC15004C0,
- 0xC5D40068, 0xDD9C0000, 0xC5D41C20, 0xC1C00000, 0xDD800001, 0x58000030, 0xC9C00080, 0xDD800001,
- 0x58000002, 0xC9800000, 0x6DDC2000, 0xC000491C, 0x41D8E000, 0xCD400001, 0xCDC00000, 0xDD940001,
- 0xC1C00000, 0x58140030, 0xC9C00080, 0xC1800000, 0x58140006, 0xC9820080, 0x00000000, 0x59DC0002,
- 0x459CC000, 0x8400FFF8, 0xC1C00000, 0x9D000000, 0x58140030, 0xC5D80080, 0xCD800080, 0xC1C00000,
- 0xDF5C0040, 0x5DDC0080, 0x8400FFD2, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000,
- 0xC160FFFE, 0xC0000A10, 0xC9440068, 0xC1A0FFFE, 0x59980E28, 0xC000100C, 0xCD400000, 0xC000100E,
- 0xCD800000, 0xC0004964, 0xC9800000, 0x00000000, 0xC170000A, 0x7194A000, 0x6C988000, 0x4498C000,
- 0x4498C000, 0x59980004, 0xC5940278, 0xC0001010, 0xCD400000, 0xC0004946, 0xC9400000, 0x00000000,
- 0x00000000, 0x6D58A000, 0x6D5C4000, 0x45D8C000, 0x4558C000, 0xC000494A, 0xC9400000, 0xC0004948,
- 0xC9C00000, 0x4194C000, 0xC1400012, 0xC55C1820, 0x9D000000, 0xC59C0270, 0xC0001012, 0xCDC00000,
- 0xC1400000, 0x58000012, 0xC9410040, 0xC0004950, 0xC9C00000, 0xC5580000, 0xC5940840, 0xC5581080,
- 0xD9940000, 0xC000493C, 0xC9400000, 0xC0004954, 0xC9800000, 0x59DC00A8, 0x455CE000, 0x41D8E000,
- 0x5D5C0030, 0x8800FFF8, 0xC1C00030, 0xC1800000, 0xC5D84030, 0xC1400000, 0xC5D40010, 0x5DD40002,
- 0x8400005A, 0x5DD40004, 0x84000082, 0x5DD40006, 0x840000AA, 0x5DD80026, 0x840000D2, 0xDD540000,
- 0xDD800001, 0x58000008, 0x40180000, 0xCD400000, 0x59980002, 0x8000FFA8, 0xDD540000, 0xDD800001,
- 0x58000008, 0x40180000, 0xCD4000C0, 0x59980002, 0x8000FF70, 0xDD540000, 0xDD800001, 0x58000008,
- 0x40180000, 0xCD400080, 0x59980002, 0x8000FF38, 0xDD540000, 0xDD800001, 0x58000008, 0x40180000,
- 0xCD400040, 0x59980002, 0x8000FF00, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000,
- 0x58000012, 0xC9400000, 0xC0004954, 0xC9C00000, 0xC0004950, 0xC9400080, 0xDD800001, 0x58000028,
- 0x5D9C0000, 0x8400003A, 0x5D9C0002, 0x8400003A, 0x5D9C0004, 0x84000052, 0xC55B0040, 0xC55C08C0,
- 0xCD800041, 0xCDC008C0, 0x80000048, 0xCD400000, 0x80000038, 0xC55900C0, 0xC55C1840, 0xCD8000C1,
- 0xCDC01840, 0x80000010, 0xC55A0080, 0xC55C1080, 0xCD800081, 0xCDC01080, 0x9D000000, 0x00000000,
- 0x00000000, 0x00000000, 0x59540002, 0x6994E018, 0x61C0C008, 0x4194A000, 0x5D940040, 0x8800FFFA,
- 0xC5940000, 0x9D000000, 0xCD400000, 0x00000000, 0x00000000, 0x9D000000, 0x4158A000, 0xCD400000,
- 0x00000000,
-};
-
-static unsigned int firmware_binary_data[] = {
-};
-
-
-#endif // IFXMIPS_ATM_FW_DANUBE_H
+++ /dev/null
-#ifndef IFXMIPS_ATM_FW_REGS_COMMON_H
-#define IFXMIPS_ATM_FW_REGS_COMMON_H
-
-
-
-#if defined(CONFIG_DANUBE)
- #include "ifxmips_atm_fw_regs_danube.h"
-#elif defined(CONFIG_AMAZON_SE)
- #include "ifxmips_atm_fw_regs_amazon_se.h"
-#elif defined(CONFIG_AR9)
- #include "ifxmips_atm_fw_regs_ar9.h"
-#elif defined(CONFIG_VR9)
- #include "ifxmips_atm_fw_regs_vr9.h"
-#else
- #error Platform is not specified!
-#endif
-
-
-
-/*
- * PPE ATM Cell Header
- */
-#if defined(__BIG_ENDIAN)
- struct uni_cell_header {
- unsigned int gfc :4;
- unsigned int vpi :8;
- unsigned int vci :16;
- unsigned int pti :3;
- unsigned int clp :1;
- };
-#else
- struct uni_cell_header {
- unsigned int clp :1;
- unsigned int pti :3;
- unsigned int vci :16;
- unsigned int vpi :8;
- unsigned int gfc :4;
- };
-#endif // defined(__BIG_ENDIAN)
-
-/*
- * Inband Header and Trailer
- */
-#if defined(__BIG_ENDIAN)
- struct rx_inband_trailer {
- /* 0 - 3h */
- unsigned int uu :8;
- unsigned int cpi :8;
- unsigned int stw_res1:4;
- unsigned int stw_clp :1;
- unsigned int stw_ec :1;
- unsigned int stw_uu :1;
- unsigned int stw_cpi :1;
- unsigned int stw_ovz :1;
- unsigned int stw_mfl :1;
- unsigned int stw_usz :1;
- unsigned int stw_crc :1;
- unsigned int stw_il :1;
- unsigned int stw_ra :1;
- unsigned int stw_res2:2;
- /* 4 - 7h */
- unsigned int gfc :4;
- unsigned int vpi :8;
- unsigned int vci :16;
- unsigned int pti :3;
- unsigned int clp :1;
- };
-
- struct tx_inband_header {
- /* 0 - 3h */
- unsigned int gfc :4;
- unsigned int vpi :8;
- unsigned int vci :16;
- unsigned int pti :3;
- unsigned int clp :1;
- /* 4 - 7h */
- unsigned int uu :8;
- unsigned int cpi :8;
- unsigned int pad :8;
- unsigned int res1 :8;
- };
-#else
- struct rx_inband_trailer {
- /* 0 - 3h */
- unsigned int stw_res2:2;
- unsigned int stw_ra :1;
- unsigned int stw_il :1;
- unsigned int stw_crc :1;
- unsigned int stw_usz :1;
- unsigned int stw_mfl :1;
- unsigned int stw_ovz :1;
- unsigned int stw_cpi :1;
- unsigned int stw_uu :1;
- unsigned int stw_ec :1;
- unsigned int stw_clp :1;
- unsigned int stw_res1:4;
- unsigned int cpi :8;
- unsigned int uu :8;
- /* 4 - 7h */
- unsigned int clp :1;
- unsigned int pti :3;
- unsigned int vci :16;
- unsigned int vpi :8;
- unsigned int gfc :4;
- };
-
- struct tx_inband_header {
- /* 0 - 3h */
- unsigned int clp :1;
- unsigned int pti :3;
- unsigned int vci :16;
- unsigned int vpi :8;
- unsigned int gfc :4;
- /* 4 - 7h */
- unsigned int res1 :8;
- unsigned int pad :8;
- unsigned int cpi :8;
- unsigned int uu :8;
- };
-#endif // defined(__BIG_ENDIAN)
-
-/*
- * MIB Table Maintained by Firmware
- */
-struct wan_mib_table {
- u32 res1;
- u32 wrx_drophtu_cell;
- u32 wrx_dropdes_pdu;
- u32 wrx_correct_pdu;
- u32 wrx_err_pdu;
- u32 wrx_dropdes_cell;
- u32 wrx_correct_cell;
- u32 wrx_err_cell;
- u32 wrx_total_byte;
- u32 res2;
- u32 wtx_total_pdu;
- u32 wtx_total_cell;
- u32 wtx_total_byte;
-};
-
-/*
- * Host-PPE Communication Data Structure
- */
-
-#if defined(__BIG_ENDIAN)
- struct wrx_queue_config {
- /* 0h */
- unsigned int res2 :27;
- unsigned int dmach :4;
- unsigned int errdp :1;
- /* 1h */
- unsigned int oversize :16;
- unsigned int undersize :16;
- /* 2h */
- unsigned int res1 :16;
- unsigned int mfs :16;
- /* 3h */
- unsigned int uumask :8;
- unsigned int cpimask :8;
- unsigned int uuexp :8;
- unsigned int cpiexp :8;
- };
-
- struct wtx_port_config {
- unsigned int res1 :27;
- unsigned int qid :4;
- unsigned int qsben :1;
- };
-
- struct wtx_queue_config {
- unsigned int res1 :25;
- unsigned int sbid :1;
- unsigned int res2 :3;
- unsigned int type :2;
- unsigned int qsben :1;
- };
-
- struct wrx_dma_channel_config {
- /* 0h */
- unsigned int res1 :1;
- unsigned int mode :2;
- unsigned int rlcfg :1;
- unsigned int desba :28;
- /* 1h */
- unsigned int chrl :16;
- unsigned int clp1th :16;
- /* 2h */
- unsigned int deslen :16;
- unsigned int vlddes :16;
- };
-
- struct wtx_dma_channel_config {
- /* 0h */
- unsigned int res2 :1;
- unsigned int mode :2;
- unsigned int res3 :1;
- unsigned int desba :28;
- /* 1h */
- unsigned int res1 :32;
- /* 2h */
- unsigned int deslen :16;
- unsigned int vlddes :16;
- };
-
- struct htu_entry {
- unsigned int res1 :1;
- unsigned int clp :1;
- unsigned int pid :2;
- unsigned int vpi :8;
- unsigned int vci :16;
- unsigned int pti :3;
- unsigned int vld :1;
- };
-
- struct htu_mask {
- unsigned int set :1;
- unsigned int clp :1;
- unsigned int pid_mask :2;
- unsigned int vpi_mask :8;
- unsigned int vci_mask :16;
- unsigned int pti_mask :3;
- unsigned int clear :1;
- };
-
- struct htu_result {
- unsigned int res1 :12;
- unsigned int cellid :4;
- unsigned int res2 :5;
- unsigned int type :1;
- unsigned int ven :1;
- unsigned int res3 :5;
- unsigned int qid :4;
- };
-
- struct rx_descriptor {
- /* 0 - 3h */
- unsigned int own :1;
- unsigned int c :1;
- unsigned int sop :1;
- unsigned int eop :1;
- unsigned int res1 :3;
- unsigned int byteoff :2;
- unsigned int res2 :2;
- unsigned int id :4;
- unsigned int err :1;
- unsigned int datalen :16;
- /* 4 - 7h */
- unsigned int res3 :4;
- unsigned int dataptr :28;
- };
-
- struct tx_descriptor {
- /* 0 - 3h */
- unsigned int own :1;
- unsigned int c :1;
- unsigned int sop :1;
- unsigned int eop :1;
- unsigned int byteoff :5;
- unsigned int res1 :5;
- unsigned int iscell :1;
- unsigned int clp :1;
- unsigned int datalen :16;
- /* 4 - 7h */
- unsigned int res2 :4;
- unsigned int dataptr :28;
- };
-#else
- struct wrx_queue_config {
- /* 0h */
- unsigned int errdp :1;
- unsigned int dmach :4;
- unsigned int res2 :27;
- /* 1h */
- unsigned int undersize :16;
- unsigned int oversize :16;
- /* 2h */
- unsigned int mfs :16;
- unsigned int res1 :16;
- /* 3h */
- unsigned int cpiexp :8;
- unsigned int uuexp :8;
- unsigned int cpimask :8;
- unsigned int uumask :8;
- };
-
- struct wtx_port_config {
- unsigned int qsben :1;
- unsigned int qid :4;
- unsigned int res1 :27;
- };
-
- struct wtx_queue_config {
- unsigned int qsben :1;
- unsigned int type :2;
- unsigned int res2 :3;
- unsigned int sbid :1;
- unsigned int res1 :25;
- };
-
- struct wrx_dma_channel_config
- {
- /* 0h */
- unsigned int desba :28;
- unsigned int rlcfg :1;
- unsigned int mode :2;
- unsigned int res1 :1;
- /* 1h */
- unsigned int clp1th :16;
- unsigned int chrl :16;
- /* 2h */
- unsigned int vlddes :16;
- unsigned int deslen :16;
- };
-
- struct wtx_dma_channel_config {
- /* 0h */
- unsigned int desba :28;
- unsigned int res3 :1;
- unsigned int mode :2;
- unsigned int res2 :1;
- /* 1h */
- unsigned int res1 :32;
- /* 2h */
- unsigned int vlddes :16;
- unsigned int deslen :16;
- };
-
- struct rx_descriptor {
- /* 4 - 7h */
- unsigned int dataptr :28;
- unsigned int res3 :4;
- /* 0 - 3h */
- unsigned int datalen :16;
- unsigned int err :1;
- unsigned int id :4;
- unsigned int res2 :2;
- unsigned int byteoff :2;
- unsigned int res1 :3;
- unsigned int eop :1;
- unsigned int sop :1;
- unsigned int c :1;
- unsigned int own :1;
- };
-
- struct tx_descriptor {
- /* 4 - 7h */
- unsigned int dataptr :28;
- unsigned int res2 :4;
- /* 0 - 3h */
- unsigned int datalen :16;
- unsigned int clp :1;
- unsigned int iscell :1;
- unsigned int res1 :5;
- unsigned int byteoff :5;
- unsigned int eop :1;
- unsigned int sop :1;
- unsigned int c :1;
- unsigned int own :1;
- };
-#endif // defined(__BIG_ENDIAN)
-
-
-
-#endif // IFXMIPS_ATM_FW_REGS_COMMON_H
+++ /dev/null
-#ifndef IFXMIPS_ATM_FW_REGS_DANUBE_H
-#define IFXMIPS_ATM_FW_REGS_DANUBE_H
-
-
-
-/*
- * Host-PPE Communication Data Address Mapping
- */
-#define FW_VER_ID SB_BUFFER(0x2001)
-#define CFG_WRX_HTUTS SB_BUFFER(0x2400) /* WAN RX HTU Table Size, must be configured before enable PPE firmware. */
-#define CFG_WRX_QNUM SB_BUFFER(0x2401) /* WAN RX Queue Number */
-#define CFG_WRX_DCHNUM SB_BUFFER(0x2402) /* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */
-#define CFG_WTX_DCHNUM SB_BUFFER(0x2403) /* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */
-#define CFG_WRDES_DELAY SB_BUFFER(0x2404) /* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */
-#define WRX_DMACH_ON SB_BUFFER(0x2405) /* WAN RX DMA Channel Enable, must be configured before enable PPE firmware. */
-#define WTX_DMACH_ON SB_BUFFER(0x2406) /* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */
-#define WRX_HUNT_BITTH SB_BUFFER(0x2407) /* WAN RX HUNT Threshold, must be between 2 to 8. */
-#define WRX_QUEUE_CONFIG(i) ((struct wrx_queue_config*) SB_BUFFER(0x2500 + (i) * 20))
-#define WRX_DMA_CHANNEL_CONFIG(i) ((struct wrx_dma_channel_config*) SB_BUFFER(0x2640 + (i) * 7))
-#define WTX_PORT_CONFIG(i) ((struct wtx_port_config*) SB_BUFFER(0x2440 + (i)))
-#define WTX_QUEUE_CONFIG(i) ((struct wtx_queue_config*) SB_BUFFER(0x2710 + (i) * 27))
-#define WTX_DMA_CHANNEL_CONFIG(i) ((struct wtx_dma_channel_config*) SB_BUFFER(0x2711 + (i) * 27))
-#define WAN_MIB_TABLE ((struct wan_mib_table*) SB_BUFFER(0x2410))
-#define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x2000 + (i)))
-#define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x2020 + (i)))
-#define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x2040 + (i)))
-
-
-
-#endif // IFXMIPS_ATM_FW_REGS_DANUBE_H
+++ /dev/null
-#ifndef IFXMIPS_ATM_PPE_COMMON_H
-#define IFXMIPS_ATM_PPE_COMMON_H
-
-
-
-#if defined(CONFIG_DANUBE)
- #include "ifxmips_atm_ppe_danube.h"
-#elif defined(CONFIG_AMAZON_SE)
- #include "ifxmips_atm_ppe_amazon_se.h"
-#elif defined(CONFIG_AR9)
- #include "ifxmips_atm_ppe_ar9.h"
-#elif defined(CONFIG_VR9)
- #include "ifxmips_atm_ppe_vr9.h"
-#else
- #error Platform is not specified!
-#endif
-
-
-
-/*
- * Code/Data Memory (CDM) Interface Configuration Register
- */
-#define CDM_CFG PPE_REG_ADDR(0x0100)
-
-#define CDM_CFG_RAM1 GET_BITS(*CDM_CFG, 3, 2)
-#define CDM_CFG_RAM0 (*CDM_CFG & (1 << 1))
-
-#define CDM_CFG_RAM1_SET(value) SET_BITS(0, 3, 2, value)
-#define CDM_CFG_RAM0_SET(value) ((value) ? (1 << 1) : 0)
-
-/*
- * QSB Internal Cell Delay Variation Register
- */
-#define QSB_ICDV QSB_CONF_REG_ADDR(0x0007)
-
-#define QSB_ICDV_TAU GET_BITS(*QSB_ICDV, 5, 0)
-
-#define QSB_ICDV_TAU_SET(value) SET_BITS(0, 5, 0, value)
-
-/*
- * QSB Scheduler Burst Limit Register
- */
-#define QSB_SBL QSB_CONF_REG_ADDR(0x0009)
-
-#define QSB_SBL_SBL GET_BITS(*QSB_SBL, 3, 0)
-
-#define QSB_SBL_SBL_SET(value) SET_BITS(0, 3, 0, value)
-
-/*
- * QSB Configuration Register
- */
-#define QSB_CFG QSB_CONF_REG_ADDR(0x000A)
-
-#define QSB_CFG_TSTEPC GET_BITS(*QSB_CFG, 1, 0)
-
-#define QSB_CFG_TSTEPC_SET(value) SET_BITS(0, 1, 0, value)
-
-/*
- * QSB RAM Transfer Table Register
- */
-#define QSB_RTM QSB_CONF_REG_ADDR(0x000B)
-
-#define QSB_RTM_DM (*QSB_RTM)
-
-#define QSB_RTM_DM_SET(value) ((value) & 0xFFFFFFFF)
-
-/*
- * QSB RAM Transfer Data Register
- */
-#define QSB_RTD QSB_CONF_REG_ADDR(0x000C)
-
-#define QSB_RTD_TTV (*QSB_RTD)
-
-#define QSB_RTD_TTV_SET(value) ((value) & 0xFFFFFFFF)
-
-/*
- * QSB RAM Access Register
- */
-#define QSB_RAMAC QSB_CONF_REG_ADDR(0x000D)
-
-#define QSB_RAMAC_RW (*QSB_RAMAC & (1 << 31))
-#define QSB_RAMAC_TSEL GET_BITS(*QSB_RAMAC, 27, 24)
-#define QSB_RAMAC_LH (*QSB_RAMAC & (1 << 16))
-#define QSB_RAMAC_TESEL GET_BITS(*QSB_RAMAC, 9, 0)
-
-#define QSB_RAMAC_RW_SET(value) ((value) ? (1 << 31) : 0)
-#define QSB_RAMAC_TSEL_SET(value) SET_BITS(0, 27, 24, value)
-#define QSB_RAMAC_LH_SET(value) ((value) ? (1 << 16) : 0)
-#define QSB_RAMAC_TESEL_SET(value) SET_BITS(0, 9, 0, value)
-
-/*
- * QSB Queue Scheduling and Shaping Definitions
- */
-#define QSB_WFQ_NONUBR_MAX 0x3f00
-#define QSB_WFQ_UBR_BYPASS 0x3fff
-#define QSB_TP_TS_MAX 65472
-#define QSB_TAUS_MAX 64512
-#define QSB_GCR_MIN 18
-
-/*
- * QSB Constant
- */
-#define QSB_RAMAC_RW_READ 0
-#define QSB_RAMAC_RW_WRITE 1
-
-#define QSB_RAMAC_TSEL_QPT 0x01
-#define QSB_RAMAC_TSEL_SCT 0x02
-#define QSB_RAMAC_TSEL_SPT 0x03
-#define QSB_RAMAC_TSEL_VBR 0x08
-
-#define QSB_RAMAC_LH_LOW 0
-#define QSB_RAMAC_LH_HIGH 1
-
-#define QSB_QPT_SET_MASK 0x0
-#define QSB_QVPT_SET_MASK 0x0
-#define QSB_SET_SCT_MASK 0x0
-#define QSB_SET_SPT_MASK 0x0
-#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF
-
-#define QSB_SPT_SBV_VALID (1 << 31)
-#define QSB_SPT_PN_SET(value) (((value) & 0x01) ? (1 << 16) : 0)
-#define QSB_SPT_INTRATE_SET(value) SET_BITS(0, 13, 0, value)
-
-/*
- * QSB Queue Parameter Table Entry and Queue VBR Parameter Table Entry
- */
-#if defined(__BIG_ENDIAN)
- union qsb_queue_parameter_table {
- struct {
- unsigned int res1 :1;
- unsigned int vbr :1;
- unsigned int wfqf :14;
- unsigned int tp :16;
- } bit;
- u32 dword;
- };
-
- union qsb_queue_vbr_parameter_table {
- struct {
- unsigned int taus :16;
- unsigned int ts :16;
- } bit;
- u32 dword;
- };
-#else
- union qsb_queue_parameter_table {
- struct {
- unsigned int tp :16;
- unsigned int wfqf :14;
- unsigned int vbr :1;
- unsigned int res1 :1;
- } bit;
- u32 dword;
- };
-
- union qsb_queue_vbr_parameter_table {
- struct {
- unsigned int ts :16;
- unsigned int taus :16;
- } bit;
- u32 dword;
- };
-#endif // defined(__BIG_ENDIAN)
-
-/*
- * Mailbox IGU0 Registers
- */
-#define MBOX_IGU0_ISRS PPE_REG_ADDR(0x0200)
-#define MBOX_IGU0_ISRC PPE_REG_ADDR(0x0201)
-#define MBOX_IGU0_ISR PPE_REG_ADDR(0x0202)
-#define MBOX_IGU0_IER PPE_REG_ADDR(0x0203)
-
-#define MBOX_IGU0_ISRS_SET(n) (1 << (n))
-#define MBOX_IGU0_ISRC_CLEAR(n) (1 << (n))
-#define MBOX_IGU0_ISR_ISR(n) (*MBOX_IGU0_ISR & (1 << (n)))
-#define MBOX_IGU0_IER_EN(n) (*MBOX_IGU0_IER & (1 << (n)))
-#define MBOX_IGU0_IER_EN_SET(n) (1 << (n))
-
-/*
- * Mailbox IGU1 Registers
- */
-#define MBOX_IGU1_ISRS PPE_REG_ADDR(0x0204)
-#define MBOX_IGU1_ISRC PPE_REG_ADDR(0x0205)
-#define MBOX_IGU1_ISR PPE_REG_ADDR(0x0206)
-#define MBOX_IGU1_IER PPE_REG_ADDR(0x0207)
-
-#define MBOX_IGU1_ISRS_SET(n) (1 << (n))
-#define MBOX_IGU1_ISRC_CLEAR(n) (1 << (n))
-#define MBOX_IGU1_ISR_ISR(n) (*MBOX_IGU1_ISR & (1 << (n)))
-#define MBOX_IGU1_IER_EN(n) (*MBOX_IGU1_IER & (1 << (n)))
-#define MBOX_IGU1_IER_EN_SET(n) (1 << (n))
-
-/*
- * Mailbox IGU3 Registers
- */
-#define MBOX_IGU3_ISRS PPE_REG_ADDR(0x0214)
-#define MBOX_IGU3_ISRC PPE_REG_ADDR(0x0215)
-#define MBOX_IGU3_ISR PPE_REG_ADDR(0x0216)
-#define MBOX_IGU3_IER PPE_REG_ADDR(0x0217)
-
-#define MBOX_IGU3_ISRS_SET(n) (1 << (n))
-#define MBOX_IGU3_ISRC_CLEAR(n) (1 << (n))
-#define MBOX_IGU3_ISR_ISR(n) (*MBOX_IGU3_ISR & (1 << (n)))
-#define MBOX_IGU3_IER_EN(n) (*MBOX_IGU3_IER & (1 << (n)))
-#define MBOX_IGU3_IER_EN_SET(n) (1 << (n))
-
-/*
- * RTHA/TTHA Registers
- */
-#define SFSM_STATE0 PPE_REG_ADDR(0x0410)
-#define SFSM_STATE1 PPE_REG_ADDR(0x0411)
-#define SFSM_DBA0 PPE_REG_ADDR(0x0412)
-#define SFSM_DBA1 PPE_REG_ADDR(0x0413)
-#define SFSM_CBA0 PPE_REG_ADDR(0x0414)
-#define SFSM_CBA1 PPE_REG_ADDR(0x0415)
-#define SFSM_CFG0 PPE_REG_ADDR(0x0416)
-#define SFSM_CFG1 PPE_REG_ADDR(0x0417)
-#define SFSM_PGCNT0 PPE_REG_ADDR(0x041C)
-#define SFSM_PGCNT1 PPE_REG_ADDR(0x041D)
-#define FFSM_DBA0 PPE_REG_ADDR(0x0508)
-#define FFSM_DBA1 PPE_REG_ADDR(0x0509)
-#define FFSM_CFG0 PPE_REG_ADDR(0x050A)
-#define FFSM_CFG1 PPE_REG_ADDR(0x050B)
-#define FFSM_IDLE_HEAD_BC0 PPE_REG_ADDR(0x050E)
-#define FFSM_IDLE_HEAD_BC1 PPE_REG_ADDR(0x050F)
-#define FFSM_PGCNT0 PPE_REG_ADDR(0x0514)
-#define FFSM_PGCNT1 PPE_REG_ADDR(0x0515)
-
-
-
-#endif // IFXMIPS_ATM_PPE_COMMON_H
+++ /dev/null
-#ifndef IFXMIPS_ATM_PPE_DANUBE_H
-#define IFXMIPS_ATM_PPE_DANUBE_H
-
-
-
-/*
- * FPI Configuration Bus Register and Memory Address Mapping
- */
-#define IFX_PPE (KSEG1 | 0x1E180000)
-#define PP32_DEBUG_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2)))
-#define PPM_INT_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2)))
-#define PP32_INTERNAL_RES_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2)))
-#define CDM_CODE_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2)))
-#define PPE_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2)))
-#define CDM_DATA_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2)))
-#define PPM_INT_UNIT_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2)))
-#define PPM_TIMER0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2)))
-#define PPM_TASK_IND_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2)))
-#define PPS_BRK_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2)))
-#define PPM_TIMER1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2)))
-#define SB_RAM0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8000) << 2)))
-#define SB_RAM1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8400) << 2)))
-#define SB_RAM2_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2)))
-#define SB_RAM3_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9600) << 2)))
-#define QSB_CONF_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2)))
-
-/*
- * DWORD-Length of Memory Blocks
- */
-#define PP32_DEBUG_REG_DWLEN 0x0030
-#define PPM_INT_REG_DWLEN 0x0010
-#define PP32_INTERNAL_RES_DWLEN 0x00C0
-#define CDM_CODE_MEMORYn_DWLEN(n) ((n) == 0 ? 0x1000 : 0x0800)
-#define PPE_REG_DWLEN 0x1000
-#define CDM_DATA_MEMORY_DWLEN CDM_CODE_MEMORYn_DWLEN(1)
-#define PPM_INT_UNIT_DWLEN 0x0100
-#define PPM_TIMER0_DWLEN 0x0100
-#define PPM_TASK_IND_REG_DWLEN 0x0100
-#define PPS_BRK_DWLEN 0x0100
-#define PPM_TIMER1_DWLEN 0x0100
-#define SB_RAM0_DWLEN 0x0400
-#define SB_RAM1_DWLEN 0x0800
-#define SB_RAM2_DWLEN 0x0A00
-#define SB_RAM3_DWLEN 0x0400
-#define QSB_CONF_REG_DWLEN 0x0100
-
-/*
- * PP32 to FPI Address Mapping
- */
-#define SB_BUFFER(__sb_addr) ((volatile unsigned int *)((((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x23FF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) : \
- (((__sb_addr) >= 0x2400) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2400) : \
- (((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM2_ADDR((__sb_addr) - 0x2C00) : \
- (((__sb_addr) >= 0x3600) && ((__sb_addr) <= 0x39FF)) ? SB_RAM3_ADDR((__sb_addr) - 0x3600) : \
- 0))
-
-/*
- * PP32 Debug Control Register
- */
-#define PP32_DBG_CTRL PP32_DEBUG_REG_ADDR(0, 0x0000)
-
-#define DBG_CTRL_START_SET(value) ((value) ? (1 << 0) : 0)
-#define DBG_CTRL_STOP_SET(value) ((value) ? (1 << 1) : 0)
-#define DBG_CTRL_STEP_SET(value) ((value) ? (1 << 2) : 0)
-
-#define PP32_HALT_STAT PP32_DEBUG_REG_ADDR(0, 0x0001)
-
-#define PP32_BRK_SRC PP32_DEBUG_REG_ADDR(0, 0x0002)
-
-#define PP32_DBG_PC_MIN(i) PP32_DEBUG_REG_ADDR(0, 0x0010 + (i))
-#define PP32_DBG_PC_MAX(i) PP32_DEBUG_REG_ADDR(0, 0x0014 + (i))
-#define PP32_DBG_DATA_MIN(i) PP32_DEBUG_REG_ADDR(0, 0x0018 + (i))
-#define PP32_DBG_DATA_MAX(i) PP32_DEBUG_REG_ADDR(0, 0x001A + (i))
-#define PP32_DBG_DATA_VAL(i) PP32_DEBUG_REG_ADDR(0, 0x001C + (i))
-
-#define PP32_DBG_CUR_PC PP32_DEBUG_REG_ADDR(0, 0x0080)
-
-#define PP32_DBG_TASK_NO PP32_DEBUG_REG_ADDR(0, 0x0081)
-
-/*
- * EMA Registers
- */
-#define EMA_CMDCFG PPE_REG_ADDR(0x0A00)
-#define EMA_DATACFG PPE_REG_ADDR(0x0A01)
-#define EMA_CMDCNT PPE_REG_ADDR(0x0A02)
-#define EMA_DATACNT PPE_REG_ADDR(0x0A03)
-#define EMA_ISR PPE_REG_ADDR(0x0A04)
-#define EMA_IER PPE_REG_ADDR(0x0A05)
-#define EMA_CFG PPE_REG_ADDR(0x0A06)
-#define EMA_SUBID PPE_REG_ADDR(0x0A07)
-
-#define EMA_ALIGNMENT 4
-
-/*
- * Mailbox IGU1 Interrupt
- */
-#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
-
-
-
-#endif // IFXMIPS_ATM_PPE_DANUBE_H
+++ /dev/null
-/******************************************************************************
-
- Copyright (c) 2009
- Infineon Technologies AG
- Am Campeon 1-12; 81726 Munich, Germany
-
- For licensing information, see the file 'LICENSE' in the root folder of
- this software module.
-
-******************************************************************************/
-
-/*!
- \defgroup AMAZON_S_MEI Amazon-S MEI Driver Module
- \brief Amazon-S MEI driver module
- */
-
-/*!
- \defgroup Internal Compile Parametere
- \ingroup AMAZON_S_MEI
- \brief exported functions for other driver use
- */
-
-/*!
- \file amazon_s_mei_bsp.c
- \ingroup AMAZON_S_MEI
- \brief Amazon-S MEI driver file
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/version.h>
-#include <linux/utsrelease.h>
-#include <linux/types.h>
-#include <linux/fs.h>
-#include <linux/mm.h>
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/proc_fs.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <asm/uaccess.h>
-#include <asm/hardirq.h>
-#include <asm/ifx/ifx_regs.h>
-#include <asm/ifx/irq.h>
-#include <asm/ifx/ifx_gpio.h>
-//#include <asm/ifx/ifx_led.h>
-#include <asm/ifx/ifx_pmu.h>
-#include <asm/ifx/ifx_atm.h>
-#define IFX_MEI_BSP
-#include "ifxmips_mei_interface.h"
-
-#define IFXMIPS_RCU_RST IFX_RCU_RST_REQ
-#define IFXMIPS_RCU_RST_REQ_ARC_JTAG IFX_RCU_RST_REQ_ARC_JTAG
-#define IFXMIPS_RCU_RST_REQ_DFE IFX_RCU_RST_REQ_DFE
-#define IFXMIPS_RCU_RST_REQ_AFE IFX_RCU_RST_REQ_AFE
-#define IFXMIPS_FUSE_BASE_ADDR IFX_FUSE_BASE_ADDR
-#define IFXMIPS_ICU_IM0_IER IFX_ICU_IM0_IER
-#define IFXMIPS_ICU_IM2_IER IFX_ICU_IM2_IER
-#define IFXMIPS_MEI_INT IFX_MEI_INT
-#define IFXMIPS_MEI_DYING_GASP_INT IFX_MEI_DYING_GASP_INT
-#define IFXMIPS_MEI_BASE_ADDR IFX_MEI_SPACE_ACCESS
-#define IFXMIPS_PMU_PWDCR IFX_PMU_PWDCR
-#define IFXMIPS_MPS_CHIPID IFX_MPS_CHIPID
-
-#define ifxmips_port_reserve_pin ifx_gpio_pin_reserve
-#define ifxmips_port_set_dir_in ifx_gpio_dir_in_set
-#define ifxmips_port_clear_altsel0 ifx_gpio_altsel0_set
-#define ifxmips_port_clear_altsel1 ifx_gpio_altsel1_clear
-#define ifxmips_port_set_open_drain ifx_gpio_open_drain_clear
-#define ifxmips_port_free_pin ifx_gpio_pin_free
-#define ifxmips_mask_and_ack_irq bsp_mask_and_ack_irq
-#define IFXMIPS_MPS_CHIPID_VERSION_GET IFX_MCD_CHIPID_VERSION_GET
-#define ifxmips_r32(reg) __raw_readl(reg)
-#define ifxmips_w32(val, reg) __raw_writel(val, reg)
-#define ifxmips_w32_mask(clear, set, reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg)
-
-#define IFX_MEI_EMSG(fmt, args...) printk(KERN_ERR "[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args)
-#define IFX_MEI_DMSG(fmt, args...) printk(KERN_INFO "[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args)
-
-#ifdef CONFIG_IFXMIPS_MEI_FW_LOOPBACK
-//#define DFE_MEM_TEST
-//#define DFE_PING_TEST
-#define DFE_ATM_LOOPBACK
-
-#ifdef DFE_PING_TEST
-#include "dsp_xmem_arb_rand_em.h"
-#endif
-
-#ifdef DFE_MEM_TEST
-#include "aai_mem_test.h"
-#endif
-
-#ifdef DFE_ATM_LOOPBACK
-#include <asm/ifxmips/ifxmips_mei_fw_loopback.h>
-#endif
-
-void dfe_loopback_irq_handler (DSL_DEV_Device_t *pDev);
-
-#endif //CONFIG_AMAZON_S_MEI_FW_LOOPBACK
-
-DSL_DEV_Version_t bsp_mei_version = {
- major: 5,
- minor: 0,
- revision:0
-};
-DSL_DEV_HwVersion_t bsp_chip_info;
-
-#define IFX_MEI_DEVNAME "ifx_mei"
-#define BSP_MAX_DEVICES 1
-
-DSL_DEV_MeiError_t DSL_BSP_FWDownload (DSL_DEV_Device_t *, const char *, unsigned long, long *, long *);
-DSL_DEV_MeiError_t DSL_BSP_Showtime (DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t);
-DSL_DEV_MeiError_t DSL_BSP_AdslLedInit (DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t);
-//DSL_DEV_MeiError_t DSL_BSP_AdslLedSet (DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedMode_t);
-DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess (DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t*, DSL_uint32_t);
-DSL_DEV_MeiError_t DSL_BSP_SendCMV (DSL_DEV_Device_t *, u16 *, int, u16 *);
-
-int DSL_BSP_KernelIoctls (DSL_DEV_Device_t *, unsigned int, unsigned long);
-
-static DSL_DEV_MeiError_t IFX_MEI_RunAdslModem (DSL_DEV_Device_t *);
-static DSL_DEV_MeiError_t IFX_MEI_CpuModeSet (DSL_DEV_Device_t *, DSL_DEV_CpuMode_t);
-static DSL_DEV_MeiError_t IFX_MEI_DownloadBootCode (DSL_DEV_Device_t *);
-static DSL_DEV_MeiError_t IFX_MEI_ArcJtagEnable (DSL_DEV_Device_t *, int);
-static DSL_DEV_MeiError_t IFX_MEI_AdslMailboxIRQEnable (DSL_DEV_Device_t *, int);
-
-static int IFX_MEI_GetPage (DSL_DEV_Device_t *, u32, u32, u32, u32 *, u32 *);
-static int IFX_MEI_BarUpdate (DSL_DEV_Device_t *, int);
-
-static ssize_t IFX_MEI_Write (DSL_DRV_file_t *, const char *, size_t, loff_t *);
-static int IFX_MEI_UserIoctls (DSL_DRV_inode_t *, DSL_DRV_file_t *, unsigned int, unsigned long);
-static int IFX_MEI_Open (DSL_DRV_inode_t *, DSL_DRV_file_t *);
-static int IFX_MEI_Release (DSL_DRV_inode_t *, DSL_DRV_file_t *);
-
-void AMAZON_SE_MEI_ARC_MUX_Test(void);
-
-#ifdef CONFIG_PROC_FS
-static int IFX_MEI_ProcRead (struct file *, char *, size_t, loff_t *);
-static ssize_t IFX_MEI_ProcWrite (struct file *, const char *, size_t, loff_t *);
-
-#define PROC_ITEMS 11
-#define MEI_DIRNAME "ifxmips_mei"
-
-static struct proc_dir_entry *meidir;
-static struct file_operations IFX_MEI_ProcOperations = {
- read:IFX_MEI_ProcRead,
- write:IFX_MEI_ProcWrite,
-};
-static reg_entry_t regs[BSP_MAX_DEVICES][PROC_ITEMS]; //total items to be monitored by /proc/mei
-#define NUM_OF_REG_ENTRY (sizeof(regs[0])/sizeof(reg_entry_t))
-#endif //CONFIG_PROC_FS
-
-void IFX_MEI_ARC_MUX_Test(void);
-
-static int adsl_dummy_ledcallback(void);
-
-int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
-EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);
-
-int (*ifx_mei_atm_showtime_exit)(void) = NULL;
-EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);
-
-static int (*g_adsl_ledcallback)(void) = adsl_dummy_ledcallback;
-
-static unsigned int g_tx_link_rate[2] = {0};
-
-static void *g_xdata_addr = NULL;
-
-static u32 *mei_arc_swap_buff = NULL; // holding swap pages
-
-extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);
-#define MEI_MASK_AND_ACK_IRQ ifxmips_mask_and_ack_irq
-
-static int dev_major = 105;
-
-static struct file_operations bsp_mei_operations = {
- owner:THIS_MODULE,
- open:IFX_MEI_Open,
- release:IFX_MEI_Release,
- write:IFX_MEI_Write,
- ioctl:IFX_MEI_UserIoctls,
-};
-
-static DSL_DEV_Device_t dsl_devices[BSP_MAX_DEVICES];
-
-static ifx_mei_device_private_t
- sDanube_Mei_Private[BSP_MAX_DEVICES];
-
-static DSL_BSP_EventCallBack_t dsl_bsp_event_callback[DSL_BSP_CB_LAST + 1];
-
-/**
- * Write a value to register
- * This function writes a value to danube register
- *
- * \param ul_address The address to write
- * \param ul_data The value to write
- * \ingroup Internal
- */
-static void
-IFX_MEI_LongWordWrite (u32 ul_address, u32 ul_data)
-{
- IFX_MEI_WRITE_REGISTER_L (ul_data, ul_address);
- wmb();
- return;
-}
-
-/**
- * Write a value to register
- * This function writes a value to danube register
- *
- * \param pDev the device pointer
- * \param ul_address The address to write
- * \param ul_data The value to write
- * \ingroup Internal
- */
-static void
-IFX_MEI_LongWordWriteOffset (DSL_DEV_Device_t * pDev, u32 ul_address,
- u32 ul_data)
-{
- IFX_MEI_WRITE_REGISTER_L (ul_data, pDev->base_address + ul_address);
- wmb();
- return;
-}
-
-/**
- * Read the danube register
- * This function read the value from danube register
- *
- * \param ul_address The address to write
- * \param pul_data Pointer to the data
- * \ingroup Internal
- */
-static void
-IFX_MEI_LongWordRead (u32 ul_address, u32 * pul_data)
-{
- *pul_data = IFX_MEI_READ_REGISTER_L (ul_address);
- rmb();
- return;
-}
-
-/**
- * Read the danube register
- * This function read the value from danube register
- *
- * \param pDev the device pointer
- * \param ul_address The address to write
- * \param pul_data Pointer to the data
- * \ingroup Internal
- */
-static void
-IFX_MEI_LongWordReadOffset (DSL_DEV_Device_t * pDev, u32 ul_address,
- u32 * pul_data)
-{
- *pul_data = IFX_MEI_READ_REGISTER_L (pDev->base_address + ul_address);
- rmb();
- return;
-}
-
-/**
- * Write several DWORD datas to ARC memory via ARC DMA interface
- * This function writes several DWORD datas to ARC memory via DMA interface.
- *
- * \param pDev the device pointer
- * \param destaddr The address to write
- * \param databuff Pointer to the data buffer
- * \param databuffsize Number of DWORDs to write
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-IFX_MEI_DMAWrite (DSL_DEV_Device_t * pDev, u32 destaddr,
- u32 * databuff, u32 databuffsize)
-{
- u32 *p = databuff;
- u32 temp;
-
- if (destaddr & 3)
- return DSL_DEV_MEI_ERR_FAILURE;
-
- // Set the write transfer address
- IFX_MEI_LongWordWriteOffset (pDev, ME_DX_AD, destaddr);
-
- // Write the data pushed across DMA
- while (databuffsize--) {
- temp = *p;
- if (destaddr == MEI_TO_ARC_MAILBOX)
- MEI_HALF_WORD_SWAP (temp);
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DX_DATA, temp);
- p++;
- }
-
- return DSL_DEV_MEI_ERR_SUCCESS;
-
-}
-
-/**
- * Read several DWORD datas from ARC memory via ARC DMA interface
- * This function reads several DWORD datas from ARC memory via DMA interface.
- *
- * \param pDev the device pointer
- * \param srcaddr The address to read
- * \param databuff Pointer to the data buffer
- * \param databuffsize Number of DWORDs to read
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-IFX_MEI_DMARead (DSL_DEV_Device_t * pDev, u32 srcaddr, u32 * databuff,
- u32 databuffsize)
-{
- u32 *p = databuff;
- u32 temp;
-
- if (srcaddr & 3)
- return DSL_DEV_MEI_ERR_FAILURE;
-
- // Set the read transfer address
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DX_AD, srcaddr);
-
- // Read the data popped across DMA
- while (databuffsize--) {
- IFX_MEI_LongWordReadOffset (pDev, (u32) ME_DX_DATA, &temp);
- if (databuff == (u32 *) DSL_DEV_PRIVATE(pDev)->CMV_RxMsg) // swap half word
- MEI_HALF_WORD_SWAP (temp);
- *p = temp;
- p++;
- }
-
- return DSL_DEV_MEI_ERR_SUCCESS;
-
-}
-
-/**
- * Switch the ARC control mode
- * This function switchs the ARC control mode to JTAG mode or MEI mode
- *
- * \param pDev the device pointer
- * \param mode The mode want to switch: JTAG_MASTER_MODE or MEI_MASTER_MODE.
- * \ingroup Internal
- */
-static void
-IFX_MEI_ControlModeSet (DSL_DEV_Device_t * pDev, int mode)
-{
- u32 temp = 0x0;
-
- IFX_MEI_LongWordReadOffset (pDev, (u32) ME_DBG_MASTER, &temp);
- switch (mode) {
- case JTAG_MASTER_MODE:
- temp &= ~(HOST_MSTR);
- break;
- case MEI_MASTER_MODE:
- temp |= (HOST_MSTR);
- break;
- default:
- IFX_MEI_EMSG ("IFX_MEI_ControlModeSet: unkonwn mode [%d]\n", mode);
- return;
- }
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_MASTER, temp);
-}
-
-/**
- * Disable ARC to MEI interrupt
- *
- * \param pDev the device pointer
- * \ingroup Internal
- */
-static void
-IFX_MEI_IRQDisable (DSL_DEV_Device_t * pDev)
-{
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_MASK, 0x0);
-}
-
-/**
- * Eable ARC to MEI interrupt
- *
- * \param pDev the device pointer
- * \ingroup Internal
- */
-static void
-IFX_MEI_IRQEnable (DSL_DEV_Device_t * pDev)
-{
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_MASK, MSGAV_EN);
-}
-
-/**
- * Poll for transaction complete signal
- * This function polls and waits for transaction complete signal.
- *
- * \param pDev the device pointer
- * \ingroup Internal
- */
-static void
-meiPollForDbgDone (DSL_DEV_Device_t * pDev)
-{
- u32 query = 0;
- int i = 0;
-
- while (i < WHILE_DELAY) {
- IFX_MEI_LongWordReadOffset (pDev, (u32) ME_ARC2ME_STAT, &query);
- query &= (ARC_TO_MEI_DBG_DONE);
- if (query)
- break;
- i++;
- if (i == WHILE_DELAY) {
- IFX_MEI_EMSG ("PollforDbg fail!\n");
- }
- }
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_DBG_DONE); // to clear this interrupt
-}
-
-/**
- * ARC Debug Memory Access for a single DWORD reading.
- * This function used for direct, address-based access to ARC memory.
- *
- * \param pDev the device pointer
- * \param DEC_mode ARC memory space to used
- * \param address Address to read
- * \param data Pointer to data
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-_IFX_MEI_DBGLongWordRead (DSL_DEV_Device_t * pDev, u32 DEC_mode,
- u32 address, u32 * data)
-{
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_DECODE, DEC_mode);
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_RD_AD, address);
- meiPollForDbgDone (pDev);
- IFX_MEI_LongWordReadOffset (pDev, (u32) ME_DBG_DATA, data);
- return DSL_DEV_MEI_ERR_SUCCESS;
-}
-
-/**
- * ARC Debug Memory Access for a single DWORD writing.
- * This function used for direct, address-based access to ARC memory.
- *
- * \param pDev the device pointer
- * \param DEC_mode ARC memory space to used
- * \param address The address to write
- * \param data The data to write
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-_IFX_MEI_DBGLongWordWrite (DSL_DEV_Device_t * pDev, u32 DEC_mode,
- u32 address, u32 data)
-{
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_DECODE, DEC_mode);
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_WR_AD, address);
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_DATA, data);
- meiPollForDbgDone (pDev);
- return DSL_DEV_MEI_ERR_SUCCESS;
-}
-
-/**
- * ARC Debug Memory Access for writing.
- * This function used for direct, address-based access to ARC memory.
- *
- * \param pDev the device pointer
- * \param destaddr The address to read
- * \param databuffer Pointer to data
- * \param databuffsize The number of DWORDs to read
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-
-static DSL_DEV_MeiError_t
-IFX_MEI_DebugWrite (DSL_DEV_Device_t * pDev, u32 destaddr,
- u32 * databuff, u32 databuffsize)
-{
- u32 i;
- u32 temp = 0x0;
- u32 address = 0x0;
- u32 *buffer = 0x0;
-
- // Open the debug port before DMP memory write
- IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
-
- // For the requested length, write the address and write the data
- address = destaddr;
- buffer = databuff;
- for (i = 0; i < databuffsize; i++) {
- temp = *buffer;
- _IFX_MEI_DBGLongWordWrite (pDev, ME_DBG_DECODE_DMP1_MASK, address, temp);
- address += 4;
- buffer++;
- }
-
- // Close the debug port after DMP memory write
- IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
-
- return DSL_DEV_MEI_ERR_SUCCESS;
-}
-
-/**
- * ARC Debug Memory Access for reading.
- * This function used for direct, address-based access to ARC memory.
- *
- * \param pDev the device pointer
- * \param srcaddr The address to read
- * \param databuffer Pointer to data
- * \param databuffsize The number of DWORDs to read
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-IFX_MEI_DebugRead (DSL_DEV_Device_t * pDev, u32 srcaddr, u32 * databuff, u32 databuffsize)
-{
- u32 i;
- u32 temp = 0x0;
- u32 address = 0x0;
- u32 *buffer = 0x0;
-
- // Open the debug port before DMP memory read
- IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
-
- // For the requested length, write the address and read the data
- address = srcaddr;
- buffer = databuff;
- for (i = 0; i < databuffsize; i++) {
- _IFX_MEI_DBGLongWordRead (pDev, ME_DBG_DECODE_DMP1_MASK, address, &temp);
- *buffer = temp;
- address += 4;
- buffer++;
- }
-
- // Close the debug port after DMP memory read
- IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
-
- return DSL_DEV_MEI_ERR_SUCCESS;
-}
-
-/**
- * Send a message to ARC MailBox.
- * This function sends a message to ARC Mailbox via ARC DMA interface.
- *
- * \param pDev the device pointer
- * \param msgsrcbuffer Pointer to message.
- * \param msgsize The number of words to write.
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-IFX_MEI_MailboxWrite (DSL_DEV_Device_t * pDev, u16 * msgsrcbuffer,
- u16 msgsize)
-{
- int i;
- u32 arc_mailbox_status = 0x0;
- u32 temp = 0;
- DSL_DEV_MeiError_t meiMailboxError = DSL_DEV_MEI_ERR_SUCCESS;
-
- // Write to mailbox
- meiMailboxError =
- IFX_MEI_DMAWrite (pDev, MEI_TO_ARC_MAILBOX, (u32 *) msgsrcbuffer, msgsize / 2);
- meiMailboxError =
- IFX_MEI_DMAWrite (pDev, MEI_TO_ARC_MAILBOXR, (u32 *) (&temp), 1);
-
- // Notify arc that mailbox write completed
- DSL_DEV_PRIVATE(pDev)->cmv_waiting = 1;
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ME2ARC_INT, MEI_TO_ARC_MSGAV);
-
- i = 0;
- while (i < WHILE_DELAY) { // wait for ARC to clear the bit
- IFX_MEI_LongWordReadOffset (pDev, (u32) ME_ME2ARC_INT, &arc_mailbox_status);
- if ((arc_mailbox_status & MEI_TO_ARC_MSGAV) != MEI_TO_ARC_MSGAV)
- break;
- i++;
- if (i == WHILE_DELAY) {
- IFX_MEI_EMSG (">>> Timeout waiting for ARC to clear MEI_TO_ARC_MSGAV!!!"
- " MEI_TO_ARC message size = %d DWORDs <<<\n", msgsize/2);
- meiMailboxError = DSL_DEV_MEI_ERR_FAILURE;
- }
- }
-
- return meiMailboxError;
-}
-
-/**
- * Read a message from ARC MailBox.
- * This function reads a message from ARC Mailbox via ARC DMA interface.
- *
- * \param pDev the device pointer
- * \param msgsrcbuffer Pointer to message.
- * \param msgsize The number of words to read
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-IFX_MEI_MailboxRead (DSL_DEV_Device_t * pDev, u16 * msgdestbuffer,
- u16 msgsize)
-{
- DSL_DEV_MeiError_t meiMailboxError = DSL_DEV_MEI_ERR_SUCCESS;
- // Read from mailbox
- meiMailboxError =
- IFX_MEI_DMARead (pDev, ARC_TO_MEI_MAILBOX, (u32 *) msgdestbuffer, msgsize / 2);
-
- // Notify arc that mailbox read completed
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_MSGAV);
-
- return meiMailboxError;
-}
-
-/**
- * Download boot pages to ARC.
- * This function downloads boot pages to ARC.
- *
- * \param pDev the device pointer
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-IFX_MEI_DownloadBootPages (DSL_DEV_Device_t * pDev)
-{
- int boot_loop;
- int page_size;
- u32 dest_addr;
-
- /*
- ** DMA the boot code page(s)
- */
-
- for (boot_loop = 1;
- boot_loop <
- (DSL_DEV_PRIVATE(pDev)->img_hdr-> count); boot_loop++) {
- if ((DSL_DEV_PRIVATE(pDev)-> img_hdr->page[boot_loop].p_size) & BOOT_FLAG) {
- page_size = IFX_MEI_GetPage (pDev, boot_loop,
- GET_PROG, MAXSWAPSIZE,
- mei_arc_swap_buff,
- &dest_addr);
- if (page_size > 0) {
- IFX_MEI_DMAWrite (pDev, dest_addr,
- mei_arc_swap_buff,
- page_size);
- }
- }
- if ((DSL_DEV_PRIVATE(pDev)-> img_hdr->page[boot_loop].d_size) & BOOT_FLAG) {
- page_size = IFX_MEI_GetPage (pDev, boot_loop,
- GET_DATA, MAXSWAPSIZE,
- mei_arc_swap_buff,
- &dest_addr);
- if (page_size > 0) {
- IFX_MEI_DMAWrite (pDev, dest_addr,
- mei_arc_swap_buff,
- page_size);
- }
- }
- }
- return DSL_DEV_MEI_ERR_SUCCESS;
-}
-
-/**
- * Initial efuse rar.
- **/
-static void
-IFX_MEI_FuseInit (DSL_DEV_Device_t * pDev)
-{
- u32 data = 0;
- IFX_MEI_DMAWrite (pDev, IRAM0_BASE, &data, 1);
- IFX_MEI_DMAWrite (pDev, IRAM0_BASE + 4, &data, 1);
- IFX_MEI_DMAWrite (pDev, IRAM1_BASE, &data, 1);
- IFX_MEI_DMAWrite (pDev, IRAM1_BASE + 4, &data, 1);
- IFX_MEI_DMAWrite (pDev, BRAM_BASE, &data, 1);
- IFX_MEI_DMAWrite (pDev, BRAM_BASE + 4, &data, 1);
- IFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE, &data, 1);
- IFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE + 4, &data, 1);
-}
-
-/**
- * efuse rar program
- **/
-static void
-IFX_MEI_FuseProg (DSL_DEV_Device_t * pDev)
-{
- u32 reg_data, fuse_value;
- int i = 0;
-
- IFX_MEI_LongWordRead ((u32) IFXMIPS_RCU_RST, ®_data);
- while ((reg_data & 0x10000000) == 0) {
- IFX_MEI_LongWordRead ((u32) IFXMIPS_RCU_RST, ®_data);
- i++;
- /* 0x4000 translate to about 16 ms@111M, so should be enough */
- if (i == 0x4000)
- return;
- }
- // STEP a: Prepare memory for external accesses
- // Write fuse_en bit24
- IFX_MEI_LongWordRead ((u32) IFXMIPS_RCU_RST, ®_data);
- IFX_MEI_LongWordWrite ((u32) IFXMIPS_RCU_RST, reg_data | (1 << 24));
-
- IFX_MEI_FuseInit (pDev);
- for (i = 0; i < 4; i++) {
- IFX_MEI_LongWordRead ((u32) (IFXMIPS_FUSE_BASE_ADDR) + i * 4, &fuse_value);
- switch (fuse_value & 0xF0000) {
- case 0x80000:
- reg_data = ((fuse_value & RX_DILV_ADDR_BIT_MASK) |
- (RX_DILV_ADDR_BIT_MASK + 0x1));
- IFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE, ®_data, 1);
- break;
- case 0x90000:
- reg_data = ((fuse_value & RX_DILV_ADDR_BIT_MASK) |
- (RX_DILV_ADDR_BIT_MASK + 0x1));
- IFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE + 4, ®_data, 1);
- break;
- case 0xA0000:
- reg_data = ((fuse_value & IRAM0_ADDR_BIT_MASK) |
- (IRAM0_ADDR_BIT_MASK + 0x1));
- IFX_MEI_DMAWrite (pDev, IRAM0_BASE, ®_data, 1);
- break;
- case 0xB0000:
- reg_data = ((fuse_value & IRAM0_ADDR_BIT_MASK) |
- (IRAM0_ADDR_BIT_MASK + 0x1));
- IFX_MEI_DMAWrite (pDev, IRAM0_BASE + 4, ®_data, 1);
- break;
- case 0xC0000:
- reg_data = ((fuse_value & IRAM1_ADDR_BIT_MASK) |
- (IRAM1_ADDR_BIT_MASK + 0x1));
- IFX_MEI_DMAWrite (pDev, IRAM1_BASE, ®_data, 1);
- break;
- case 0xD0000:
- reg_data = ((fuse_value & IRAM1_ADDR_BIT_MASK) |
- (IRAM1_ADDR_BIT_MASK + 0x1));
- IFX_MEI_DMAWrite (pDev, IRAM1_BASE + 4, ®_data, 1);
- break;
- case 0xE0000:
- reg_data = ((fuse_value & BRAM_ADDR_BIT_MASK) |
- (BRAM_ADDR_BIT_MASK + 0x1));
- IFX_MEI_DMAWrite (pDev, BRAM_BASE, ®_data, 1);
- break;
- case 0xF0000:
- reg_data = ((fuse_value & BRAM_ADDR_BIT_MASK) |
- (BRAM_ADDR_BIT_MASK + 0x1));
- IFX_MEI_DMAWrite (pDev, BRAM_BASE + 4, ®_data, 1);
- break;
- default: // PPE efuse
- break;
- }
- }
- IFX_MEI_LongWordRead ((u32) IFXMIPS_RCU_RST, ®_data);
- IFX_MEI_LongWordWrite ((u32) IFXMIPS_RCU_RST, reg_data & ~(1 << 24));
- IFX_MEI_LongWordRead ((u32) IFXMIPS_RCU_RST, ®_data);
-}
-
-/**
- * Enable DFE Clock
- * This function enables DFE Clock
- *
- * \param pDev the device pointer
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-IFX_MEI_EnableCLK (DSL_DEV_Device_t * pDev)
-{
- u32 arc_debug_data = 0;
- IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
- //enable ac_clk signal
- _IFX_MEI_DBGLongWordRead (pDev, ME_DBG_DECODE_DMP1_MASK,
- CRI_CCR0, &arc_debug_data);
- arc_debug_data |= ACL_CLK_MODE_ENABLE;
- _IFX_MEI_DBGLongWordWrite (pDev, ME_DBG_DECODE_DMP1_MASK,
- CRI_CCR0, arc_debug_data);
- IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
- return DSL_DEV_MEI_ERR_SUCCESS;
-}
-
-/**
- * Halt the ARC.
- * This function halts the ARC.
- *
- * \param pDev the device pointer
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-IFX_MEI_HaltArc (DSL_DEV_Device_t * pDev)
-{
- u32 arc_debug_data = 0x0;
-
- // Switch arc control from JTAG mode to MEI mode
- IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
- _IFX_MEI_DBGLongWordRead (pDev, MEI_DEBUG_DEC_AUX_MASK,
- ARC_DEBUG, &arc_debug_data);
- arc_debug_data |= ARC_DEBUG_HALT;
- _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,
- ARC_DEBUG, arc_debug_data);
- // Switch arc control from MEI mode to JTAG mode
- IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
-
- MEI_WAIT (10);
-
- return DSL_DEV_MEI_ERR_SUCCESS;
-}
-
-/**
- * Run the ARC.
- * This function runs the ARC.
- *
- * \param pDev the device pointer
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-IFX_MEI_RunArc (DSL_DEV_Device_t * pDev)
-{
- u32 arc_debug_data = 0x0;
-
- // Switch arc control from JTAG mode to MEI mode- write '1' to bit0
- IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
- _IFX_MEI_DBGLongWordRead (pDev, MEI_DEBUG_DEC_AUX_MASK,
- AUX_STATUS, &arc_debug_data);
-
- // Write debug data reg with content ANDd with 0xFDFFFFFF (halt bit cleared)
- arc_debug_data &= ~ARC_AUX_HALT;
- _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,
- AUX_STATUS, arc_debug_data);
-
- // Switch arc control from MEI mode to JTAG mode- write '0' to bit0
- IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
- // Enable mask for arc codeswap interrupts
- IFX_MEI_IRQEnable (pDev);
-
- return DSL_DEV_MEI_ERR_SUCCESS;
-
-}
-
-/**
- * Reset the ARC.
- * This function resets the ARC.
- *
- * \param pDev the device pointer
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-IFX_MEI_ResetARC (DSL_DEV_Device_t * pDev)
-{
- u32 arc_debug_data = 0;
-
- IFX_MEI_HaltArc (pDev);
-
- IFX_MEI_LongWordRead ((u32) IFXMIPS_RCU_RST, &arc_debug_data);
- IFX_MEI_LongWordWrite ((u32) IFXMIPS_RCU_RST,
- arc_debug_data | IFXMIPS_RCU_RST_REQ_DFE | IFXMIPS_RCU_RST_REQ_AFE);
-
- // reset ARC
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_RST_CTRL, MEI_SOFT_RESET);
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_RST_CTRL, 0);
-
- IFX_MEI_IRQDisable (pDev);
-
- IFX_MEI_EnableCLK (pDev);
-
-#if 0
- // reset part of PPE
- *(unsigned long *) (BSP_PPE32_SRST) = 0xC30;
- *(unsigned long *) (BSP_PPE32_SRST) = 0xFFF;
-#endif
-
- DSL_DEV_PRIVATE(pDev)->modem_ready = 0;
-
- return DSL_DEV_MEI_ERR_SUCCESS;
-}
-
-DSL_DEV_MeiError_t
-DSL_BSP_Showtime (DSL_DEV_Device_t * dev, DSL_uint32_t rate_fast, DSL_uint32_t rate_intl)
-{
- struct port_cell_info port_cell = {0};
-
- IFX_MEI_EMSG ("Datarate US intl = %d, fast = %d\n", (int)rate_intl,
- (int)rate_fast);
-
- if ( rate_fast )
- g_tx_link_rate[0] = rate_fast / (53 * 8);
- if ( rate_intl )
- g_tx_link_rate[1] = rate_intl / (53 * 8);
-
- if ( g_tx_link_rate[0] == 0 && g_tx_link_rate[1] == 0 ) {
- IFX_MEI_EMSG ("Got rate fail.\n");
- }
-
- if ( ifx_mei_atm_showtime_enter )
- {
- port_cell.port_num = 2;
- port_cell.tx_link_rate[0] = g_tx_link_rate[0];
- port_cell.tx_link_rate[1] = g_tx_link_rate[1];
- ifx_mei_atm_showtime_enter(&port_cell, g_xdata_addr);
- }
- else
- {
- IFX_MEI_EMSG("no hookup from ATM driver to set cell rate\n");
- }
-
- return DSL_DEV_MEI_ERR_SUCCESS;
-};
-
-/**
- * Reset/halt/run the DFE.
- * This function provide operations to reset/halt/run the DFE.
- *
- * \param pDev the device pointer
- * \param mode which operation want to do
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-IFX_MEI_CpuModeSet (DSL_DEV_Device_t *pDev,
- DSL_DEV_CpuMode_t mode)
-{
- DSL_DEV_MeiError_t err_ret = DSL_DEV_MEI_ERR_FAILURE;
- switch (mode) {
- case DSL_CPU_HALT:
- err_ret = IFX_MEI_HaltArc (pDev);
- break;
- case DSL_CPU_RUN:
- err_ret = IFX_MEI_RunArc (pDev);
- break;
- case DSL_CPU_RESET:
- err_ret = IFX_MEI_ResetARC (pDev);
- break;
- default:
- break;
- }
- return err_ret;
-}
-
-/**
- * Accress DFE memory.
- * This function provide a way to access DFE memory;
- *
- * \param pDev the device pointer
- * \param type read or write
- * \param destaddr destination address
- * \param databuff pointer to hold data
- * \param databuffsize size want to read/write
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-DSL_DEV_MeiError_t
-DSL_BSP_MemoryDebugAccess (DSL_DEV_Device_t * pDev,
- DSL_BSP_MemoryAccessType_t type,
- DSL_uint32_t destaddr, DSL_uint32_t *databuff,
- DSL_uint32_t databuffsize)
-{
- DSL_DEV_MeiError_t meierr = DSL_DEV_MEI_ERR_SUCCESS;
- switch (type) {
- case DSL_BSP_MEMORY_READ:
- meierr = IFX_MEI_DebugRead (pDev, (u32)destaddr, (u32*)databuff, (u32)databuffsize);
- break;
- case DSL_BSP_MEMORY_WRITE:
- meierr = IFX_MEI_DebugWrite (pDev, (u32)destaddr, (u32*)databuff, (u32)databuffsize);
- break;
- }
- return DSL_DEV_MEI_ERR_SUCCESS;
-};
-
-/**
- * Download boot code to ARC.
- * This function downloads boot code to ARC.
- *
- * \param pDev the device pointer
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-IFX_MEI_DownloadBootCode (DSL_DEV_Device_t *pDev)
-{
- IFX_MEI_IRQDisable (pDev);
-
- IFX_MEI_EnableCLK (pDev);
-
- IFX_MEI_FuseProg (pDev); //program fuse rar
-
- IFX_MEI_DownloadBootPages (pDev);
-
- return DSL_DEV_MEI_ERR_SUCCESS;
-};
-
-/**
- * Enable Jtag debugger interface
- * This function setups mips gpio to enable jtag debugger
- *
- * \param pDev the device pointer
- * \param enable enable or disable
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-IFX_MEI_ArcJtagEnable (DSL_DEV_Device_t *dev, int enable)
-{
- int meierr=0;
- u32 reg_data;
-
- switch (enable) {
- case 1:
- //reserve gpio 9, 10, 11, 14, 19 for ARC JTAG
- ifxmips_port_reserve_pin (0, 9);
- ifxmips_port_reserve_pin (0, 10);
- ifxmips_port_reserve_pin (0, 11);
- ifxmips_port_reserve_pin (0, 14);
- ifxmips_port_reserve_pin (1, 3);
-
- ifxmips_port_set_dir_in(0, 11);
- ifxmips_port_clear_altsel0(0, 11);
- ifxmips_port_clear_altsel1(0, 11);
- ifxmips_port_set_open_drain(0, 11);
- //enable ARC JTAG
- IFX_MEI_LongWordRead ((u32) IFXMIPS_RCU_RST, ®_data);
- IFX_MEI_LongWordWrite ((u32) IFXMIPS_RCU_RST, reg_data | IFXMIPS_RCU_RST_REQ_ARC_JTAG);
- break;
- case 0:
- default:
- //reserve gpio 9, 10, 11, 14, 19 for ARC JTAG
- meierr = ifxmips_port_free_pin (0, 9);
- if (meierr < 0) {
- IFX_MEI_EMSG ("Reserve GPIO 9 Fail.\n");
- goto jtag_end;
- }
- meierr = ifxmips_port_free_pin (0, 10);
- if (meierr < 0) {
- IFX_MEI_EMSG ("Reserve GPIO 10 Fail.\n");
- goto jtag_end;
- }
- meierr = ifxmips_port_free_pin (0, 11);
- if (meierr < 0) {
- IFX_MEI_EMSG ("Reserve GPIO 11 Fail.\n");
- goto jtag_end;
- }
- meierr = ifxmips_port_free_pin (0, 14);
- if (meierr < 0) {
- IFX_MEI_EMSG ("Reserve GPIO 14 Fail.\n");
- goto jtag_end;
- }
- meierr = ifxmips_port_free_pin (1, 3);
- if (meierr < 0) {
- IFX_MEI_EMSG ("Reserve GPIO 19 Fail.\n");
- goto jtag_end;
- }
- break;
- }
-jtag_end:
- if (meierr)
- return DSL_DEV_MEI_ERR_FAILURE;
-
- return DSL_DEV_MEI_ERR_SUCCESS;
-};
-
-/**
- * Enable DFE to MIPS interrupt
- * This function enable DFE to MIPS interrupt
- *
- * \param pDev the device pointer
- * \param enable enable or disable
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-IFX_MEI_AdslMailboxIRQEnable (DSL_DEV_Device_t *pDev, int enable)
-{
- DSL_DEV_MeiError_t meierr;
- switch (enable) {
- case 0:
- meierr = DSL_DEV_MEI_ERR_SUCCESS;
- IFX_MEI_IRQDisable (pDev);
- break;
- case 1:
- IFX_MEI_IRQEnable (pDev);
- meierr = DSL_DEV_MEI_ERR_SUCCESS;
- break;
- default:
- meierr = DSL_DEV_MEI_ERR_FAILURE;
- break;
-
- }
- return meierr;
-}
-
-/**
- * Get the modem status
- * This function return the modem status
- *
- * \param pDev the device pointer
- * \return 1: modem ready 0: not ready
- * \ingroup Internal
- */
-static int
-IFX_MEI_IsModemReady (DSL_DEV_Device_t * pDev)
-{
- return DSL_DEV_PRIVATE(pDev)->modem_ready;
-}
-
-DSL_DEV_MeiError_t
-DSL_BSP_AdslLedInit (DSL_DEV_Device_t * dev,
- DSL_DEV_LedId_t led_number,
- DSL_DEV_LedType_t type,
- DSL_DEV_LedHandler_t handler)
-{
-#if 0
- struct led_config_param param;
- if (led_number == DSL_LED_LINK_ID && type == DSL_LED_LINK_TYPE && handler == /*DSL_LED_HD_CPU*/DSL_LED_HD_FW) {
- param.operation_mask = CONFIG_OPERATION_UPDATE_SOURCE;
- param.led = 0x01;
- param.source = 0x01;
-// bsp_led_config (¶m);
-
- } else if (led_number == DSL_LED_DATA_ID && type == DSL_LED_DATA_TYPE && (handler == DSL_LED_HD_FW)) {
- param.operation_mask = CONFIG_OPERATION_UPDATE_SOURCE;
- param.led = 0x02;
- param.source = 0x02;
-// bsp_led_config (¶m);
- }
-#endif
- return DSL_DEV_MEI_ERR_SUCCESS;
-};
-#if 0
-DSL_DEV_MeiError_t
-DSL_BSP_AdslLedSet (DSL_DEV_Device_t * dev, DSL_DEV_LedId_t led_number, DSL_DEV_LedMode_t mode)
-{
- printk(KERN_INFO "[%s %d]: mode = %#x, led_number = %d\n", __func__, __LINE__, mode, led_number);
- switch (mode) {
- case DSL_LED_OFF:
- switch (led_number) {
- case DSL_LED_LINK_ID:
-#ifdef CONFIG_BSP_LED
- bsp_led_set_blink (1, 0);
- bsp_led_set_data (1, 0);
-#endif
- break;
- case DSL_LED_DATA_ID:
-#ifdef CONFIG_BSP_LED
- bsp_led_set_blink (0, 0);
- bsp_led_set_data (0, 0);
-#endif
- break;
- }
- break;
- case DSL_LED_FLASH:
- switch (led_number) {
- case DSL_LED_LINK_ID:
-#ifdef CONFIG_BSP_LED
- bsp_led_set_blink (1, 1); // data
-#endif
- break;
- case DSL_LED_DATA_ID:
-#ifdef CONFIG_BSP_LED
- bsp_led_set_blink (0, 1); // data
-#endif
- break;
- }
- break;
- case DSL_LED_ON:
- switch (led_number) {
- case DSL_LED_LINK_ID:
-#ifdef CONFIG_BSP_LED
- bsp_led_set_blink (1, 0);
- bsp_led_set_data (1, 1);
-#endif
- break;
- case DSL_LED_DATA_ID:
-#ifdef CONFIG_BSP_LED
- bsp_led_set_blink (0, 0);
- bsp_led_set_data (0, 1);
-#endif
- break;
- }
- break;
- }
- return DSL_DEV_MEI_ERR_SUCCESS;
-};
-
-#endif
-
-/**
-* Compose a message.
-* This function compose a message from opcode, group, address, index, size, and data
-*
-* \param opcode The message opcode
-* \param group The message group number
-* \param address The message address.
-* \param index The message index.
-* \param size The number of words to read/write.
-* \param data The pointer to data.
-* \param CMVMSG The pointer to message buffer.
-* \ingroup Internal
-*/
-void
-makeCMV (u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data, u16 *CMVMSG)
-{
- memset (CMVMSG, 0, MSG_LENGTH * 2);
- CMVMSG[0] = (opcode << 4) + (size & 0xf);
- CMVMSG[1] = (((index == 0) ? 0 : 1) << 7) + (group & 0x7f);
- CMVMSG[2] = address;
- CMVMSG[3] = index;
- if (opcode == H2D_CMV_WRITE)
- memcpy (CMVMSG + 4, data, size * 2);
- return;
-}
-
-/**
- * Send a message to ARC and read the response
- * This function sends a message to arc, waits the response, and reads the responses.
- *
- * \param pDev the device pointer
- * \param request Pointer to the request
- * \param reply Wait reply or not.
- * \param response Pointer to the response
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-DSL_DEV_MeiError_t
-DSL_BSP_SendCMV (DSL_DEV_Device_t * pDev, u16 * request, int reply, u16 * response) // write cmv to arc, if reply needed, wait for reply
-{
- DSL_DEV_MeiError_t meierror;
-#if defined(BSP_PORT_RTEMS)
- int delay_counter = 0;
-#endif
-
- if (MEI_MUTEX_LOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema))
- return -ERESTARTSYS;
-
- DSL_DEV_PRIVATE(pDev)->cmv_reply = reply;
- memset (DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, 0,
- sizeof (DSL_DEV_PRIVATE(pDev)->
- CMV_RxMsg));
- DSL_DEV_PRIVATE(pDev)->arcmsgav = 0;
-
- meierror = IFX_MEI_MailboxWrite (pDev, request, MSG_LENGTH);
-
- if (meierror != DSL_DEV_MEI_ERR_SUCCESS) {
- DSL_DEV_PRIVATE(pDev)->cmv_waiting = 0;
- DSL_DEV_PRIVATE(pDev)->arcmsgav = 0;
- IFX_MEI_EMSG ("MailboxWrite Fail!\n");
- IFX_MEI_EMSG ("Resetting ARC...\n");
- IFX_MEI_ResetARC(pDev);
- MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);
- return meierror;
- }
- else {
- DSL_DEV_PRIVATE(pDev)->cmv_count++;
- }
-
- if (DSL_DEV_PRIVATE(pDev)->cmv_reply ==
- NO_REPLY) {
- MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);
- return DSL_DEV_MEI_ERR_SUCCESS;
- }
-
-#if !defined(BSP_PORT_RTEMS)
- if (DSL_DEV_PRIVATE(pDev)->arcmsgav == 0)
- MEI_WAIT_EVENT_TIMEOUT (DSL_DEV_PRIVATE(pDev)->wait_queue_arcmsgav, CMV_TIMEOUT);
-#else
- while (DSL_DEV_PRIVATE(pDev)->arcmsgav == 0 && delay_counter < CMV_TIMEOUT / 5) {
- MEI_WAIT (5);
- delay_counter++;
- }
-#endif
-
- DSL_DEV_PRIVATE(pDev)->cmv_waiting = 0;
- if (DSL_DEV_PRIVATE(pDev)->arcmsgav == 0) { //CMV_timeout
- DSL_DEV_PRIVATE(pDev)->arcmsgav = 0;
- IFX_MEI_EMSG ("\%s: DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT\n",
- __FUNCTION__);
- MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);
- return DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT;
- }
- else {
- DSL_DEV_PRIVATE(pDev)->arcmsgav = 0;
- DSL_DEV_PRIVATE(pDev)->
- reply_count++;
- memcpy (response, DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, MSG_LENGTH * 2);
- MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);
- return DSL_DEV_MEI_ERR_SUCCESS;
- }
- MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);
- return DSL_DEV_MEI_ERR_SUCCESS;
-}
-
-/**
- * Reset the ARC, download boot codes, and run the ARC.
- * This function resets the ARC, downloads boot codes to ARC, and runs the ARC.
- *
- * \param pDev the device pointer
- * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
- * \ingroup Internal
- */
-static DSL_DEV_MeiError_t
-IFX_MEI_RunAdslModem (DSL_DEV_Device_t *pDev)
-{
- int nSize = 0, idx = 0;
- uint32_t im0_register, im2_register;
-// DSL_DEV_WinHost_Message_t m;
-
- if (mei_arc_swap_buff == NULL) {
- mei_arc_swap_buff =
- (u32 *) kmalloc (MAXSWAPSIZE * 4, GFP_KERNEL);
- if (mei_arc_swap_buff == NULL) {
- IFX_MEI_EMSG (">>> malloc fail for codeswap buff!!! <<<\n");
- return DSL_DEV_MEI_ERR_FAILURE;
- }
- printk("allocate %dKB swap buff memory at: 0x%p\n", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff);
- }
-
- DSL_DEV_PRIVATE(pDev)->img_hdr =
- (ARC_IMG_HDR *) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[0].address;
- if ((DSL_DEV_PRIVATE(pDev)->img_hdr->
- count) * sizeof (ARC_SWP_PAGE_HDR) > SDRAM_SEGMENT_SIZE) {
- IFX_MEI_EMSG ("firmware header size is bigger than 64K segment size\n");
- return DSL_DEV_MEI_ERR_FAILURE;
- }
- // check image size
- for (idx = 0; idx < MAX_BAR_REGISTERS; idx++) {
- nSize += DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].nCopy;
- }
- if (nSize !=
- DSL_DEV_PRIVATE(pDev)->image_size) {
- IFX_MEI_EMSG ("Firmware download is not completed. Please download firmware again!\n");
- return DSL_DEV_MEI_ERR_FAILURE;
- }
- // TODO: check crc
- ///
-
- IFX_MEI_ResetARC (pDev);
- IFX_MEI_HaltArc (pDev);
- IFX_MEI_BarUpdate (pDev, DSL_DEV_PRIVATE(pDev)->nBar);
-
- //IFX_MEI_DMSG("Starting to meiDownloadBootCode\n");
-
- IFX_MEI_DownloadBootCode (pDev);
-
- im0_register = (*IFXMIPS_ICU_IM0_IER) & (1 << 20);
- im2_register = (*IFXMIPS_ICU_IM2_IER) & (1 << 20);
- /* Turn off irq */
- #ifdef CONFIG_IFXMIPS_AMAZON_SE
- disable_irq (IFXMIPS_USB_OC_INT0);
- disable_irq (IFXMIPS_USB_OC_INT2);
- #elif defined(CONFIG_IFXMIPS_AR9)
- disable_irq (IFXMIPS_USB_OC_INT0);
- disable_irq (IFXMIPS_USB_OC_INT2);
- #elif defined(CONFIG_IFXMIPS_DANUBE)
- disable_irq (IFXMIPS_USB_OC_INT);
- #endif
- disable_irq (pDev->nIrq[IFX_DYING_GASP]);
-
- IFX_MEI_RunArc (pDev);
-
- MEI_WAIT_EVENT_TIMEOUT (DSL_DEV_PRIVATE(pDev)->wait_queue_modemready, 1000);
-
- #ifdef CONFIG_IFXMIPS_AMAZON_SE
- MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT0);
- MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT2);
- #elif defined(CONFIG_IFXMIPS_AMAZON_S)
- MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT0);
- MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT2);
- #elif defined(CONFIG_IFXMIPS_DANUBE)
- MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT);
- #endif
- MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DYING_GASP]);
-
- /* Re-enable irq */
- enable_irq(pDev->nIrq[IFX_DYING_GASP]);
- *IFXMIPS_ICU_IM0_IER |= im0_register;
- *IFXMIPS_ICU_IM2_IER |= im2_register;
-
- if (DSL_DEV_PRIVATE(pDev)->modem_ready != 1) {
- IFX_MEI_EMSG ("Modem failed to be ready!\n");
- return DSL_DEV_MEI_ERR_FAILURE;
- } else {
- IFX_MEI_DMSG("Modem is ready.\n");
- return DSL_DEV_MEI_ERR_SUCCESS;
- }
-}
-
-/**
- * Get the page's data pointer
- * This function caculats the data address from the firmware header.
- *
- * \param pDev the device pointer
- * \param Page The page number.
- * \param data Data page or program page.
- * \param MaxSize The maximum size to read.
- * \param Buffer Pointer to data.
- * \param Dest Pointer to the destination address.
- * \return The number of bytes to read.
- * \ingroup Internal
- */
-static int
-IFX_MEI_GetPage (DSL_DEV_Device_t * pDev, u32 Page, u32 data,
- u32 MaxSize, u32 * Buffer, u32 * Dest)
-{
- u32 size;
- u32 i;
- u32 *p;
- u32 idx, offset, nBar = 0;
-
- if (Page > DSL_DEV_PRIVATE(pDev)->img_hdr->count)
- return -2;
- /*
- ** Get program or data size, depending on "data" flag
- */
- size = (data == GET_DATA) ? (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].d_size) :
- (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].p_size);
- size &= BOOT_FLAG_MASK; // Clear boot bit!
- if (size > MaxSize)
- return -1;
-
- if (size == 0)
- return 0;
- /*
- ** Get program or data offset, depending on "data" flag
- */
- i = data ? (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].d_offset) :
- (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].p_offset);
-
- /*
- ** Copy data/program to buffer
- */
-
- idx = i / SDRAM_SEGMENT_SIZE;
- offset = i % SDRAM_SEGMENT_SIZE;
- p = (u32 *) ((u8 *) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address + offset);
-
- for (i = 0; i < size; i++) {
- if (offset + i * 4 - (nBar * SDRAM_SEGMENT_SIZE) >= SDRAM_SEGMENT_SIZE) {
- idx++;
- nBar++;
- p = (u32 *) ((u8 *) KSEG1ADDR ((u32)DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address));
- }
- Buffer[i] = *p++;
- }
-
- /*
- ** Pass back data/program destination address
- */
- *Dest = data ? (DSL_DEV_PRIVATE(pDev)-> img_hdr->page[Page].d_dest) :
- (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].p_dest);
-
- return size;
-}
-
-/**
- * Free the memory for ARC firmware
- *
- * \param pDev the device pointer
- * \param type Free all memory or free the unused memory after showtime
- * \ingroup Internal
- */
-const char *free_str[4] = {"Invalid", "Free_Reload", "Free_Showtime", "Free_All"};
-static int
-IFX_MEI_DFEMemoryFree (DSL_DEV_Device_t * pDev, int type)
-{
- int idx = 0;
- smmu_mem_info_t *adsl_mem_info =
- DSL_DEV_PRIVATE(pDev)->adsl_mem_info;
-
- for (idx = 0; idx < MAX_BAR_REGISTERS; idx++) {
- if (type == FREE_ALL ||adsl_mem_info[idx].type == type) {
- if (adsl_mem_info[idx].size > 0) {
- IFX_MEI_DMSG ("Freeing memory %p (%s)\n", adsl_mem_info[idx].org_address, free_str[adsl_mem_info[idx].type]);
- if ( idx == XDATA_REGISTER ) {
- g_xdata_addr = NULL;
- if ( ifx_mei_atm_showtime_exit )
- ifx_mei_atm_showtime_exit();
- }
- kfree (adsl_mem_info[idx].org_address);
- adsl_mem_info[idx].org_address = 0;
- adsl_mem_info[idx].address = 0;
- adsl_mem_info[idx].size = 0;
- adsl_mem_info[idx].type = 0;
- adsl_mem_info[idx].nCopy = 0;
- }
- }
- }
-
- if(mei_arc_swap_buff != NULL){
- printk("free %dKB swap buff memory at: 0x%p\n", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff);
- kfree(mei_arc_swap_buff);
- mei_arc_swap_buff=NULL;
- }
-
- return 0;
-}
-static int
-IFX_MEI_DFEMemoryAlloc (DSL_DEV_Device_t * pDev, long size)
-{
- unsigned long mem_ptr;
- char *org_mem_ptr = NULL;
- int idx = 0;
- long total_size = 0;
- int err = 0;
- smmu_mem_info_t *adsl_mem_info =
- ((ifx_mei_device_private_t *) pDev->pPriv)->adsl_mem_info;
-// DSL_DEV_PRIVATE(pDev)->adsl_mem_info;
- int allocate_size = SDRAM_SEGMENT_SIZE;
-
- printk(KERN_INFO "[%s %d]: image_size = %ld\n", __func__, __LINE__, size);
- // Alloc Swap Pages
- for (idx = 0; size > 0 && idx < MAX_BAR_REGISTERS; idx++) {
- // skip bar15 for XDATA usage.
-#ifndef CONFIG_IFXMIPS_MEI_FW_LOOPBACK
- if (idx == XDATA_REGISTER)
- continue;
-#endif
-#if 0
- if (size < SDRAM_SEGMENT_SIZE) {
- allocate_size = size;
- if (allocate_size < 1024)
- allocate_size = 1024;
- }
-#endif
- if (idx == (MAX_BAR_REGISTERS - 1))
- allocate_size = size;
- else
- allocate_size = SDRAM_SEGMENT_SIZE;
- org_mem_ptr = kmalloc (allocate_size + 1024, GFP_KERNEL);
- if (org_mem_ptr == NULL) {
- IFX_MEI_EMSG ("%d: kmalloc %d bytes memory fail!\n", idx, allocate_size);
- err = -ENOMEM;
- goto allocate_error;
- }
- mem_ptr = (unsigned long) (org_mem_ptr + 1023) & ~(1024 -1);
- adsl_mem_info[idx].address = (char *) mem_ptr;
- adsl_mem_info[idx].org_address = org_mem_ptr;
- adsl_mem_info[idx].size = allocate_size;
- size -= allocate_size;
- total_size += allocate_size;
- }
- if (size > 0) {
- IFX_MEI_EMSG ("Image size is too large!\n");
- err = -EFBIG;
- goto allocate_error;
- }
- err = idx;
- return err;
-
- allocate_error:
- IFX_MEI_DFEMemoryFree (pDev, FREE_ALL);
- return err;
-}
-
-/**
- * Program the BAR registers
- *
- * \param pDev the device pointer
- * \param nTotalBar The number of bar to program.
- * \ingroup Internal
- */
-static int
-IFX_MEI_BarUpdate (DSL_DEV_Device_t * pDev, int nTotalBar)
-{
- int idx = 0;
- smmu_mem_info_t *adsl_mem_info =
- DSL_DEV_PRIVATE(pDev)->adsl_mem_info;
-
- for (idx = 0; idx < nTotalBar; idx++) {
- //skip XDATA register
- if (idx == XDATA_REGISTER)
- continue;
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XMEM_BAR_BASE + idx * 4,
- (((uint32_t) adsl_mem_info[idx].address) & 0x0FFFFFFF));
- }
- for (idx = nTotalBar; idx < MAX_BAR_REGISTERS; idx++) {
- if (idx == XDATA_REGISTER)
- continue;
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XMEM_BAR_BASE + idx * 4,
- (((uint32_t)adsl_mem_info[nTotalBar - 1].address) & 0x0FFFFFFF));
- /* These are for /proc/danube_mei/meminfo purpose */
- adsl_mem_info[idx].address = adsl_mem_info[nTotalBar - 1].address;
- adsl_mem_info[idx].org_address = adsl_mem_info[nTotalBar - 1].org_address;
- adsl_mem_info[idx].size = 0; /* Prevent it from being freed */
- }
-
- g_xdata_addr = adsl_mem_info[XDATA_REGISTER].address;
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XMEM_BAR_BASE + XDATA_REGISTER * 4,
- (((uint32_t) adsl_mem_info [XDATA_REGISTER].address) & 0x0FFFFFFF));
- // update MEI_XDATA_BASE_SH
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XDATA_BASE_SH,
- ((unsigned long)adsl_mem_info[XDATA_REGISTER].address) & 0x0FFFFFFF);
-
- return DSL_DEV_MEI_ERR_SUCCESS;
-}
-
-/* This copies the firmware from secondary storage to 64k memory segment in SDRAM */
-DSL_DEV_MeiError_t
-DSL_BSP_FWDownload (DSL_DEV_Device_t * pDev, const char *buf,
- unsigned long size, long *loff, long *current_offset)
-{
- ARC_IMG_HDR img_hdr_tmp;
- smmu_mem_info_t *adsl_mem_info = DSL_DEV_PRIVATE(pDev)->adsl_mem_info;
-
- size_t nRead = 0, nCopy = 0;
- char *mem_ptr;
- ssize_t retval = -ENOMEM;
- int idx = 0;
-
- printk("\n%s\n", __func__);
-
- if (*loff == 0) {
- if (size < sizeof (img_hdr_tmp)) {
- IFX_MEI_EMSG ("Firmware size is too small!\n");
- return retval;
- }
- copy_from_user ((char *) &img_hdr_tmp, buf, sizeof (img_hdr_tmp));
- // header of image_size and crc are not included.
- DSL_DEV_PRIVATE(pDev)->image_size = le32_to_cpu (img_hdr_tmp.size) + 8;
-
- if (DSL_DEV_PRIVATE(pDev)->image_size > 1024 * 1024) {
- IFX_MEI_EMSG ("Firmware size is too large!\n");
- return retval;
- }
- // check if arc is halt
- IFX_MEI_ResetARC (pDev);
- IFX_MEI_HaltArc (pDev);
-
- IFX_MEI_DFEMemoryFree (pDev, FREE_ALL); //free all
-
- retval = IFX_MEI_DFEMemoryAlloc (pDev, DSL_DEV_PRIVATE(pDev)->image_size);
- if (retval < 0) {
- IFX_MEI_EMSG ("Error: No memory space left.\n");
- goto error;
- }
- for (idx = 0; idx < retval; idx++) {
- //skip XDATA register
- if (idx == XDATA_REGISTER)
- continue;
- if (idx * SDRAM_SEGMENT_SIZE < le32_to_cpu (img_hdr_tmp.page[0].p_offset))
- adsl_mem_info[idx].type = FREE_RELOAD;
- else
- adsl_mem_info[idx].type = FREE_SHOWTIME;
- }
- DSL_DEV_PRIVATE(pDev)->nBar = retval;
-
- DSL_DEV_PRIVATE(pDev)->img_hdr =
- (ARC_IMG_HDR *) adsl_mem_info[0].address;
-
- adsl_mem_info[XDATA_REGISTER].org_address = kmalloc (SDRAM_SEGMENT_SIZE + 1024, GFP_KERNEL);
- adsl_mem_info[XDATA_REGISTER].address =
- (char *) ((unsigned long) (adsl_mem_info[XDATA_REGISTER].org_address + 1023) & 0xFFFFFC00);
-
- adsl_mem_info[XDATA_REGISTER].size = SDRAM_SEGMENT_SIZE;
-
- if (adsl_mem_info[XDATA_REGISTER].address == NULL) {
- IFX_MEI_EMSG ("kmalloc memory fail!\n");
- retval = -ENOMEM;
- goto error;
- }
- adsl_mem_info[XDATA_REGISTER].type = FREE_RELOAD;
- printk(KERN_INFO "[%s %d] -> IFX_MEI_BarUpdate()\n", __func__, __LINE__);
- IFX_MEI_BarUpdate (pDev, (DSL_DEV_PRIVATE(pDev)->nBar));
- }
- else if (DSL_DEV_PRIVATE(pDev)-> image_size == 0) {
- IFX_MEI_EMSG ("Error: Firmware size=0! \n");
- goto error;
- }
-
- nRead = 0;
- while (nRead < size) {
- long offset = ((long) (*loff) + nRead) % SDRAM_SEGMENT_SIZE;
- idx = (((long) (*loff)) + nRead) / SDRAM_SEGMENT_SIZE;
- mem_ptr = (char *) KSEG1ADDR ((unsigned long) (adsl_mem_info[idx].address) + offset);
- if ((size - nRead + offset) > SDRAM_SEGMENT_SIZE)
- nCopy = SDRAM_SEGMENT_SIZE - offset;
- else
- nCopy = size - nRead;
- copy_from_user (mem_ptr, buf + nRead, nCopy);
- for (offset = 0; offset < (nCopy / 4); offset++) {
- ((unsigned long *) mem_ptr)[offset] = le32_to_cpu (((unsigned long *) mem_ptr)[offset]);
- }
- nRead += nCopy;
- adsl_mem_info[idx].nCopy += nCopy;
- }
-
- *loff += size;
- *current_offset = size;
- return DSL_DEV_MEI_ERR_SUCCESS;
-error:
- IFX_MEI_DFEMemoryFree (pDev, FREE_ALL);
- return DSL_DEV_MEI_ERR_FAILURE;
-}
-/*
- * Register a callback event.
- * Return:
- * -1 if the event already has a callback function registered.
- * 0 success
- */
-int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *p)
-{
- if (!p) {
- IFX_MEI_EMSG("Invalid parameter!\n");
- return -EINVAL;
- }
- if (p->event > DSL_BSP_CB_LAST || p->event < DSL_BSP_CB_FIRST) {
- IFX_MEI_EMSG("Invalid Event %d\n", p->event);
- return -EINVAL;
- }
- if (dsl_bsp_event_callback[p->event].function) {
- IFX_MEI_EMSG("Event %d already has a callback function registered!\n", p->event);
- return -1;
- } else {
- dsl_bsp_event_callback[p->event].function = p->function;
- dsl_bsp_event_callback[p->event].event = p->event;
- dsl_bsp_event_callback[p->event].pData = p->pData;
- }
- return 0;
-}
-int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *p)
-{
- if (!p) {
- IFX_MEI_EMSG("Invalid parameter!\n");
- return -EINVAL;
- }
- if (p->event > DSL_BSP_CB_LAST || p->event < DSL_BSP_CB_FIRST) {
- IFX_MEI_EMSG("Invalid Event %d\n", p->event);
- return -EINVAL;
- }
- if (dsl_bsp_event_callback[p->event].function) {
- IFX_MEI_EMSG("Unregistering Event %d...\n", p->event);
- dsl_bsp_event_callback[p->event].function = NULL;
- dsl_bsp_event_callback[p->event].pData = NULL;
- } else {
- IFX_MEI_EMSG("Event %d is not registered!\n", p->event);
- return -1;
- }
- return 0;
-}
-
-/**
- * MEI Dying Gasp interrupt handler
- *
- * \param int1
- * \param void0
- * \param regs Pointer to the structure of danube mips registers
- * \ingroup Internal
- */
-static irqreturn_t IFX_MEI_Dying_Gasp_IrqHandle (int int1, void *void0)
-{
- DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) void0;
- DSL_BSP_CB_Type_t event;
-
- if (pDev == NULL)
- IFX_MEI_EMSG("Error: Got Interrupt but pDev is NULL!!!!\n");
-
-#ifndef CONFIG_SMP
- disable_irq (pDev->nIrq[IFX_DYING_GASP]);
-#else
- disable_irq_nosync(pDev->nIrq[IFX_DYING_GASP]);
-#endif
- event = DSL_BSP_CB_DYING_GASP;
-
- if (dsl_bsp_event_callback[event].function)
- (*dsl_bsp_event_callback[event].function)(pDev, event, dsl_bsp_event_callback[event].pData);
-
-#ifdef CONFIG_USE_EMULATOR
- IFX_MEI_EMSG("Dying Gasp! Shutting Down... (Work around for Amazon-S Venus emulator)\n");
-#else
- IFX_MEI_EMSG("Dying Gasp! Shutting Down...\n");
-// kill_proc (1, SIGINT, 1); /* Ask init to reboot us */
-#endif
- return IRQ_HANDLED;
-}
-
-extern void ifx_usb_enable_afe_oc(void);
-
-/**
- * MEI interrupt handler
- *
- * \param int1
- * \param void0
- * \param regs Pointer to the structure of danube mips registers
- * \ingroup Internal
- */
-static irqreturn_t IFX_MEI_IrqHandle (int int1, void *void0)
-{
- u32 scratch;
- DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) void0;
-#if defined(CONFIG_IFXMIPS_MEI_FW_LOOPBACK) && defined(DFE_PING_TEST)
- dfe_loopback_irq_handler (pDev);
- return IRQ_HANDLED;
-#endif //CONFIG_AMAZON_S_MEI_FW_LOOPBACK
- DSL_BSP_CB_Type_t event;
-
- if (pDev == NULL)
- IFX_MEI_EMSG("Error: Got Interrupt but pDev is NULL!!!!\n");
-
- IFX_MEI_DebugRead (pDev, ARC_MEI_MAILBOXR, &scratch, 1);
- if (scratch & OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK) {
- IFX_MEI_EMSG("Receive Code Swap Request interrupt!!!\n");
- return IRQ_HANDLED;
- }
- else if (scratch & OMB_CLEAREOC_INTERRUPT_CODE) {
- // clear eoc message interrupt
- IFX_MEI_DMSG("OMB_CLEAREOC_INTERRUPT_CODE\n");
- event = DSL_BSP_CB_CEOC_IRQ;
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_MSGAV);
- if (dsl_bsp_event_callback[event].function)
- (*dsl_bsp_event_callback[event].function)(pDev, event, dsl_bsp_event_callback[event].pData);
- } else if (scratch & OMB_REBOOT_INTERRUPT_CODE) {
- // Reboot
- IFX_MEI_DMSG("OMB_REBOOT_INTERRUPT_CODE\n");
- event = DSL_BSP_CB_FIRMWARE_REBOOT;
-
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_MSGAV);
-
- if (dsl_bsp_event_callback[event].function)
- (*dsl_bsp_event_callback[event].function)(pDev, event, dsl_bsp_event_callback[event].pData);
- } else { // normal message
- IFX_MEI_MailboxRead (pDev, DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, MSG_LENGTH);
- if (DSL_DEV_PRIVATE(pDev)-> cmv_waiting == 1) {
- DSL_DEV_PRIVATE(pDev)-> arcmsgav = 1;
- DSL_DEV_PRIVATE(pDev)-> cmv_waiting = 0;
-#if !defined(BSP_PORT_RTEMS)
- MEI_WAKEUP_EVENT (DSL_DEV_PRIVATE(pDev)->wait_queue_arcmsgav);
-#endif
- }
- else {
- DSL_DEV_PRIVATE(pDev)-> modem_ready_cnt++;
- memcpy ((char *) DSL_DEV_PRIVATE(pDev)->Recent_indicator,
- (char *) DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, MSG_LENGTH * 2);
- if (((DSL_DEV_PRIVATE(pDev)->CMV_RxMsg[0] & 0xff0) >> 4) == D2H_AUTONOMOUS_MODEM_READY_MSG) {
- //check ARC ready message
- IFX_MEI_DMSG ("Got MODEM_READY_MSG\n");
- DSL_DEV_PRIVATE(pDev)->modem_ready = 1;
- MEI_WAKEUP_EVENT (DSL_DEV_PRIVATE(pDev)->wait_queue_modemready);
- }
- }
- }
-
- return IRQ_HANDLED;
-}
-
-int
-DSL_BSP_ATMLedCBRegister (int (*ifx_adsl_ledcallback) (void))
-{
- g_adsl_ledcallback = ifx_adsl_ledcallback;
- return 0;
-}
-
-int
-DSL_BSP_ATMLedCBUnregister (int (*ifx_adsl_ledcallback) (void))
-{
- g_adsl_ledcallback = adsl_dummy_ledcallback;
- return 0;
-}
-
-#if 0
-int
-DSL_BSP_EventCBRegister (int (*ifx_adsl_callback)
- (DSL_BSP_CB_Event_t * param))
-{
- int error = 0;
-
- if (DSL_EventCB == NULL) {
- DSL_EventCB = ifx_adsl_callback;
- }
- else {
- error = -EIO;
- }
- return error;
-}
-
-int
-DSL_BSP_EventCBUnregister (int (*ifx_adsl_callback)
- (DSL_BSP_CB_Event_t * param))
-{
- int error = 0;
-
- if (DSL_EventCB == ifx_adsl_callback) {
- DSL_EventCB = NULL;
- }
- else {
- error = -EIO;
- }
- return error;
-}
-
-static int
-DSL_BSP_GetEventCB (int (**ifx_adsl_callback)
- (DSL_BSP_CB_Event_t * param))
-{
- *ifx_adsl_callback = DSL_EventCB;
- return 0;
-}
-#endif
-
-#ifdef CONFIG_IFXMIPS_MEI_FW_LOOPBACK
-#define mte_reg_base (0x4800*4+0x20000)
-
-/* Iridia Registers Address Constants */
-#define MTE_Reg(r) (int)(mte_reg_base + (r*4))
-
-#define IT_AMODE MTE_Reg(0x0004)
-
-#define TIMER_DELAY (1024)
-#define BC0_BYTES (32)
-#define BC1_BYTES (30)
-#define NUM_MB (12)
-#define TIMEOUT_VALUE 2000
-
-static void
-BFMWait (u32 cycle)
-{
- u32 i;
- for (i = 0; i < cycle; i++);
-}
-
-static void
-WriteRegLong (u32 addr, u32 data)
-{
- //*((volatile u32 *)(addr)) = data;
- IFX_MEI_WRITE_REGISTER_L (data, addr);
-}
-
-static u32
-ReadRegLong (u32 addr)
-{
- // u32 rd_val;
- //rd_val = *((volatile u32 *)(addr));
- // return rd_val;
- return IFX_MEI_READ_REGISTER_L (addr);
-}
-
-/* This routine writes the mailbox with the data in an input array */
-static void
-WriteMbox (u32 * mboxarray, u32 size)
-{
- IFX_MEI_DebugWrite (&dsl_devices[0], IMBOX_BASE, mboxarray, size);
- printk ("write to %X\n", IMBOX_BASE);
- IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ME2ARC_INT, MEI_TO_ARC_MSGAV);
-}
-
-/* This routine reads the output mailbox and places the results into an array */
-static void
-ReadMbox (u32 * mboxarray, u32 size)
-{
- IFX_MEI_DebugRead (&dsl_devices[0], OMBOX_BASE, mboxarray, size);
- printk ("read from %X\n", OMBOX_BASE);
-}
-
-static void
-MEIWriteARCValue (u32 address, u32 value)
-{
- u32 i, check = 0;
-
- /* Write address register */
- IFX_MEI_WRITE_REGISTER_L (address, ME_DBG_WR_AD + IFXMIPS_MEI_BASE_ADDR);
-
- /* Write data register */
- IFX_MEI_WRITE_REGISTER_L (value, ME_DBG_DATA + IFXMIPS_MEI_BASE_ADDR);
-
- /* wait until complete - timeout at 40 */
- for (i = 0; i < 40; i++) {
- check = IFX_MEI_READ_REGISTER_L (ME_ARC2ME_STAT + IFXMIPS_MEI_BASE_ADDR);
-
- if ((check & ARC_TO_MEI_DBG_DONE))
- break;
- }
- /* clear the flag */
- IFX_MEI_WRITE_REGISTER_L (ARC_TO_MEI_DBG_DONE, ME_ARC2ME_STAT + IFXMIPS_MEI_BASE_ADDR);
-}
-
-void
-arc_code_page_download (uint32_t arc_code_length, uint32_t * start_address)
-{
- int count;
-
- printk ("try to download pages,size=%d\n", arc_code_length);
- IFX_MEI_ControlModeSet (&dsl_devices[0], MEI_MASTER_MODE);
- IFX_MEI_HaltArc (&dsl_devices[0]);
- IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_DX_AD, 0);
- for (count = 0; count < arc_code_length; count++) {
- IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_DX_DATA,
- *(start_address + count));
- }
- IFX_MEI_ControlModeSet (&dsl_devices[0], JTAG_MASTER_MODE);
-}
-static int
-load_jump_table (unsigned long addr)
-{
- int i;
- uint32_t addr_le, addr_be;
- uint32_t jump_table[32];
-
- for (i = 0; i < 16; i++) {
- addr_le = i * 8 + addr;
- addr_be = ((addr_le >> 16) & 0xffff);
- addr_be |= ((addr_le & 0xffff) << 16);
- jump_table[i * 2 + 0] = 0x0f802020;
- jump_table[i * 2 + 1] = addr_be;
- //printk("jt %X %08X %08X\n",i,jump_table[i*2+0],jump_table[i*2+1]);
- }
- arc_code_page_download (32, &jump_table[0]);
-return 0;
-}
-
-int got_int = 0;
-
-void
-dfe_loopback_irq_handler (DSL_DEV_Device_t *pDev)
-{
- uint32_t rd_mbox[10];
-
- memset (&rd_mbox[0], 0, 10 * 4);
- ReadMbox (&rd_mbox[0], 6);
- if (rd_mbox[0] == 0x0) {
- printk ("Get ARC_ACK\n");
- got_int = 1;
- }
- else if (rd_mbox[0] == 0x5) {
- printk ("Get ARC_BUSY\n");
- got_int = 2;
- }
- else if (rd_mbox[0] == 0x3) {
- printk ("Get ARC_EDONE\n");
- if (rd_mbox[1] == 0x0) {
- got_int = 3;
- printk ("Get E_MEMTEST\n");
- if (rd_mbox[2] != 0x1) {
- got_int = 4;
- printk ("Get Result %X\n", rd_mbox[2]);
- }
- }
- }
- IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ARC2ME_STAT,
- ARC_TO_MEI_DBG_DONE);
- MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DFEIR]);
- disable_irq (pDev->nIrq[IFX_DFEIR]);
- //got_int = 1;
- return;
-}
-
-static void
-wait_mem_test_result (void)
-{
- uint32_t mbox[5];
- mbox[0] = 0;
-
- printk ("Waiting Starting\n");
- while (mbox[0] == 0) {
- ReadMbox (&mbox[0], 5);
- }
- printk ("Try to get mem test result.\n");
- ReadMbox (&mbox[0], 5);
- if (mbox[0] == 0xA) {
- printk ("Success.\n");
- }
- else if (mbox[0] == 0xA) {
- printk ("Fail,address %X,except data %X,receive data %X\n",
- mbox[1], mbox[2], mbox[3]);
- }
- else {
- printk ("Fail\n");
- }
-}
-
-static int
-arc_ping_testing (DSL_DEV_Device_t *pDev)
-{
-#define MEI_PING 0x00000001
- uint32_t wr_mbox[10], rd_mbox[10];
- int i;
-
- for (i = 0; i < 10; i++) {
- wr_mbox[i] = 0;
- rd_mbox[i] = 0;
- }
-
- printk ("send ping msg\n");
- wr_mbox[0] = MEI_PING;
- WriteMbox (&wr_mbox[0], 10);
-
- while (got_int == 0) {
- MEI_WAIT (100);
- }
-
- printk ("send start event\n");
- got_int = 0;
-
- wr_mbox[0] = 0x4;
- wr_mbox[1] = 0;
- wr_mbox[2] = 0;
- wr_mbox[3] = (uint32_t) 0xf5acc307e;
- wr_mbox[4] = 5;
- wr_mbox[5] = 2;
- wr_mbox[6] = 0x1c000;
- wr_mbox[7] = 64;
- wr_mbox[8] = 0;
- wr_mbox[9] = 0;
- WriteMbox (&wr_mbox[0], 10);
- DSL_ENABLE_IRQ (pDev->nIrq[IFX_DFEIR]);
- //printk("IFX_MEI_MailboxWrite ret=%d\n",i);
- IFX_MEI_LongWordWriteOffset (&dsl_devices[0],
- (u32) ME_ME2ARC_INT,
- MEI_TO_ARC_MSGAV);
- printk ("sleeping\n");
- while (1) {
- if (got_int > 0) {
-
- if (got_int > 3)
- printk ("got_int >>>> 3\n");
- else
- printk ("got int = %d\n", got_int);
- got_int = 0;
- //schedule();
- DSL_ENABLE_IRQ (pDev->nIrq[IFX_DFEIR]);
- }
- //mbox_read(&rd_mbox[0],6);
- MEI_WAIT (100);
- }
- return 0;
-}
-
-static DSL_DEV_MeiError_t
-DFE_Loopback_Test (void)
-{
- int i = 0;
- u32 arc_debug_data = 0, temp;
- DSL_DEV_Device_t *pDev = &dsl_devices[0];
- uint32_t wr_mbox[10];
-
- IFX_MEI_ResetARC (pDev);
- // start the clock
- arc_debug_data = ACL_CLK_MODE_ENABLE;
- IFX_MEI_DebugWrite (pDev, CRI_CCR0, &arc_debug_data, 1);
-
-#if defined( DFE_PING_TEST )|| defined( DFE_ATM_LOOPBACK)
- // WriteARCreg(AUX_XMEM_LTEST,0);
- IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
-#define AUX_XMEM_LTEST 0x128
- _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK, AUX_XMEM_LTEST, 0);
- IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
-
- // WriteARCreg(AUX_XDMA_GAP,0);
- IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
-#define AUX_XDMA_GAP 0x114
- _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK, AUX_XDMA_GAP, 0);
- IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
-
- IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
- temp = 0;
- _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,
- (u32) ME_XDATA_BASE_SH + IFXMIPS_MEI_BASE_ADDR, temp);
- IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
-
- i = IFX_MEI_DFEMemoryAlloc (pDev, SDRAM_SEGMENT_SIZE * 16);
- if (i >= 0) {
- int idx;
-
- for (idx = 0; idx < i; idx++) {
- DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].type = FREE_RELOAD;
- IFX_MEI_WRITE_REGISTER_L ((((uint32_t) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address) & 0x0fffffff),
- IFXMIPS_MEI_BASE_ADDR + ME_XMEM_BAR_BASE + idx * 4);
- printk ("bar%d(%X)=%X\n", idx,
- IFXMIPS_MEI_BASE_ADDR + ME_XMEM_BAR_BASE +
- idx * 4, (((uint32_t)
- ((ifx_mei_device_private_t *)
- pDev->pPriv)->adsl_mem_info[idx].
- address) & 0x0fffffff));
- memset ((u8 *) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address, 0, SDRAM_SEGMENT_SIZE);
- }
-
- IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XDATA_BASE_SH,
- ((unsigned long) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[XDATA_REGISTER].address) & 0x0FFFFFFF);
- }
- else {
- IFX_MEI_EMSG ("cannot load image: no memory\n");
- return DSL_DEV_MEI_ERR_FAILURE;
- }
- //WriteARCreg(AUX_IC_CTRL,2);
- printk(KERN_INFO "[%s %s %d]: Setting MEI_MASTER_MODE..\n", __FILE__, __func__, __LINE__);
- IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
-#define AUX_IC_CTRL 0x11
- _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,
- AUX_IC_CTRL, 2);
- printk(KERN_INFO "[%s %s %d]: Setting JTAG_MASTER_MODE..\n", __FILE__, __func__, __LINE__);
- IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
-
- printk(KERN_INFO "[%s %s %d]: Halting ARC...\n", __FILE__, __func__, __LINE__);
- IFX_MEI_HaltArc (&dsl_devices[0]);
-
-#ifdef DFE_PING_TEST
-
- printk ("ping test image size=%d\n", sizeof (arc_ahb_access_code));
- memcpy ((u8 *) (DSL_DEV_PRIVATE(pDev)->
- adsl_mem_info[0].address + 0x1004),
- &arc_ahb_access_code[0], sizeof (arc_ahb_access_code));
- load_jump_table (0x80000 + 0x1004);
-
-#endif //DFE_PING_TEST
-
- printk ("ARC ping test code download complete\n");
-#endif //defined( DFE_PING_TEST )|| defined( DFE_ATM_LOOPBACK)
-#ifdef DFE_MEM_TEST
- IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ARC2ME_MASK, MSGAV_EN);
-
- arc_code_page_download (1537, &code_array[0]);
- printk ("ARC mem test code download complete\n");
-#endif //DFE_MEM_TEST
-#ifdef DFE_ATM_LOOPBACK
- arc_debug_data = 0xf;
- arc_code_page_download (sizeof(code_array) / sizeof(*code_array), &code_array[0]);
- wr_mbox[0] = 0; //TIMER_DELAY - org: 1024
- wr_mbox[1] = 0; //TXFB_START0
- wr_mbox[2] = 0x7f; //TXFB_END0 - org: 49
- wr_mbox[3] = 0x80; //TXFB_START1 - org: 80
- wr_mbox[4] = 0xff; //TXFB_END1 - org: 109
- wr_mbox[5] = 0x100; //RXFB_START0 - org: 0
- wr_mbox[6] = 0x17f; //RXFB_END0 - org: 49
- wr_mbox[7] = 0x180; //RXFB_START1 - org: 256
- wr_mbox[8] = 0x1ff; //RXFB_END1 - org: 315
- WriteMbox (&wr_mbox[0], 9);
- // Start Iridia IT_AMODE (in dmp access) why is it required?
- IFX_MEI_DebugWrite (&dsl_devices[0], 0x32010, &arc_debug_data, 1);
-#endif //DFE_ATM_LOOPBACK
- IFX_MEI_IRQEnable (pDev);
- printk(KERN_INFO "[%s %s %d]: run ARC...\n", __FILE__, __func__, __LINE__);
- IFX_MEI_RunArc (&dsl_devices[0]);
-
-#ifdef DFE_PING_TEST
- arc_ping_testing (pDev);
-#endif //DFE_PING_TEST
-#ifdef DFE_MEM_TEST
- wait_mem_test_result ();
-#endif //DFE_MEM_TEST
-
- IFX_MEI_DFEMemoryFree (pDev, FREE_ALL);
- return DSL_DEV_MEI_ERR_SUCCESS;
-}
-
-#endif //CONFIG_AMAZON_S_MEI_FW_LOOPBACK
-
-static int
-IFX_MEI_InitDevNode (int num)
-{
- if (num == 0) {
- if ((dev_major = register_chrdev (dev_major, IFX_MEI_DEVNAME, &bsp_mei_operations)) < 0) {
- IFX_MEI_EMSG ("register_chrdev(%d %s) failed!\n", dev_major, IFX_MEI_DEVNAME);
- return -ENODEV;
- }
- }
- return 0;
-}
-
-static int
-IFX_MEI_CleanUpDevNode (int num)
-{
- if (num == 0)
- unregister_chrdev (dev_major, MEI_DIRNAME);
- return 0;
-}
-
-static int
-IFX_MEI_InitDevice (int num)
-{
- DSL_DEV_Device_t *pDev;
- u32 temp;
- pDev = &dsl_devices[num];
- if (pDev == NULL)
- return -ENOMEM;
- pDev->pPriv = &sDanube_Mei_Private[num];
- memset (pDev->pPriv, 0, sizeof (ifx_mei_device_private_t));
-
- memset (&DSL_DEV_PRIVATE(pDev)->
- adsl_mem_info[0], 0,
- sizeof (smmu_mem_info_t) * MAX_BAR_REGISTERS);
-
- if (num == 0) {
- pDev->nIrq[IFX_DFEIR] = IFXMIPS_MEI_INT;
- pDev->nIrq[IFX_DYING_GASP] = IFXMIPS_MEI_DYING_GASP_INT;
- pDev->base_address = IFXMIPS_MEI_BASE_ADDR;
-
- /* Power up MEI */
-#ifdef CONFIG_IFXMIPS_AMAZON_SE
- *IFXMIPS_PMU_PWDCR &= ~(1 << 9); // enable dsl
- *IFXMIPS_PMU_PWDCR &= ~(1 << 15); // enable AHB base
-#else
- temp = ifxmips_r32(IFXMIPS_PMU_PWDCR);
- temp &= 0xffff7dbe;
- ifxmips_w32(temp, IFXMIPS_PMU_PWDCR);
-#endif
- }
- pDev->nInUse = 0;
- DSL_DEV_PRIVATE(pDev)->modem_ready = 0;
- DSL_DEV_PRIVATE(pDev)->arcmsgav = 0;
-
- MEI_INIT_WAKELIST ("arcq", DSL_DEV_PRIVATE(pDev)->wait_queue_arcmsgav); // for ARCMSGAV
- MEI_INIT_WAKELIST ("arcr", DSL_DEV_PRIVATE(pDev)->wait_queue_modemready); // for arc modem ready
-
- MEI_MUTEX_INIT (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema, 1); // semaphore initialization, mutex
-#if 0
- MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DFEIR]);
- MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DYING_GASP]);
-#endif
- if (request_irq (pDev->nIrq[IFX_DFEIR], IFX_MEI_IrqHandle, 0, "DFEIR", pDev) != 0) {
- IFX_MEI_EMSG ("request_irq %d failed!\n", pDev->nIrq[IFX_DFEIR]);
- return -1;
- }
- if (request_irq (pDev->nIrq[IFX_DYING_GASP], IFX_MEI_Dying_Gasp_IrqHandle, 0, "DYING_GASP", pDev) != 0) {
- IFX_MEI_EMSG ("request_irq %d failed!\n", pDev->nIrq[IFX_DYING_GASP]);
- return -1;
- }
-// IFX_MEI_DMSG("Device %d initialized. IER %#x\n", num, bsp_get_irq_ier(pDev->nIrq[IFX_DYING_GASP]));
- return 0;
-}
-
-static int
-IFX_MEI_ExitDevice (int num)
-{
- DSL_DEV_Device_t *pDev;
- pDev = &dsl_devices[num];
-
- if (pDev == NULL)
- return -EIO;
-
- disable_irq (pDev->nIrq[IFX_DFEIR]);
- disable_irq (pDev->nIrq[IFX_DYING_GASP]);
-
- free_irq(pDev->nIrq[IFX_DFEIR], pDev);
- free_irq(pDev->nIrq[IFX_DYING_GASP], pDev);
-
- return 0;
-}
-
-static DSL_DEV_Device_t *
-IFX_BSP_HandleGet (int maj, int num)
-{
- if (num > BSP_MAX_DEVICES)
- return NULL;
- return &dsl_devices[num];
-}
-
-DSL_DEV_Device_t *
-DSL_BSP_DriverHandleGet (int maj, int num)
-{
- DSL_DEV_Device_t *pDev;
-
- if (num > BSP_MAX_DEVICES)
- return NULL;
-
- pDev = &dsl_devices[num];
- if (!try_module_get(pDev->owner))
- return NULL;
-
- pDev->nInUse++;
- return pDev;
-}
-
-int
-DSL_BSP_DriverHandleDelete (DSL_DEV_Device_t * nHandle)
-{
- DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) nHandle;
- if (pDev->nInUse)
- pDev->nInUse--;
- module_put(pDev->owner);
- return 0;
-}
-
-static int
-IFX_MEI_Open (DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil)
-{
- int maj = MAJOR (ino->i_rdev);
- int num = MINOR (ino->i_rdev);
-
- DSL_DEV_Device_t *pDev = NULL;
- if ((pDev = DSL_BSP_DriverHandleGet (maj, num)) == NULL) {
- IFX_MEI_EMSG("open(%d:%d) fail!\n", maj, num);
- return -EIO;
- }
- fil->private_data = pDev;
- return 0;
-}
-
-static int
-IFX_MEI_Release (DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil)
-{
- //int maj = MAJOR(ino->i_rdev);
- int num = MINOR (ino->i_rdev);
- DSL_DEV_Device_t *pDev;
-
- pDev = &dsl_devices[num];
- if (pDev == NULL)
- return -EIO;
- DSL_BSP_DriverHandleDelete (pDev);
- return 0;
-}
-
-/**
- * Callback function for linux userspace program writing
- */
-static ssize_t
-IFX_MEI_Write (DSL_DRV_file_t * filp, const char *buf, size_t size, loff_t * loff)
-{
- DSL_DEV_MeiError_t mei_error = DSL_DEV_MEI_ERR_FAILURE;
- long offset = 0;
- DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) filp->private_data;
-
- if (pDev == NULL)
- return -EIO;
-
- mei_error =
- DSL_BSP_FWDownload (pDev, buf, size, (long *) loff, &offset);
-
- if (mei_error == DSL_DEV_MEI_ERR_FAILURE)
- return -EIO;
- return (ssize_t) offset;
-}
-
-/**
- * Callback function for linux userspace program ioctling
- */
-static int
-IFX_MEI_IoctlCopyFrom (int from_kernel, char *dest, char *from, int size)
-{
- int ret = 0;
-
- if (!from_kernel)
- ret = copy_from_user ((char *) dest, (char *) from, size);
- else
- ret = (int)memcpy ((char *) dest, (char *) from, size);
- return ret;
-}
-
-static int
-IFX_MEI_IoctlCopyTo (int from_kernel, char *dest, char *from, int size)
-{
- int ret = 0;
-
- if (!from_kernel)
- ret = copy_to_user ((char *) dest, (char *) from, size);
- else
- ret = (int)memcpy ((char *) dest, (char *) from, size);
- return ret;
-}
-
-static int
-IFX_MEI_Ioctls (DSL_DEV_Device_t * pDev, int from_kernel, unsigned int command, unsigned long lon)
-{
- int i = 0;
- int meierr = DSL_DEV_MEI_ERR_SUCCESS;
- u32 base_address = IFXMIPS_MEI_BASE_ADDR;
- DSL_DEV_WinHost_Message_t winhost_msg, m;
- DSL_DEV_MeiDebug_t debugrdwr;
- DSL_DEV_MeiReg_t regrdwr;
-
- switch (command) {
-
- case DSL_FIO_BSP_CMV_WINHOST:
- IFX_MEI_IoctlCopyFrom (from_kernel, (char *) winhost_msg.msg.TxMessage,
- (char *) lon, MSG_LENGTH * 2);
-
- if ((meierr = DSL_BSP_SendCMV (pDev, winhost_msg.msg.TxMessage, YES_REPLY,
- winhost_msg.msg.RxMessage)) != DSL_DEV_MEI_ERR_SUCCESS) {
- IFX_MEI_EMSG ("WINHOST CMV fail :TxMessage:%X %X %X %X, RxMessage:%X %X %X %X %X\n",
- winhost_msg.msg.TxMessage[0], winhost_msg.msg.TxMessage[1], winhost_msg.msg.TxMessage[2], winhost_msg.msg.TxMessage[3],
- winhost_msg.msg.RxMessage[0], winhost_msg.msg.RxMessage[1], winhost_msg.msg.RxMessage[2], winhost_msg.msg.RxMessage[3],
- winhost_msg.msg.RxMessage[4]);
- meierr = DSL_DEV_MEI_ERR_FAILURE;
- }
- else {
- IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon,
- (char *) winhost_msg.msg.RxMessage,
- MSG_LENGTH * 2);
- }
- break;
-
- case DSL_FIO_BSP_CMV_READ:
- IFX_MEI_IoctlCopyFrom (from_kernel, (char *) (®rdwr),
- (char *) lon, sizeof (DSL_DEV_MeiReg_t));
-
- IFX_MEI_LongWordRead ((u32) regrdwr.iAddress,
- (u32 *) & (regrdwr.iData));
-
- IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon,
- (char *) (®rdwr),
- sizeof (DSL_DEV_MeiReg_t));
-
- break;
-
- case DSL_FIO_BSP_CMV_WRITE:
- IFX_MEI_IoctlCopyFrom (from_kernel, (char *) (®rdwr),
- (char *) lon, sizeof (DSL_DEV_MeiReg_t));
-
- IFX_MEI_LongWordWrite ((u32) regrdwr.iAddress,
- regrdwr.iData);
- break;
-
- case DSL_FIO_BSP_GET_BASE_ADDRESS:
- IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon,
- (char *) (&base_address),
- sizeof (base_address));
- break;
-
- case DSL_FIO_BSP_IS_MODEM_READY:
- i = IFX_MEI_IsModemReady (pDev);
- IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon,
- (char *) (&i), sizeof (int));
- meierr = DSL_DEV_MEI_ERR_SUCCESS;
- break;
- case DSL_FIO_BSP_RESET:
- case DSL_FIO_BSP_REBOOT:
- meierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_RESET);
- meierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_HALT);
- break;
-
- case DSL_FIO_BSP_HALT:
- meierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_HALT);
- break;
-
- case DSL_FIO_BSP_RUN:
- meierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_RUN);
- break;
- case DSL_FIO_BSP_BOOTDOWNLOAD:
- meierr = IFX_MEI_DownloadBootCode (pDev);
- break;
- case DSL_FIO_BSP_JTAG_ENABLE:
- meierr = IFX_MEI_ArcJtagEnable (pDev, 1);
- break;
-
- case DSL_FIO_BSP_REMOTE:
- IFX_MEI_IoctlCopyFrom (from_kernel, (char *) (&i),
- (char *) lon, sizeof (int));
-
- meierr = IFX_MEI_AdslMailboxIRQEnable (pDev, i);
- break;
-
- case DSL_FIO_BSP_DSL_START:
- printk("\n%s: DSL_FIO_BSP_DSL_START\n",__func__);
- if ((meierr = IFX_MEI_RunAdslModem (pDev)) != DSL_DEV_MEI_ERR_SUCCESS) {
- IFX_MEI_EMSG ("IFX_MEI_RunAdslModem() error...");
- meierr = DSL_DEV_MEI_ERR_FAILURE;
- }
- break;
-
- case DSL_FIO_BSP_DEBUG_READ:
- case DSL_FIO_BSP_DEBUG_WRITE:
- IFX_MEI_IoctlCopyFrom (from_kernel,
- (char *) (&debugrdwr),
- (char *) lon,
- sizeof (debugrdwr));
-
- if (command == DSL_FIO_BSP_DEBUG_READ)
- meierr = DSL_BSP_MemoryDebugAccess (pDev,
- DSL_BSP_MEMORY_READ,
- debugrdwr.
- iAddress,
- debugrdwr.
- buffer,
- debugrdwr.
- iCount);
- else
- meierr = DSL_BSP_MemoryDebugAccess (pDev,
- DSL_BSP_MEMORY_WRITE,
- debugrdwr.
- iAddress,
- debugrdwr.
- buffer,
- debugrdwr.
- iCount);
-
- IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&debugrdwr), sizeof (debugrdwr));
- break;
- case DSL_FIO_BSP_GET_VERSION:
- IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&bsp_mei_version), sizeof (DSL_DEV_Version_t));
- break;
-
- case DSL_FIO_BSP_GET_CHIP_INFO:
- bsp_chip_info.major = 1;
- bsp_chip_info.minor = IFXMIPS_MPS_CHIPID_VERSION_GET(*IFXMIPS_MPS_CHIPID);
- IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&bsp_chip_info), sizeof (DSL_DEV_HwVersion_t));
- meierr = DSL_DEV_MEI_ERR_SUCCESS;
- break;
-
- case DSL_FIO_BSP_FREE_RESOURCE:
- makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_STAT, 4, 0, 1, NULL, m.msg.TxMessage);
- if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS) {
- meierr = DSL_DEV_MEI_ERR_FAILURE;
- return -EIO;
- }
- IFX_MEI_DMSG("RxMessage[4] = %#x\n", m.msg.RxMessage[4]);
- if (!(m.msg.RxMessage[4] & DSL_DEV_STAT_CODESWAP_COMPLETE)) {
- meierr = DSL_DEV_MEI_ERR_FAILURE;
- return -EAGAIN;
- }
- IFX_MEI_DMSG("Freeing all memories marked FREE_SHOWTIME\n");
- IFX_MEI_DFEMemoryFree (pDev, FREE_SHOWTIME);
- meierr = DSL_DEV_MEI_ERR_SUCCESS;
- break;
-#ifdef CONFIG_IFXMIPS_AMAZON_SE
- case DSL_FIO_ARC_MUX_TEST:
- AMAZON_SE_MEI_ARC_MUX_Test();
- break;
-#endif
- default:
-// IFX_MEI_EMSG("Invalid IOCTL command: %d\n");
- break;
- }
- return meierr;
-}
-
-#ifdef CONFIG_IFXMIPS_AMAZON_SE
-void AMAZON_SE_MEI_ARC_MUX_Test(void)
-{
- u32 *p, i;
- *IFXMIPS_RCU_RST |= IFXMIPS_RCU_RST_REQ_MUX_ARC;
-
- p = (u32*)(DFE_LDST_BASE_ADDR + IRAM0_BASE);
- IFX_MEI_EMSG("Writing to IRAM0(%p)...\n", p);
- for (i = 0; i < IRAM0_SIZE/sizeof(u32); i++, p++) {
- *p = 0xdeadbeef;
- if (*p != 0xdeadbeef)
- IFX_MEI_EMSG("%p: %#x\n", p, *p);
- }
-
- p = (u32*)(DFE_LDST_BASE_ADDR + IRAM1_BASE);
- IFX_MEI_EMSG("Writing to IRAM1(%p)...\n", p);
- for (i = 0; i < IRAM1_SIZE/sizeof(u32); i++, p++) {
- *p = 0xdeadbeef;
- if (*p != 0xdeadbeef)
- IFX_MEI_EMSG("%p: %#x\n", p, *p);
- }
-
- p = (u32*)(DFE_LDST_BASE_ADDR + BRAM_BASE);
- IFX_MEI_EMSG("Writing to BRAM(%p)...\n", p);
- for (i = 0; i < BRAM_SIZE/sizeof(u32); i++, p++) {
- *p = 0xdeadbeef;
- if (*p != 0xdeadbeef)
- IFX_MEI_EMSG("%p: %#x\n", p, *p);
- }
-
- p = (u32*)(DFE_LDST_BASE_ADDR + XRAM_BASE);
- IFX_MEI_EMSG("Writing to XRAM(%p)...\n", p);
- for (i = 0; i < XRAM_SIZE/sizeof(u32); i++, p++) {
- *p = 0xdeadbeef;
- if (*p != 0xdeadbeef)
- IFX_MEI_EMSG("%p: %#x\n", p, *p);
- }
-
- p = (u32*)(DFE_LDST_BASE_ADDR + YRAM_BASE);
- IFX_MEI_EMSG("Writing to YRAM(%p)...\n", p);
- for (i = 0; i < YRAM_SIZE/sizeof(u32); i++, p++) {
- *p = 0xdeadbeef;
- if (*p != 0xdeadbeef)
- IFX_MEI_EMSG("%p: %#x\n", p, *p);
- }
-
- p = (u32*)(DFE_LDST_BASE_ADDR + EXT_MEM_BASE);
- IFX_MEI_EMSG("Writing to EXT_MEM(%p)...\n", p);
- for (i = 0; i < EXT_MEM_SIZE/sizeof(u32); i++, p++) {
- *p = 0xdeadbeef;
- if (*p != 0xdeadbeef)
- IFX_MEI_EMSG("%p: %#x\n", p, *p);
- }
- *IFXMIPS_RCU_RST &= ~IFXMIPS_RCU_RST_REQ_MUX_ARC;
-}
-#endif
-int
-DSL_BSP_KernelIoctls (DSL_DEV_Device_t * pDev, unsigned int command,
- unsigned long lon)
-{
- int error = 0;
-
- error = IFX_MEI_Ioctls (pDev, 1, command, lon);
- return error;
-}
-
-static int
-IFX_MEI_UserIoctls (DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil,
- unsigned int command, unsigned long lon)
-{
- int error = 0;
- int maj = MAJOR (ino->i_rdev);
- int num = MINOR (ino->i_rdev);
- DSL_DEV_Device_t *pDev;
-
- pDev = IFX_BSP_HandleGet (maj, num);
- if (pDev == NULL)
- return -EIO;
-
- error = IFX_MEI_Ioctls (pDev, 0, command, lon);
- return error;
-}
-
-#ifdef CONFIG_PROC_FS
-/*
- * Register a callback function for linux proc filesystem
- */
-static int
-IFX_MEI_InitProcFS (int num)
-{
- struct proc_dir_entry *entry;
- int i ;
- DSL_DEV_Device_t *pDev;
- reg_entry_t regs_temp[PROC_ITEMS] = {
- /* flag, name, description } */
- {NULL, "arcmsgav", "arc to mei message ", 0},
- {NULL, "cmv_reply", "cmv needs reply", 0},
- {NULL, "cmv_waiting", "waiting for cmv reply from arc", 0},
- {NULL, "modem_ready_cnt", "ARC to MEI indicator count", 0},
- {NULL, "cmv_count", "MEI to ARC CMVs", 0},
- {NULL, "reply_count", "ARC to MEI Reply", 0},
- {NULL, "Recent_indicator", "most recent indicator", 0},
- {NULL, "fw_version", "Firmware Version", 0},
- {NULL, "fw_date", "Firmware Date", 0},
- {NULL, "meminfo", "Memory Allocation Information", 0},
- {NULL, "version", "MEI version information", 0},
- };
-
- pDev = &dsl_devices[num];
- if (pDev == NULL)
- return -ENOMEM;
-
- regs_temp[0].flag = &(DSL_DEV_PRIVATE(pDev)->arcmsgav);
- regs_temp[1].flag = &(DSL_DEV_PRIVATE(pDev)->cmv_reply);
- regs_temp[2].flag = &(DSL_DEV_PRIVATE(pDev)->cmv_waiting);
- regs_temp[3].flag = &(DSL_DEV_PRIVATE(pDev)->modem_ready_cnt);
- regs_temp[4].flag = &(DSL_DEV_PRIVATE(pDev)->cmv_count);
- regs_temp[5].flag = &(DSL_DEV_PRIVATE(pDev)->reply_count);
- regs_temp[6].flag = (int *) &(DSL_DEV_PRIVATE(pDev)->Recent_indicator);
-
- memcpy ((char *) regs[num], (char *) regs_temp, sizeof (regs_temp));
- // procfs
- meidir = proc_mkdir (MEI_DIRNAME, NULL);
- if (meidir == NULL) {
- IFX_MEI_EMSG ("Failed to create /proc/%s\n", MEI_DIRNAME);
- return (-ENOMEM);
- }
-
- for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
- entry = create_proc_entry (regs[num][i].name,
- S_IWUSR | S_IRUSR | S_IRGRP |
- S_IROTH, meidir);
- if (entry) {
- regs[num][i].low_ino = entry->low_ino;
- entry->proc_fops = &IFX_MEI_ProcOperations;
- }
- else {
- IFX_MEI_EMSG ("Failed to create /proc/%s/%s\n", MEI_DIRNAME, regs[num][i].name);
- return (-ENOMEM);
- }
- }
- return 0;
-}
-
-/*
- * Reading function for linux proc filesystem
- */
-static int
-IFX_MEI_ProcRead (struct file *file, char *buf, size_t nbytes, loff_t * ppos)
-{
- int i_ino = (file->f_dentry->d_inode)->i_ino;
- char *p = buf;
- int i;
- int num;
- reg_entry_t *entry = NULL;
- DSL_DEV_Device_t *pDev = NULL;
- DSL_DEV_WinHost_Message_t m;
-
- for (num = 0; num < BSP_MAX_DEVICES; num++) {
- for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
- if (regs[num][i].low_ino == (unsigned short)i_ino) {
- entry = ®s[num][i];
- pDev = &dsl_devices[num];
- break;
- }
- }
- }
- if (entry == NULL)
- return -EINVAL;
- else if (strcmp(entry->name, "meminfo") == 0) {
- if (*ppos > 0) /* Assume reading completed in previous read */
- return 0;
- p += sprintf (p, "No Address Size\n");
- for (i = 0; i < MAX_BAR_REGISTERS; i++) {
- p += sprintf (p, "BAR[%02d] Addr:0x%08X Size:%lu\n",
- i, (u32) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[i].address,
- DSL_DEV_PRIVATE(pDev)-> adsl_mem_info[i].size);
- //printk( "BAR[%02d] Addr:0x%08X Size:%d\n",i,adsl_mem_info[i].address,adsl_mem_info[i].size);
- }
- *ppos += (p - buf);
- } else if (strcmp(entry->name, "fw_version") == 0) {
- if (*ppos > 0) /* Assume reading completed in previous read */
- return 0;
- if (DSL_DEV_PRIVATE(pDev)->modem_ready_cnt < 1)
- return -EAGAIN;
- //major:bits 0-7
- //minor:bits 8-15
- makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 54, 0, 1, NULL, m.msg.TxMessage);
- if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
- return -EIO;
- p += sprintf(p, "FW Version: %d.%d.", m.msg.RxMessage[4] & 0xFF, (m.msg.RxMessage[4] >> 8) & 0xFF);
- //sub_version:bits 4-7
- //int_version:bits 0-3
- //spl_appl:bits 8-13
- //rel_state:bits 14-15
- makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 54, 1, 1, NULL, m.msg.TxMessage);
- if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
- return -EIO;
- p += sprintf(p, "%d.%d.%d.%d\n",
- (m.msg.RxMessage[4] >> 4) & 0xF, m.msg.RxMessage[4] & 0xF,
- (m.msg.RxMessage[4] >> 14) & 3, (m.msg.RxMessage[4] >> 8) & 0x3F);
- *ppos += (p - buf);
- } else if (strcmp(entry->name, "fw_date") == 0) {
- if (*ppos > 0) /* Assume reading completed in previous read */
- return 0;
- if (DSL_DEV_PRIVATE(pDev)->modem_ready_cnt < 1)
- return -EAGAIN;
-
- makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 55, 0, 1, NULL, m.msg.TxMessage);
- if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
- return -EIO;
- /* Day/Month */
- p += sprintf(p, "FW Date: %d.%d.", m.msg.RxMessage[4] & 0xFF, (m.msg.RxMessage[4] >> 8) & 0xFF);
-
- makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 55, 2, 1, NULL, m.msg.TxMessage);
- if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
- return -EIO;
- /* Year */
- p += sprintf(p, "%d ", m.msg.RxMessage[4]);
-
- makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 55, 1, 1, NULL, m.msg.TxMessage);
- if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
- return -EIO;
- /* Hour:Minute */
- p += sprintf(p, "%d:%d\n", (m.msg.RxMessage[4] >> 8) & 0xFF, m.msg.RxMessage[4] & 0xFF);
-
- *ppos += (p - buf);
- } else if (strcmp(entry->name, "version") == 0) {
- if (*ppos > 0) /* Assume reading completed in previous read */
- return 0;
- p += sprintf (p, "IFX MEI V%ld.%ld.%ld\n", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision);
-
- *ppos += (p - buf);
- } else if (entry->flag != (int *) DSL_DEV_PRIVATE(pDev)->Recent_indicator) {
- if (*ppos > 0) /* Assume reading completed in previous read */
- return 0; // indicates end of file
- p += sprintf (p, "0x%08X\n\n", *(entry->flag));
- *ppos += (p - buf);
- if ((p - buf) > nbytes) /* Assume output can be read at one time */
- return -EINVAL;
- } else {
- if ((int) (*ppos) / ((int) 7) == 16)
- return 0; // indicate end of the message
- p += sprintf (p, "0x%04X\n\n", *(((u16 *) (entry->flag)) + (int) (*ppos) / ((int) 7)));
- *ppos += (p - buf);
- }
- return p - buf;
-}
-
-/*
- * Writing function for linux proc filesystem
- */
-static ssize_t
-IFX_MEI_ProcWrite (struct file *file, const char *buffer, size_t count, loff_t * ppos)
-{
- int i_ino = (file->f_dentry->d_inode)->i_ino;
- reg_entry_t *current_reg = NULL;
- int i = 0;
- int num = 0;
- unsigned long newRegValue = 0;
- char *endp = NULL;
- DSL_DEV_Device_t *pDev = NULL;
-
- for (num = 0; num < BSP_MAX_DEVICES; num++) {
- for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
- if (regs[num][i].low_ino == i_ino) {
- current_reg = ®s[num][i];
- pDev = &dsl_devices[num];
- break;
- }
- }
- }
- if ((current_reg == NULL)
- || (current_reg->flag ==
- (int *) DSL_DEV_PRIVATE(pDev)->
- Recent_indicator))
- return -EINVAL;
-
- newRegValue = simple_strtoul (buffer, &endp, 0);
- *(current_reg->flag) = (int) newRegValue;
- return (count + endp - buffer);
-}
-#endif //CONFIG_PROC_FS
-
-static int adsl_dummy_ledcallback(void)
-{
- return 0;
-}
-
-int ifx_mei_atm_led_blink(void)
-{
- return g_adsl_ledcallback();
-}
-EXPORT_SYMBOL(ifx_mei_atm_led_blink);
-
-int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)
-{
- int i;
-
- if ( is_showtime ) {
- *is_showtime = g_tx_link_rate[0] == 0 && g_tx_link_rate[1] == 0 ? 0 : 1;
- }
-
- if ( port_cell ) {
- for ( i = 0; i < port_cell->port_num && i < 2; i++ )
- port_cell->tx_link_rate[i] = g_tx_link_rate[i];
- }
-
- if ( xdata_addr ) {
- if ( g_tx_link_rate[0] == 0 && g_tx_link_rate[1] == 0 )
- *xdata_addr = NULL;
- else
- *xdata_addr = g_xdata_addr;
- }
-
- return 0;
-}
-EXPORT_SYMBOL(ifx_mei_atm_showtime_check);
-
-/*
- * Writing function for linux proc filesystem
- */
-int __init
-IFX_MEI_ModuleInit (void)
-{
- int i = 0;
-
- printk ("IFX MEI Version %ld.%02ld.%02ld", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision);
-
- for (i = 0; i < BSP_MAX_DEVICES; i++) {
- if (IFX_MEI_InitDevice (i) != 0) {
- printk ("%s: Init device fail!\n", __FUNCTION__);
- return -EIO;
- }
- IFX_MEI_InitDevNode (i);
-#ifdef CONFIG_PROC_FS
- IFX_MEI_InitProcFS (i);
-#endif
- }
- for (i = 0; i <= DSL_BSP_CB_LAST ; i++)
- dsl_bsp_event_callback[i].function = NULL;
-
-#ifdef CONFIG_IFXMIPS_MEI_FW_LOOPBACK
- printk(KERN_INFO "[%s %s %d]: Start loopback test...\n", __FILE__, __func__, __LINE__);
- DFE_Loopback_Test ();
-#endif
-
- return 0;
-}
-
-void __exit
-IFX_MEI_ModuleExit (void)
-{
- int i = 0;
- int num;
-
- for (num = 0; num < BSP_MAX_DEVICES; num++) {
- IFX_MEI_CleanUpDevNode (num);
-#ifdef CONFIG_PROC_FS
- for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
- remove_proc_entry (regs[num][i].name, meidir);
- }
-#endif
- }
-
- remove_proc_entry (MEI_DIRNAME, NULL);
- for (i = 0; i < BSP_MAX_DEVICES; i++) {
- for (i = 0; i < BSP_MAX_DEVICES; i++) {
- IFX_MEI_ExitDevice (i);
- }
- }
-}
-
-/* export function for DSL Driver */
-
-/* The functions of MEI_DriverHandleGet and MEI_DriverHandleDelete are
-something like open/close in kernel space , where the open could be used
-to register a callback for autonomous messages and returns a mei driver context pointer (comparable to the file descriptor in user space)
- The context will be required for the multi line chips future! */
-
-EXPORT_SYMBOL (DSL_BSP_DriverHandleGet);
-EXPORT_SYMBOL (DSL_BSP_DriverHandleDelete);
-
-EXPORT_SYMBOL (DSL_BSP_ATMLedCBRegister);
-EXPORT_SYMBOL (DSL_BSP_ATMLedCBUnregister);
-EXPORT_SYMBOL (DSL_BSP_KernelIoctls);
-EXPORT_SYMBOL (DSL_BSP_AdslLedInit);
-//EXPORT_SYMBOL (DSL_BSP_AdslLedSet);
-EXPORT_SYMBOL (DSL_BSP_FWDownload);
-EXPORT_SYMBOL (DSL_BSP_Showtime);
-
-EXPORT_SYMBOL (DSL_BSP_MemoryDebugAccess);
-EXPORT_SYMBOL (DSL_BSP_SendCMV);
-
-// provide a register/unregister function for DSL driver to register a event callback function
-EXPORT_SYMBOL (DSL_BSP_EventCBRegister);
-EXPORT_SYMBOL (DSL_BSP_EventCBUnregister);
-
-module_init (IFX_MEI_ModuleInit);
-module_exit (IFX_MEI_ModuleExit);
+++ /dev/null
-/******************************************************************************
-
- Copyright (c) 2009
- Infineon Technologies AG
- Am Campeon 1-12; 81726 Munich, Germany
-
- For licensing information, see the file 'LICENSE' in the root folder of
- this software module.
-
-******************************************************************************/
-
-#ifndef IFXMIPS_MEI_H
-#define IFXMIPS_MEI_H
-
-#define CONFIG_DANUBE 1
-
-#if !defined(CONFIG_DANUBE) && !defined(CONFIG_AMAZON_SE) && !defined(CONFIG_AR9) && !defined(CONFIG_VR9)
-#error Platform undefined!!!
-#endif
-
-#ifdef IFX_MEI_BSP
-/** This is the character datatype. */
-typedef char DSL_char_t;
-/** This is the unsigned 8-bit datatype. */
-typedef unsigned char DSL_uint8_t;
-/** This is the signed 8-bit datatype. */
-typedef signed char DSL_int8_t;
-/** This is the unsigned 16-bit datatype. */
-typedef unsigned short DSL_uint16_t;
-/** This is the signed 16-bit datatype. */
-typedef signed short DSL_int16_t;
-/** This is the unsigned 32-bit datatype. */
-typedef unsigned long DSL_uint32_t;
-/** This is the signed 32-bit datatype. */
-typedef signed long DSL_int32_t;
-/** This is the float datatype. */
-typedef float DSL_float_t;
-/** This is the void datatype. */
-typedef void DSL_void_t;
-/** integer type, width is depending on processor arch */
-typedef int DSL_int_t;
-/** unsigned integer type, width is depending on processor arch */
-typedef unsigned int DSL_uint_t;
-typedef struct file DSL_DRV_file_t;
-typedef struct inode DSL_DRV_inode_t;
-
-/**
- * Defines all possible CMV groups
- * */
-typedef enum {
- DSL_CMV_GROUP_CNTL = 1,
- DSL_CMV_GROUP_STAT = 2,
- DSL_CMV_GROUP_INFO = 3,
- DSL_CMV_GROUP_TEST = 4,
- DSL_CMV_GROUP_OPTN = 5,
- DSL_CMV_GROUP_RATE = 6,
- DSL_CMV_GROUP_PLAM = 7,
- DSL_CMV_GROUP_CNFG = 8
-} DSL_CmvGroup_t;
-/**
- * Defines all opcode types
- * */
-typedef enum {
- H2D_CMV_READ = 0x00,
- H2D_CMV_WRITE = 0x04,
- H2D_CMV_INDICATE_REPLY = 0x10,
- H2D_ERROR_OPCODE_UNKNOWN =0x20,
- H2D_ERROR_CMV_UNKNOWN =0x30,
-
- D2H_CMV_READ_REPLY =0x01,
- D2H_CMV_WRITE_REPLY = 0x05,
- D2H_CMV_INDICATE = 0x11,
- D2H_ERROR_OPCODE_UNKNOWN = 0x21,
- D2H_ERROR_CMV_UNKNOWN = 0x31,
- D2H_ERROR_CMV_READ_NOT_AVAILABLE = 0x41,
- D2H_ERROR_CMV_WRITE_ONLY = 0x51,
- D2H_ERROR_CMV_READ_ONLY = 0x61,
-
- H2D_DEBUG_READ_DM = 0x02,
- H2D_DEBUG_READ_PM = 0x06,
- H2D_DEBUG_WRITE_DM = 0x0a,
- H2D_DEBUG_WRITE_PM = 0x0e,
-
- D2H_DEBUG_READ_DM_REPLY = 0x03,
- D2H_DEBUG_READ_FM_REPLY = 0x07,
- D2H_DEBUG_WRITE_DM_REPLY = 0x0b,
- D2H_DEBUG_WRITE_FM_REPLY = 0x0f,
- D2H_ERROR_ADDR_UNKNOWN = 0x33,
-
- D2H_AUTONOMOUS_MODEM_READY_MSG = 0xf1
-} DSL_CmvOpcode_t;
-
-/* mutex macros */
-#define MEI_MUTEX_INIT(id,flag) \
- sema_init(&id,flag)
-#define MEI_MUTEX_LOCK(id) \
- down_interruptible(&id)
-#define MEI_MUTEX_UNLOCK(id) \
- up(&id)
-#define MEI_WAIT(ms) \
- {\
- set_current_state(TASK_INTERRUPTIBLE);\
- schedule_timeout(ms);\
- }
-#define MEI_INIT_WAKELIST(name,queue) \
- init_waitqueue_head(&queue)
-
-/* wait for an event, timeout is measured in ms */
-#define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\
- interruptible_sleep_on_timeout(&ev,timeout * HZ / 1000)
-#define MEI_WAKEUP_EVENT(ev)\
- wake_up_interruptible(&ev)
-#endif /* IFX_MEI_BSP */
-
-/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/
-#define ME_DX_DATA (0x0000)
-#define ME_VERSION (0x0004)
-#define ME_ARC_GP_STAT (0x0008)
-#define ME_DX_STAT (0x000C)
-#define ME_DX_AD (0x0010)
-#define ME_DX_MWS (0x0014)
-#define ME_ME2ARC_INT (0x0018)
-#define ME_ARC2ME_STAT (0x001C)
-#define ME_ARC2ME_MASK (0x0020)
-#define ME_DBG_WR_AD (0x0024)
-#define ME_DBG_RD_AD (0x0028)
-#define ME_DBG_DATA (0x002C)
-#define ME_DBG_DECODE (0x0030)
-#define ME_CONFIG (0x0034)
-#define ME_RST_CTRL (0x0038)
-#define ME_DBG_MASTER (0x003C)
-#define ME_CLK_CTRL (0x0040)
-#define ME_BIST_CTRL (0x0044)
-#define ME_BIST_STAT (0x0048)
-#define ME_XDATA_BASE_SH (0x004c)
-#define ME_XDATA_BASE (0x0050)
-#define ME_XMEM_BAR_BASE (0x0054)
-#define ME_XMEM_BAR0 (0x0054)
-#define ME_XMEM_BAR1 (0x0058)
-#define ME_XMEM_BAR2 (0x005C)
-#define ME_XMEM_BAR3 (0x0060)
-#define ME_XMEM_BAR4 (0x0064)
-#define ME_XMEM_BAR5 (0x0068)
-#define ME_XMEM_BAR6 (0x006C)
-#define ME_XMEM_BAR7 (0x0070)
-#define ME_XMEM_BAR8 (0x0074)
-#define ME_XMEM_BAR9 (0x0078)
-#define ME_XMEM_BAR10 (0x007C)
-#define ME_XMEM_BAR11 (0x0080)
-#define ME_XMEM_BAR12 (0x0084)
-#define ME_XMEM_BAR13 (0x0088)
-#define ME_XMEM_BAR14 (0x008C)
-#define ME_XMEM_BAR15 (0x0090)
-#define ME_XMEM_BAR16 (0x0094)
-
-#define WHILE_DELAY 20000
-/*
-** Define where in ME Processor's memory map the Stratify chip lives
-*/
-
-#define MAXSWAPSIZE (8 * 1024) //8k *(32bits)
-
-// Mailboxes
-#define MSG_LENGTH 16 // x16 bits
-#define YES_REPLY 1
-#define NO_REPLY 0
-
-#define CMV_TIMEOUT 1000 //jiffies
-
-// Block size per BAR
-#define SDRAM_SEGMENT_SIZE (64*1024)
-// Number of Bar registers
-#define MAX_BAR_REGISTERS (17)
-
-#define XDATA_REGISTER (15)
-
-// ARC register addresss
-#define ARC_STATUS 0x0
-#define ARC_LP_START 0x2
-#define ARC_LP_END 0x3
-#define ARC_DEBUG 0x5
-#define ARC_INT_MASK 0x10A
-
-#define IRAM0_BASE (0x00000)
-#define IRAM1_BASE (0x04000)
-#if defined(CONFIG_DANUBE)
-#define BRAM_BASE (0x0A000)
-#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
-#define BRAM_BASE (0x08000)
-#endif
-#define XRAM_BASE (0x18000)
-#define YRAM_BASE (0x1A000)
-#define EXT_MEM_BASE (0x80000)
-#define ARC_GPIO_CTRL (0xC030)
-#define ARC_GPIO_DATA (0xC034)
-
-#define IRAM0_SIZE (16*1024)
-#define IRAM1_SIZE (16*1024)
-#define BRAM_SIZE (12*1024)
-#define XRAM_SIZE (8*1024)
-#define YRAM_SIZE (8*1024)
-#define EXT_MEM_SIZE (1536*1024)
-
-#define ADSL_BASE (0x20000)
-#define CRI_BASE (ADSL_BASE + 0x11F00)
-#define CRI_CCR0 (CRI_BASE + 0x00)
-#define CRI_RST (CRI_BASE + 0x04*4)
-#define ADSL_DILV_BASE (ADSL_BASE+0x20000)
-
-//
-#define IRAM0_ADDR_BIT_MASK 0xFFF
-#define IRAM1_ADDR_BIT_MASK 0xFFF
-#define BRAM_ADDR_BIT_MASK 0xFFF
-#define RX_DILV_ADDR_BIT_MASK 0x1FFF
-
-/*** Bit definitions ***/
-#define ARC_AUX_HALT (1 << 25)
-#define ARC_DEBUG_HALT (1 << 1)
-#define FALSE 0
-#define TRUE 1
-#define BIT0 (1<<0)
-#define BIT1 (1<<1)
-#define BIT2 (1<<2)
-#define BIT3 (1<<3)
-#define BIT4 (1<<4)
-#define BIT5 (1<<5)
-#define BIT6 (1<<6)
-#define BIT7 (1<<7)
-#define BIT8 (1<<8)
-#define BIT9 (1<<9)
-#define BIT10 (1<<10)
-#define BIT11 (1<<11)
-#define BIT12 (1<<12)
-#define BIT13 (1<<13)
-#define BIT14 (1<<14)
-#define BIT15 (1<<15)
-#define BIT16 (1<<16)
-#define BIT17 (1<<17)
-#define BIT18 (1<<18)
-#define BIT19 (1<<19)
-#define BIT20 (1<<20)
-#define BIT21 (1<<21)
-#define BIT22 (1<<22)
-#define BIT23 (1<<23)
-#define BIT24 (1<<24)
-#define BIT25 (1<<25)
-#define BIT26 (1<<26)
-#define BIT27 (1<<27)
-#define BIT28 (1<<28)
-#define BIT29 (1<<29)
-#define BIT30 (1<<30)
-#define BIT31 (1<<31)
-
-// CRI_CCR0 Register definitions
-#define CLK_2M_MODE_ENABLE BIT6
-#define ACL_CLK_MODE_ENABLE BIT4
-#define FDF_CLK_MODE_ENABLE BIT2
-#define STM_CLK_MODE_ENABLE BIT0
-
-// CRI_RST Register definitions
-#define FDF_SRST BIT3
-#define MTE_SRST BIT2
-#define FCI_SRST BIT1
-#define AAI_SRST BIT0
-
-// MEI_TO_ARC_INTERRUPT Register definitions
-#define MEI_TO_ARC_INT1 BIT3
-#define MEI_TO_ARC_INT0 BIT2
-#define MEI_TO_ARC_CS_DONE BIT1 //need to check
-#define MEI_TO_ARC_MSGAV BIT0
-
-// ARC_TO_MEI_INTERRUPT Register definitions
-#define ARC_TO_MEI_INT1 BIT8
-#define ARC_TO_MEI_INT0 BIT7
-#define ARC_TO_MEI_CS_REQ BIT6
-#define ARC_TO_MEI_DBG_DONE BIT5
-#define ARC_TO_MEI_MSGACK BIT4
-#define ARC_TO_MEI_NO_ACCESS BIT3
-#define ARC_TO_MEI_CHECK_AAITX BIT2
-#define ARC_TO_MEI_CHECK_AAIRX BIT1
-#define ARC_TO_MEI_MSGAV BIT0
-
-// ARC_TO_MEI_INTERRUPT_MASK Register definitions
-#define GP_INT1_EN BIT8
-#define GP_INT0_EN BIT7
-#define CS_REQ_EN BIT6
-#define DBG_DONE_EN BIT5
-#define MSGACK_EN BIT4
-#define NO_ACC_EN BIT3
-#define AAITX_EN BIT2
-#define AAIRX_EN BIT1
-#define MSGAV_EN BIT0
-
-#define MEI_SOFT_RESET BIT0
-
-#define HOST_MSTR BIT0
-
-#define JTAG_MASTER_MODE 0x0
-#define MEI_MASTER_MODE HOST_MSTR
-
-// MEI_DEBUG_DECODE Register definitions
-#define MEI_DEBUG_DEC_MASK (0x3)
-#define MEI_DEBUG_DEC_AUX_MASK (0x0)
-#define ME_DBG_DECODE_DMP1_MASK (0x1)
-#define MEI_DEBUG_DEC_DMP2_MASK (0x2)
-#define MEI_DEBUG_DEC_CORE_MASK (0x3)
-
-#define AUX_STATUS (0x0)
-#define AUX_ARC_GPIO_CTRL (0x10C)
-#define AUX_ARC_GPIO_DATA (0x10D)
-// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
-// page swap requests.
-#if defined(CONFIG_DANUBE)
-#define OMBOX_BASE 0xDF80
-#define ARC_TO_MEI_MAILBOX 0xDFA0
-#define IMBOX_BASE 0xDFC0
-#define MEI_TO_ARC_MAILBOX 0xDFD0
-#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
-#define OMBOX_BASE 0xAF80
-#define ARC_TO_MEI_MAILBOX 0xAFA0
-#define IMBOX_BASE 0xAFC0
-#define MEI_TO_ARC_MAILBOX 0xAFD0
-#endif
-
-#define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C)
-#define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C)
-#define OMBOX1 (OMBOX_BASE+0x4)
-
-// Codeswap request messages are indicated by setting BIT31
-#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000)
-
-// Clear Eoc messages received are indicated by setting BIT17
-#define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000)
-#define OMB_REBOOT_INTERRUPT_CODE (1 << 18)
-
-/*
-** Swap page header
-*/
-// Page must be loaded at boot time if size field has BIT31 set
-#define BOOT_FLAG (BIT31)
-#define BOOT_FLAG_MASK ~BOOT_FLAG
-
-#define FREE_RELOAD 1
-#define FREE_SHOWTIME 2
-#define FREE_ALL 3
-
-// marcos
-#define IFX_MEI_WRITE_REGISTER_L(data,addr) *((volatile u32*)(addr)) = (u32)(data)
-#define IFX_MEI_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
-#define SET_BIT(reg, mask) reg |= (mask)
-#define CLEAR_BIT(reg, mask) reg &= (~mask)
-#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
-//#define SET_BITS(reg, mask) SET_BIT(reg, mask)
-#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
-
-#define ALIGN_SIZE ( 1L<<10 ) //1K size align
-#define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
-
-// swap marco
-#define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
-#define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
-
-
-#ifdef CONFIG_PROC_FS
-typedef struct reg_entry
-{
- int *flag;
- char name[30]; /* big enough to hold names */
- char description[100]; /* big enough to hold description */
- unsigned short low_ino;
-} reg_entry_t;
-#endif
-// Swap page header describes size in 32-bit words, load location, and image offset
-// for program and/or data segments
-typedef struct _arc_swp_page_hdr {
- u32 p_offset; //Offset bytes of progseg from beginning of image
- u32 p_dest; //Destination addr of progseg on processor
- u32 p_size; //Size in 32-bitwords of program segment
- u32 d_offset; //Offset bytes of dataseg from beginning of image
- u32 d_dest; //Destination addr of dataseg on processor
- u32 d_size; //Size in 32-bitwords of data segment
-} ARC_SWP_PAGE_HDR;
-
-/*
-** Swap image header
-*/
-#define GET_PROG 0 // Flag used for program mem segment
-#define GET_DATA 1 // Flag used for data mem segment
-
-// Image header contains size of image, checksum for image, and count of
-// page headers. Following that are 'count' page headers followed by
-// the code and/or data segments to be loaded
-typedef struct _arc_img_hdr {
- u32 size; // Size of binary image in bytes
- u32 checksum; // Checksum for image
- u32 count; // Count of swp pages in image
- ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy
-} ARC_IMG_HDR;
-
-typedef struct smmu_mem_info {
- int type;
- int boot;
- unsigned long nCopy;
- unsigned long size;
- unsigned char *address;
- unsigned char *org_address;
-} smmu_mem_info_t;
-
-#ifdef __KERNEL__
-typedef struct ifx_mei_device_private {
- int modem_ready;
- int arcmsgav;
- int cmv_reply;
- int cmv_waiting;
- // Mei to ARC CMV count, reply count, ARC Indicator count
- int modem_ready_cnt;
- int cmv_count;
- int reply_count;
- unsigned long image_size;
- int nBar;
- u16 Recent_indicator[MSG_LENGTH];
-
- u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));
-
- smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS];
- ARC_IMG_HDR *img_hdr;
- // to wait for arc cmv reply, sleep on wait_queue_arcmsgav;
- wait_queue_head_t wait_queue_arcmsgav;
- wait_queue_head_t wait_queue_modemready;
- struct semaphore mei_cmv_sema;
-} ifx_mei_device_private_t;
-#endif
-typedef struct winhost_message {
- union {
- u16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
- u16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
- } msg;
-} DSL_DEV_WinHost_Message_t;
-/********************************************************************************************************
- * DSL CPE API Driver Stack Interface Definitions
- * *****************************************************************************************************/
-/** IOCTL codes for bsp driver */
-#define DSL_IOC_MEI_BSP_MAGIC 's'
-
-#define DSL_FIO_BSP_DSL_START _IO (DSL_IOC_MEI_BSP_MAGIC, 0)
-#define DSL_FIO_BSP_RUN _IO (DSL_IOC_MEI_BSP_MAGIC, 1)
-#define DSL_FIO_BSP_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 2)
-#define DSL_FIO_BSP_RESET _IO (DSL_IOC_MEI_BSP_MAGIC, 3)
-#define DSL_FIO_BSP_REBOOT _IO (DSL_IOC_MEI_BSP_MAGIC, 4)
-#define DSL_FIO_BSP_HALT _IO (DSL_IOC_MEI_BSP_MAGIC, 5)
-#define DSL_FIO_BSP_BOOTDOWNLOAD _IO (DSL_IOC_MEI_BSP_MAGIC, 6)
-#define DSL_FIO_BSP_JTAG_ENABLE _IO (DSL_IOC_MEI_BSP_MAGIC, 7)
-#define DSL_FIO_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 8)
-#define DSL_FIO_ARC_MUX_TEST _IO (DSL_IOC_MEI_BSP_MAGIC, 9)
-#define DSL_FIO_BSP_REMOTE _IOW (DSL_IOC_MEI_BSP_MAGIC, 10, u32)
-#define DSL_FIO_BSP_GET_BASE_ADDRESS _IOR (DSL_IOC_MEI_BSP_MAGIC, 11, u32)
-#define DSL_FIO_BSP_IS_MODEM_READY _IOR (DSL_IOC_MEI_BSP_MAGIC, 12, u32)
-#define DSL_FIO_BSP_GET_VERSION _IOR (DSL_IOC_MEI_BSP_MAGIC, 13, DSL_DEV_Version_t)
-#define DSL_FIO_BSP_CMV_WINHOST _IOWR(DSL_IOC_MEI_BSP_MAGIC, 14, DSL_DEV_WinHost_Message_t)
-#define DSL_FIO_BSP_CMV_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 15, DSL_DEV_MeiReg_t)
-#define DSL_FIO_BSP_CMV_WRITE _IOW (DSL_IOC_MEI_BSP_MAGIC, 16, DSL_DEV_MeiReg_t)
-#define DSL_FIO_BSP_DEBUG_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 17, DSL_DEV_MeiDebug_t)
-#define DSL_FIO_BSP_DEBUG_WRITE _IOWR(DSL_IOC_MEI_BSP_MAGIC, 18, DSL_DEV_MeiDebug_t)
-#define DSL_FIO_BSP_GET_CHIP_INFO _IOR (DSL_IOC_MEI_BSP_MAGIC, 19, DSL_DEV_HwVersion_t)
-
-#define DSL_DEV_MEIDEBUG_BUFFER_SIZES 512
-
-typedef struct DSL_DEV_MeiDebug
-{
- DSL_uint32_t iAddress;
- DSL_uint32_t iCount;
- DSL_uint32_t buffer[DSL_DEV_MEIDEBUG_BUFFER_SIZES];
-} DSL_DEV_MeiDebug_t; /* meidebug */
-
-/**
- * Structure is used for debug access only.
- * Refer to configure option INCLUDE_ADSL_WINHOST_DEBUG */
-typedef struct struct_meireg
-{
- /*
- * Specifies that address for debug access */
- unsigned long iAddress;
- /*
- * Specifies the pointer to the data that has to be written or returns a
- * pointer to the data that has been read out*/
- unsigned long iData;
-} DSL_DEV_MeiReg_t; /* meireg */
-
-typedef struct DSL_DEV_Device
-{
- DSL_int_t nInUse; /* modem state, update by bsp driver, */
- DSL_void_t *pPriv;
- DSL_uint32_t base_address; /* mei base address */
- DSL_int_t nIrq[2]; /* irq number */
-#define IFX_DFEIR 0
-#define IFX_DYING_GASP 1
- DSL_DEV_MeiDebug_t lop_debugwr; /* dying gasp */
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0))
- struct module *owner;
-#endif
-} DSL_DEV_Device_t; /* ifx_adsl_device_t */
-
-#define DSL_DEV_PRIVATE(dev) ((ifx_mei_device_private_t*)(dev->pPriv))
-
-typedef struct DSL_DEV_Version /* ifx_adsl_bsp_version */
-{
- unsigned long major;
- unsigned long minor;
- unsigned long revision;
-} DSL_DEV_Version_t; /* ifx_adsl_bsp_version_t */
-
-typedef struct DSL_DEV_ChipInfo
-{
- unsigned long major;
- unsigned long minor;
-} DSL_DEV_HwVersion_t;
-
-typedef struct
-{
- DSL_uint8_t dummy;
-} DSL_DEV_DeviceConfig_t;
-
-/** error code definitions */
-typedef enum DSL_DEV_MeiError
-{
- DSL_DEV_MEI_ERR_SUCCESS = 0,
- DSL_DEV_MEI_ERR_FAILURE = -1,
- DSL_DEV_MEI_ERR_MAILBOX_FULL = -2,
- DSL_DEV_MEI_ERR_MAILBOX_EMPTY = -3,
- DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT = -4
-} DSL_DEV_MeiError_t; /* MEI_ERROR */
-
-typedef enum {
- DSL_BSP_MEMORY_READ=0,
- DSL_BSP_MEMORY_WRITE,
-} DSL_BSP_MemoryAccessType_t; /* ifx_adsl_memory_access_type_t */
-
-typedef enum
-{
- DSL_LED_LINK_ID=0,
- DSL_LED_DATA_ID
-} DSL_DEV_LedId_t; /* ifx_adsl_led_id_t */
-
-typedef enum
-{
- DSL_LED_LINK_TYPE=0,
- DSL_LED_DATA_TYPE
-} DSL_DEV_LedType_t; /* ifx_adsl_led_type_t */
-
-typedef enum
-{
- DSL_LED_HD_CPU=0,
- DSL_LED_HD_FW
-} DSL_DEV_LedHandler_t; /* ifx_adsl_led_handler_t */
-
-typedef enum {
- DSL_LED_ON=0,
- DSL_LED_OFF,
- DSL_LED_FLASH,
-} DSL_DEV_LedMode_t; /* ifx_adsl_led_mode_t */
-
-typedef enum {
- DSL_CPU_HALT=0,
- DSL_CPU_RUN,
- DSL_CPU_RESET,
-} DSL_DEV_CpuMode_t; /* ifx_adsl_cpu_mode_t */
-
-#if 0
-typedef enum {
- DSL_BSP_EVENT_DYING_GASP = 0,
- DSL_BSP_EVENT_CEOC_IRQ,
-} DSL_BSP_Event_id_t; /* ifx_adsl_event_id_t */
-
-typedef union DSL_BSP_CB_Param
-{
- DSL_uint32_t nIrqMessage;
-} DSL_BSP_CB_Param_t; /* ifx_adsl_cbparam_t */
-
-typedef struct DSL_BSP_CB_Event
-{
- DSL_BSP_Event_id_t nID;
- DSL_DEV_Device_t *pDev;
- DSL_BSP_CB_Param_t *pParam;
-} DSL_BSP_CB_Event_t; /* ifx_adsl_cb_event_t */
-#endif
-
-/* external functions (from the BSP Driver) */
-extern DSL_DEV_Device_t* DSL_BSP_DriverHandleGet(int, int);
-extern DSL_int_t DSL_BSP_DriverHandleDelete(DSL_DEV_Device_t *);
-extern DSL_DEV_MeiError_t DSL_BSP_FWDownload(DSL_DEV_Device_t *, const DSL_char_t *, DSL_uint32_t, DSL_int32_t *, DSL_int32_t *);
-extern int DSL_BSP_KernelIoctls(DSL_DEV_Device_t *, unsigned int, unsigned long);
-extern DSL_DEV_MeiError_t DSL_BSP_SendCMV(DSL_DEV_Device_t *, DSL_uint16_t *, DSL_int_t, DSL_uint16_t *);
-extern DSL_DEV_MeiError_t DSL_BSP_AdslLedInit(DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t);
-extern DSL_DEV_MeiError_t DSL_BSP_Showtime(DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t);
-extern int DSL_BSP_ATMLedCBRegister( int (*ifx_adsl_ledcallback)(void));
-extern DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess(DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t *, DSL_uint32_t);
-extern volatile DSL_DEV_Device_t *adsl_dev;
-
-/**
- * Dummy structure by now to show mechanism of extended data that will be
- * provided within event callback itself.
- * */
-typedef struct
-{
- /**
- * Dummy value */
- DSL_uint32_t nDummy1;
-} DSL_BSP_CB_Event1DataDummy_t;
-
-/**
- * Dummy structure by now to show mechanism of extended data that will be
- * provided within event callback itself.
- * */
-typedef struct
-{
- /**
- * Dummy value */
- DSL_uint32_t nDummy2;
-} DSL_BSP_CB_Event2DataDummy_t;
-
-/**
- * encapsulate all data structures that are necessary for status event
- * callbacks.
- * */
-typedef union
-{
- DSL_BSP_CB_Event1DataDummy_t dataEvent1;
- DSL_BSP_CB_Event2DataDummy_t dataEvent2;
-} DSL_BSP_CB_DATA_Union_t;
-
-
-typedef enum
-{
- /**
- * Informs the upper layer driver (DSL CPE API) about a reboot request from the
- * firmware.
- * \note This event does NOT include any additional data.
- * More detailed information upon reboot reason has to be requested from
- * upper layer software via CMV (INFO 109) if necessary. */
- DSL_BSP_CB_FIRST = 0,
- DSL_BSP_CB_DYING_GASP,
- DSL_BSP_CB_CEOC_IRQ,
- DSL_BSP_CB_FIRMWARE_REBOOT,
- /**
- * Delimiter only */
- DSL_BSP_CB_LAST
-} DSL_BSP_CB_Type_t;
-
-/**
- * Specifies the common event type that has to be used for registering and
- * signalling of interrupts/autonomous status events from MEI BSP Driver.
- *
- * \param pDev
- * Context pointer from MEI BSP Driver.
- *
- * \param IFX_ADSL_BSP_CallbackType_t
- * Specifies the event callback type (reason of callback). Regrading to the
- * setting of this value the data which is included in the following union
- * might have different meanings.
- * Please refer to the description of the union to get information about the
- * meaning of the included data.
- *
- * \param pData
- * Data according to \ref DSL_BSP_CB_DATA_Union_t.
- * If this pointer is NULL there is no additional data available.
- *
- * \return depending on event
- */
-typedef int (*DSL_BSP_EventCallback_t)
-(
- DSL_DEV_Device_t *pDev,
- DSL_BSP_CB_Type_t nCallbackType,
- DSL_BSP_CB_DATA_Union_t *pData
-);
-
-typedef struct {
- DSL_BSP_EventCallback_t function;
- DSL_BSP_CB_Type_t event;
- DSL_BSP_CB_DATA_Union_t *pData;
-} DSL_BSP_EventCallBack_t;
-
-extern int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *);
-extern int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *);
-
-/** Modem states */
-#define DSL_DEV_STAT_InitState 0x0000
-#define DSL_DEV_STAT_ReadyState 0x0001
-#define DSL_DEV_STAT_FailState 0x0002
-#define DSL_DEV_STAT_IdleState 0x0003
-#define DSL_DEV_STAT_QuietState 0x0004
-#define DSL_DEV_STAT_GhsState 0x0005
-#define DSL_DEV_STAT_FullInitState 0x0006
-#define DSL_DEV_STAT_ShowTimeState 0x0007
-#define DSL_DEV_STAT_FastRetrainState 0x0008
-#define DSL_DEV_STAT_LoopDiagMode 0x0009
-#define DSL_DEV_STAT_ShortInit 0x000A /* Bis short initialization */
-
-#define DSL_DEV_STAT_CODESWAP_COMPLETE 0x0002
-
-#endif //IFXMIPS_MEI_H
+++ /dev/null
-#
-# Copyright (C) 2009-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-# ralph / blogic
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_BASE_NAME:=dsl_cpe_control_danube
-PKG_VERSION:=3.24.4.4
-PKG_RELEASE:=1
-PKG_SOURCE:=$(PKG_BASE_NAME)-$(PKG_VERSION).tar.gz
-PKG_BUILD_DIR:=$(BUILD_DIR)/dsl_cpe_control-$(PKG_VERSION)
-PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources/
-PKG_MD5SUM:=ee315306626b68794d3d3636dabfe161
-
-include $(INCLUDE_DIR)/package.mk
-
-define Package/ifxmips-dsl-control
- SECTION:=net
- CATEGORY:=Network
- TITLE:=DSL CPE control application
- URL:=http://www.infineon.com/
- MAINTAINER:=Infineon Technologies AG / Lantiq / John Crispin <blogic@openwrt.org>
- DEPENDS:=+kmod-ifxmips-dsl-api +libpthread
-endef
-
-define Package/ifxmips-dsl-control/description
- Infineon DSL CPE API for Amazon SE, Danube and Vinax.
- This package contains the DSL CPE control application for Amazon SE & Danube.
-
- Supported Devices:
- - Amazon SE
- - Danube
-
- This package was kindly contributed to openwrt by Infineon/Lantiq
-endef
-
-IFX_DSL_MAX_DEVICE=1
-IFX_DSL_LINES_PER_DEVICE=1
-IFX_DSL_CHANNELS_PER_LINE=1
-#CONFIG_IFX_CLI=y
-
-CONFIGURE_ARGS += \
- --with-max-device="$(IFX_DSL_MAX_DEVICE)" \
- --with-lines-per-device="$(IFX_DSL_LINES_PER_DEVICE)" \
- --with-channels-per-line="$(IFX_DSL_CHANNELS_PER_LINE)" \
- --enable-danube \
- --enable-driver-include="-I$(STAGING_DIR)/usr/include" \
- --enable-debug-prints \
- --enable-add-appl-cflags="-DMAX_CLI_PIPES=2" \
- --enable-cmv-scripts \
- --enable-debug-tool-interface \
- --enable-adsl-led \
- --enable-dsl-ceoc \
- --enable-script-notification \
- --enable-dsl-pm \
- --enable-dsl-pm-total \
- --enable-dsl-pm-history \
- --enable-dsl-pm-showtime \
- --enable-dsl-pm-channel-counters \
- --enable-dsl-pm-datapath-counters \
- --enable-dsl-pm-line-counters \
- --enable-dsl-pm-channel-thresholds \
- --enable-dsl-pm-datapath-thresholds \
- --enable-dsl-pm-line-thresholds \
- --enable-dsl-pm-optional-parameters
-
-ifeq ($(CONFIG_IFX_CLI),y)
-CONFIGURE_ARGS += \
- --enable-cli-support \
- --enable-soap-support
-endif
-
-TARGET_CFLAGS += -I$(LINUX_DIR)/include
-
-define Package/ifxmips-dsl-control/install
- $(INSTALL_DIR) $(1)/etc/init.d
- $(INSTALL_BIN) ./files/ifx_cpe_control_init.sh $(1)/etc/init.d/
-
- $(INSTALL_DIR) $(1)/sbin
- $(INSTALL_BIN) $(PKG_BUILD_DIR)/src/dsl_cpe_control $(1)/sbin
-endef
-
-$(eval $(call BuildPackage,ifxmips-dsl-control))
+++ /dev/null
-#!/bin/sh /etc/rc.common
-# Copyright (C) 2008 OpenWrt.org
-START=99
-
-start() {
-
- # start CPE dsl daemon in the background
- /sbin/dsl_cpe_control -i -f /lib/firmware/ModemHWE.bin &
-
-# PS=`ps`
-# echo $PS | grep -q dsl_cpe_control && {
-# # workaround for nfs: allow write to pipes for non-root
-# while [ ! -e /tmp/pipe/dsl_cpe1_ack ] ; do sleep 1; done
-# chmod a+w /tmp/pipe/dsl_*
-# }
- echo $PS | grep -q dsl_cpe_control || {
- echo "Start of dsl_cpe_control failed!!!"
- false
- }
-
-}
+++ /dev/null
-#
-# Copyright (C) 2007-2008 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=mips
-BOARD:=ifxmips
-BOARDNAME:=Infineon Mips
-FEATURES:=squashfs jffs2 atm
-SUBTARGETS:=danube ar9
-
-LINUX_VERSION:=2.6.35.9
-
-CFLAGS=-Os -pipe -mips32r2 -mtune=mips32r2 -funit-at-a-time
-
-include $(INCLUDE_DIR)/target.mk
-DEFAULT_PACKAGES+=uboot-lantiq kmod-pppoa ppp-mod-pppoa linux-atm atm-tools br2684ctl ifxmips-dsl-api ifxmips-dsl-control tapi_sip lqtapi_firmware_danube
-
-define Target/Description
- Build firmware images for Infineon Mips Controllers
-endef
-
-$(eval $(call BuildTarget))
+++ /dev/null
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-CONFIG_ADM6996_PHY=y
-# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
-# CONFIG_AR7 is not set
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_ARCH_SUPPORTS_OPROFILE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_BCM47XX is not set
-# CONFIG_BCM63XX is not set
-CONFIG_BITREVERSE=y
-# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
-# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_R4K_LIB=y
-CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_BIG_ENDIAN=y
-# CONFIG_CPU_CAVIUM_OCTEON is not set
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-# CONFIG_CPU_LITTLE_ENDIAN is not set
-# CONFIG_CPU_LOONGSON2E is not set
-# CONFIG_CPU_LOONGSON2F is not set
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-CONFIG_CPU_MIPSR2=y
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R5500 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_RM7000 is not set
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_VR41XX is not set
-CONFIG_CSRC_R4K=y
-CONFIG_CSRC_R4K_LIB=y
-CONFIG_DANUBE_MACH_ARV4519=y
-CONFIG_DANUBE_MACH_ARV45XX=y
-CONFIG_DANUBE_MACH_EASY4010=y
-CONFIG_DANUBE_MACH_EASY50712=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DEVPORT=y
-# CONFIG_DM9000 is not set
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_EARLY_PRINTK=y
-# CONFIG_FSNOTIFY is not set
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_STD_PC_SERIAL_PORT=y
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_IFXMIPS=y
-# CONFIG_IFXMIPS_AR9 is not set
-CONFIG_IFXMIPS_ARCAYDIAN_BRNBOOT=y
-# CONFIG_IFXMIPS_ASE is not set
-CONFIG_IFXMIPS_COMPAT=y
-CONFIG_IFXMIPS_DANUBE=y
-CONFIG_IFXMIPS_MII0=y
-# CONFIG_IFXMIPS_PROM_ASC0 is not set
-CONFIG_IFXMIPS_PROM_ASC1=y
-# CONFIG_IFXMIPS_VR9 is not set
-CONFIG_IFXMIPS_WDT=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQ_CPU=y
-CONFIG_KALLSYMS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_IFXMIPS=y
-# CONFIG_LOONGSON_MC146818 is not set
-CONFIG_LOONGSON_UART_BASE=y
-# CONFIG_MACH_ALCHEMY is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MACH_LOONGSON is not set
-# CONFIG_MACH_TX39XX is not set
-# CONFIG_MACH_TX49XX is not set
-# CONFIG_MACH_VR41XX is not set
-# CONFIG_MIKROTIK_RB532 is not set
-CONFIG_MIPS=y
-# CONFIG_MIPS_COBALT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_MACHINE=y
-# CONFIG_MIPS_MALTA is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_SIM is not set
-# CONFIG_MIPS_VPE_LOADER is not set
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_IFXMIPS=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NLS=y
-# CONFIG_NO_IOPORT is not set
-# CONFIG_NXP_STB220 is not set
-# CONFIG_NXP_STB225 is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PHYLIB=y
-# CONFIG_PMC_MSP is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-# CONFIG_POWERTV is not set
-CONFIG_RTL8306_PHY=y
-CONFIG_SCHED_OMIT_FRAME_POINTER=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SCSI_MOD=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_IFXMIPS=y
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP28 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_SWARM is not set
-CONFIG_SOC_DANUBE=y
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MULTITHREADING=y
-# CONFIG_TC35815 is not set
-# CONFIG_TINY_RCU is not set
-CONFIG_TRAD_SIGNALS=y
-CONFIG_TREE_RCU=y
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-#
-# Copyright (C) 2006-2008 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/None
- NAME:=Generic, No WiFi
- PACKAGES:=-wpad-mini
-endef
-
-define Profile/None/Description
- Package set without WiFi support
-endef
-$(eval $(call Profile,None))
-
+++ /dev/null
-#
-# Copyright (C) 2008 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Atheros
- NAME:=Atheros WiFi
- PACKAGES:=kmod-madwifi hostapd-mini
-endef
-
-$(eval $(call Profile,Atheros))
-
+++ /dev/null
-#
-# Copyright (C) 2008 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Ralink
- NAME:=Ralink RT61 Wifi
- PACKAGES:=kmod-rt61-pci hostapd-mini
-endef
-
-$(eval $(call Profile,Ralink))
-
+++ /dev/null
-ARCH:=mips
-SUBTARGET:=ar9
-BOARDNAME:=AR9
-FEATURES:=squashfs jffs2
-
-define Target/Description
- Lantiq AR9
-endef
-
+++ /dev/null
-config interface loopback
- option ifname lo
- option proto static
- option ipaddr 127.0.0.1
- option netmask 255.0.0.0
-
-config interface lan
- option ifname eth0
- option type bridge
- option proto static
- option ipaddr 192.168.1.1
- option netmask 255.255.255.0
-
-config atm-bridge
- option unit 0
- option encaps llc
- option vpi 1
- option vci 32
- option payload bridged # some ISPs need this set to 'routed'
-
-config interface wan
- option ifname nas0
- option proto pppoe
- option username ""
- option password ""
- option unit 0
+++ /dev/null
-[ "$ACTION" = "released" -a "$BUTTON" = reset ] && {
- reboot
-}
+++ /dev/null
-::sysinit:/etc/init.d/rcS S boot
-::shutdown:/etc/init.d/rcS K shutdown
-ttyS0::askfirst:/bin/ash --login
-ttyS1::askfirst:/bin/ash --login
+++ /dev/null
-PART_NAME=linux
-
-platform_check_image() {
- [ "$ARGC" -gt 1 ] && return 1
-
- case "$(get_magic_word "$1")" in
- # .trx files
- 2705) return 0;;
- *)
- echo "Invalid image type"
- return 1
- ;;
- esac
-}
-
-# use default for platform_do_upgrade()
-
-disable_watchdog() {
- killall watchdog
- ( ps | grep -v 'grep' | grep '/dev/watchdog' ) && {
- echo 'Could not disable watchdog'
- return 1
- }
-}
-append sysupgrade_pre_upgrade disable_watchdog
+++ /dev/null
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-CONFIG_ADM6996_PHY=y
-# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
-# CONFIG_AR7 is not set
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_ARCH_SUPPORTS_OPROFILE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_BCM47XX is not set
-# CONFIG_BCM63XX is not set
-CONFIG_BITREVERSE=y
-# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
-# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_R4K_LIB=y
-CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_BIG_ENDIAN=y
-# CONFIG_CPU_CAVIUM_OCTEON is not set
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-# CONFIG_CPU_LITTLE_ENDIAN is not set
-# CONFIG_CPU_LOONGSON2E is not set
-# CONFIG_CPU_LOONGSON2F is not set
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-CONFIG_CPU_MIPSR2=y
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R5500 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_RM7000 is not set
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_VR41XX is not set
-CONFIG_CSRC_R4K=y
-CONFIG_CSRC_R4K_LIB=y
-CONFIG_DANUBE_MACH_ARV4519=y
-CONFIG_DANUBE_MACH_ARV45XX=y
-CONFIG_DANUBE_MACH_EASY4010=y
-CONFIG_DANUBE_MACH_EASY50712=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DEVPORT=y
-# CONFIG_DM9000 is not set
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_EARLY_PRINTK is not set
-# CONFIG_FSNOTIFY is not set
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_STD_PC_SERIAL_PORT=y
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_IFXMIPS=y
-# CONFIG_IFXMIPS_AR9 is not set
-CONFIG_IFXMIPS_ARCAYDIAN_BRNBOOT=y
-# CONFIG_IFXMIPS_ASE is not set
-CONFIG_IFXMIPS_COMPAT=y
-CONFIG_IFXMIPS_DANUBE=y
-CONFIG_IFXMIPS_MII0=y
-# CONFIG_IFXMIPS_VR9 is not set
-CONFIG_IFXMIPS_WDT=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_GPIO_BUTTONS is not set
-CONFIG_IRQ_CPU=y
-CONFIG_KALLSYMS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_IFXMIPS=y
-# CONFIG_LOONGSON_MC146818 is not set
-# CONFIG_MACH_ALCHEMY is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MACH_LOONGSON is not set
-# CONFIG_MACH_TX39XX is not set
-# CONFIG_MACH_TX49XX is not set
-# CONFIG_MACH_VR41XX is not set
-# CONFIG_MIKROTIK_RB532 is not set
-CONFIG_MIPS=y
-# CONFIG_MIPS_COBALT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_MACHINE=y
-# CONFIG_MIPS_MALTA is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_SIM is not set
-# CONFIG_MIPS_VPE_LOADER is not set
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_IFXMIPS=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NLS=y
-# CONFIG_NO_IOPORT is not set
-# CONFIG_NXP_STB220 is not set
-# CONFIG_NXP_STB225 is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PHYLIB=y
-# CONFIG_PMC_MSP is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-# CONFIG_POWERTV is not set
-CONFIG_RTL8306_PHY=y
-CONFIG_SCHED_OMIT_FRAME_POINTER=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SCSI_MOD=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_IFXMIPS=y
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP28 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_SWARM is not set
-CONFIG_SOC_DANUBE=y
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MULTITHREADING=y
-# CONFIG_TC35815 is not set
-# CONFIG_TINY_RCU is not set
-CONFIG_TRAD_SIGNALS=y
-CONFIG_TREE_RCU=y
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-# CONFIG_USB_DWC_OTG is not set
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-#
-# Copyright (C) 2006-2008 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/None
- NAME:=Generic, No WiFi
- PACKAGES:=-wpad-mini
-endef
-
-define Profile/None/Description
- Package set without WiFi support
-endef
-$(eval $(call Profile,None))
-
+++ /dev/null
-#
-# Copyright (C) 2008 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Atheros
- NAME:=Atheros WiFi
- PACKAGES:=kmod-madwifi hostapd-mini
-endef
-
-$(eval $(call Profile,Atheros))
-
+++ /dev/null
-#
-# Copyright (C) 2008 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Ralink
- NAME:=Ralink RT61 Wifi
- PACKAGES:=kmod-rt61-pci hostapd-mini
-endef
-
-$(eval $(call Profile,Ralink))
+++ /dev/null
-ARCH:=mips
-SUBTARGET:=danube
-BOARDNAME:=Danube
-FEATURES:=squashfs jffs2
-DEFAULT_PACKAGES+=lqtapi-firmware-danube
-define Target/Description
- Lantiq Danube
-endef
-
+++ /dev/null
-#!/usr/bin/python
-from sys import stdin, stdout
-while True:
- c = stdin.read(2)
- if len(c) < 2:
- break
- n1, n2 = ord(c[0]), ord(c[1])
- stdout.write(chr(((n2 & 15) << 4) + ((n2 & 240) >> 4)))
- stdout.write(chr(((n1 & 15) << 4) + ((n1 & 240) >> 4)))
+++ /dev/null
-#!/bin/sh
-
-DIR="$1/"
-FILE="$1/$2"
-
-echo "This tool downloads the arcor a800 firmware release and extracts the voip firmware for the danube."
-echo "Please only do so if it is legal in your country"
-
-[ ! -f ${FILE} ] && {
- echo ${FILE} is missing
- exit 1
-}
-
-[ -f ${DIR}/ifxmips_fw_decodev2.tar.bz2 -a ! -f ${DIR}voip_coef.bin ] && {
- [ ! -f ${DIR}decode_ifx_fw && -f ${DIR}ifxmips_fw_decodev2.tar.bz2 ] && {
- tar xjf ${DIR}ifxmips_fw_decodev2.tar.bz2 ifxmips_fw_decode/decode.c -O > ${DIR}decode.c
- gcc -o ${DIR}decode_ifx_fw ${DIR}decode.c
- }
- [ ! -f ${DIR}decode_ifx_fw ] && {
- [ ! -f ${DIR}voip_coef.lzma ] && {
- ${DIR}decode_ifx_fw $FILE ${DIR}voip_coef.lzma
- }
- lzma d ${DIR}voip_coef.lzma ${DIR}voip_coef.bin
- }
-}
-[ ! -f ${DIR}dsl_a.bin ] && {
- dd if=${FILE} of=${DIR}dsl1.lzma bs=1 skip=2168832 count=150724
- lzma d ${DIR}dsl2.lzma ${DIR}dsl_a.bin
-}
-
-[ ! -f ${DIR}dsl_b.bin ] && {
- dd if=${FILE} of=${DIR}dsl2.lzma bs=1 skip=2320384 count=148343
- lzma d ${DIR}dsl1.lzma ${DIR}dsl_b.bin
-}
-
-[ ! -f ${DIR}voip.bin ] && {
- dd if=${FILE} of=${DIR}voip.lzma bs=1 skip=2468864 count=452105
- lzma d ${DIR}voip.lzma ${DIR}voip.bin
-}
-exit 0
-
-# get lzma offsets
-# hexdump -C arcor_A800_452CPW_FW_1.02.206\(20081201\).bin | grep "5d 00 00 80"
-# hexdump -C arcor_A800_452CPW_FW_1.02.206\(20081201\).bin | grep "00 d5 08 00"
+++ /dev/null
-if IFXMIPS
-
-choice
- prompt "Infineon SoC chip selection"
- default SOC_DANUBE
- help
- Select Infineon MIPS SoC type.
-
- config IFXMIPS_DANUBE
- bool "Danube/Twinpass"
- select SOC_DANUBE
-
- config IFXMIPS_ASE
- bool "Amazon-SE"
- select SOC_ASE
-
- config IFXMIPS_AR9
- bool "AR9"
- select SOC_AR9
-
- config IFXMIPS_VR9
- bool "VR9"
- select SOC_VR9
-
-endchoice
-
-source "arch/mips/ifxmips/danube/Kconfig"
-
-config SOC_DANUBE
- bool
- select DMA_NONCOHERENT
- select IRQ_CPU
- select CEVT_R4K
- select CSRC_R4K
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_HAS_CPU_MIPS32_R2
- select HAVE_STD_PC_SERIAL_PORT
- select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_MULTITHREADING
- select SYS_HAS_EARLY_PRINTK
- select HW_HAS_PCI
- select ARCH_REQUIRE_GPIOLIB
- select SWAP_IO_SPACE
- select MIPS_MACHINE
-
-config SOC_ASE
- bool
- select DMA_NONCOHERENT
- select IRQ_CPU
- select CEVT_R4K
- select CSRC_R4K
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_HAS_CPU_MIPS32_R2
- select HAVE_STD_PC_SERIAL_PORT
- select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_MULTITHREADING
- select SYS_HAS_EARLY_PRINTK
- select HW_HAS_PCI
- select ARCH_REQUIRE_GPIOLIB
- select SWAP_IO_SPACE
- select MIPS_MACHINE
-
-config SOC_AR9
- bool
- select DMA_NONCOHERENT
- select IRQ_CPU
- select CEVT_R4K
- select CSRC_R4K
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_HAS_CPU_MIPS32_R2
- select HAVE_STD_PC_SERIAL_PORT
- select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_MULTITHREADING
- select SYS_HAS_EARLY_PRINTK
- select HW_HAS_PCI
- select ARCH_REQUIRE_GPIOLIB
- select SWAP_IO_SPACE
- select MIPS_MACHINE
-
-config SOC_VR9
- bool
- select DMA_NONCOHERENT
- select IRQ_CPU
- select CEVT_R4K
- select CSRC_R4K
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_HAS_CPU_MIPS32_R2
- select HAVE_STD_PC_SERIAL_PORT
- select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_MULTITHREADING
- select SYS_HAS_EARLY_PRINTK
- select HW_HAS_PCI
- select ARCH_REQUIRE_GPIOLIB
- select SWAP_IO_SPACE
- select MIPS_MACHINE
-
-if EARLY_PRINTK
-menu "Infineon SoC settings"
-
-choice
- prompt "Early printk port"
- help
- Choose which serial port is used, until the console driver is loaded
-
-config IFXMIPS_PROM_ASC0
- bool "ASC0"
-
-config IFXMIPS_PROM_ASC1
- bool "ASC1"
-
-endchoice
-
-endmenu
-endif
-
-config IFXMIPS_COMPAT
- bool "Spinacer compatibility"
- default y
- help
- Enable this to get some legacy API. This is needed if you use Lantiq DSL and VOIP drivers.
-endif
+++ /dev/null
-if IFXMIPS_DANUBE
-
-config IFXMIPS_ARCAYDIAN_BRNBOOT
- bool
- default n
-
-menu "Lantiq SoC machine selection"
-
-config DANUBE_MACH_EASY80712
- bool "Easy50812"
- default y
-
-endmenu
-
-endif
+++ /dev/null
-obj-y := dma-core.o irq.o setup.o devices.o cgu.o
-obj-$(CONFIG_DANUBE_MACH_EASY50812) += mach-easy50812.o
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/autoconf.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/mtd/physmap.h>
-#include <linux/kernel.h>
-#include <linux/reboot.h>
-#include <linux/platform_device.h>
-#include <linux/leds.h>
-#include <linux/etherdevice.h>
-#include <linux/reboot.h>
-#include <linux/time.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <asm/bootinfo.h>
-#include <asm/irq.h>
-
-#include <ifxmips.h>
-#include <ifxmips_irq.h>
+++ /dev/null
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/init.h>
-#include <linux/uaccess.h>
-#include <linux/unistd.h>
-#include <linux/errno.h>
-
-#include <asm/irq.h>
-#include <asm/div64.h>
-
-#include <ifxmips.h>
-#include <ifxmips_cgu.h>
-
-void
-cgu_setup_pci_clk(int external_clock)
-{
- /* set clock to 33Mhz */
- ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000,
- IFXMIPS_CGU_IFCCR);
- ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000,
- IFXMIPS_CGU_IFCCR);
- if (external_clock)
- {
- ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~(1 << 16),
- IFXMIPS_CGU_IFCCR);
- ifxmips_w32((1 << 30), IFXMIPS_CGU_PCICR);
- } else {
- ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16),
- IFXMIPS_CGU_IFCCR);
- ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
- }
-}
-
-
+++ /dev/null
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/mtd/physmap.h>
-#include <linux/kernel.h>
-#include <linux/reboot.h>
-#include <linux/platform_device.h>
-#include <linux/leds.h>
-#include <linux/etherdevice.h>
-#include <linux/reboot.h>
-#include <linux/time.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-
-#include <asm/bootinfo.h>
-#include <asm/irq.h>
-
-#include <ifxmips.h>
-#include <ifxmips_irq.h>
-
-/* pci */
-extern int ifxmips_pci_external_clock;
-extern int ifxmips_pci_req_mask;
-
-void __init
-ar9_register_pci(int clock, int irq_mask)
-{
- ifxmips_pci_external_clock = clock;
- if(irq_mask)
- ifxmips_pci_req_mask = irq_mask;
-}
+++ /dev/null
-#ifndef _DANUBE_DEVICES_H__
-#define _DANUBE_DEVICES_H__
-
-#include "../common/devices.h"
-
-enum {
- PCI_CLOCK_INT = 0,
- PCI_CLOCK_EXT
-};
-
-void __init ar9_register_usb(void);
-void __init ar9_register_ebu_gpio(struct resource *resource, u32 value);
-void __init ar9_register_ethernet(unsigned char *mac);
-void __init ar9_register_pci(int clock, int irq_mask);
-
-#endif
+++ /dev/null
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/timer.h>
-#include <linux/fs.h>
-#include <linux/errno.h>
-#include <linux/stat.h>
-#include <linux/mm.h>
-#include <linux/tty.h>
-#include <linux/selection.h>
-#include <linux/kmod.h>
-#include <linux/vmalloc.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/uaccess.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-
-#include <ifxmips.h>
-#include <ifxmips_irq.h>
-#include <ifxmips_dma.h>
-#include <ifxmips_pmu.h>
-
-/*25 descriptors for each dma channel,4096/8/20=25.xx*/
-#define IFXMIPS_DMA_DESCRIPTOR_OFFSET 25
-
-#define MAX_DMA_DEVICE_NUM 6 /*max ports connecting to dma */
-#define MAX_DMA_CHANNEL_NUM 20 /*max dma channels */
-#define DMA_INT_BUDGET 100 /*budget for interrupt handling */
-#define DMA_POLL_COUNTER 4 /*fix me, set the correct counter value here! */
-
-extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);
-extern void ifxmips_enable_irq(unsigned int irq_nr);
-extern void ifxmips_disable_irq(unsigned int irq_nr);
-
-u64 *g_desc_list;
-struct dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
-struct dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM];
-
-static const char *global_device_name[MAX_DMA_DEVICE_NUM] =
- { "PPE", "DEU", "SPI", "SDIO", "MCTRL0", "MCTRL1" };
-
-struct dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
- {"PPE", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH0_INT, 0},
- {"PPE", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH1_INT, 0},
- {"PPE", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH2_INT, 1},
- {"PPE", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH3_INT, 1},
- {"PPE", IFXMIPS_DMA_RX, 2, IFXMIPS_DMA_CH4_INT, 2},
- {"PPE", IFXMIPS_DMA_TX, 2, IFXMIPS_DMA_CH5_INT, 2},
- {"PPE", IFXMIPS_DMA_RX, 3, IFXMIPS_DMA_CH6_INT, 3},
- {"PPE", IFXMIPS_DMA_TX, 3, IFXMIPS_DMA_CH7_INT, 3},
- {"DEU", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH8_INT, 0},
- {"DEU", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH9_INT, 0},
- {"DEU", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH10_INT, 1},
- {"DEU", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH11_INT, 1},
- {"SPI", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH12_INT, 0},
- {"SPI", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH13_INT, 0},
- {"SDIO", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH14_INT, 0},
- {"SDIO", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH15_INT, 0},
- {"MCTRL0", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH16_INT, 0},
- {"MCTRL0", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH17_INT, 0},
- {"MCTRL1", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH18_INT, 1},
- {"MCTRL1", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH19_INT, 1}
-};
-
-struct dma_chan_map *chan_map = default_dma_map;
-volatile u32 g_ifxmips_dma_int_status;
-volatile int g_ifxmips_dma_in_process; /* 0=not in process, 1=in process */
-
-void do_dma_tasklet(unsigned long);
-DECLARE_TASKLET(dma_tasklet, do_dma_tasklet, 0);
-
-u8 *common_buffer_alloc(int len, int *byte_offset, void **opt)
-{
- u8 *buffer = kmalloc(len * sizeof(u8), GFP_KERNEL);
-
- *byte_offset = 0;
-
- return buffer;
-}
-
-void common_buffer_free(u8 *dataptr, void *opt)
-{
- kfree(dataptr);
-}
-
-void enable_ch_irq(struct dma_channel_info *pCh)
-{
- int chan_no = (int)(pCh - dma_chan);
- unsigned long flag;
-
- local_irq_save(flag);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- ifxmips_w32(0x4a, IFXMIPS_DMA_CIE);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
- local_irq_restore(flag);
- ifxmips_enable_irq(pCh->irq);
-}
-
-void disable_ch_irq(struct dma_channel_info *pCh)
-{
- unsigned long flag;
- int chan_no = (int) (pCh - dma_chan);
-
- local_irq_save(flag);
- g_ifxmips_dma_int_status &= ~(1 << chan_no);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- ifxmips_w32(0, IFXMIPS_DMA_CIE);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);
- local_irq_restore(flag);
- ifxmips_mask_and_ack_irq(pCh->irq);
-}
-
-void open_chan(struct dma_channel_info *pCh)
-{
- unsigned long flag;
- int chan_no = (int)(pCh - dma_chan);
-
- local_irq_save(flag);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 1, IFXMIPS_DMA_CCTRL);
- if (pCh->dir == IFXMIPS_DMA_RX)
- enable_ch_irq(pCh);
- local_irq_restore(flag);
-}
-
-void close_chan(struct dma_channel_info *pCh)
-{
- unsigned long flag;
- int chan_no = (int) (pCh - dma_chan);
-
- local_irq_save(flag);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
- disable_ch_irq(pCh);
- local_irq_restore(flag);
-}
-
-void reset_chan(struct dma_channel_info *pCh)
-{
- int chan_no = (int) (pCh - dma_chan);
-
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
-}
-
-void rx_chan_intr_handler(int chan_no)
-{
- struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
- struct dma_channel_info *pCh = &dma_chan[chan_no];
- struct rx_desc *rx_desc_p;
- int tmp;
- unsigned long flag;
-
- /*handle command complete interrupt */
- rx_desc_p = (struct rx_desc *)pCh->desc_base + pCh->curr_desc;
- if (rx_desc_p->status.field.OWN == CPU_OWN
- && rx_desc_p->status.field.C
- && rx_desc_p->status.field.data_length < 1536){
- /* Every thing is correct, then we inform the upper layer */
- pDev->current_rx_chan = pCh->rel_chan_no;
- if (pDev->intr_handler)
- pDev->intr_handler(pDev, RCV_INT);
- pCh->weight--;
- } else {
- local_irq_save(flag);
- tmp = ifxmips_r32(IFXMIPS_DMA_CS);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
- ifxmips_w32(tmp, IFXMIPS_DMA_CS);
- g_ifxmips_dma_int_status &= ~(1 << chan_no);
- local_irq_restore(flag);
- ifxmips_enable_irq(dma_chan[chan_no].irq);
- }
-}
-
-inline void tx_chan_intr_handler(int chan_no)
-{
- struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
- struct dma_channel_info *pCh = &dma_chan[chan_no];
- int tmp;
- unsigned long flag;
-
- local_irq_save(flag);
- tmp = ifxmips_r32(IFXMIPS_DMA_CS);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
- ifxmips_w32(tmp, IFXMIPS_DMA_CS);
- g_ifxmips_dma_int_status &= ~(1 << chan_no);
- local_irq_restore(flag);
- pDev->current_tx_chan = pCh->rel_chan_no;
- if (pDev->intr_handler)
- pDev->intr_handler(pDev, TRANSMIT_CPT_INT);
-}
-
-void do_dma_tasklet(unsigned long unused)
-{
- int i;
- int chan_no = 0;
- int budget = DMA_INT_BUDGET;
- int weight = 0;
- unsigned long flag;
-
- while (g_ifxmips_dma_int_status) {
- if (budget-- < 0) {
- tasklet_schedule(&dma_tasklet);
- return;
- }
- chan_no = -1;
- weight = 0;
- for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
- if ((g_ifxmips_dma_int_status & (1 << i)) && dma_chan[i].weight > 0) {
- if (dma_chan[i].weight > weight) {
- chan_no = i;
- weight = dma_chan[chan_no].weight;
- }
- }
- }
-
- if (chan_no >= 0) {
- if (chan_map[chan_no].dir == IFXMIPS_DMA_RX)
- rx_chan_intr_handler(chan_no);
- else
- tx_chan_intr_handler(chan_no);
- } else {
- for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
- dma_chan[i].weight = dma_chan[i].default_weight;
- }
- }
-
- local_irq_save(flag);
- g_ifxmips_dma_in_process = 0;
- if (g_ifxmips_dma_int_status) {
- g_ifxmips_dma_in_process = 1;
- tasklet_schedule(&dma_tasklet);
- }
- local_irq_restore(flag);
-}
-
-irqreturn_t dma_interrupt(int irq, void *dev_id)
-{
- struct dma_channel_info *pCh;
- int chan_no = 0;
- int tmp;
-
- pCh = (struct dma_channel_info *)dev_id;
- chan_no = (int)(pCh - dma_chan);
- if (chan_no < 0 || chan_no > 19)
- BUG();
-
- tmp = ifxmips_r32(IFXMIPS_DMA_IRNEN);
- ifxmips_w32(0, IFXMIPS_DMA_IRNEN);
- g_ifxmips_dma_int_status |= 1 << chan_no;
- ifxmips_w32(tmp, IFXMIPS_DMA_IRNEN);
- ifxmips_mask_and_ack_irq(irq);
-
- if (!g_ifxmips_dma_in_process) {
- g_ifxmips_dma_in_process = 1;
- tasklet_schedule(&dma_tasklet);
- }
-
- return IRQ_HANDLED;
-}
-
-struct dma_device_info *dma_device_reserve(char *dev_name)
-{
- int i;
-
- for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
- if (strcmp(dev_name, dma_devs[i].device_name) == 0) {
- if (dma_devs[i].reserved)
- return NULL;
- dma_devs[i].reserved = 1;
- break;
- }
- }
-
- return &dma_devs[i];
-}
-EXPORT_SYMBOL(dma_device_reserve);
-
-void dma_device_release(struct dma_device_info *dev)
-{
- dev->reserved = 0;
-}
-EXPORT_SYMBOL(dma_device_release);
-
-void dma_device_register(struct dma_device_info *dev)
-{
- int i, j;
- int chan_no = 0;
- u8 *buffer;
- int byte_offset;
- unsigned long flag;
- struct dma_device_info *pDev;
- struct dma_channel_info *pCh;
- struct rx_desc *rx_desc_p;
- struct tx_desc *tx_desc_p;
-
- for (i = 0; i < dev->max_tx_chan_num; i++) {
- pCh = dev->tx_chan[i];
- if (pCh->control == IFXMIPS_DMA_CH_ON) {
- chan_no = (int)(pCh - dma_chan);
- for (j = 0; j < pCh->desc_len; j++) {
- tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
- memset(tx_desc_p, 0, sizeof(struct tx_desc));
- }
- local_irq_save(flag);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- /* check if the descriptor length is changed */
- if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
- ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN);
-
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
- while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2)
- ;
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
- ifxmips_w32(0x30100, IFXMIPS_DMA_CCTRL); /* reset and enable channel,enable channel later */
- local_irq_restore(flag);
- }
- }
-
- for (i = 0; i < dev->max_rx_chan_num; i++) {
- pCh = dev->rx_chan[i];
- if (pCh->control == IFXMIPS_DMA_CH_ON) {
- chan_no = (int)(pCh - dma_chan);
-
- for (j = 0; j < pCh->desc_len; j++) {
- rx_desc_p = (struct rx_desc *)pCh->desc_base + j;
- pDev = (struct dma_device_info *)(pCh->dma_dev);
- buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void *)&(pCh->opt[j]));
- if (!buffer)
- break;
-
- dma_cache_inv((unsigned long) buffer, pCh->packet_size);
-
- rx_desc_p->Data_Pointer = (u32)CPHYSADDR((u32)buffer);
- rx_desc_p->status.word = 0;
- rx_desc_p->status.field.byte_offset = byte_offset;
- rx_desc_p->status.field.OWN = DMA_OWN;
- rx_desc_p->status.field.data_length = pCh->packet_size;
- }
-
- local_irq_save(flag);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- /* check if the descriptor length is changed */
- if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
- ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
- while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2)
- ;
- ifxmips_w32(0x0a, IFXMIPS_DMA_CIE); /* fix me, should enable all the interrupts here? */
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
- ifxmips_w32(0x30000, IFXMIPS_DMA_CCTRL);
- local_irq_restore(flag);
- ifxmips_enable_irq(dma_chan[chan_no].irq);
- }
- }
-}
-EXPORT_SYMBOL(dma_device_register);
-
-void dma_device_unregister(struct dma_device_info *dev)
-{
- int i, j;
- int chan_no;
- struct dma_channel_info *pCh;
- struct rx_desc *rx_desc_p;
- struct tx_desc *tx_desc_p;
- unsigned long flag;
-
- for (i = 0; i < dev->max_tx_chan_num; i++) {
- pCh = dev->tx_chan[i];
- if (pCh->control == IFXMIPS_DMA_CH_ON) {
- chan_no = (int)(dev->tx_chan[i] - dma_chan);
- local_irq_save(flag);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- pCh->curr_desc = 0;
- pCh->prev_desc = 0;
- pCh->control = IFXMIPS_DMA_CH_OFF;
- ifxmips_w32(0, IFXMIPS_DMA_CIE); /* fix me, should disable all the interrupts here? */
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /* disable interrupts */
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
- while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1)
- ;
- local_irq_restore(flag);
-
- for (j = 0; j < pCh->desc_len; j++) {
- tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
- if ((tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C)
- || (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0)) {
- dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), (void *)pCh->opt[j]);
- }
- tx_desc_p->status.field.OWN = CPU_OWN;
- memset(tx_desc_p, 0, sizeof(struct tx_desc));
- }
- /* TODO should free buffer that is not transferred by dma */
- }
- }
-
- for (i = 0; i < dev->max_rx_chan_num; i++) {
- pCh = dev->rx_chan[i];
- chan_no = (int)(dev->rx_chan[i] - dma_chan);
- ifxmips_disable_irq(pCh->irq);
-
- local_irq_save(flag);
- g_ifxmips_dma_int_status &= ~(1 << chan_no);
- pCh->curr_desc = 0;
- pCh->prev_desc = 0;
- pCh->control = IFXMIPS_DMA_CH_OFF;
-
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- ifxmips_w32(0, IFXMIPS_DMA_CIE); /* fix me, should disable all the interrupts here? */
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /* disable interrupts */
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
- while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1)
- ;
-
- local_irq_restore(flag);
- for (j = 0; j < pCh->desc_len; j++) {
- rx_desc_p = (struct rx_desc *) pCh->desc_base + j;
- if ((rx_desc_p->status.field.OWN == CPU_OWN
- && rx_desc_p->status.field.C)
- || (rx_desc_p->status.field.OWN == DMA_OWN
- && rx_desc_p->status.field.data_length > 0)) {
- dev->buffer_free((u8 *)
- __va(rx_desc_p->Data_Pointer),
- (void *) pCh->opt[j]);
- }
- }
- }
-}
-EXPORT_SYMBOL(dma_device_unregister);
-
-int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt)
-{
- u8 *buf;
- int len;
- int byte_offset = 0;
- void *p = NULL;
- struct dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan];
- struct rx_desc *rx_desc_p;
-
- /* get the rx data first */
- rx_desc_p = (struct rx_desc *) pCh->desc_base + pCh->curr_desc;
- if (!(rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C))
- return 0;
-
- buf = (u8 *) __va(rx_desc_p->Data_Pointer);
- *(u32 *)dataptr = (u32)buf;
- len = rx_desc_p->status.field.data_length;
-
- if (opt)
- *(int *)opt = (int)pCh->opt[pCh->curr_desc];
-
- /* replace with a new allocated buffer */
- buf = dma_dev->buffer_alloc(pCh->packet_size, &byte_offset, &p);
-
- if (buf) {
- dma_cache_inv((unsigned long) buf, pCh->packet_size);
- pCh->opt[pCh->curr_desc] = p;
- wmb();
-
- rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buf);
- rx_desc_p->status.word = (DMA_OWN << 31) | ((byte_offset) << 23) | pCh->packet_size;
- wmb();
- } else {
- *(u32 *) dataptr = 0;
- if (opt)
- *(int *) opt = 0;
- len = 0;
- }
-
- /* increase the curr_desc pointer */
- pCh->curr_desc++;
- if (pCh->curr_desc == pCh->desc_len)
- pCh->curr_desc = 0;
-
- return len;
-}
-EXPORT_SYMBOL(dma_device_read);
-
-int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, void *opt)
-{
- unsigned long flag;
- u32 tmp, byte_offset;
- struct dma_channel_info *pCh;
- int chan_no;
- struct tx_desc *tx_desc_p;
- local_irq_save(flag);
-
- pCh = dma_dev->tx_chan[dma_dev->current_tx_chan];
- chan_no = (int)(pCh - (struct dma_channel_info *) dma_chan);
-
- tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
- while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) {
- dma_dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), pCh->opt[pCh->prev_desc]);
- memset(tx_desc_p, 0, sizeof(struct tx_desc));
- pCh->prev_desc = (pCh->prev_desc + 1) % (pCh->desc_len);
- tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
- }
- tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->curr_desc;
- /* Check whether this descriptor is available */
- if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C) {
- /* if not, the tell the upper layer device */
- dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
- local_irq_restore(flag);
- printk(KERN_INFO "%s %d: failed to write!\n", __func__, __LINE__);
-
- return 0;
- }
- pCh->opt[pCh->curr_desc] = opt;
- /* byte offset----to adjust the starting address of the data buffer, should be multiple of the burst length. */
- byte_offset = ((u32) CPHYSADDR((u32) dataptr)) % ((dma_dev->tx_burst_len) * 4);
- dma_cache_wback((unsigned long) dataptr, len);
- wmb();
- tx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) dataptr) - byte_offset;
- wmb();
- tx_desc_p->status.word = (DMA_OWN << 31) | DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | ((byte_offset) << 23) | len;
- wmb();
-
- pCh->curr_desc++;
- if (pCh->curr_desc == pCh->desc_len)
- pCh->curr_desc = 0;
-
- /*Check whether this descriptor is available */
- tx_desc_p = (struct tx_desc *) pCh->desc_base + pCh->curr_desc;
- if (tx_desc_p->status.field.OWN == DMA_OWN) {
- /*if not , the tell the upper layer device */
- dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
- }
-
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- tmp = ifxmips_r32(IFXMIPS_DMA_CCTRL);
-
- if (!(tmp & 1))
- pCh->open(pCh);
-
- local_irq_restore(flag);
-
- return len;
-}
-EXPORT_SYMBOL(dma_device_write);
-
-int map_dma_chan(struct dma_chan_map *map)
-{
- int i, j;
- int result;
-
- for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
- strcpy(dma_devs[i].device_name, global_device_name[i]);
-
- for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
- dma_chan[i].irq = map[i].irq;
- result = request_irq(dma_chan[i].irq, dma_interrupt, IRQF_DISABLED, map[i].dev_name, (void *)&dma_chan[i]);
- if (result) {
- printk(KERN_WARNING "error, cannot get dma_irq!\n");
- free_irq(dma_chan[i].irq, (void *) &dma_interrupt);
-
- return -EFAULT;
- }
- }
-
- for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
- dma_devs[i].num_tx_chan = 0; /*set default tx channel number to be one */
- dma_devs[i].num_rx_chan = 0; /*set default rx channel number to be one */
- dma_devs[i].max_rx_chan_num = 0;
- dma_devs[i].max_tx_chan_num = 0;
- dma_devs[i].buffer_alloc = &common_buffer_alloc;
- dma_devs[i].buffer_free = &common_buffer_free;
- dma_devs[i].intr_handler = NULL;
- dma_devs[i].tx_burst_len = 4;
- dma_devs[i].rx_burst_len = 4;
- if (i == 0) {
- ifxmips_w32(0, IFXMIPS_DMA_PS);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), IFXMIPS_DMA_PCTRL); /*enable dma drop */
- }
-
- if (i == 1) {
- ifxmips_w32(1, IFXMIPS_DMA_PS);
- ifxmips_w32(0x14, IFXMIPS_DMA_PCTRL); /*deu port setting */
- }
-
- for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
- dma_chan[j].byte_offset = 0;
- dma_chan[j].open = &open_chan;
- dma_chan[j].close = &close_chan;
- dma_chan[j].reset = &reset_chan;
- dma_chan[j].enable_irq = &enable_ch_irq;
- dma_chan[j].disable_irq = &disable_ch_irq;
- dma_chan[j].rel_chan_no = map[j].rel_chan_no;
- dma_chan[j].control = IFXMIPS_DMA_CH_OFF;
- dma_chan[j].default_weight = IFXMIPS_DMA_CH_DEFAULT_WEIGHT;
- dma_chan[j].weight = dma_chan[j].default_weight;
- dma_chan[j].curr_desc = 0;
- dma_chan[j].prev_desc = 0;
- }
-
- for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
- if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0) {
- if (map[j].dir == IFXMIPS_DMA_RX) {
- dma_chan[j].dir = IFXMIPS_DMA_RX;
- dma_devs[i].max_rx_chan_num++;
- dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j];
- dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri;
- dma_chan[j].dma_dev = (void *)&dma_devs[i];
- } else if (map[j].dir == IFXMIPS_DMA_TX) {
- /*TX direction */
- dma_chan[j].dir = IFXMIPS_DMA_TX;
- dma_devs[i].max_tx_chan_num++;
- dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j];
- dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri;
- dma_chan[j].dma_dev = (void *)&dma_devs[i];
- } else {
- printk(KERN_WARNING "WRONG DMA MAP!\n");
- }
- }
- }
- }
-
- return 0;
-}
-
-void dma_chip_init(void)
-{
- int i;
-
- /* enable DMA from PMU */
- ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
-
- /* reset DMA */
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CTRL) | 1, IFXMIPS_DMA_CTRL);
-
- /* disable all interrupts */
- ifxmips_w32(0, IFXMIPS_DMA_IRNEN);
-
- for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
- ifxmips_w32(i, IFXMIPS_DMA_CS);
- ifxmips_w32(0x2, IFXMIPS_DMA_CCTRL);
- ifxmips_w32(0x80000040, IFXMIPS_DMA_CPOLL);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~0x1, IFXMIPS_DMA_CCTRL);
- }
-}
-
-int ifxmips_dma_init(void)
-{
- int i;
-
- dma_chip_init();
- if (map_dma_chan(default_dma_map))
- BUG();
-
- g_desc_list = (u64 *)KSEG1ADDR(__get_free_page(GFP_DMA));
-
- if (g_desc_list == NULL) {
- printk(KERN_WARNING "no memory for desriptor\n");
- return -ENOMEM;
- }
-
- memset(g_desc_list, 0, PAGE_SIZE);
-
- for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
- dma_chan[i].desc_base = (u32)g_desc_list + i * IFXMIPS_DMA_DESCRIPTOR_OFFSET * 8;
- dma_chan[i].curr_desc = 0;
- dma_chan[i].desc_len = IFXMIPS_DMA_DESCRIPTOR_OFFSET;
-
- ifxmips_w32(i, IFXMIPS_DMA_CS);
- ifxmips_w32((u32)CPHYSADDR(dma_chan[i].desc_base), IFXMIPS_DMA_CDBA);
- ifxmips_w32(dma_chan[i].desc_len, IFXMIPS_DMA_CDLEN);
- }
-
- return 0;
-}
-
-arch_initcall(ifxmips_dma_init);
-
-void dma_cleanup(void)
-{
- int i;
-
- free_page(KSEG0ADDR((unsigned long) g_desc_list));
- for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
- free_irq(dma_chan[i].irq, (void *)&dma_interrupt);
-}
-
-MODULE_LICENSE("GPL");
+++ /dev/null
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-
-#include <asm/bootinfo.h>
-#include <asm/irq.h>
-#include <asm/irq_cpu.h>
-
-#include <ifxmips.h>
-#include <ifxmips_irq.h>
-
-void
-ifxmips_disable_irq(unsigned int irq_nr)
-{
- int i;
- u32 *ier = IFXMIPS_ICU_IM0_IER;
-
- irq_nr -= INT_NUM_IRQ0;
- for (i = 0; i <= 4; i++)
- {
- if (irq_nr < INT_NUM_IM_OFFSET)
- {
- ifxmips_w32(ifxmips_r32(ier) & ~(1 << irq_nr), ier);
- return;
- }
- ier += IFXMIPS_ICU_OFFSET;
- irq_nr -= INT_NUM_IM_OFFSET;
- }
-}
-EXPORT_SYMBOL(ifxmips_disable_irq);
-
-void
-ifxmips_mask_and_ack_irq(unsigned int irq_nr)
-{
- int i;
- u32 *ier = IFXMIPS_ICU_IM0_IER;
- u32 *isr = IFXMIPS_ICU_IM0_ISR;
-
- irq_nr -= INT_NUM_IRQ0;
- for (i = 0; i <= 4; i++)
- {
- if (irq_nr < INT_NUM_IM_OFFSET)
- {
- ifxmips_w32(ifxmips_r32(ier) & ~(1 << irq_nr), ier);
- ifxmips_w32((1 << irq_nr), isr);
- return;
- }
- ier += IFXMIPS_ICU_OFFSET;
- isr += IFXMIPS_ICU_OFFSET;
- irq_nr -= INT_NUM_IM_OFFSET;
- }
-}
-EXPORT_SYMBOL(ifxmips_mask_and_ack_irq);
-
-void
-ifxmips_enable_irq(unsigned int irq_nr)
-{
- int i;
- u32 *ier = IFXMIPS_ICU_IM0_IER;
-
- irq_nr -= INT_NUM_IRQ0;
- for (i = 0; i <= 4; i++)
- {
- if (irq_nr < INT_NUM_IM_OFFSET)
- {
- ifxmips_w32(ifxmips_r32(ier) | (1 << irq_nr), ier);
- return;
- }
- ier += IFXMIPS_ICU_OFFSET;
- irq_nr -= INT_NUM_IM_OFFSET;
- }
-}
-EXPORT_SYMBOL(ifxmips_enable_irq);
-
-static unsigned int
-ifxmips_startup_irq(unsigned int irq)
-{
- ifxmips_enable_irq(irq);
- return 0;
-}
-
-static void
-ifxmips_end_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
- ifxmips_enable_irq(irq);
-}
-
-static struct irq_chip
-ifxmips_irq_type = {
- "ifxmips",
- .startup = ifxmips_startup_irq,
- .enable = ifxmips_enable_irq,
- .disable = ifxmips_disable_irq,
- .unmask = ifxmips_enable_irq,
- .ack = ifxmips_end_irq,
- .mask = ifxmips_disable_irq,
- .mask_ack = ifxmips_mask_and_ack_irq,
- .end = ifxmips_end_irq,
-};
-
-/* silicon bug causes only the msb set to 1 to be valid. all
- other bits might be bogus */
-static inline int
-ls1bit32(unsigned long x)
-{
- __asm__ (
- ".set push \n"
- ".set mips32 \n"
- "clz %0, %1 \n"
- ".set pop \n"
- : "=r" (x)
- : "r" (x));
- return 31 - x;
-}
-
-static void
-ifxmips_hw_irqdispatch(int module)
-{
- u32 irq;
-
- irq = ifxmips_r32(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
- if (irq == 0)
- return;
-
- /* we need to do this due to a silicon bug */
- irq = ls1bit32(irq);
- do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
-
- if ((irq == 22) && (module == 0))
- ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10,
- IFXMIPS_EBU_PCC_ISTAT);
-}
-
-#ifdef CONFIG_CPU_MIPSR2_IRQ_VI
-#define DEFINE_HWx_IRQDISPATCH(x) \
-static void ifxmips_hw ## x ## _irqdispatch(void)\
-{\
- ifxmips_hw_irqdispatch(x); \
-}
-static void ifxmips_hw5_irqdispatch(void)
-{
- do_IRQ(MIPS_CPU_TIMER_IRQ);
-}
-DEFINE_HWx_IRQDISPATCH(0)
-DEFINE_HWx_IRQDISPATCH(1)
-DEFINE_HWx_IRQDISPATCH(2)
-DEFINE_HWx_IRQDISPATCH(3)
-DEFINE_HWx_IRQDISPATCH(4)
-/*DEFINE_HWx_IRQDISPATCH(5)*/
-#endif /* #ifdef CONFIG_CPU_MIPSR2_IRQ_VI */
-
-asmlinkage void
-plat_irq_dispatch(void)
-{
- unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
- unsigned int i;
-
- if (pending & CAUSEF_IP7)
- {
- do_IRQ(MIPS_CPU_TIMER_IRQ);
- goto out;
- } else {
- for (i = 0; i < 5; i++)
- {
- if (pending & (CAUSEF_IP2 << i))
- {
- ifxmips_hw_irqdispatch(i);
- goto out;
- }
- }
- }
- printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
-
-out:
- return;
-}
-
-static struct irqaction
-cascade = {
- .handler = no_action,
- .flags = IRQF_DISABLED,
- .name = "cascade",
-};
-
-void __init
-arch_init_irq(void)
-{
- int i;
-
- for (i = 0; i < 5; i++)
- ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
-
- mips_cpu_irq_init();
-
- for (i = 2; i <= 6; i++)
- setup_irq(i, &cascade);
-
-#ifdef CONFIG_CPU_MIPSR2_IRQ_VI
- if (cpu_has_vint) {
- printk(KERN_INFO "Setting up vectored interrupts\n");
- set_vi_handler(2, ifxmips_hw0_irqdispatch);
- set_vi_handler(3, ifxmips_hw1_irqdispatch);
- set_vi_handler(4, ifxmips_hw2_irqdispatch);
- set_vi_handler(5, ifxmips_hw3_irqdispatch);
- set_vi_handler(6, ifxmips_hw4_irqdispatch);
- set_vi_handler(7, ifxmips_hw5_irqdispatch);
- }
-#endif
-
- for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
- set_irq_chip_and_handler(i, &ifxmips_irq_type,
- handle_level_irq);
-
- #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
- set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
- IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
- #else
- set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
- IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
- #endif
-}
-
-void __cpuinit
-arch_fixup_c0_irqs(void)
-{
- /* FIXME: check for CPUID and only do fix for specific chips/versions */
- cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
- cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
-}
+++ /dev/null
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/gpio_buttons.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/input.h>
-
-#include <machine.h>
-#include <ifxmips_prom.h>
-
-#include "arcaydian.h"
-#include "devices.h"
-
-#define ARV452_EBU_GPIO_START 0x14000000
-#define ARV452_EBU_GPIO_SIZE 0x00001000
-
-#define ARV452_GPIO_BUTTON_RESET 14
-#define ARV452_BUTTONS_POLL_INTERVAL 20
-
-#define ARV452_LATCH_SWITCH (1 << 10)
-
-#ifdef CONFIG_MTD_PARTITIONS
-static struct mtd_partition arv452_partitions[] =
-{
- {
- .name = "uboot",
- .offset = 0x0,
- .size = 0x20000,
- },
- {
- .name = "uboot_env",
- .offset = 0x20000,
- .size = 0x0,
- },
- {
- .name = "kernel",
- .offset = 0x0,
- .size = 0x0,
- },
- {
- .name = "rootfs",
- .offset = 0x0,
- .size = 0x0,
- },
- {
- .name = "board_config",
- .offset = 0x3f0000,
- .size = 0x10000,
- },
- {
- .name = "openwrt",
- .offset = 0x0,
- .size = 0x0,
- },
-};
-#endif
-
-static struct physmap_flash_data arv452_flash_data = {
-#ifdef CONFIG_MTD_PARTITIONS
- .nr_parts = ARRAY_SIZE(arv452_partitions),
- .parts = arv452_partitions,
-#endif
-};
-
-static struct gpio_led
-arv452_leds_gpio[] __initdata = {
-/*
- { .name = "ifx0", .gpio = 0, .active_low = 1, },
- { .name = "ifx1", .gpio = 1, .active_low = 1, },
- { .name = "ifx2", .gpio = 2, .active_low = 1, },
-*/
- { .name = "ifx:blue:power", .gpio = 3, .active_low = 1, },
- { .name = "ifx:blue:adsl", .gpio = 4, .active_low = 1, },
- { .name = "ifx:blue:internet", .gpio = 5, .active_low = 1, },
- { .name = "ifx:red:power", .gpio = 6, .active_low = 1, },
- { .name = "ifx:yello:wps", .gpio = 7, .active_low = 1, },
- { .name = "ifx:red:wps", .gpio = 9, .active_low = 1, },
-/*
- { .name = "ifx10", .gpio = 10, .active_low = 1, },
- { .name = "ifx11", .gpio = 11, .active_low = 1, },
- { .name = "ifx12", .gpio = 12, .active_low = 1, },
- { .name = "ifx13", .gpio = 13, .active_low = 1, },
- { .name = "ifx14", .gpio = 14, .active_low = 1, },
- { .name = "ifx15", .gpio = 15, .active_low = 1, },
- { .name = "ifx16", .gpio = 16, .active_low = 1, },
- { .name = "ifx17", .gpio = 17, .active_low = 1, },
- { .name = "ifx18", .gpio = 18, .active_low = 1, },
- { .name = "ifx19", .gpio = 19, .active_low = 1, },
- { .name = "ifx20", .gpio = 20, .active_low = 1, },
- { .name = "ifx21", .gpio = 21, .active_low = 1, },
- { .name = "ifx22", .gpio = 22, .active_low = 1, },
- { .name = "ifx23", .gpio = 23, .active_low = 1, },
- { .name = "ifx24", .gpio = 24, .active_low = 1, },
- { .name = "ifx25", .gpio = 25, .active_low = 1, },
- { .name = "ifx26", .gpio = 26, .active_low = 1, },
- { .name = "ifx27", .gpio = 27, .active_low = 1, },
- { .name = "ifx28", .gpio = 28, .active_low = 1, },
- { .name = "ifx29", .gpio = 29, .active_low = 1, },
- { .name = "ifx30", .gpio = 30, .active_low = 1, },
- { .name = "ifx31", .gpio = 31, .active_low = 1, },
-*/
- { .name = "ifx:blue:voip", .gpio = 32, .active_low = 1, },
- { .name = "ifx:blue:fxs1", .gpio = 33, .active_low = 1, },
- { .name = "ifx:blue:fxs2", .gpio = 34, .active_low = 1, },
- { .name = "ifx:blue:fxo", .gpio = 35, .active_low = 1, },
- { .name = "ifx:blue:voice", .gpio = 36, .active_low = 1, },
- { .name = "ifx:blue:usb", .gpio = 37, .active_low = 1, },
- { .name = "ifx:blue:wlan", .gpio = 38, .active_low = 1, },
-/* { .name = "ifx39", .gpio = 39, .active_low = 1, },
- { .name = "ifx40", .gpio = 40, .active_low = 1, },
- { .name = "ifx41", .gpio = 41, .active_low = 1, },
- { .name = "ifx42", .gpio = 42, .active_low = 1, },
- { .name = "ifx43", .gpio = 43, .active_low = 1, },
- { .name = "ifx44", .gpio = 44, .active_low = 1, },
- { .name = "ifx45", .gpio = 45, .active_low = 1, },
- { .name = "ifx46", .gpio = 46, .active_low = 1, },
- { .name = "ifx47", .gpio = 47, .active_low = 1, },
-*/
-};
-
-static struct gpio_button
-arv452_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = BTN_0,
- .threshold = 3,
- .gpio = ARV452_GPIO_BUTTON_RESET,
- .active_low = 1,
- }
-};
-
-static struct resource arv452_ebu_resource =
-{
- .name = "ebu-gpio",
- .start = ARV452_EBU_GPIO_START,
- .end = ARV452_EBU_GPIO_START + ARV452_EBU_GPIO_SIZE - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static void __init
-arv452_init(void)
-{
- unsigned char mac[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
- ifxmips_find_brn_mac(mac);
-
- ifxmips_register_gpio();
-
- ar9_register_ebu_gpio(&arv452_ebu_resource, ARV452_LATCH_SWITCH);
-
- ifxmips_register_mtd(&arv452_flash_data);
-
- ar9_register_pci(PCI_CLOCK_EXT, 0);
-
- ifxmips_register_wdt();
-
- ifxmips_register_gpio_leds(arv452_leds_gpio, ARRAY_SIZE(arv452_leds_gpio));
-
- ar9_register_ethernet(mac);
-
- ar9_register_usb();
-}
-
-MIPS_MACHINE(IFXMIPS_MACH_ARV452,
- "ARV452",
- "Airties WAV-281, Arcor A800",
- arv452_init);
+++ /dev/null
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/gpio_buttons.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/input.h>
-
-#include <machine.h>
-#include <ifxmips_prom.h>
-
-#include "devices.h"
-
-extern unsigned char ifxmips_ethaddr[6];
-
-#ifdef CONFIG_MTD_PARTITIONS
-static struct mtd_partition easy50812_partitions[] =
-{
- {
- .name = "uboot",
- .offset = 0x0,
- .size = 0x40000,
- },
- {
- .name = "uboot_env",
- .offset = 0x40000,
- .size = 0x10000,
- },
- {
- .name = "kernel",
- .offset = 0x0,
- .size = 0x0,
- },
- {
- .name = "rootfs",
- .offset = 0x0,
- .size = 0x0,
- }
-};
-#endif
-
-static struct physmap_flash_data easy50812_flash_data = {
-#ifdef CONFIG_MTD_PARTITIONS
- .nr_parts = ARRAY_SIZE(easy50812_partitions),
- .parts = easy50812_partitions,
-#endif
-};
-
-static struct gpio_led easy50812_leds[] = {
- { .name = "ifx:green:test0", .gpio = 0,},
- { .name = "ifx:green:test1", .gpio = 1,},
- { .name = "ifx:green:test2", .gpio = 2,},
- { .name = "ifx:green:test3", .gpio = 3,},
-};
-
-static void __init
-easy50812_init(void)
-{
- ifxmips_register_gpio();
-
- ifxmips_register_mtd(&easy50812_flash_data);
-
- ifxmips_register_leds(easy50812_leds, ARRAY_SIZE(easy50812_leds));
-
- ifxmips_register_wdt();
-
- ar9_register_ethernet(ifxmips_ethaddr);
-
- ar9_register_usb();
-}
-
-MIPS_MACHINE(IFXMIPS_MACH_EASY50812,
- "EASY50812",
- "Lantiq AR9 Eval Board",
- easy50812_init);
+++ /dev/null
-#include <linux/cpu.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/pm.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <asm/reboot.h>
-#include <asm/system.h>
-#include <ifxmips.h>
-#include <ifxmips_cgu.h>
-
-#define SYSTEM_AR9 "AR9"
-#define SYSTEM_AR9_CHIPID1 0x00129083
-#define SYSTEM_AR9_CHIPID2 0x0012B083
-
-static unsigned int chiprev = 0;
-unsigned char ifxmips_sys_type[IFXMIPS_SYS_TYPE_LEN];
-
-unsigned int
-ifxmips_get_cpu_ver(void)
-{
- return (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0xF0000000) >> 28;
-}
-EXPORT_SYMBOL(ifxmips_get_cpu_ver);
-
-const char*
-get_system_type(void)
-{
- return ifxmips_sys_type;
-}
-
-static void
-ifxmips_machine_restart(char *command)
-{
- printk(KERN_NOTICE "System restart\n");
- local_irq_disable();
- ifxmips_w32(ifxmips_r32(IFXMIPS_RCU_RST) | IFXMIPS_RCU_RST_ALL,
- IFXMIPS_RCU_RST);
- for(;;);
-}
-
-static void
-ifxmips_machine_halt(void)
-{
- printk(KERN_NOTICE "System halted.\n");
- local_irq_disable();
- for(;;);
-}
-
-static void
-ifxmips_machine_power_off(void)
-{
- printk(KERN_NOTICE "Please turn off the power now.\n");
- local_irq_disable();
- for(;;);
-}
-
-static inline u16 get_chip_partnum(void)
-{
- return (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0x0FFFF000) >> 12;
-}
-
-void __init
-ifxmips_soc_setup(void)
-{
- char *name = SYSTEM_AR9;
- ioport_resource.start = IOPORT_RESOURCE_START;
- ioport_resource.end = IOPORT_RESOURCE_END;
- iomem_resource.start = IOMEM_RESOURCE_START;
- iomem_resource.end = IOMEM_RESOURCE_END;
-
- _machine_restart = ifxmips_machine_restart;
- _machine_halt = ifxmips_machine_halt;
- pm_power_off = ifxmips_machine_power_off;
-
- switch (get_chip_partnum())
- {
- case 0x16C:
- name = "ARX188";
- break;
- case 0x16D:
- name = "ARX168";
- break;
- case 0x16F:
- name = "ARX182";
- break;
- case 0x170:
- name = "GRX188";
- break;
- case 0x171:
- name = "GRX168";
- break;
- default:
- printk(KERN_ERR "This is not a AR9 chiprev : 0x%08X\n", get_chip_partnum());
- BUG();
- break;
- }
-
- snprintf(ifxmips_sys_type, IFXMIPS_SYS_TYPE_LEN - 1, "%s rev1.%d %dMhz",
- name, ifxmips_get_cpu_ver(),
- ifxmips_get_cpu_hz() / 1000000);
- ifxmips_sys_type[IFXMIPS_SYS_TYPE_LEN - 1] = '\0';
-}
+++ /dev/null
-obj-y := gpio.o pmu.o prom.o setup.o devices.o
-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+++ /dev/null
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/mtd/physmap.h>
-#include <linux/kernel.h>
-#include <linux/reboot.h>
-#include <linux/platform_device.h>
-#include <linux/leds.h>
-#include <linux/etherdevice.h>
-#include <linux/reboot.h>
-#include <linux/time.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-
-#include <asm/bootinfo.h>
-#include <asm/irq.h>
-
-#include <ifxmips.h>
-#include <ifxmips_irq.h>
-
-/* gpio leds */
-#ifdef CONFIG_LEDS_GPIO
-static struct gpio_led_platform_data ifxmips_gpio_led_data;
-
-static struct platform_device ifxmips_gpio_leds =
-{
- .name = "leds-gpio",
- .dev = {
- .platform_data = (void *) &ifxmips_gpio_led_data,
- }
-};
-
-void __init
-ifxmips_register_gpio_leds(struct gpio_led *leds, int cnt)
-{
- ifxmips_gpio_led_data.leds = leds;
- ifxmips_gpio_led_data.num_leds = cnt;
- platform_device_register(&ifxmips_gpio_leds);
-}
-#endif
-
-/* leds */
-static struct gpio_led_platform_data ifxmips_led_data;
-
-static struct platform_device ifxmips_led =
-{
- .name = "ifxmips_led",
- .dev = {
- .platform_data = (void *) &ifxmips_led_data,
- }
-};
-
-void __init
-ifxmips_register_leds(struct gpio_led *leds, int cnt)
-{
- ifxmips_led_data.leds = leds;
- ifxmips_led_data.num_leds = cnt;
- platform_device_register(&ifxmips_led);
-}
-
-/* mtd flash */
-static struct resource ifxmips_mtd_resource =
-{
- .start = IFXMIPS_FLASH_START,
- .end = IFXMIPS_FLASH_START + IFXMIPS_FLASH_MAX - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ifxmips_mtd =
-{
- .name = "ifxmips_mtd",
- .resource = &ifxmips_mtd_resource,
- .num_resources = 1,
-};
-
-void __init
-ifxmips_register_mtd(struct physmap_flash_data *pdata)
-{
- ifxmips_mtd.dev.platform_data = pdata;
- platform_device_register(&ifxmips_mtd);
-}
-
-/* watchdog */
-static struct resource ifxmips_wdt_resource =
-{
- .start = IFXMIPS_WDT_BASE_ADDR,
- .end = IFXMIPS_WDT_BASE_ADDR + IFXMIPS_WDT_SIZE - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ifxmips_wdt =
-{
- .name = "ifxmips_wdt",
- .resource = &ifxmips_wdt_resource,
- .num_resources = 1,
-};
-
-void __init
-ifxmips_register_wdt(void)
-{
- platform_device_register(&ifxmips_wdt);
-}
-
-/* gpio */
-static struct platform_device ifxmips_gpio0 =
-{
- .name = "ifxmips_gpio",
-};
-
-static struct platform_device ifxmips_gpio1 =
-{
- .name = "ifxmips_gpio1",
-};
-
-void __init
-ifxmips_register_gpio(void)
-{
- platform_device_register(&ifxmips_gpio0);
- platform_device_register(&ifxmips_gpio1);
-}
+++ /dev/null
-#ifndef _IFXMIPS_DEVICES_H__
-#define _IFXMIPS_DEVICES_H__
-
-#include <ifxmips_platform.h>
-
-void __init ifxmips_register_gpio_leds(struct gpio_led *leds, int cnt);
-void __init ifxmips_register_leds(struct gpio_led *leds, int cnt);
-void __init ifxmips_register_mtd(struct physmap_flash_data *pdata);
-void __init ifxmips_register_wdt(void);
-void __init ifxmips_register_gpio(void);
-
-#endif
+++ /dev/null
-#include <linux/init.h>
-#include <linux/cpu.h>
-
-#include <ifxmips.h>
-
-#ifdef CONFIG_IFXMIPS_PROM_ASC0
-#define IFXMIPS_ASC_DIFF 0
-#else
-#define IFXMIPS_ASC_DIFF IFXMIPS_ASC_BASE_DIFF
-#endif
-
-static char buf[1024];
-
-static inline u32
-asc_r32(unsigned long r)
-{
- return ifxmips_r32((u32 *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_DIFF + r));
-}
-
-static inline void
-asc_w32(u32 v, unsigned long r)
-{
- ifxmips_w32(v, (u32 *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_DIFF + r));
-}
-
-void
-prom_putchar(char c)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- while ((asc_r32(IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
-
- if (c == '\n')
- asc_w32('\r', IFXMIPS_ASC_TBUF);
- asc_w32(c, IFXMIPS_ASC_TBUF);
- local_irq_restore(flags);
-}
-
-void
-early_printf(const char *fmt, ...)
-{
- va_list args;
- int l;
- char *p, *buf_end;
-
- va_start(args, fmt);
- l = vsprintf(buf, fmt, args);
- va_end(args);
- buf_end = buf + l;
-
- for (p = buf; p < buf_end; p++)
- prom_putchar(*p);
-}
-
-
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2004 btxu Generate from INCA-IP project
- * Copyright (C) 2005 Jin-Sze.Sow Comments edited
- * Copyright (C) 2006 Huang Xiaogang Modification & verification on Danube chip
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/proc_fs.h>
-#include <linux/init.h>
-#include <linux/ioctl.h>
-#include <linux/timer.h>
-#include <linux/module.h>
-#include <linux/timer.h>
-#include <linux/interrupt.h>
-#include <linux/kobject.h>
-#include <linux/workqueue.h>
-#include <linux/skbuff.h>
-#include <linux/netlink.h>
-#include <linux/platform_device.h>
-#include <linux/uaccess.h>
-#include <linux/semaphore.h>
-#include <linux/gpio.h>
-
-#include <net/sock.h>
-
-#include <ifxmips.h>
-
-#define MAX_PORTS 2
-#define PINS_PER_PORT 16
-
-#define IFXMIPS_GPIO_SANITY {if (port > MAX_PORTS || pin > PINS_PER_PORT) return -EINVAL; }
-
-#define GPIO_TO_PORT(x) ((x > 15) ? (1) : (0))
-#define GPIO_TO_GPIO(x) ((x > 15) ? (x - 16) : (x))
-
-int
-ifxmips_port_reserve_pin(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- printk(KERN_INFO "%s : call to obseleted function\n", __func__);
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_reserve_pin);
-
-int
-ifxmips_port_free_pin(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- printk(KERN_INFO "%s : call to obseleted function\n", __func__);
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_free_pin);
-
-int
-ifxmips_port_set_open_drain(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) | (1 << pin),
- IFXMIPS_GPIO_P0_OD + (port * 0xC));
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_set_open_drain);
-
-int
-ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) & ~(1 << pin),
- IFXMIPS_GPIO_P0_OD + (port * 0xC));
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_clear_open_drain);
-
-int
-ifxmips_port_set_pudsel(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) | (1 << pin),
- IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_set_pudsel);
-
-int
-ifxmips_port_clear_pudsel(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) & ~(1 << pin),
- IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_clear_pudsel);
-
-int
-ifxmips_port_set_puden(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) | (1 << pin),
- IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_set_puden);
-
-int
-ifxmips_port_clear_puden(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) & ~(1 << pin),
- IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_clear_puden);
-
-int
-ifxmips_port_set_stoff(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) | (1 << pin),
- IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_set_stoff);
-
-int
-ifxmips_port_clear_stoff(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) & ~(1 << pin),
- IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_clear_stoff);
-
-int
-ifxmips_port_set_dir_out(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) | (1 << pin),
- IFXMIPS_GPIO_P0_DIR + (port * 0xC));
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_set_dir_out);
-
-int
-ifxmips_port_set_dir_in(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) & ~(1 << pin),
- IFXMIPS_GPIO_P0_DIR + (port * 0xC));
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_set_dir_in);
-
-int
-ifxmips_port_set_output(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) | (1 << pin),
- IFXMIPS_GPIO_P0_OUT + (port * 0xC));
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_set_output);
-
-int
-ifxmips_port_clear_output(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) & ~(1 << pin),
- IFXMIPS_GPIO_P0_OUT + (port * 0xC));
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_clear_output);
-
-int
-ifxmips_port_get_input(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- if (ifxmips_r32(IFXMIPS_GPIO_P0_IN + (port * 0xC)) & (1 << pin))
- return 0;
- else
- return 1;
-}
-EXPORT_SYMBOL(ifxmips_port_get_input);
-
-int
-ifxmips_port_set_altsel0(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) | (1 << pin),
- IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_set_altsel0);
-
-int
-ifxmips_port_clear_altsel0(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) & ~(1 << pin),
- IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_clear_altsel0);
-
-int
-ifxmips_port_set_altsel1(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) | (1 << pin),
- IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_set_altsel1);
-
-int
-ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin)
-{
- IFXMIPS_GPIO_SANITY;
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) & ~(1 << pin),
- IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_port_clear_altsel1);
-
-static void
-ifxmips_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
-{
- int port = GPIO_TO_PORT(offset);
- int gpio = GPIO_TO_GPIO(offset);
- if(value)
- ifxmips_port_set_output(port, gpio);
- else
- ifxmips_port_clear_output(port, gpio);
-}
-
-static int
-ifxmips_gpio_get(struct gpio_chip *chip, unsigned int offset)
-{
- int port = GPIO_TO_PORT(offset);
- int gpio = GPIO_TO_GPIO(offset);
- return ifxmips_port_get_input(port, gpio);
-}
-
-static int
-ifxmips_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
-{
- int port = GPIO_TO_PORT(offset);
- int gpio = GPIO_TO_GPIO(offset);
- ifxmips_port_set_open_drain(port, gpio);
- ifxmips_port_clear_altsel0(port, gpio);
- ifxmips_port_clear_altsel1(port, gpio);
- ifxmips_port_set_dir_in(port, gpio);
- return 0;
-}
-
-static int
-ifxmips_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value)
-{
- int port = GPIO_TO_PORT(offset);
- int gpio = GPIO_TO_GPIO(offset);
- ifxmips_port_clear_open_drain(port, gpio);
- ifxmips_port_clear_altsel0(port, gpio);
- ifxmips_port_clear_altsel1(port, gpio);
- ifxmips_port_set_dir_out(port, gpio);
- ifxmips_gpio_set(chip, offset, value);
- return 0;
-}
-
-int
-gpio_to_irq(unsigned int gpio)
-{
- return -EINVAL;
-}
-EXPORT_SYMBOL(gpio_to_irq);
-
-struct gpio_chip
-ifxmips_gpio_chip =
-{
- .label = "ifxmips-gpio",
- .direction_input = ifxmips_gpio_direction_input,
- .direction_output = ifxmips_gpio_direction_output,
- .get = ifxmips_gpio_get,
- .set = ifxmips_gpio_set,
- .base = 0,
- .ngpio = 32,
-};
-
-static int
-ifxmips_gpio_probe(struct platform_device *dev)
-{
- gpiochip_add(&ifxmips_gpio_chip);
- return 0;
-}
-
-static int
-ifxmips_gpio_remove(struct platform_device *pdev)
-{
- gpiochip_remove(&ifxmips_gpio_chip);
- return 0;
-}
-
-static struct platform_driver
-ifxmips_gpio_driver = {
- .probe = ifxmips_gpio_probe,
- .remove = ifxmips_gpio_remove,
- .driver = {
- .name = "ifxmips_gpio",
- .owner = THIS_MODULE,
- },
-};
-
-int __init
-ifxmips_gpio_init(void)
-{
- int ret = platform_driver_register(&ifxmips_gpio_driver);
- if (ret)
- printk(KERN_INFO "ifxmips_gpio : Error registering platfom driver!");
- return ret;
-}
-
-void __exit
-ifxmips_gpio_exit(void)
-{
- platform_driver_unregister(&ifxmips_gpio_driver);
-}
-
-module_init(ifxmips_gpio_init);
-module_exit(ifxmips_gpio_exit);
+++ /dev/null
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/version.h>
-
-#include <ifxmips.h>
-
-void
-ifxmips_pmu_enable(unsigned int module)
-{
- int err = 1000000;
-
- ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) & ~module, IFXMIPS_PMU_PWDCR);
- while (--err && (ifxmips_r32(IFXMIPS_PMU_PWDSR) & module));
-
- if (!err)
- panic("activating PMU module failed!");
-}
-EXPORT_SYMBOL(ifxmips_pmu_enable);
-
-void
-ifxmips_pmu_disable(unsigned int module)
-{
- ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) | module, IFXMIPS_PMU_PWDCR);
-}
-EXPORT_SYMBOL(ifxmips_pmu_disable);
+++ /dev/null
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/bootmem.h>
-#include <linux/etherdevice.h>
-
-#include <asm/bootinfo.h>
-#include <machine.h>
-
-#include <ifxmips.h>
-#include <ifxmips_prom.h>
-
-/* for Multithreading (APRP) on MIPS34K */
-unsigned long physical_memsize;
-
-void
-prom_free_prom_memory(void)
-{
-}
-
-extern unsigned char ifxmips_ethaddr[6];
-int cmdline_mac = 0;
-
-static int __init
-ifxmips_set_ethaddr(char *str)
-{
-#define IS_HEX(x) \
- (((x >= '0' && x <= '9') || (x >= 'a' && x <= 'f') \
- || (x >= 'A' && x <= 'F')) ? (1) : (0))
- int i;
- str = strchr(str, '=');
- if (!str)
- goto out;
- str++;
- if (strlen(str) != 17)
- goto out;
- for (i = 0; i < 6; i++) {
- if (!IS_HEX(str[3 * i]) || !IS_HEX(str[(3 * i) + 1]))
- goto out;
- if ((i != 5) && (str[(3 * i) + 2] != ':'))
- goto out;
- ifxmips_ethaddr[i] = simple_strtoul(&str[3 * i], NULL, 16);
- }
- if (is_valid_ether_addr(ifxmips_ethaddr))
- cmdline_mac = 1;
-out:
- return 1;
-}
-__setup("ethaddr", ifxmips_set_ethaddr);
-
-static void __init prom_detect_machtype(void)
-{
- mips_machtype = IFXMIPS_MACH_EASY50712;
-}
-
-static void __init prom_init_cmdline(void)
-{
- int argc = fw_arg0;
- char **argv = (char **) fw_arg1;
- char **envp = (char **) fw_arg2;
-
- int memsize = 16; /* assume 16M as default */
- int i;
-
- if (argc)
- {
- argv = (char **)KSEG1ADDR((unsigned long)argv);
- arcs_cmdline[0] = '\0';
- for (i = 1; i < argc; i++)
- {
- char *a = (char *)KSEG1ADDR(argv[i]);
- if (!argv[i])
- continue;
- if (strlen(arcs_cmdline) + strlen(a + 1) >= sizeof(arcs_cmdline))
- {
- printk("cmdline overflow, skipping: %s\n", a);
- break;
- }
- strcat(arcs_cmdline, a);
- strcat(arcs_cmdline, " ");
- }
- if (!*arcs_cmdline)
- strcpy(&(arcs_cmdline[0]),
- "console=ttyS0,115200 rootfstype=squashfs,jffs2");
- }
- envp = (char **)KSEG1ADDR((unsigned long)envp);
- while (*envp)
- {
- char *e = (char *)KSEG1ADDR(*envp);
-
- if (!strncmp(e, "memsize=", 8))
- {
- e += 8;
- memsize = simple_strtoul(e, NULL, 10);
- }
- envp++;
- }
- memsize *= 1024 * 1024;
-
- add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
-}
-
-void __init
-prom_init(void)
-{
- prom_detect_machtype();
- prom_init_cmdline();
-}
+++ /dev/null
-#include <linux/init.h>
-#include <linux/cpu.h>
-
-#include <asm/time.h>
-#include <asm/traps.h>
-#include <asm/irq.h>
-#include <asm/bootinfo.h>
-
-#include <ifxmips.h>
-#include <ifxmips_irq.h>
-#include <ifxmips_pmu.h>
-#include <ifxmips_cgu.h>
-#include <ifxmips_prom.h>
-
-#include <machine.h>
-
-DEFINE_SPINLOCK(ebu_lock);
-EXPORT_SYMBOL_GPL(ebu_lock);
-
-static unsigned int r4k_offset;
-static unsigned int r4k_cur;
-
-static unsigned int ifxmips_ram_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
-#define DDR_HZ ifxmips_ram_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3]
-
-extern void __init ifxmips_soc_setup(void);
-
-static inline u32
-ifxmips_get_counter_resolution(void)
-{
- u32 res;
- __asm__ __volatile__(
- ".set push\n"
- ".set mips32r2\n"
- ".set noreorder\n"
- "rdhwr %0, $3\n"
- "ehb\n"
- ".set pop\n"
- : "=&r" (res)
- : /* no input */
- : "memory");
- instruction_hazard();
- return res;
-}
-
-void __init
-plat_time_init(void)
-{
- mips_hpt_frequency = ifxmips_get_cpu_hz() / ifxmips_get_counter_resolution();
- r4k_cur = (read_c0_count() + r4k_offset);
- write_c0_compare(r4k_cur);
-
- ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI);
- ifxmips_w32(0x100, IFXMIPS_GPTU_GPT_CLC); /* set clock divider to 1 */
-}
-
-void __init
-plat_mem_setup(void)
-{
- u32 status;
-
- /* make sure to have no "reverse endian" for user mode! */
- status = read_c0_status();
- status &= (~(1<<25));
- write_c0_status(status);
-
- /* call the chip specific init code */
- ifxmips_soc_setup();
-}
-
-
-unsigned int
-ifxmips_get_cpu_hz(void)
-{
- switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc)
- {
- case 0:
- return CLOCK_333M;
- case 4:
- return DDR_HZ;
- case 8:
- return DDR_HZ << 1;
- default:
- return DDR_HZ >> 1;
- }
-}
-EXPORT_SYMBOL(ifxmips_get_cpu_hz);
-
-static int __init
-ifxmips_machine_setup(void)
-{
- mips_machine_setup();
- return 0;
-}
-
-arch_initcall(ifxmips_machine_setup);
-
-static void __init
-ifxmips_generic_init(void)
-{
-}
-
-MIPS_MACHINE(IFXMIPS_MACH_GENERIC, "Generic", "Generic Infineon board",
- ifxmips_generic_init);
-
-__setup("board=", mips_machtype_setup);
-
+++ /dev/null
-obj-y := timer.o cgu.o
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2007 Xu Liang, infineon
- * Copyright (C) 2008 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/init.h>
-#include <linux/uaccess.h>
-#include <linux/unistd.h>
-#include <linux/errno.h>
-
-#include <asm/irq.h>
-#include <asm/div64.h>
-
-#include <ifxmips.h>
-#include <ifxmips_cgu.h>
-
-static unsigned int cgu_get_pll0_fdiv(void);
-unsigned int ifxmips_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
-
-#define DDR_HZ ifxmips_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3]
-
-static inline unsigned int get_input_clock(int pll)
-{
- switch (pll) {
- case 0:
- if (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & CGU_PLL0_SRC)
- return BASIS_INPUT_CRYSTAL_USB;
- else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
- return BASIC_INPUT_CLOCK_FREQUENCY_1;
- else
- return BASIC_INPUT_CLOCK_FREQUENCY_2;
- case 1:
- if (CGU_PLL1_SRC)
- return BASIS_INPUT_CRYSTAL_USB;
- else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
- return BASIC_INPUT_CLOCK_FREQUENCY_1;
- else
- return BASIC_INPUT_CLOCK_FREQUENCY_2;
- case 2:
- switch (CGU_PLL2_SRC) {
- case 0:
- return cgu_get_pll0_fdiv();
- case 1:
- return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
- BASIC_INPUT_CLOCK_FREQUENCY_1 :
- BASIC_INPUT_CLOCK_FREQUENCY_2;
- case 2:
- return BASIS_INPUT_CRYSTAL_USB;
- }
- default:
- return 0;
- }
-}
-
-static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
-{
- u64 res, clock = get_input_clock(pll);
-
- res = num * clock;
- do_div(res, den);
- return res;
-}
-
-static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
- unsigned int K)
-{
- unsigned int num = ((N + 1) << 10) + K;
- unsigned int den = (M + 1) << 10;
-
- return cal_dsm(pll, num, den);
-}
-
-static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
- unsigned int K)
-{
- unsigned int num = ((N + 1) << 11) + K + 512;
- unsigned int den = (M + 1) << 11;
-
- return cal_dsm(pll, num, den);
-}
-
-static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
- unsigned int K)
-{
- unsigned int num = K >= 512 ?
- ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
- unsigned int den = (M + 1) << 12;
-
- return cal_dsm(pll, num, den);
-}
-
-static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
- unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
-{
- if (!dsmsel)
- return mash_dsm(pll, M, N, K);
- else if (!phase_div_en)
- return mash_dsm(pll, M, N, K);
- else
- return ssff_dsm_2(pll, M, N, K);
-}
-
-static inline unsigned int cgu_get_pll0_fosc(void)
-{
- if (CGU_PLL0_BYPASS)
- return get_input_clock(0);
- else
- return !CGU_PLL0_CFG_FRAC_EN
- ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL,
- CGU_PLL0_PHASE_DIVIDER_ENABLE)
- : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK,
- CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
-}
-
-static unsigned int cgu_get_pll0_fdiv(void)
-{
- unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
- return (cgu_get_pll0_fosc() + (div >> 1)) / div;
-}
-
-unsigned int cgu_get_io_region_clock(void)
-{
- unsigned int ret = cgu_get_pll0_fosc();
- switch (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
- default:
- case 0:
- return (ret + 1) / 2;
- case 1:
- return (ret * 2 + 2) / 5;
- case 2:
- return (ret + 1) / 3;
- case 3:
- return (ret + 2) / 4;
- }
-}
-
-unsigned int cgu_get_fpi_bus_clock(int fpi)
-{
- unsigned int ret = cgu_get_io_region_clock();
- if ((fpi == 2) && (ifxmips_r32(IFXMIPS_CGU_SYS) & CGU_SYS_FPI_SEL))
- ret >>= 1;
- return ret;
-}
-EXPORT_SYMBOL(cgu_get_fpi_bus_clock);
-
-unsigned int ifxmips_get_fpi_hz(void)
-{
- unsigned int ddr_clock = DDR_HZ;
- if (ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
- return ddr_clock >> 1;
- return ddr_clock;
-}
-EXPORT_SYMBOL(ifxmips_get_fpi_hz);
+++ /dev/null
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/init.h>
-#include <linux/uaccess.h>
-#include <linux/unistd.h>
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-
-#include <asm/irq.h>
-#include <asm/div64.h>
-
-#include <ifxmips.h>
-#include <ifxmips_irq.h>
-#include <ifxmips_cgu.h>
-#include <ifxmips_gptu.h>
-#include <ifxmips_pmu.h>
-
-#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
-
-#ifdef TIMER1A
-#define FIRST_TIMER TIMER1A
-#else
-#define FIRST_TIMER 2
-#endif
-
-/*
- * GPTC divider is set or not.
- */
-#define GPTU_CLC_RMC_IS_SET 0
-
-/*
- * Timer Interrupt (IRQ)
- */
-/* Must be adjusted when ICU driver is available */
-#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
-
-/*
- * Bits Operation
- */
-#define GET_BITS(x, msb, lsb) \
- (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
-#define SET_BITS(x, msb, lsb, value) \
- (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
- (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
-
-/*
- * GPTU Register Mapping
- */
-#define IFXMIPS_GPTU (KSEG1 + 0x1E100A00)
-#define IFXMIPS_GPTU_CLC ((volatile u32 *)(IFXMIPS_GPTU + 0x0000))
-#define IFXMIPS_GPTU_ID ((volatile u32 *)(IFXMIPS_GPTU + 0x0008))
-#define IFXMIPS_GPTU_CON(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
-#define IFXMIPS_GPTU_RUN(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
-#define IFXMIPS_GPTU_RELOAD(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
-#define IFXMIPS_GPTU_COUNT(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
-#define IFXMIPS_GPTU_IRNEN ((volatile u32 *)(IFXMIPS_GPTU + 0x00F4))
-#define IFXMIPS_GPTU_IRNICR ((volatile u32 *)(IFXMIPS_GPTU + 0x00F8))
-#define IFXMIPS_GPTU_IRNCR ((volatile u32 *)(IFXMIPS_GPTU + 0x00FC))
-
-/*
- * Clock Control Register
- */
-#define GPTU_CLC_SMC GET_BITS(*IFXMIPS_GPTU_CLC, 23, 16)
-#define GPTU_CLC_RMC GET_BITS(*IFXMIPS_GPTU_CLC, 15, 8)
-#define GPTU_CLC_FSOE (*IFXMIPS_GPTU_CLC & (1 << 5))
-#define GPTU_CLC_EDIS (*IFXMIPS_GPTU_CLC & (1 << 3))
-#define GPTU_CLC_SPEN (*IFXMIPS_GPTU_CLC & (1 << 2))
-#define GPTU_CLC_DISS (*IFXMIPS_GPTU_CLC & (1 << 1))
-#define GPTU_CLC_DISR (*IFXMIPS_GPTU_CLC & (1 << 0))
-
-#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
-#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
-#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
-#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
-#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
-#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
-#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
-
-/*
- * ID Register
- */
-#define GPTU_ID_ID GET_BITS(*IFXMIPS_GPTU_ID, 15, 8)
-#define GPTU_ID_CFG GET_BITS(*IFXMIPS_GPTU_ID, 7, 5)
-#define GPTU_ID_REV GET_BITS(*IFXMIPS_GPTU_ID, 4, 0)
-
-/*
- * Control Register of Timer/Counter nX
- * n is the index of block (1 based index)
- * X is either A or B
- */
-#define GPTU_CON_SRC_EG(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 10))
-#define GPTU_CON_SRC_EXT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 9))
-#define GPTU_CON_SYNC(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 8))
-#define GPTU_CON_EDGE(n, X) GET_BITS(*IFXMIPS_GPTU_CON(n, X), 7, 6)
-#define GPTU_CON_INV(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 5))
-#define GPTU_CON_EXT(n, X) (*IFXMIPS_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
-#define GPTU_CON_STP(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 3))
-#define GPTU_CON_CNT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 2))
-#define GPTU_CON_DIR(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 1))
-#define GPTU_CON_EN(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 0))
-
-#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
-#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
-#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
-#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
-#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
-#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
-#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
-#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
-#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
-
-#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
-#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
-#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
-
-#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
-#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
-
-#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
-#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
-#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
-#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
-#define TIMER_FLAG_NONE_EDGE 0x0000
-#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
-#define TIMER_FLAG_REAL 0x0000
-#define TIMER_FLAG_INVERT 0x0040
-#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
-#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
-#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
-#define TIMER_FLAG_CALLBACK_IN_HB 0x0200
-#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
-#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
-
-struct timer_dev_timer {
- unsigned int f_irq_on;
- unsigned int irq;
- unsigned int flag;
- unsigned long arg1;
- unsigned long arg2;
-};
-
-struct timer_dev {
- struct mutex gptu_mutex;
- unsigned int number_of_timers;
- unsigned int occupation;
- unsigned int f_gptu_on;
- struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
-};
-
-static int gptu_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
-static int gptu_open(struct inode *, struct file *);
-static int gptu_release(struct inode *, struct file *);
-
-static struct file_operations gptu_fops = {
- .owner = THIS_MODULE,
- .ioctl = gptu_ioctl,
- .open = gptu_open,
- .release = gptu_release
-};
-
-static struct miscdevice gptu_miscdev = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "gptu",
- .fops = &gptu_fops,
-};
-
-static struct timer_dev timer_dev;
-
-static irqreturn_t timer_irq_handler(int irq, void *p)
-{
- unsigned int timer;
- unsigned int flag;
- struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
-
- timer = irq - TIMER_INTERRUPT;
- if (timer < timer_dev.number_of_timers
- && dev_timer == &timer_dev.timer[timer]) {
- /* Clear interrupt. */
- ifxmips_w32(1 << timer, IFXMIPS_GPTU_IRNCR);
-
- /* Call user hanler or signal. */
- flag = dev_timer->flag;
- if (!(timer & 0x01)
- || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
- /* 16-bit timer or timer A of 32-bit timer */
- switch (TIMER_FLAG_MASK_HANDLE(flag)) {
- case TIMER_FLAG_CALLBACK_IN_IRQ:
- case TIMER_FLAG_CALLBACK_IN_HB:
- if (dev_timer->arg1)
- (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
- break;
- case TIMER_FLAG_SIGNAL:
- send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
- break;
- }
- }
- }
- return IRQ_HANDLED;
-}
-
-static inline void ifxmips_enable_gptu(void)
-{
- ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT);
-
- /* Set divider as 1, disable write protection for SPEN, enable module. */
- *IFXMIPS_GPTU_CLC =
- GPTU_CLC_SMC_SET(0x00) |
- GPTU_CLC_RMC_SET(0x01) |
- GPTU_CLC_FSOE_SET(0) |
- GPTU_CLC_SBWE_SET(1) |
- GPTU_CLC_EDIS_SET(0) |
- GPTU_CLC_SPEN_SET(0) |
- GPTU_CLC_DISR_SET(0);
-}
-
-static inline void ifxmips_disable_gptu(void)
-{
- ifxmips_w32(0x00, IFXMIPS_GPTU_IRNEN);
- ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR);
-
- /* Set divider as 0, enable write protection for SPEN, disable module. */
- *IFXMIPS_GPTU_CLC =
- GPTU_CLC_SMC_SET(0x00) |
- GPTU_CLC_RMC_SET(0x00) |
- GPTU_CLC_FSOE_SET(0) |
- GPTU_CLC_SBWE_SET(0) |
- GPTU_CLC_EDIS_SET(0) |
- GPTU_CLC_SPEN_SET(0) |
- GPTU_CLC_DISR_SET(1);
-
- ifxmips_pmu_disable(IFXMIPS_PMU_PWDCR_GPT);
-}
-
-int ifxmips_request_timer(unsigned int timer, unsigned int flag,
- unsigned long value, unsigned long arg1, unsigned long arg2)
-{
- int ret = 0;
- unsigned int con_reg, irnen_reg;
- int n, X;
-
- if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
- return -EINVAL;
-
- printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
- timer, flag, value);
-
- if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
- value &= 0xFFFF;
- else
- timer &= ~0x01;
-
- mutex_lock(&timer_dev.gptu_mutex);
-
- /*
- * Allocate timer.
- */
- if (timer < FIRST_TIMER) {
- unsigned int mask;
- unsigned int shift;
- /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
- unsigned int offset = TIMER2A;
-
- /*
- * Pick up a free timer.
- */
- if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
- mask = 1 << offset;
- shift = 1;
- } else {
- mask = 3 << offset;
- shift = 2;
- }
- for (timer = offset;
- timer < offset + timer_dev.number_of_timers;
- timer += shift, mask <<= shift)
- if (!(timer_dev.occupation & mask)) {
- timer_dev.occupation |= mask;
- break;
- }
- if (timer >= offset + timer_dev.number_of_timers) {
- printk("failed![%d]\n", __LINE__);
- mutex_unlock(&timer_dev.gptu_mutex);
- return -EINVAL;
- } else
- ret = timer;
- } else {
- register unsigned int mask;
-
- /*
- * Check if the requested timer is free.
- */
- mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
- if ((timer_dev.occupation & mask)) {
- printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
- __LINE__, mask, timer_dev.occupation);
- mutex_unlock(&timer_dev.gptu_mutex);
- return -EBUSY;
- } else {
- timer_dev.occupation |= mask;
- ret = 0;
- }
- }
-
- /*
- * Prepare control register value.
- */
- switch (TIMER_FLAG_MASK_EDGE(flag)) {
- default:
- case TIMER_FLAG_NONE_EDGE:
- con_reg = GPTU_CON_EDGE_SET(0x00);
- break;
- case TIMER_FLAG_RISE_EDGE:
- con_reg = GPTU_CON_EDGE_SET(0x01);
- break;
- case TIMER_FLAG_FALL_EDGE:
- con_reg = GPTU_CON_EDGE_SET(0x02);
- break;
- case TIMER_FLAG_ANY_EDGE:
- con_reg = GPTU_CON_EDGE_SET(0x03);
- break;
- }
- if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
- con_reg |=
- TIMER_FLAG_MASK_SRC(flag) ==
- TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
- GPTU_CON_SRC_EXT_SET(0);
- else
- con_reg |=
- TIMER_FLAG_MASK_SRC(flag) ==
- TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
- GPTU_CON_SRC_EG_SET(0);
- con_reg |=
- TIMER_FLAG_MASK_SYNC(flag) ==
- TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
- GPTU_CON_SYNC_SET(1);
- con_reg |=
- TIMER_FLAG_MASK_INVERT(flag) ==
- TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
- con_reg |=
- TIMER_FLAG_MASK_SIZE(flag) ==
- TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
- GPTU_CON_EXT_SET(1);
- con_reg |=
- TIMER_FLAG_MASK_STOP(flag) ==
- TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
- con_reg |=
- TIMER_FLAG_MASK_TYPE(flag) ==
- TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
- GPTU_CON_CNT_SET(1);
- con_reg |=
- TIMER_FLAG_MASK_DIR(flag) ==
- TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
-
- /*
- * Fill up running data.
- */
- timer_dev.timer[timer - FIRST_TIMER].flag = flag;
- timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
- timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
- if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
- timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
-
- /*
- * Enable GPTU module.
- */
- if (!timer_dev.f_gptu_on) {
- ifxmips_enable_gptu();
- timer_dev.f_gptu_on = 1;
- }
-
- /*
- * Enable IRQ.
- */
- if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
- if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
- timer_dev.timer[timer - FIRST_TIMER].arg1 =
- (unsigned long) find_task_by_vpid((int) arg1);
-
- irnen_reg = 1 << (timer - FIRST_TIMER);
-
- if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
- || (TIMER_FLAG_MASK_HANDLE(flag) ==
- TIMER_FLAG_CALLBACK_IN_IRQ
- && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
- enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
- timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
- }
- } else
- irnen_reg = 0;
-
- /*
- * Write config register, reload value and enable interrupt.
- */
- n = timer >> 1;
- X = timer & 0x01;
- *IFXMIPS_GPTU_CON(n, X) = con_reg;
- *IFXMIPS_GPTU_RELOAD(n, X) = value;
- /* printk("reload value = %d\n", (u32)value); */
- *IFXMIPS_GPTU_IRNEN |= irnen_reg;
-
- mutex_unlock(&timer_dev.gptu_mutex);
- printk("successful!\n");
- return ret;
-}
-EXPORT_SYMBOL(ifxmips_request_timer);
-
-int ifxmips_free_timer(unsigned int timer)
-{
- unsigned int flag;
- unsigned int mask;
- int n, X;
-
- if (!timer_dev.f_gptu_on)
- return -EINVAL;
-
- if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
- return -EINVAL;
-
- mutex_lock(&timer_dev.gptu_mutex);
-
- flag = timer_dev.timer[timer - FIRST_TIMER].flag;
- if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
- timer &= ~0x01;
-
- mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
- if (((timer_dev.occupation & mask) ^ mask)) {
- mutex_unlock(&timer_dev.gptu_mutex);
- return -EINVAL;
- }
-
- n = timer >> 1;
- X = timer & 0x01;
-
- if (GPTU_CON_EN(n, X))
- *IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
-
- *IFXMIPS_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
- *IFXMIPS_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
-
- if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
- disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
- timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
- }
-
- timer_dev.occupation &= ~mask;
- if (!timer_dev.occupation && timer_dev.f_gptu_on) {
- ifxmips_disable_gptu();
- timer_dev.f_gptu_on = 0;
- }
-
- mutex_unlock(&timer_dev.gptu_mutex);
-
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_free_timer);
-
-int ifxmips_start_timer(unsigned int timer, int is_resume)
-{
- unsigned int flag;
- unsigned int mask;
- int n, X;
-
- if (!timer_dev.f_gptu_on)
- return -EINVAL;
-
- if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
- return -EINVAL;
-
- mutex_lock(&timer_dev.gptu_mutex);
-
- flag = timer_dev.timer[timer - FIRST_TIMER].flag;
- if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
- timer &= ~0x01;
-
- mask = (TIMER_FLAG_MASK_SIZE(flag) ==
- TIMER_FLAG_16BIT ? 1 : 3) << timer;
- if (((timer_dev.occupation & mask) ^ mask)) {
- mutex_unlock(&timer_dev.gptu_mutex);
- return -EINVAL;
- }
-
- n = timer >> 1;
- X = timer & 0x01;
-
- *IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
-
- mutex_unlock(&timer_dev.gptu_mutex);
-
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_start_timer);
-
-int ifxmips_stop_timer(unsigned int timer)
-{
- unsigned int flag;
- unsigned int mask;
- int n, X;
-
- if (!timer_dev.f_gptu_on)
- return -EINVAL;
-
- if (timer < FIRST_TIMER
- || timer >= FIRST_TIMER + timer_dev.number_of_timers)
- return -EINVAL;
-
- mutex_lock(&timer_dev.gptu_mutex);
-
- flag = timer_dev.timer[timer - FIRST_TIMER].flag;
- if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
- timer &= ~0x01;
-
- mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
- if (((timer_dev.occupation & mask) ^ mask)) {
- mutex_unlock(&timer_dev.gptu_mutex);
- return -EINVAL;
- }
-
- n = timer >> 1;
- X = timer & 0x01;
-
- *IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
-
- mutex_unlock(&timer_dev.gptu_mutex);
-
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_stop_timer);
-
-int ifxmips_reset_counter_flags(u32 timer, u32 flags)
-{
- unsigned int oflag;
- unsigned int mask, con_reg;
- int n, X;
-
- if (!timer_dev.f_gptu_on)
- return -EINVAL;
-
- if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
- return -EINVAL;
-
- mutex_lock(&timer_dev.gptu_mutex);
-
- oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
- if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
- timer &= ~0x01;
-
- mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
- if (((timer_dev.occupation & mask) ^ mask)) {
- mutex_unlock(&timer_dev.gptu_mutex);
- return -EINVAL;
- }
-
- switch (TIMER_FLAG_MASK_EDGE(flags)) {
- default:
- case TIMER_FLAG_NONE_EDGE:
- con_reg = GPTU_CON_EDGE_SET(0x00);
- break;
- case TIMER_FLAG_RISE_EDGE:
- con_reg = GPTU_CON_EDGE_SET(0x01);
- break;
- case TIMER_FLAG_FALL_EDGE:
- con_reg = GPTU_CON_EDGE_SET(0x02);
- break;
- case TIMER_FLAG_ANY_EDGE:
- con_reg = GPTU_CON_EDGE_SET(0x03);
- break;
- }
- if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
- con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
- else
- con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
- con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
- con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
- con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
- con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
- con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
- con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
-
- timer_dev.timer[timer - FIRST_TIMER].flag = flags;
- if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
- timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
-
- n = timer >> 1;
- X = timer & 0x01;
-
- *IFXMIPS_GPTU_CON(n, X) = con_reg;
- smp_wmb();
- printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *IFXMIPS_GPTU_CON(n, X));
- mutex_unlock(&timer_dev.gptu_mutex);
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_reset_counter_flags);
-
-int ifxmips_get_count_value(unsigned int timer, unsigned long *value)
-{
- unsigned int flag;
- unsigned int mask;
- int n, X;
-
- if (!timer_dev.f_gptu_on)
- return -EINVAL;
-
- if (timer < FIRST_TIMER
- || timer >= FIRST_TIMER + timer_dev.number_of_timers)
- return -EINVAL;
-
- mutex_lock(&timer_dev.gptu_mutex);
-
- flag = timer_dev.timer[timer - FIRST_TIMER].flag;
- if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
- timer &= ~0x01;
-
- mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
- if (((timer_dev.occupation & mask) ^ mask)) {
- mutex_unlock(&timer_dev.gptu_mutex);
- return -EINVAL;
- }
-
- n = timer >> 1;
- X = timer & 0x01;
-
- *value = *IFXMIPS_GPTU_COUNT(n, X);
-
- mutex_unlock(&timer_dev.gptu_mutex);
-
- return 0;
-}
-EXPORT_SYMBOL(ifxmips_get_count_value);
-
-u32 ifxmips_cal_divider(unsigned long freq)
-{
- u64 module_freq, fpi = cgu_get_fpi_bus_clock(2);
- u32 clock_divider = 1;
- module_freq = fpi * 1000;
- do_div(module_freq, clock_divider * freq);
- return module_freq;
-}
-EXPORT_SYMBOL(ifxmips_cal_divider);
-
-int ifxmips_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
- int is_ext_src, unsigned int handle_flag, unsigned long arg1,
- unsigned long arg2)
-{
- unsigned long divider;
- unsigned int flag;
-
- divider = ifxmips_cal_divider(freq);
- if (divider == 0)
- return -EINVAL;
- flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
- | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
- | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
- | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
- | TIMER_FLAG_MASK_HANDLE(handle_flag);
-
- printk(KERN_INFO "ifxmips_set_timer(%d, %d), divider = %lu\n",
- timer, freq, divider);
- return ifxmips_request_timer(timer, flag, divider, arg1, arg2);
-}
-EXPORT_SYMBOL(ifxmips_set_timer);
-
-int ifxmips_set_counter(unsigned int timer, unsigned int flag, u32 reload,
- unsigned long arg1, unsigned long arg2)
-{
- printk(KERN_INFO "ifxmips_set_counter(%d, %#x, %d)\n", timer, flag, reload);
- return ifxmips_request_timer(timer, flag, reload, arg1, arg2);
-}
-EXPORT_SYMBOL(ifxmips_set_counter);
-
-static int gptu_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
- unsigned long arg)
-{
- int ret;
- struct gptu_ioctl_param param;
-
- if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
- return -EFAULT;
- copy_from_user(¶m, (void *) arg, sizeof(param));
-
- if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
- || GPTU_SET_COUNTER) && param.timer < 2)
- || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
- && !access_ok(VERIFY_WRITE, arg,
- sizeof(struct gptu_ioctl_param)))
- return -EFAULT;
-
- switch (cmd) {
- case GPTU_REQUEST_TIMER:
- ret = ifxmips_request_timer(param.timer, param.flag, param.value,
- (unsigned long) param.pid,
- (unsigned long) param.sig);
- if (ret > 0) {
- copy_to_user(&((struct gptu_ioctl_param *) arg)->
- timer, &ret, sizeof(&ret));
- ret = 0;
- }
- break;
- case GPTU_FREE_TIMER:
- ret = ifxmips_free_timer(param.timer);
- break;
- case GPTU_START_TIMER:
- ret = ifxmips_start_timer(param.timer, param.flag);
- break;
- case GPTU_STOP_TIMER:
- ret = ifxmips_stop_timer(param.timer);
- break;
- case GPTU_GET_COUNT_VALUE:
- ret = ifxmips_get_count_value(param.timer, ¶m.value);
- if (!ret)
- copy_to_user(&((struct gptu_ioctl_param *) arg)->
- value, ¶m.value,
- sizeof(param.value));
- break;
- case GPTU_CALCULATE_DIVIDER:
- param.value = ifxmips_cal_divider(param.value);
- if (param.value == 0)
- ret = -EINVAL;
- else {
- copy_to_user(&((struct gptu_ioctl_param *) arg)->
- value, ¶m.value,
- sizeof(param.value));
- ret = 0;
- }
- break;
- case GPTU_SET_TIMER:
- ret = ifxmips_set_timer(param.timer, param.value,
- TIMER_FLAG_MASK_STOP(param.flag) !=
- TIMER_FLAG_ONCE ? 1 : 0,
- TIMER_FLAG_MASK_SRC(param.flag) ==
- TIMER_FLAG_EXT_SRC ? 1 : 0,
- TIMER_FLAG_MASK_HANDLE(param.flag) ==
- TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
- TIMER_FLAG_NO_HANDLE,
- (unsigned long) param.pid,
- (unsigned long) param.sig);
- if (ret > 0) {
- copy_to_user(&((struct gptu_ioctl_param *) arg)->
- timer, &ret, sizeof(&ret));
- ret = 0;
- }
- break;
- case GPTU_SET_COUNTER:
- ifxmips_set_counter(param.timer, param.flag, param.value, 0, 0);
- if (ret > 0) {
- copy_to_user(&((struct gptu_ioctl_param *) arg)->
- timer, &ret, sizeof(&ret));
- ret = 0;
- }
- break;
- default:
- ret = -ENOTTY;
- }
-
- return ret;
-}
-
-static int gptu_open(struct inode *inode, struct file *file)
-{
- return 0;
-}
-
-static int gptu_release(struct inode *inode, struct file *file)
-{
- return 0;
-}
-
-int __init ifxmips_gptu_init(void)
-{
- int ret;
- unsigned int i;
-
- ifxmips_w32(0, IFXMIPS_GPTU_IRNEN);
- ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR);
-
- memset(&timer_dev, 0, sizeof(timer_dev));
- mutex_init(&timer_dev.gptu_mutex);
-
- ifxmips_enable_gptu();
- timer_dev.number_of_timers = GPTU_ID_CFG * 2;
- ifxmips_disable_gptu();
- if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
- timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
- printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
-
- ret = misc_register(&gptu_miscdev);
- if (ret) {
- printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
- return ret;
- } else {
- printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
- }
-
- for (i = 0; i < timer_dev.number_of_timers; i++) {
- ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
- if (ret) {
- for (; i >= 0; i--)
- free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
- misc_deregister(&gptu_miscdev);
- printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
- return ret;
- } else {
- timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
- disable_irq(timer_dev.timer[i].irq);
- printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
- }
- }
-
- return 0;
-}
-
-void __exit ifxmips_gptu_exit(void)
-{
- unsigned int i;
-
- for (i = 0; i < timer_dev.number_of_timers; i++) {
- if (timer_dev.timer[i].f_irq_on)
- disable_irq(timer_dev.timer[i].irq);
- free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
- }
- ifxmips_disable_gptu();
- misc_deregister(&gptu_miscdev);
-}
-
-module_init(ifxmips_gptu_init);
-module_exit(ifxmips_gptu_exit);
+++ /dev/null
-if IFXMIPS_DANUBE
-
-config IFXMIPS_ARCAYDIAN_BRNBOOT
- bool
- default n
-
-menu "Infineon SoC machine selection"
-
-config DANUBE_MACH_EASY50712
- bool "Easy50712"
- default y
-
-config DANUBE_MACH_EASY4010
- bool "Easy4010"
- default y
-
-config DANUBE_MACH_ARV4519
- bool "ARV4519"
- default y
- select DANUBE_ARCAYDIAN_BRNBOOT
-
-config DANUBE_MACH_ARV45XX
- bool "ARV45XX"
- default y
- select IFXMIPS_ARCAYDIAN_BRNBOOT
-
-endmenu
-
-endif
+++ /dev/null
-obj-y := dma-core.o irq.o ebu.o setup.o devices.o cgu.o
-obj-$(CONFIG_IFXMIPS_ARCAYDIAN_BRNBOOT) += arcaydian.o
-obj-$(CONFIG_DANUBE_MACH_ARV45XX) += mach-arv45xx.o
-obj-$(CONFIG_DANUBE_MACH_EASY50712) += mach-easy50712.o
-obj-$(CONFIG_DANUBE_MACH_EASY4010) += mach-easy4010.o
+++ /dev/null
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/mtd/physmap.h>
-#include <linux/kernel.h>
-#include <linux/reboot.h>
-#include <linux/platform_device.h>
-#include <linux/leds.h>
-#include <linux/etherdevice.h>
-#include <linux/reboot.h>
-#include <linux/time.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <ifxmips.h>
-#include <ifxmips_prom.h>
-
-#include "arcaydian.h"
-
-static int ifxmips_brn = 0;
-
-int __init
-ifxmix_detect_brn_block(unsigned int offset)
-{
- unsigned char temp[8];
- memcpy_fromio(temp, (void *)KSEG1ADDR(IFXMIPS_FLASH_START + offset), 8);
- if (!memcmp(temp, "BRN-BOOT", 8))
- ifxmips_brn = 1;
- return !ifxmips_brn;
-}
-
-int __init
-ifxmips_find_brn_mac(unsigned int offset, unsigned char *ifxmips_ethaddr)
-{
- if(!ifxmips_brn)
- return 1;
- memcpy_fromio(ifxmips_ethaddr,
- (void *)KSEG1ADDR(IFXMIPS_FLASH_START + offset), 6);
- return is_valid_ether_addr(ifxmips_ethaddr);
-}
-
-/* used by madwifi to know if eeprom is located in flash */
-int
-ifxmips_has_brn_block(void)
-{
- return ifxmips_brn;
-}
-EXPORT_SYMBOL(ifxmips_has_brn_block);
+++ /dev/null
-#ifndef _ARCAYDIAN_H__
-#define _ARCAYDIAN_H__
-
-int __init ifxmix_detect_brn_block(unsigned int offset);
-int __init ifxmips_find_brn_mac(unsigned int offset, unsigned char *ifxmips_ethaddr);
-
-#endif
+++ /dev/null
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/init.h>
-#include <linux/uaccess.h>
-#include <linux/unistd.h>
-#include <linux/errno.h>
-
-#include <asm/irq.h>
-#include <asm/div64.h>
-
-#include <ifxmips.h>
-#include <ifxmips_cgu.h>
-
-void
-cgu_setup_pci_clk(int external_clock)
-{
- /* set clock to 33Mhz */
- ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000,
- IFXMIPS_CGU_IFCCR);
- ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000,
- IFXMIPS_CGU_IFCCR);
- if (external_clock)
- {
- ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~(1 << 16),
- IFXMIPS_CGU_IFCCR);
- ifxmips_w32((1 << 30), IFXMIPS_CGU_PCICR);
- } else {
- ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16),
- IFXMIPS_CGU_IFCCR);
- ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
- }
-}
-
-
+++ /dev/null
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/mtd/physmap.h>
-#include <linux/kernel.h>
-#include <linux/reboot.h>
-#include <linux/platform_device.h>
-#include <linux/leds.h>
-#include <linux/etherdevice.h>
-#include <linux/reboot.h>
-#include <linux/time.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-
-#include <asm/bootinfo.h>
-#include <asm/irq.h>
-
-#include <ifxmips.h>
-#include <ifxmips_irq.h>
-#include <ifxmips_pmu.h>
-#include <ifxmips_led.h>
-
-#include "devices.h"
-
-/* asc ports */
-static struct resource danube_asc0_resources[] =
-{
- [0] = {
- .start = (IFXMIPS_ASC_BASE_ADDR & ~KSEG1),
- .end = (IFXMIPS_ASC_BASE_ADDR & ~KSEG1) + 0x100 - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IFXMIPSASC_TIR(0),
- .end = IFXMIPSASC_TIR(0)+3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct resource danube_asc1_resources[] =
-{
- [0] = {
- .start = (IFXMIPS_ASC_BASE_ADDR & ~KSEG1) + IFXMIPS_ASC_BASE_DIFF,
- .end = (IFXMIPS_ASC_BASE_ADDR & ~KSEG1) + IFXMIPS_ASC_BASE_DIFF + 0x100 - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IFXMIPSASC_TIR(1),
- .end = IFXMIPSASC_TIR(1)+3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-void __init danube_register_asc(int port)
-{
- switch (port) {
- case 0:
- platform_device_register_simple("ifxmips_asc", 0,
- danube_asc0_resources, ARRAY_SIZE(danube_asc0_resources));
- break;
- case 1:
- platform_device_register_simple("ifxmips_asc", 1,
- danube_asc1_resources, ARRAY_SIZE(danube_asc1_resources));
- break;
- default:
- break;
- }
-}
-
-/* ebu gpio */
-static struct platform_device ifxmips_ebu_gpio =
-{
- .name = "ifxmips_ebu",
- .num_resources = 1,
-};
-
-void __init
-danube_register_ebu_gpio(struct resource *resource, u32 value)
-{
- ifxmips_ebu_gpio.resource = resource;
- ifxmips_ebu_gpio.dev.platform_data = (void*)value;
- platform_device_register(&ifxmips_ebu_gpio);
-}
-
-/* ethernet */
-unsigned char ifxmips_ethaddr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-static struct resource danube_ethernet_resources =
-{
- .start = IFXMIPS_PPE32_BASE_ADDR,
- .end = IFXMIPS_PPE32_BASE_ADDR + IFXMIPS_PPE32_SIZE - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device danube_ethernet =
-{
- .name = "ifxmips_mii0",
- .resource = &danube_ethernet_resources,
- .num_resources = 1,
- .dev = {
- .platform_data = ifxmips_ethaddr,
- }
-};
-
-void __init
-danube_register_ethernet(unsigned char *mac, int mii_mode)
-{
- struct ifxmips_eth_data *eth = kmalloc(sizeof(struct ifxmips_eth_data), GFP_KERNEL);
- memset(eth, 0, sizeof(struct ifxmips_eth_data));
- if(mac)
- eth->mac = mac;
- else
- eth->mac = ifxmips_ethaddr;
- eth->mii_mode = mii_mode;
- danube_ethernet.dev.platform_data = eth;
- platform_device_register(&danube_ethernet);
-}
-
-/* pci */
-extern int ifxmips_pci_external_clock;
-extern int ifxmips_pci_req_mask;
-
-void __init
-danube_register_pci(int clock, int irq_mask)
-{
- ifxmips_pci_external_clock = clock;
- if(irq_mask)
- ifxmips_pci_req_mask = irq_mask;
-}
-
-/* tapi */
-static struct resource mps_resources[] = {
- {
- .name = "mem",
- .flags = IORESOURCE_MEM,
- .start = 0x1f107000,
- .end = 0x1f1073ff,
- },
- {
- .name = "mailbox",
- .flags = IORESOURCE_MEM,
- .start = 0x1f200000,
- .end = 0x1f2007ff,
- },
-};
-
-static struct platform_device mps_device = {
- .name = "mps",
- .resource = mps_resources,
- .num_resources = ARRAY_SIZE(mps_resources),
-};
-
-static struct platform_device vmmc_device = {
- .name = "vmmc",
- .dev = {
- .parent = &mps_device.dev,
- },
-};
-
-void __init
-danube_register_tapi(void)
-{
-#define CP1_SIZE (1 << 20)
- dma_addr_t dma;
- mps_device.dev.platform_data = CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC));
- platform_device_register(&mps_device);
- platform_device_register(&vmmc_device);
-}
+++ /dev/null
-#ifndef _DANUBE_DEVICES_H__
-#define _DANUBE_DEVICES_H__
-
-#include "../common/devices.h"
-
-enum {
- PCI_CLOCK_INT = 0,
- PCI_CLOCK_EXT
-};
-
-void __init danube_register_ebu_gpio(struct resource *resource, u32 value);
-void __init danube_register_ethernet(unsigned char *mac, int mii_mode);
-void __init danube_register_pci(int clock, int irq_mask);
-void __init danube_register_tapi(void);
-
-#endif
+++ /dev/null
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/timer.h>
-#include <linux/fs.h>
-#include <linux/errno.h>
-#include <linux/stat.h>
-#include <linux/mm.h>
-#include <linux/tty.h>
-#include <linux/selection.h>
-#include <linux/kmod.h>
-#include <linux/vmalloc.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/uaccess.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-
-#include <ifxmips.h>
-#include <ifxmips_irq.h>
-#include <ifxmips_dma.h>
-#include <ifxmips_pmu.h>
-
-/*25 descriptors for each dma channel,4096/8/20=25.xx*/
-#define IFXMIPS_DMA_DESCRIPTOR_OFFSET 25
-
-#define MAX_DMA_DEVICE_NUM 6 /*max ports connecting to dma */
-#define MAX_DMA_CHANNEL_NUM 20 /*max dma channels */
-#define DMA_INT_BUDGET 100 /*budget for interrupt handling */
-#define DMA_POLL_COUNTER 4 /*fix me, set the correct counter value here! */
-
-extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);
-extern void ifxmips_enable_irq(unsigned int irq_nr);
-extern void ifxmips_disable_irq(unsigned int irq_nr);
-
-u64 *g_desc_list;
-struct dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
-struct dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM];
-
-static const char *global_device_name[MAX_DMA_DEVICE_NUM] =
- { "PPE", "DEU", "SPI", "SDIO", "MCTRL0", "MCTRL1" };
-
-struct dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
- {"PPE", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH0_INT, 0},
- {"PPE", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH1_INT, 0},
- {"PPE", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH2_INT, 1},
- {"PPE", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH3_INT, 1},
- {"PPE", IFXMIPS_DMA_RX, 2, IFXMIPS_DMA_CH4_INT, 2},
- {"PPE", IFXMIPS_DMA_TX, 2, IFXMIPS_DMA_CH5_INT, 2},
- {"PPE", IFXMIPS_DMA_RX, 3, IFXMIPS_DMA_CH6_INT, 3},
- {"PPE", IFXMIPS_DMA_TX, 3, IFXMIPS_DMA_CH7_INT, 3},
- {"DEU", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH8_INT, 0},
- {"DEU", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH9_INT, 0},
- {"DEU", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH10_INT, 1},
- {"DEU", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH11_INT, 1},
- {"SPI", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH12_INT, 0},
- {"SPI", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH13_INT, 0},
- {"SDIO", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH14_INT, 0},
- {"SDIO", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH15_INT, 0},
- {"MCTRL0", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH16_INT, 0},
- {"MCTRL0", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH17_INT, 0},
- {"MCTRL1", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH18_INT, 1},
- {"MCTRL1", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH19_INT, 1}
-};
-
-struct dma_chan_map *chan_map = default_dma_map;
-volatile u32 g_ifxmips_dma_int_status;
-volatile int g_ifxmips_dma_in_process; /* 0=not in process, 1=in process */
-
-void do_dma_tasklet(unsigned long);
-DECLARE_TASKLET(dma_tasklet, do_dma_tasklet, 0);
-
-u8 *common_buffer_alloc(int len, int *byte_offset, void **opt)
-{
- u8 *buffer = kmalloc(len * sizeof(u8), GFP_KERNEL);
-
- *byte_offset = 0;
-
- return buffer;
-}
-
-void common_buffer_free(u8 *dataptr, void *opt)
-{
- kfree(dataptr);
-}
-
-void enable_ch_irq(struct dma_channel_info *pCh)
-{
- int chan_no = (int)(pCh - dma_chan);
- unsigned long flag;
-
- local_irq_save(flag);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- ifxmips_w32(0x4a, IFXMIPS_DMA_CIE);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
- local_irq_restore(flag);
- ifxmips_enable_irq(pCh->irq);
-}
-
-void disable_ch_irq(struct dma_channel_info *pCh)
-{
- unsigned long flag;
- int chan_no = (int) (pCh - dma_chan);
-
- local_irq_save(flag);
- g_ifxmips_dma_int_status &= ~(1 << chan_no);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- ifxmips_w32(0, IFXMIPS_DMA_CIE);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);
- local_irq_restore(flag);
- ifxmips_mask_and_ack_irq(pCh->irq);
-}
-
-void open_chan(struct dma_channel_info *pCh)
-{
- unsigned long flag;
- int chan_no = (int)(pCh - dma_chan);
-
- local_irq_save(flag);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 1, IFXMIPS_DMA_CCTRL);
- if (pCh->dir == IFXMIPS_DMA_RX)
- enable_ch_irq(pCh);
- local_irq_restore(flag);
-}
-
-void close_chan(struct dma_channel_info *pCh)
-{
- unsigned long flag;
- int chan_no = (int) (pCh - dma_chan);
-
- local_irq_save(flag);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
- disable_ch_irq(pCh);
- local_irq_restore(flag);
-}
-
-void reset_chan(struct dma_channel_info *pCh)
-{
- int chan_no = (int) (pCh - dma_chan);
-
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
-}
-
-void rx_chan_intr_handler(int chan_no)
-{
- struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
- struct dma_channel_info *pCh = &dma_chan[chan_no];
- struct rx_desc *rx_desc_p;
- int tmp;
- unsigned long flag;
-
- /*handle command complete interrupt */
- rx_desc_p = (struct rx_desc *)pCh->desc_base + pCh->curr_desc;
- if (rx_desc_p->status.field.OWN == CPU_OWN
- && rx_desc_p->status.field.C
- && rx_desc_p->status.field.data_length < 1536){
- /* Every thing is correct, then we inform the upper layer */
- pDev->current_rx_chan = pCh->rel_chan_no;
- if (pDev->intr_handler)
- pDev->intr_handler(pDev, RCV_INT);
- pCh->weight--;
- } else {
- local_irq_save(flag);
- tmp = ifxmips_r32(IFXMIPS_DMA_CS);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
- ifxmips_w32(tmp, IFXMIPS_DMA_CS);
- g_ifxmips_dma_int_status &= ~(1 << chan_no);
- local_irq_restore(flag);
- ifxmips_enable_irq(dma_chan[chan_no].irq);
- }
-}
-
-inline void tx_chan_intr_handler(int chan_no)
-{
- struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
- struct dma_channel_info *pCh = &dma_chan[chan_no];
- int tmp;
- unsigned long flag;
-
- local_irq_save(flag);
- tmp = ifxmips_r32(IFXMIPS_DMA_CS);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
- ifxmips_w32(tmp, IFXMIPS_DMA_CS);
- g_ifxmips_dma_int_status &= ~(1 << chan_no);
- local_irq_restore(flag);
- pDev->current_tx_chan = pCh->rel_chan_no;
- if (pDev->intr_handler)
- pDev->intr_handler(pDev, TRANSMIT_CPT_INT);
-}
-
-void do_dma_tasklet(unsigned long unused)
-{
- int i;
- int chan_no = 0;
- int budget = DMA_INT_BUDGET;
- int weight = 0;
- unsigned long flag;
-
- while (g_ifxmips_dma_int_status) {
- if (budget-- < 0) {
- tasklet_schedule(&dma_tasklet);
- return;
- }
- chan_no = -1;
- weight = 0;
- for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
- if ((g_ifxmips_dma_int_status & (1 << i)) && dma_chan[i].weight > 0) {
- if (dma_chan[i].weight > weight) {
- chan_no = i;
- weight = dma_chan[chan_no].weight;
- }
- }
- }
-
- if (chan_no >= 0) {
- if (chan_map[chan_no].dir == IFXMIPS_DMA_RX)
- rx_chan_intr_handler(chan_no);
- else
- tx_chan_intr_handler(chan_no);
- } else {
- for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
- dma_chan[i].weight = dma_chan[i].default_weight;
- }
- }
-
- local_irq_save(flag);
- g_ifxmips_dma_in_process = 0;
- if (g_ifxmips_dma_int_status) {
- g_ifxmips_dma_in_process = 1;
- tasklet_schedule(&dma_tasklet);
- }
- local_irq_restore(flag);
-}
-
-irqreturn_t dma_interrupt(int irq, void *dev_id)
-{
- struct dma_channel_info *pCh;
- int chan_no = 0;
- int tmp;
-
- pCh = (struct dma_channel_info *)dev_id;
- chan_no = (int)(pCh - dma_chan);
- if (chan_no < 0 || chan_no > 19)
- BUG();
-
- tmp = ifxmips_r32(IFXMIPS_DMA_IRNEN);
- ifxmips_w32(0, IFXMIPS_DMA_IRNEN);
- g_ifxmips_dma_int_status |= 1 << chan_no;
- ifxmips_w32(tmp, IFXMIPS_DMA_IRNEN);
- ifxmips_mask_and_ack_irq(irq);
-
- if (!g_ifxmips_dma_in_process) {
- g_ifxmips_dma_in_process = 1;
- tasklet_schedule(&dma_tasklet);
- }
-
- return IRQ_HANDLED;
-}
-
-struct dma_device_info *dma_device_reserve(char *dev_name)
-{
- int i;
-
- for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
- if (strcmp(dev_name, dma_devs[i].device_name) == 0) {
- if (dma_devs[i].reserved)
- return NULL;
- dma_devs[i].reserved = 1;
- break;
- }
- }
-
- return &dma_devs[i];
-}
-EXPORT_SYMBOL(dma_device_reserve);
-
-void dma_device_release(struct dma_device_info *dev)
-{
- dev->reserved = 0;
-}
-EXPORT_SYMBOL(dma_device_release);
-
-void dma_device_register(struct dma_device_info *dev)
-{
- int i, j;
- int chan_no = 0;
- u8 *buffer;
- int byte_offset;
- unsigned long flag;
- struct dma_device_info *pDev;
- struct dma_channel_info *pCh;
- struct rx_desc *rx_desc_p;
- struct tx_desc *tx_desc_p;
-
- for (i = 0; i < dev->max_tx_chan_num; i++) {
- pCh = dev->tx_chan[i];
- if (pCh->control == IFXMIPS_DMA_CH_ON) {
- chan_no = (int)(pCh - dma_chan);
- for (j = 0; j < pCh->desc_len; j++) {
- tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
- memset(tx_desc_p, 0, sizeof(struct tx_desc));
- }
- local_irq_save(flag);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- /* check if the descriptor length is changed */
- if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
- ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN);
-
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
- while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2)
- ;
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
- ifxmips_w32(0x30100, IFXMIPS_DMA_CCTRL); /* reset and enable channel,enable channel later */
- local_irq_restore(flag);
- }
- }
-
- for (i = 0; i < dev->max_rx_chan_num; i++) {
- pCh = dev->rx_chan[i];
- if (pCh->control == IFXMIPS_DMA_CH_ON) {
- chan_no = (int)(pCh - dma_chan);
-
- for (j = 0; j < pCh->desc_len; j++) {
- rx_desc_p = (struct rx_desc *)pCh->desc_base + j;
- pDev = (struct dma_device_info *)(pCh->dma_dev);
- buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void *)&(pCh->opt[j]));
- if (!buffer)
- break;
-
- dma_cache_inv((unsigned long) buffer, pCh->packet_size);
-
- rx_desc_p->Data_Pointer = (u32)CPHYSADDR((u32)buffer);
- rx_desc_p->status.word = 0;
- rx_desc_p->status.field.byte_offset = byte_offset;
- rx_desc_p->status.field.OWN = DMA_OWN;
- rx_desc_p->status.field.data_length = pCh->packet_size;
- }
-
- local_irq_save(flag);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- /* check if the descriptor length is changed */
- if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
- ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
- while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2)
- ;
- ifxmips_w32(0x0a, IFXMIPS_DMA_CIE); /* fix me, should enable all the interrupts here? */
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
- ifxmips_w32(0x30000, IFXMIPS_DMA_CCTRL);
- local_irq_restore(flag);
- ifxmips_enable_irq(dma_chan[chan_no].irq);
- }
- }
-}
-EXPORT_SYMBOL(dma_device_register);
-
-void dma_device_unregister(struct dma_device_info *dev)
-{
- int i, j;
- int chan_no;
- struct dma_channel_info *pCh;
- struct rx_desc *rx_desc_p;
- struct tx_desc *tx_desc_p;
- unsigned long flag;
-
- for (i = 0; i < dev->max_tx_chan_num; i++) {
- pCh = dev->tx_chan[i];
- if (pCh->control == IFXMIPS_DMA_CH_ON) {
- chan_no = (int)(dev->tx_chan[i] - dma_chan);
- local_irq_save(flag);
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- pCh->curr_desc = 0;
- pCh->prev_desc = 0;
- pCh->control = IFXMIPS_DMA_CH_OFF;
- ifxmips_w32(0, IFXMIPS_DMA_CIE); /* fix me, should disable all the interrupts here? */
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /* disable interrupts */
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
- while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1)
- ;
- local_irq_restore(flag);
-
- for (j = 0; j < pCh->desc_len; j++) {
- tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
- if ((tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C)
- || (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0)) {
- dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), (void *)pCh->opt[j]);
- }
- tx_desc_p->status.field.OWN = CPU_OWN;
- memset(tx_desc_p, 0, sizeof(struct tx_desc));
- }
- /* TODO should free buffer that is not transferred by dma */
- }
- }
-
- for (i = 0; i < dev->max_rx_chan_num; i++) {
- pCh = dev->rx_chan[i];
- chan_no = (int)(dev->rx_chan[i] - dma_chan);
- ifxmips_disable_irq(pCh->irq);
-
- local_irq_save(flag);
- g_ifxmips_dma_int_status &= ~(1 << chan_no);
- pCh->curr_desc = 0;
- pCh->prev_desc = 0;
- pCh->control = IFXMIPS_DMA_CH_OFF;
-
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- ifxmips_w32(0, IFXMIPS_DMA_CIE); /* fix me, should disable all the interrupts here? */
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /* disable interrupts */
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
- while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1)
- ;
-
- local_irq_restore(flag);
- for (j = 0; j < pCh->desc_len; j++) {
- rx_desc_p = (struct rx_desc *) pCh->desc_base + j;
- if ((rx_desc_p->status.field.OWN == CPU_OWN
- && rx_desc_p->status.field.C)
- || (rx_desc_p->status.field.OWN == DMA_OWN
- && rx_desc_p->status.field.data_length > 0)) {
- dev->buffer_free((u8 *)
- __va(rx_desc_p->Data_Pointer),
- (void *) pCh->opt[j]);
- }
- }
- }
-}
-EXPORT_SYMBOL(dma_device_unregister);
-
-int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt)
-{
- u8 *buf;
- int len;
- int byte_offset = 0;
- void *p = NULL;
- struct dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan];
- struct rx_desc *rx_desc_p;
-
- /* get the rx data first */
- rx_desc_p = (struct rx_desc *) pCh->desc_base + pCh->curr_desc;
- if (!(rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C))
- return 0;
-
- buf = (u8 *) __va(rx_desc_p->Data_Pointer);
- *(u32 *)dataptr = (u32)buf;
- len = rx_desc_p->status.field.data_length;
-
- if (opt)
- *(int *)opt = (int)pCh->opt[pCh->curr_desc];
-
- /* replace with a new allocated buffer */
- buf = dma_dev->buffer_alloc(pCh->packet_size, &byte_offset, &p);
-
- if (buf) {
- dma_cache_inv((unsigned long) buf, pCh->packet_size);
- pCh->opt[pCh->curr_desc] = p;
- wmb();
-
- rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buf);
- rx_desc_p->status.word = (DMA_OWN << 31) | ((byte_offset) << 23) | pCh->packet_size;
- wmb();
- } else {
- *(u32 *) dataptr = 0;
- if (opt)
- *(int *) opt = 0;
- len = 0;
- }
-
- /* increase the curr_desc pointer */
- pCh->curr_desc++;
- if (pCh->curr_desc == pCh->desc_len)
- pCh->curr_desc = 0;
-
- return len;
-}
-EXPORT_SYMBOL(dma_device_read);
-
-int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, void *opt)
-{
- unsigned long flag;
- u32 tmp, byte_offset;
- struct dma_channel_info *pCh;
- int chan_no;
- struct tx_desc *tx_desc_p;
- local_irq_save(flag);
-
- pCh = dma_dev->tx_chan[dma_dev->current_tx_chan];
- chan_no = (int)(pCh - (struct dma_channel_info *) dma_chan);
-
- tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
- while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) {
- dma_dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), pCh->opt[pCh->prev_desc]);
- memset(tx_desc_p, 0, sizeof(struct tx_desc));
- pCh->prev_desc = (pCh->prev_desc + 1) % (pCh->desc_len);
- tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
- }
- tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->curr_desc;
- /* Check whether this descriptor is available */
- if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C) {
- /* if not, the tell the upper layer device */
- dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
- local_irq_restore(flag);
- printk(KERN_INFO "%s %d: failed to write!\n", __func__, __LINE__);
-
- return 0;
- }
- pCh->opt[pCh->curr_desc] = opt;
- /* byte offset----to adjust the starting address of the data buffer, should be multiple of the burst length. */
- byte_offset = ((u32) CPHYSADDR((u32) dataptr)) % ((dma_dev->tx_burst_len) * 4);
- dma_cache_wback((unsigned long) dataptr, len);
- wmb();
- tx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) dataptr) - byte_offset;
- wmb();
- tx_desc_p->status.word = (DMA_OWN << 31) | DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | ((byte_offset) << 23) | len;
- wmb();
-
- pCh->curr_desc++;
- if (pCh->curr_desc == pCh->desc_len)
- pCh->curr_desc = 0;
-
- /*Check whether this descriptor is available */
- tx_desc_p = (struct tx_desc *) pCh->desc_base + pCh->curr_desc;
- if (tx_desc_p->status.field.OWN == DMA_OWN) {
- /*if not , the tell the upper layer device */
- dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
- }
-
- ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
- tmp = ifxmips_r32(IFXMIPS_DMA_CCTRL);
-
- if (!(tmp & 1))
- pCh->open(pCh);
-
- local_irq_restore(flag);
-
- return len;
-}
-EXPORT_SYMBOL(dma_device_write);
-
-int map_dma_chan(struct dma_chan_map *map)
-{
- int i, j;
- int result;
-
- for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
- strcpy(dma_devs[i].device_name, global_device_name[i]);
-
- for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
- dma_chan[i].irq = map[i].irq;
- result = request_irq(dma_chan[i].irq, dma_interrupt, IRQF_DISABLED, map[i].dev_name, (void *)&dma_chan[i]);
- if (result) {
- printk(KERN_WARNING "error, cannot get dma_irq!\n");
- free_irq(dma_chan[i].irq, (void *) &dma_interrupt);
-
- return -EFAULT;
- }
- }
-
- for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
- dma_devs[i].num_tx_chan = 0; /*set default tx channel number to be one */
- dma_devs[i].num_rx_chan = 0; /*set default rx channel number to be one */
- dma_devs[i].max_rx_chan_num = 0;
- dma_devs[i].max_tx_chan_num = 0;
- dma_devs[i].buffer_alloc = &common_buffer_alloc;
- dma_devs[i].buffer_free = &common_buffer_free;
- dma_devs[i].intr_handler = NULL;
- dma_devs[i].tx_burst_len = 4;
- dma_devs[i].rx_burst_len = 4;
- if (i == 0) {
- ifxmips_w32(0, IFXMIPS_DMA_PS);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), IFXMIPS_DMA_PCTRL); /*enable dma drop */
- }
-
- if (i == 1) {
- ifxmips_w32(1, IFXMIPS_DMA_PS);
- ifxmips_w32(0x14, IFXMIPS_DMA_PCTRL); /*deu port setting */
- }
-
- for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
- dma_chan[j].byte_offset = 0;
- dma_chan[j].open = &open_chan;
- dma_chan[j].close = &close_chan;
- dma_chan[j].reset = &reset_chan;
- dma_chan[j].enable_irq = &enable_ch_irq;
- dma_chan[j].disable_irq = &disable_ch_irq;
- dma_chan[j].rel_chan_no = map[j].rel_chan_no;
- dma_chan[j].control = IFXMIPS_DMA_CH_OFF;
- dma_chan[j].default_weight = IFXMIPS_DMA_CH_DEFAULT_WEIGHT;
- dma_chan[j].weight = dma_chan[j].default_weight;
- dma_chan[j].curr_desc = 0;
- dma_chan[j].prev_desc = 0;
- }
-
- for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
- if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0) {
- if (map[j].dir == IFXMIPS_DMA_RX) {
- dma_chan[j].dir = IFXMIPS_DMA_RX;
- dma_devs[i].max_rx_chan_num++;
- dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j];
- dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri;
- dma_chan[j].dma_dev = (void *)&dma_devs[i];
- } else if (map[j].dir == IFXMIPS_DMA_TX) {
- /*TX direction */
- dma_chan[j].dir = IFXMIPS_DMA_TX;
- dma_devs[i].max_tx_chan_num++;
- dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j];
- dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri;
- dma_chan[j].dma_dev = (void *)&dma_devs[i];
- } else {
- printk(KERN_WARNING "WRONG DMA MAP!\n");
- }
- }
- }
- }
-
- return 0;
-}
-
-void dma_chip_init(void)
-{
- int i;
-
- /* enable DMA from PMU */
- ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
-
- /* reset DMA */
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CTRL) | 1, IFXMIPS_DMA_CTRL);
-
- /* disable all interrupts */
- ifxmips_w32(0, IFXMIPS_DMA_IRNEN);
-
- for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
- ifxmips_w32(i, IFXMIPS_DMA_CS);
- ifxmips_w32(0x2, IFXMIPS_DMA_CCTRL);
- ifxmips_w32(0x80000040, IFXMIPS_DMA_CPOLL);
- ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~0x1, IFXMIPS_DMA_CCTRL);
- }
-}
-
-int ifxmips_dma_init(void)
-{
- int i;
-
- dma_chip_init();
- if (map_dma_chan(default_dma_map))
- BUG();
-
- g_desc_list = (u64 *)KSEG1ADDR(__get_free_page(GFP_DMA));
-
- if (g_desc_list == NULL) {
- printk(KERN_WARNING "no memory for desriptor\n");
- return -ENOMEM;
- }
-
- memset(g_desc_list, 0, PAGE_SIZE);
-
- for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
- dma_chan[i].desc_base = (u32)g_desc_list + i * IFXMIPS_DMA_DESCRIPTOR_OFFSET * 8;
- dma_chan[i].curr_desc = 0;
- dma_chan[i].desc_len = IFXMIPS_DMA_DESCRIPTOR_OFFSET;
-
- ifxmips_w32(i, IFXMIPS_DMA_CS);
- ifxmips_w32((u32)CPHYSADDR(dma_chan[i].desc_base), IFXMIPS_DMA_CDBA);
- ifxmips_w32(dma_chan[i].desc_len, IFXMIPS_DMA_CDLEN);
- }
-
- return 0;
-}
-
-arch_initcall(ifxmips_dma_init);
-
-void dma_cleanup(void)
-{
- int i;
-
- free_page(KSEG0ADDR((unsigned long) g_desc_list));
- for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
- free_irq(dma_chan[i].irq, (void *)&dma_interrupt);
-}
-
-MODULE_LICENSE("GPL");
+++ /dev/null
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/platform_device.h>
-#include <linux/mutex.h>
-#include <linux/gpio.h>
-
-#include <ifxmips.h>
-#include <ifxmips_ebu.h>
-
-#define IFXMIPS_EBU_BUSCON 0x1e7ff
-#define IFXMIPS_EBU_WP 0x80000000
-
-static int shadow = 0;
-static void __iomem *virt;
-
-static int
-ifxmips_ebu_direction_output(struct gpio_chip *chip, unsigned offset, int value)
-{
- return 0;
-}
-
-static void
-ifxmips_ebu_set(struct gpio_chip *chip, unsigned offset, int value)
-{
- unsigned long flags;
- if(value)
- shadow |= (1 << offset);
- else
- shadow &= ~(1 << offset);
- spin_lock_irqsave(&ebu_lock, flags);
- ifxmips_w32(IFXMIPS_EBU_BUSCON, IFXMIPS_EBU_BUSCON1);
- *((__u16*)virt) = shadow;
- ifxmips_w32(IFXMIPS_EBU_BUSCON | IFXMIPS_EBU_WP, IFXMIPS_EBU_BUSCON1);
- spin_unlock_irqrestore(&ebu_lock, flags);
-}
-
-static struct gpio_chip
-ifxmips_ebu_chip =
-{
- .label = "ifxmips_ebu",
- .direction_output = ifxmips_ebu_direction_output,
- .set = ifxmips_ebu_set,
- .base = 32,
- .ngpio = 16,
- .can_sleep = 1,
- .owner = THIS_MODULE,
-};
-
-static int __devinit
-ifxmips_ebu_probe(struct platform_device *pdev)
-{
- ifxmips_w32(pdev->resource->start | 0x1, IFXMIPS_EBU_ADDRSEL1);
- ifxmips_w32(IFXMIPS_EBU_BUSCON | IFXMIPS_EBU_WP, IFXMIPS_EBU_BUSCON1);
- virt = ioremap_nocache(pdev->resource->start, pdev->resource->end);
- if(gpiochip_add(&ifxmips_ebu_chip))
- return -EINVAL;
- shadow = (int) pdev->dev.platform_data;
- printk("IFXMIPS: ebu-gpio loaded\n");
- return 0;
-}
-
-static int
-ifxmips_ebu_remove(struct platform_device *dev)
-{
- return gpiochip_remove(&ifxmips_ebu_chip);
-}
-
-static struct platform_driver
-ifxmips_ebu_driver = {
- .probe = ifxmips_ebu_probe,
- .remove = ifxmips_ebu_remove,
- .driver = {
- .name = "ifxmips_ebu",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init
-ifxmips_ebu_init(void)
-{
- return platform_driver_register(&ifxmips_ebu_driver);
-}
-
-static void __exit
-ifxmips_ebu_exit(void)
-{
- platform_driver_unregister(&ifxmips_ebu_driver);
-}
-
-module_init(ifxmips_ebu_init);
-module_exit(ifxmips_ebu_exit);
-
-MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("ifxmips - EBU Latch GPIO-Expander");
+++ /dev/null
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-
-#include <asm/bootinfo.h>
-#include <asm/irq.h>
-#include <asm/irq_cpu.h>
-
-#include <ifxmips.h>
-#include <ifxmips_irq.h>
-
-void
-ifxmips_disable_irq(unsigned int irq_nr)
-{
- int i;
- u32 *ier = IFXMIPS_ICU_IM0_IER;
-
- irq_nr -= INT_NUM_IRQ0;
- for (i = 0; i <= 4; i++)
- {
- if (irq_nr < INT_NUM_IM_OFFSET)
- {
- ifxmips_w32(ifxmips_r32(ier) & ~(1 << irq_nr), ier);
- return;
- }
- ier += IFXMIPS_ICU_OFFSET;
- irq_nr -= INT_NUM_IM_OFFSET;
- }
-}
-EXPORT_SYMBOL(ifxmips_disable_irq);
-
-void
-ifxmips_mask_and_ack_irq(unsigned int irq_nr)
-{
- int i;
- u32 *ier = IFXMIPS_ICU_IM0_IER;
- u32 *isr = IFXMIPS_ICU_IM0_ISR;
-
- irq_nr -= INT_NUM_IRQ0;
- for (i = 0; i <= 4; i++)
- {
- if (irq_nr < INT_NUM_IM_OFFSET)
- {
- ifxmips_w32(ifxmips_r32(ier) & ~(1 << irq_nr), ier);
- ifxmips_w32((1 << irq_nr), isr);
- return;
- }
- ier += IFXMIPS_ICU_OFFSET;
- isr += IFXMIPS_ICU_OFFSET;
- irq_nr -= INT_NUM_IM_OFFSET;
- }
-}
-EXPORT_SYMBOL(ifxmips_mask_and_ack_irq);
-
-static void
-ifxmips_ack_irq(unsigned int irq_nr)
-{
- int i;
- u32 *isr = IFXMIPS_ICU_IM0_ISR;
-
- irq_nr -= INT_NUM_IRQ0;
- for (i = 0; i <= 4; i++)
- {
- if (irq_nr < INT_NUM_IM_OFFSET)
- {
- ifxmips_w32((1 << irq_nr), isr);
- return;
- }
- isr += IFXMIPS_ICU_OFFSET;
- irq_nr -= INT_NUM_IM_OFFSET;
- }
-}
-
-
-void
-ifxmips_enable_irq(unsigned int irq_nr)
-{
- int i;
- u32 *ier = IFXMIPS_ICU_IM0_IER;
-
- irq_nr -= INT_NUM_IRQ0;
- for (i = 0; i <= 4; i++)
- {
- if (irq_nr < INT_NUM_IM_OFFSET)
- {
- ifxmips_w32(ifxmips_r32(ier) | (1 << irq_nr), ier);
- return;
- }
- ier += IFXMIPS_ICU_OFFSET;
- irq_nr -= INT_NUM_IM_OFFSET;
- }
-}
-EXPORT_SYMBOL(ifxmips_enable_irq);
-
-static unsigned int
-ifxmips_startup_irq(unsigned int irq)
-{
- ifxmips_enable_irq(irq);
- return 0;
-}
-
-static void
-ifxmips_end_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
- ifxmips_enable_irq(irq);
-}
-
-static struct irq_chip
-ifxmips_irq_type = {
- "ifxmips",
- .startup = ifxmips_startup_irq,
- .enable = ifxmips_enable_irq,
- .disable = ifxmips_disable_irq,
- .unmask = ifxmips_enable_irq,
- .ack = ifxmips_ack_irq,
- .mask = ifxmips_disable_irq,
- .mask_ack = ifxmips_mask_and_ack_irq,
- .end = ifxmips_end_irq,
-};
-
-/* silicon bug causes only the msb set to 1 to be valid. all
- other bits might be bogus */
-static inline int
-ls1bit32(unsigned long x)
-{
- __asm__ (
- ".set push \n"
- ".set mips32 \n"
- "clz %0, %1 \n"
- ".set pop \n"
- : "=r" (x)
- : "r" (x));
- return 31 - x;
-}
-
-static void
-ifxmips_hw_irqdispatch(int module)
-{
- u32 irq;
-
- irq = ifxmips_r32(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
- if (irq == 0)
- return;
-
- /* we need to do this due to a silicon bug */
- irq = ls1bit32(irq);
- do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
-
- if ((irq == 22) && (module == 0))
- ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10,
- IFXMIPS_EBU_PCC_ISTAT);
-}
-
-#ifdef CONFIG_CPU_MIPSR2_IRQ_VI
-#define DEFINE_HWx_IRQDISPATCH(x) \
-static void ifxmips_hw ## x ## _irqdispatch(void)\
-{\
- ifxmips_hw_irqdispatch(x); \
-}
-static void ifxmips_hw5_irqdispatch(void)
-{
- do_IRQ(MIPS_CPU_TIMER_IRQ);
-}
-DEFINE_HWx_IRQDISPATCH(0)
-DEFINE_HWx_IRQDISPATCH(1)
-DEFINE_HWx_IRQDISPATCH(2)
-DEFINE_HWx_IRQDISPATCH(3)
-DEFINE_HWx_IRQDISPATCH(4)
-/*DEFINE_HWx_IRQDISPATCH(5)*/
-#endif /* #ifdef CONFIG_CPU_MIPSR2_IRQ_VI */
-
-asmlinkage void
-plat_irq_dispatch(void)
-{
- unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
- unsigned int i;
-
- if (pending & CAUSEF_IP7)
- {
- do_IRQ(MIPS_CPU_TIMER_IRQ);
- goto out;
- } else {
- for (i = 0; i < 5; i++)
- {
- if (pending & (CAUSEF_IP2 << i))
- {
- ifxmips_hw_irqdispatch(i);
- goto out;
- }
- }
- }
- printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
-
-out:
- return;
-}
-
-static struct irqaction
-cascade = {
- .handler = no_action,
- .flags = IRQF_DISABLED,
- .name = "cascade",
-};
-
-void __init
-arch_init_irq(void)
-{
- int i;
-
- for (i = 0; i < 5; i++)
- ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
-
- mips_cpu_irq_init();
-
- for (i = 2; i <= 6; i++)
- setup_irq(i, &cascade);
-
-#ifdef CONFIG_CPU_MIPSR2_IRQ_VI
- if (cpu_has_vint) {
- printk(KERN_INFO "Setting up vectored interrupts\n");
- set_vi_handler(2, ifxmips_hw0_irqdispatch);
- set_vi_handler(3, ifxmips_hw1_irqdispatch);
- set_vi_handler(4, ifxmips_hw2_irqdispatch);
- set_vi_handler(5, ifxmips_hw3_irqdispatch);
- set_vi_handler(6, ifxmips_hw4_irqdispatch);
- set_vi_handler(7, ifxmips_hw5_irqdispatch);
- }
-#endif
-
- for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
- set_irq_chip_and_handler(i, &ifxmips_irq_type,
- handle_level_irq);
-
- #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
- set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
- IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
- #else
- set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
- IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
- #endif
-}
-
-void __cpuinit
-arch_fixup_c0_irqs(void)
-{
- /* FIXME: check for CPUID and only do fix for specific chips/versions */
- cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
- cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
-}
+++ /dev/null
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/gpio_buttons.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/input.h>
-#include <linux/etherdevice.h>
-
-#include <machine.h>
-#include <ifxmips.h>
-#include <ifxmips_prom.h>
-
-#include "arcaydian.h"
-#include "devices.h"
-
-#define ARV45XX_BRN 0x3f0000
-#define ARV45XX_BRN_MAC 0x3f0016
-
-#define ARV45XX_EBU_GPIO_START 0x14000000
-#define ARV45XX_EBU_GPIO_SIZE 0x00001000
-
-#define ARV4520_LATCH_SWITCH (1 << 10)
-
-#ifdef CONFIG_MTD_PARTITIONS
-static struct mtd_partition arv45xx_partitions[] =
-{
- {
- .name = "uboot",
- .offset = 0x0,
- .size = 0x20000,
- },
- {
- .name = "uboot_env",
- .offset = 0x20000,
- .size = 0x0,
- },
- {
- .name = "kernel",
- .offset = 0x0,
- .size = 0x0,
- },
- {
- .name = "rootfs",
- .offset = 0x0,
- .size = 0x0,
- },
- {
- .name = "board_config",
- .offset = 0x3f0000,
- .size = 0x10000,
- },
- {
- .name = "openwrt",
- .offset = 0x0,
- .size = 0x0,
- },
-};
-#endif
-
-static struct physmap_flash_data arv45xx_flash_data = {
-#ifdef CONFIG_MTD_PARTITIONS
- .nr_parts = ARRAY_SIZE(arv45xx_partitions),
- .parts = arv45xx_partitions,
-#endif
-};
-
-static struct gpio_led
-arv4518_leds_gpio[] __initdata = {
- { .name = "ifx:blue:power", .gpio = 3, .active_low = 1, },
- { .name = "ifx:blue:adsl", .gpio = 4, .active_low = 1, },
- { .name = "ifx:blue:internet", .gpio = 5, .active_low = 1, },
- { .name = "ifx:red:power", .gpio = 6, .active_low = 1, },
- { .name = "ifx:yello:wps", .gpio = 7, .active_low = 1, },
- { .name = "ifx:red:wps", .gpio = 9, .active_low = 1, },
- { .name = "ifx:blue:voip", .gpio = 32, .active_low = 1, },
- { .name = "ifx:blue:fxs1", .gpio = 33, .active_low = 1, },
- { .name = "ifx:blue:fxs2", .gpio = 34, .active_low = 1, },
- { .name = "ifx:blue:fxo", .gpio = 35, .active_low = 1, },
- { .name = "ifx:blue:voice", .gpio = 36, .active_low = 1, },
- { .name = "ifx:blue:usb", .gpio = 37, .active_low = 1, },
- { .name = "ifx:blue:wlan", .gpio = 38, .active_low = 1, },
-};
-
-static struct gpio_led
-arv4520_leds_gpio[] __initdata = {
- { .name = "ifx:blue:power", .gpio = 3, .active_low = 1, },
- { .name = "ifx:blue:adsl", .gpio = 4, .active_low = 1, },
- { .name = "ifx:blue:internet", .gpio = 5, .active_low = 1, },
- { .name = "ifx:red:power", .gpio = 6, .active_low = 1, },
- { .name = "ifx:yello:wps", .gpio = 7, .active_low = 1, },
- { .name = "ifx:red:wps", .gpio = 9, .active_low = 1, },
- { .name = "ifx:blue:voip", .gpio = 32, .active_low = 1, },
- { .name = "ifx:blue:fxs1", .gpio = 33, .active_low = 1, },
- { .name = "ifx:blue:fxs2", .gpio = 34, .active_low = 1, },
- { .name = "ifx:blue:fxo", .gpio = 35, .active_low = 1, },
- { .name = "ifx:blue:voice", .gpio = 36, .active_low = 1, },
- { .name = "ifx:blue:usb", .gpio = 37, .active_low = 1, },
- { .name = "ifx:blue:wlan", .gpio = 38, .active_low = 1, },
-};
-
-static struct gpio_led arv4525_leds_gpio[] __initdata = {
- { .name = "ifx:green:festnetz", .gpio = 4, .active_low = 1, },
- { .name = "ifx:green:internet", .gpio = 5, .active_low = 1, },
- { .name = "ifx:green:dsl", .gpio = 6, .active_low = 1, },
- { .name = "ifx:green:wlan", .gpio = 8, .active_low = 1, },
- { .name = "ifx:green:online", .gpio = 9, .active_low = 1, },
-};
-
-static struct resource arv45xx_ebu_resource =
-{
- .name = "ebu-gpio",
- .start = ARV45XX_EBU_GPIO_START,
- .end = ARV45XX_EBU_GPIO_START + ARV45XX_EBU_GPIO_SIZE - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static void __init
-arv4518_init(void)
-{
- static unsigned char mac[6];
- if(!ifxmix_detect_brn_block(ARV45XX_BRN))
- ifxmips_find_brn_mac(ARV45XX_BRN_MAC, mac);
- else
- random_ether_addr(mac);
- ifxmips_register_gpio();
- danube_register_ebu_gpio(&arv45xx_ebu_resource, ARV4520_LATCH_SWITCH);
- ifxmips_register_mtd(&arv45xx_flash_data);
- danube_register_pci(PCI_CLOCK_EXT, 0);
- ifxmips_register_wdt();
- ifxmips_register_gpio_leds(arv4518_leds_gpio, ARRAY_SIZE(arv4518_leds_gpio));
- danube_register_ethernet(mac, REV_MII_MODE);
- danube_register_tapi();
-}
-
-MIPS_MACHINE(IFXMIPS_MACH_ARV4518,
- "ARV4518",
- "ARV4518 - SMC7908A-ISP",
- arv4518_init);
-
-static void __init
-arv4520_init(void)
-{
- static unsigned char mac[6];
- if(!ifxmix_detect_brn_block(ARV45XX_BRN))
- ifxmips_find_brn_mac(ARV45XX_BRN_MAC, mac);
- else
- random_ether_addr(mac);
- ifxmips_register_gpio();
- danube_register_ebu_gpio(&arv45xx_ebu_resource, ARV4520_LATCH_SWITCH);
- ifxmips_register_mtd(&arv45xx_flash_data);
- danube_register_pci(PCI_CLOCK_EXT, 0);
- ifxmips_register_wdt();
- ifxmips_register_gpio_leds(arv4520_leds_gpio, ARRAY_SIZE(arv4520_leds_gpio));
- danube_register_ethernet(mac, REV_MII_MODE);
- danube_register_tapi();
-}
-
-MIPS_MACHINE(IFXMIPS_MACH_ARV4520,
- "ARV452",
- "ARV4520 - Airties WAV-281, Arcor A800",
- arv4520_init);
-
-static void __init
-arv4525_init(void)
-{
- static unsigned char mac[6];
- if(!ifxmix_detect_brn_block(ARV45XX_BRN))
- ifxmips_find_brn_mac(ARV45XX_BRN_MAC, mac);
- else
- random_ether_addr(mac);
- ifxmips_register_gpio();
- ifxmips_register_mtd(&arv45xx_flash_data);
- danube_register_pci(PCI_CLOCK_INT, 0);
- ifxmips_register_wdt();
- ifxmips_register_gpio_leds(arv4525_leds_gpio, ARRAY_SIZE(arv4525_leds_gpio));
- danube_register_ethernet(mac, MII_MODE);
- danube_register_tapi();
-}
-
-MIPS_MACHINE(IFXMIPS_MACH_ARV4525,
- "ARV4525",
- "ARV4525 - Speedport W502V",
- arv4525_init);
+++ /dev/null
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/gpio_buttons.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/input.h>
-
-#include <machine.h>
-#include <ifxmips.h>
-#include <ifxmips_prom.h>
-
-#include "devices.h"
-
-extern unsigned char ifxmips_ethaddr[6];
-
-#ifdef CONFIG_MTD_PARTITIONS
-static struct mtd_partition easy4010_partitions[] =
-{
- {
- .name = "uboot",
- .offset = 0x0,
- .size = 0x40000,
- },
- {
- .name = "uboot_env",
- .offset = 0x40000,
- .size = 0x10000,
- },
- {
- .name = "kernel",
- .offset = 0x0,
- .size = 0x0,
- },
- {
- .name = "rootfs",
- .offset = 0x0,
- .size = 0x0,
- }
-};
-#endif
-
-static struct physmap_flash_data easy4010_flash_data = {
-#ifdef CONFIG_MTD_PARTITIONS
- .nr_parts = ARRAY_SIZE(easy4010_partitions),
- .parts = easy4010_partitions,
-#endif
-};
-
-static struct gpio_led easy4010_leds[] = {
- { .name = "ifx:green:test0", .gpio = 0,},
- { .name = "ifx:green:test1", .gpio = 1,},
- { .name = "ifx:green:test2", .gpio = 2,},
- { .name = "ifx:green:test3", .gpio = 3,},
-};
-
-static void __init
-easy4010_init(void)
-{
- ifxmips_register_gpio();
- ifxmips_register_mtd(&easy4010_flash_data);
- ifxmips_register_leds(easy4010_leds, ARRAY_SIZE(easy4010_leds));
- ifxmips_register_wdt();
- danube_register_ethernet(ifxmips_ethaddr, REV_MII_MODE);
-}
-
-MIPS_MACHINE(IFXMIPS_MACH_EASY4010,
- "EASY4010",
- "Lantiq Twinpass Eval Board",
- easy4010_init);
+++ /dev/null
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/gpio_buttons.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/input.h>
-
-#include <machine.h>
-#include <ifxmips.h>
-#include <ifxmips_prom.h>
-
-#include "devices.h"
-
-extern unsigned char ifxmips_ethaddr[6];
-
-#ifdef CONFIG_MTD_PARTITIONS
-static struct mtd_partition easy50712_partitions[] =
-{
- {
- .name = "uboot",
- .offset = 0x0,
- .size = 0x40000,
- },
- {
- .name = "uboot_env",
- .offset = 0x40000,
- .size = 0x10000,
- },
- {
- .name = "kernel",
- .offset = 0x0,
- .size = 0x0,
- },
- {
- .name = "rootfs",
- .offset = 0x0,
- .size = 0x0,
- }
-};
-#endif
-
-static struct physmap_flash_data easy50712_flash_data = {
-#ifdef CONFIG_MTD_PARTITIONS
- .nr_parts = ARRAY_SIZE(easy50712_partitions),
- .parts = easy50712_partitions,
-#endif
-};
-
-static struct gpio_led easy50712_leds[] = {
- { .name = "ifx:green:test0", .gpio = 0,},
- { .name = "ifx:green:test1", .gpio = 1,},
- { .name = "ifx:green:test2", .gpio = 2,},
- { .name = "ifx:green:test3", .gpio = 3,},
-};
-
-static void __init
-easy50712_init(void)
-{
- ifxmips_register_gpio();
- ifxmips_register_mtd(&easy50712_flash_data);
- ifxmips_register_leds(easy50712_leds, ARRAY_SIZE(easy50712_leds));
- ifxmips_register_wdt();
- danube_register_ethernet(ifxmips_ethaddr, REV_MII_MODE);
-}
-
-MIPS_MACHINE(IFXMIPS_MACH_EASY50712,
- "EASY50712",
- "Lantiq Eval Board",
- easy50712_init);
+++ /dev/null
-#include <linux/cpu.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/pm.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <asm/reboot.h>
-#include <asm/system.h>
-#include <ifxmips.h>
-#include <ifxmips_cgu.h>
-
-#define SYSTEM_DANUBE "Danube"
-#define SYSTEM_DANUBE_CHIPID1 0x00129083
-#define SYSTEM_DANUBE_CHIPID2 0x0012B083
-
-#define SYSTEM_TWINPASS "Twinpass"
-#define SYSTEM_TWINPASS_CHIPID 0x0012D083
-
-static unsigned int chiprev = 0;
-unsigned char ifxmips_sys_type[IFXMIPS_SYS_TYPE_LEN];
-
-unsigned int
-ifxmips_get_cpu_ver(void)
-{
- return (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0xF0000000) >> 28;
-}
-EXPORT_SYMBOL(ifxmips_get_cpu_ver);
-
-const char*
-get_system_type(void)
-{
- return ifxmips_sys_type;
-}
-
-static void
-ifxmips_machine_restart(char *command)
-{
- printk(KERN_NOTICE "System restart\n");
- local_irq_disable();
- ifxmips_w32(ifxmips_r32(IFXMIPS_RCU_RST) | IFXMIPS_RCU_RST_ALL,
- IFXMIPS_RCU_RST);
- for(;;);
-}
-
-static void
-ifxmips_machine_halt(void)
-{
- printk(KERN_NOTICE "System halted.\n");
- local_irq_disable();
- for(;;);
-}
-
-static void
-ifxmips_machine_power_off(void)
-{
- printk(KERN_NOTICE "Please turn off the power now.\n");
- local_irq_disable();
- for(;;);
-}
-
-void __init
-ifxmips_soc_setup(void)
-{
- char *name = SYSTEM_DANUBE;
- ioport_resource.start = IOPORT_RESOURCE_START;
- ioport_resource.end = IOPORT_RESOURCE_END;
- iomem_resource.start = IOMEM_RESOURCE_START;
- iomem_resource.end = IOMEM_RESOURCE_END;
-
- _machine_restart = ifxmips_machine_restart;
- _machine_halt = ifxmips_machine_halt;
- pm_power_off = ifxmips_machine_power_off;
-
- chiprev = (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0x0FFFFFFF);
-
- switch (chiprev)
- {
- case SYSTEM_DANUBE_CHIPID1:
- case SYSTEM_DANUBE_CHIPID2:
- name = SYSTEM_DANUBE;
- break;
-
- case SYSTEM_TWINPASS_CHIPID:
- name = SYSTEM_TWINPASS;
- break;
-
- default:
- printk(KERN_ERR "This is not a danube chiprev : 0x%08X\n", chiprev);
- BUG();
- break;
- }
- snprintf(ifxmips_sys_type, IFXMIPS_SYS_TYPE_LEN - 1, "%s rev1.%d %dMhz",
- name, ifxmips_get_cpu_ver(),
- ifxmips_get_cpu_hz() / 1000000);
- ifxmips_sys_type[IFXMIPS_SYS_TYPE_LEN - 1] = '\0';
-}
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2005 infineon
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-#ifndef _IFXMIPS_H__
-#define _IFXMIPS_H__
-
-#define ifxmips_r32(reg) __raw_readl(reg)
-#define ifxmips_w32(val, reg) __raw_writel(val, reg)
-#define ifxmips_w32_mask(clear, set, reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg)
-
-/*------------ GENERAL */
-
-#define BOARD_SYSTEM_TYPE "IFXMIPS"
-#define IFXMIPS_SYS_TYPE_LEN 0x100
-
-#define IOPORT_RESOURCE_START 0x10000000
-#define IOPORT_RESOURCE_END 0xffffffff
-#define IOMEM_RESOURCE_START 0x10000000
-#define IOMEM_RESOURCE_END 0xffffffff
-
-#define IFXMIPS_FLASH_START 0x10000000
-#define IFXMIPS_FLASH_MAX 0x02000000
-
-/*------------ ASC0/1 */
-
-#define IFXMIPS_ASC_BASE_ADDR (KSEG1 + 0x1E100400)
-#define IFXMIPS_ASC_BASE_DIFF (0x1E100C00 - 0x1E100400)
-
-#define IFXMIPS_ASC_FSTAT 0x0048
-#define IFXMIPS_ASC_TBUF 0x0020
-#define IFXMIPS_ASC_WHBSTATE 0x0018
-#define IFXMIPS_ASC_RBUF 0x0024
-#define IFXMIPS_ASC_STATE 0x0014
-#define IFXMIPS_ASC_IRNCR 0x00F8
-#define IFXMIPS_ASC_CLC 0x0000
-#define IFXMIPS_ASC_PISEL 0x0004
-#define IFXMIPS_ASC_TXFCON 0x0044
-#define IFXMIPS_ASC_RXFCON 0x0040
-#define IFXMIPS_ASC_CON 0x0010
-#define IFXMIPS_ASC_BG 0x0050
-#define IFXMIPS_ASC_IRNREN 0x00F4
-
-#define IFXMIPS_ASC_CLC_DISS 0x2
-#define ASC_IRNREN_RX_BUF 0x8
-#define ASC_IRNREN_TX_BUF 0x4
-#define ASC_IRNREN_ERR 0x2
-#define ASC_IRNREN_TX 0x1
-#define ASC_IRNCR_TIR 0x4
-#define ASC_IRNCR_RIR 0x2
-#define ASC_IRNCR_EIR 0x4
-#define ASCOPT_CSIZE 0x3
-#define ASCOPT_CS7 0x1
-#define ASCOPT_CS8 0x2
-#define ASCOPT_PARENB 0x4
-#define ASCOPT_STOPB 0x8
-#define ASCOPT_PARODD 0x0
-#define ASCOPT_CREAD 0x20
-#define TXFIFO_FL 1
-#define RXFIFO_FL 1
-#define TXFIFO_FULL 16
-#define ASCCLC_RMCMASK 0x0000FF00
-#define ASCCLC_RMCOFFSET 8
-#define ASCCON_M_8ASYNC 0x0
-#define ASCCON_M_7ASYNC 0x2
-#define ASCCON_ODD 0x00000020
-#define ASCCON_STP 0x00000080
-#define ASCCON_BRS 0x00000100
-#define ASCCON_FDE 0x00000200
-#define ASCCON_R 0x00008000
-#define ASCCON_FEN 0x00020000
-#define ASCCON_ROEN 0x00080000
-#define ASCCON_TOEN 0x00100000
-#define ASCSTATE_PE 0x00010000
-#define ASCSTATE_FE 0x00020000
-#define ASCSTATE_ROE 0x00080000
-#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
-#define ASCWHBSTATE_CLRREN 0x00000001
-#define ASCWHBSTATE_SETREN 0x00000002
-#define ASCWHBSTATE_CLRPE 0x00000004
-#define ASCWHBSTATE_CLRFE 0x00000008
-#define ASCWHBSTATE_CLRROE 0x00000020
-#define ASCTXFCON_TXFEN 0x0001
-#define ASCTXFCON_TXFFLU 0x0002
-#define ASCTXFCON_TXFITLMASK 0x3F00
-#define ASCTXFCON_TXFITLOFF 8
-#define ASCRXFCON_RXFEN 0x0001
-#define ASCRXFCON_RXFFLU 0x0002
-#define ASCRXFCON_RXFITLMASK 0x3F00
-#define ASCRXFCON_RXFITLOFF 8
-#define ASCFSTAT_RXFFLMASK 0x003F
-#define ASCFSTAT_TXFFLMASK 0x3F00
-#define ASCFSTAT_TXFFLOFF 8
-
-
-
-/*------------ RCU */
-#define IFXMIPS_RCU_BASE_ADDR 0xBF203000
-
-/* reset request */
-#define IFXMIPS_RCU_RST ((u32 *)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
-#define IFXMIPS_RCU_RST_CPU1 (1 << 3)
-#define IFXMIPS_RCU_RST_ALL 0x40000000
-
-#define IFXMIPS_RCU_RST_REQ_DFE (1 << 7)
-#define IFXMIPS_RCU_RST_REQ_AFE (1 << 11)
-#define IFXMIPS_RCU_RST_REQ_ARC_JTAG (1 << 20)
-
-
-/*------------ GPTU */
-
-#define IFXMIPS_GPTU_BASE_ADDR 0xB8000300
-
-/* clock control register */
-#define IFXMIPS_GPTU_GPT_CLC ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0000))
-
-/* captur reload register */
-#define IFXMIPS_GPTU_GPT_CAPREL ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0030))
-
-/* timer 6 control register */
-#define IFXMIPS_GPTU_GPT_T6CON ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0020))
-
-
-/*------------ EBU */
-
-#define IFXMIPS_EBU_BASE_ADDR 0xBE105300
-
-/* bus configuration register */
-#define IFXMIPS_EBU_BUSCON0 ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0060))
-#define IFXMIPS_EBU_PCC_CON ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0090))
-#define IFXMIPS_EBU_PCC_IEN ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x00A4))
-#define IFXMIPS_EBU_PCC_ISTAT ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x00A0))
-#define IFXMIPS_EBU_BUSCON1 ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0064))
-#define IFXMIPS_EBU_ADDRSEL1 ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0024))
-
-/*------------ CGU */
-#define IFXMIPS_CGU_BASE_ADDR (KSEG1 + 0x1F103000)
-#define IFXMIPS_CGU_PLL0_CFG ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0004))
-#define IFXMIPS_CGU_PLL1_CFG ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0008))
-#define IFXMIPS_CGU_PLL2_CFG ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x000C))
-#define IFXMIPS_CGU_SYS ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
-#define IFXMIPS_CGU_UPDATE ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0014))
-#define IFXMIPS_CGU_IF_CLK ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
-#define IFXMIPS_CGU_OSC_CON ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x001C))
-#define IFXMIPS_CGU_SMD ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0020))
-#define IFXMIPS_CGU_CT1SR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0028))
-#define IFXMIPS_CGU_CT2SR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x002C))
-#define IFXMIPS_CGU_PCMCR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0030))
-#define IFXMIPS_CGU_PCI_CR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
-#define IFXMIPS_CGU_PD_PC ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0038))
-#define IFXMIPS_CGU_FMR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x003C))
-
-/* clock mux */
-#define IFXMIPS_CGU_SYS ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
-#define IFXMIPS_CGU_IFCCR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
-#define IFXMIPS_CGU_PCICR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
-
-#define CLOCK_60M 60000000
-#define CLOCK_83M 83333333
-#define CLOCK_111M 111111111
-#define CLOCK_133M 133333333
-#define CLOCK_167M 166666667
-#define CLOCK_333M 333333333
-
-
-/*------------ CGU */
-
-#define IFXMIPS_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
-
-#define IFXMIPS_PMU_PWDCR ((u32 *)(IFXMIPS_PMU_BASE_ADDR + 0x001C))
-#define IFXMIPS_PMU_PWDSR ((u32 *)(IFXMIPS_PMU_BASE_ADDR + 0x0020))
-
-
-/*------------ ICU */
-
-#define IFXMIPS_ICU_BASE_ADDR 0xBF880200
-
-
-#define IFXMIPS_ICU_IM0_ISR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0000))
-#define IFXMIPS_ICU_IM0_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0008))
-#define IFXMIPS_ICU_IM0_IOSR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0010))
-#define IFXMIPS_ICU_IM0_IRSR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0018))
-#define IFXMIPS_ICU_IM0_IMR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0020))
-
-#define IFXMIPS_ICU_IM1_ISR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0028))
-#define IFXMIPS_ICU_IM2_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0058))
-#define IFXMIPS_ICU_IM3_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0080))
-#define IFXMIPS_ICU_IM4_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x00A8))
-#define IFXMIPS_ICU_IM5_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x00D0))
-
-#define IFXMIPS_ICU_OFFSET (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR)
-
-
-/*------------ ETOP */
-
-#define IFXMIPS_PPE32_BASE_ADDR 0xBE180000
-#define IFXMIPS_PPE32_SIZE 0x40000
-
-#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600
-
-#define IFXMIPS_PPE32_MEM_MAP ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x10000))
-#define IFXMIPS_PPE32_SRST ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x10080))
-
-#define MII_MODE 1
-#define REV_MII_MODE 2
-
-/* mdio access */
-#define IFXMIPS_PPE32_MDIO_CFG ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x11800))
-#define IFXMIPS_PPE32_MDIO_ACC ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x11804))
-
-#define MDIO_ACC_REQUEST 0x80000000
-#define MDIO_ACC_READ 0x40000000
-#define MDIO_ACC_ADDR_MASK 0x1f
-#define MDIO_ACC_ADDR_OFFSET 0x15
-#define MDIO_ACC_REG_MASK 0x1f
-#define MDIO_ACC_REG_OFFSET 0x10
-#define MDIO_ACC_VAL_MASK 0xffff
-
-/* configuration */
-#define IFXMIPS_PPE32_CFG ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1808))
-
-#define PPE32_MII_MASK 0xfffffffc
-#define PPE32_MII_NORMAL 0x8
-#define PPE32_MII_REVERSE 0xe
-
-/* packet length */
-#define IFXMIPS_PPE32_IG_PLEN_CTRL ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1820))
-
-#define PPE32_PLEN_OVER 0x5ee
-#define PPE32_PLEN_UNDER 0x400000
-
-/* enet */
-#define IFXMIPS_PPE32_ENET_MAC_CFG ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1840))
-
-#define PPE32_CGEN 0x800
-
-
-/*------------ DMA */
-#define IFXMIPS_DMA_BASE_ADDR 0xBE104100
-
-#define IFXMIPS_DMA_CS ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x18))
-#define IFXMIPS_DMA_CIE ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x2C))
-#define IFXMIPS_DMA_IRNEN ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0xf4))
-#define IFXMIPS_DMA_CCTRL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x1C))
-#define IFXMIPS_DMA_CIS ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x28))
-#define IFXMIPS_DMA_CDLEN ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x24))
-#define IFXMIPS_DMA_PS ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x40))
-#define IFXMIPS_DMA_PCTRL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x44))
-#define IFXMIPS_DMA_CTRL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x10))
-#define IFXMIPS_DMA_CPOLL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x14))
-#define IFXMIPS_DMA_CDBA ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x20))
-
-
-/*------------ PCI */
-#define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400)
-
-#define PCI_CR_FCI_ADDR_MAP0 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C0))
-#define PCI_CR_FCI_ADDR_MAP1 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C4))
-#define PCI_CR_FCI_ADDR_MAP2 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C8))
-#define PCI_CR_FCI_ADDR_MAP3 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00CC))
-#define PCI_CR_FCI_ADDR_MAP4 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D0))
-#define PCI_CR_FCI_ADDR_MAP5 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D4))
-#define PCI_CR_FCI_ADDR_MAP6 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D8))
-#define PCI_CR_FCI_ADDR_MAP7 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00DC))
-#define PCI_CR_CLK_CTRL ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0000))
-#define PCI_CR_PCI_MOD ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0030))
-#define PCI_CR_PC_ARB ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0080))
-#define PCI_CR_FCI_ADDR_MAP11hg ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E4))
-#define PCI_CR_BAR11MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0044))
-#define PCI_CR_BAR12MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0048))
-#define PCI_CR_BAR13MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x004C))
-#define PCI_CS_BASE_ADDR1 ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0010))
-#define PCI_CR_PCI_ADDR_MAP11 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0064))
-#define PCI_CR_FCI_BURST_LENGTH ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E8))
-#define PCI_CR_PCI_EOI ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x002C))
-
-#define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000)
-
-#define PCI_CS_STS_CMD ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0004))
-
-#define PCI_MASTER0_REQ_MASK_2BITS 8
-#define PCI_MASTER1_REQ_MASK_2BITS 10
-#define PCI_MASTER2_REQ_MASK_2BITS 12
-#define INTERNAL_ARB_ENABLE_BIT 0
-
-
-/*------------ WDT */
-
-#define IFXMIPS_WDT_BASE_ADDR (KSEG1 + 0x1F880000)
-#define IFXMIPS_WDT_SIZE 0x400
-
-#define IFXMIPS_BIU_WDT_CR ((u32 *)(IFXMIPS_WDT_BASE_ADDR + 0x03F0))
-#define IFXMIPS_BIU_WDT_SR ((u32 *)(IFXMIPS_WDT_BASE_ADDR + 0x03F8))
-
-
-/*------------ LED */
-
-#define IFXMIPS_LED_BASE_ADDR (KSEG1 + 0x1E100BB0)
-#define IFXMIPS_LED_CON0 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0000))
-#define IFXMIPS_LED_CON1 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0004))
-#define IFXMIPS_LED_CPU0 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0008))
-#define IFXMIPS_LED_CPU1 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x000C))
-#define IFXMIPS_LED_AR ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0010))
-
-#define LED_CON0_SWU (1 << 31)
-#define LED_CON0_AD1 (1 << 25)
-#define LED_CON0_AD0 (1 << 24)
-
-#define IFXMIPS_LED_2HZ (0)
-#define IFXMIPS_LED_4HZ (1 << 23)
-#define IFXMIPS_LED_8HZ (2 << 23)
-#define IFXMIPS_LED_10HZ (3 << 23)
-#define IFXMIPS_LED_MASK (0xf << 23)
-
-#define IFXMIPS_LED_UPD_SRC_FPI (1 << 31)
-#define IFXMIPS_LED_UPD_MASK (3 << 30)
-#define IFXMIPS_LED_ADSL_SRC (3 << 24)
-
-#define IFXMIPS_LED_GROUP0 (1 << 0)
-#define IFXMIPS_LED_GROUP1 (1 << 1)
-#define IFXMIPS_LED_GROUP2 (1 << 2)
-
-#define IFXMIPS_LED_RISING 0
-#define IFXMIPS_LED_FALLING (1 << 26)
-#define IFXMIPS_LED_EDGE_MASK (1 << 26)
-
-
-/*------------ GPIO */
-
-#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00)
-
-#define IFXMIPS_GPIO_P0_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0010))
-#define IFXMIPS_GPIO_P1_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0040))
-#define IFXMIPS_GPIO_P0_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0014))
-#define IFXMIPS_GPIO_P1_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))
-#define IFXMIPS_GPIO_P0_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))
-#define IFXMIPS_GPIO_P1_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))
-#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
-#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
-#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
-#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
-#define IFXMIPS_GPIO_P0_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))
-#define IFXMIPS_GPIO_P1_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))
-#define IFXMIPS_GPIO_P0_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
-#define IFXMIPS_GPIO_P1_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
-#define IFXMIPS_GPIO_P0_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
-#define IFXMIPS_GPIO_P1_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
-#define IFXMIPS_GPIO_P0_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
-#define IFXMIPS_GPIO_P1_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
-
-
-/*------------ SSC */
-
-#define IFXMIPS_SSC_BASE_ADDR (KSEG1 + 0x1e100800)
-
-
-#define IFXMIPS_SSC_CLC ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0000))
-#define IFXMIPS_SSC_IRN ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))
-#define IFXMIPS_SSC_SFCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0060))
-#define IFXMIPS_SSC_WHBGPOSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
-#define IFXMIPS_SSC_STATE ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
-#define IFXMIPS_SSC_WHBSTATE ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
-#define IFXMIPS_SSC_FSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0038))
-#define IFXMIPS_SSC_ID ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0008))
-#define IFXMIPS_SSC_TB ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0020))
-#define IFXMIPS_SSC_RXFCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0030))
-#define IFXMIPS_SSC_TXFCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0034))
-#define IFXMIPS_SSC_CON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0010))
-#define IFXMIPS_SSC_GPOSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0074))
-#define IFXMIPS_SSC_RB ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0024))
-#define IFXMIPS_SSC_RXCNT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0084))
-#define IFXMIPS_SSC_GPOCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0070))
-#define IFXMIPS_SSC_BR ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0040))
-#define IFXMIPS_SSC_RXREQ ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0080))
-#define IFXMIPS_SSC_SFSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0064))
-#define IFXMIPS_SSC_RXCNT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0084))
-
-
-/*------------ MEI */
-
-#define IFXMIPS_MEI_BASE_ADDR (KSEG1 + 0x1E116000)
-
-#define MEI_DATA_XFR ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0000))
-#define MEI_VERSION ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0004))
-#define MEI_ARC_GP_STAT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0008))
-#define MEI_DATA_XFR_STAT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x000C))
-#define MEI_XFR_ADDR ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0010))
-#define MEI_MAX_WAIT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0014))
-#define MEI_TO_ARC_INT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0018))
-#define ARC_TO_MEI_INT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x001C))
-#define ARC_TO_MEI_INT_MASK ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0020))
-#define MEI_DEBUG_WAD ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0024))
-#define MEI_DEBUG_RAD ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0028))
-#define MEI_DEBUG_DATA ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x002C))
-#define MEI_DEBUG_DEC ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0030))
-#define MEI_CONFIG ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0034))
-#define MEI_RST_CONTROL ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0038))
-#define MEI_DBG_MASTER ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x003C))
-#define MEI_CLK_CONTROL ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0040))
-#define MEI_BIST_CONTROL ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0044))
-#define MEI_BIST_STAT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0048))
-#define MEI_XDATA_BASE_SH ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x004c))
-#define MEI_XDATA_BASE ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0050))
-#define MEI_XMEM_BAR_BASE ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0054))
-#define MEI_XMEM_BAR0 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0054))
-#define MEI_XMEM_BAR1 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0058))
-#define MEI_XMEM_BAR2 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x005C))
-#define MEI_XMEM_BAR3 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0060))
-#define MEI_XMEM_BAR4 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0064))
-#define MEI_XMEM_BAR5 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0068))
-#define MEI_XMEM_BAR6 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x006C))
-#define MEI_XMEM_BAR7 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0070))
-#define MEI_XMEM_BAR8 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0074))
-#define MEI_XMEM_BAR9 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0078))
-#define MEI_XMEM_BAR10 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x007C))
-#define MEI_XMEM_BAR11 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0080))
-#define MEI_XMEM_BAR12 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0084))
-#define MEI_XMEM_BAR13 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0088))
-#define MEI_XMEM_BAR14 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x008C))
-#define MEI_XMEM_BAR15 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0090))
-#define MEI_XMEM_BAR16 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0094))
-
-
-/*------------ DEU */
-
-#define IFXMIPS_DEU_BASE (KSEG1 + 0x1E103100)
-#define IFXMIPS_DEU_CLK ((u32 *)(IFXMIPS_DEU_BASE + 0x0000))
-#define IFXMIPS_DEU_ID ((u32 *)(IFXMIPS_DEU_BASE + 0x0008))
-
-#define IFXMIPS_DES_CON ((u32 *)(IFXMIPS_DEU_BASE + 0x0010))
-#define IFXMIPS_DES_IHR ((u32 *)(IFXMIPS_DEU_BASE + 0x0014))
-#define IFXMIPS_DES_ILR ((u32 *)(IFXMIPS_DEU_BASE + 0x0018))
-#define IFXMIPS_DES_K1HR ((u32 *)(IFXMIPS_DEU_BASE + 0x001C))
-#define IFXMIPS_DES_K1LR ((u32 *)(IFXMIPS_DEU_BASE + 0x0020))
-#define IFXMIPS_DES_K3HR ((u32 *)(IFXMIPS_DEU_BASE + 0x0024))
-#define IFXMIPS_DES_K3LR ((u32 *)(IFXMIPS_DEU_BASE + 0x0028))
-#define IFXMIPS_DES_IVHR ((u32 *)(IFXMIPS_DEU_BASE + 0x002C))
-#define IFXMIPS_DES_IVLR ((u32 *)(IFXMIPS_DEU_BASE + 0x0030))
-#define IFXMIPS_DES_OHR ((u32 *)(IFXMIPS_DEU_BASE + 0x0040))
-#define IFXMIPS_DES_OLR ((u32 *)(IFXMIPS_DEU_BASE + 0x0050))
-#define IFXMIPS_AES_CON ((u32 *)(IFXMIPS_DEU_BASE + 0x0050))
-#define IFXMIPS_AES_ID3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0054))
-#define IFXMIPS_AES_ID2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0058))
-#define IFXMIPS_AES_ID1R ((u32 *)(IFXMIPS_DEU_BASE + 0x005C))
-#define IFXMIPS_AES_ID0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0060))
-#define IFXMIPS_AES_K7R ((u32 *)(IFXMIPS_DEU_BASE + 0x0064))
-#define IFXMIPS_AES_K6R ((u32 *)(IFXMIPS_DEU_BASE + 0x0068))
-#define IFXMIPS_AES_K5R ((u32 *)(IFXMIPS_DEU_BASE + 0x006C))
-#define IFXMIPS_AES_K4R ((u32 *)(IFXMIPS_DEU_BASE + 0x0070))
-#define IFXMIPS_AES_K3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0074))
-#define IFXMIPS_AES_K2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0078))
-#define IFXMIPS_AES_K1R ((u32 *)(IFXMIPS_DEU_BASE + 0x007C))
-#define IFXMIPS_AES_K0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0080))
-#define IFXMIPS_AES_IV3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0084))
-#define IFXMIPS_AES_IV2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0088))
-#define IFXMIPS_AES_IV1R ((u32 *)(IFXMIPS_DEU_BASE + 0x008C))
-#define IFXMIPS_AES_IV0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0090))
-#define IFXMIPS_AES_0D3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0094))
-#define IFXMIPS_AES_0D2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0098))
-#define IFXMIPS_AES_OD1R ((u32 *)(IFXMIPS_DEU_BASE + 0x009C))
-#define IFXMIPS_AES_OD0R ((u32 *)(IFXMIPS_DEU_BASE + 0x00A0))
-
-/*------------ FUSE */
-
-#define IFXMIPS_FUSE_BASE_ADDR (KSEG1 + 0x1F107354)
-
-
-/*------------ MPS */
-
-#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
-#define IFXMIPS_MPS_SRAM ((u32 *)(KSEG1 + 0x1F200000))
-
-#define IFXMIPS_MPS_CHIPID ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
-#define IFXMIPS_MPS_VC0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
-#define IFXMIPS_MPS_VC1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0004))
-#define IFXMIPS_MPS_VC2ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0008))
-#define IFXMIPS_MPS_VC3ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x000C))
-#define IFXMIPS_MPS_RVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
-#define IFXMIPS_MPS_RVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0014))
-#define IFXMIPS_MPS_RVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0018))
-#define IFXMIPS_MPS_RVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x001C))
-#define IFXMIPS_MPS_SVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0020))
-#define IFXMIPS_MPS_SVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0024))
-#define IFXMIPS_MPS_SVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0028))
-#define IFXMIPS_MPS_SVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x002C))
-#define IFXMIPS_MPS_CVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0030))
-#define IFXMIPS_MPS_CVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0034))
-#define IFXMIPS_MPS_CVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0038))
-#define IFXMIPS_MPS_CVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x003C))
-#define IFXMIPS_MPS_RAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0040))
-#define IFXMIPS_MPS_RAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0044))
-#define IFXMIPS_MPS_SAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0048))
-#define IFXMIPS_MPS_SAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x004C))
-#define IFXMIPS_MPS_CAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0050))
-#define IFXMIPS_MPS_CAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0054))
-#define IFXMIPS_MPS_AD0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
-#define IFXMIPS_MPS_AD1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
-
-#define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
-#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) ((((1 << 4) - 1) & (value)) << 28)
-#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
-#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) ((((1 << 16) - 1) & (value)) << 12)
-#define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
-#define IFXMIPS_MPS_CHIPID_MANID_SET(value) ((((1 << 10) - 1) & (value)) << 1)
-
-#endif
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-
-#ifndef _IFXMIPS_CGU_H__
-#define _IFXMIPS_CGU_H__
-
-#define BASIC_INPUT_CLOCK_FREQUENCY_1 35328000
-#define BASIC_INPUT_CLOCK_FREQUENCY_2 36000000
-
-#define BASIS_INPUT_CRYSTAL_USB 12000000
-
-#define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
-
-#define CGU_PLL0_PHASE_DIVIDER_ENABLE (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 31))
-#define CGU_PLL0_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 30))
-#define CGU_PLL0_CFG_DSMSEL (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 28))
-#define CGU_PLL0_CFG_FRAC_EN (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 27))
-#define CGU_PLL1_SRC (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 31))
-#define CGU_PLL1_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 30))
-#define CGU_PLL1_CFG_DSMSEL (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 28))
-#define CGU_PLL1_CFG_FRAC_EN (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 27))
-#define CGU_PLL2_PHASE_DIVIDER_ENABLE (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 20))
-#define CGU_PLL2_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 19))
-#define CGU_SYS_FPI_SEL (1 << 6)
-#define CGU_SYS_DDR_SEL 0x3
-#define CGU_PLL0_SRC (1 << 29)
-
-#define CGU_PLL0_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17)
-#define CGU_PLL0_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6)
-#define CGU_PLL0_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2)
-#define CGU_PLL1_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17)
-#define CGU_PLL1_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6)
-#define CGU_PLL1_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2)
-#define CGU_PLL2_SRC GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17)
-#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13)
-#define CGU_PLL2_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6)
-#define CGU_PLL2_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2)
-#define CGU_IF_CLK_PCI_CLK GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20)
-
-
-unsigned int cgu_get_mips_clock(int cpu);
-unsigned int cgu_get_io_region_clock(void);
-unsigned int cgu_get_fpi_bus_clock(int fpi);
-void cgu_setup_pci_clk(int internal_clock);
-unsigned int ifxmips_get_ddr_hz(void);
-unsigned int ifxmips_get_fpi_hz(void);
-unsigned int ifxmips_get_cpu_hz(void);
-
-#endif
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2005 infineon
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- *
- */
-#ifndef _IFXMIPS_DMA_H__
-#define _IFXMIPS_DMA_H__
-
-#define RCV_INT 1
-#define TX_BUF_FULL_INT 2
-#define TRANSMIT_CPT_INT 4
-#define IFXMIPS_DMA_CH_ON 1
-#define IFXMIPS_DMA_CH_OFF 0
-#define IFXMIPS_DMA_CH_DEFAULT_WEIGHT 100
-
-enum attr_t{
- TX = 0,
- RX = 1,
- RESERVED = 2,
- DEFAULT = 3,
-};
-
-#define DMA_OWN 1
-#define CPU_OWN 0
-#define DMA_MAJOR 250
-
-#define DMA_DESC_OWN_CPU 0x0
-#define DMA_DESC_OWN_DMA 0x80000000
-#define DMA_DESC_CPT_SET 0x40000000
-#define DMA_DESC_SOP_SET 0x20000000
-#define DMA_DESC_EOP_SET 0x10000000
-
-#define MISCFG_MASK 0x40
-#define RDERR_MASK 0x20
-#define CHOFF_MASK 0x10
-#define DESCPT_MASK 0x8
-#define DUR_MASK 0x4
-#define EOP_MASK 0x2
-
-#define DMA_DROP_MASK (1<<31)
-
-#define IFXMIPS_DMA_RX -1
-#define IFXMIPS_DMA_TX 1
-
-struct dma_chan_map {
- const char *dev_name;
- enum attr_t dir;
- int pri;
- int irq;
- int rel_chan_no;
-};
-
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-struct rx_desc {
- u32 data_length:16;
- volatile u32 reserved:7;
- volatile u32 byte_offset:2;
- volatile u32 Burst_length_offset:3;
- volatile u32 EoP:1;
- volatile u32 Res:1;
- volatile u32 C:1;
- volatile u32 OWN:1;
- volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
-};
-
-struct tx_desc {
- volatile u32 data_length:16;
- volatile u32 reserved1:7;
- volatile u32 byte_offset:5;
- volatile u32 EoP:1;
- volatile u32 SoP:1;
- volatile u32 C:1;
- volatile u32 OWN:1;
- volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
-};
-#else /* BIG */
-struct rx_desc {
- union {
- struct {
- volatile u32 OWN:1;
- volatile u32 C:1;
- volatile u32 SoP:1;
- volatile u32 EoP:1;
- volatile u32 Burst_length_offset:3;
- volatile u32 byte_offset:2;
- volatile u32 reserve:7;
- volatile u32 data_length:16;
- } field;
- volatile u32 word;
- } status;
- volatile u32 Data_Pointer;
-};
-
-struct tx_desc {
- union {
- struct {
- volatile u32 OWN:1;
- volatile u32 C:1;
- volatile u32 SoP:1;
- volatile u32 EoP:1;
- volatile u32 byte_offset:5;
- volatile u32 reserved:7;
- volatile u32 data_length:16;
- } field;
- volatile u32 word;
- } status;
- volatile u32 Data_Pointer;
-};
-#endif /* ENDIAN */
-
-struct dma_channel_info {
- /* relative channel number */
- int rel_chan_no;
- /* class for this channel for QoS */
- int pri;
- /* specify byte_offset */
- int byte_offset;
- /* direction */
- int dir;
- /* irq number */
- int irq;
- /* descriptor parameter */
- int desc_base;
- int desc_len;
- int curr_desc;
- int prev_desc; /* only used if it is a tx channel*/
- /* weight setting for WFQ algorithm*/
- int weight;
- int default_weight;
- int packet_size;
- int burst_len;
- /* on or off of this channel */
- int control;
- /* optional information for the upper layer devices */
-#if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA)
- void *opt[64];
-#else
- void *opt[25];
-#endif
- /* Pointer to the peripheral device who is using this channel */
- void *dma_dev;
- /* channel operations */
- void (*open)(struct dma_channel_info *pCh);
- void (*close)(struct dma_channel_info *pCh);
- void (*reset)(struct dma_channel_info *pCh);
- void (*enable_irq)(struct dma_channel_info *pCh);
- void (*disable_irq)(struct dma_channel_info *pCh);
-};
-
-struct dma_device_info {
- /* device name of this peripheral */
- char device_name[15];
- int reserved;
- int tx_burst_len;
- int rx_burst_len;
- int default_weight;
- int current_tx_chan;
- int current_rx_chan;
- int num_tx_chan;
- int num_rx_chan;
- int max_rx_chan_num;
- int max_tx_chan_num;
- struct dma_channel_info *tx_chan[20];
- struct dma_channel_info *rx_chan[20];
- /*functions, optional*/
- u8 *(*buffer_alloc)(int len, int *offset, void **opt);
- void (*buffer_free)(u8 *dataptr, void *opt);
- int (*intr_handler)(struct dma_device_info *info, int status);
- void *priv; /* used by peripheral driver only */
-};
-
-struct dma_device_info *dma_device_reserve(char *dev_name);
-void dma_device_release(struct dma_device_info *dev);
-void dma_device_register(struct dma_device_info *info);
-void dma_device_unregister(struct dma_device_info *info);
-int dma_device_read(struct dma_device_info *info, u8 **dataptr, void **opt);
-int dma_device_write(struct dma_device_info *info, u8 *dataptr, int len,
- void *opt);
-
-#endif
-
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-#ifndef _IFXMIPS_EBU_H__
-#define _IFXMIPS_EBU_H__
-
-extern spinlock_t ebu_lock;
-
-#endif
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-#ifndef _IFXMIPS_GPIO_H__
-#define _IFXMIPS_GPIO_H__
-
-extern int ifxmips_port_reserve_pin(unsigned int port, unsigned int pin);
-extern int ifxmips_port_free_pin(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_open_drain(unsigned int port, unsigned int pin);
-extern int ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_pudsel(unsigned int port, unsigned int pin);
-extern int ifxmips_port_clear_pudsel(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_puden(unsigned int port, unsigned int pin);
-extern int ifxmips_port_clear_puden(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_stoff(unsigned int port, unsigned int pin);
-extern int ifxmips_port_clear_stoff(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_dir_out(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_dir_in(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_output(unsigned int port, unsigned int pin);
-extern int ifxmips_port_clear_output(unsigned int port, unsigned int pin);
-extern int ifxmips_port_get_input(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_altsel0(unsigned int port, unsigned int pin);
-extern int ifxmips_port_clear_altsel0(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_altsel1(unsigned int port, unsigned int pin);
-extern int ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin);
-
-#endif
+++ /dev/null
-#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
-#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
-
-
-/******************************************************************************
- Copyright (c) 2002, Infineon Technologies. All rights reserved.
-
- No Warranty
- Because the program is licensed free of charge, there is no warranty for
- the program, to the extent permitted by applicable law. Except when
- otherwise stated in writing the copyright holders and/or other parties
- provide the program "as is" without warranty of any kind, either
- expressed or implied, including, but not limited to, the implied
- warranties of merchantability and fitness for a particular purpose. The
- entire risk as to the quality and performance of the program is with
- you. should the program prove defective, you assume the cost of all
- necessary servicing, repair or correction.
-
- In no event unless required by applicable law or agreed to in writing
- will any copyright holder, or any other party who may modify and/or
- redistribute the program as permitted above, be liable to you for
- damages, including any general, special, incidental or consequential
- damages arising out of the use or inability to use the program
- (including but not limited to loss of data or data being rendered
- inaccurate or losses sustained by you or third parties or a failure of
- the program to operate with any other programs), even if such holder or
- other party has been advised of the possibility of such damages.
-******************************************************************************/
-
-
-/*
- * ####################################
- * Definition
- * ####################################
- */
-
-/*
- * Available Timer/Counter Index
- */
-#define TIMER(n, X) (n * 2 + (X ? 1 : 0))
-#define TIMER_ANY 0x00
-#define TIMER1A TIMER(1, 0)
-#define TIMER1B TIMER(1, 1)
-#define TIMER2A TIMER(2, 0)
-#define TIMER2B TIMER(2, 1)
-#define TIMER3A TIMER(3, 0)
-#define TIMER3B TIMER(3, 1)
-
-/*
- * Flag of Timer/Counter
- * These flags specify the way in which timer is configured.
- */
-/* Bit size of timer/counter. */
-#define TIMER_FLAG_16BIT 0x0000
-#define TIMER_FLAG_32BIT 0x0001
-/* Switch between timer and counter. */
-#define TIMER_FLAG_TIMER 0x0000
-#define TIMER_FLAG_COUNTER 0x0002
-/* Stop or continue when overflowing/underflowing. */
-#define TIMER_FLAG_ONCE 0x0000
-#define TIMER_FLAG_CYCLIC 0x0004
-/* Count up or counter down. */
-#define TIMER_FLAG_UP 0x0000
-#define TIMER_FLAG_DOWN 0x0008
-/* Count on specific level or edge. */
-#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
-#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040
-#define TIMER_FLAG_RISE_EDGE 0x0010
-#define TIMER_FLAG_FALL_EDGE 0x0020
-#define TIMER_FLAG_ANY_EDGE 0x0030
-/* Signal is syncronous to module clock or not. */
-#define TIMER_FLAG_UNSYNC 0x0000
-#define TIMER_FLAG_SYNC 0x0080
-/* Different interrupt handle type. */
-#define TIMER_FLAG_NO_HANDLE 0x0000
-#if defined(__KERNEL__)
- #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100
-#endif // defined(__KERNEL__)
-#define TIMER_FLAG_SIGNAL 0x0300
-/* Internal clock source or external clock source */
-#define TIMER_FLAG_INT_SRC 0x0000
-#define TIMER_FLAG_EXT_SRC 0x1000
-
-
-/*
- * ioctl Command
- */
-#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */
-#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */
-#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */
-#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */
-#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */
-#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/
-#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */
-#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */
-
-/*
- * Data Type Used to Call ioctl
- */
-struct gptu_ioctl_param {
- unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
- * GPTU_SET_COUNTER, this field is ID of expected *
- * timer/counter. If it's zero, a timer/counter would *
- * be dynamically allocated and ID would be stored in *
- * this field. *
- * In command GPTU_GET_COUNT_VALUE, this field is *
- * ignored. *
- * In other command, this field is ID of timer/counter *
- * allocated. */
- unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
- * GPTU_SET_COUNTER, this field contains flags to *
- * specify how to configure timer/counter. *
- * In command GPTU_START_TIMER, zero indicate start *
- * and non-zero indicate resume timer/counter. *
- * In other command, this field is ignored. */
- unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains *
- * init/reload value. *
- * In command GPTU_SET_TIMER, this field contains *
- * frequency (0.001Hz) of timer. *
- * In command GPTU_GET_COUNT_VALUE, current count *
- * value would be stored in this field. *
- * In command GPTU_CALCULATE_DIVIDER, this field *
- * contains frequency wanted, and after calculation, *
- * divider would be stored in this field to overwrite *
- * the frequency. *
- * In other command, this field is ignored. */
- int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
- * if signal is required, this field contains process *
- * ID to which signal would be sent. *
- * In other command, this field is ignored. */
- int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
- * if signal is required, this field contains signal *
- * number which would be sent. *
- * In other command, this field is ignored. */
-};
-
-/*
- * ####################################
- * Data Type
- * ####################################
- */
-typedef void (*timer_callback)(unsigned long arg);
-
-extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
-extern int ifxmips_free_timer(unsigned int);
-extern int ifxmips_start_timer(unsigned int, int);
-extern int ifxmips_stop_timer(unsigned int);
-extern int ifxmips_reset_counter_flags(u32 timer, u32 flags);
-extern int ifxmips_get_count_value(unsigned int, unsigned long *);
-extern u32 ifxmips_cal_divider(unsigned long);
-extern int ifxmips_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
-extern int ifxmips_set_counter(unsigned int timer, unsigned int flag,
- u32 reload, unsigned long arg1, unsigned long arg2);
-
-#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2005 infineon
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-#ifndef _IFXMIPS_IRQ__
-#define _IFXMIPS_IRQ__
-
-#define INT_NUM_IRQ0 8
-#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
-#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
-#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
-#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
-#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
-#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
-
-#define IFXMIPSASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 7))
-#define IFXMIPSASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 7) + 2)
-#define IFXMIPSASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 7) + 3)
-
-#define IFXMIPS_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
-#define IFXMIPS_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
-#define IFXMIPS_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
-
-#define IFXMIPS_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
-#define IFXMIPS_MEI_INT (INT_NUM_IM1_IRL0 + 23)
-
-#define IFXMIPS_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
-#define IFXMIPS_USB_INT (INT_NUM_IM1_IRL0 + 22)
-#define IFXMIPS_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
-
-#define MIPS_CPU_TIMER_IRQ 7
-
-#define IFXMIPS_DMA_CH0_INT (INT_NUM_IM2_IRL0)
-#define IFXMIPS_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
-#define IFXMIPS_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
-#define IFXMIPS_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
-#define IFXMIPS_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
-#define IFXMIPS_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
-#define IFXMIPS_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
-#define IFXMIPS_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
-#define IFXMIPS_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
-#define IFXMIPS_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
-#define IFXMIPS_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
-#define IFXMIPS_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
-#define IFXMIPS_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
-#define IFXMIPS_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
-#define IFXMIPS_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
-#define IFXMIPS_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
-#define IFXMIPS_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
-#define IFXMIPS_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
-#define IFXMIPS_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
-#define IFXMIPS_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
-
-#define IFXMIPS_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
-
-#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
-#define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18)
-#define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19)
-#define IFXMIPS_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
-
-
-extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);
-
-#endif
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-#ifndef _IFXMIPS_LED_H__
-#define _IFXMIPS_LED_H__
-
-extern void ifxmips_led_set(unsigned int led);
-extern void ifxmips_led_clear(unsigned int led);
-extern void ifxmips_led_blink_set(unsigned int led);
-extern void ifxmips_led_blink_clear(unsigned int led);
-
-#endif
+++ /dev/null
-#ifndef _IFXMIPS_PLATFORM_H__
-#define _IFXMIPS_PLATFORM_H__
-
-struct ifxmips_eth_data {
- const char *mac;
- int mii_mode;
-};
-
-#endif
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-#ifndef _IFXMIPS_PMU_H__
-#define _IFXMIPS_PMU_H__
-
-
-#define IFXMIPS_PMU_PWDCR_DMA 0x0020
-#define IFXMIPS_PMU_PWDCR_USB 0x8041
-#define IFXMIPS_PMU_PWDCR_LED 0x0800
-#define IFXMIPS_PMU_PWDCR_GPT 0x1000
-#define IFXMIPS_PMU_PWDCR_PPE 0x2000
-#define IFXMIPS_PMU_PWDCR_FPI 0x4000
-
-void ifxmips_pmu_enable(unsigned int module);
-void ifxmips_pmu_disable(unsigned int module);
-
-#endif
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2008 John Crispin <blogic@openwrt.org>
- */
-#ifndef _IFXPROM_H__
-#define _IFXPROM_H__
-
-extern void early_printf(const char *fmt, ...);
-extern int ifxmips_has_brn_block(void);
-
-#endif
+++ /dev/null
-/*
- * include/asm-mips/mach-ifxmips/irq.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- *
- */
-
-#ifndef __IFXMIPS_IRQ_H
-#define __IFXMIPS_IRQ_H
-
-#define NR_IRQS 256
-#include_next <irq.h>
-
-#endif
+++ /dev/null
-#include <asm/mips_machine.h>
-
-enum ifxmips_mach_type {
- IFXMIPS_MACH_GENERIC,
-
- /* Danube/Twinpass based machines */
- IFXMIPS_MACH_EASY50712, /* Danube evalkit */
- IFXMIPS_MACH_EASY4010, /* Twinpass evalkit */
- IFXMIPS_MACH_ARV4518, /* Airties WAV-221 */
- IFXMIPS_MACH_ARV4520, /* Airties WAV-281, Arcor EasyboxA800 */
- IFXMIPS_MACH_ARV4525, /* Speedport W502V */
-
- /* ASE based machines */
- IFXMIPS_MACH_EASY50601, /* ASE wave board */
-
- /* AR9 based machines */
- IFXMIPS_MACH_EASY50822, /* AR9 eval board */
-
- /* VR9 based machines */
- IFXMIPS_MACH_EASY80920, /* VRX200 eval board */
-};
-
+++ /dev/null
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- */
-#ifndef __ASM_MIPS_MACH_IFXMIPS_WAR_H
-#define __ASM_MIPS_MACH_IFXMIPS_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
-#define R4600_V1_HIT_CACHEOP_WAR 0
-#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
-#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
-#define RM9000_CDEX_SMP_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
-#define R10000_LLSC_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
-
-#endif
+++ /dev/null
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/mm.h>
-#include <asm/addrspace.h>
-#include <linux/vmalloc.h>
-#include <ifxmips.h>
-#include <ifxmips_irq.h>
-#include <ifxmips_ebu.h>
-
-#define IFXMIPS_PCI_CFG_BUSNUM_SHF 16
-#define IFXMIPS_PCI_CFG_DEVNUM_SHF 11
-#define IFXMIPS_PCI_CFG_FUNNUM_SHF 8
-
-#define PCI_ACCESS_READ 0
-#define PCI_ACCESS_WRITE 1
-
-extern u32 ifxmips_pci_mapped_cfg;
-
-static int
-ifxmips_pci_config_access(unsigned char access_type,
- struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
-{
- unsigned long cfg_base;
- unsigned long flags;
-
- u32 temp;
-
- /* IFXMips support slot from 0 to 15 */
- /* dev_fn 0&0x68 (AD29) is ifxmips itself */
- if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
- || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
- return 1;
-
- spin_lock_irqsave(&ebu_lock, flags);
-
- cfg_base = ifxmips_pci_mapped_cfg;
- cfg_base |= (bus->number << IFXMIPS_PCI_CFG_BUSNUM_SHF) | (devfn <<
- IFXMIPS_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
-
- /* Perform access */
- if (access_type == PCI_ACCESS_WRITE)
- {
-#ifdef CONFIG_SWAP_IO_SPACE
- ifxmips_w32(swab32(*data), ((u32*)cfg_base));
-#else
- ifxmips_w32(*data, ((u32*)cfg_base));
-#endif
- } else {
- *data = ifxmips_r32(((u32*)(cfg_base)));
-#ifdef CONFIG_SWAP_IO_SPACE
- *data = swab32(*data);
-#endif
- }
- wmb();
-
- /* clean possible Master abort */
- cfg_base = (ifxmips_pci_mapped_cfg | (0x0 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
- temp = ifxmips_r32(((u32*)(cfg_base)));
-#ifdef CONFIG_SWAP_IO_SPACE
- temp = swab32 (temp);
-#endif
- cfg_base = (ifxmips_pci_mapped_cfg | (0x68 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
- ifxmips_w32(temp, ((u32*)cfg_base));
-
- spin_unlock_irqrestore(&ebu_lock, flags);
-
- if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
- return 1;
-
- return 0;
-}
-
-int
-ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 * val)
-{
- u32 data = 0;
-
- if (ifxmips_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- if (size == 1)
- *val = (data >> ((where & 3) << 3)) & 0xff;
- else if (size == 2)
- *val = (data >> ((where & 3) << 3)) & 0xffff;
- else
- *val = data;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-int
-ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 val)
-{
- u32 data = 0;
-
- if (size == 4)
- {
- data = val;
- } else {
- if (ifxmips_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- if (size == 1)
- data = (data & ~(0xff << ((where & 3) << 3))) |
- (val << ((where & 3) << 3));
- else if (size == 2)
- data = (data & ~(0xffff << ((where & 3) << 3))) |
- (val << ((where & 3) << 3));
- }
-
- if (ifxmips_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- return PCIBIOS_SUCCESSFUL;
-}
+++ /dev/null
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/mm.h>
-#include <asm/addrspace.h>
-#include <linux/vmalloc.h>
-#include <ifxmips.h>
-#include <ifxmips_irq.h>
-#include <ifxmips_cgu.h>
-
-#define IFXMIPS_PCI_MEM_BASE 0x18000000
-#define IFXMIPS_PCI_MEM_SIZE 0x02000000
-#define IFXMIPS_PCI_IO_BASE 0x1AE00000
-#define IFXMIPS_PCI_IO_SIZE 0x00200000
-
-extern int ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
-extern int ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
-
-struct pci_ops ifxmips_pci_ops =
-{
- .read = ifxmips_pci_read_config_dword,
- .write = ifxmips_pci_write_config_dword
-};
-
-static struct resource pci_io_resource =
-{
- .name = "io pci IO space",
- .start = IFXMIPS_PCI_IO_BASE,
- .end = IFXMIPS_PCI_IO_BASE + IFXMIPS_PCI_IO_SIZE - 1,
- .flags = IORESOURCE_IO
-};
-
-static struct resource pci_mem_resource =
-{
- .name = "ext pci memory space",
- .start = IFXMIPS_PCI_MEM_BASE,
- .end = IFXMIPS_PCI_MEM_BASE + IFXMIPS_PCI_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM
-};
-
-static struct pci_controller ifxmips_pci_controller =
-{
- .pci_ops = &ifxmips_pci_ops,
- .mem_resource = &pci_mem_resource,
- .mem_offset = 0x00000000UL,
- .io_resource = &pci_io_resource,
- .io_offset = 0x00000000UL,
-};
-
-/* the cpu can can generate the 33Mhz or rely on an external clock the cgu needs the
- proper setting, otherwise the cpu hangs. we have no way of runtime detecting this */
-u32 ifxmips_pci_mapped_cfg;
-int ifxmips_pci_external_clock = 0;
-
-/* Since the PCI REQ pins can be reused for other functionality, make it possible
- to exclude those from interpretation by the PCI controller */
-int ifxmips_pci_req_mask = 0xf;
-
-static int __init
-ifxmips_pci_set_external_clk(char *str)
-{
- printk("cgu: setting up external pci clock\n");
- ifxmips_pci_external_clock = 1;
- return 1;
-}
-__setup("pci_external_clk", ifxmips_pci_set_external_clk);
-
-int
-pcibios_plat_dev_init(struct pci_dev *dev)
-{
- u8 pin;
-
- pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
- switch(pin)
- {
- case 0:
- break;
- case 1:
- //falling edge level triggered:0x4, low level:0xc, rising edge:0x2
- ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_CON) | 0xc, IFXMIPS_EBU_PCC_CON);
- ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_IEN) | 0x10, IFXMIPS_EBU_PCC_IEN);
- break;
- case 2:
- case 3:
- case 4:
- printk ("WARNING: interrupt pin %d not supported yet!\n", pin);
- default:
- printk ("WARNING: invalid interrupt pin %d\n", pin);
- return 1;
- }
- return 0;
-}
-
-static u32 calc_bar11mask(void)
-{
- u32 mem, bar11mask;
-
- /* BAR11MASK value depends on available memory on system. */
- mem = num_physpages * PAGE_SIZE;
- bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) -1)) -1)) | 8;
-
- return bar11mask;
-}
-
-static void __init
-ifxmips_pci_startup(void)
-{
- u32 temp_buffer;
-
- cgu_setup_pci_clk(ifxmips_pci_external_clock);
-
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD);
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR);
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1);
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0);
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) & ~0x2000, IFXMIPS_GPIO_P1_DIR);
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | 0x4000, IFXMIPS_GPIO_P1_DIR);
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1);
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0);
- /* enable auto-switching between PCI and EBU */
- ifxmips_w32(0xa, PCI_CR_CLK_CTRL);
- /* busy, i.e. configuration is not done, PCI access has to be retried */
- ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
- wmb ();
- /* BUS Master/IO/MEM access */
- ifxmips_w32(ifxmips_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
-
- /* enable external 2 PCI masters */
- temp_buffer = ifxmips_r32(PCI_CR_PC_ARB);
- temp_buffer &= (~(ifxmips_pci_req_mask << 16));
- /* enable internal arbiter */
- temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
- /* enable internal PCI master reqest */
- temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
-
- /* enable EBU reqest */
- temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
-
- /* enable all external masters request */
- temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
- ifxmips_w32(temp_buffer, PCI_CR_PC_ARB);
- wmb ();
-
- ifxmips_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
- ifxmips_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
- ifxmips_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
- ifxmips_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
- ifxmips_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
- ifxmips_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
- ifxmips_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
- ifxmips_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
- ifxmips_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
- ifxmips_w32(calc_bar11mask(), PCI_CR_BAR11MASK);
- ifxmips_w32(0, PCI_CR_PCI_ADDR_MAP11);
- ifxmips_w32(0, PCI_CS_BASE_ADDR1);
-#ifdef CONFIG_SWAP_IO_SPACE
- /* both TX and RX endian swap are enabled */
- ifxmips_w32(ifxmips_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
- wmb ();
-#endif
- /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
- ifxmips_w32(ifxmips_r32(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
- ifxmips_w32(ifxmips_r32(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
- /*use 8 dw burst length */
- ifxmips_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
- ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
- wmb();
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT);
- wmb();
- mdelay(1);
- ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
-}
-
-int __init
-pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
- switch(slot)
- {
- case 13:
- /* IDSEL = AD29 --> USB Host Controller */
- return (INT_NUM_IM1_IRL0 + 17);
- case 14:
- /* IDSEL = AD30 --> mini PCI connector */
- return (INT_NUM_IM0_IRL0 + 22);
- default:
- printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin);
- return 0;
- }
-}
-
-int __init
-pcibios_init(void)
-{
- extern int pci_probe_only;
-
- pci_probe_only = 0;
- printk("PCI: Probing PCI hardware on host bus 0.\n");
- ifxmips_pci_startup ();
- ifxmips_pci_mapped_cfg = (u32)ioremap_nocache(0x17000000, 0x800 * 16);
- printk("IFXMips PCI mapped to 0x%08lX\n", (unsigned long)ifxmips_pci_mapped_cfg);
- ifxmips_pci_controller.io_map_base = (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE, IFXMIPS_PCI_IO_SIZE - 1);
- printk("IFXMips PCI I/O mapped to 0x%08lX\n", (unsigned long)ifxmips_pci_controller.io_map_base);
- register_pci_controller(&ifxmips_pci_controller);
- return 0;
-}
-
-arch_initcall(pcibios_init);
+++ /dev/null
-obj-$(CONFIG_CRYPTO_DEV_IFXMIPS) += ifxmips_deu.o
-obj-$(CONFIG_CRYPTO_DEV_IFXMIPS) += ifxmips_deu_danube.o
-obj-$(CONFIG_CRYPTO_DEV_IFXMIPS_DES) += ifxmips_des.o
-obj-$(CONFIG_CRYPTO_DEV_IFXMIPS_AES) += ifxmips_aes.o
-obj-$(CONFIG_CRYPTO_DEV_IFXMIPS_ARC4) += ifxmips_arc4.o
-obj-$(CONFIG_CRYPTO_DEV_IFXMIPS_SHA1) += ifxmips_sha1.o
-obj-$(CONFIG_CRYPTO_DEV_IFXMIPS_SHA1_HMAC) += ifxmips_sha1_hmac.o
-obj-$(CONFIG_CRYPTO_DEV_IFXMIPS_MD5) += ifxmips_mda5.o
-obj-$(CONFIG_CRYPTO_DEV_IFXMIPS_MDA5_HMAC) += ifxmips_mda5_hmac.o
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
- * Copyright (C) 2009 Mohammad Firdaus
- */
-
-/*!
- \defgroup IFX_DEU IFX_DEU_DRIVERS
- \ingroup API
- \brief ifx DEU driver module
-*/
-
-/*!
- \file ifxmips_aes.c
- \ingroup IFX_DEU
- \brief AES Encryption Driver main file
-*/
-
-/*!
- \defgroup IFX_AES_FUNCTIONS IFX_AES_FUNCTIONS
- \ingroup IFX_DEU
- \brief IFX AES driver Functions
-*/
-
-
-/* Project Header Files */
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/crypto.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <asm/byteorder.h>
-#include <crypto/algapi.h>
-#include "ifxmips_deu.h"
-
-/* DMA related header and variables */
-#ifdef CONFIG_CRYPTO_DEV_DMA
-#include "ifxmips_deu_dma.h"
-#include <asm/ifx/irq.h>
-#include <asm/ifx/ifx_dma_core.h>
-extern _ifx_deu_device ifx_deu[1];
-extern u32 *aes_buff_in;
-extern u32 *aes_buff_out;
-#ifndef CONFIG_CRYPTO_DEV_POLL_DMA
-#define CONFIG_CRYPTO_DEV_POLL_DMA
-#endif
-#endif /* CONFIG_CRYPTO_DEV_DMA */
-
-spinlock_t aes_lock;
-#define CRTCL_SECT_INIT spin_lock_init(&aes_lock)
-#define CRTCL_SECT_START spin_lock_irqsave(&aes_lock, flag)
-#define CRTCL_SECT_END spin_unlock_irqrestore(&aes_lock, flag)
-
-/* Definition of constants */
-#define AES_START IFX_AES_CON
-#define AES_MIN_KEY_SIZE 16
-#define AES_MAX_KEY_SIZE 32
-#define AES_BLOCK_SIZE 16
-#define CTR_RFC3686_NONCE_SIZE 4
-#define CTR_RFC3686_IV_SIZE 8
-#define CTR_RFC3686_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE)
-
-/* Function decleration */
-int aes_chip_init(void);
-u32 endian_swap(u32 input);
-u32 input_swap(u32 input);
-u32* memory_alignment(const u8 *arg, u32 *buff_alloc, int in_out, int nbytes);
-void aes_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);
-void des_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);
-int aes_memory_allocate(int value);
-int des_memory_allocate(int value);
-void memory_release(u32 *addr);
-
-#ifndef CONFIG_CRYPTO_DEV_DMA
-extern void ifx_deu_aes (void *ctx_arg, uint8_t *out_arg, const uint8_t *in_arg,
- uint8_t *iv_arg, size_t nbytes, int encdec, int mode);
-#else
-extern void ifx_deu_aes_core (void *ctx_arg, uint8_t *out_arg, const uint8_t *in_arg,
- uint8_t *iv_arg, size_t nbytes, int encdec, int mode);
-#endif
-/* End of function decleration */
-
-struct aes_ctx {
- int key_length;
- u32 buf[AES_MAX_KEY_SIZE];
- u8 nonce[CTR_RFC3686_NONCE_SIZE];
-};
-
-
-extern int disable_deudma;
-
-
-/*! \fn int aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief sets the AES keys
- * \param tfm linux crypto algo transform
- * \param in_key input key
- * \param key_len key lengths of 16, 24 and 32 bytes supported
- * \return -EINVAL - bad key length, 0 - SUCCESS
-*/
-int aes_set_key (struct crypto_tfm *tfm, const u8 *in_key, unsigned int key_len)
-{
- struct aes_ctx *ctx = crypto_tfm_ctx(tfm);
- u32 *flags = &tfm->crt_flags;
-
- DPRINTF(0, "ctx @%p, key_len %d\n", ctx, key_len);
-
- if (key_len != 16 && key_len != 24 && key_len != 32) {
- *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
- return -EINVAL;
- }
-
- ctx->key_length = key_len;
- memcpy ((u8 *) (ctx->buf), in_key, key_len);
-
- return 0;
-}
-
-
-#ifndef CONFIG_CRYPTO_DEV_DMA
-/*! \fn void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, size_t nbytes, int encdec, int mode)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief main interface to AES hardware
- * \param ctx_arg crypto algo context
- * \param out_arg output bytestream
- * \param in_arg input bytestream
- * \param iv_arg initialization vector
- * \param nbytes length of bytestream
- * \param encdec 1 for encrypt; 0 for decrypt
- * \param mode operation mode such as ebc, cbc, ctr
- *
-*/
-void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg,
- u8 *iv_arg, size_t nbytes, int encdec, int mode)
-#else
-
-/*! \fn void ifx_deu_aes_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, size_t nbytes, int encdec, int mode)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief main interface to AES hardware
- * \param ctx_arg crypto algo context
- * \param out_arg output bytestream
- * \param in_arg input bytestream
- * \param iv_arg initialization vector
- * \param nbytes length of bytestream
- * \param encdec 1 for encrypt; 0 for decrypt
- * \param mode operation mode such as ebc, cbc, ctr
- *
-*/
-void ifx_deu_aes_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg,
- u8 *iv_arg, size_t nbytes, int encdec, int mode)
-#endif
-
-{
- /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
- volatile struct aes_t *aes = (volatile struct aes_t *) AES_START;
- struct aes_ctx *ctx = (struct aes_ctx *)ctx_arg;
- u32 *in_key = ctx->buf;
- ulong flag;
- /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
- int key_len = ctx->key_length;
-
-#ifndef CONFIG_CRYPTO_DEV_DMA
- int i = 0;
- int byte_cnt = nbytes;
-
-#else
- volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON;
- struct dma_device_info *dma_device = ifx_deu[0].dma_device;
- //deu_drv_priv_t *deu_priv = (deu_drv_priv_t *)dma_device->priv;
- int wlen = 0;
- u32 *outcopy = NULL;
- u32 *dword_mem_aligned_in = NULL;
-
-#ifdef CONFIG_CRYPTO_DEV_POLL_DMA
- u32 timeout = 0;
- u32 *out_dma = NULL;
-#endif
-
-#endif
-
- DPRINTF(0, "ctx @%p, mode %d, encdec %d\n", ctx, mode, encdec);
-
- CRTCL_SECT_START;
-
- /* 128, 192 or 256 bit key length */
- aes->controlr.K = key_len / 8 - 2;
- if (key_len == 128 / 8) {
- aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));
- aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));
- aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));
- aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));
- }
- else if (key_len == 192 / 8) {
- aes->K5R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));
- aes->K4R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));
- aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));
- aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));
- aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 4));
- aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 5));
- }
- else if (key_len == 256 / 8) {
- aes->K7R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));
- aes->K6R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));
- aes->K5R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));
- aes->K4R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));
- aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 4));
- aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 5));
- aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 6));
- aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 7));
- }
- else {
- printk (KERN_ERR "[%s %s %d]: Invalid key_len : %d\n", __FILE__, __func__, __LINE__, key_len);
- CRTCL_SECT_END;
- return;// -EINVAL;
- }
-
- /* let HW pre-process DEcryption key in any case (even if
- ENcryption is used). Key Valid (KV) bit is then only
- checked in decryption routine! */
- aes->controlr.PNK = 1;
-
-#ifdef CONFIG_CRYPTO_DEV_DMA
- while (aes->controlr.BUS) {
- // this will not take long
- }
- AES_DMA_MISC_CONFIG();
-#endif
-
- aes->controlr.E_D = !encdec; /* encryption */
- aes->controlr.O = mode; /* 0 ECB 1 CBC 2 OFB 3 CFB 4 CTR */
- aes->controlr.SM = 1; /* start after writing input register */
- aes->controlr.DAU = 0; /* Disable Automatic Update of init vector */
- aes->controlr.ARS = 1; /* Autostart Select - write to IHR */
-
- //aes->controlr.F = 128; //default; only for CFB and OFB modes; change only for customer-specific apps
- if (mode > 0) {
- aes->IV3R = DEU_ENDIAN_SWAP(*(u32 *) iv_arg);
- aes->IV2R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1));
- aes->IV1R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 2));
- aes->IV0R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 3));
- };
-
-#ifndef CONFIG_CRYPTO_DEV_DMA
- i = 0;
- while (byte_cnt >= 16) {
-
- aes->ID3R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 0));
- aes->ID2R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 1));
- aes->ID1R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 2));
- aes->ID0R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 3)); /* start crypto */
-
- while (aes->controlr.BUS) {
- // this will not take long
- }
-
- *((volatile u32 *) out_arg + (i * 4) + 0) = aes->OD3R;
- *((volatile u32 *) out_arg + (i * 4) + 1) = aes->OD2R;
- *((volatile u32 *) out_arg + (i * 4) + 2) = aes->OD1R;
- *((volatile u32 *) out_arg + (i * 4) + 3) = aes->OD0R;
-
- i++;
- byte_cnt -= 16;
- }
-
-#else // dma
-
- /* Prepare Rx buf length used in dma psuedo interrupt */
- //deu_priv->deu_rx_buf = out_arg;
- //deu_priv->deu_rx_len = nbytes;
-
- /* memory alignment issue */
- dword_mem_aligned_in = (u32 *) DEU_DWORD_REORDERING(in_arg, aes_buff_in, BUFFER_IN, nbytes);
-
- dma->controlr.ALGO = 1; //AES
- dma->controlr.BS = 0;
- aes->controlr.DAU = 0;
- dma->controlr.EN = 1;
-
- while (aes->controlr.BUS) {
- // wait for AES to be ready
- };
-
- wlen = dma_device_write (dma_device, (u8 *)dword_mem_aligned_in, nbytes, NULL);
- if (wlen != nbytes) {
- dma->controlr.EN = 0;
- CRTCL_SECT_END;
- printk (KERN_ERR "[%s %s %d]: dma_device_write fail!\n", __FILE__, __func__, __LINE__);
- return; // -EINVAL;
- }
-
- WAIT_AES_DMA_READY();
-
-#ifdef CONFIG_CRYPTO_DEV_POLL_DMA
-
- outcopy = (u32 *) DEU_DWORD_REORDERING(out_arg, aes_buff_out, BUFFER_OUT, nbytes);
-
- // polling DMA rx channel
- while ((dma_device_read (dma_device, (u8 **) &out_dma, NULL)) == 0) {
- timeout++;
-
- if (timeout >= 333000) {
- dma->controlr.EN = 0;
- CRTCL_SECT_END;
- printk (KERN_ERR "[%s %s %d]: timeout!!\n", __FILE__, __func__, __LINE__);
- return; // -EINVAL;
- }
- }
-
- WAIT_AES_DMA_READY();
-
- AES_MEMORY_COPY(outcopy, out_dma, out_arg, nbytes);
-
-#else // not working at the moment..
- CRTCL_SECT_END;
-
- /* Sleep and wait for Rx finished */
- DEU_WAIT_EVENT(deu_priv->deu_thread_wait, DEU_EVENT, deu_priv->deu_event_flags);
-
- CRTCL_SECT_START;
-#endif
-
-#endif // dma
-
- //tc.chen : copy iv_arg back
- if (mode > 0) {
- *((u32 *) iv_arg) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg));
- *((u32 *) iv_arg + 1) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1));
- *((u32 *) iv_arg + 2) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 2));
- *((u32 *) iv_arg + 3) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 3));
- }
-
- CRTCL_SECT_END;
-}
-
-/*!
- * \fn int ctr_rfc3686_aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief sets RFC3686 key
- * \param tfm linux crypto algo transform
- * \param in_key input key
- * \param key_len key lengths of 20, 28 and 36 bytes supported; last 4 bytes is nonce
- * \return 0 - SUCCESS
- * -EINVAL - bad key length
-*/
-int ctr_rfc3686_aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len)
-{
- struct aes_ctx *ctx = crypto_tfm_ctx(tfm);
- u32 *flags = &tfm->crt_flags;
-
- printk("ctr_rfc3686_aes_set_key in %s\n", __FILE__);
-
- memcpy(ctx->nonce, in_key + (key_len - CTR_RFC3686_NONCE_SIZE),
- CTR_RFC3686_NONCE_SIZE);
-
- key_len -= CTR_RFC3686_NONCE_SIZE; // remove 4 bytes of nonce
-
- if (key_len != 16 && key_len != 24 && key_len != 32) {
- *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
- return -EINVAL;
- }
-
- ctx->key_length = key_len;
-
- memcpy ((u8 *) (ctx->buf), in_key, key_len);
-
- return 0;
-}
-
-/*! \fn void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief main interface with deu hardware in DMA mode
- * \param ctx_arg crypto algo context
- * \param out_arg output bytestream
- * \param in_arg input bytestream
- * \param iv_arg initialization vector
- * \param nbytes length of bytestream
- * \param encdec 1 for encrypt; 0 for decrypt
- * \param mode operation mode such as ebc, cbc, ctr
-*/
-
-#ifdef CONFIG_CRYPTO_DEV_DMA
-void ifx_deu_aes (void *ctx_arg, u8 * out_arg, const u8 * in_arg,
- u8 * iv_arg, u32 nbytes, int encdec, int mode)
-{
- u32 remain = nbytes;
- u32 inc;
-
- while (remain > 0)
- {
- if (remain >= DEU_MAX_PACKET_SIZE)
- {
- inc = DEU_MAX_PACKET_SIZE;
- }
- else
- {
- inc = remain;
- }
-
- remain -= inc;
-
- ifx_deu_aes_core(ctx_arg, out_arg, in_arg, iv_arg, inc, encdec, mode);
-
- out_arg += inc;
- in_arg += inc;
- }
-
-}
-#endif
-
-//definitions from linux/include/crypto.h:
-//#define CRYPTO_TFM_MODE_ECB 0x00000001
-//#define CRYPTO_TFM_MODE_CBC 0x00000002
-//#define CRYPTO_TFM_MODE_CFB 0x00000004
-//#define CRYPTO_TFM_MODE_CTR 0x00000008
-//#define CRYPTO_TFM_MODE_OFB 0x00000010 // not even defined
-//but hardware definition: 0 ECB 1 CBC 2 OFB 3 CFB 4 CTR
-
-/*! \fn void ifx_deu_aes_ecb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief sets AES hardware to ECB mode
- * \param ctx crypto algo context
- * \param dst output bytestream
- * \param src input bytestream
- * \param iv initialization vector
- * \param nbytes length of bytestream
- * \param encdec 1 for encrypt; 0 for decrypt
- * \param inplace not used
-*/
-void ifx_deu_aes_ecb (void *ctx, uint8_t *dst, const uint8_t *src,
- uint8_t *iv, size_t nbytes, int encdec, int inplace)
-{
- ifx_deu_aes (ctx, dst, src, NULL, nbytes, encdec, 0);
-}
-
-/*! \fn void ifx_deu_aes_cbc (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief sets AES hardware to CBC mode
- * \param ctx crypto algo context
- * \param dst output bytestream
- * \param src input bytestream
- * \param iv initialization vector
- * \param nbytes length of bytestream
- * \param encdec 1 for encrypt; 0 for decrypt
- * \param inplace not used
-*/
-void ifx_deu_aes_cbc (void *ctx, uint8_t *dst, const uint8_t *src,
- uint8_t *iv, size_t nbytes, int encdec, int inplace)
-{
- ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 1);
-}
-
-/*! \fn void ifx_deu_aes_ofb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief sets AES hardware to OFB mode
- * \param ctx crypto algo context
- * \param dst output bytestream
- * \param src input bytestream
- * \param iv initialization vector
- * \param nbytes length of bytestream
- * \param encdec 1 for encrypt; 0 for decrypt
- * \param inplace not used
-*/
-void ifx_deu_aes_ofb (void *ctx, uint8_t *dst, const uint8_t *src,
- uint8_t *iv, size_t nbytes, int encdec, int inplace)
-{
- ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 2);
-}
-
-/*! \fn void ifx_deu_aes_cfb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief sets AES hardware to CFB mode
- * \param ctx crypto algo context
- * \param dst output bytestream
- * \param src input bytestream
- * \param iv initialization vector
- * \param nbytes length of bytestream
- * \param encdec 1 for encrypt; 0 for decrypt
- * \param inplace not used
-*/
-void ifx_deu_aes_cfb (void *ctx, uint8_t *dst, const uint8_t *src,
- uint8_t *iv, size_t nbytes, int encdec, int inplace)
-{
- ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 3);
-}
-
-/*! \fn void ifx_deu_aes_ctr (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief sets AES hardware to CTR mode
- * \param ctx crypto algo context
- * \param dst output bytestream
- * \param src input bytestream
- * \param iv initialization vector
- * \param nbytes length of bytestream
- * \param encdec 1 for encrypt; 0 for decrypt
- * \param inplace not used
-*/
-void ifx_deu_aes_ctr (void *ctx, uint8_t *dst, const uint8_t *src,
- uint8_t *iv, size_t nbytes, int encdec, int inplace)
-{
- ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 4);
-}
-
-/*! \fn void aes_encrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief encrypt AES_BLOCK_SIZE of data
- * \param tfm linux crypto algo transform
- * \param out output bytestream
- * \param in input bytestream
-*/
-void aes_encrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
-{
- struct aes_ctx *ctx = crypto_tfm_ctx(tfm);
- ifx_deu_aes (ctx, out, in, NULL, AES_BLOCK_SIZE,
- CRYPTO_DIR_ENCRYPT, 0);
-
-}
-
-/*! \fn void aes_decrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief decrypt AES_BLOCK_SIZE of data
- * \param tfm linux crypto algo transform
- * \param out output bytestream
- * \param in input bytestream
-*/
-void aes_decrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
-{
- struct aes_ctx *ctx = crypto_tfm_ctx(tfm);
- ifx_deu_aes (ctx, out, in, NULL, AES_BLOCK_SIZE,
- CRYPTO_DIR_DECRYPT, 0);
-}
-
-/*
- * \brief AES function mappings
-*/
-struct crypto_alg ifxdeu_aes_alg = {
- .cra_name = "aes",
- .cra_driver_name = "ifxdeu-aes",
- .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct aes_ctx),
- .cra_module = THIS_MODULE,
- .cra_list = LIST_HEAD_INIT(ifxdeu_aes_alg.cra_list),
- .cra_u = {
- .cipher = {
- .cia_min_keysize = AES_MIN_KEY_SIZE,
- .cia_max_keysize = AES_MAX_KEY_SIZE,
- .cia_setkey = aes_set_key,
- .cia_encrypt = aes_encrypt,
- .cia_decrypt = aes_decrypt,
- }
- }
-};
-
-/*! \fn int ecb_aes_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief ECB AES encrypt using linux crypto blkcipher
- * \param desc blkcipher descriptor
- * \param dst output scatterlist
- * \param src input scatterlist
- * \param nbytes data size in bytes
- * \return err
-*/
-int ecb_aes_encrypt(struct blkcipher_desc *desc,
- struct scatterlist *dst, struct scatterlist *src,
- unsigned int nbytes)
-{
- struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
- struct blkcipher_walk walk;
- int err;
-
- blkcipher_walk_init(&walk, dst, src, nbytes);
- err = blkcipher_walk_virt(desc, &walk);
-
- while ((nbytes = walk.nbytes)) {
- nbytes -= (nbytes % AES_BLOCK_SIZE);
- ifx_deu_aes_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr,
- NULL, nbytes, CRYPTO_DIR_ENCRYPT, 0);
- nbytes &= AES_BLOCK_SIZE - 1;
- err = blkcipher_walk_done(desc, &walk, nbytes);
- }
-
- return err;
-}
-
-/*! \fn int ecb_aes_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief ECB AES decrypt using linux crypto blkcipher
- * \param desc blkcipher descriptor
- * \param dst output scatterlist
- * \param src input scatterlist
- * \param nbytes data size in bytes
- * \return err
-*/
-int ecb_aes_decrypt(struct blkcipher_desc *desc,
- struct scatterlist *dst, struct scatterlist *src,
- unsigned int nbytes)
-{
- struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
- struct blkcipher_walk walk;
- int err;
-
- blkcipher_walk_init(&walk, dst, src, nbytes);
- err = blkcipher_walk_virt(desc, &walk);
-
- while ((nbytes = walk.nbytes)) {
- nbytes -= (nbytes % AES_BLOCK_SIZE);
- ifx_deu_aes_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr,
- NULL, nbytes, CRYPTO_DIR_DECRYPT, 0);
- nbytes &= AES_BLOCK_SIZE - 1;
- err = blkcipher_walk_done(desc, &walk, nbytes);
- }
-
- return err;
-}
-
-/*
- * \brief AES function mappings
-*/
-struct crypto_alg ifxdeu_ecb_aes_alg = {
- .cra_name = "ecb(aes)",
- .cra_driver_name = "ifxdeu-ecb(aes)",
- .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct aes_ctx),
- .cra_type = &crypto_blkcipher_type,
- .cra_module = THIS_MODULE,
- .cra_list = LIST_HEAD_INIT(ifxdeu_ecb_aes_alg.cra_list),
- .cra_u = {
- .blkcipher = {
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .setkey = aes_set_key,
- .encrypt = ecb_aes_encrypt,
- .decrypt = ecb_aes_decrypt,
- }
- }
-};
-
-
-/*! \fn int cbc_aes_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief CBC AES encrypt using linux crypto blkcipher
- * \param desc blkcipher descriptor
- * \param dst output scatterlist
- * \param src input scatterlist
- * \param nbytes data size in bytes
- * \return err
-*/
-int cbc_aes_encrypt(struct blkcipher_desc *desc,
- struct scatterlist *dst, struct scatterlist *src,
- unsigned int nbytes)
-{
- struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
- struct blkcipher_walk walk;
- int err;
-
- blkcipher_walk_init(&walk, dst, src, nbytes);
- err = blkcipher_walk_virt(desc, &walk);
-
- while ((nbytes = walk.nbytes)) {
- u8 *iv = walk.iv;
- nbytes -= (nbytes % AES_BLOCK_SIZE);
- ifx_deu_aes_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr,
- iv, nbytes, CRYPTO_DIR_ENCRYPT, 0);
- nbytes &= AES_BLOCK_SIZE - 1;
- err = blkcipher_walk_done(desc, &walk, nbytes);
- }
-
- return err;
-}
-
-/*! \fn int cbc_aes_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief CBC AES decrypt using linux crypto blkcipher
- * \param desc blkcipher descriptor
- * \param dst output scatterlist
- * \param src input scatterlist
- * \param nbytes data size in bytes
- * \return err
-*/
-int cbc_aes_decrypt(struct blkcipher_desc *desc,
- struct scatterlist *dst, struct scatterlist *src,
- unsigned int nbytes)
-{
- struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
- struct blkcipher_walk walk;
- int err;
-
- blkcipher_walk_init(&walk, dst, src, nbytes);
- err = blkcipher_walk_virt(desc, &walk);
-
- while ((nbytes = walk.nbytes)) {
- u8 *iv = walk.iv;
- nbytes -= (nbytes % AES_BLOCK_SIZE);
- ifx_deu_aes_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr,
- iv, nbytes, CRYPTO_DIR_DECRYPT, 0);
- nbytes &= AES_BLOCK_SIZE - 1;
- err = blkcipher_walk_done(desc, &walk, nbytes);
- }
-
- return err;
-}
-
-/*
- * \brief AES function mappings
-*/
-struct crypto_alg ifxdeu_cbc_aes_alg = {
- .cra_name = "cbc(aes)",
- .cra_driver_name = "ifxdeu-cbc(aes)",
- .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct aes_ctx),
- .cra_type = &crypto_blkcipher_type,
- .cra_module = THIS_MODULE,
- .cra_list = LIST_HEAD_INIT(ifxdeu_cbc_aes_alg.cra_list),
- .cra_u = {
- .blkcipher = {
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .ivsize = AES_BLOCK_SIZE,
- .setkey = aes_set_key,
- .encrypt = cbc_aes_encrypt,
- .decrypt = cbc_aes_decrypt,
- }
- }
-};
-
-
-/*! \fn int ctr_basic_aes_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief Counter mode AES encrypt using linux crypto blkcipher
- * \param desc blkcipher descriptor
- * \param dst output scatterlist
- * \param src input scatterlist
- * \param nbytes data size in bytes
- * \return err
-*/
-int ctr_basic_aes_encrypt(struct blkcipher_desc *desc,
- struct scatterlist *dst, struct scatterlist *src,
- unsigned int nbytes)
-{
- struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
- struct blkcipher_walk walk;
- int err;
-
- blkcipher_walk_init(&walk, dst, src, nbytes);
- err = blkcipher_walk_virt(desc, &walk);
-
- while ((nbytes = walk.nbytes)) {
- u8 *iv = walk.iv;
- nbytes -= (nbytes % AES_BLOCK_SIZE);
- ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
- iv, nbytes, CRYPTO_DIR_ENCRYPT, 0);
- nbytes &= AES_BLOCK_SIZE - 1;
- err = blkcipher_walk_done(desc, &walk, nbytes);
- }
-
- return err;
-}
-
-/*! \fn int ctr_basic_aes_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief Counter mode AES decrypt using linux crypto blkcipher
- * \param desc blkcipher descriptor
- * \param dst output scatterlist
- * \param src input scatterlist
- * \param nbytes data size in bytes
- * \return err
-*/
-int ctr_basic_aes_decrypt(struct blkcipher_desc *desc,
- struct scatterlist *dst, struct scatterlist *src,
- unsigned int nbytes)
-{
- struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
- struct blkcipher_walk walk;
- int err;
-
- blkcipher_walk_init(&walk, dst, src, nbytes);
- err = blkcipher_walk_virt(desc, &walk);
-
- while ((nbytes = walk.nbytes)) {
- u8 *iv = walk.iv;
- nbytes -= (nbytes % AES_BLOCK_SIZE);
- ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
- iv, nbytes, CRYPTO_DIR_DECRYPT, 0);
- nbytes &= AES_BLOCK_SIZE - 1;
- err = blkcipher_walk_done(desc, &walk, nbytes);
- }
-
- return err;
-}
-
-/*
- * \brief AES function mappings
-*/
-struct crypto_alg ifxdeu_ctr_basic_aes_alg = {
- .cra_name = "ctr(aes)",
- .cra_driver_name = "ifxdeu-ctr(aes)",
- .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct aes_ctx),
- .cra_type = &crypto_blkcipher_type,
- .cra_module = THIS_MODULE,
- .cra_list = LIST_HEAD_INIT(ifxdeu_ctr_basic_aes_alg.cra_list),
- .cra_u = {
- .blkcipher = {
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .ivsize = AES_BLOCK_SIZE,
- .setkey = aes_set_key,
- .encrypt = ctr_basic_aes_encrypt,
- .decrypt = ctr_basic_aes_decrypt,
- }
- }
-};
-
-
-/*! \fn int ctr_rfc3686_aes_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief Counter mode AES (rfc3686) encrypt using linux crypto blkcipher
- * \param desc blkcipher descriptor
- * \param dst output scatterlist
- * \param src input scatterlist
- * \param nbytes data size in bytes
- * \return err
-*/
-int ctr_rfc3686_aes_encrypt(struct blkcipher_desc *desc,
- struct scatterlist *dst, struct scatterlist *src,
- unsigned int nbytes)
-{
- struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
- struct blkcipher_walk walk;
- int err;
- u8 rfc3686_iv[16];
-
- blkcipher_walk_init(&walk, dst, src, nbytes);
- err = blkcipher_walk_virt(desc, &walk);
-
- /* set up counter block */
- memcpy(rfc3686_iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
- memcpy(rfc3686_iv + CTR_RFC3686_NONCE_SIZE, walk.iv, CTR_RFC3686_IV_SIZE);
-
- /* initialize counter portion of counter block */
- *(__be32 *)(rfc3686_iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
- cpu_to_be32(1);
-
- while ((nbytes = walk.nbytes)) {
- nbytes -= (nbytes % AES_BLOCK_SIZE);
- ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
- rfc3686_iv, nbytes, CRYPTO_DIR_ENCRYPT, 0);
- nbytes &= AES_BLOCK_SIZE - 1;
- err = blkcipher_walk_done(desc, &walk, nbytes);
- }
-
- return err;
-}
-
-/*! \fn int ctr_rfc3686_aes_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief Counter mode AES (rfc3686) decrypt using linux crypto blkcipher
- * \param desc blkcipher descriptor
- * \param dst output scatterlist
- * \param src input scatterlist
- * \param nbytes data size in bytes
- * \return err
-*/
-int ctr_rfc3686_aes_decrypt(struct blkcipher_desc *desc,
- struct scatterlist *dst, struct scatterlist *src,
- unsigned int nbytes)
-{
- struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
- struct blkcipher_walk walk;
- int err;
- u8 rfc3686_iv[16];
-
- blkcipher_walk_init(&walk, dst, src, nbytes);
- err = blkcipher_walk_virt(desc, &walk);
-
- /* set up counter block */
- memcpy(rfc3686_iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
- memcpy(rfc3686_iv + CTR_RFC3686_NONCE_SIZE, walk.iv, CTR_RFC3686_IV_SIZE);
-
- /* initialize counter portion of counter block */
- *(__be32 *)(rfc3686_iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
- cpu_to_be32(1);
-
- while ((nbytes = walk.nbytes)) {
- nbytes -= (nbytes % AES_BLOCK_SIZE);
- ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
- rfc3686_iv, nbytes, CRYPTO_DIR_DECRYPT, 0);
- nbytes &= AES_BLOCK_SIZE - 1;
- err = blkcipher_walk_done(desc, &walk, nbytes);
- }
-
- return err;
-}
-
-/*
- * \brief AES function mappings
-*/
-struct crypto_alg ifxdeu_ctr_rfc3686_aes_alg = {
- .cra_name = "rfc3686(ctr(aes))",
- .cra_driver_name = "ifxdeu-ctr-rfc3686(aes)",
- .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct aes_ctx),
- .cra_type = &crypto_blkcipher_type,
- .cra_module = THIS_MODULE,
- .cra_list = LIST_HEAD_INIT(ifxdeu_ctr_rfc3686_aes_alg.cra_list),
- .cra_u = {
- .blkcipher = {
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = CTR_RFC3686_MAX_KEY_SIZE,
- .ivsize = CTR_RFC3686_IV_SIZE,
- .setkey = ctr_rfc3686_aes_set_key,
- .encrypt = ctr_rfc3686_aes_encrypt,
- .decrypt = ctr_rfc3686_aes_decrypt,
- }
- }
-};
-
-
-/*! \fn int __init ifxdeu_init_aes (void)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief function to initialize AES driver
- * \return ret
-*/
-int __init ifxdeu_init_aes (void)
-{
- int ret;
-
- if ((ret = crypto_register_alg(&ifxdeu_aes_alg)))
- goto aes_err;
-
- if ((ret = crypto_register_alg(&ifxdeu_ecb_aes_alg)))
- goto ecb_aes_err;
-
- if ((ret = crypto_register_alg(&ifxdeu_cbc_aes_alg)))
- goto cbc_aes_err;
-
- if ((ret = crypto_register_alg(&ifxdeu_ctr_basic_aes_alg)))
- goto ctr_basic_aes_err;
-
- if ((ret = crypto_register_alg(&ifxdeu_ctr_rfc3686_aes_alg)))
- goto ctr_rfc3686_aes_err;
-
- aes_chip_init ();
-
- CRTCL_SECT_INIT;
-
-#ifdef CONFIG_CRYPTO_DEV_DMA
- if (ALLOCATE_MEMORY(BUFFER_IN, AES_ALGO) < 0) {
- printk(KERN_ERR "[%s %s %d]: malloc memory fail!\n", __FILE__, __func__, __LINE__);
- goto ctr_rfc3686_aes_err;
- }
- if (ALLOCATE_MEMORY(BUFFER_OUT, AES_ALGO) < 0) {
- printk(KERN_ERR "[%s %s %d]: malloc memory fail!\n", __FILE__, __func__, __LINE__);
- goto ctr_rfc3686_aes_err;
- }
-#endif
-
- printk (KERN_NOTICE "IFX DEU AES initialized %s.\n", disable_deudma ? "" : " (DMA)");
- return ret;
-
-ctr_rfc3686_aes_err:
- crypto_unregister_alg(&ifxdeu_ctr_rfc3686_aes_alg);
- printk (KERN_ERR "IFX ctr_rfc3686_aes initialization failed!\n");
- return ret;
-ctr_basic_aes_err:
- crypto_unregister_alg(&ifxdeu_ctr_basic_aes_alg);
- printk (KERN_ERR "IFX ctr_basic_aes initialization failed!\n");
- return ret;
-cbc_aes_err:
- crypto_unregister_alg(&ifxdeu_cbc_aes_alg);
- printk (KERN_ERR "IFX cbc_aes initialization failed!\n");
- return ret;
-ecb_aes_err:
- crypto_unregister_alg(&ifxdeu_ecb_aes_alg);
- printk (KERN_ERR "IFX aes initialization failed!\n");
- return ret;
-aes_err:
- printk(KERN_ERR "IFX DEU AES initialization failed!\n");
- return ret;
-}
-
-/*! \fn void __exit ifxdeu_fini_aes (void)
- * \ingroup IFX_AES_FUNCTIONS
- * \brief unregister aes driver
-*/
-void __exit ifxdeu_fini_aes (void)
-{
- crypto_unregister_alg (&ifxdeu_aes_alg);
- crypto_unregister_alg (&ifxdeu_ecb_aes_alg);
- crypto_unregister_alg (&ifxdeu_cbc_aes_alg);
- crypto_unregister_alg (&ifxdeu_ctr_basic_aes_alg);
- crypto_unregister_alg (&ifxdeu_ctr_rfc3686_aes_alg);
-
-#ifdef CONFIG_CRYPTO_DEV_DMA
- FREE_MEMORY(aes_buff_in);
- FREE_MEMORY(aes_buff_out);
-#endif
-
-}
-
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
- * Copyright (C) 2009 Mohammad Firdaus
- */
-
-/*!
- \defgroup IFX_DEU IFX_DEU_DRIVERS
- \ingroup API
- \brief ifx deu driver module
-*/
-
-/*!
- \file ifxmips_arc4.c
- \ingroup IFX_DEU
- \brief ARC4 encryption DEU driver file
-*/
-
-/*!
- \defgroup IFX_ARC4_FUNCTIONS IFX_ARC4_FUNCTIONS
- \ingroup IFX_DEU
- \brief IFX deu driver functions
-*/
-
-/* Project header */
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/crypto.h>
-#include <crypto/algapi.h>
-#include <linux/interrupt.h>
-#include <asm/byteorder.h>
-#include <linux/delay.h>
-#include "ifxmips_deu.h"
-
-#ifdef CONFIG_CRYPTO_DEV_IFXMIPS_DMA
-
-static spinlock_t lock;
-#define CRTCL_SECT_INIT spin_lock_init(&lock)
-#define CRTCL_SECT_START spin_lock_irqsave(&lock, flag)
-#define CRTCL_SECT_END spin_unlock_irqrestore(&lock, flag)
-
-/* Preprocessor declerations */
-#define ARC4_MIN_KEY_SIZE 1
-//#define ARC4_MAX_KEY_SIZE 256
-#define ARC4_MAX_KEY_SIZE 16
-#define ARC4_BLOCK_SIZE 1
-#define ARC4_START IFX_ARC4_CON
-
-/*
- * \brief arc4 private structure
-*/
-struct arc4_ctx {
- int key_length;
- u8 buf[120];
-};
-
-extern int disable_deudma;
-
-/*! \fn static void _deu_arc4 (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode)
- \ingroup IFX_ARC4_FUNCTIONS
- \brief main interface to AES hardware
- \param ctx_arg crypto algo context
- \param out_arg output bytestream
- \param in_arg input bytestream
- \param iv_arg initialization vector
- \param nbytes length of bytestream
- \param encdec 1 for encrypt; 0 for decrypt
- \param mode operation mode such as ebc, cbc, ctr
-*/
-static void _deu_arc4 (void *ctx_arg, u8 *out_arg, const u8 *in_arg,
- u8 *iv_arg, u32 nbytes, int encdec, int mode)
-{
- volatile struct arc4_t *arc4 = (struct arc4_t *) ARC4_START;
- int i = 0;
- ulong flag;
-
-#if 1 // need to handle nbytes not multiple of 16
- volatile u32 tmp_array32[4];
- volatile u8 *tmp_ptr8;
- int remaining_bytes, j;
-#endif
-
- CRTCL_SECT_START;
-
- arc4->IDLEN = nbytes;
-
-#if 1
- while (i < nbytes) {
- arc4->ID3R = *((u32 *) in_arg + (i>>2) + 0);
- arc4->ID2R = *((u32 *) in_arg + (i>>2) + 1);
- arc4->ID1R = *((u32 *) in_arg + (i>>2) + 2);
- arc4->ID0R = *((u32 *) in_arg + (i>>2) + 3);
-
- arc4->controlr.GO = 1;
-
- while (arc4->controlr.BUS) {
- // this will not take long
- }
-
-#if 1
- // need to handle nbytes not multiple of 16
- tmp_array32[0] = arc4->OD3R;
- tmp_array32[1] = arc4->OD2R;
- tmp_array32[2] = arc4->OD1R;
- tmp_array32[3] = arc4->OD0R;
-
- remaining_bytes = nbytes - i;
- if (remaining_bytes > 16)
- remaining_bytes = 16;
-
- tmp_ptr8 = (u8 *)&tmp_array32[0];
- for (j = 0; j < remaining_bytes; j++)
- *out_arg++ = *tmp_ptr8++;
-#else
- *((u32 *) out_arg + (i>>2) + 0) = arc4->OD3R;
- *((u32 *) out_arg + (i>>2) + 1) = arc4->OD2R;
- *((u32 *) out_arg + (i>>2) + 2) = arc4->OD1R;
- *((u32 *) out_arg + (i>>2) + 3) = arc4->OD0R;
-#endif
-
- i += 16;
- }
-#else // dma
-
-
-#endif // dma
-
- CRTCL_SECT_END;
-}
-
-/*! \fn arc4_chip_init (void)
- \ingroup IFX_ARC4_FUNCTIONS
- \brief initialize arc4 hardware
-*/
-static void arc4_chip_init (void)
-{
- //do nothing
-}
-
-/*! \fn static int arc4_set_key(struct crypto_tfm *tfm, const u8 *in_key, unsigned int key_len)
- \ingroup IFX_ARC4_FUNCTIONS
- \brief sets ARC4 key
- \param tfm linux crypto algo transform
- \param in_key input key
- \param key_len key lengths less than or equal to 16 bytes supported
-*/
-static int arc4_set_key(struct crypto_tfm *tfm, const u8 *inkey,
- unsigned int key_len)
-{
- //struct arc4_ctx *ctx = crypto_tfm_ctx(tfm);
- volatile struct arc4_t *arc4 = (struct arc4_t *) ARC4_START;
-
- u32 *in_key = (u32 *)inkey;
-
- // must program all bits at one go?!!!
-#if 1
-//#ifndef CONFIG_CRYPTO_DEV_VR9_DMA
- *IFX_ARC4_CON = ( (1<<31) | ((key_len - 1)<<27) | (1<<26) | (3<<16) );
- //NDC=1,ENDI=1,GO=0,KSAE=1,SM=0
-
- arc4->K3R = *((u32 *) in_key + 0);
- arc4->K2R = *((u32 *) in_key + 1);
- arc4->K1R = *((u32 *) in_key + 2);
- arc4->K0R = *((u32 *) in_key + 3);
-#else //dma
- *AMAZONS_ARC4_CON = ( (1<<31) | ((key_len - 1)<<27) | (1<<26) | (3<<16) | (1<<4) );
- //NDC=1,ENDI=1,GO=0,KSAE=1,SM=1
-
- arc4->K3R = *((u32 *) in_key + 0);
- arc4->K2R = *((u32 *) in_key + 1);
- arc4->K1R = *((u32 *) in_key + 2);
- arc4->K0R = *((u32 *) in_key + 3);
-
-#if 0
- arc4->K3R = endian_swap(*((u32 *) in_key + 0));
- arc4->K2R = endian_swap(*((u32 *) in_key + 1));
- arc4->K1R = endian_swap(*((u32 *) in_key + 2));
- arc4->K0R = endian_swap(*((u32 *) in_key + 3));
-#endif
-
-#endif
-
-#if 0 // arc4 is a ugly state machine, KSAE can only be set once per session
- ctx->key_length = key_len;
-
- memcpy ((u8 *) (ctx->buf), in_key, key_len);
-#endif
-
- return 0;
-}
-
-/*! \fn static void _deu_arc4_ecb(void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
- \ingroup IFX_ARC4_FUNCTIONS
- \brief sets ARC4 hardware to ECB mode
- \param ctx crypto algo context
- \param dst output bytestream
- \param src input bytestream
- \param iv initialization vector
- \param nbytes length of bytestream
- \param encdec 1 for encrypt; 0 for decrypt
- \param inplace not used
-*/
-static void _deu_arc4_ecb(void *ctx, uint8_t *dst, const uint8_t *src,
- uint8_t *iv, size_t nbytes, int encdec, int inplace)
-{
- _deu_arc4 (ctx, dst, src, NULL, nbytes, encdec, 0);
-}
-
-/*! \fn static void arc4_crypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
- \ingroup IFX_ARC4_FUNCTIONS
- \brief encrypt/decrypt ARC4_BLOCK_SIZE of data
- \param tfm linux crypto algo transform
- \param out output bytestream
- \param in input bytestream
-*/
-static void arc4_crypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
-{
- struct arc4_ctx *ctx = crypto_tfm_ctx(tfm);
-
- _deu_arc4 (ctx, out, in, NULL, ARC4_BLOCK_SIZE,
- CRYPTO_DIR_DECRYPT, CRYPTO_TFM_MODE_ECB);
-
-}
-
-/*
- * \brief ARC4 function mappings
-*/
-static struct crypto_alg ifxdeu_arc4_alg = {
- .cra_name = "arc4",
- .cra_driver_name = "ifxdeu-arc4",
- .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
- .cra_blocksize = ARC4_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct arc4_ctx),
- .cra_module = THIS_MODULE,
- .cra_list = LIST_HEAD_INIT(ifxdeu_arc4_alg.cra_list),
- .cra_u = {
- .cipher = {
- .cia_min_keysize = ARC4_MIN_KEY_SIZE,
- .cia_max_keysize = ARC4_MAX_KEY_SIZE,
- .cia_setkey = arc4_set_key,
- .cia_encrypt = arc4_crypt,
- .cia_decrypt = arc4_crypt,
- }
- }
-};
-
-/*! \fn static int ecb_arc4_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
- \ingroup IFX_ARC4_FUNCTIONS
- \brief ECB ARC4 encrypt using linux crypto blkcipher
- \param desc blkcipher descriptor
- \param dst output scatterlist
- \param src input scatterlist
- \param nbytes data size in bytes
-*/
-static int ecb_arc4_encrypt(struct blkcipher_desc *desc,
- struct scatterlist *dst, struct scatterlist *src,
- unsigned int nbytes)
-{
- struct arc4_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
- struct blkcipher_walk walk;
- int err;
-
- DPRINTF(1, "\n");
- blkcipher_walk_init(&walk, dst, src, nbytes);
- err = blkcipher_walk_virt(desc, &walk);
-
- while ((nbytes = walk.nbytes)) {
- _deu_arc4_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr,
- NULL, nbytes, CRYPTO_DIR_ENCRYPT, 0);
- nbytes &= ARC4_BLOCK_SIZE - 1;
- err = blkcipher_walk_done(desc, &walk, nbytes);
- }
-
- return err;
-}
-
-/*! \fn static int ecb_arc4_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
- \ingroup IFX_ARC4_FUNCTIONS
- \brief ECB ARC4 decrypt using linux crypto blkcipher
- \param desc blkcipher descriptor
- \param dst output scatterlist
- \param src input scatterlist
- \param nbytes data size in bytes
-*/
-static int ecb_arc4_decrypt(struct blkcipher_desc *desc,
- struct scatterlist *dst, struct scatterlist *src,
- unsigned int nbytes)
-{
- struct arc4_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
- struct blkcipher_walk walk;
- int err;
-
- DPRINTF(1, "\n");
- blkcipher_walk_init(&walk, dst, src, nbytes);
- err = blkcipher_walk_virt(desc, &walk);
-
- while ((nbytes = walk.nbytes)) {
- _deu_arc4_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr,
- NULL, nbytes, CRYPTO_DIR_DECRYPT, 0);
- nbytes &= ARC4_BLOCK_SIZE - 1;
- err = blkcipher_walk_done(desc, &walk, nbytes);
- }
-
- return err;
-}
-
-/*
- * \brief ARC4 function mappings
-*/
-static struct crypto_alg ifxdeu_ecb_arc4_alg = {
- .cra_name = "ecb(arc4)",
- .cra_driver_name = "ifxdeu-ecb(arc4)",
- .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
- .cra_blocksize = ARC4_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct arc4_ctx),
- .cra_type = &crypto_blkcipher_type,
- .cra_module = THIS_MODULE,
- .cra_list = LIST_HEAD_INIT(ifxdeu_ecb_arc4_alg.cra_list),
- .cra_u = {
- .blkcipher = {
- .min_keysize = ARC4_MIN_KEY_SIZE,
- .max_keysize = ARC4_MAX_KEY_SIZE,
- .setkey = arc4_set_key,
- .encrypt = ecb_arc4_encrypt,
- .decrypt = ecb_arc4_decrypt,
- }
- }
-};
-
-/*! \fn int __init ifxdeu_init_arc4(void)
- \ingroup IFX_ARC4_FUNCTIONS
- \brief initialize arc4 driver
-*/
-int __init ifxdeu_init_arc4(void)
-{
- int ret;
-
- if ((ret = crypto_register_alg(&ifxdeu_arc4_alg)))
- goto arc4_err;
-
- if ((ret = crypto_register_alg(&ifxdeu_ecb_arc4_alg)))
- goto ecb_arc4_err;
-
- arc4_chip_init ();
-
- CRTCL_SECT_INIT;
-
- printk (KERN_NOTICE "IFX DEU ARC4 initialized %s.\n", disable_deudma ? "" : " (DMA)");
- return ret;
-
-arc4_err:
- crypto_unregister_alg(&ifxdeu_arc4_alg);
- printk(KERN_ERR "IFX arc4 initialization failed!\n");
- return ret;
-ecb_arc4_err:
- crypto_unregister_alg(&ifxdeu_ecb_arc4_alg);
- printk (KERN_ERR "IFX ecb_arc4 initialization failed!\n");
- return ret;
-
-}
-
-/*! \fn void __exit ifxdeu_fini_arc4(void)
- \ingroup IFX_ARC4_FUNCTIONS
- \brief unregister arc4 driver
-*/
-void __exit ifxdeu_fini_arc4(void)
-{
- crypto_unregister_alg (&ifxdeu_arc4_alg);
- crypto_unregister_alg (&ifxdeu_ecb_arc4_alg);
-}
-
-#endif
+++ /dev/null
-#ifndef IFXMIPS_ARC4_H
-#define IFXMIPS_ARC4_H
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
- * Copyright (C) 2009 Mohammad Firdaus
- */
-
-/*!
- \defgroup IFX_DEU IFX_DEU_DRIVERS
- \ingroup API
- \brief ifx deu driver file
-*/
-
-/*!
- \defgroup IFX_DEU_DEFINITIONS IFX_DEU_DRIVERS
- \ingroup IFX_DEU
- \brief ifx deu definitions
-*/
-
-/*!
- \file ifxmips_arc4.h
- \brief ARC4 DEU header driver file
-*/
-
-
-
-#define ARC4_START IFX_ARC4_CON
-
-#ifdef CONFIG_CRYPTO_DEV_ARC4_AR9
-#include "ifxmips_deu_structs_ar9.h"
-#endif
-#ifdef CONFIG_CRYPTO_DEV_DMA_AR9
-#include "ifxmips_deu_structs_ar9.h"
-#endif
-
-#ifdef CONFIG_CRYPTO_DEV_ARC4_VR9
-#include "ifxmips_deu_structs_vr9.h"
-#endif
-#ifdef CONFIG_CRYPTO_DEV_DMA_VR9
-#include "ifxmips_deu_structs_vr9.h"
-#include <asm/ifx/irq.h>
-#endif
-
-#endif /* IFXMIPS_ARC4_H */
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
- * Copyright (C) 2009 Mohammad Firdaus
- */
-
-/*!
- \defgroup IFX_DEU IFX_DEU_DRIVERS
- \ingroup API
- \brief ifx deu driver
-*/
-
-/*!
- \file ifxmips_des.c
- \ingroup IFX_DEU
- \brief DES encryption DEU driver file
-*/
-
-/*!
- \defgroup IFX_DES_FUNCTIONS IFX_DES_FUNCTIONS
- \ingroup IFX_DEU
- \brief IFX DES Encryption functions
-*/
-
-/* Project Header Files */
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/crypto.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <asm/byteorder.h>
-#include <crypto/algapi.h>
-#include "ifxmips_deu.h"
-
-/* DMA specific header and variables */
-#ifdef CONFIG_CRYPTO_DEV_IFXMIPS_DMA
-#include "ifxmips_deu_dma.h"
-#include <asm/ifx/irq.h>
-#include <asm/ifx/ifx_dma_core.h>
-extern _ifx_deu_device ifx_deu[1];
-extern u32 *des_buff_in;
-extern u32 *des_buff_out;
-#ifndef CONFIG_CRYPTO_DEV_IFXMIPS_POLL_DMA
-#define CONFIG_CRYPTO_DEV_IFXMIPS_POLL_DMA
-#endif /* CONFIG_CRYPTO_DEV_IFXMIPS_POLL_DMA */
-#endif /* CONFIG_CRYPTO_DEV_IFXMIPS_DMA */
-
-spinlock_t des_lock;
-#define CRTCL_SECT_INIT spin_lock_init(&des_lock)
-#define CRTCL_SECT_START spin_lock_irqsave(&des_lock, flag)
-#define CRTCL_SECT_END spin_unlock_irqrestore(&des_lock, flag)
-
-/* Preprocessor declarations */
-#define DES_3DES_START IFX_DES_CON
-#define DES_KEY_SIZE 8
-#define DES_EXPKEY_WORDS 32
-#define DES_BLOCK_SIZE 8
-#define DES3_EDE_KEY_SIZE (3 * DES_KEY_SIZE)
-#define DES3_EDE_EXPKEY_WORDS (3 * DES_EXPKEY_WORDS)
-#define DES3_EDE_BLOCK_SIZE DES_BLOCK_SIZE
-
-/* Function Declaration to prevent warning messages */
-void des_chip_init (void);
-u32 endian_swap(u32 input);
-u32 input_swap(u32 input);
-int aes_memory_allocate(int value);
-int des_memory_allocate(int value);
-void memory_release(u32 *buffer);
-u32* memory_alignment(const u8 *arg, u32 *buff_alloc, int in_out, int nbytes);
-void aes_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);
-void des_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);
-
-#ifndef CONFIG_CRYPTO_DEV_IFXMIPS_DMA
-void ifx_deu_des (void *ctx_arg, u8 *out_arg, const u8 *in_arg,
- u8 *iv_arg, u32 nbytes, int encdec, int mode);
-#else
-void ifx_deu_des_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg,
- u8 *iv_arg, u32 nbytes, int encdec, int mode);
-#endif /* CONFIG_CRYPTO_DEV_IFXMIPS_DMA */
-
-struct des_ctx {
- int controlr_M;
- int key_length;
- u8 iv[DES_BLOCK_SIZE];
- u32 expkey[DES3_EDE_EXPKEY_WORDS];
-};
-
-extern int disable_deudma;
-
-/*! \fn int des_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int key_len)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief sets DES key
- * \param tfm linux crypto algo transform
- * \param key input key
- * \param key_len key length
-*/
-int des_setkey(struct crypto_tfm *tfm, const u8 *key,
- unsigned int key_len)
-{
- struct des_ctx *ctx = crypto_tfm_ctx(tfm);
-
- DPRINTF(0, "ctx @%p, key_len %d %d\n", ctx, key_len);
-
- ctx->controlr_M = 0; /* des */
- ctx->key_length = key_len;
-
- memcpy ((u8 *) (ctx->expkey), key, key_len);
-
- return 0;
-}
-
-#ifndef CONFIG_CRYPTO_DEV_IFXMIPS_DMA
-/*! \fn void ifx_deu_des(void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief main interface to DES hardware
- * \param ctx_arg crypto algo context
- * \param out_arg output bytestream
- * \param in_arg input bytestream
- * \param iv_arg initialization vector
- * \param nbytes length of bytestream
- * \param encdec 1 for encrypt; 0 for decrypt
- * \param mode operation mode such as ebc, cbc
-*/
-
-void ifx_deu_des (void *ctx_arg, u8 *out_arg, const u8 *in_arg,
- u8 *iv_arg, u32 nbytes, int encdec, int mode)
-#else
-/*! \fn void ifx_deu_des_core(void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief main interface to DES hardware
- * \param ctx_arg crypto algo context
- * \param out_arg output bytestream
- * \param in_arg input bytestream
- * \param iv_arg initialization vector
- * \param nbytes length of bytestream
- * \param encdec 1 for encrypt; 0 for decrypt
- * \param mode operation mode such as ebc, cbc
-*/
-
-void ifx_deu_des_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg,
- u8 *iv_arg, u32 nbytes, int encdec, int mode)
-#endif
-{
- volatile struct des_t *des = (struct des_t *) DES_3DES_START;
- struct des_ctx *dctx = ctx_arg;
- u32 *key = dctx->expkey;
- ulong flag;
-
-#ifndef CONFIG_CRYPTO_DEV_IFXMIPS_DMA
- int i = 0;
- int nblocks = 0;
-#else
- volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON;
- struct dma_device_info *dma_device = ifx_deu[0].dma_device;
- //deu_drv_priv_t *deu_priv = (deu_drv_priv_t *)dma_device->priv;
- int wlen = 0;
- u32 *outcopy = NULL;
- u32 *dword_mem_aligned_in = NULL;
-
-#ifdef CONFIG_CRYPTO_DEV_IFXMIPS_POLL_DMA
- u32 timeout = 0;
- u32 *out_dma = NULL;
-#endif
-
-#endif
-
- DPRINTF(0, "ctx @%p, mode %d, encdec %d\n", dctx, mode, encdec);
-
- CRTCL_SECT_START;
-
- des->controlr.E_D = !encdec; /* encryption */
- des->controlr.O = mode; /* 0 ECB, 1 CBC, 2 OFB, 3 CFB, 4 CTR */
- des->controlr.SM = 1; /* start after writing input register */
- des->controlr.DAU = 0; /* Disable Automatic Update of init vector */
- des->controlr.ARS = 1; /* Autostart Select - write to IHR */
-
- des->controlr.M = dctx->controlr_M;
- /* write keys */
- if (dctx->controlr_M == 0) {
- /* DES mode */
- des->K1HR = DEU_ENDIAN_SWAP(*((u32 *) key + 0));
- des->K1LR = DEU_ENDIAN_SWAP(*((u32 *) key + 1));
-#ifdef CRYPTO_DEBUG
- printk ("key1: %x\n", (*((u32 *) key + 0)));
- printk ("key2: %x\n", (*((u32 *) key + 1)));
-#endif
- } else {
- /* 3DES mode (EDE-x) */
- switch (dctx->key_length) {
- case 24:
- des->K3HR = DEU_ENDIAN_SWAP(*((u32 *) key + 4));
- des->K3LR = DEU_ENDIAN_SWAP(*((u32 *) key + 5));
- /* no break; */
- case 16:
- des->K2HR = DEU_ENDIAN_SWAP(*((u32 *) key + 2));
- des->K2LR = DEU_ENDIAN_SWAP(*((u32 *) key + 3));
- /* no break; */
- case 8:
- des->K1HR = DEU_ENDIAN_SWAP(*((u32 *) key + 0));
- des->K1LR = DEU_ENDIAN_SWAP(*((u32 *) key + 1));
- break;
- default:
- CRTCL_SECT_END;
- return;
- }
- }
-
- /* write init vector (not required for ECB mode) */
- if (mode > 0) {
- des->IVHR = DEU_ENDIAN_SWAP(*(u32 *) iv_arg);
- des->IVLR = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1));
- }
-
-#ifndef CONFIG_CRYPTO_DEV_IFXMIPS_DMA
- nblocks = nbytes / 4;
-
- for (i = 0; i < nblocks; i += 2) {
- /* wait for busy bit to clear */
-
- /*--- Workaround ----------------------------------------------------
- do a dummy read to the busy flag because it is not raised early
- enough in CFB/OFB 3DES modes */
-#ifdef CRYPTO_DEBUG
- printk ("ihr: %x\n", (*((u32 *) in_arg + i)));
- printk ("ilr: %x\n", (*((u32 *) in_arg + 1 + i)));
-#endif
- des->IHR = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + i));
- des->ILR = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + 1 + i)); /* start crypto */
-
- while (des->controlr.BUS) {
- /* this will not take long */
- }
-
- *((u32 *) out_arg + 0 + i) = des->OHR;
- *((u32 *) out_arg + 1 + i) = des->OLR;
-
-#ifdef CRYPTO_DEBUG
- printk ("ohr: %x\n", (*((u32 *) out_arg + i)));
- printk ("olr: %x\n", (*((u32 *) out_arg + 1 + i)));
-#endif
- }
-
-#else /* dma mode */
-
- /* Prepare Rx buf length used in dma psuedo interrupt */
- //deu_priv->deu_rx_buf = out_arg;
- //deu_priv->deu_rx_len = nbytes;
-
- /* memory alignment issue */
- dword_mem_aligned_in = (u32 *) DEU_DWORD_REORDERING(in_arg, des_buff_in, BUFFER_IN, nbytes);
-
- dma->controlr.ALGO = 0; //DES
- des->controlr.DAU = 0;
- dma->controlr.BS = 0;
- dma->controlr.EN = 1;
-
- while (des->controlr.BUS) {
- // wait for AES to be ready
- };
-
- wlen = dma_device_write (dma_device, (u8 *) dword_mem_aligned_in, nbytes, NULL);
- if (wlen != nbytes) {
- dma->controlr.EN = 0;
- CRTCL_SECT_END;
- printk (KERN_ERR "[%s %s %d]: dma_device_write fail!\n", __FILE__, __func__, __LINE__);
- return; // -EINVAL;
- }
-
- WAIT_DES_DMA_READY();
-
-#ifdef CONFIG_CRYPTO_DEV_IFXMIPS_POLL_DMA
-
- outcopy = (u32 *) DEU_DWORD_REORDERING(out_arg, des_buff_out, BUFFER_OUT, nbytes);
-
- // polling DMA rx channel
- while ((dma_device_read (dma_device, (u8 **) &out_dma, NULL)) == 0) {
- timeout++;
-
- if (timeout >= 333000) {
- dma->controlr.EN = 0;
- CRTCL_SECT_END;
- printk (KERN_ERR "[%s %s %d]: timeout!!\n", __FILE__, __func__, __LINE__);
- return; // -EINVAL;
- }
- }
-
- WAIT_DES_DMA_READY();
-
- DES_MEMORY_COPY(outcopy, out_dma, out_arg, nbytes);
-
-#else
-
- CRTCL_SECT_END; /* Sleep and wait for Rx finished */
- DEU_WAIT_EVENT(deu_priv->deu_thread_wait, DEU_EVENT, deu_priv->deu_event_flags);
- CRTCL_SECT_START;
-
-#endif
-
-#endif /* dma mode */
-
- if (mode > 0) {
- *(u32 *) iv_arg = DEU_ENDIAN_SWAP(des->IVHR);
- *((u32 *) iv_arg + 1) = DEU_ENDIAN_SWAP(des->IVLR);
- };
-
- CRTCL_SECT_END;
-}
-
-//definitions from linux/include/crypto.h:
-//#define CRYPTO_TFM_MODE_ECB 0x00000001
-//#define CRYPTO_TFM_MODE_CBC 0x00000002
-//#define CRYPTO_TFM_MODE_CFB 0x00000004
-//#define CRYPTO_TFM_MODE_CTR 0x00000008
-//#define CRYPTO_TFM_MODE_OFB 0x00000010 // not even defined
-//but hardware definition: 0 ECB 1 CBC 2 OFB 3 CFB 4 CTR
-
-/*! \fn void ifx_deu_des(void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief main interface to DES hardware
- * \param ctx_arg crypto algo context
- * \param out_arg output bytestream
- * \param in_arg input bytestream
- * \param iv_arg initialization vector
- * \param nbytes length of bytestream
- * \param encdec 1 for encrypt; 0 for decrypt
- * \param mode operation mode such as ebc, cbc
-*/
-
-#ifdef CONFIG_CRYPTO_DEV_IFXMIPS_DMA
-void ifx_deu_des (void *ctx_arg, u8 *out_arg, const u8 *in_arg,
- u8 *iv_arg, u32 nbytes, int encdec, int mode)
-{
- u32 remain = nbytes;
- u32 inc;
-
- DPRINTF(0, "\n");
-
- while (remain > 0)
- {
- if (remain >= DEU_MAX_PACKET_SIZE)
- {
- inc = DEU_MAX_PACKET_SIZE;
- }
- else
- {
- inc = remain;
- }
-
- remain -= inc;
-
- ifx_deu_des_core(ctx_arg, out_arg, in_arg, iv_arg, inc, encdec, mode);
-
- out_arg += inc;
- in_arg += inc;
- }
-}
-#endif
-
-
-/*! \fn void ifx_deu_des_ecb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief sets DES hardware to ECB mode
- * \param ctx crypto algo context
- * \param dst output bytestream
- * \param src input bytestream
- * \param iv initialization vector
- * \param nbytes length of bytestream
- * \param encdec 1 for encrypt; 0 for decrypt
- * \param inplace not used
-*/
-
-void ifx_deu_des_ecb (void *ctx, uint8_t *dst, const uint8_t *src,
- uint8_t *iv, size_t nbytes, int encdec, int inplace)
-{
- DPRINTF(0, "ctx @%p\n", ctx);
- ifx_deu_des (ctx, dst, src, NULL, nbytes, encdec, 0);
-}
-
-/*! \fn void ifx_deu_des_cbc (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief sets DES hardware to CBC mode
- * \param ctx crypto algo context
- * \param dst output bytestream
- * \param src input bytestream
- * \param iv initialization vector
- * \param nbytes length of bytestream
- * \param encdec 1 for encrypt; 0 for decrypt
- * \param inplace not used
-*/
-void ifx_deu_des_cbc (void *ctx, uint8_t *dst, const uint8_t *src,
- uint8_t *iv, size_t nbytes, int encdec, int inplace)
-{
- DPRINTF(0, "ctx @%p\n", ctx);
- ifx_deu_des (ctx, dst, src, iv, nbytes, encdec, 1);
-}
-
-/*! \fn void ifx_deu_des_ofb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief sets DES hardware to OFB mode
- * \param ctx crypto algo context
- * \param dst output bytestream
- * \param src input bytestream
- * \param iv initialization vector
- * \param nbytes length of bytestream
- * \param encdec 1 for encrypt; 0 for decrypt
- * \param inplace not used
-*/
-void ifx_deu_des_ofb (void *ctx, uint8_t *dst, const uint8_t *src,
- uint8_t *iv, size_t nbytes, int encdec, int inplace)
-{
- DPRINTF(0, "ctx @%p\n", ctx);
- ifx_deu_des (ctx, dst, src, iv, nbytes, encdec, 2);
-}
-
-/*! \fn void ifx_deu_des_cfb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
- \ingroup IFX_DES_FUNCTIONS
- \brief sets DES hardware to CFB mode
- \param ctx crypto algo context
- \param dst output bytestream
- \param src input bytestream
- \param iv initialization vector
- \param nbytes length of bytestream
- \param encdec 1 for encrypt; 0 for decrypt
- \param inplace not used
-*/
-void ifx_deu_des_cfb (void *ctx, uint8_t *dst, const uint8_t *src,
- uint8_t *iv, size_t nbytes, int encdec, int inplace)
-{
- DPRINTF(0, "ctx @%p\n", ctx);
- ifx_deu_des (ctx, dst, src, iv, nbytes, encdec, 3);
-}
-
-/*! \fn void ifx_deu_des_ctr (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief sets DES hardware to CTR mode
- * \param ctx crypto algo context
- * \param dst output bytestream
- * \param src input bytestream
- * \param iv initialization vector
- * \param nbytes length of bytestream
- * \param encdec 1 for encrypt; 0 for decrypt
- * \param inplace not used
-*/
-void ifx_deu_des_ctr (void *ctx, uint8_t *dst, const uint8_t *src,
- uint8_t *iv, size_t nbytes, int encdec, int inplace)
-{
- DPRINTF(0, "ctx @%p\n", ctx);
- ifx_deu_des (ctx, dst, src, iv, nbytes, encdec, 4);
-}
-
-/*! \fn void des_encrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief encrypt DES_BLOCK_SIZE of data
- * \param tfm linux crypto algo transform
- * \param out output bytestream
- * \param in input bytestream
-*/
-void des_encrypt (struct crypto_tfm *tfm, uint8_t * out, const uint8_t * in)
-{
- struct des_ctx *ctx = crypto_tfm_ctx(tfm);
- DPRINTF(0, "ctx @%p\n", ctx);
- ifx_deu_des (ctx, out, in, NULL, DES_BLOCK_SIZE, CRYPTO_DIR_ENCRYPT, 0);
-}
-
-/*! \fn void des_decrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief encrypt DES_BLOCK_SIZE of data
- * \param tfm linux crypto algo transform
- * \param out output bytestream
- * \param in input bytestream
-*/
-void des_decrypt (struct crypto_tfm *tfm, uint8_t * out, const uint8_t * in)
-{
- struct des_ctx *ctx = crypto_tfm_ctx(tfm);
- DPRINTF(0, "ctx @%p\n", ctx);
- ifx_deu_des (ctx, out, in, NULL, DES_BLOCK_SIZE, CRYPTO_DIR_DECRYPT, 0);
-}
-
-/*
- * \brief RFC2451:
- *
- * For DES-EDE3, there is no known need to reject weak or
- * complementation keys. Any weakness is obviated by the use of
- * multiple keys.
- *
- * However, if the first two or last two independent 64-bit keys are
- * equal (k1 == k2 or k2 == k3), then the DES3 operation is simply the
- * same as DES. Implementers MUST reject keys that exhibit this
- * property.
- *
- */
-
-/*! \fn int des3_ede_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief sets 3DES key
- * \param tfm linux crypto algo transform
- * \param key input key
- * \param keylen key length
-*/
-int des3_ede_setkey(struct crypto_tfm *tfm, const u8 *key,
- unsigned int key_len)
-{
- struct des_ctx *ctx = crypto_tfm_ctx(tfm);
-
- DPRINTF(0, "ctx @%p, key_len %d\n", ctx, key_len);
-
- ctx->controlr_M = key_len / 8 + 1; // 3DES EDE1 / EDE2 / EDE3 Mode
- ctx->key_length = key_len;
-
- memcpy ((u8 *) (ctx->expkey), key, key_len);
-
- return 0;
-}
-
-/*
- * \brief DES function mappings
-*/
-struct crypto_alg ifxdeu_des_alg = {
- .cra_name = "des",
- .cra_driver_name = "ifxdeu-des",
- .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
- .cra_blocksize = DES_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct des_ctx),
- .cra_module = THIS_MODULE,
- .cra_alignmask = 3,
- .cra_list = LIST_HEAD_INIT(ifxdeu_des_alg.cra_list),
- .cra_u = { .cipher = {
- .cia_min_keysize = DES_KEY_SIZE,
- .cia_max_keysize = DES_KEY_SIZE,
- .cia_setkey = des_setkey,
- .cia_encrypt = des_encrypt,
- .cia_decrypt = des_decrypt } }
-};
-
-/*
- * \brief DES function mappings
-*/
-struct crypto_alg ifxdeu_des3_ede_alg = {
- .cra_name = "des3_ede",
- .cra_driver_name = "ifxdeu-des3_ede",
- .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
- .cra_blocksize = DES_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct des_ctx),
- .cra_module = THIS_MODULE,
- .cra_alignmask = 3,
- .cra_list = LIST_HEAD_INIT(ifxdeu_des3_ede_alg.cra_list),
- .cra_u = { .cipher = {
- .cia_min_keysize = DES_KEY_SIZE,
- .cia_max_keysize = DES_KEY_SIZE,
- .cia_setkey = des3_ede_setkey,
- .cia_encrypt = des_encrypt,
- .cia_decrypt = des_decrypt } }
-};
-
-/*! \fn int ecb_des_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief ECB DES encrypt using linux crypto blkcipher
- * \param desc blkcipher descriptor
- * \param dst output scatterlist
- * \param src input scatterlist
- * \param nbytes data size in bytes
-*/
-int ecb_des_encrypt(struct blkcipher_desc *desc,
- struct scatterlist *dst, struct scatterlist *src,
- unsigned int nbytes)
-{
- struct des_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
- struct blkcipher_walk walk;
- int err;
-
- DPRINTF(0, "ctx @%p\n", ctx);
-
- blkcipher_walk_init(&walk, dst, src, nbytes);
- err = blkcipher_walk_virt(desc, &walk);
-
- while ((nbytes = walk.nbytes)) {
- nbytes -= (nbytes % DES_BLOCK_SIZE);
- ifx_deu_des_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr,
- NULL, nbytes, CRYPTO_DIR_ENCRYPT, 0);
- nbytes &= DES_BLOCK_SIZE - 1;
- err = blkcipher_walk_done(desc, &walk, nbytes);
- }
-
- return err;
-}
-
-/*! \fn int ecb_des_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief ECB DES decrypt using linux crypto blkcipher
- * \param desc blkcipher descriptor
- * \param dst output scatterlist
- * \param src input scatterlist
- * \param nbytes data size in bytes
- * \return err
-*/
-int ecb_des_decrypt(struct blkcipher_desc *desc,
- struct scatterlist *dst, struct scatterlist *src,
- unsigned int nbytes)
-{
- struct des_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
- struct blkcipher_walk walk;
- int err;
-
- DPRINTF(0, "ctx @%p\n", ctx);
-
- blkcipher_walk_init(&walk, dst, src, nbytes);
- err = blkcipher_walk_virt(desc, &walk);
-
- while ((nbytes = walk.nbytes)) {
- nbytes -= (nbytes % DES_BLOCK_SIZE);
- ifx_deu_des_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr,
- NULL, nbytes, CRYPTO_DIR_DECRYPT, 0);
- nbytes &= DES_BLOCK_SIZE - 1;
- err = blkcipher_walk_done(desc, &walk, nbytes);
- }
-
- return err;
-}
-
-/*
- * \brief DES function mappings
-*/
-struct crypto_alg ifxdeu_ecb_des_alg = {
- .cra_name = "ecb(des)",
- .cra_driver_name = "ifxdeu-ecb(des)",
- .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
- .cra_blocksize = DES_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct des_ctx),
- .cra_type = &crypto_blkcipher_type,
- .cra_module = THIS_MODULE,
- .cra_list = LIST_HEAD_INIT(ifxdeu_ecb_des_alg.cra_list),
- .cra_u = {
- .blkcipher = {
- .min_keysize = DES_KEY_SIZE,
- .max_keysize = DES_KEY_SIZE,
- .setkey = des_setkey,
- .encrypt = ecb_des_encrypt,
- .decrypt = ecb_des_decrypt,
- }
- }
-};
-
-/*
- * \brief DES function mappings
-*/
-struct crypto_alg ifxdeu_ecb_des3_ede_alg = {
- .cra_name = "ecb(des3_ede)",
- .cra_driver_name = "ifxdeu-ecb(des3_ede)",
- .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct des_ctx),
- .cra_type = &crypto_blkcipher_type,
- .cra_module = THIS_MODULE,
- .cra_list = LIST_HEAD_INIT(ifxdeu_ecb_des3_ede_alg.cra_list),
- .cra_u = {
- .blkcipher = {
- .min_keysize = DES3_EDE_KEY_SIZE,
- .max_keysize = DES3_EDE_KEY_SIZE,
- .setkey = des3_ede_setkey,
- .encrypt = ecb_des_encrypt,
- .decrypt = ecb_des_decrypt,
- }
- }
-};
-
-/*! \fn int cbc_des_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief CBC DES encrypt using linux crypto blkcipher
- * \param desc blkcipher descriptor
- * \param dst output scatterlist
- * \param src input scatterlist
- * \param nbytes data size in bytes
- * \return err
-*/
-int cbc_des_encrypt(struct blkcipher_desc *desc,
- struct scatterlist *dst, struct scatterlist *src,
- unsigned int nbytes)
-{
- struct des_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
- struct blkcipher_walk walk;
- int err;
-
- DPRINTF(0, "ctx @%p\n", ctx);
-
- blkcipher_walk_init(&walk, dst, src, nbytes);
- err = blkcipher_walk_virt(desc, &walk);
-
- while ((nbytes = walk.nbytes)) {
- u8 *iv = walk.iv;
- //printk("iv = %08x\n", *(u32 *)iv);
- nbytes -= (nbytes % DES_BLOCK_SIZE);
- ifx_deu_des_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr,
- iv, nbytes, CRYPTO_DIR_ENCRYPT, 0);
- nbytes &= DES_BLOCK_SIZE - 1;
- err = blkcipher_walk_done(desc, &walk, nbytes);
- }
-
- return err;
-}
-
-/*! \fn int cbc_des_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief CBC DES decrypt using linux crypto blkcipher
- * \param desc blkcipher descriptor
- * \param dst output scatterlist
- * \param src input scatterlist
- * \param nbytes data size in bytes
- * \return err
-*/
-int cbc_des_decrypt(struct blkcipher_desc *desc,
- struct scatterlist *dst, struct scatterlist *src,
- unsigned int nbytes)
-{
- struct des_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
- struct blkcipher_walk walk;
- int err;
-
- DPRINTF(0, "ctx @%p\n", ctx);
-
- blkcipher_walk_init(&walk, dst, src, nbytes);
- err = blkcipher_walk_virt(desc, &walk);
-
- while ((nbytes = walk.nbytes)) {
- u8 *iv = walk.iv;
- //printk("iv = %08x\n", *(u32 *)iv);
- nbytes -= (nbytes % DES_BLOCK_SIZE);
- ifx_deu_des_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr,
- iv, nbytes, CRYPTO_DIR_DECRYPT, 0);
- nbytes &= DES_BLOCK_SIZE - 1;
- err = blkcipher_walk_done(desc, &walk, nbytes);
- }
-
- return err;
-}
-
-/*
- * \brief DES function mappings
-*/
-struct crypto_alg ifxdeu_cbc_des_alg = {
- .cra_name = "cbc(des)",
- .cra_driver_name = "ifxdeu-cbc(des)",
- .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
- .cra_blocksize = DES_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct des_ctx),
- .cra_type = &crypto_blkcipher_type,
- .cra_module = THIS_MODULE,
- .cra_list = LIST_HEAD_INIT(ifxdeu_cbc_des_alg.cra_list),
- .cra_u = {
- .blkcipher = {
- .min_keysize = DES_KEY_SIZE,
- .max_keysize = DES_KEY_SIZE,
- .ivsize = DES_BLOCK_SIZE,
- .setkey = des_setkey,
- .encrypt = cbc_des_encrypt,
- .decrypt = cbc_des_decrypt,
- }
- }
-};
-
-/*
- * \brief DES function mappings
-*/
-struct crypto_alg ifxdeu_cbc_des3_ede_alg = {
- .cra_name = "cbc(des3_ede)",
- .cra_driver_name = "ifxdeu-cbc(des3_ede)",
- .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct des_ctx),
- .cra_type = &crypto_blkcipher_type,
- .cra_module = THIS_MODULE,
- .cra_list = LIST_HEAD_INIT(ifxdeu_cbc_des3_ede_alg.cra_list),
- .cra_u = {
- .blkcipher = {
- .min_keysize = DES3_EDE_KEY_SIZE,
- .max_keysize = DES3_EDE_KEY_SIZE,
- .ivsize = DES_BLOCK_SIZE,
- .setkey = des3_ede_setkey,
- .encrypt = cbc_des_encrypt,
- .decrypt = cbc_des_decrypt,
- }
- }
-};
-
-/*! \fn int __init ifxdeu_init_des (void)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief initialize des driver
-*/
-int __init ifxdeu_init_des (void)
-{
- int ret = 0;
-
- ret = crypto_register_alg(&ifxdeu_des_alg);
- if (ret < 0)
- goto des_err;
-
- ret = crypto_register_alg(&ifxdeu_ecb_des_alg);
- if (ret < 0)
- goto ecb_des_err;
-
- ret = crypto_register_alg(&ifxdeu_cbc_des_alg);
- if (ret < 0)
- goto cbc_des_err;
-
- ret = crypto_register_alg(&ifxdeu_des3_ede_alg);
- if (ret < 0)
- goto des3_ede_err;
-
- ret = crypto_register_alg(&ifxdeu_ecb_des3_ede_alg);
- if (ret < 0)
- goto ecb_des3_ede_err;
-
- ret = crypto_register_alg(&ifxdeu_cbc_des3_ede_alg);
- if (ret < 0)
- goto cbc_des3_ede_err;
-
- des_chip_init();
-
- CRTCL_SECT_INIT;
-
-#ifdef CONFIG_CRYPTO_DEV_IFXMIPS_DMA
- if (ALLOCATE_MEMORY(BUFFER_IN, DES_ALGO) < 0) {
- printk(KERN_ERR "[%s %s %d]: malloc memory fail!\n", __FILE__, __func__, __LINE__);
- goto cbc_des3_ede_err;
- }
- if (ALLOCATE_MEMORY(BUFFER_OUT, DES_ALGO) < 0) {
- printk(KERN_ERR "[%s %s %d]: malloc memory fail!\n", __FILE__, __func__, __LINE__);
- goto cbc_des3_ede_err;
- }
-#endif
-
- printk (KERN_NOTICE "IFX DEU DES initialized %s.\n", disable_deudma ? "" : " (DMA)");
- return ret;
-
-des_err:
- crypto_unregister_alg(&ifxdeu_des_alg);
- printk(KERN_ERR "IFX des initialization failed!\n");
- return ret;
-ecb_des_err:
- crypto_unregister_alg(&ifxdeu_ecb_des_alg);
- printk (KERN_ERR "IFX ecb_des initialization failed!\n");
- return ret;
-cbc_des_err:
- crypto_unregister_alg(&ifxdeu_cbc_des_alg);
- printk (KERN_ERR "IFX cbc_des initialization failed!\n");
- return ret;
-des3_ede_err:
- crypto_unregister_alg(&ifxdeu_des3_ede_alg);
- printk(KERN_ERR "IFX des3_ede initialization failed!\n");
- return ret;
-ecb_des3_ede_err:
- crypto_unregister_alg(&ifxdeu_ecb_des3_ede_alg);
- printk (KERN_ERR "IFX ecb_des3_ede initialization failed!\n");
- return ret;
-cbc_des3_ede_err:
- crypto_unregister_alg(&ifxdeu_cbc_des3_ede_alg);
- printk (KERN_ERR "IFX cbc_des3_ede initialization failed!\n");
- return ret;
-}
-
-/*! \fn void __exit ifxdeu_fini_des (void)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief unregister des driver
-*/
-void __exit ifxdeu_fini_des (void)
-{
- crypto_unregister_alg (&ifxdeu_des_alg);
- crypto_unregister_alg (&ifxdeu_ecb_des_alg);
- crypto_unregister_alg (&ifxdeu_cbc_des_alg);
- crypto_unregister_alg (&ifxdeu_des3_ede_alg);
- crypto_unregister_alg (&ifxdeu_ecb_des3_ede_alg);
- crypto_unregister_alg (&ifxdeu_cbc_des3_ede_alg);
-
-#ifdef CONFIG_CRYPTO_DEV_IFXMIPS_DMA
- FREE_MEMORY(des_buff_in);
- FREE_MEMORY(des_buff_out);
-#endif /* CONFIG_CRYPTO_DEV_IFXMIPS_DMA_DANUBE */
-}
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
- * Copyright (C) 2009 Mohammad Firdaus
- */
-
-/*!
- \defgroup IFX_DEU IFX_DEU_DRIVERS
- \ingroup API
- \brief ifx deu driver module
-*/
-
-/*!
- \file ifxmips_deu.c
- \ingroup IFX_DEU
- \brief main deu driver file
-*/
-
-/*!
- \defgroup IFX_DEU_FUNCTIONS IFX_DEU_FUNCTIONS
- \ingroup IFX_DEU
- \brief IFX DEU functions
-*/
-
-/* Project header */
-#include <linux/version.h>
-#if defined(CONFIG_MODVERSIONS)
-#define MODVERSIONS
-#include <linux/modversions.h>
-#endif
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/crypto.h>
-#include <linux/proc_fs.h>
-#include <linux/fs.h> /* Stuff about file systems that we need */
-#include <asm/byteorder.h>
-#include <ifxmips_pmu.h>
-#include "ifxmips_deu.h"
-
-#ifdef CONFIG_CRYPTO_DEV_IFXMIPS_DMA
-int disable_deudma = 0;
-#else
-int disable_deudma = 1;
-#endif /* CONFIG_CRYPTO_DEV_IFXMIPS_DMA */
-
-#ifdef CRYPTO_DEBUG
-char deu_debug_level = 3;
-#endif
-
-/*! \fn static int __init deu_init (void)
- * \ingroup IFX_DEU_FUNCTIONS
- * \brief link all modules that have been selected in kernel config for ifx hw crypto support
- * \return ret
-*/
-static int __init deu_init (void)
-{
- int ret = -ENOSYS;
- u32 config;
-
- volatile struct clc_controlr_t *clc = (struct clc_controlr_t *) IFX_DEU_CLK;
-
- ifxmips_pmu_enable(1<<20);
-
- printk(KERN_INFO "Lantiq crypto hardware driver version %s\n", IFX_DEU_DRV_VERSION);
-
- chip_version();
-
- clc->FSOE = 0;
- clc->SBWE = 0;
- clc->SPEN = 0;
- clc->SBWE = 0;
- clc->DISS = 0;
- clc->DISR = 0;
-
- config = *IFX_DEU_ID;
-
-#ifdef CONFIG_CRYPTO_DEV_IFXMIPS_DMA
- deu_dma_init ();
-#endif
-
-#if defined(CONFIG_CRYPTO_DEV_IFXMIPS_DES)
- if(config & IFX_DEU_ID_DES) {
- if ((ret = ifxdeu_init_des ())) {
- printk (KERN_ERR "IFX DES initialization failed!\n");
- }
- } else {
- printk (KERN_ERR "IFX DES not supported!\n");
- }
-#endif
-#if defined(CONFIG_CRYPTO_DEV_IFXMIPS_AES)
- if(config & IFX_DEU_ID_AES) {
- if ((ret = ifxdeu_init_aes ())) {
- printk (KERN_ERR "IFX AES initialization failed!\n");
- }
- } else {
- printk (KERN_ERR "IFX AES not supported!\n");
- }
-#endif
-#if defined(CONFIG_CRYPTO_DEV_IFXMIPS_ARC4)
- if ((ret = ifxdeu_init_arc4 ())) {
- printk (KERN_ERR "IFX ARC4 initialization failed!\n");
- }
-#endif
-#if defined(CONFIG_CRYPTO_DEV_IFXMIPS_SHA1)
- if(config & IFX_DEU_ID_HASH) {
- if ((ret = ifxdeu_init_sha1 ())) {
- printk (KERN_ERR "IFX SHA1 initialization failed!\n");
- }
- } else {
- printk (KERN_ERR "IFX SHA1 not supported!\n");
- }
-#endif
-#if defined(CONFIG_CRYPTO_DEV_IFXMIPS_MD5)
- if(config & IFX_DEU_ID_HASH) {
- if ((ret = ifxdeu_init_md5 ())) {
- printk (KERN_ERR "IFX MD5 initialization failed!\n");
- }
- } else {
- printk (KERN_ERR "IFX MD5 not supported!\n");
- }
-#endif
-#if defined(CONFIG_CRYPTO_DEV_IFXMIPS_SHA1_HMAC)
- if ((ret = ifxdeu_init_sha1_hmac ())) {
- printk (KERN_ERR "IFX SHA1_HMAC initialization failed!\n");
- }
-#endif
-#if defined(CONFIG_CRYPTO_DEV_IFXMIPS_MD5_HMAC)
- if ((ret = ifxdeu_init_md5_hmac ())) {
- printk (KERN_ERR "IFX MD5_HMAC initialization failed!\n");
- }
-#endif
- return ret;
-}
-
-/*! \fn static void __exit deu_fini (void)
- * \ingroup IFX_DEU_FUNCTIONS
- * \brief remove the loaded crypto algorithms
-*/
-static void __exit deu_fini (void)
-{
- #if defined(CONFIG_CRYPTO_DEV_IFXMIPS_DES)
- ifxdeu_fini_des ();
- #endif
- #if defined(CONFIG_CRYPTO_DEV_IFXMIPS_AES)
- ifxdeu_fini_aes ();
- #endif
- #if defined(CONFIG_CRYPTO_DEV_IFXMIPS_ARC4)
- ifxdeu_fini_arc4 ();
- #endif
- #if defined(CONFIG_CRYPTO_DEV_IFXMIPS_SHA1)
- ifxdeu_fini_sha1 ();
- #endif
- #if defined(CONFIG_CRYPTO_DEV_IFXMIPS_MD5)
- ifxdeu_fini_md5 ();
- #endif
- #if defined(CONFIG_CRYPTO_DEV_IFXMIPS_SHA1_HMAC)
- ifxdeu_fini_sha1_hmac ();
- #endif
- #if defined(CONFIG_CRYPTO_DEV_IFXMIPS_MD5_HMAC)
- ifxdeu_fini_md5_hmac ();
- #endif
- printk("DEU has exited successfully\n");
-
- #if defined(CONFIG_CRYPTO_DEV_IFXMIPS_DMA)
- ifxdeu_fini_dma();
- printk("DMA has deregistered successfully\n");
- #endif
-}
-
-module_init (deu_init);
-module_exit (deu_fini);
-
-MODULE_DESCRIPTION ("Infineon crypto engine support.");
-MODULE_LICENSE ("GPL");
-MODULE_AUTHOR ("Mohammad Firdaus");
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
- * Copyright (C) 2009 Mohammad Firdaus
- */
-
-/*!
- \defgroup IFX_DEU IFX_DEU_DRIVERS
- \ingroup API
- \brief ifx deu driver module
-*/
-
-/*!
- \file ifxmips_deu.h
- \brief main deu driver header file
-*/
-
-/*!
- \defgroup IFX_DEU_DEFINITIONS IFX_DEU_DEFINITIONS
- \ingroup IFX_DEU
- \brief ifx deu definitions
-*/
-
-
-#ifndef IFXMIPS_DEU_H
-#define IFXMIPS_DEU_H
-
-#define IFX_DEU_DRV_VERSION "1.0.1"
-
-#include "ifxmips_deu_danube.h"
-
-#define IFXDEU_ALIGNMENT 16
-
-#define PFX "ifxdeu: "
-
-#define IFXDEU_CRA_PRIORITY 300
-#define IFXDEU_COMPOSITE_PRIORITY 400
-
-
-#define IFX_DEU_BASE_ADDR (KSEG1 | 0x1E103100)
-#define IFX_DEU_CLK ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0000))
-#define IFX_DEU_ID ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0008))
-#define IFX_DES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0010))
-#define IFX_AES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050))
-#define IFX_HASH_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B0))
-#define IFX_ARC4_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0100))
-
-#define IFX_DEU_ID_REV 0x00001F
-#define IFX_DEU_ID_ID 0x00FF00
-#define IFX_DEU_ID_DMA 0x010000
-#define IFX_DEU_ID_HASH 0x020000
-#define IFX_DEU_ID_AES 0x040000
-#define IFX_DEU_ID_3DES 0x080000
-#define IFX_DEU_ID_DES 0x100000
-
-#define CRYPTO_DIR_ENCRYPT 1
-#define CRYPTO_DIR_DECRYPT 0
-
-#undef CRYPTO_DEBUG
-
-#ifdef CRYPTO_DEBUG
-extern char deu_debug_level;
-#define DPRINTF(level, format, args...) if (level < deu_debug_level) printk(KERN_INFO "[%s %s %d]: " format, __FILE__, __func__, __LINE__, ##args);
-#else
-#define DPRINTF(level, format, args...)
-#endif
-
-#define IFX_MPS (KSEG1 | 0x1F107000)
-
-#define IFX_MPS_CHIPID ((volatile u32*)(IFX_MPS + 0x0344))
-#define IFX_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & 0xF)
-#define IFX_MPS_CHIPID_VERSION_SET(value) (((value) & 0xF) << 28)
-#define IFX_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & 0xFFFF)
-#define IFX_MPS_CHIPID_PARTNUM_SET(value) (((value) & 0xFFFF) << 12)
-#define IFX_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & 0x7FF)
-#define IFX_MPS_CHIPID_MANID_SET(value) (((value) & 0x7FF) << 1)
-
-void chip_version(void);
-
-int __init ifxdeu_init_des (void);
-int __init ifxdeu_init_aes (void);
-int __init ifxdeu_init_arc4 (void);
-int __init ifxdeu_init_sha1 (void);
-int __init ifxdeu_init_md5 (void);
-int __init ifxdeu_init_sha1_hmac (void);
-int __init ifxdeu_init_md5_hmac (void);
-
-void __exit ifxdeu_fini_des (void);
-void __exit ifxdeu_fini_aes (void);
-void __exit ifxdeu_fini_arc4 (void);
-void __exit ifxdeu_fini_sha1 (void);
-void __exit ifxdeu_fini_md5 (void);
-void __exit ifxdeu_fini_sha1_hmac (void);
-void __exit ifxdeu_fini_md5_hmac (void);
-void __exit ifxdeu_fini_dma(void);
-
-int deu_dma_init (void);
-
-#define DEU_WAKELIST_INIT(queue) \
- init_waitqueue_head(&queue)
-
-#define DEU_WAIT_EVENT_TIMEOUT(queue, event, flags, timeout) \
- do { \
- wait_event_interruptible_timeout((queue), \
- test_bit((event), &(flags)), (timeout)); \
- clear_bit((event), &(flags)); \
- }while (0)
-
-
-#define DEU_WAKEUP_EVENT(queue, event, flags) \
- do { \
- set_bit((event), &(flags)); \
- wake_up_interruptible(&(queue)); \
- }while (0)
-
-#define DEU_WAIT_EVENT(queue, event, flags) \
- do { \
- wait_event_interruptible(queue, \
- test_bit((event), &(flags))); \
- clear_bit((event), &(flags)); \
- }while (0)
-
-typedef struct deu_drv_priv {
- wait_queue_head_t deu_thread_wait;
-#define DEU_EVENT 1
- volatile long deu_event_flags;
- u8 *deu_rx_buf;
- u32 deu_rx_len;
-}deu_drv_priv_t;
-
-#endif /* IFXMIPS_DEU_H */
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
- * Copyright (C) 2009 Mohammad Firdaus
- */
-
-/*!
- \defgroup IFX_DEU IFX_DEU_DRIVERS
- \ingroup API
- \brief deu driver module
-*/
-
-/*!
- \file ifxmips_deu_danube.c
- \ingroup IFX_DEU
- \brief board specific deu driver file for danube
-*/
-
-/*!
- \defgroup BOARD_SPECIFIC_FUNCTIONS IFX_BOARD_SPECIFIC_FUNCTIONS
- \ingroup IFX_DEU
- \brief board specific deu functions
-*/
-
-/* Project header files */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <asm/io.h> //dma_cache_inv
-#include "ifxmips_deu.h"
-
-#ifdef CONFIG_CRYPTO_DEV_IFXMIPS_DMA
-u32 *des_buff_in = NULL;
-u32 *des_buff_out = NULL;
-u32 *aes_buff_in = NULL;
-u32 *aes_buff_out = NULL;
-_ifx_deu_device ifx_deu[1];
-#endif
-
-/* Function Declerations */
-int aes_memory_allocate(int value);
-int des_memory_allocate(int value);
-void memory_release(u32 *addr);
-int aes_chip_init (void);
-void des_chip_init (void);
-int deu_dma_init (void);
-u32 endian_swap(u32 input);
-u32* memory_alignment(const u8 *arg, u32 *buff_alloc, int in_out, int nbytes);
-void dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);
-void __exit ifxdeu_fini_dma(void);
-
-#define DES_3DES_START IFX_DES_CON
-#define AES_START IFX_AES_CON
-
-/* Variables definition */
-int ifx_danube_pre_1_4;
-u8 *g_dma_page_ptr = NULL;
-u8 *g_dma_block = NULL;
-u8 *g_dma_block2 = NULL;
-
-
-/*! \fn int deu_dma_init (void)
- * \ingroup BOARD_SPECIFIC_FUNCTIONS
- * \brief Initialize DMA for DEU usage. DMA specific registers are
- * intialized here, including a pointer to the device, memory
- * space for the device and DEU-DMA descriptors
- * \return -1 if fail, otherwise return 0
-*/
-
-#ifdef CONFIG_CRYPTO_DEV_IFXMIPS_DMA
-int deu_dma_init (void)
-{
- struct dma_device_info *dma_device = NULL;
- int i = 0;
- volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON;
- struct dma_device_info *deu_dma_device_ptr;
-
- // get one free page and share between g_dma_block and g_dma_block2
- printk("PAGE_SIZE = %ld\n", PAGE_SIZE);
- g_dma_page_ptr = (u8 *)__get_free_page(GFP_KERNEL); // need 16-byte alignment memory block
- g_dma_block = g_dma_page_ptr; // need 16-byte alignment memory block
- g_dma_block2 = (u8 *)(g_dma_page_ptr + (PAGE_SIZE >> 1)); // need 16-byte alignment memory block
-
-
- deu_dma_device_ptr = dma_device_reserve ("DEU");
- if (!deu_dma_device_ptr) {
- printk ("DEU: reserve DMA fail!\n");
- return -1;
- }
- ifx_deu[0].dma_device = deu_dma_device_ptr;
- dma_device = deu_dma_device_ptr;
- //dma_device->priv = &deu_dma_priv;
- dma_device->buffer_alloc = &deu_dma_buffer_alloc;
- dma_device->buffer_free = &deu_dma_buffer_free;
- dma_device->intr_handler = &deu_dma_intr_handler;
- dma_device->tx_endianness_mode = IFX_DMA_ENDIAN_TYPE3;
- dma_device->rx_endianness_mode = IFX_DMA_ENDIAN_TYPE3;
- dma_device->port_num = 1;
- dma_device->tx_burst_len = 4;
- dma_device->max_rx_chan_num = 1;
- dma_device->max_tx_chan_num = 1;
- dma_device->port_packet_drop_enable = 0;
-
- for (i = 0; i < dma_device->max_rx_chan_num; i++) {
- dma_device->rx_chan[i]->packet_size = DEU_MAX_PACKET_SIZE;
- dma_device->rx_chan[i]->desc_len = 1;
- dma_device->rx_chan[i]->control = IFX_DMA_CH_ON;
- dma_device->rx_chan[i]->byte_offset = 0;
- dma_device->rx_chan[i]->chan_poll_enable = 1;
-
- }
-
- for (i = 0; i < dma_device->max_tx_chan_num; i++) {
- dma_device->tx_chan[i]->control = IFX_DMA_CH_ON;
- dma_device->tx_chan[i]->desc_len = 1;
- dma_device->tx_chan[i]->chan_poll_enable = 1;
- }
-
- dma_device->current_tx_chan = 0;
- dma_device->current_rx_chan = 0;
-
- dma_device_register (dma_device);
- for (i = 0; i < dma_device->max_rx_chan_num; i++) {
- (dma_device->rx_chan[i])->open (dma_device->rx_chan[i]);
- }
-
- dma->controlr.BS = 0;
- dma->controlr.RXCLS = 0;
- dma->controlr.EN = 1;
-
-
- *IFX_DMA_PS = 1;
-
- /* DANUBE PRE 1.4 SOFTWARE FIX */
- if (ifx_danube_pre_1_4)
- *IFX_DMA_PCTRL = 0x14;
- else
- *IFX_DMA_PCTRL = 0xF14;
-
- return 0;
-}
-
-/*! \fn u32 *memory_alignment(const u8 *arg, u32 *buffer_alloc, int in_buff, int nbytes)
- * \ingroup BOARD_SPECIFIC_FUNCTIONS
- * \brief A fix to align mis-aligned address for Danube version 1.3 chips which has
- * memory alignment issues.
- * \param arg Pointer to the input / output memory address
- * \param buffer_alloc A pointer to the buffer
- * \param in_buff Input (if == 1) or Output (if == 0) buffer
- * \param nbytes Number of bytes of data
- * \return returns arg: if address is aligned, buffer_alloc: if memory address is not aligned
-*/
-
-u32 *memory_alignment(const u8 *arg, u32 *buffer_alloc, int in_buff, int nbytes)
-{
- if (ifx_danube_pre_1_4) {
- /* for input buffer */
- if(in_buff) {
- if (((u32) arg) & 0xF) {
- memcpy(buffer_alloc, arg, nbytes);
- return (u32 *) buffer_alloc;
- }
- else
- return (u32 *) arg;
- }
- else {
- /* for output buffer */
- if (((u32) arg) & 0x3)
- return buffer_alloc;
- else
- return (u32 *) arg;
- }
- }
-
- return (u32 *) arg;
-}
-
-/*! \fn void aes_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes)
- * \ingroup BOARD_SPECIFIC_FUNCTIONS
- * \brief copy the DMA data to the memory address space for AES. The swaping of the 4 bytes
- * is done only for Danube version 1.3 (FIX). Otherwise, it is a direct memory copy
- * to out_arg pointer
- * \param outcopy Pointer to the address to store swapped copy
- * \param out_dma A pointer to the memory address that stores the DMA data
- * \param out_arg The pointer to the memory address that needs to be copied to
- * \param nbytes Number of bytes of data
-*/
-
-void aes_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes)
-{
- int i = 0;
- int x = 0;
-
- /* DANUBE PRE 1.4 SOFTWARE FIX */
- if (ifx_danube_pre_1_4) {
- for (i = 0; i < (nbytes / 4); i++) {
- x = i ^ 0x3;
- outcopy[i] = out_dma[x];
-
- }
- if (((u32) out_arg) & 0x3) {
- memcpy((u8 *)out_arg, outcopy, nbytes);
- }
- }
- else
- memcpy (out_arg, out_dma, nbytes);
-}
-
-/*! \fn void des_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes)
- * \ingroup BOARD_SPECIFIC_FUNCTIONS
- * \brief copy the DMA data to the memory address space for DES. The swaping of the 4 bytes
- * is done only for Danube version 1.3 (FIX). Otherwise, it is a direct memory copy
- * to out_arg pointer
- *
- * \param outcopy Pointer to the address to store swapped copy
- * \param out_dma A pointer to the memory address that stores the DMA data
- * \param out_arg The pointer to the memory address that needs to be copied to
- * \param nbytes Number of bytes of data
-*/
-
-void des_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes)
-{
- int i = 0;
- int x = 0;
-
- /* DANUBE PRE 1.4 SOFTWARE FIX */
- if (ifx_danube_pre_1_4) {
- for (i = 0; i < (nbytes / 4); i++) {
- x = i ^ 1;
- outcopy[i] = out_dma[x];
-
- }
- if (((u32) out_arg) & 0x3) {
- memcpy((u8 *)out_arg, outcopy, nbytes);
- }
- }
- else
- memcpy (out_arg, out_dma, nbytes);
-}
-
-/*! \fn int des_memory_allocate(int value)
- * \ingroup BOARD_SPECIFIC_FUNCTIONS
- * \brief allocates memory to the necessary memory input/output buffer location, used during
- * the DES algorithm DMA transfer (memory alignment issues)
- * \param value value determinds whether the calling of the function is for a input buffer
- * or for an output buffer memory allocation
-*/
-
-int des_memory_allocate(int value)
-{
- if (ifx_danube_pre_1_4) {
- if (value == BUFFER_IN) {
- des_buff_in = kmalloc(DEU_MAX_PACKET_SIZE, GFP_ATOMIC);
- if (!des_buff_in)
- return -1;
- else
- return 0;
- }
- else {
- des_buff_out = kmalloc(DEU_MAX_PACKET_SIZE, GFP_ATOMIC);
- if (!des_buff_out)
- return -1;
- else
- return 0;
- }
- }
-
- else
- return 0;
-}
-
-/*! \fn int aes_memory_allocate(int value)
- * \ingroup BOARD_SPECIFIC_FUNCTIONS
- * \brief allocates memory to the necessary memory input/output buffer location, used during
- * the AES algorithm DMA transfer (memory alignment issues)
- * \param value value determinds whether the calling of the function is for a input buffer
- * or for an output buffer memory allocation
-*/
-
-int aes_memory_allocate(int value)
-{
- if (ifx_danube_pre_1_4) {
- if (value == BUFFER_IN) {
- aes_buff_in = kmalloc(DEU_MAX_PACKET_SIZE, GFP_ATOMIC);
- if (!aes_buff_in)
- return -1;
- else
- return 0;
- }
- else {
- aes_buff_out = kmalloc(DEU_MAX_PACKET_SIZE, GFP_ATOMIC);
- if (!aes_buff_out)
- return -1;
- else
- return 0;
- }
- }
-
- else
- return 0;
-}
-
-/*! \fn void memory_release(u32 *addr)
- * \ingroup BOARD_SPECIFIC_FUNCTIONS
- * \brief frees previously allocated memory
- * \param addr memory address of the buffer that needs to be freed
-*/
-
-void memory_release(u32 *addr)
-{
- if (addr)
- kfree(addr);
- return;
-}
-
-/*! \fn __exit ifxdeu_fini_dma(void)
- * \ingroup BOARD_SPECIFIC_FUNCTIONS
- * \brief unregister dma devices after exit
-*/
-
-void __exit ifxdeu_fini_dma(void)
-{
- if (g_dma_page_ptr)
- free_page((u32) g_dma_page_ptr);
- dma_device_release(ifx_deu[0].dma_device);
- dma_device_unregister(ifx_deu[0].dma_device);
-
-}
-
-#endif /* CONFIG_CRYPTO_DEV_IFXMIPS_DMA */
-
-/*! \fn u32 endian_swap(u32 input)
- * \ingroup BOARD_SPECIFIC_FUNCTIONS
- * \brief function is not used
- * \param input Data input to be swapped
- * \return input
-*/
-
-u32 endian_swap(u32 input)
-{
- return input;
-}
-
-/*! \fn u32 input_swap(u32 input)
- * \ingroup BOARD_SPECIFIC_FUNCTIONS
- * \brief Swap the input data if the current chip is Danube version
- * 1.4 and do nothing to the data if the current chip is
- * Danube version 1.3
- * \param input data that needs to be swapped
- * \return input or swapped input
-*/
-
-u32 input_swap(u32 input)
-{
- if (!ifx_danube_pre_1_4) {
- u8 *ptr = (u8 *)&input;
- return ((ptr[3] << 24) | (ptr[2] << 16) | (ptr[1] << 8) | ptr[0]);
- }
- else
- return input;
-}
-
-
-
-/*! \fn void aes_chip_init (void)
- * \ingroup BOARD_SPECIFIC_FUNCTIONS
- * \brief initialize AES hardware
-*/
-
-int aes_chip_init (void)
-{
- volatile struct aes_t *aes = (struct aes_t *) AES_START;
-
-#ifndef CONFIG_CRYPTO_DEV_IFXMIPS_DMA
- //start crypto engine with write to ILR
- aes->controlr.SM = 1;
- aes->controlr.ARS = 1;
-#else
- aes->controlr.SM = 1;
- aes->controlr.ARS = 1; // 0 for dma
-#endif
- return 0;
-}
-
-/*! \fn void des_chip_init (void)
- * \ingroup BOARD_SPECIFIC_FUNCTIONS
- * \brief initialize DES hardware
-*/
-
-void des_chip_init (void)
-{
- volatile struct des_t *des = (struct des_t *) DES_3DES_START;
-
-#ifndef CONFIG_CRYPTO_DEV_IFXMIPS_DMA
- // start crypto engine with write to ILR
- des->controlr.SM = 1;
- des->controlr.ARS = 1;
-#else
- des->controlr.SM = 1;
- des->controlr.ARS = 1; // 0 for dma
-
-#endif
-}
-
-/*! \fn void chip_version (void)
- * \ingroup IFX_DES_FUNCTIONS
- * \brief To find the version of the chip by looking at the chip ID
- * \param ifx_danube_pre_1_4 (sets to 1 if Chip is Danube less than v1.4)
-*/
-
-void chip_version(void)
-{
- /* DANUBE PRE 1.4 SOFTWARE FIX */
- int chip_id = 0;
- chip_id = *IFX_MPS_CHIPID;
- chip_id >>= 28;
-
- if (chip_id >= 4) {
- ifx_danube_pre_1_4 = 0;
- printk("Danube Chip ver. 1.4 detected. \n");
- }
- else {
- ifx_danube_pre_1_4 = 1;
- printk("Danube Chip ver. 1.3 or below detected. \n");
- }
-
- return;
-}
-
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
- * Copyright (C) 2009 Mohammad Firdaus / Infineon Technologies
- */
-
-/*!
- \defgroup IFX_DEU IFX_DEU_DRIVERS
- \ingroup API
- \brief deu driver module
-*/
-
-/*!
- \file ifxmips_deu_danube.h
- \brief board specific driver header file for danube
-*/
-
-/*!
- \defgroup BOARD_SPECIFIC_FUNCTIONS IFX_BOARD_SPECIFIC_FUNCTIONS
- \ingroup IFX_DEU
- \brief board specific deu header files
-*/
-
-#ifndef IFXMIPS_DEU_DANUBE_H
-#define IFXMIPS_DEU_DANUBE_H
-
-#ifdef CONFIG_CRYPTO_DEV_DMA
-#define DEU_DWORD_REORDERING(ptr, buffer, in_out, bytes) memory_alignment(ptr, buffer, in_out, bytes)
-#define AES_MEMORY_COPY(outcopy, out_dma, out_arg, nbytes) aes_dma_memory_copy(outcopy, out_dma, out_arg, nbytes)
-#define DES_MEMORY_COPY(outcopy, out_dma, out_arg, nbytes) des_dma_memory_copy(outcopy, out_dma, out_arg, nbytes)
-#define BUFFER_IN 1
-#define BUFFER_OUT 0
-#define DELAY_PERIOD 9
-#define AES_ALGO 1
-#define DES_ALGO 0
-#define FREE_MEMORY(buff) memory_release(buff)
-#define ALLOCATE_MEMORY(val, type) type ? aes_memory_allocate(val) : des_memory_allocate(val)
-#endif /* CONFIG_CRYPTO_DEV_DMA */
-
-#define INPUT_ENDIAN_SWAP(input) input_swap(input)
-#define DEU_ENDIAN_SWAP(input) endian_swap(input)
-#define AES_DMA_MISC_CONFIG()
-
-#define WAIT_AES_DMA_READY() \
- do { \
- int i; \
- volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \
- volatile struct aes_t *aes = (volatile struct aes_t *) AES_START; \
- for (i = 0; i < 10; i++) \
- udelay(DELAY_PERIOD); \
- while (dma->controlr.BSY) {}; \
- while (aes->controlr.BUS) {}; \
- } while (0)
-
-#define WAIT_DES_DMA_READY() \
- do { \
- int i; \
- volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \
- volatile struct des_t *des = (struct des_t *) DES_3DES_START; \
- for (i = 0; i < 10; i++) \
- udelay(DELAY_PERIOD); \
- while (dma->controlr.BSY) {}; \
- while (des->controlr.BUS) {}; \
- } while (0)
-
-#define SHA_HASH_INIT \
- do { \
- volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; \
- hash->controlr.SM = 1; \
- hash->controlr.ALGO = 0; \
- hash->controlr.INIT = 1; \
- } while(0)
-
-/* DEU STRUCTURES */
-
-struct clc_controlr_t {
- u32 Res:26;
- u32 FSOE:1;
- u32 SBWE:1;
- u32 EDIS:1;
- u32 SPEN:1;
- u32 DISS:1;
- u32 DISR:1;
-
-};
-
-struct des_t {
- struct des_controlr {
- u32 KRE:1;
- u32 reserved1:5;
- u32 GO:1;
- u32 STP:1;
- u32 Res2:6;
- u32 NDC:1;
- u32 ENDI:1;
- u32 Res3:2;
- u32 F:3;
- u32 O:3;
- u32 BUS:1;
- u32 DAU:1;
- u32 ARS:1;
- u32 SM:1;
- u32 E_D:1;
- u32 M:3;
-
- } controlr;
- u32 IHR;
- u32 ILR;
- u32 K1HR;
- u32 K1LR;
- u32 K2HR;
- u32 K2LR;
- u32 K3HR;
- u32 K3LR;
- u32 IVHR;
- u32 IVLR;
- u32 OHR;
- u32 OLR;
-};
-
-struct aes_t {
- struct aes_controlr {
-
- u32 KRE:1;
- u32 reserved1:4;
- u32 PNK:1;
- u32 GO:1;
- u32 STP:1;
-
- u32 reserved2:6;
- u32 NDC:1;
- u32 ENDI:1;
- u32 reserved3:2;
-
- u32 F:3; //fbs
- u32 O:3; //om
- u32 BUS:1; //bsy
- u32 DAU:1;
- u32 ARS:1;
- u32 SM:1;
- u32 E_D:1;
- u32 KV:1;
- u32 K:2; //KL
-
- } controlr;
- u32 ID3R; //80h
- u32 ID2R; //84h
- u32 ID1R; //88h
- u32 ID0R; //8Ch
- u32 K7R; //90h
- u32 K6R; //94h
- u32 K5R; //98h
- u32 K4R; //9Ch
- u32 K3R; //A0h
- u32 K2R; //A4h
- u32 K1R; //A8h
- u32 K0R; //ACh
- u32 IV3R; //B0h
- u32 IV2R; //B4h
- u32 IV1R; //B8h
- u32 IV0R; //BCh
- u32 OD3R; //D4h
- u32 OD2R; //D8h
- u32 OD1R; //DCh
- u32 OD0R; //E0h
-};
-
-struct deu_hash_t {
- struct hash_controlr {
- u32 reserved1:5;
- u32 KHS:1;
- u32 GO:1;
- u32 INIT:1;
- u32 reserved2:6;
- u32 NDC:1;
- u32 ENDI:1;
- u32 reserved3:7;
- u32 DGRY:1;
- u32 BSY:1;
- u32 reserved4:1;
- u32 IRCL:1;
- u32 SM:1;
- u32 KYUE:1;
- u32 HMEN:1;
- u32 SSEN:1;
- u32 ALGO:1;
-
- } controlr;
- u32 MR; //B4h
- u32 D1R; //B8h
- u32 D2R; //BCh
- u32 D3R; //C0h
- u32 D4R; //C4h
- u32 D5R; //C8h
-
- u32 dummy; //CCh
-
- u32 KIDX; //D0h
- u32 KEY; //D4h
- u32 DBN; //D8h
-};
-
-struct deu_dma_t {
- struct dma_controlr {
- u32 reserved1:22;
- u32 BS:2;
- u32 BSY:1;
- u32 reserved2:1;
- u32 ALGO:2;
- u32 RXCLS:2;
- u32 reserved3:1;
- u32 EN:1;
-
- } controlr;
-};
-
-#endif /* IFXMIPS_DEU_DANUBE_H */
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
- * Copyright (C) 2009 Mohammad Firdaus
- */
-
-/*!
- \defgroup IFX_DEU IFX_DEU_DRIVERS
- \ingroup IFX_API
- \brief ifx deu driver module
-*/
-
-/*!
- \file ifxmips_deu_dma.c
- \ingroup IFX_DEU
- \brief DMA deu driver file
-*/
-
-/*!
- \defgroup IFX_DMA_FUNCTIONS IFX_DMA_FUNCTIONS
- \ingroup IFX_DEU
- \brief deu-dma driver functions
-*/
-
-/* Project header files */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <asm/io.h>
-#include "ifxmips_deu.h"
-
-extern _ifx_deu_device ifx_deu[1];
-extern spinlock_t ifx_deu_lock;
-
-//extern deu_drv_priv_t deu_dma_priv;
-
-/*! \fn int deu_dma_intr_handler (struct dma_device_info *dma_dev, int status)
- * \ingroup IFX_DMA_FUNCTIONS
- * \brief callback function for deu dma interrupt
- * \param dma_dev dma device
- * \param status not used
-*/
-int deu_dma_intr_handler (struct dma_device_info *dma_dev, int status)
-{
-#if 0
- int len = 0;
- while (len <= 20000) { len++; }
- u8 *buf;
- int len = 0;
-
-
- deu_drv_priv_t *deu_priv = (deu_drv_priv_t *)dma_dev->priv;
- //printk("status:%d \n",status);
- switch(status) {
- case RCV_INT:
- len = dma_device_read(dma_dev, (u8 **)&buf, NULL);
- if ( len != deu_priv->deu_rx_len) {
- printk(KERN_ERR "%s packet length %d is not equal to expect %d\n",
- __func__, len, deu_priv->deu_rx_len);
- return -1;
- }
- memcpy(deu_priv->deu_rx_buf, buf, deu_priv->deu_rx_len);
- /* Reset for next usage */
- deu_priv->deu_rx_buf = NULL;
- deu_priv->deu_rx_len = 0;
- DEU_WAKEUP_EVENT(deu_priv->deu_thread_wait, DEU_EVENT, deu_priv->deu_event_flags);
- break;
- case TX_BUF_FULL_INT:
- // delay for buffer to be cleared
- while (len <= 20000) { len++; }
- break;
-
- case TRANSMIT_CPT_INT:
- break;
- default:
- break;
- }
-#endif
- return 0;
-}
-
-extern u8 *g_dma_block;
-extern u8 *g_dma_block2;
-
-/*! \fn u8 *deu_dma_buffer_alloc (int len, int *byte_offset, void **opt)
- * \ingroup IFX_DMA_FUNCTIONS
- * \brief callback function for allocating buffers for dma receive descriptors
- * \param len not used
- * \param byte_offset dma byte offset
- * \param *opt not used
- *
-*/
-u8 *deu_dma_buffer_alloc (int len, int *byte_offset, void **opt)
-{
- u8 *swap = NULL;
-
- // dma-core needs at least 2 blocks of memory
- swap = g_dma_block;
- g_dma_block = g_dma_block2;
- g_dma_block2 = swap;
-
- //dma_cache_wback_inv((unsigned long) g_dma_block, (PAGE_SIZE >> 1));
- *byte_offset = 0;
-
- return g_dma_block;
-}
-
-/*! \fn int deu_dma_buffer_free (u8 * dataptr, void *opt)
- * \ingroup IFX_DMA_FUNCTIONS
- * \brief callback function for freeing dma transmit descriptors
- * \param dataptr data pointer to be freed
- * \param opt not used
-*/
-int deu_dma_buffer_free (u8 *dataptr, void *opt)
-{
-#if 0
- printk("Trying to free memory buffer\n");
- if (dataptr == NULL && opt == NULL)
- return 0;
- else if (opt == NULL) {
- kfree(dataptr);
- return 1;
- }
- else if (dataptr == NULL) {
- kfree(opt);
- return 1;
- }
- else {
- kfree(opt);
- kfree(dataptr);
- }
-#endif
- return 0;
-}
-
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
- * Copyright (C) 2009 Mohammad Firdaus
- */
-
-/*!
- \addtogroup IFX_DEU IFX_DEU_DRIVERS
- \ingroup API
- \brief ifx deu driver module
-*/
-
-/*!
- \file ifxmips_deu_dma.h
- \ingroup IFX_DEU
- \brief DMA deu driver header file
-*/
-
-#ifndef IFXMIPS_DEU_DMA_H
-#define IFXMIPS_DEU_DMA_H
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <linux/crypto.h>
-#include <asm/scatterlist.h>
-#include <asm/byteorder.h>
-#include <linux/skbuff.h>
-#include <linux/netdevice.h>
-
-// must match the size of memory block allocated for g_dma_block and g_dma_block2
-#define DEU_MAX_PACKET_SIZE (PAGE_SIZE >> 1)
-
-typedef struct ifx_deu_device {
- struct dma_device_info *dma_device;
- u8 *dst;
- u8 *src;
- int len;
- int dst_count;
- int src_count;
- int recv_count;
- int packet_size;
- int packet_num;
- wait_queue_t wait;
-} _ifx_deu_device;
-
-extern _ifx_deu_device ifx_deu[1];
-
-extern int deu_dma_intr_handler (struct dma_device_info *, int);
-extern u8 *deu_dma_buffer_alloc (int, int *, void **);
-extern int deu_dma_buffer_free (u8 *, void *);
-extern void deu_dma_inactivate_poll(struct dma_device_info* dma_dev);
-extern void deu_dma_activate_poll (struct dma_device_info* dma_dev);
-extern struct dma_device_info* deu_dma_reserve(struct dma_device_info** dma_device);
-extern int deu_dma_release(struct dma_device_info** dma_device);
-
-#endif /* IFMIPS_DEU_DMA_H */
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
- * Copyright (C) 2009 Mohammad Firdaus
- */
-
-/*!
- \defgroup IFX_DEU IFX_DEU_DRIVERS
- \ingroup API
- \brief ifx deu driver module
-*/
-
-/*!
- \file ifxmips_md5.c
- \ingroup IFX_DEU
- \brief MD5 encryption deu driver file
-*/
-
-/*!
- \defgroup IFX_MD5_FUNCTIONS IFX_MD5_FUNCTIONS
- \ingroup IFX_DEU
- \brief ifx deu MD5 functions
-*/
-
-/*Project header files */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/crypto.h>
-#include <linux/types.h>
-#include <asm/byteorder.h>
-#include "ifxmips_deu.h"
-
-#define MD5_DIGEST_SIZE 16
-#define MD5_HMAC_BLOCK_SIZE 64
-#define MD5_BLOCK_WORDS 16
-#define MD5_HASH_WORDS 4
-#define HASH_START IFX_HASH_CON
-
-static spinlock_t lock;
-#define CRTCL_SECT_INIT spin_lock_init(&lock)
-#define CRTCL_SECT_START spin_lock_irqsave(&lock, flag)
-#define CRTCL_SECT_END spin_unlock_irqrestore(&lock, flag)
-
-struct md5_ctx {
- u32 hash[MD5_HASH_WORDS];
- u32 block[MD5_BLOCK_WORDS];
- u64 byte_count;
-};
-
-extern int disable_deudma;
-
-/*! \fn static u32 endian_swap(u32 input)
- * \ingroup IFX_MD5_FUNCTIONS
- * \brief perform dword level endian swap
- * \param input value of dword that requires to be swapped
-*/
-static u32 endian_swap(u32 input)
-{
- u8 *ptr = (u8 *)&input;
-
- return ((ptr[3] << 24) | (ptr[2] << 16) | (ptr[1] << 8) | ptr[0]);
-}
-
-/*! \fn static void md5_transform(u32 *hash, u32 const *in)
- * \ingroup IFX_MD5_FUNCTIONS
- * \brief main interface to md5 hardware
- * \param hash current hash value
- * \param in 64-byte block of input
-*/
-static void md5_transform(u32 *hash, u32 const *in)
-{
- int i;
- volatile struct deu_hash_t *hashs = (struct deu_hash_t *) HASH_START;
- ulong flag;
-
- CRTCL_SECT_START;
-
- for (i = 0; i < 16; i++) {
- hashs->MR = endian_swap(in[i]);
- };
-
- //wait for processing
- while (hashs->controlr.BSY) {
- // this will not take long
- }
-
- CRTCL_SECT_END;
-}
-
-/*! \fn static inline void md5_transform_helper(struct md5_ctx *ctx)
- * \ingroup IFX_MD5_FUNCTIONS
- * \brief interfacing function for md5_transform()
- * \param ctx crypto context
-*/
-static inline void md5_transform_helper(struct md5_ctx *ctx)
-{
- //le32_to_cpu_array(ctx->block, sizeof(ctx->block) / sizeof(u32));
- md5_transform(ctx->hash, ctx->block);
-}
-
-/*! \fn static void md5_init(struct crypto_tfm *tfm)
- * \ingroup IFX_MD5_FUNCTIONS
- * \brief initialize md5 hardware
- * \param tfm linux crypto algo transform
-*/
-static void md5_init(struct crypto_tfm *tfm)
-{
- struct md5_ctx *mctx = crypto_tfm_ctx(tfm);
- volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START;
-
- hash->controlr.SM = 1;
- hash->controlr.ALGO = 1; // 1 = md5 0 = sha1
- hash->controlr.INIT = 1; // Initialize the hash operation by writing a '1' to the INIT bit.
-
- mctx->byte_count = 0;
-}
-
-/*! \fn static void md5_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len)
- * \ingroup IFX_MD5_FUNCTIONS
- * \brief on-the-fly md5 computation
- * \param tfm linux crypto algo transform
- * \param data input data
- * \param len size of input data
-*/
-static void md5_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len)
-{
- struct md5_ctx *mctx = crypto_tfm_ctx(tfm);
- const u32 avail = sizeof(mctx->block) - (mctx->byte_count & 0x3f);
-
- mctx->byte_count += len;
-
- if (avail > len) {
- memcpy((char *)mctx->block + (sizeof(mctx->block) - avail),
- data, len);
- return;
- }
-
- memcpy((char *)mctx->block + (sizeof(mctx->block) - avail),
- data, avail);
-
- md5_transform_helper(mctx);
- data += avail;
- len -= avail;
-
- while (len >= sizeof(mctx->block)) {
- memcpy(mctx->block, data, sizeof(mctx->block));
- md5_transform_helper(mctx);
- data += sizeof(mctx->block);
- len -= sizeof(mctx->block);
- }
-
- memcpy(mctx->block, data, len);
-}
-
-/*! \fn static void md5_final(struct crypto_tfm *tfm, u8 *out)
- * \ingroup IFX_MD5_FUNCTIONS
- * \brief compute final md5 value
- * \param tfm linux crypto algo transform
- * \param out final md5 output value
-*/
-static void md5_final(struct crypto_tfm *tfm, u8 *out)
-{
- struct md5_ctx *mctx = crypto_tfm_ctx(tfm);
- const unsigned int offset = mctx->byte_count & 0x3f;
- char *p = (char *)mctx->block + offset;
- int padding = 56 - (offset + 1);
- volatile struct deu_hash_t *hashs = (struct deu_hash_t *) HASH_START;
- u32 flag;
-
- *p++ = 0x80;
- if (padding < 0) {
- memset(p, 0x00, padding + sizeof (u64));
- md5_transform_helper(mctx);
- p = (char *)mctx->block;
- padding = 56;
- }
-
- memset(p, 0, padding);
- mctx->block[14] = endian_swap(mctx->byte_count << 3);
- mctx->block[15] = endian_swap(mctx->byte_count >> 29);
-
-#if 0
- le32_to_cpu_array(mctx->block, (sizeof(mctx->block) -
- sizeof(u64)) / sizeof(u32));
-#endif
-
- md5_transform(mctx->hash, mctx->block);
-
- CRTCL_SECT_START;
-
- *((u32 *) out + 0) = endian_swap (hashs->D1R);
- *((u32 *) out + 1) = endian_swap (hashs->D2R);
- *((u32 *) out + 2) = endian_swap (hashs->D3R);
- *((u32 *) out + 3) = endian_swap (hashs->D4R);
-
- CRTCL_SECT_END;
-
- // Wipe context
- memset(mctx, 0, sizeof(*mctx));
-}
-
-/*
- * \brief MD5 function mappings
-*/
-static struct crypto_alg ifxdeu_md5_alg = {
- .cra_name = "md5",
- .cra_driver_name = "ifxdeu-md5",
- .cra_flags = CRYPTO_ALG_TYPE_DIGEST,
- .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct md5_ctx),
- .cra_module = THIS_MODULE,
- .cra_list = LIST_HEAD_INIT(ifxdeu_md5_alg.cra_list),
- .cra_u = { .digest = {
- .dia_digestsize = MD5_DIGEST_SIZE,
- .dia_init = md5_init,
- .dia_update = md5_update,
- .dia_final = md5_final } }
-};
-
-/*! \fn int __init ifxdeu_init_md5 (void)
- * \ingroup IFX_MD5_FUNCTIONS
- * \brief initialize md5 driver
-*/
-int __init ifxdeu_init_md5 (void)
-{
- int ret;
-
- if ((ret = crypto_register_alg(&ifxdeu_md5_alg)))
- goto md5_err;
-
- CRTCL_SECT_INIT;
-
- printk (KERN_NOTICE "IFX DEU MD5 initialized%s.\n", disable_deudma ? "" : " (DMA)");
- return ret;
-
-md5_err:
- printk(KERN_ERR "IFX DEU MD5 initialization failed!\n");
- return ret;
-}
-
-/*! \fn void __exit ifxdeu_fini_md5 (void)
- * \ingroup IFX_MD5_FUNCTIONS
- * \brief unregister md5 driver
-*/
-
-void __exit ifxdeu_fini_md5 (void)
-{
- crypto_unregister_alg (&ifxdeu_md5_alg);
-}
-
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
- * Copyright (C) 2009 Mohammad Firdaus
- */
-
-/*!
- \defgroup IFX_DEU IFX_DEU_DRIVERS
- \ingroup API
- \brief ifx deu driver module
-*/
-
-/*!
- \file ifxmips_md5_hmac.c
- \ingroup IFX_DEU
- \brief MD5-HMAC encryption deu driver file
-*/
-
-/*!
- \defgroup IFX_MD5_HMAC_FUNCTIONS IFX_MD5_HMAC_FUNCTIONS
- \ingroup IFX_DEU
- \brief ifx md5-hmac driver functions
-*/
-
-/* Project Header files */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/crypto.h>
-#include <linux/types.h>
-#include <asm/byteorder.h>
-#include "ifxmips_deu.h"
-
-#define MD5_DIGEST_SIZE 16
-#define MD5_HMAC_BLOCK_SIZE 64
-#define MD5_BLOCK_WORDS 16
-#define MD5_HASH_WORDS 4
-#define MD5_HMAC_DBN_TEMP_SIZE 1024 // size in dword, needed for dbn workaround
-#define HASH_START IFX_HASH_CON
-
-static spinlock_t lock;
-#define CRTCL_SECT_INIT spin_lock_init(&lock)
-#define CRTCL_SECT_START spin_lock_irqsave(&lock, flag)
-#define CRTCL_SECT_END spin_unlock_irqrestore(&lock, flag)
-
-struct md5_hmac_ctx {
- u32 hash[MD5_HASH_WORDS];
- u32 block[MD5_BLOCK_WORDS];
- u64 byte_count;
- u32 dbn;
- u32 temp[MD5_HMAC_DBN_TEMP_SIZE];
-};
-
-extern int disable_deudma;
-
-/*! \fn static u32 endian_swap(u32 input)
- * \ingroup IFX_MD5_HMAC_FUNCTIONS
- * \brief perform dword level endian swap
- * \param input value of dword that requires to be swapped
-*/
-static u32 endian_swap(u32 input)
-{
- u8 *ptr = (u8 *)&input;
-
- return ((ptr[3] << 24) | (ptr[2] << 16) | (ptr[1] << 8) | ptr[0]);
-}
-
-/*! \fn static void md5_hmac_transform(struct crypto_tfm *tfm, u32 const *in)
- * \ingroup IFX_MD5_HMAC_FUNCTIONS
- * \brief save input block to context
- * \param tfm linux crypto algo transform
- * \param in 64-byte block of input
-*/
-static void md5_hmac_transform(struct crypto_tfm *tfm, u32 const *in)
-{
- struct md5_hmac_ctx *mctx = crypto_tfm_ctx(tfm);
-
- memcpy(&mctx->temp[mctx->dbn<<4], in, 64); //dbn workaround
- mctx->dbn += 1;
-
- if ( (mctx->dbn<<4) > MD5_HMAC_DBN_TEMP_SIZE )
- {
- printk("MD5_HMAC_DBN_TEMP_SIZE exceeded\n");
- }
-
-}
-
-/*! \fn int md5_hmac_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen)
- * \ingroup IFX_MD5_HMAC_FUNCTIONS
- * \brief sets md5 hmac key
- * \param tfm linux crypto algo transform
- * \param key input key
- * \param keylen key length greater than 64 bytes IS NOT SUPPORTED
-*/
-int md5_hmac_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen)
-{
- volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START;
- int i, j;
- u32 *in_key = (u32 *)key;
-
- hash->KIDX = 0x80000000; // reset all 16 words of the key to '0'
- asm("sync");
-
- j = 0;
- for (i = 0; i < keylen; i+=4)
- {
- hash->KIDX = j;
- asm("sync");
- hash->KEY = *((u32 *) in_key + j);
- j++;
- }
-
- return 0;
-}
-
-/*! \fn void md5_hmac_init(struct crypto_tfm *tfm)
- * \ingroup IFX_MD5_HMAC_FUNCTIONS
- * \brief initialize md5 hmac context
- * \param tfm linux crypto algo transform
-*/
-void md5_hmac_init(struct crypto_tfm *tfm)
-{
- struct md5_hmac_ctx *mctx = crypto_tfm_ctx(tfm);
-
- memset(mctx, 0, sizeof(struct md5_hmac_ctx));
- mctx->dbn = 0; //dbn workaround
-}
-
-/*! \fn void md5_hmac_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len)
- * \ingroup IFX_MD5_HMAC_FUNCTIONS
- * \brief on-the-fly md5 hmac computation
- * \param tfm linux crypto algo transform
- * \param data input data
- * \param len size of input data
-*/
-void md5_hmac_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len)
-{
- struct md5_hmac_ctx *mctx = crypto_tfm_ctx(tfm);
- const u32 avail = sizeof(mctx->block) - (mctx->byte_count & 0x3f);
-
- mctx->byte_count += len;
-
- if (avail > len) {
- memcpy((char *)mctx->block + (sizeof(mctx->block) - avail),
- data, len);
- return;
- }
-
- memcpy((char *)mctx->block + (sizeof(mctx->block) - avail),
- data, avail);
-
- md5_hmac_transform(tfm, mctx->block);
- data += avail;
- len -= avail;
-
- while (len >= sizeof(mctx->block)) {
- memcpy(mctx->block, data, sizeof(mctx->block));
- md5_hmac_transform(tfm, mctx->block);
- data += sizeof(mctx->block);
- len -= sizeof(mctx->block);
- }
-
- memcpy(mctx->block, data, len);
-
-}
-
-/*! \fn void md5_hmac_final(struct crypto_tfm *tfm, u8 *out)
- * \ingroup IFX_MD5_HMAC_FUNCTIONS
- * \brief compute final md5 hmac value
- * \param tfm linux crypto algo transform
- * \param out final md5 hmac output value
-*/
-void md5_hmac_final(struct crypto_tfm *tfm, u8 *out)
-{
- struct md5_hmac_ctx *mctx = crypto_tfm_ctx(tfm);
- const unsigned int offset = mctx->byte_count & 0x3f;
- char *p = (char *)mctx->block + offset;
- int padding = 56 - (offset + 1);
- volatile struct deu_hash_t *hashs = (struct deu_hash_t *) HASH_START;
- u32 flag;
- int i = 0;
- int dbn;
- u32 *in = &mctx->temp[0];
-
- *p++ = 0x80;
- if (padding < 0) {
- memset(p, 0x00, padding + sizeof (u64));
- md5_hmac_transform(tfm, mctx->block);
- p = (char *)mctx->block;
- padding = 56;
- }
-
- memset(p, 0, padding);
- mctx->block[14] = endian_swap((mctx->byte_count + 64) << 3); // need to add 512 bit of the IPAD operation
- mctx->block[15] = 0x00000000;
-
- md5_hmac_transform(tfm, mctx->block);
-
- CRTCL_SECT_START;
-
- printk("dbn = %d\n", mctx->dbn);
- hashs->DBN = mctx->dbn;
-
- *IFX_HASH_CON = 0x0703002D; //khs, go, init, ndc, endi, kyue, hmen, md5
-
- //wait for processing
- while (hashs->controlr.BSY) {
- // this will not take long
- }
-
-for (dbn = 0; dbn < mctx->dbn; dbn++)
-{
- for (i = 0; i < 16; i++) {
- hashs->MR = in[i];
- };
-
- hashs->controlr.GO = 1;
- asm("sync");
-
- //wait for processing
- while (hashs->controlr.BSY) {
- // this will not take long
- }
-
- in += 16;
-}
-
-
-#if 1
- //wait for digest ready
- while (! hashs->controlr.DGRY) {
- // this will not take long
- }
-#endif
-
- *((u32 *) out + 0) = hashs->D1R;
- *((u32 *) out + 1) = hashs->D2R;
- *((u32 *) out + 2) = hashs->D3R;
- *((u32 *) out + 3) = hashs->D4R;
- *((u32 *) out + 4) = hashs->D5R;
-
- CRTCL_SECT_END;
-}
-
-/*
- * \brief MD5_HMAC function mappings
-*/
-
-static struct crypto_alg ifxdeu_md5_hmac_alg = {
- .cra_name = "hmac(md5)",
- .cra_driver_name = "ifxdeu-md5_hmac",
- .cra_flags = CRYPTO_ALG_TYPE_DIGEST,
- .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct md5_hmac_ctx),
- .cra_module = THIS_MODULE,
- .cra_list = LIST_HEAD_INIT(ifxdeu_md5_hmac_alg.cra_list),
- .cra_u = { .digest = {
- .dia_digestsize = MD5_DIGEST_SIZE,
- .dia_setkey = md5_hmac_setkey,
- .dia_init = md5_hmac_init,
- .dia_update = md5_hmac_update,
- .dia_final = md5_hmac_final } }
-};
-
-/*! \fn int __init ifxdeu_init_md5_hmac (void)
- * \ingroup IFX_MD5_HMAC_FUNCTIONS
- * \brief initialize md5 hmac driver
-*/
-int __init ifxdeu_init_md5_hmac (void)
-{
- int ret;
-
- if ((ret = crypto_register_alg(&ifxdeu_md5_hmac_alg)))
- goto md5_hmac_err;
-
- CRTCL_SECT_INIT;
-
- printk (KERN_NOTICE "IFX DEU MD5_HMAC initialized%s.\n", disable_deudma ? "" : " (DMA)");
- return ret;
-
-md5_hmac_err:
- printk(KERN_ERR "IFX DEU MD5_HMAC initialization failed!\n");
- return ret;
-}
-
-/** \fn void __exit ifxdeu_fini_md5_hmac (void)
- * \ingroup IFX_MD5_HMAC_FUNCTIONS
- * \brief unregister md5 hmac driver
-*/
-void __exit ifxdeu_fini_md5_hmac (void)
-{
- crypto_unregister_alg (&ifxdeu_md5_hmac_alg);
-}
-
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
- * Copyright (C) 2009 Mohammad Firdaus
- */
-
-/*!
- \defgroup IFX_DEU IFX_DEU_DRIVERS
- \ingroup API
- \brief ifx deu driver module
-*/
-
-/*!
- \file ifxmips_sha1.c
- \ingroup IFX_DEU
- \brief SHA1 encryption deu driver file
-*/
-
-/*!
- \defgroup IFX_SHA1_FUNCTIONS IFX_SHA1_FUNCTIONS
- \ingroup IFX_DEU
- \brief ifx deu sha1 functions
-*/
-
-
-/* Project header */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <linux/crypto.h>
-#include <linux/cryptohash.h>
-#include <linux/types.h>
-#include <asm/scatterlist.h>
-#include <asm/byteorder.h>
-#include "ifxmips_deu.h"
-
-#define SHA1_DIGEST_SIZE 20
-#define SHA1_HMAC_BLOCK_SIZE 64
-#define HASH_START IFX_HASH_CON
-
-static spinlock_t lock;
-#define CRTCL_SECT_INIT spin_lock_init(&lock)
-#define CRTCL_SECT_START spin_lock_irqsave(&lock, flag)
-#define CRTCL_SECT_END spin_unlock_irqrestore(&lock, flag)
-
-/*
- * \brief SHA1 private structure
-*/
-struct sha1_ctx {
- u64 count;
- u32 state[5];
- u8 buffer[64];
-};
-
-extern int disable_deudma;
-
-
-/*! \fn static void sha1_transform (u32 *state, const u32 *in)
- * \ingroup IFX_SHA1_FUNCTIONS
- * \brief main interface to sha1 hardware
- * \param state current state
- * \param in 64-byte block of input
-*/
-static void sha1_transform (u32 *state, const u32 *in)
-{
- int i = 0;
- volatile struct deu_hash_t *hashs = (struct deu_hash_t *) HASH_START;
- u32 flag;
-
- CRTCL_SECT_START;
-
- for (i = 0; i < 16; i++) {
- hashs->MR = in[i];
- };
-
- //wait for processing
- while (hashs->controlr.BSY) {
- // this will not take long
- }
-
- CRTCL_SECT_END;
-}
-
-/*! \fn static void sha1_init(struct crypto_tfm *tfm)
- * \ingroup IFX_SHA1_FUNCTIONS
- * \brief initialize sha1 hardware
- * \param tfm linux crypto algo transform
-*/
-static void sha1_init(struct crypto_tfm *tfm)
-{
- struct sha1_ctx *sctx = crypto_tfm_ctx(tfm);
-
- SHA_HASH_INIT;
-
- sctx->count = 0;
-}
-
-/*! \fn static void sha1_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len)
- * \ingroup IFX_SHA1_FUNCTIONS
- * \brief on-the-fly sha1 computation
- * \param tfm linux crypto algo transform
- * \param data input data
- * \param len size of input data
-*/
-static void sha1_update(struct crypto_tfm *tfm, const u8 *data,
- unsigned int len)
-{
- struct sha1_ctx *sctx = crypto_tfm_ctx(tfm);
- unsigned int i, j;
-
- j = (sctx->count >> 3) & 0x3f;
- sctx->count += len << 3;
-
- if ((j + len) > 63) {
- memcpy (&sctx->buffer[j], data, (i = 64 - j));
- sha1_transform (sctx->state, (const u32 *)sctx->buffer);
- for (; i + 63 < len; i += 64) {
- sha1_transform (sctx->state, (const u32 *)&data[i]);
- }
-
- j = 0;
- }
- else
- i = 0;
-
- memcpy (&sctx->buffer[j], &data[i], len - i);
-}
-
-/*! \fn static void sha1_final(struct crypto_tfm *tfm, u8 *out)
- * \ingroup IFX_SHA1_FUNCTIONS
- * \brief compute final sha1 value
- * \param tfm linux crypto algo transform
- * \param out final md5 output value
-*/
-static void sha1_final(struct crypto_tfm *tfm, u8 *out)
-{
- struct sha1_ctx *sctx = crypto_tfm_ctx(tfm);
- u32 index, padlen;
- u64 t;
- u8 bits[8] = { 0, };
- static const u8 padding[64] = { 0x80, };
- volatile struct deu_hash_t *hashs = (struct deu_hash_t *) HASH_START;
- ulong flag;
-
- t = sctx->count;
- bits[7] = 0xff & t;
- t >>= 8;
- bits[6] = 0xff & t;
- t >>= 8;
- bits[5] = 0xff & t;
- t >>= 8;
- bits[4] = 0xff & t;
- t >>= 8;
- bits[3] = 0xff & t;
- t >>= 8;
- bits[2] = 0xff & t;
- t >>= 8;
- bits[1] = 0xff & t;
- t >>= 8;
- bits[0] = 0xff & t;
-
- /* Pad out to 56 mod 64 */
- index = (sctx->count >> 3) & 0x3f;
- padlen = (index < 56) ? (56 - index) : ((64 + 56) - index);
- sha1_update (tfm, padding, padlen);
-
- /* Append length */
- sha1_update (tfm, bits, sizeof bits);
-
- CRTCL_SECT_START;
-
- *((u32 *) out + 0) = hashs->D1R;
- *((u32 *) out + 1) = hashs->D2R;
- *((u32 *) out + 2) = hashs->D3R;
- *((u32 *) out + 3) = hashs->D4R;
- *((u32 *) out + 4) = hashs->D5R;
-
- CRTCL_SECT_END;
-
- // Wipe context
- memset (sctx, 0, sizeof *sctx);
-}
-
-/*
- * \brief SHA1 function mappings
-*/
-struct crypto_alg ifxdeu_sha1_alg = {
- .cra_name = "sha1",
- .cra_driver_name= "ifxdeu-sha1",
- .cra_flags = CRYPTO_ALG_TYPE_DIGEST,
- .cra_blocksize = SHA1_HMAC_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct sha1_ctx),
- .cra_module = THIS_MODULE,
- .cra_alignmask = 3,
- .cra_list = LIST_HEAD_INIT(ifxdeu_sha1_alg.cra_list),
- .cra_u = { .digest = {
- .dia_digestsize = SHA1_DIGEST_SIZE,
- .dia_init = sha1_init,
- .dia_update = sha1_update,
- .dia_final = sha1_final } }
-};
-
-/*! \fn int __init ifxdeu_init_sha1 (void)
- * \ingroup IFX_SHA1_FUNCTIONS
- * \brief initialize sha1 driver
-*/
-int __init ifxdeu_init_sha1 (void)
-{
- int ret;
-
- if ((ret = crypto_register_alg(&ifxdeu_sha1_alg)))
- goto sha1_err;
-
- CRTCL_SECT_INIT;
-
- printk (KERN_NOTICE "IFX DEU SHA1 initialized%s.\n", disable_deudma ? "" : " (DMA)");
- return ret;
-
-sha1_err:
- printk(KERN_ERR "IFX DEU SHA1 initialization failed!\n");
- return ret;
-}
-
-/*! \fn void __exit ifxdeu_fini_sha1 (void)
- * \ingroup IFX_SHA1_FUNCTIONS
- * \brief unregister sha1 driver
-*/
-void __exit ifxdeu_fini_sha1 (void)
-{
- crypto_unregister_alg (&ifxdeu_sha1_alg);
-}
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
- * Copyright (C) 2009 Mohammad Firdaus
- */
-
-/*!
- \defgroup IFX_DEU IFX_DEU_DRIVERS
- \ingroup API
- \brief ifx deu driver module
-*/
-
-/*!
- \file ifxmips_sha1_hmac.c
- \ingroup IFX_DEU
- \brief SHA1-HMAC deu driver file
-*/
-
-/*!
- \defgroup IFX_SHA1_HMAC_FUNCTIONS IFX_SHA1_HMAC_FUNCTIONS
- \ingroup IFX_DEU
- \brief ifx sha1 hmac functions
-*/
-
-
-/* Project header */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <linux/crypto.h>
-#include <linux/cryptohash.h>
-#include <linux/types.h>
-#include <asm/scatterlist.h>
-#include <asm/byteorder.h>
-#include <linux/delay.h>
-#include "ifxmips_deu.h"
-
-#ifdef CONFIG_CRYPTO_DEV_IFXMIPS_SHA1_HMAC
-
-#define SHA1_DIGEST_SIZE 20
-#define SHA1_HMAC_BLOCK_SIZE 64
-#define SHA1_HMAC_DBN_TEMP_SIZE 1024 // size in dword, needed for dbn workaround
-#define HASH_START IFX_HASH_CON
-
-static spinlock_t lock;
-#define CRTCL_SECT_INIT spin_lock_init(&lock)
-#define CRTCL_SECT_START spin_lock_irqsave(&lock, flag)
-#define CRTCL_SECT_END spin_unlock_irqrestore(&lock, flag)
-
-struct sha1_hmac_ctx {
- u64 count;
- u32 state[5];
- u8 buffer[64];
- u32 dbn;
- u32 temp[SHA1_HMAC_DBN_TEMP_SIZE];
-};
-
-extern int disable_deudma;
-
-/*! \fn static void sha1_hmac_transform(struct crypto_tfm *tfm, u32 const *in)
- * \ingroup IFX_SHA1_HMAC_FUNCTIONS
- * \brief save input block to context
- * \param tfm linux crypto algo transform
- * \param in 64-byte block of input
-*/
-static void sha1_hmac_transform(struct crypto_tfm *tfm, u32 const *in)
-{
- struct sha1_hmac_ctx *sctx = crypto_tfm_ctx(tfm);
-
- memcpy(&sctx->temp[sctx->dbn<<4], in, 64); //dbn workaround
- sctx->dbn += 1;
-
- if ( (sctx->dbn<<4) > SHA1_HMAC_DBN_TEMP_SIZE )
- {
- printk("SHA1_HMAC_DBN_TEMP_SIZE exceeded\n");
- }
-
-}
-
-/*! \fn int sha1_hmac_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen)
- * \ingroup IFX_SHA1_HMAC_FUNCTIONS
- * \brief sets sha1 hmac key
- * \param tfm linux crypto algo transform
- * \param key input key
- * \param keylen key length greater than 64 bytes IS NOT SUPPORTED
-*/
-int sha1_hmac_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen)
-{
- volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START;
- int i, j;
- u32 *in_key = (u32 *)key;
-
- hash->KIDX = 0x80000000; // reset all 16 words of the key to '0'
- asm("sync");
-
- j = 0;
- for (i = 0; i < keylen; i+=4)
- {
- hash->KIDX = j;
- asm("sync");
- hash->KEY = *((u32 *) in_key + j);
- j++;
- }
-
- return 0;
-}
-
-/*! \fn void sha1_hmac_init(struct crypto_tfm *tfm)
- * \ingroup IFX_SHA1_HMAC_FUNCTIONS
- * \brief initialize sha1 hmac context
- * \param tfm linux crypto algo transform
-*/
-void sha1_hmac_init(struct crypto_tfm *tfm)
-{
- struct sha1_hmac_ctx *sctx = crypto_tfm_ctx(tfm);
-
- memset(sctx, 0, sizeof(struct sha1_hmac_ctx));
- sctx->dbn = 0; //dbn workaround
-}
-
-/*! \fn static void sha1_hmac_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len)
- * \ingroup IFX_SHA1_HMAC_FUNCTIONS
- * \brief on-the-fly sha1 hmac computation
- * \param tfm linux crypto algo transform
- * \param data input data
- * \param len size of input data
-*/
-static void sha1_hmac_update(struct crypto_tfm *tfm, const u8 *data,
- unsigned int len)
-{
- struct sha1_hmac_ctx *sctx = crypto_tfm_ctx(tfm);
- unsigned int i, j;
-
- j = (sctx->count >> 3) & 0x3f;
- sctx->count += len << 3;
- //printk("sctx->count = %d\n", (sctx->count >> 3));
-
- if ((j + len) > 63) {
- memcpy (&sctx->buffer[j], data, (i = 64 - j));
- sha1_hmac_transform (tfm, (const u32 *)sctx->buffer);
- for (; i + 63 < len; i += 64) {
- sha1_hmac_transform (tfm, (const u32 *)&data[i]);
- }
-
- j = 0;
- }
- else
- i = 0;
-
- memcpy (&sctx->buffer[j], &data[i], len - i);
-}
-
-/*! \fn static void sha1_hmac_final(struct crypto_tfm *tfm, u8 *out)
- * \ingroup IFX_SHA1_HMAC_FUNCTIONS
- * \brief ompute final sha1 hmac value
- * \param tfm linux crypto algo transform
- * \param out final sha1 hmac output value
-*/
-static void sha1_hmac_final(struct crypto_tfm *tfm, u8 *out)
-{
- struct sha1_hmac_ctx *sctx = crypto_tfm_ctx(tfm);
- u32 index, padlen;
- u64 t;
- u8 bits[8] = { 0, };
- static const u8 padding[64] = { 0x80, };
- volatile struct deu_hash_t *hashs = (struct deu_hash_t *) HASH_START;
- ulong flag;
- int i = 0;
- int dbn;
- u32 *in = &sctx->temp[0];
-
- t = sctx->count + 512; // need to add 512 bit of the IPAD operation
- bits[7] = 0xff & t;
- t >>= 8;
- bits[6] = 0xff & t;
- t >>= 8;
- bits[5] = 0xff & t;
- t >>= 8;
- bits[4] = 0xff & t;
- t >>= 8;
- bits[3] = 0xff & t;
- t >>= 8;
- bits[2] = 0xff & t;
- t >>= 8;
- bits[1] = 0xff & t;
- t >>= 8;
- bits[0] = 0xff & t;
-
- /* Pad out to 56 mod 64 */
- index = (sctx->count >> 3) & 0x3f;
- padlen = (index < 56) ? (56 - index) : ((64 + 56) - index);
- sha1_hmac_update (tfm, padding, padlen);
-
- /* Append length */
- sha1_hmac_update (tfm, bits, sizeof bits);
-
- CRTCL_SECT_START;
-
- hashs->DBN = sctx->dbn;
-
- //for vr9 change, ENDI = 1
- *IFX_HASH_CON = HASH_CON_VALUE;
-
- //wait for processing
- while (hashs->controlr.BSY) {
- // this will not take long
- }
-
- for (dbn = 0; dbn < sctx->dbn; dbn++)
- {
- for (i = 0; i < 16; i++) {
- hashs->MR = in[i];
- };
-
- hashs->controlr.GO = 1;
- asm("sync");
-
- //wait for processing
- while (hashs->controlr.BSY) {
- // this will not take long
- }
-
- in += 16;
-}
-
-
-#if 1
- //wait for digest ready
- while (! hashs->controlr.DGRY) {
- // this will not take long
- }
-#endif
-
- *((u32 *) out + 0) = hashs->D1R;
- *((u32 *) out + 1) = hashs->D2R;
- *((u32 *) out + 2) = hashs->D3R;
- *((u32 *) out + 3) = hashs->D4R;
- *((u32 *) out + 4) = hashs->D5R;
-
- CRTCL_SECT_END;
-}
-
-/*
- * \brief SHA1-HMAC function mappings
-*/
-
-struct crypto_alg ifxdeu_sha1_hmac_alg = {
- .cra_name = "hmac(sha1)",
- .cra_driver_name= "ifxdeu-sha1_hmac",
- .cra_flags = CRYPTO_ALG_TYPE_DIGEST,
- .cra_blocksize = SHA1_HMAC_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct sha1_hmac_ctx),
- .cra_module = THIS_MODULE,
- .cra_alignmask = 3,
- .cra_list = LIST_HEAD_INIT(ifxdeu_sha1_hmac_alg.cra_list),
- .cra_u = { .digest = {
- .dia_digestsize = SHA1_DIGEST_SIZE,
- .dia_setkey = sha1_hmac_setkey,
- .dia_init = sha1_hmac_init,
- .dia_update = sha1_hmac_update,
- .dia_final = sha1_hmac_final } }
-};
-
-
-/*! \fn int __init ifxdeu_init_sha1_hmac (void)
- * \ingroup IFX_SHA1_HMAC_FUNCTIONS
- * \brief initialize sha1 hmac driver
-*/
-int __init ifxdeu_init_sha1_hmac (void)
-{
- int ret;
-
- if ((ret = crypto_register_alg(&ifxdeu_sha1_hmac_alg)))
- goto sha1_err;
-
- CRTCL_SECT_INIT;
-
- printk (KERN_NOTICE "IFX DEU SHA1_HMAC initialized%s.\n", disable_deudma ? "" : " (DMA)");
- return ret;
-
-sha1_err:
- printk(KERN_ERR "IFX DEU SHA1_HMAC initialization failed!\n");
- return ret;
-}
-
-/*! \fn void __exit ifxdeu_fini_sha1_hmac (void)
- * \ingroup IFX_SHA1_HMAC_FUNCTIONS
- * \brief unregister sha1 hmac driver
-*/
-void __exit ifxdeu_fini_sha1_hmac (void)
-{
- crypto_unregister_alg (&ifxdeu_sha1_hmac_alg);
-}
-
-#endif
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2006 infineon
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- *
- */
-
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/uaccess.h>
-#include <linux/unistd.h>
-#include <linux/errno.h>
-#include <linux/leds.h>
-#include <linux/delay.h>
-
-#include <ifxmips.h>
-#include <ifxmips_gpio.h>
-#include <ifxmips_pmu.h>
-
-#define DRVNAME "ifxmips_led"
-
-/* might need to be changed depending on shift register used on the pcb */
-#if 1
-#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_FALLING
-#else
-#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_RISING
-#endif
-
-#define IFXMIPS_LED_SPEED IFXMIPS_LED_8HZ
-
-#define IFXMIPS_LED_GPIO_PORT 0
-
-#define IFXMIPS_MAX_LED 24
-
-struct ifxmips_led {
- struct led_classdev cdev;
- u8 bit;
-};
-
-void ifxmips_led_set(unsigned int led)
-{
- led &= 0xffffff;
- ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CPU0) | led, IFXMIPS_LED_CPU0);
-}
-EXPORT_SYMBOL(ifxmips_led_set);
-
-void ifxmips_led_clear(unsigned int led)
-{
- led = ~(led & 0xffffff);
- ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CPU0) & led, IFXMIPS_LED_CPU0);
-}
-EXPORT_SYMBOL(ifxmips_led_clear);
-
-void ifxmips_led_blink_set(unsigned int led)
-{
- led &= 0xffffff;
- ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | led, IFXMIPS_LED_CON0);
-}
-EXPORT_SYMBOL(ifxmips_led_blink_set);
-
-void ifxmips_led_blink_clear(unsigned int led)
-{
- led = ~(led & 0xffffff);
- ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) & led, IFXMIPS_LED_CON0);
-}
-EXPORT_SYMBOL(ifxmips_led_blink_clear);
-
-static void ifxmips_ledapi_set(struct led_classdev *led_cdev,
- enum led_brightness value)
-{
- struct ifxmips_led *led_dev =
- container_of(led_cdev, struct ifxmips_led, cdev);
-
- if (value)
- ifxmips_led_set(1 << led_dev->bit);
- else
- ifxmips_led_clear(1 << led_dev->bit);
-}
-
-void ifxmips_led_setup_gpio(void)
-{
- int i = 0;
-
- /* leds are controlled via a shift register
- we need to setup pins SH,D,ST (4,5,6) to make it work */
- for (i = 4; i < 7; i++) {
- ifxmips_port_set_altsel0(IFXMIPS_LED_GPIO_PORT, i);
- ifxmips_port_clear_altsel1(IFXMIPS_LED_GPIO_PORT, i);
- ifxmips_port_set_dir_out(IFXMIPS_LED_GPIO_PORT, i);
- ifxmips_port_set_open_drain(IFXMIPS_LED_GPIO_PORT, i);
- }
-}
-
-static int ifxmips_led_probe(struct platform_device *dev)
-{
- int i = 0;
-
- ifxmips_led_setup_gpio();
-
- ifxmips_w32(0, IFXMIPS_LED_AR);
- ifxmips_w32(0, IFXMIPS_LED_CPU0);
- ifxmips_w32(0, IFXMIPS_LED_CPU1);
- ifxmips_w32(LED_CON0_SWU, IFXMIPS_LED_CON0);
- ifxmips_w32(0, IFXMIPS_LED_CON1);
-
- /* setup the clock edge that the shift register is triggered on */
- ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) & ~IFXMIPS_LED_EDGE_MASK,
- IFXMIPS_LED_CON0);
- ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | IFXMIPS_LED_CLK_EDGE,
- IFXMIPS_LED_CON0);
-
- /* per default leds 15-0 are set */
- ifxmips_w32(IFXMIPS_LED_GROUP1 | IFXMIPS_LED_GROUP0, IFXMIPS_LED_CON1);
-
- /* leds are update periodically by the FPID */
- ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_UPD_MASK,
- IFXMIPS_LED_CON1);
- ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) | IFXMIPS_LED_UPD_SRC_FPI,
- IFXMIPS_LED_CON1);
-
- /* set led update speed */
- ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_MASK,
- IFXMIPS_LED_CON1);
- ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) | IFXMIPS_LED_SPEED,
- IFXMIPS_LED_CON1);
-
- /* adsl 0 and 1 leds are updated by the arc */
- ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | IFXMIPS_LED_ADSL_SRC,
- IFXMIPS_LED_CON0);
-
- /* per default, the leds are turned on */
- ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_LED);
-
- for (i = 0; i < IFXMIPS_MAX_LED; i++) {
- struct ifxmips_led *tmp =
- kzalloc(sizeof(struct ifxmips_led), GFP_KERNEL);
- tmp->cdev.brightness_set = ifxmips_ledapi_set;
- tmp->cdev.name = kmalloc(sizeof("ifxmips:led:00"), GFP_KERNEL);
- sprintf((char *)tmp->cdev.name, "ifxmips:led:%02d", i);
- tmp->cdev.default_trigger = NULL;
- tmp->bit = i;
- led_classdev_register(&dev->dev, &tmp->cdev);
- }
-
- return 0;
-}
-
-static int ifxmips_led_remove(struct platform_device *pdev)
-{
- return 0;
-}
-
-static struct platform_driver ifxmips_led_driver = {
- .probe = ifxmips_led_probe,
- .remove = ifxmips_led_remove,
- .driver = {
- .name = DRVNAME,
- .owner = THIS_MODULE,
- },
-};
-
-int __init ifxmips_led_init(void)
-{
- int ret = platform_driver_register(&ifxmips_led_driver);
- if (ret)
- printk(KERN_INFO
- "ifxmips_led: Error registering platfom driver!");
-
- return ret;
-}
-
-void __exit ifxmips_led_exit(void)
-{
- platform_driver_unregister(&ifxmips_led_driver);
-}
-
-module_init(ifxmips_led_init);
-module_exit(ifxmips_led_exit);
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE
- * Copyright (C) 2008 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/cfi.h>
-#include <linux/magic.h>
-#include <linux/platform_device.h>
-
-#include <ifxmips.h>
-#include <ifxmips_prom.h>
-#include <ifxmips_ebu.h>
-
-#ifndef CONFIG_MTD_PARTITIONS
-#error Please enable CONFIG_MTD_PARTITIONS
-#endif
-
-static struct map_info ifxmips_map = {
- .name = "ifx-nor",
- .bankwidth = 2,
- .size = 0x400000,
-};
-
-static map_word ifxmips_read16(struct map_info *map, unsigned long adr)
-{
- unsigned long flags;
- map_word temp;
- spin_lock_irqsave(&ebu_lock, flags);
- adr ^= 2;
- temp.x[0] = *((__u16 *)(map->virt + adr));
- spin_unlock_irqrestore(&ebu_lock, flags);
- return temp;
-}
-
-static void ifxmips_write16(struct map_info *map, map_word d, unsigned long adr)
-{
- unsigned long flags;
- spin_lock_irqsave(&ebu_lock, flags);
- adr ^= 2;
- *((__u16 *)(map->virt + adr)) = d.x[0];
- spin_unlock_irqrestore(&ebu_lock, flags);
-}
-
-void ifxmips_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
-{
- unsigned char *p;
- unsigned char *to_8;
- unsigned long flags;
- spin_lock_irqsave(&ebu_lock, flags);
- from = (unsigned long)(from + map->virt);
- p = (unsigned char *) from;
- to_8 = (unsigned char *) to;
- while (len--)
- *to_8++ = *p++;
- spin_unlock_irqrestore(&ebu_lock, flags);
-}
-
-void ifxmips_copy_to(struct map_info *map,
- unsigned long to,
- const void *from,
- ssize_t len)
-{
- unsigned char *p = (unsigned char *)from;
- unsigned char *to_8;
- unsigned long flags;
- spin_lock_irqsave(&ebu_lock, flags);
- to += (unsigned long) map->virt;
- to_8 = (unsigned char *)to;
- while (len--)
- *p++ = *to_8++;
- spin_unlock_irqrestore(&ebu_lock, flags);
-}
-
-static struct mtd_partition ifxmips_partitions[] = {
- {
- .name = "uboot",
- .offset = 0x00000000,
- .size = 0x00020000,
- },
- {
- .name = "uboot_env",
- .offset = 0x00020000,
- .size = 0x0,
- },
- {
- .name = "kernel",
- .offset = 0x0,
- .size = 0x0,
- },
- {
- .name = "rootfs",
- .offset = 0x0,
- .size = 0x0,
- },
- {
- .name = "board_config",
- .offset = 0x0,
- .size = 0x0,
- },
-};
-
-static struct mtd_partition ifxmips_meta_partition = {
- .name = "linux",
- .offset = 0x00030000,
- .size = 0x0,
-};
-
-static const char *part_probe_types[] = { "cmdlinepart", NULL };
-
-int find_uImage_size(unsigned long start_offset)
-{
- unsigned long magic;
- unsigned long temp;
- ifxmips_copy_from(&ifxmips_map, &magic, start_offset, 4);
- if (le32_to_cpu(magic) != 0x56190527) {
- printk(KERN_INFO "ifxmips_mtd: invalid magic (0x%08X) of kernel at 0x%08lx \n", le32_to_cpu(magic), start_offset);
- return 0;
- }
- ifxmips_copy_from(&ifxmips_map, &temp, start_offset + 12, 4);
- printk(KERN_INFO "ifxmips_mtd: kernel size is %ld \n", temp + 0x40);
- return temp + 0x40;
-}
-
-int find_brn_block(unsigned long start_offset)
-{
- unsigned char temp[9];
- ifxmips_copy_from(&ifxmips_map, &temp, start_offset, 8);
- temp[8] = '\0';
- printk(KERN_INFO "data in brn block %s\n", temp);
- if (memcmp(temp, "BRN-BOOT", 8) == 0)
- return 1;
- else
- return 0;
-}
-
-int detect_squashfs_partition(unsigned long start_offset)
-{
- unsigned long temp;
- ifxmips_copy_from(&ifxmips_map, &temp, start_offset, 4);
- return le32_to_cpu(temp) == SQUASHFS_MAGIC;
-}
-
-static int ifxmips_mtd_probe(struct platform_device *dev)
-{
- struct mtd_info *ifxmips_mtd = NULL;
- struct mtd_partition *parts = NULL;
- unsigned long uimage_size;
- int err, i;
- int kernel_part = 2, rootfs_part = 3;
- int num_parts = ARRAY_SIZE(ifxmips_partitions);
-
- ifxmips_w32(0x1d7ff, IFXMIPS_EBU_BUSCON0);
-
- ifxmips_map.read = ifxmips_read16;
- ifxmips_map.write = ifxmips_write16;
- ifxmips_map.copy_from = ifxmips_copy_from;
- ifxmips_map.copy_to = ifxmips_copy_to;
- ifxmips_map.phys = dev->resource->start;
- ifxmips_map.size = dev->resource->end - ifxmips_map.phys + 1;
- ifxmips_map.virt = ioremap_nocache(ifxmips_map.phys, ifxmips_map.size);
-
- if (!ifxmips_map.virt) {
- printk(KERN_WARNING "ifxmips_mtd: failed to ioremap!\n");
- return -EIO;
- }
-
- ifxmips_mtd = (struct mtd_info *) do_map_probe("cfi_probe", &ifxmips_map);
- if (!ifxmips_mtd) {
- iounmap(ifxmips_map.virt);
- printk(KERN_WARNING "ifxmips_mtd: probing failed\n");
- return -ENXIO;
- }
-
- ifxmips_mtd->owner = THIS_MODULE;
-
- err = parse_mtd_partitions(ifxmips_mtd, part_probe_types, &parts, 0);
- if (err > 0) {
- printk(KERN_INFO "ifxmips_mtd: found %d partitions from cmdline\n", err);
- num_parts = err;
- kernel_part = 0;
- rootfs_part = 0;
- for (i = 0; i < num_parts; i++) {
- if (strcmp(parts[i].name, "kernel") == 0)
- kernel_part = i;
- if (strcmp(parts[i].name, "rootfs") == 0)
- rootfs_part = i;
- }
- } else {
- /* if the flash is 64k sectors, the kernel will reside at 0xb0030000
- if the flash is 128k sectors, the kernel will reside at 0xb0040000 */
- ifxmips_partitions[1].size = ifxmips_mtd->erasesize;
- ifxmips_partitions[2].offset = ifxmips_partitions[1].offset + ifxmips_mtd->erasesize;
- parts = &ifxmips_partitions[0];
- }
-
- /* dynamic size detection only if rootfs-part follows kernel-part */
- if (kernel_part+1 == rootfs_part) {
- uimage_size = find_uImage_size(parts[kernel_part].offset);
-
- if (detect_squashfs_partition(parts[kernel_part].offset + uimage_size)) {
- printk(KERN_INFO "ifxmips_mtd: found a squashfs following the uImage\n");
- } else {
- uimage_size &= ~(ifxmips_mtd->erasesize -1);
- uimage_size += ifxmips_mtd->erasesize;
- }
-
- parts[kernel_part].size = uimage_size;
- parts[rootfs_part].offset = parts[kernel_part].offset + parts[kernel_part].size;
- parts[rootfs_part].size = ((ifxmips_mtd->size >> 20) * 1024 * 1024) - parts[rootfs_part].offset;
-
- ifxmips_meta_partition.offset = parts[kernel_part].offset;
- ifxmips_meta_partition.size = parts[kernel_part].size + parts[rootfs_part].size;
- }
-
- if (err <= 0) {
- if (ifxmips_has_brn_block()) {
- parts[3].size -= ifxmips_mtd->erasesize;
- parts[4].offset = ifxmips_mtd->size - ifxmips_mtd->erasesize;
- parts[4].size = ifxmips_mtd->erasesize;
- ifxmips_meta_partition.size -= ifxmips_mtd->erasesize;
- } else {
- num_parts--;
- }
- }
-
- add_mtd_partitions(ifxmips_mtd, parts, num_parts);
- add_mtd_partitions(ifxmips_mtd, &ifxmips_meta_partition, 1);
-
- printk(KERN_INFO "ifxmips_mtd: added %s flash with %dMB\n",
- ifxmips_map.name, ((int)ifxmips_mtd->size) >> 20);
- return 0;
-}
-
-static struct platform_driver ifxmips_mtd_driver = {
- .probe = ifxmips_mtd_probe,
- .driver = {
- .name = "ifxmips_mtd",
- .owner = THIS_MODULE,
- },
-};
-
-int __init init_ifxmips_mtd(void)
-{
- int ret = platform_driver_register(&ifxmips_mtd_driver);
- if (ret)
- printk(KERN_INFO "ifxmips_mtd: error registering platfom driver!");
- return ret;
-}
-
-static void __exit cleanup_ifxmips_mtd(void)
-{
- platform_driver_unregister(&ifxmips_mtd_driver);
-}
-
-module_init(init_ifxmips_mtd);
-module_exit(cleanup_ifxmips_mtd);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-MODULE_DESCRIPTION("MTD map driver for IFXMIPS boards");
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2005 Wu Qi Ming <Qi-Ming.Wu@infineon.com>
- * Copyright (C) 2008 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/errno.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/uaccess.h>
-#include <linux/in.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/phy.h>
-#include <linux/ip.h>
-#include <linux/tcp.h>
-#include <linux/skbuff.h>
-#include <linux/mm.h>
-#include <linux/platform_device.h>
-#include <linux/ethtool.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-
-#include <asm/checksum.h>
-
-#include <ifxmips.h>
-#include <ifxmips_dma.h>
-#include <ifxmips_pmu.h>
-#include <ifxmips_platform.h>
-
-struct ifxmips_mii_priv {
- struct net_device_stats stats;
- struct dma_device_info *dma_device;
- struct sk_buff *skb;
-
- struct mii_bus *mii_bus;
- struct phy_device *phydev;
- int oldlink, oldspeed, oldduplex;
-};
-
-static struct net_device *ifxmips_mii0_dev;
-static unsigned char mac_addr[MAX_ADDR_LEN];
-
-static int ifxmips_mdiobus_write(struct mii_bus *bus, int phy_addr,
- int phy_reg, u16 phy_data)
-{
- u32 val = MDIO_ACC_REQUEST |
- ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
- ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
- phy_data;
-
- while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST)
- ;
- ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
-
- return 0;
-}
-
-static int ifxmips_mdiobus_read(struct mii_bus *bus, int phy_addr, int phy_reg)
-{
- u32 val = MDIO_ACC_REQUEST | MDIO_ACC_READ |
- ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
- ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
-
- while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST)
- ;
- ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
- while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST)
- ;
- val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
- return val;
-}
-
-int ifxmips_ifxmips_mii_open(struct net_device *dev)
-{
- struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(dev);
- struct dma_device_info *dma_dev = priv->dma_device;
- int i;
-
- for (i = 0; i < dma_dev->max_rx_chan_num; i++) {
- if ((dma_dev->rx_chan[i])->control == IFXMIPS_DMA_CH_ON)
- (dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]);
- }
- netif_start_queue(dev);
- return 0;
-}
-
-int ifxmips_mii_release(struct net_device *dev)
-{
- struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(dev);
- struct dma_device_info *dma_dev = priv->dma_device;
- int i;
-
- for (i = 0; i < dma_dev->max_rx_chan_num; i++)
- dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]);
- netif_stop_queue(dev);
- return 0;
-}
-
-int ifxmips_mii_hw_receive(struct net_device *dev, struct dma_device_info *dma_dev)
-{
- struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(dev);
- unsigned char *buf = NULL;
- struct sk_buff *skb = NULL;
- int len = 0;
-
- len = dma_device_read(dma_dev, &buf, (void **)&skb);
-
- if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE) {
- printk(KERN_INFO "ifxmips_mii0: packet too large %d\n", len);
- goto ifxmips_mii_hw_receive_err_exit;
- }
-
- /* remove CRC */
- len -= 4;
- if (skb == NULL) {
- printk(KERN_INFO "ifxmips_mii0: cannot restore pointer\n");
- goto ifxmips_mii_hw_receive_err_exit;
- }
-
- if (len > (skb->end - skb->tail)) {
- printk(KERN_INFO "ifxmips_mii0: BUG, len:%d end:%p tail:%p\n",
- (len+4), skb->end, skb->tail);
- goto ifxmips_mii_hw_receive_err_exit;
- }
-
- skb_put(skb, len);
- skb->dev = dev;
- skb->protocol = eth_type_trans(skb, dev);
- netif_rx(skb);
-
- priv->stats.rx_packets++;
- priv->stats.rx_bytes += len;
- return 0;
-
-ifxmips_mii_hw_receive_err_exit:
- if (len == 0) {
- if (skb)
- dev_kfree_skb_any(skb);
- priv->stats.rx_errors++;
- priv->stats.rx_dropped++;
- return -EIO;
- } else {
- return len;
- }
-}
-
-int ifxmips_mii_hw_tx(char *buf, int len, struct net_device *dev)
-{
- int ret = 0;
- struct ifxmips_mii_priv *priv = netdev_priv(dev);
- struct dma_device_info *dma_dev = priv->dma_device;
- ret = dma_device_write(dma_dev, buf, len, priv->skb);
- return ret;
-}
-
-int ifxmips_mii_tx(struct sk_buff *skb, struct net_device *dev)
-{
- int len;
- char *data;
- struct ifxmips_mii_priv *priv = netdev_priv(dev);
- struct dma_device_info *dma_dev = priv->dma_device;
-
- len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
- data = skb->data;
- priv->skb = skb;
- dev->trans_start = jiffies;
- /* TODO: we got more than 1 dma channel,
- so we should do something intelligent here to select one */
- dma_dev->current_tx_chan = 0;
-
- wmb();
-
- if (ifxmips_mii_hw_tx(data, len, dev) != len) {
- dev_kfree_skb_any(skb);
- priv->stats.tx_errors++;
- priv->stats.tx_dropped++;
- } else {
- priv->stats.tx_packets++;
- priv->stats.tx_bytes += len;
- }
-
- return 0;
-}
-
-void ifxmips_mii_tx_timeout(struct net_device *dev)
-{
- int i;
- struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(dev);
-
- priv->stats.tx_errors++;
- for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
- priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]);
- netif_wake_queue(dev);
- return;
-}
-
-int dma_intr_handler(struct dma_device_info *dma_dev, int status)
-{
- int i;
-
- switch (status) {
- case RCV_INT:
- ifxmips_mii_hw_receive(ifxmips_mii0_dev, dma_dev);
- break;
-
- case TX_BUF_FULL_INT:
- printk(KERN_INFO "ifxmips_mii0: tx buffer full\n");
- netif_stop_queue(ifxmips_mii0_dev);
- for (i = 0; i < dma_dev->max_tx_chan_num; i++) {
- if ((dma_dev->tx_chan[i])->control == IFXMIPS_DMA_CH_ON)
- dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]);
- }
- break;
-
- case TRANSMIT_CPT_INT:
- for (i = 0; i < dma_dev->max_tx_chan_num; i++)
- dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]);
-
- netif_wake_queue(ifxmips_mii0_dev);
- break;
- }
-
- return 0;
-}
-
-unsigned char *ifxmips_etop_dma_buffer_alloc(int len, int *byte_offset, void **opt)
-{
- unsigned char *buffer = NULL;
- struct sk_buff *skb = NULL;
-
- skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE);
- if (skb == NULL)
- return NULL;
-
- buffer = (unsigned char *)(skb->data);
- skb_reserve(skb, 2);
- *(int *)opt = (int)skb;
- *byte_offset = 2;
-
- return buffer;
-}
-
-void ifxmips_etop_dma_buffer_free(unsigned char *dataptr, void *opt)
-{
- struct sk_buff *skb = NULL;
-
- if (opt == NULL) {
- kfree(dataptr);
- } else {
- skb = (struct sk_buff *)opt;
- dev_kfree_skb_any(skb);
- }
-}
-
-static void
-ifxmips_adjust_link(struct net_device *dev)
-{
- struct ifxmips_mii_priv *priv = netdev_priv(dev);
- struct phy_device *phydev = priv->phydev;
- int new_state = 0;
-
- /* Did anything change? */
- if (priv->oldlink != phydev->link ||
- priv->oldduplex != phydev->duplex ||
- priv->oldspeed != phydev->speed) {
- /* Yes, so update status and mark as changed */
- new_state = 1;
- priv->oldduplex = phydev->duplex;
- priv->oldspeed = phydev->speed;
- priv->oldlink = phydev->link;
- }
-
- /* If link status changed, show new status */
- if (new_state)
- phy_print_status(phydev);
-}
-
-static int mii_probe(struct net_device *dev)
-{
- struct ifxmips_mii_priv *priv = netdev_priv(dev);
- struct phy_device *phydev = NULL;
- int phy_addr;
-
- priv->oldlink = 0;
- priv->oldspeed = 0;
- priv->oldduplex = -1;
-
- /* find the first (lowest address) PHY on the current MAC's MII bus */
- for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
- if (priv->mii_bus->phy_map[phy_addr]) {
- phydev = priv->mii_bus->phy_map[phy_addr];
- break; /* break out with first one found */
- }
- }
-
- if (!phydev) {
- printk (KERN_ERR "%s: no PHY found\n", dev->name);
- return -ENODEV;
- }
-
- /* now we are supposed to have a proper phydev, to attach to... */
- BUG_ON(!phydev);
- BUG_ON(phydev->attached_dev);
-
- phydev = phy_connect(dev, dev_name(&phydev->dev), &ifxmips_adjust_link,
- 0, PHY_INTERFACE_MODE_MII);
-
- if (IS_ERR(phydev)) {
- printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
- return PTR_ERR(phydev);
- }
-
- /* mask with MAC supported features */
- phydev->supported &= (SUPPORTED_10baseT_Half
- | SUPPORTED_10baseT_Full
- | SUPPORTED_100baseT_Half
- | SUPPORTED_100baseT_Full
- | SUPPORTED_Autoneg
- /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
- | SUPPORTED_MII
- | SUPPORTED_TP);
-
- phydev->advertising = phydev->supported;
-
- priv->phydev = phydev;
-
- printk(KERN_INFO "%s: attached PHY driver [%s] "
- "(mii_bus:phy_addr=%s, irq=%d)\n",
- dev->name, phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
-
- return 0;
-}
-
-
-static int ifxmips_mii_dev_init(struct net_device *dev)
-{
- int i;
- struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(dev);
- ether_setup(dev);
- dev->watchdog_timeo = 10 * HZ;
- dev->mtu = 1500;
- memset(priv, 0, sizeof(struct ifxmips_mii_priv));
- priv->dma_device = dma_device_reserve("PPE");
- if (!priv->dma_device) {
- BUG();
- return -ENODEV;
- }
- priv->dma_device->buffer_alloc = &ifxmips_etop_dma_buffer_alloc;
- priv->dma_device->buffer_free = &ifxmips_etop_dma_buffer_free;
- priv->dma_device->intr_handler = &dma_intr_handler;
- priv->dma_device->max_rx_chan_num = 4;
-
- for (i = 0; i < priv->dma_device->max_rx_chan_num; i++) {
- priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE;
- priv->dma_device->rx_chan[i]->control = IFXMIPS_DMA_CH_ON;
- }
-
- for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
- if (i == 0)
- priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_ON;
- else
- priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_OFF;
-
- dma_device_register(priv->dma_device);
-
- printk(KERN_INFO "%s: using mac=", dev->name);
- for (i = 0; i < 6; i++) {
- dev->dev_addr[i] = mac_addr[i];
- printk("%02X%c", dev->dev_addr[i], (i == 5) ? ('\n') : (':'));
- }
-
- priv->mii_bus = mdiobus_alloc();
- if (priv->mii_bus == NULL)
- return -ENOMEM;
-
- priv->mii_bus->priv = dev;
- priv->mii_bus->read = ifxmips_mdiobus_read;
- priv->mii_bus->write = ifxmips_mdiobus_write;
- priv->mii_bus->name = "ifxmips_mii";
- snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
- priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
- for(i = 0; i < PHY_MAX_ADDR; ++i)
- priv->mii_bus->irq[i] = PHY_POLL;
-
- mdiobus_register(priv->mii_bus);
-
- return mii_probe(dev);
-}
-
-static void ifxmips_mii_chip_init(int mode)
-{
- ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
- ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_PPE);
-
- if (mode == REV_MII_MODE)
- ifxmips_w32_mask(PPE32_MII_MASK, PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
- else if (mode == MII_MODE)
- ifxmips_w32_mask(PPE32_MII_MASK, PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
- ifxmips_w32(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
- ifxmips_w32(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
- wmb();
-}
-
-static const struct net_device_ops ifxmips_eth_netdev_ops = {
- .ndo_init = ifxmips_mii_dev_init,
- .ndo_open = ifxmips_ifxmips_mii_open,
- .ndo_stop = ifxmips_mii_release,
- .ndo_start_xmit = ifxmips_mii_tx,
- .ndo_tx_timeout = ifxmips_mii_tx_timeout,
- .ndo_change_mtu = eth_change_mtu,
- .ndo_set_mac_address = eth_mac_addr,
- .ndo_validate_addr = eth_validate_addr,
-};
-
-static int
-ifxmips_mii_probe(struct platform_device *dev)
-{
- int result = 0;
- struct ifxmips_eth_data *eth = (struct ifxmips_eth_data*)dev->dev.platform_data;
- ifxmips_mii0_dev = alloc_etherdev(sizeof(struct ifxmips_mii_priv));
- ifxmips_mii0_dev->netdev_ops = &ifxmips_eth_netdev_ops;
- memcpy(mac_addr, eth->mac, 6);
- strcpy(ifxmips_mii0_dev->name, "eth%d");
- ifxmips_mii_chip_init(eth->mii_mode);
- result = register_netdev(ifxmips_mii0_dev);
- if (result) {
- printk(KERN_INFO "ifxmips_mii0: error %i registering device \"%s\"\n", result, ifxmips_mii0_dev->name);
- goto out;
- }
-
- printk(KERN_INFO "ifxmips_mii0: driver loaded!\n");
-
-out:
- return result;
-}
-
-static int ifxmips_mii_remove(struct platform_device *dev)
-{
- struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(ifxmips_mii0_dev);
-
- printk(KERN_INFO "ifxmips_mii0: ifxmips_mii0 cleanup\n");
-
- dma_device_unregister(priv->dma_device);
- dma_device_release(priv->dma_device);
- kfree(priv->dma_device);
- unregister_netdev(ifxmips_mii0_dev);
- return 0;
-}
-
-static struct platform_driver ifxmips_mii_driver = {
- .probe = ifxmips_mii_probe,
- .remove = ifxmips_mii_remove,
- .driver = {
- .name = "ifxmips_mii0",
- .owner = THIS_MODULE,
- },
-};
-
-int __init ifxmips_mii_init(void)
-{
- int ret = platform_driver_register(&ifxmips_mii_driver);
- if (ret)
- printk(KERN_INFO "ifxmips_mii0: Error registering platfom driver!");
- return ret;
-}
-
-static void __exit ifxmips_mii_cleanup(void)
-{
- platform_driver_unregister(&ifxmips_mii_driver);
-}
-
-module_init(ifxmips_mii_init);
-module_exit(ifxmips_mii_cleanup);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-MODULE_DESCRIPTION("ethernet driver for IFXMIPS boards");
+++ /dev/null
-/*
- * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Copyright (C) 2004 Infineon IFAP DC COM CPE
- * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/tty.h>
-#include <linux/tty_flip.h>
-#include <linux/major.h>
-#include <linux/string.h>
-#include <linux/fcntl.h>
-#include <linux/ptrace.h>
-#include <linux/ioport.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/circ_buf.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/console.h>
-#include <linux/sysrq.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/uaccess.h>
-#include <linux/bitops.h>
-
-#include <asm/system.h>
-
-#include <ifxmips.h>
-#include <ifxmips_irq.h>
-
-#define PORT_IFXMIPSASC 111
-
-#include <linux/serial_core.h>
-
-#define UART_DUMMY_UER_RX 1
-
-static void ifxmipsasc_tx_chars(struct uart_port *port);
-extern void prom_printf(const char *fmt, ...);
-static struct uart_port ifxmipsasc_port[2];
-static struct uart_driver ifxmipsasc_reg;
-extern unsigned int ifxmips_get_fpi_hz(void);
-
-static void ifxmipsasc_stop_tx(struct uart_port *port)
-{
- return;
-}
-
-static void ifxmipsasc_start_tx(struct uart_port *port)
-{
- unsigned long flags;
- local_irq_save(flags);
- ifxmipsasc_tx_chars(port);
- local_irq_restore(flags);
- return;
-}
-
-static void ifxmipsasc_stop_rx(struct uart_port *port)
-{
- ifxmips_w32(ASCWHBSTATE_CLRREN, port->membase + IFXMIPS_ASC_WHBSTATE);
-}
-
-static void ifxmipsasc_enable_ms(struct uart_port *port)
-{
-}
-
-#include <linux/version.h>
-
-static void ifxmipsasc_rx_chars(struct uart_port *port)
-{
- struct tty_struct *tty = port->state->port.tty;
- unsigned int ch = 0, rsr = 0, fifocnt;
-
- fifocnt = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
- while (fifocnt--) {
- u8 flag = TTY_NORMAL;
- ch = ifxmips_r32(port->membase + IFXMIPS_ASC_RBUF);
- rsr = (ifxmips_r32(port->membase + IFXMIPS_ASC_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
- tty_flip_buffer_push(tty);
- port->icount.rx++;
-
- /*
- * Note that the error handling code is
- * out of the main execution path
- */
- if (rsr & ASCSTATE_ANY) {
- if (rsr & ASCSTATE_PE) {
- port->icount.parity++;
- ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE, port->membase + IFXMIPS_ASC_WHBSTATE);
- } else if (rsr & ASCSTATE_FE) {
- port->icount.frame++;
- ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRFE, port->membase + IFXMIPS_ASC_WHBSTATE);
- }
- if (rsr & ASCSTATE_ROE) {
- port->icount.overrun++;
- ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE);
- }
-
- rsr &= port->read_status_mask;
-
- if (rsr & ASCSTATE_PE)
- flag = TTY_PARITY;
- else if (rsr & ASCSTATE_FE)
- flag = TTY_FRAME;
- }
-
- if ((rsr & port->ignore_status_mask) == 0)
- tty_insert_flip_char(tty, ch, flag);
-
- if (rsr & ASCSTATE_ROE)
- /*
- * Overrun is special, since it's reported
- * immediately, and doesn't affect the current
- * character
- */
- tty_insert_flip_char(tty, 0, TTY_OVERRUN);
- }
- if (ch != 0)
- tty_flip_buffer_push(tty);
- return;
-}
-
-
-static void ifxmipsasc_tx_chars(struct uart_port *port)
-{
- struct circ_buf *xmit = &port->state->xmit;
- if (uart_tx_stopped(port)) {
- ifxmipsasc_stop_tx(port);
- return;
- }
-
- while (((ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK)
- >> ASCFSTAT_TXFFLOFF) != TXFIFO_FULL) {
- if (port->x_char) {
- ifxmips_w32(port->x_char, port->membase + IFXMIPS_ASC_TBUF);
- port->icount.tx++;
- port->x_char = 0;
- continue;
- }
-
- if (uart_circ_empty(xmit))
- break;
-
- ifxmips_w32(port->state->xmit.buf[port->state->xmit.tail], port->membase + IFXMIPS_ASC_TBUF);
- xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
- port->icount.tx++;
- }
-
- if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
- uart_write_wakeup(port);
-}
-
-static irqreturn_t ifxmipsasc_tx_int(int irq, void *_port)
-{
- struct uart_port *port = (struct uart_port *)_port;
- ifxmips_w32(ASC_IRNCR_TIR, port->membase + IFXMIPS_ASC_IRNCR);
- ifxmipsasc_start_tx(port);
- ifxmips_mask_and_ack_irq(irq);
- return IRQ_HANDLED;
-}
-
-static irqreturn_t ifxmipsasc_er_int(int irq, void *_port)
-{
- struct uart_port *port = (struct uart_port *)_port;
- /* clear any pending interrupts */
- ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE |
- ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE);
- return IRQ_HANDLED;
-}
-
-static irqreturn_t ifxmipsasc_rx_int(int irq, void *_port)
-{
- struct uart_port *port = (struct uart_port *)_port;
- ifxmips_w32(ASC_IRNCR_RIR, port->membase + IFXMIPS_ASC_IRNCR);
- ifxmipsasc_rx_chars((struct uart_port *)port);
- ifxmips_mask_and_ack_irq(irq);
- return IRQ_HANDLED;
-}
-
-static unsigned int ifxmipsasc_tx_empty(struct uart_port *port)
-{
- int status;
- status = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
- return status ? 0 : TIOCSER_TEMT;
-}
-
-static unsigned int ifxmipsasc_get_mctrl(struct uart_port *port)
-{
- return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
-}
-
-static void ifxmipsasc_set_mctrl(struct uart_port *port, u_int mctrl)
-{
-}
-
-static void ifxmipsasc_break_ctl(struct uart_port *port, int break_state)
-{
-}
-
-static int ifxmipsasc_startup(struct uart_port *port)
-{
- int retval;
-
- port->uartclk = ifxmips_get_fpi_hz();
-
- ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~IFXMIPS_ASC_CLC_DISS, port->membase + IFXMIPS_ASC_CLC);
- ifxmips_w32(((ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~ASCCLC_RMCMASK)) | (1 << ASCCLC_RMCOFFSET), port->membase + IFXMIPS_ASC_CLC);
- ifxmips_w32(0, port->membase + IFXMIPS_ASC_PISEL);
- ifxmips_w32(((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
- ifxmips_w32(((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
- wmb();
- ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN, port->membase + IFXMIPS_ASC_CON);
-
- retval = request_irq(port->irq, ifxmipsasc_tx_int, IRQF_DISABLED, "asc_tx", port);
- if (retval) {
- printk(KERN_ERR "failed to request ifxmipsasc_tx_int\n");
- return retval;
- }
-
- retval = request_irq(port->irq + 2, ifxmipsasc_rx_int, IRQF_DISABLED, "asc_rx", port);
- if (retval) {
- printk(KERN_ERR "failed to request ifxmipsasc_rx_int\n");
- goto err1;
- }
-
- retval = request_irq(port->irq + 3, ifxmipsasc_er_int, IRQF_DISABLED, "asc_er", port);
- if (retval) {
- printk(KERN_ERR "failed to request ifxmipsasc_er_int\n");
- goto err2;
- }
-
- ifxmips_w32(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX, port->membase + IFXMIPS_ASC_IRNREN);
- return 0;
-
-err2:
- free_irq(port->irq + 2, port);
-err1:
- free_irq(port->irq, port);
- return retval;
-}
-
-static void ifxmipsasc_shutdown(struct uart_port *port)
-{
- free_irq(port->irq, port);
- free_irq(port->irq + 2, port);
- free_irq(port->irq + 3, port);
-
- ifxmips_w32(0, port->membase + IFXMIPS_ASC_CON);
- ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
- ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) & ~ASCRXFCON_RXFEN, port->membase + IFXMIPS_ASC_RXFCON);
- ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
- ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) & ~ASCTXFCON_TXFEN, port->membase + IFXMIPS_ASC_TXFCON);
-}
-
-static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
-{
- unsigned int cflag;
- unsigned int iflag;
- unsigned int quot;
- unsigned int baud;
- unsigned int con = 0;
- unsigned long flags;
-
- cflag = new->c_cflag;
- iflag = new->c_iflag;
-
- switch (cflag & CSIZE) {
- case CS7:
- con = ASCCON_M_7ASYNC;
- break;
-
- case CS5:
- case CS6:
- default:
- con = ASCCON_M_8ASYNC;
- break;
- }
-
- if (cflag & CSTOPB)
- con |= ASCCON_STP;
-
- if (cflag & PARENB) {
- if (!(cflag & PARODD))
- con &= ~ASCCON_ODD;
- else
- con |= ASCCON_ODD;
- }
-
- port->read_status_mask = ASCSTATE_ROE;
- if (iflag & INPCK)
- port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
-
- port->ignore_status_mask = 0;
- if (iflag & IGNPAR)
- port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
-
- if (iflag & IGNBRK) {
- /*
- * If we're ignoring parity and break indicators,
- * ignore overruns too (for real raw support).
- */
- if (iflag & IGNPAR)
- port->ignore_status_mask |= ASCSTATE_ROE;
- }
-
- if ((cflag & CREAD) == 0)
- port->ignore_status_mask |= UART_DUMMY_UER_RX;
-
- /* set error signals - framing, parity and overrun, enable receiver */
- con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
-
- local_irq_save(flags);
-
- /* set up CON */
- ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | con, port->membase + IFXMIPS_ASC_CON);
-
- /* Set baud rate - take a divider of 2 into account */
- baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
- quot = uart_get_divisor(port, baud);
- quot = quot / 2 - 1;
-
- /* disable the baudrate generator */
- ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_R, port->membase + IFXMIPS_ASC_CON);
-
- /* make sure the fractional divider is off */
- ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_FDE, port->membase + IFXMIPS_ASC_CON);
-
- /* set up to use divisor of 2 */
- ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_BRS, port->membase + IFXMIPS_ASC_CON);
-
- /* now we can write the new baudrate into the register */
- ifxmips_w32(quot, port->membase + IFXMIPS_ASC_BG);
-
- /* turn the baudrate generator back on */
- ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_R, port->membase + IFXMIPS_ASC_CON);
-
- /* enable rx */
- ifxmips_w32(ASCWHBSTATE_SETREN, port->membase + IFXMIPS_ASC_WHBSTATE);
-
- local_irq_restore(flags);
-}
-
-static const char *ifxmipsasc_type(struct uart_port *port)
-{
- if (port->type == PORT_IFXMIPSASC) {
- if (port->membase == (void *)IFXMIPS_ASC_BASE_ADDR)
- return "asc0";
- else
- return "asc1";
- } else {
- return NULL;
- }
-}
-
-static void ifxmipsasc_release_port(struct uart_port *port)
-{
-}
-
-static int ifxmipsasc_request_port(struct uart_port *port)
-{
- return 0;
-}
-
-static void ifxmipsasc_config_port(struct uart_port *port, int flags)
-{
- if (flags & UART_CONFIG_TYPE) {
- port->type = PORT_IFXMIPSASC;
- ifxmipsasc_request_port(port);
- }
-}
-
-static int ifxmipsasc_verify_port(struct uart_port *port, struct serial_struct *ser)
-{
- int ret = 0;
- if (ser->type != PORT_UNKNOWN && ser->type != PORT_IFXMIPSASC)
- ret = -EINVAL;
- if (ser->irq < 0 || ser->irq >= NR_IRQS)
- ret = -EINVAL;
- if (ser->baud_base < 9600)
- ret = -EINVAL;
- return ret;
-}
-
-static struct uart_ops ifxmipsasc_pops = {
- .tx_empty = ifxmipsasc_tx_empty,
- .set_mctrl = ifxmipsasc_set_mctrl,
- .get_mctrl = ifxmipsasc_get_mctrl,
- .stop_tx = ifxmipsasc_stop_tx,
- .start_tx = ifxmipsasc_start_tx,
- .stop_rx = ifxmipsasc_stop_rx,
- .enable_ms = ifxmipsasc_enable_ms,
- .break_ctl = ifxmipsasc_break_ctl,
- .startup = ifxmipsasc_startup,
- .shutdown = ifxmipsasc_shutdown,
- .set_termios = ifxmipsasc_set_termios,
- .type = ifxmipsasc_type,
- .release_port = ifxmipsasc_release_port,
- .request_port = ifxmipsasc_request_port,
- .config_port = ifxmipsasc_config_port,
- .verify_port = ifxmipsasc_verify_port,
-};
-
-static struct uart_port ifxmipsasc_port[2] = {
- {
- .membase = (void *)IFXMIPS_ASC_BASE_ADDR,
- .mapbase = IFXMIPS_ASC_BASE_ADDR,
- .iotype = SERIAL_IO_MEM,
- .irq = IFXMIPSASC_TIR(0),
- .uartclk = 0,
- .fifosize = 16,
- .type = PORT_IFXMIPSASC,
- .ops = &ifxmipsasc_pops,
- .flags = ASYNC_BOOT_AUTOCONF,
- .line = 0
- }, {
- .membase = (void *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF),
- .mapbase = IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF,
- .iotype = SERIAL_IO_MEM,
- .irq = IFXMIPSASC_TIR(1),
- .uartclk = 0,
- .fifosize = 16,
- .type = PORT_IFXMIPSASC,
- .ops = &ifxmipsasc_pops,
- .flags = ASYNC_BOOT_AUTOCONF,
- .line = 1
- }
-};
-
-static void ifxmipsasc_console_write(struct console *co, const char *s, u_int count)
-{
- int port = co->index;
- int i, fifocnt;
- unsigned long flags;
- local_irq_save(flags);
- for (i = 0; i < count; i++) {
- do {
- fifocnt = (ifxmips_r32((u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
- >> ASCFSTAT_TXFFLOFF;
- } while (fifocnt == TXFIFO_FULL);
-
- if (s[i] == '\0')
- break;
-
- if (s[i] == '\n') {
- ifxmips_w32('\r', (u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
- do {
- fifocnt = (ifxmips_r32((u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
- >> ASCFSTAT_TXFFLOFF;
- } while (fifocnt == TXFIFO_FULL);
- }
- ifxmips_w32(s[i], (u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
- }
-
- local_irq_restore(flags);
-}
-
-static int __init ifxmipsasc_console_setup(struct console *co, char *options)
-{
- int port = co->index;
- int baud = 115200;
- int bits = 8;
- int parity = 'n';
- int flow = 'n';
- ifxmipsasc_port[port].uartclk = ifxmips_get_fpi_hz();
- ifxmipsasc_port[port].type = PORT_IFXMIPSASC;
- if (options)
- uart_parse_options(options, &baud, &parity, &bits, &flow);
- return uart_set_options(&ifxmipsasc_port[port], co, baud, parity, bits, flow);
-}
-
-static struct console ifxmipsasc_console[2] =
-{
- {
- .name = "ttyS",
- .write = ifxmipsasc_console_write,
- .device = uart_console_device,
- .setup = ifxmipsasc_console_setup,
- .flags = CON_PRINTBUFFER,
- .index = 0,
- .data = &ifxmipsasc_reg,
- }, {
- .name = "ttyS",
- .write = ifxmipsasc_console_write,
- .device = uart_console_device,
- .setup = ifxmipsasc_console_setup,
- .flags = CON_PRINTBUFFER,
- .index = 1,
- .data = &ifxmipsasc_reg,
- }
-};
-
-static int __init ifxmipsasc_console_init(void)
-{
- register_console(&ifxmipsasc_console[0]);
- register_console(&ifxmipsasc_console[1]);
- return 0;
-}
-console_initcall(ifxmipsasc_console_init);
-
-static struct uart_driver ifxmipsasc_reg = {
- .owner = THIS_MODULE,
- .driver_name = "serial",
- .dev_name = "ttyS",
- .major = TTY_MAJOR,
- .minor = 64,
- .nr = 2,
- .cons = &ifxmipsasc_console[1],
-};
-
-int __init ifxmipsasc_init(void)
-{
- int ret;
- uart_register_driver(&ifxmipsasc_reg);
- ret = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[0]);
- ret = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[1]);
- return 0;
-}
-
-void __exit ifxmipsasc_exit(void)
-{
- uart_unregister_driver(&ifxmipsasc_reg);
-}
-
-module_init(ifxmipsasc_init);
-module_exit(ifxmipsasc_exit);
-
-MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-MODULE_DESCRIPTION("MIPS IFXMips serial port driver");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Copyright (C) 2008 John Crispin <blogic@openwrt.org>
- * Based on EP93xx wdt driver
- */
-
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/miscdevice.h>
-#include <linux/watchdog.h>
-#include <linux/platform_device.h>
-#include <linux/uaccess.h>
-
-#include <ifxmips.h>
-#include <ifxmips_cgu.h>
-
-#define IFXMIPS_WDT_PW1 0x00BE0000
-#define IFXMIPS_WDT_PW2 0x00DC0000
-
-#ifndef CONFIG_WATCHDOG_NOWAYOUT
-static int wdt_ok_to_close;
-#endif
-
-static int wdt_timeout = 30;
-
-int ifxmips_wdt_enable(unsigned int timeout)
-{
- u32 fpi;
- fpi = cgu_get_io_region_clock();
- ifxmips_w32(IFXMIPS_WDT_PW1, IFXMIPS_BIU_WDT_CR);
- ifxmips_w32(IFXMIPS_WDT_PW2 |
- (0x3 << 26) | /* PWL */
- (0x3 << 24) | /* CLKDIV */
- (0x1 << 31) | /* enable */
- ((timeout * (fpi / 0x40000)) + 0x1000), /* reload */
- IFXMIPS_BIU_WDT_CR);
- return 0;
-}
-
-void ifxmips_wdt_disable(void)
-{
-#ifndef CONFIG_WATCHDOG_NOWAYOUT
- wdt_ok_to_close = 0;
-#endif
- ifxmips_w32(IFXMIPS_WDT_PW1, IFXMIPS_BIU_WDT_CR);
- ifxmips_w32(IFXMIPS_WDT_PW2, IFXMIPS_BIU_WDT_CR);
-}
-
-static ssize_t ifxmips_wdt_write(struct file *file, const char __user *data,
- size_t len, loff_t *ppos)
-{
- size_t i;
-
- if (!len)
- return 0;
-
-#ifndef CONFIG_WATCHDOG_NOWAYOUT
- for (i = 0; i != len; i++) {
- char c;
- if (get_user(c, data + i))
- return -EFAULT;
- if (c == 'V')
- wdt_ok_to_close = 1;
- }
-#endif
- ifxmips_wdt_enable(wdt_timeout);
- return len;
-}
-
-static struct watchdog_info ident = {
- .options = WDIOF_MAGICCLOSE,
- .identity = "ifxmips Watchdog",
-};
-
-static int ifxmips_wdt_ioctl(struct inode *inode, struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- int ret = -ENOTTY;
-
- switch (cmd) {
- case WDIOC_GETSUPPORT:
- ret = copy_to_user((struct watchdog_info __user *)arg, &ident,
- sizeof(ident)) ? -EFAULT : 0;
- break;
-
- case WDIOC_GETTIMEOUT:
- ret = put_user(wdt_timeout, (int __user *)arg);
- break;
-
- case WDIOC_SETTIMEOUT:
- ret = get_user(wdt_timeout, (int __user *)arg);
- break;
-
- case WDIOC_KEEPALIVE:
- ifxmips_wdt_enable(wdt_timeout);
- ret = 0;
- break;
- }
- return ret;
-}
-
-static int ifxmips_wdt_open(struct inode *inode, struct file *file)
-{
- ifxmips_wdt_enable(wdt_timeout);
- return nonseekable_open(inode, file);
-}
-
-static int ifxmips_wdt_release(struct inode *inode, struct file *file)
-{
-#ifndef CONFIG_WATCHDOG_NOWAYOUT
- if (wdt_ok_to_close)
- ifxmips_wdt_disable();
- else
-#endif
- printk(KERN_ERR "ifxmips_wdt: watchdog closed without warning,"
- " rebooting system\n");
- return 0;
-}
-
-static const struct file_operations ifxmips_wdt_fops = {
- .owner = THIS_MODULE,
- .write = ifxmips_wdt_write,
- .ioctl = ifxmips_wdt_ioctl,
- .open = ifxmips_wdt_open,
- .release = ifxmips_wdt_release,
-};
-
-static struct miscdevice ifxmips_wdt_miscdev = {
- .minor = WATCHDOG_MINOR,
- .name = "watchdog",
- .fops = &ifxmips_wdt_fops,
-};
-
-static int ifxmips_wdt_probe(struct platform_device *dev)
-{
- int err;
- err = misc_register(&ifxmips_wdt_miscdev);
- if (err)
- printk(KERN_INFO "ifxmips_wdt: error creating device\n");
- else
- printk(KERN_INFO "ifxmips_wdt: loaded\n");
- return err;
-}
-
-static int ifxmips_wdt_remove(struct platform_device *dev)
-{
- ifxmips_wdt_disable();
- misc_deregister(&ifxmips_wdt_miscdev);
- return 0;
-}
-
-
-static struct platform_driver ifxmips_wdt_driver = {
- .probe = ifxmips_wdt_probe,
- .remove = ifxmips_wdt_remove,
- .driver = {
- .name = "ifxmips_wdt",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init init_ifxmips_wdt(void)
-{
- int ret = platform_driver_register(&ifxmips_wdt_driver);
- if (ret)
- printk(KERN_INFO "ifxmips_wdt: error registering platfom driver!");
- return ret;
-}
-
-static void __exit exit_ifxmips_wdt(void)
-{
- platform_driver_unregister(&ifxmips_wdt_driver);
-}
-
-module_init(init_ifxmips_wdt);
-module_exit(exit_ifxmips_wdt);
-
-MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-MODULE_DESCRIPTION("ifxmips Watchdog");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
+++ /dev/null
-#
-# Copyright (C) 2006-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-define Image/BuildKernel
- $(STAGING_DIR_HOST)/bin/lzma e $(KDIR)/vmlinux $(KDIR)/vmlinux.lzma
- mkimage -A mips -O linux -T kernel -a 0x80002000 -C lzma -e \
- 0x80002000 \
- -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \
- -d $(KDIR)/vmlinux.lzma $(KDIR)/uImage
-
- cp $(KDIR)/uImage $(BIN_DIR)/$(IMG_PREFIX)-uImage
-endef
-
-define Image/Build/squashfs
- cat $(KDIR)/uImage $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(1).image
- $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(1).image)
-endef
-
-define Image/Build/jffs2-64k
- dd if=$(KDIR)/uImage of=$(KDIR)/uImage.$(1) bs=64k conv=sync
- cat $(KDIR)/uImage.$(1) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(1).image
-endef
-
-define Image/Build/jffs2-128k
- dd if=$(KDIR)/uImage of=$(KDIR)/uImage.$(1) bs=128k conv=sync
- cat $(KDIR)/uImage.$(1) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(1).image
-endef
-
-define Image/Build
- $(call Image/Build/$(1),$(1))
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
---- a/arch/mips/kernel/traps.c
-+++ b/arch/mips/kernel/traps.c
-@@ -1496,7 +1496,18 @@ void __cpuinit per_cpu_trap_init(void)
- if (cpu_has_mips_r2) {
- cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
- cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
-+
-+ if (!cp0_compare_irq)
-+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
-+
- cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
-+
-+ if (!cp0_perfcount_irq)
-+ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
-+
-+ if (arch_fixup_c0_irqs)
-+ arch_fixup_c0_irqs();
-+
- if (cp0_perfcount_irq == cp0_compare_irq)
- cp0_perfcount_irq = -1;
- } else {
---- a/arch/mips/include/asm/irq.h
-+++ b/arch/mips/include/asm/irq.h
-@@ -133,9 +133,11 @@ extern void free_irqno(unsigned int irq)
- * IE7. Since R2 their number has to be read from the c0_intctl register.
- */
- #define CP0_LEGACY_COMPARE_IRQ 7
-+#define CP0_LEGACY_PERFCNT_IRQ 7
-
- extern int cp0_compare_irq;
- extern int cp0_compare_irq_shift;
- extern int cp0_perfcount_irq;
-+extern void __weak arch_fixup_c0_irqs(void);
-
- #endif /* _ASM_IRQ_H */
+++ /dev/null
---- a/arch/mips/kernel/cevt-r4k.c
-+++ b/arch/mips/kernel/cevt-r4k.c
-@@ -22,6 +22,22 @@
-
- #ifndef CONFIG_MIPS_MT_SMTC
-
-+/*
-+ * Compare interrupt can be routed and latched outside the core,
-+ * so a single execution hazard barrier may not be enough to give
-+ * it time to clear as seen in the Cause register. 4 time the
-+ * pipeline depth seems reasonably conservative, and empirically
-+ * works better in configurations with high CPU/bus clock ratios.
-+ */
-+
-+#define compare_change_hazard() \
-+ do { \
-+ irq_disable_hazard(); \
-+ irq_disable_hazard(); \
-+ irq_disable_hazard(); \
-+ irq_disable_hazard(); \
-+ } while (0)
-+
- static int mips_next_event(unsigned long delta,
- struct clock_event_device *evt)
- {
-@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long
- cnt = read_c0_count();
- cnt += delta;
- write_c0_compare(cnt);
-+ compare_change_hazard();
- res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
- return res;
- }
+++ /dev/null
---- a/kernel/irq/chip.c
-+++ b/kernel/irq/chip.c
-@@ -650,6 +650,9 @@ handle_percpu_irq(unsigned int irq, stru
-
- kstat_incr_irqs_this_cpu(irq, desc);
-
-+ if (unlikely(!desc->action || (desc->status & IRQ_DISABLED)))
-+ return;
-+
- if (desc->chip->ack)
- desc->chip->ack(irq);
-
+++ /dev/null
-Index: linux-2.6.35.4/arch/mips/Kconfig
-===================================================================
---- linux-2.6.35.4.orig/arch/mips/Kconfig 2010-09-23 20:41:50.000000000 +0200
-+++ linux-2.6.35.4/arch/mips/Kconfig 2010-09-23 20:41:52.000000000 +0200
-@@ -139,6 +139,9 @@
-
- otherwise choose R3000.
-
-+config IFXMIPS
-+ bool "Infineon MIPS"
-+
- config MACH_JAZZ
- bool "Jazz family of machines"
- select ARC
-@@ -695,6 +698,7 @@
- source "arch/mips/vr41xx/Kconfig"
- source "arch/mips/cavium-octeon/Kconfig"
- source "arch/mips/loongson/Kconfig"
-+source "arch/mips/ifxmips/Kconfig"
-
- endmenu
-
-Index: linux-2.6.35.4/arch/mips/Makefile
-===================================================================
---- linux-2.6.35.4.orig/arch/mips/Makefile 2010-09-23 20:41:50.000000000 +0200
-+++ linux-2.6.35.4/arch/mips/Makefile 2010-09-23 22:41:58.000000000 +0200
-@@ -339,6 +339,22 @@
- load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
-
- #
-+# Infineon IFXMIPS
-+#
-+core-$(CONFIG_IFXMIPS) += arch/mips/ifxmips/common/
-+cflags-$(CONFIG_IFXMIPS) += -I$(srctree)/arch/mips/include/asm/mach-ifxmips
-+
-+core-$(CONFIG_IFXMIPS_DANUBE) += arch/mips/ifxmips/danube/
-+cflags-$(CONFIG_IFXMIPS_DANUBE) += -I$(srctree)/arch/mips/include/asm/mach-ifxmips/danube/
-+load-$(CONFIG_IFXMIPS_DANUBE) += 0xffffffff80002000
-+
-+core-$(CONFIG_IFXMIPS_AR9) += arch/mips/ifxmips/ar9/
-+cflags-$(CONFIG_IFXMIPS_AR9) += -I$(srctree)/arch/mips/include/asm/mach-ifxmips/ar9/
-+load-$(CONFIG_IFXMIPS_AR9) += 0xffffffff80002000
-+
-+core-$(CONFIG_IFXMIPS_COMPAT) += arch/mips/ifxmips/compat/
-+
-+#
- # DECstation family
- #
- core-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/
-Index: linux-2.6.35.4/arch/mips/pci/Makefile
-===================================================================
---- linux-2.6.35.4.orig/arch/mips/pci/Makefile 2010-08-27 01:47:12.000000000 +0200
-+++ linux-2.6.35.4/arch/mips/pci/Makefile 2010-09-23 20:41:52.000000000 +0200
-@@ -55,7 +55,7 @@
- obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
- obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
- obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
--
-+obj-$(CONFIG_IFXMIPS) += pci-ifxmips.o ops-ifxmips.o
- ifdef CONFIG_PCI_MSI
- obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
- endif
+++ /dev/null
-Index: linux-2.6.35.8/drivers/serial/Kconfig
-===================================================================
---- linux-2.6.35.8.orig/drivers/serial/Kconfig 2010-10-29 06:52:43.000000000 +0200
-+++ linux-2.6.35.8/drivers/serial/Kconfig 2010-11-01 11:34:31.000000000 +0100
-@@ -1397,6 +1397,14 @@
- help
- Support for Console on the NWP serial ports.
-
-+config SERIAL_IFXMIPS
-+ bool "IFXMips serial driver"
-+ depends on IFXMIPS
-+ select SERIAL_CORE
-+ select SERIAL_CORE_CONSOLE
-+ help
-+ Driver for the ifxmipss built in ASC hardware
-+
- config SERIAL_QE
- tristate "Freescale QUICC Engine serial port support"
- depends on QUICC_ENGINE
-Index: linux-2.6.35.8/drivers/serial/Makefile
-===================================================================
---- linux-2.6.35.8.orig/drivers/serial/Makefile 2010-10-29 06:52:43.000000000 +0200
-+++ linux-2.6.35.8/drivers/serial/Makefile 2010-11-01 11:34:55.000000000 +0100
-@@ -84,3 +84,4 @@
- obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o
- obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o
- obj-$(CONFIG_SERIAL_ALTERA_UART) += altera_uart.o
-+obj-$(CONFIG_SERIAL_IFXMIPS) += ifxmips.o
-Index: linux-2.6.35.8/drivers/net/Kconfig
-===================================================================
---- linux-2.6.35.8.orig/drivers/net/Kconfig 2010-10-29 06:52:43.000000000 +0200
-+++ linux-2.6.35.8/drivers/net/Kconfig 2010-11-01 11:34:31.000000000 +0100
-@@ -232,6 +232,12 @@
-
- source "drivers/net/arm/Kconfig"
-
-+config IFXMIPS_MII0
-+ tristate "Infineon IFXMips eth0 driver"
-+ depends on IFXMIPS
-+ help
-+ Support for the MII0 inside the IFXMips SOC
-+
- config AX88796
- tristate "ASIX AX88796 NE2000 clone support"
- depends on ARM || MIPS || SUPERH
-Index: linux-2.6.35.8/drivers/net/Makefile
-===================================================================
---- linux-2.6.35.8.orig/drivers/net/Makefile 2010-10-29 06:52:43.000000000 +0200
-+++ linux-2.6.35.8/drivers/net/Makefile 2010-11-01 11:35:13.000000000 +0100
-@@ -252,6 +252,7 @@
- obj-$(CONFIG_ENC28J60) += enc28j60.o
- obj-$(CONFIG_ETHOC) += ethoc.o
- obj-$(CONFIG_GRETH) += greth.o
-+obj-$(CONFIG_IFXMIPS_MII0) += ifxmips.o
-
- obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o
-
-Index: linux-2.6.35.8/drivers/mtd/maps/Kconfig
-===================================================================
---- linux-2.6.35.8.orig/drivers/mtd/maps/Kconfig 2010-10-29 06:52:43.000000000 +0200
-+++ linux-2.6.35.8/drivers/mtd/maps/Kconfig 2010-11-01 11:34:31.000000000 +0100
-@@ -251,6 +251,12 @@
- help
- Support for flash chips on NETtel/SecureEdge/SnapGear boards.
-
-+config MTD_IFXMIPS
-+ tristate "IFXMIPS MTD support"
-+ depends on IFXMIPS
-+ help
-+ Flash memory access on AMD Alchemy Pb/Db/RDK Reference Boards
-+
- config MTD_DILNETPC
- tristate "CFI Flash device mapped on DIL/Net PC"
- depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN
-Index: linux-2.6.35.8/drivers/mtd/maps/Makefile
-===================================================================
---- linux-2.6.35.8.orig/drivers/mtd/maps/Makefile 2010-10-29 06:52:43.000000000 +0200
-+++ linux-2.6.35.8/drivers/mtd/maps/Makefile 2010-11-01 11:34:31.000000000 +0100
-@@ -59,3 +59,4 @@
- obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o
- obj-$(CONFIG_MTD_VMU) += vmu-flash.o
- obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o
-+obj-$(CONFIG_MTD_IFXMIPS) += ifxmips.o
-Index: linux-2.6.35.8/drivers/watchdog/Kconfig
-===================================================================
---- linux-2.6.35.8.orig/drivers/watchdog/Kconfig 2010-10-29 06:52:43.000000000 +0200
-+++ linux-2.6.35.8/drivers/watchdog/Kconfig 2010-11-01 11:34:31.000000000 +0100
-@@ -875,6 +875,12 @@
- help
- Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs.
-
-+config IFXMIPS_WDT
-+ bool "IFXMips watchdog"
-+ depends on IFXMIPS
-+ help
-+ Hardware driver for the IFXMIPS Watchdog Timer.
-+
- # PARISC Architecture
-
- # POWERPC Architecture
-Index: linux-2.6.35.8/drivers/watchdog/Makefile
-===================================================================
---- linux-2.6.35.8.orig/drivers/watchdog/Makefile 2010-10-29 06:52:43.000000000 +0200
-+++ linux-2.6.35.8/drivers/watchdog/Makefile 2010-11-01 11:34:31.000000000 +0100
-@@ -114,6 +114,7 @@
- obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
- obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
- obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
-+obj-$(CONFIG_IFXMIPS_WDT) += ifxmips.o
-
- # PARISC Architecture
-
-Index: linux-2.6.35.8/drivers/leds/Kconfig
-===================================================================
---- linux-2.6.35.8.orig/drivers/leds/Kconfig 2010-11-01 11:19:33.000000000 +0100
-+++ linux-2.6.35.8/drivers/leds/Kconfig 2010-11-01 11:34:31.000000000 +0100
-@@ -311,6 +311,12 @@
-
- if LEDS_TRIGGERS
-
-+config LEDS_IFXMIPS
-+ tristate "LED Support for IFXMIPS LEDs"
-+ depends on LEDS_CLASS && IFXMIPS
-+ help
-+ This option enables support for the CM-X270 LEDs.
-+
- comment "LED Triggers"
-
- config LEDS_TRIGGER_TIMER
-Index: linux-2.6.35.8/drivers/leds/Makefile
-===================================================================
---- linux-2.6.35.8.orig/drivers/leds/Makefile 2010-11-01 11:19:33.000000000 +0100
-+++ linux-2.6.35.8/drivers/leds/Makefile 2010-11-01 11:35:43.000000000 +0100
-@@ -37,6 +37,7 @@
- obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o
- obj-$(CONFIG_LEDS_DELL_NETBOOKS) += dell-led.o
- obj-$(CONFIG_LEDS_MC13783) += leds-mc13783.o
-+obj-$(CONFIG_LEDS_IFXMIPS) += leds-ifxmips.o
-
- # LED SPI Drivers
- obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o
+++ /dev/null
-Index: linux-2.6.35.8/drivers/crypto/Kconfig
-===================================================================
---- linux-2.6.35.8.orig/drivers/crypto/Kconfig 2010-10-29 06:52:43.000000000 +0200
-+++ linux-2.6.35.8/drivers/crypto/Kconfig 2010-11-01 11:36:03.000000000 +0100
-@@ -243,4 +243,66 @@
- OMAP processors have SHA1/MD5 hw accelerator. Select this if you
- want to use the OMAP module for SHA1/MD5 algorithms.
-
-+config CRYPTO_DEV_IFXMIPS
-+ bool "Support for IFXMIPS crypto engine"
-+ select CRYPTO_ALGAPI
-+ default y
-+ help
-+ Will support IFXMIPS crypto hardware
-+ If you are unsure, say M.
-+
-+menuconfig CRYPTO_DEV_IFXMIPS_DES
-+ bool "IFXMIPS crypto hardware for DES algorithm"
-+ depends on CRYPTO_DEV_IFXMIPS
-+ select CRYPTO_BLKCIPHER
-+ default y
-+ help
-+ Use crypto hardware for DES/3DES algorithm.
-+ If unsure say N.
-+
-+menuconfig CRYPTO_DEV_IFXMIPS_AES
-+ bool "IFXMIPS crypto hardware for AES algorithm"
-+ depends on CRYPTO_DEV_IFXMIPS
-+ select CRYPTO_BLKCIPHER
-+ default y
-+ help
-+ Use crypto hardware for AES algorithm.
-+ If unsure say N.
-+
-+menuconfig CRYPTO_DEV_IFXMIPS_ARC4
-+ bool "IFXMIPS crypto hardware for ARC4 algorithm"
-+ depends on (CRYPTO_DEV_IFXMIPS && !DANUBE)
-+ select CRYPTO_BLKCIPHER
-+ default y
-+ help
-+ Use crypto hardware for ARC4 algorithm.
-+ If unsure say N.
-+
-+menuconfig CRYPTO_DEV_IFXMIPS_SHA1
-+ bool "IFXMIPS crypto hardware for SHA1 algorithm"
-+ depends on CRYPTO_DEV_IFXMIPS
-+ select CRYPTO_BLKCIPHER
-+ default y
-+ help
-+ Use crypto hardware for SHA1 algorithm.
-+ If unsure say N.
-+
-+menuconfig CRYPTO_DEV_IFXMIPS_SHA1_HMAC
-+ bool "IFXMIPS crypto hardware for SHA1_HMAC algorithm"
-+ depends on (CRYPTO_DEV_IFXMIPS && !DANUBE)
-+ select CRYPTO_BLKCIPHER
-+ default y
-+ help
-+ Use crypto hardware for SHA1_HMAC algorithm.
-+ If unsure say N.
-+
-+menuconfig CRYPTO_DEV_IFXMIPS_MD5_HMAC
-+ bool "IFXMIPS crypto hardware for MD5_HMAC algorithms"
-+ depends on (CRYPTO_DEV_IFXMIPS && !DANUBE)
-+ select CRYPTO_BLKCIPHER
-+ default y
-+ help
-+ Use crypto hardware for MD5_HMAC algorithm.
-+ If unsure say N.
-+
- endif # CRYPTO_HW
-Index: linux-2.6.35.8/drivers/crypto/Makefile
-===================================================================
---- linux-2.6.35.8.orig/drivers/crypto/Makefile 2010-10-29 06:52:43.000000000 +0200
-+++ linux-2.6.35.8/drivers/crypto/Makefile 2010-11-01 11:36:23.000000000 +0100
-@@ -9,4 +9,4 @@
- obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o
- obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/
- obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o
--
-+obj-$(CONFIG_CRYPTO_DEV_IFXMIPS) += ifxmips/
+++ /dev/null
-Index: linux-2.6.35.8/drivers/mtd/chips/cfi_cmdset_0001.c
-===================================================================
---- linux-2.6.35.8.orig/drivers/mtd/chips/cfi_cmdset_0001.c 2010-10-29 06:52:43.000000000 +0200
-+++ linux-2.6.35.8/drivers/mtd/chips/cfi_cmdset_0001.c 2010-11-01 13:01:30.000000000 +0100
-@@ -41,7 +41,11 @@
- /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */
-
- // debugging, turns off buffer write mode if set to 1
--#define FORCE_WORD_WRITE 0
-+#ifdef CONFIG_IFXMIPS
-+# define FORCE_WORD_WRITE 1
-+#else
-+# define FORCE_WORD_WRITE 0
-+#endif
-
- /* Intel chips */
- #define I82802AB 0x00ad
-@@ -1491,6 +1495,9 @@
- int ret=0;
-
- adr += chip->start;
-+#ifdef CONFIG_IFXMIPS
-+ adr ^= 2;
-+#endif
-
- switch (mode) {
- case FL_WRITING:
-Index: linux-2.6.35.8/drivers/mtd/chips/cfi_cmdset_0002.c
-===================================================================
---- linux-2.6.35.8.orig/drivers/mtd/chips/cfi_cmdset_0002.c 2010-11-01 13:01:29.000000000 +0100
-+++ linux-2.6.35.8/drivers/mtd/chips/cfi_cmdset_0002.c 2010-11-01 15:14:17.000000000 +0100
-@@ -40,7 +40,11 @@
- #include <linux/mtd/xip.h>
-
- #define AMD_BOOTLOC_BUG
--#define FORCE_WORD_WRITE 0
-+#ifdef CONFIG_IFXMIPS
-+# define FORCE_WORD_WRITE 1
-+#else
-+# define FORCE_WORD_WRITE 0
-+#endif
-
- #define MAX_WORD_RETRIES 3
-
-@@ -1156,6 +1160,10 @@
-
- adr += chip->start;
-
-+#ifdef CONFIG_IFXMIPS
-+ adr ^= 2;
-+#endif
-+
- mutex_lock(&chip->mutex);
- ret = get_chip(map, chip, adr, FL_WRITING);
- if (ret) {
+++ /dev/null
-Index: linux-2.6.35.8/arch/mips/mm/cache.c
-===================================================================
---- linux-2.6.35.8.orig/arch/mips/mm/cache.c 2010-10-29 06:52:43.000000000 +0200
-+++ linux-2.6.35.8/arch/mips/mm/cache.c 2010-11-01 11:38:06.000000000 +0100
-@@ -52,6 +52,8 @@
- void (*_dma_cache_inv)(unsigned long start, unsigned long size);
-
- EXPORT_SYMBOL(_dma_cache_wback_inv);
-+EXPORT_SYMBOL(_dma_cache_wback);
-+EXPORT_SYMBOL(_dma_cache_inv);
-
- #endif /* CONFIG_DMA_NONCOHERENT */
-
-Index: linux-2.6.35.8/net/atm/proc.c
-===================================================================
---- linux-2.6.35.8.orig/net/atm/proc.c 2010-10-29 06:52:43.000000000 +0200
-+++ linux-2.6.35.8/net/atm/proc.c 2010-11-01 11:38:36.000000000 +0100
-@@ -153,7 +153,7 @@
- static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
- {
- static const char *const class_name[] = {
-- "off", "UBR", "CBR", "VBR", "ABR"};
-+ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR" };
- static const char *const aal_name[] = {
- "---", "1", "2", "3/4", /* 0- 3 */
- "???", "5", "???", "???", /* 4- 7 */
-Index: linux-2.6.35.8/net/atm/common.c
-===================================================================
---- linux-2.6.35.8.orig/net/atm/common.c 2010-10-29 06:52:43.000000000 +0200
-+++ linux-2.6.35.8/net/atm/common.c 2010-11-01 11:39:17.000000000 +0100
-@@ -60,11 +60,17 @@
- write_unlock_irq(&vcc_sklist_lock);
- }
-
-+struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
-+EXPORT_SYMBOL(ifx_atm_alloc_tx);
-+
- static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size)
- {
- struct sk_buff *skb;
- struct sock *sk = sk_atm(vcc);
-
-+ if (ifx_atm_alloc_tx != NULL)
-+ return ifx_atm_alloc_tx(vcc, size);
-+
- if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) {
- pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n",
- sk_wmem_alloc_get(sk), size, sk->sk_sndbuf);
+++ /dev/null
-Index: linux-2.6.35.7/kernel/irq/chip.c
-===================================================================
---- linux-2.6.35.7.orig/kernel/irq/chip.c 2010-10-15 18:40:33.000000000 +0200
-+++ linux-2.6.35.7/kernel/irq/chip.c 2010-10-15 18:44:19.000000000 +0200
-@@ -723,6 +723,7 @@
- set_irq_chip(irq, chip);
- __set_irq_handler(irq, handle, 0, NULL);
- }
-+EXPORT_SYMBOL_GPL(set_irq_chip_and_handler);
-
- void
- set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
-Index: linux-2.6.35.7/kernel/irq/handle.c
-===================================================================
---- linux-2.6.35.7.orig/kernel/irq/handle.c 2010-10-15 18:40:33.000000000 +0200
-+++ linux-2.6.35.7/kernel/irq/handle.c 2010-10-15 18:44:19.000000000 +0200
-@@ -276,6 +276,7 @@
- {
- return (irq < NR_IRQS) ? irq_desc + irq : NULL;
- }
-+EXPORT_SYMBOL_GPL(irq_to_desc);
-
- struct irq_desc *irq_to_desc_alloc_node(unsigned int irq, int node)
- {
projects / openwrt / openwrt.git / commitdiff