mediatek: update patches
authorJohn Crispin <john@phrozen.org>
Mon, 23 May 2016 09:20:20 +0000 (11:20 +0200)
committerJohn Crispin <john@phrozen.org>
Mon, 23 May 2016 09:20:20 +0000 (11:20 +0200)
* fixes NAND
* adds latest ethernet patches

Signed-off-by: John Crispin <john@phrozen.org>
151 files changed:
target/linux/mediatek/Makefile
target/linux/mediatek/base-files/etc/board.d/02_network
target/linux/mediatek/config-4.4
target/linux/mediatek/files/arch/arm/boot/dts/_mt7623.dtsi [new file with mode: 0644]
target/linux/mediatek/files/arch/arm/boot/dts/mt7623-NAND.dts
target/linux/mediatek/files/arch/arm/boot/dts/mt7623-eMMC.dts
target/linux/mediatek/image/Makefile
target/linux/mediatek/patches-4.4/0001-NET-multi-phy-support.patch
target/linux/mediatek/patches-4.4/0002-soc-mediatek-Separate-scpsys-driver-common-code.patch
target/linux/mediatek/patches-4.4/0003-soc-mediatek-Init-MT8173-scpsys-driver-earlier.patch
target/linux/mediatek/patches-4.4/0004-soc-mediatek-Add-MT2701-power-dt-bindings.patch
target/linux/mediatek/patches-4.4/0005-soc-mediatek-Add-MT2701-MT7623-scpsys-driver.patch
target/linux/mediatek/patches-4.4/0006-clk-mediatek-Refine-the-makefile-to-support-multiple.patch
target/linux/mediatek/patches-4.4/0007-dt-bindings-ARM-Mediatek-Document-bindings-for-MT270.patch
target/linux/mediatek/patches-4.4/0008-clk-mediatek-Add-dt-bindings-for-MT2701-clocks.patch
target/linux/mediatek/patches-4.4/0009-clk-mediatek-Add-MT2701-clock-support.patch
target/linux/mediatek/patches-4.4/0010-reset-mediatek-mt2701-reset-controller-dt-binding-fi.patch
target/linux/mediatek/patches-4.4/0011-reset-mediatek-mt2701-reset-driver.patch
target/linux/mediatek/patches-4.4/0012-ARM-mediatek-Add-MT2701-config-options-for-mediatek-.patch
target/linux/mediatek/patches-4.4/0013-dt-bindings-mediatek-Modify-pinctrl-bindings-for-mt2.patch
target/linux/mediatek/patches-4.4/0014-pinctrl-dt-bindings-Add-pinfunc-header-file-for-mt27.patch
target/linux/mediatek/patches-4.4/0015-dt-bindings-mediatek-Modify-pinctrl-bindings-for-mt7.patch
target/linux/mediatek/patches-4.4/0016-pinctrl-dt-bindings-Add-pinctrl-file-for-mt7623.patch
target/linux/mediatek/patches-4.4/0017-clk-add-hifsys-reset.patch
target/linux/mediatek/patches-4.4/0018-dt-bindings-Add-a-binding-for-Mediatek-xHCI-host-con.patch
target/linux/mediatek/patches-4.4/0019-xhci-mediatek-support-MTK-xHCI-host-controller.patch
target/linux/mediatek/patches-4.4/0020-arm64-dts-mediatek-add-xHCI-usb-phy-for-mt8173.patch
target/linux/mediatek/patches-4.4/0021-Document-DT-Add-bindings-for-mediatek-MT7623-SoC-Pla.patch
target/linux/mediatek/patches-4.4/0022-soc-mediatek-add-compat-string-for-mt7623-to-scpsys.patch
target/linux/mediatek/patches-4.4/0023-ARM-dts-mediatek-add-MT7623-basic-support.patch
target/linux/mediatek/patches-4.4/0024-dt-bindings-add-MediaTek-PCIe-binding-documentation.patch
target/linux/mediatek/patches-4.4/0025-PCI-mediatek-add-support-for-PCIe-found-on-MT7623-MT.patch
target/linux/mediatek/patches-4.4/0026-scpsys-various-fixes.patch
target/linux/mediatek/patches-4.4/0027-soc-mediatek-PMIC-wrap-Clear-the-vldclr-if-state-mac.patch
target/linux/mediatek/patches-4.4/0028-ARM-mediatek-add-MT7623-smp-bringup-code.patch
target/linux/mediatek/patches-4.4/0029-soc-mediatek-PMIC-wrap-clear-the-STAUPD_TRIG-bit-of-.patch
target/linux/mediatek/patches-4.4/0030-ARM-mediatek-add-mt2701-smp-bringup-code.patch
target/linux/mediatek/patches-4.4/0031-dt-bindings-ARM-Mediatek-add-MT2701-7623-string-to-t.patch
target/linux/mediatek/patches-4.4/0032-soc-mediatek-PMIC-wrap-don-t-duplicate-the-wrapper-d.patch
target/linux/mediatek/patches-4.4/0033-soc-mediatek-PMIC-wrap-add-wrapper-callbacks-for-ini.patch
target/linux/mediatek/patches-4.4/0034-soc-mediatek-PMIC-wrap-split-SoC-specific-init-into-.patch
target/linux/mediatek/patches-4.4/0035-soc-mediatek-PMIC-wrap-WRAP_INT_EN-needs-a-different.patch
target/linux/mediatek/patches-4.4/0036-soc-mediatek-PMIC-wrap-SPI_WRITE-needs-a-different-b.patch
target/linux/mediatek/patches-4.4/0037-soc-mediatek-PMIC-wrap-move-wdt_src-into-the-pmic_wr.patch
target/linux/mediatek/patches-4.4/0038-soc-mediatek-PMIC-wrap-remove-pwrap_is_mt8135-and-pw.patch
target/linux/mediatek/patches-4.4/0039-soc-mediatek-PMIC-wrap-add-a-slave-specific-struct.patch
target/linux/mediatek/patches-4.4/0040-soc-mediatek-PMIC-wrap-add-mt6323-slave-support.patch
target/linux/mediatek/patches-4.4/0041-soc-mediatek-PMIC-wrap-add-MT2701-7623-support.patch
target/linux/mediatek/patches-4.4/0042-dt-bindings-mfd-Add-bindings-for-the-MediaTek-MT6323.patch
target/linux/mediatek/patches-4.4/0043-mfd-mt6397-int_con-and-int_status-may-vary-in-locati.patch
target/linux/mediatek/patches-4.4/0044-mfd-mt6397-add-support-for-different-Slave-types.patch
target/linux/mediatek/patches-4.4/0045-mfd-mt6397-add-MT6323-support-to-MT6397-driver.patch
target/linux/mediatek/patches-4.4/0046-regulator-Add-document-for-MT6323-regulator.patch
target/linux/mediatek/patches-4.4/0047-regulator-mt6323-Add-support-for-MT6323-regulator.patch
target/linux/mediatek/patches-4.4/0048-net-next-mediatek-document-MediaTek-SoC-ethernet-bin.patch
target/linux/mediatek/patches-4.4/0049-net-next-mediatek-add-support-for-MT7623-ethernet.patch
target/linux/mediatek/patches-4.4/0050-net-next-mediatek-add-Kconfig-and-Makefile.patch
target/linux/mediatek/patches-4.4/0051-net-next-mediatek-add-an-entry-to-MAINTAINERS.patch
target/linux/mediatek/patches-4.4/0052-clk-dont-disable-unused-clocks.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0052-mtd-nand-add-an-mtd_to_nand-helper.patch [deleted file]
target/linux/mediatek/patches-4.4/0053-clk-mediatek-enable-critical-clocks.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0053-mtd-nand-add-nand_to_mtd-helper.patch [deleted file]
target/linux/mediatek/patches-4.4/0054-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0054-mtd-nand-add-helpers-to-access-priv.patch [deleted file]
target/linux/mediatek/patches-4.4/0055-cpufreq-mediatek-add-driver.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0055-mtd-nand-embed-an-mtd_info-structure-into-nand_chip.patch [deleted file]
target/linux/mediatek/patches-4.4/0056-arm-mediatek-make-a7-timer-work-Signed-off-by-John-C.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0056-mtd-add-get-set-of_node-flash_node-helpers.patch [deleted file]
target/linux/mediatek/patches-4.4/0057-mtd-mediatek-device-tree-docs-for-MTK-Smart-Device-G.patch [deleted file]
target/linux/mediatek/patches-4.4/0057-net-mediatek-checking-for-IS_ERR-instead-of-NULL.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0058-mtd-mediatek-driver-for-MTK-Smart-Device-Gen1-NAND.patch [deleted file]
target/linux/mediatek/patches-4.4/0058-net-mediatek-unlock-on-error-in-mtk_tx_map.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0059-mtd-nand-backport-fixes.patch [deleted file]
target/linux/mediatek/patches-4.4/0059-net-mediatek-use-dma_addr_t-correctly.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0060-clk-dont-disable-unused-clocks.patch [deleted file]
target/linux/mediatek/patches-4.4/0060-net-mediatek-remove-incorrect-dma_mask-assignment.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0061-clk-mediatek-enable-critical-clocks.patch [deleted file]
target/linux/mediatek/patches-4.4/0061-net-mediatek-check-device_reset-return-code.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0062-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch [deleted file]
target/linux/mediatek/patches-4.4/0062-net-mediatek-watchdog_timeo-was-not-set.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0063-cpufreq-mediatek-add-driver.patch [deleted file]
target/linux/mediatek/patches-4.4/0063-net-mediatek-mtk_cal_txd_req-returns-bad-value.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0064-arm-mediatek-make-a7-timer-work.patch [deleted file]
target/linux/mediatek/patches-4.4/0064-net-mediatek-remove-superflous-reset-call.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0065-net-mediatek-checking-for-IS_ERR-instead-of-NULL.patch [deleted file]
target/linux/mediatek/patches-4.4/0065-net-mediatek-fix-stop-and-wakeup-of-queue.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0066-net-mediatek-fix-mtk_pending_work.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0066-net-mediatek-unlock-on-error-in-mtk_tx_map.patch [deleted file]
target/linux/mediatek/patches-4.4/0067-net-mediatek-fix-TX-locking.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0067-net-mediatek-use-dma_addr_t-correctly.patch [deleted file]
target/linux/mediatek/patches-4.4/0068-net-mediatek-move-the-pending_work-struct-to-the-dev.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0068-net-mediatek-remove-incorrect-dma_mask-assignment.patch [deleted file]
target/linux/mediatek/patches-4.4/0069-net-mediatek-check-device_reset-return-code.patch [deleted file]
target/linux/mediatek/patches-4.4/0069-net-mediatek-do-not-set-the-QID-field-in-the-TX-DMA-.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0070-net-mediatek-update-the-IRQ-part-of-the-binding-docu.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0070-net-mediatek-watchdog_timeo-was-not-set.patch [deleted file]
target/linux/mediatek/patches-4.4/0071-net-mediatek-mtk_cal_txd_req-returns-bad-value.patch [deleted file]
target/linux/mediatek/patches-4.4/0071-pwm-add-pwm-mediatek.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0072-mtd-backport-v4.7-0day-patches-from-Boris.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0072-net-mediatek-remove-superflous-reset-call.patch [deleted file]
target/linux/mediatek/patches-4.4/0073-net-mediatek-fix-stop-and-wakeup-of-queue.patch [deleted file]
target/linux/mediatek/patches-4.4/0073-of-mtd-prepare-helper-reading-NAND-ECC-algo-from-DT.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0074-mtd-mediatek-device-tree-docs-for-MTK-Smart-Device-G.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0074-net-mediatek-fix-mtk_pending_work.patch [deleted file]
target/linux/mediatek/patches-4.4/0075-mtd-mediatek-driver-for-MTK-Smart-Device-Gen1-NAND.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0075-net-mediatek-fix-TX-locking.patch [deleted file]
target/linux/mediatek/patches-4.4/0076-mtd-nand-add-power-domains-to-the-mediatek-driver.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0076-net-mediatek-move-the-pending_work-struct-to-the-dev.patch [deleted file]
target/linux/mediatek/patches-4.4/0077-net-mediatek-do-not-set-the-QID-field-in-the-TX-DMA-.patch [deleted file]
target/linux/mediatek/patches-4.4/0077-net-next-mediatek-use-mdiobus_free-in-favour-of-kfre.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0078-net-mediatek-update-the-IRQ-part-of-the-binding-docu.patch [deleted file]
target/linux/mediatek/patches-4.4/0078-net-next-mediatek-fix-gigabit-and-flow-control-adver.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0079-net-next-mediatek-add-fixed-phy-support.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0079-net-next-mediatek-fix-BQL-support.patch [deleted file]
target/linux/mediatek/patches-4.4/0080-net-next-mediatek-fix-gigabit-and-flow-control-adver.patch [deleted file]
target/linux/mediatek/patches-4.4/0080-net-next-mediatek-properly-handle-RGMII-modes.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0081-net-next-mediatek-add-fixed-phy-support.patch [deleted file]
target/linux/mediatek/patches-4.4/0081-net-next-mediatek-fix-DQL-support.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0082-net-next-mediatek-add-RX-delay-support.patch [deleted file]
target/linux/mediatek/patches-4.4/0082-net-next-mediatek-add-missing-return-code-check.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0083-net-next-mediatek-add-missing-return-code-check.patch [deleted file]
target/linux/mediatek/patches-4.4/0083-net-next-mediatek-fix-missing-free-of-scratch-memory.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0084-net-next-mediatek-fix-missing-free-of-scratch-memory.patch [deleted file]
target/linux/mediatek/patches-4.4/0084-net-next-mediatek-invalid-buffer-lookup-in-mtk_tx_ma.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0085-net-next-mediatek-dropped-rx-packets-are-not-being-c.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0085-net-next-mediatek-invalid-buffer-lookup-in-mtk_tx_ma.patch [deleted file]
target/linux/mediatek/patches-4.4/0086-net-next-mediatek-add-next-data-pointer-coherency-pr.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0086-net-next-mediatek-dropped-rx-packets-are-not-being-c.patch [deleted file]
target/linux/mediatek/patches-4.4/0087-net-next-mediatek-add-IRQ-locking.patch [deleted file]
target/linux/mediatek/patches-4.4/0087-net-next-mediatek-disable-all-interrupts-during-prob.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0088-net-next-mediatek-add-support-for-IRQ-grouping.patch [deleted file]
target/linux/mediatek/patches-4.4/0088-net-next-mediatek-fix-threshold-value.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0089-net-mediatek-add-gsw-mt7530-driver.patch [deleted file]
target/linux/mediatek/patches-4.4/0089-net-next-mediatek-increase-watchdog_timeo.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0090-net-mediatek-v4.4-backports.patch [deleted file]
target/linux/mediatek/patches-4.4/0090-net-next-mediatek-fix-off-by-one-in-the-TX-ring-allo.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0091-net-next-mediatek-WIP.patch [deleted file]
target/linux/mediatek/patches-4.4/0091-net-next-mediatek-only-wake-the-queue-if-it-is-stopp.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0092-net-next-mediatek-remove-superfluous-queue-wake-up-c.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0093-net-next-mediatek-remove-superfluous-register-reads.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0094-net-next-mediatek-don-t-use-intermediate-variables-t.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0095-net-next-mediatek-add-IRQ-locking.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0096-net-next-mediatek-add-support-for-IRQ-grouping.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0097-net-next-mediatek-change-my-email-address.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0098-net-next-mediatek-only-trigger-the-tx-watchdog-reset.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0099-MAINTAINERS-change-my-email-address.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0100-MAINTAINERS-add-Sean-as-mediatek-ethernet-maintainer.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0100-block2mtd.patch [deleted file]
target/linux/mediatek/patches-4.4/0101-net-mediatek-add-gsw-mt7530-driver.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0102-net-mediatek-v4.4-backports.patch [new file with mode: 0644]
target/linux/mediatek/patches-4.4/0201-block2mtd.patch [new file with mode: 0644]

index 6b3baa4..17deab1 100644 (file)
@@ -5,7 +5,7 @@ include $(TOPDIR)/rules.mk
 ARCH:=arm
 BOARD:=mediatek
 BOARDNAME:=Mediatek Ralink ARM
-FEATURES:=squashfs
+FEATURES:=squashfs jffs2
 CPU_TYPE:=cortex-a7
 MAINTAINER:=John Crispin <john@phrozen.org>
 
index b936d0e..1d1b5c0 100755 (executable)
@@ -10,6 +10,8 @@ mediatek_setup_interfaces()
        local board="$1"
 
        case $board in
+       eMMC | \
+       NAND | \
        mt7623_evb)
                ucidef_set_interfaces_lan_wan "eth0" "eth1"
                ucidef_add_switch "switch0" \
index cd8b915..6221024 100644 (file)
@@ -296,9 +296,10 @@ CONFIG_MODULES_USE_ELF_REL=y
 CONFIG_MTD_BLOCK2MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_MT81xx_NOR=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_MTKSDG1=y
+CONFIG_MTD_NAND_MTK=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTK_INFRACFG=y
 CONFIG_MTK_PMIC_WRAP=y
@@ -406,6 +407,10 @@ CONFIG_PREEMPT_COUNT=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_RCU=y
 CONFIG_PRINTK_TIME=y
+CONFIG_PWM=y
+CONFIG_PWM_MEDIATEK=y
+# CONFIG_PWM_MTK_DISP is not set
+CONFIG_PWM_SYSFS=y
 CONFIG_RATIONAL=y
 CONFIG_RCU_CPU_STALL_TIMEOUT=21
 # CONFIG_RCU_EXPERT is not set
diff --git a/target/linux/mediatek/files/arch/arm/boot/dts/_mt7623.dtsi b/target/linux/mediatek/files/arch/arm/boot/dts/_mt7623.dtsi
new file mode 100644 (file)
index 0000000..4afcc75
--- /dev/null
@@ -0,0 +1,615 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: John Crispin <blogic@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt2701-clk.h>
+#include <dt-bindings/power/mt2701-power.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/reset-controller/mt2701-resets.h>
+#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
+#include "skeleton64.dtsi"
+
+
+/ {
+       compatible = "mediatek,mt7623";
+       interrupt-parent = <&sysirq>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               enable-method = "mediatek,mt6589-smp";
+
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x0>;
+                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
+                                <&apmixedsys CLK_APMIXED_MAINPLL>;
+                       clock-names = "cpu", "intermediate";
+                       operating-points = <
+                               598000 1150000
+                               747500 1150000
+                               1040000 1150000
+                               1196000 1200000
+                               1300000 1300000
+                       >;
+               };
+               cpu1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x1>;
+                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
+                                <&apmixedsys CLK_APMIXED_MAINPLL>;
+                       clock-names = "cpu", "intermediate";
+                       operating-points = <
+                               598000 1150000
+                               747500 1150000
+                               1040000 1150000
+                               1196000 1200000
+                               1300000 1300000
+                       >;
+               };
+               cpu2: cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x2>;
+                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
+                                <&apmixedsys CLK_APMIXED_MAINPLL>;
+                       clock-names = "cpu", "intermediate";
+                       operating-points = <
+                               598000 1150000
+                               747500 1150000
+                               1040000 1150000
+                               1196000 1200000
+                               1300000 1300000
+                       >;
+               };
+               cpu3: cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x3>;
+                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
+                                <&apmixedsys CLK_APMIXED_MAINPLL>;
+                       clock-names = "cpu", "intermediate";
+                       operating-points = <
+                               598000 1150000
+                               747500 1150000
+                               1040000 1150000
+                               1196000 1200000
+                               1300000 1300000
+                       >;
+               };
+       };
+
+       system_clk: dummy13m {
+               compatible = "fixed-clock";
+               clock-frequency = <13000000>;
+               #clock-cells = <0>;
+       };
+
+       rtc_clk: dummy32k {
+               compatible = "fixed-clock";
+               clock-frequency = <32000>;
+               #clock-cells = <0>;
+               clock-output-names = "clk32k";
+       };
+
+       clk26m: dummy26m {
+               compatible = "fixed-clock";
+               clock-frequency = <26000000>;
+               #clock-cells = <0>;
+               clock-output-names = "clk26m";
+       };
+
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupt-parent = <&gic>;
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+               clock-frequency = <13000000>;
+               arm,cpu-registers-not-fw-configured;
+       };
+
+       topckgen: power-controller@10000000 {
+               compatible = "mediatek,mt7623-topckgen",
+                            "mediatek,mt2701-topckgen",
+                            "syscon";
+               reg = <0 0x10000000 0 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       infracfg: power-controller@10001000 {
+               compatible = "mediatek,mt7623-infracfg",
+                            "mediatek,mt2701-infracfg",
+                            "syscon";
+               reg = <0 0x10001000 0 0x1000>;
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+       };
+
+       pericfg: pericfg@10003000 {
+               compatible = "mediatek,mt7623-pericfg",
+                            "mediatek,mt2701-pericfg",
+                            "syscon";
+               reg = <0 0x10003000 0 0x1000>;
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+       };
+
+       pio: pinctrl@10005000 {
+               compatible = "mediatek,mt7623-pinctrl";
+               reg = <0 0x1000b000 0 0x1000>;
+               mediatek,pctl-regmap = <&syscfg_pctl_a>;
+               pins-are-numbered;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-controller;
+               interrupt-parent = <&gic>;
+               #interrupt-cells = <2>;
+               interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       syscfg_pctl_a: syscfg@10005000 {
+               compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
+               reg = <0 0x10005000 0 0x1000>;
+       };
+
+       scpsys: scpsys@10006000 {
+               #power-domain-cells = <1>;
+               compatible = "mediatek,mt7623-scpsys",
+                            "mediatek,mt2701-scpsys";
+               reg = <0 0x10006000 0 0x1000>;
+               infracfg = <&infracfg>;
+               clocks = <&clk26m>,
+                        <&topckgen CLK_TOP_MM_SEL>;
+               clock-names = "mfg", "mm";
+       };
+
+       watchdog: watchdog@10007000 {
+               compatible = "mediatek,mt7623-wdt",
+                            "mediatek,mt6589-wdt";
+               reg = <0 0x10007000 0 0x100>;
+       };
+
+       timer: timer@10008000 {
+               compatible = "mediatek,mt7623-timer",
+                            "mediatek,mt6577-timer";
+               reg = <0 0x10008000 0 0x80>;
+               interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&system_clk>, <&rtc_clk>;
+               clock-names = "system-clk", "rtc-clk";
+       };
+
+       pwrap: pwrap@1000d000 {
+               compatible = "mediatek,mt7623-pwrap",
+                            "mediatek,mt2701-pwrap";
+               reg = <0 0x1000d000 0 0x1000>;
+               reg-names = "pwrap";
+               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+               resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
+               reset-names = "pwrap";
+               clocks = <&infracfg CLK_INFRA_PMICSPI>,
+                        <&infracfg CLK_INFRA_PMICWRAP>;
+               clock-names = "spi", "wrap";
+       };
+
+       sysirq: interrupt-controller@10200100 {
+               compatible = "mediatek,mt7623-sysirq",
+                            "mediatek,mt6577-sysirq";
+               interrupt-controller;
+               #interrupt-cells = <3>;
+               interrupt-parent = <&gic>;
+               reg = <0 0x10200100 0 0x1c>;
+       };
+
+       apmixedsys: apmixedsys@10209000 {
+               compatible = "mediatek,mt7623-apmixedsys",
+                            "mediatek,mt2701-apmixedsys";
+               reg = <0 0x10209000 0 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       gic: interrupt-controller@10211000 {
+               compatible = "arm,cortex-a7-gic";
+               interrupt-controller;
+               #interrupt-cells = <3>;
+               interrupt-parent = <&gic>;
+               reg = <0 0x10211000 0 0x1000>,
+                     <0 0x10212000 0 0x1000>,
+                     <0 0x10214000 0 0x2000>,
+                     <0 0x10216000 0 0x2000>;
+       };
+
+       i2c0: i2c@11007000 {
+               compatible = "mediatek,mt7623-i2c",
+                            "mediatek,mt6577-i2c";
+               reg = <0 0x11007000 0 0x70>,
+                     <0 0x11000200 0 0x80>;
+               interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
+               clock-div = <16>;
+               clocks = <&pericfg CLK_PERI_I2C0>,
+                        <&pericfg CLK_PERI_AP_DMA>;
+               clock-names = "main", "dma";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       i2c1: i2c@11008000 {
+               compatible = "mediatek,mt7623-i2c",
+                            "mediatek,mt6577-i2c";
+               reg = <0 0x11008000 0 0x70>,
+                     <0 0x11000280 0 0x80>;
+               interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
+               clock-div = <16>;
+               clocks = <&pericfg CLK_PERI_I2C1>,
+                        <&pericfg CLK_PERI_AP_DMA>;
+               clock-names = "main", "dma";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       i2c2: i2c@11009000 {
+               compatible = "mediatek,mt7623-i2c",
+                            "mediatek,mt6577-i2c";
+               reg = <0 0x11009000 0 0x70>,
+                     <0 0x11000300 0 0x80>;
+               interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
+               clock-div = <16>;
+               clocks = <&pericfg CLK_PERI_I2C2>,
+                        <&pericfg CLK_PERI_AP_DMA>;
+               clock-names = "main", "dma";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       uart0: serial@11002000 {
+               compatible = "mediatek,mt7623-uart",
+                            "mediatek,mt6577-uart";
+               reg = <0 0x11002000 0 0x400>;
+               interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&pericfg CLK_PERI_UART0_SEL>,
+                        <&pericfg CLK_PERI_UART0>;
+               clock-names = "baud", "bus";
+               status = "disabled";
+       };
+
+       uart1: serial@11003000 {
+               compatible = "mediatek,mt7623-uart",
+                            "mediatek,mt6577-uart";
+               reg = <0 0x11003000 0 0x400>;
+               interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&pericfg CLK_PERI_UART1_SEL>,
+                        <&pericfg CLK_PERI_UART1>;
+               clock-names = "baud", "bus";
+               status = "disabled";
+       };
+
+       uart2: serial@11004000 {
+               compatible = "mediatek,mt7623-uart",
+                            "mediatek,mt6577-uart";
+               reg = <0 0x11004000 0 0x400>;
+               interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&pericfg CLK_PERI_UART2_SEL>,
+                        <&pericfg CLK_PERI_UART2>;
+               clock-names = "baud", "bus";
+               status = "disabled";
+       };
+
+       uart3: serial@11005000 {
+               compatible = "mediatek,mt7623-uart",
+                            "mediatek,mt6577-uart";
+               reg = <0 0x11005000 0 0x400>;
+               interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&pericfg CLK_PERI_UART3_SEL>,
+                        <&pericfg CLK_PERI_UART3>;
+               clock-names = "baud", "bus";
+               status = "disabled";
+       };
+
+       pwm: pwm@11006000 {
+               compatible = "mediatek,mt7623-pwm";
+       
+               reg = <0 0x11006000 0 0x1000>;
+               
+               resets = <&pericfg MT2701_PERI_PWM_SW_RST>;
+               reset-names = "pwm";
+
+               #pwm-cells = <2>;
+               clocks = <&topckgen CLK_TOP_PWM_SEL>,
+                        <&pericfg CLK_PERI_PWM>,
+                        <&pericfg CLK_PERI_PWM1>,
+                        <&pericfg CLK_PERI_PWM2>,
+                        <&pericfg CLK_PERI_PWM3>,
+                        <&pericfg CLK_PERI_PWM4>,
+                        <&pericfg CLK_PERI_PWM5>;
+               clock-names = "top", "main", "pwm1", "pwm2",
+                             "pwm3", "pwm4", "pwm5";
+       
+               status = "disabled";
+       };
+
+       spi: spi@1100a000 {
+               compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
+               reg = <0 0x1100a000 0 0x1000>;
+               interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&pericfg CLK_PERI_SPI0>;
+               clock-names = "main";
+
+               status = "disabled";
+       };
+
+       nandc: nfi@1100d000 {
+               compatible = "mediatek,mt2701-nfc";
+               reg = <0 0x1100d000 0 0x1000>;
+               power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+               interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&pericfg CLK_PERI_NFI>,
+                        <&pericfg CLK_PERI_NFI_PAD>;
+               clock-names = "nfi_clk", "pad_clk";
+               status = "disabled";
+               ecc-engine = <&bch>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+       bch: ecc@1100e000 {
+               compatible = "mediatek,mt2701-ecc";
+               reg = <0 0x1100e000 0 0x1000>;
+               interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&pericfg CLK_PERI_NFI_ECC>;
+               clock-names = "nfiecc_clk";
+               status = "disabled";
+       };
+
+       mmc0: mmc@11230000 {
+               compatible = "mediatek,mt7623-mmc",
+                            "mediatek,mt8135-mmc";
+               reg = <0 0x11230000 0 0x1000>;
+               interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&pericfg CLK_PERI_MSDC30_0>,
+                        <&topckgen CLK_TOP_MSDC30_0_SEL>;
+               clock-names = "source", "hclk";
+               status = "disabled";
+       };
+
+       mmc1: mmc@11240000 {
+               compatible = "mediatek,mt7623-mmc",
+                            "mediatek,mt8135-mmc";
+               reg = <0 0x11240000 0 0x1000>;
+               interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&pericfg CLK_PERI_MSDC30_1>,
+                        <&topckgen CLK_TOP_MSDC30_1_SEL>;
+               clock-names = "source", "hclk";
+               status = "disabled";
+       };
+
+       usb1: usb@1a1c0000 {
+               compatible = "mediatek,mt2701-xhci",
+                            "mediatek,mt8173-xhci";
+               reg = <0 0x1a1c0000 0 0x1000>,
+                     <0 0x1a1c4700 0 0x0100>;
+               interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
+                        <&topckgen CLK_TOP_ETHIF_SEL>;
+               clock-names = "sys_ck", "ethif";
+               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+               phys = <&phy_port0 PHY_TYPE_USB3>;
+               status = "disabled";
+       };
+
+       u3phy1: usb-phy@1a1c4000 {
+               compatible = "mediatek,mt2701-u3phy",
+                            "mediatek,mt8173-u3phy";
+               reg = <0 0x1a1c4000 0 0x0700>;
+               clocks = <&clk26m>;
+               clock-names = "u3phya_ref";
+               #phy-cells = <1>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+               status = "disabled";
+
+               phy_port0: phy_port0: port@1a1c4800 {
+                       reg = <0 0x1a1c4800 0 0x800>;
+                       #phy-cells = <1>;
+                       status = "okay";
+               };
+       };
+
+       usb2: usb@1a240000 {
+               compatible = "mediatek,mt2701-xhci",
+                            "mediatek,mt8173-xhci";
+               reg = <0 0x1a240000 0 0x1000>,
+                     <0 0x1a244700 0 0x0100>;
+               interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
+                        <&topckgen CLK_TOP_ETHIF_SEL>;
+               clock-names = "sys_ck", "ethif";
+               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+               phys = <&u3phy2 0>;
+               status = "disabled";
+       };
+
+       u3phy2: usb-phy@1a244000 {
+               compatible = "mediatek,mt2701-u3phy",
+                            "mediatek,mt8173-u3phy";
+               reg = <0 0x1a244000 0 0x0700>,
+                     <0 0x1a244800 0 0x0800>;
+               clocks = <&clk26m>;
+               clock-names = "u3phya_ref";
+               #phy-cells = <1>;
+               status = "disabled";
+       };
+
+       hifsys: clock-controller@1a000000 {
+               compatible = "mediatek,mt7623-hifsys",
+                            "mediatek,mt2701-hifsys",
+                            "syscon";
+               reg = <0 0x1a000000 0 0x1000>;
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+       };
+
+       pcie: pcie@1a140000 {
+               compatible = "mediatek,mt7623-pcie";
+               device_type = "pci";
+               reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
+                     <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
+                     <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
+                     <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
+               reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
+               interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-names = "pcie0", "pcie1", "pcie2";
+               clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
+               clock-names = "pcie";
+               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+               resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
+                        <&hifsys MT2701_HIFSYS_PCIE1_RST>,
+                        <&hifsys MT2701_HIFSYS_PCIE2_RST>;
+               reset-names = "pcie0", "pcie1", "pcie2";
+
+               mediatek,hifsys = <&hifsys>;
+
+               bus-range = <0x00 0xff>;
+               #address-cells = <3>;
+               #size-cells = <2>;
+
+               ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
+                         0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
+
+               status = "disabled";
+
+               pcie@1,0 {
+                       device_type = "pci";
+                       reg = <0x0800 0 0 0 0>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       ranges;
+               };
+
+               pcie@2,0{
+                       device_type = "pci";
+                       reg = <0x1000 0 0 0 0>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       ranges;
+               };
+
+               pcie@3,0{
+                       device_type = "pci";
+                       reg = <0x1800 0 0 0 0>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       ranges;
+               };
+       };
+
+       ethsys: syscon@1b000000 {
+               compatible = "mediatek,mt2701-ethsys", "syscon";
+               reg = <0 0x1b000000 0 0x1000>;
+               #reset-cells = <1>;
+               #clock-cells = <1>;
+       };
+
+       eth: ethernet@1b100000 {
+               compatible = "mediatek,mt7623-eth";
+               reg = <0 0x1b100000 0 0x20000>;
+       
+               clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+                        <&ethsys CLK_ETHSYS_ESW>,
+                        <&ethsys CLK_ETHSYS_GP2>,
+                        <&ethsys CLK_ETHSYS_GP1>;
+               clock-names = "ethif", "esw", "gp2", "gp1";
+               interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
+                             GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
+                             GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
+               power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+
+               resets = <&ethsys 6>;
+               reset-names = "eth";
+
+               mediatek,ethsys = <&ethsys>;
+               mediatek,pctl = <&syscfg_pctl_a>;
+
+               mediatek,switch = <&gsw>;
+
+               #address-cells = <1>;
+               #size-cells = <0>;
+       
+               status = "disabled";
+
+               gmac1: mac@0 {
+                       compatible = "mediatek,eth-mac";
+                       reg = <0>;
+
+                       status = "disabled";
+                       
+                       phy-mode = "rgmii";
+                       
+                       fixed-link {
+                               speed = <1000>;
+                               full-duplex;
+                               pause;
+                       };
+               };
+
+               gmac2: mac@1 {
+                       compatible = "mediatek,eth-mac";
+                       reg = <1>;
+
+                       status = "disabled";
+               };
+       
+               mdio-bus {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       phy5: ethernet-phy@5 {
+                               reg = <5>;
+                               phy-mode = "rgmii-rxid";
+                       };
+
+                       phy1f: ethernet-phy@1f {
+                               reg = <0x1f>;
+                               phy-mode = "rgmii";
+                       };
+               };
+       };
+
+       gsw: switch@1b100000 {
+               compatible = "mediatek,mt7623-gsw";
+               interrupt-parent = <&pio>;
+               interrupts = <168 IRQ_TYPE_EDGE_RISING>;
+               resets = <&ethsys 2>;
+               reset-names = "eth";
+               clocks = <&apmixedsys CLK_APMIXED_TRGPLL>;
+               clock-names = "trgpll";
+               mt7530-supply = <&mt6323_vpa_reg>;
+               mediatek,pctl-regmap = <&syscfg_pctl_a>;
+               mediatek,ethsys = <&ethsys>;
+               status = "disabled";
+       };
+};
index d25e46e..43551f7 100644 (file)
 
 /dts-v1/;
 
-#include "mt7623.dtsi"
+#include "_mt7623.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 
 / {
-       model = "MediaTek MT7623 evaluation board";
+       model = "MediaTek MT7623 NAND evaluation board";
        compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
 
        chosen {
                        output-low;
                };
        };
+
+       pwm_pins: pwm {
+               pins_pwm1 {
+                       pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>;
+               };
+
+               pins_pwm2 {
+                       pinmux = <MT7623_PIN_205_PWM2_FUNC_PWM2>;
+               };
+       };
 };
 
 &nandc {
 &gmac2 {
        mac-address = [00 11 22 33 44 55];
        status = "okay";
+
+       phy-mode = "rgmii";
+
+       fixed-link {
+               speed = <1000>;
+               full-duplex;
+               pause;
+       };
 };
 
 &gsw {
        mediatek,reset-pin = <&pio 15 0>;
        status = "okay";
 };
+
+&pwm {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pwm_pins>;
+       status = "okay";
+};
index 2b75b44..630240c 100644 (file)
@@ -14,7 +14,7 @@
 
 /dts-v1/;
 
-#include "mt7623.dtsi"
+#include "_mt7623.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 
 / {
                        output-low;
                };
        };
+
+       pwm_pins: pwm {
+               pins_pwm1 {
+                       pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>;
+               };
+
+               pins_pwm2 {
+                       pinmux = <MT7623_PIN_205_PWM2_FUNC_PWM2>;
+               };
+       };
 };
 
 &usb1 {
 &gmac2 {
        mac-address = [00 11 22 33 44 55];
        status = "okay";
+       phy-handle = <&phy5>;
 };
 
 &gsw {
        mediatek,reset-pin = <&pio 15 0>;
        status = "okay";
 };
+
+&pwm {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pwm_pins>;
+       status = "okay";
+};
index 7169907..b88d2dc 100644 (file)
@@ -17,7 +17,7 @@ ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
 endif
        mkdir -p "$(KDIR_TMP)/sysupgrade-$(1)/"
        echo "BOARD=$(1)" > "$(KDIR_TMP)/sysupgrade-$(1)/CONTROL"
-       $(CP) "$(KDIR)/root.squashfs" "$(KDIR_TMP)/sysupgrade-$(1)/root"
+       $(CP) "$(KDIR)/root.$(2)" "$(KDIR_TMP)/sysupgrade-$(1)/root"
        $(CP) "$(KDIR)/uImage-$(1)" "$(KDIR_TMP)/sysupgrade-$(1)/kernel"
        (cd "$(KDIR_TMP)"; $(TAR) cvf \
                "$(BIN_DIR)/$(IMG_PREFIX)-$(1)-sysupgrade.tar" sysupgrade-$(1) \
@@ -29,8 +29,13 @@ define Image/Build/squashfs
        $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
        $(CP) $(KDIR)/root.squashfs $(BIN_DIR)/$(IMG_PREFIX)-root.squashfs
 
-       $(call Image/Build/SysupgradeCombined,eMMC)
-       $(call Image/Build/SysupgradeCombined,NAND)
+       $(call Image/Build/SysupgradeCombined,eMMC,squashfs)
+endef
+
+define Image/Build/jffs2-128k
+       $(CP) $(KDIR)/root.jffs2-128k $(BIN_DIR)/$(IMG_PREFIX)-root.jffs2
+
+       $(call Image/Build/SysupgradeCombined,NAND,jffs2-128k)
 endef
 
 define Image/Build
index 35a2d4f..6ff4e75 100644 (file)
@@ -1,7 +1,7 @@
-From c30a296646a42302065ba452abe95b0b4b550883 Mon Sep 17 00:00:00 2001
+From 1e021917e634b173d466bf0dd3d2ae84e51a77ff Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 27 Jul 2014 09:38:50 +0100
-Subject: [PATCH 01/91] NET: multi phy support
+Subject: [PATCH 001/102] NET: multi phy support
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
@@ -9,9 +9,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  include/linux/phy.h   |    1 +
  2 files changed, 7 insertions(+), 3 deletions(-)
 
+diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
+index 47cd306d..f69d12f 100644
 --- a/drivers/net/phy/phy.c
 +++ b/drivers/net/phy/phy.c
-@@ -888,7 +888,8 @@ void phy_state_machine(struct work_struc
+@@ -844,7 +844,8 @@ void phy_state_machine(struct work_struct *work)
                /* If the link is down, give up on negotiation for now */
                if (!phydev->link) {
                        phydev->state = PHY_NOLINK;
@@ -21,7 +23,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
                        phydev->adjust_link(phydev->attached_dev);
                        break;
                }
-@@ -971,7 +972,8 @@ void phy_state_machine(struct work_struc
+@@ -927,7 +928,8 @@ void phy_state_machine(struct work_struct *work)
                        netif_carrier_on(phydev->attached_dev);
                } else {
                        phydev->state = PHY_NOLINK;
@@ -31,7 +33,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
                }
  
                phydev->adjust_link(phydev->attached_dev);
-@@ -983,7 +985,8 @@ void phy_state_machine(struct work_struc
+@@ -939,7 +941,8 @@ void phy_state_machine(struct work_struct *work)
        case PHY_HALTED:
                if (phydev->link) {
                        phydev->link = 0;
@@ -41,6 +43,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
                        phydev->adjust_link(phydev->attached_dev);
                        do_suspend = true;
                }
+diff --git a/include/linux/phy.h b/include/linux/phy.h
+index 05fde31..276ab8a 100644
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
 @@ -377,6 +377,7 @@ struct phy_device {
@@ -51,3 +55,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
        enum phy_state state;
  
+-- 
+1.7.10.4
+
index 074f68c..9514e86 100644 (file)
@@ -1,7 +1,7 @@
-From 2c93328ed05061a50e3bd4111379dbcf6946d3ac Mon Sep 17 00:00:00 2001
+From 1892fcf687116720d07135c83d489a23ec56a166 Mon Sep 17 00:00:00 2001
 From: James Liao <jamesjj.liao@mediatek.com>
 Date: Wed, 30 Dec 2015 14:41:43 +0800
-Subject: [PATCH 02/91] soc: mediatek: Separate scpsys driver common code
+Subject: [PATCH 002/102] soc: mediatek: Separate scpsys driver common code
 
 Separate scpsys driver common code to mtk-scpsys.c, and move MT8173
 platform code to mtk-scpsys-mt8173.c.
@@ -17,6 +17,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  create mode 100644 drivers/soc/mediatek/mtk-scpsys-mt8173.c
  create mode 100644 drivers/soc/mediatek/mtk-scpsys.h
 
+diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
+index 0a4ea80..eca6fb7 100644
 --- a/drivers/soc/mediatek/Kconfig
 +++ b/drivers/soc/mediatek/Kconfig
 @@ -22,11 +22,20 @@ config MTK_PMIC_WRAP
@@ -42,6 +44,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +        driver.
 +        The System Control Processor System (SCPSYS) has several power
 +        management related tasks in the system.
+diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
+index 12998b0..3b22baa 100644
 --- a/drivers/soc/mediatek/Makefile
 +++ b/drivers/soc/mediatek/Makefile
 @@ -1,3 +1,4 @@
@@ -49,6 +53,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
 +obj-$(CONFIG_MTK_SCPSYS_MT8173) += mtk-scpsys-mt8173.o
+diff --git a/drivers/soc/mediatek/mtk-scpsys-mt8173.c b/drivers/soc/mediatek/mtk-scpsys-mt8173.c
+new file mode 100644
+index 0000000..3c7b569
 --- /dev/null
 +++ b/drivers/soc/mediatek/mtk-scpsys-mt8173.c
 @@ -0,0 +1,179 @@
@@ -231,6 +238,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +};
 +
 +module_platform_driver_probe(scpsys_drv, scpsys_probe);
+diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
+index 4d4203c..a0943c5 100644
 --- a/drivers/soc/mediatek/mtk-scpsys.c
 +++ b/drivers/soc/mediatek/mtk-scpsys.c
 @@ -11,28 +11,14 @@
@@ -248,7 +257,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 -#include <linux/regmap.h>
  #include <linux/soc/mediatek/infracfg.h>
 -#include <dt-bindings/power/mt8173-power.h>
+-
 -#define SPM_VDE_PWR_CON                       0x0210
 -#define SPM_MFG_PWR_CON                       0x0214
 -#define SPM_VEN_PWR_CON                       0x0230
@@ -259,6 +268,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 -#define SPM_MFG_2D_PWR_CON            0x02c0
 -#define SPM_MFG_ASYNC_PWR_CON         0x02c4
 -#define SPM_USB_PWR_CON                       0x02cc
++
 +#include "mtk-scpsys.h"
 +
  #define SPM_PWR_STATUS                        0x060c
@@ -418,7 +428,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  static int scpsys_domain_is_on(struct scp_domain *scpd)
  {
        struct scp *scp = scpd->scp;
-@@ -398,63 +237,89 @@ static bool scpsys_active_wakeup(struct
+@@ -398,63 +237,89 @@ static bool scpsys_active_wakeup(struct device *dev)
        return scpd->active_wakeup;
  }
  
@@ -508,13 +518,13 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +              return ERR_PTR(-ENOMEM);
 +
 +      pd_data = &scp->pd_data;
--      for (i = 0; i < NUM_DOMAINS; i++) {
++
 +      pd_data->domains = devm_kzalloc(&pdev->dev,
 +                      sizeof(*pd_data->domains) * num, GFP_KERNEL);
 +      if (!pd_data->domains)
 +              return ERR_PTR(-ENOMEM);
-+
+-      for (i = 0; i < NUM_DOMAINS; i++) {
 +      pd_data->num_domains = num;
 +
 +      init_clks(pdev, clk);
@@ -539,7 +549,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
                pd_data->domains[i] = genpd;
                scpd->scp = scp;
  
-@@ -464,13 +329,25 @@ static int __init scpsys_probe(struct pl
+@@ -464,13 +329,25 @@ static int __init scpsys_probe(struct platform_device *pdev)
                scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
                scpd->bus_prot_mask = data->bus_prot_mask;
                scpd->active_wakeup = data->active_wakeup;
@@ -567,7 +577,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  
                /*
                 * Initially turn on all domains to make the domains usable
-@@ -489,37 +366,9 @@ static int __init scpsys_probe(struct pl
+@@ -489,37 +366,9 @@ static int __init scpsys_probe(struct platform_device *pdev)
         * valid.
         */
  
@@ -606,6 +616,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 -};
 -
 -module_platform_driver_probe(scpsys_drv, scpsys_probe);
+diff --git a/drivers/soc/mediatek/mtk-scpsys.h b/drivers/soc/mediatek/mtk-scpsys.h
+new file mode 100644
+index 0000000..466728d
 --- /dev/null
 +++ b/drivers/soc/mediatek/mtk-scpsys.h
 @@ -0,0 +1,54 @@
@@ -663,3 +676,6 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +                              struct scp *scp, int num);
 +
 +#endif /* __DRV_SOC_MTK_H */
+-- 
+1.7.10.4
+
index 9446bd1..cdcb6c2 100644 (file)
@@ -1,7 +1,7 @@
-From c359272f86805259c5801385d60fdeea9d629cf9 Mon Sep 17 00:00:00 2001
+From 6f87948c3a58f02f6a64eadda719317016739d5e Mon Sep 17 00:00:00 2001
 From: James Liao <jamesjj.liao@mediatek.com>
 Date: Wed, 30 Dec 2015 14:41:44 +0800
-Subject: [PATCH 03/91] soc: mediatek: Init MT8173 scpsys driver earlier
+Subject: [PATCH 003/102] soc: mediatek: Init MT8173 scpsys driver earlier
 
 Some power domain comsumers may init before module_init.
 So the power domain provider (scpsys) need to be initialized
@@ -12,9 +12,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  drivers/soc/mediatek/mtk-scpsys-mt8173.c |   13 ++++++++++++-
  1 file changed, 12 insertions(+), 1 deletion(-)
 
+diff --git a/drivers/soc/mediatek/mtk-scpsys-mt8173.c b/drivers/soc/mediatek/mtk-scpsys-mt8173.c
+index 3c7b569..827e696 100644
 --- a/drivers/soc/mediatek/mtk-scpsys-mt8173.c
 +++ b/drivers/soc/mediatek/mtk-scpsys-mt8173.c
-@@ -176,4 +176,15 @@ static struct platform_driver scpsys_drv
+@@ -176,4 +176,15 @@ static struct platform_driver scpsys_drv = {
        },
  };
  
@@ -31,3 +33,6 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +
 +subsys_initcall(scpsys_drv_init);
 +module_exit(scpsys_drv_exit);
+-- 
+1.7.10.4
+
index dca106f..33e3178 100644 (file)
@@ -1,7 +1,7 @@
-From f371844374fff273f817d6c43f679606417af59e Mon Sep 17 00:00:00 2001
+From 7c5b29de78f1b15c5bde40a6ca4510fc09588457 Mon Sep 17 00:00:00 2001
 From: Shunli Wang <shunli.wang@mediatek.com>
 Date: Wed, 30 Dec 2015 14:41:45 +0800
-Subject: [PATCH 04/91] soc: mediatek: Add MT2701 power dt-bindings
+Subject: [PATCH 004/102] soc: mediatek: Add MT2701 power dt-bindings
 
 Add power dt-bindings for MT2701.
 
@@ -12,6 +12,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  1 file changed, 27 insertions(+)
  create mode 100644 include/dt-bindings/power/mt2701-power.h
 
+diff --git a/include/dt-bindings/power/mt2701-power.h b/include/dt-bindings/power/mt2701-power.h
+new file mode 100644
+index 0000000..64cc826
 --- /dev/null
 +++ b/include/dt-bindings/power/mt2701-power.h
 @@ -0,0 +1,27 @@
@@ -42,3 +45,6 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +#define MT2701_POWER_DOMAIN_IFR_MSC   8
 +
 +#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
+-- 
+1.7.10.4
+
index db1aeed..388dc08 100644 (file)
@@ -1,7 +1,7 @@
-From c6711565985f359d7d3c05f01f081e4c216902de Mon Sep 17 00:00:00 2001
+From 8aa49d107d8a22fd6cbf37174614baf32d0976e2 Mon Sep 17 00:00:00 2001
 From: Shunli Wang <shunli.wang@mediatek.com>
 Date: Wed, 30 Dec 2015 14:41:46 +0800
-Subject: [PATCH 05/91] soc: mediatek: Add MT2701/MT7623 scpsys driver
+Subject: [PATCH 005/102] soc: mediatek: Add MT2701/MT7623 scpsys driver
 
 Add scpsys driver for MT2701 and MT7623.
 
@@ -14,6 +14,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  3 files changed, 173 insertions(+)
  create mode 100644 drivers/soc/mediatek/mtk-scpsys-mt2701.c
 
+diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
+index eca6fb7..92cf838 100644
 --- a/drivers/soc/mediatek/Kconfig
 +++ b/drivers/soc/mediatek/Kconfig
 @@ -39,3 +39,14 @@ config MTK_SCPSYS_MT8173
@@ -31,13 +33,18 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +        domain driver.
 +        The System Control Processor System (SCPSYS) has several power
 +        management related tasks in the system.
+diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
+index 3b22baa..822986d 100644
 --- a/drivers/soc/mediatek/Makefile
 +++ b/drivers/soc/mediatek/Makefile
-@@ -2,3 +2,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infrac
+@@ -2,3 +2,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
  obj-$(CONFIG_MTK_SCPSYS_MT8173) += mtk-scpsys-mt8173.o
 +obj-$(CONFIG_MTK_SCPSYS_MT2701) += mtk-scpsys-mt2701.o
+diff --git a/drivers/soc/mediatek/mtk-scpsys-mt2701.c b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
+new file mode 100644
+index 0000000..339d5b8
 --- /dev/null
 +++ b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
 @@ -0,0 +1,161 @@
@@ -202,3 +209,6 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +
 +MODULE_DESCRIPTION("MediaTek MT2701 scpsys driver");
 +MODULE_LICENSE("GPL v2");
+-- 
+1.7.10.4
+
index 675e2ae..40c38ca 100644 (file)
@@ -1,8 +1,8 @@
-From 0c39bcd17fa6ce723f56ad3756b4bb36c4690342 Mon Sep 17 00:00:00 2001
+From 69d4e250847f82a5896c41bcb5f1e793c5a8fbac Mon Sep 17 00:00:00 2001
 From: James Liao <jamesjj.liao@mediatek.com>
 Date: Tue, 5 Jan 2016 14:30:17 +0800
-Subject: [PATCH 06/91] clk: mediatek: Refine the makefile to support multiple
- clock drivers
+Subject: [PATCH 006/102] clk: mediatek: Refine the makefile to support
multiple clock drivers
 
 Add a Kconfig to define clock configuration for each SoC, and
 modify the Makefile to build drivers that only selected in config.
@@ -16,6 +16,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  3 files changed, 27 insertions(+), 3 deletions(-)
  create mode 100644 drivers/clk/mediatek/Kconfig
 
+diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
+index c3e3a02..b7a37dc 100644
 --- a/drivers/clk/Kconfig
 +++ b/drivers/clk/Kconfig
 @@ -198,3 +198,4 @@ source "drivers/clk/mvebu/Kconfig"
@@ -23,6 +25,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  source "drivers/clk/samsung/Kconfig"
  source "drivers/clk/tegra/Kconfig"
 +source "drivers/clk/mediatek/Kconfig"
+diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
+new file mode 100644
+index 0000000..dc224e6
 --- /dev/null
 +++ b/drivers/clk/mediatek/Kconfig
 @@ -0,0 +1,23 @@
@@ -49,6 +54,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +      default ARCH_MEDIATEK
 +      ---help---
 +        This driver supports Mediatek MT8173 clocks.
+diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
+index 95fdfac..32e7222 100644
 --- a/drivers/clk/mediatek/Makefile
 +++ b/drivers/clk/mediatek/Makefile
 @@ -1,4 +1,4 @@
@@ -59,3 +66,6 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 -obj-y += clk-mt8173.o
 +obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
 +obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
+-- 
+1.7.10.4
+
index 4ffae5d..9a0dc11 100644 (file)
@@ -1,7 +1,7 @@
-From d7e96f87f66c571e9f4171ecd89c656fbd2de89b Mon Sep 17 00:00:00 2001
+From 7c98b20fa68a2a64bca69822eb7be4fa9b668fab Mon Sep 17 00:00:00 2001
 From: James Liao <jamesjj.liao@mediatek.com>
 Date: Tue, 5 Jan 2016 14:30:18 +0800
-Subject: [PATCH 07/91] dt-bindings: ARM: Mediatek: Document bindings for
+Subject: [PATCH 007/102] dt-bindings: ARM: Mediatek: Document bindings for
  MT2701
 
 This patch adds the binding documentation for apmixedsys, bdpsys,
@@ -25,9 +25,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
 
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+index 936166f..a701e19 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
-@@ -6,6 +6,7 @@ The Mediatek apmixedsys controller provi
+@@ -6,6 +6,7 @@ The Mediatek apmixedsys controller provides the PLLs to the system.
  Required Properties:
  
  - compatible: Should be:
@@ -35,6 +37,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
        - "mediatek,mt8135-apmixedsys"
        - "mediatek,mt8173-apmixedsys"
  - #clock-cells: Must be 1
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
+new file mode 100644
+index 0000000..4137196
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
 @@ -0,0 +1,22 @@
@@ -60,6 +65,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +      reg = <0 0x1c000000 0 0x1000>;
 +      #clock-cells = <1>;
 +};
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+new file mode 100644
+index 0000000..768f3a5
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
 @@ -0,0 +1,22 @@
@@ -85,6 +93,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +      reg = <0 0x1b000000 0 0x1000>;
 +      #clock-cells = <1>;
 +};
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
+new file mode 100644
+index 0000000..b7a39b6
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
 @@ -0,0 +1,22 @@
@@ -110,9 +121,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +      reg = <0 0x1a000000 0 0x1000>;
 +      #clock-cells = <1>;
 +};
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
+index b1f2ce1..9bda7f7 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
-@@ -6,6 +6,7 @@ The Mediatek imgsys controller provides
+@@ -6,6 +6,7 @@ The Mediatek imgsys controller provides various clocks to the system.
  Required Properties:
  
  - compatible: Should be:
@@ -120,6 +133,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
        - "mediatek,mt8173-imgsys", "syscon"
  - #clock-cells: Must be 1
  
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+index f6cd3e4..2f11a69 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
 @@ -7,6 +7,7 @@ outputs to the system.
@@ -130,9 +145,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
        - "mediatek,mt8135-infracfg", "syscon"
        - "mediatek,mt8173-infracfg", "syscon"
  - #clock-cells: Must be 1
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+index 4385946..c9d9d43 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
-@@ -6,6 +6,7 @@ The Mediatek mmsys controller provides v
+@@ -6,6 +6,7 @@ The Mediatek mmsys controller provides various clocks to the system.
  Required Properties:
  
  - compatible: Should be:
@@ -140,6 +157,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
        - "mediatek,mt8173-mmsys", "syscon"
  - #clock-cells: Must be 1
  
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
+index f25b854..d3454cd 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
 @@ -7,6 +7,7 @@ outputs to the system.
@@ -150,9 +169,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
        - "mediatek,mt8135-pericfg", "syscon"
        - "mediatek,mt8173-pericfg", "syscon"
  - #clock-cells: Must be 1
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+index f9e9179..602e5bc 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
-@@ -6,6 +6,7 @@ The Mediatek topckgen controller provide
+@@ -6,6 +6,7 @@ The Mediatek topckgen controller provides various clocks to the system.
  Required Properties:
  
  - compatible: Should be:
@@ -160,9 +181,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
        - "mediatek,mt8135-topckgen"
        - "mediatek,mt8173-topckgen"
  - #clock-cells: Must be 1
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
+index 1faacf1..f5b1e7d 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
-@@ -6,6 +6,7 @@ The Mediatek vdecsys controller provides
+@@ -6,6 +6,7 @@ The Mediatek vdecsys controller provides various clocks to the system.
  Required Properties:
  
  - compatible: Should be:
@@ -170,3 +193,6 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
        - "mediatek,mt8173-vdecsys", "syscon"
  - #clock-cells: Must be 1
  
+-- 
+1.7.10.4
+
index 29e0ae4..4057365 100644 (file)
@@ -1,7 +1,7 @@
-From 2fcbc15da2f13164e0851b9c7fae290249f0b44d Mon Sep 17 00:00:00 2001
+From 190696e3995be38fa01490e4ab88ea2c859829c9 Mon Sep 17 00:00:00 2001
 From: Shunli Wang <shunli.wang@mediatek.com>
 Date: Tue, 5 Jan 2016 14:30:19 +0800
-Subject: [PATCH 08/91] clk: mediatek: Add dt-bindings for MT2701 clocks
+Subject: [PATCH 008/102] clk: mediatek: Add dt-bindings for MT2701 clocks
 
 Add MT2701 clock dt-bindings, include topckgen, apmixedsys,
 infracfg, pericfg and subsystem clocks.
@@ -13,6 +13,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  1 file changed, 481 insertions(+)
  create mode 100644 include/dt-bindings/clock/mt2701-clk.h
 
+diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
+new file mode 100644
+index 0000000..50972d1
 --- /dev/null
 +++ b/include/dt-bindings/clock/mt2701-clk.h
 @@ -0,0 +1,481 @@
@@ -497,3 +500,6 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +#define CLK_BDP_NR                            50
 +
 +#endif /* _DT_BINDINGS_CLK_MT2701_H */
+-- 
+1.7.10.4
+
index 5f87079..488fd3f 100644 (file)
@@ -1,7 +1,7 @@
-From f2c07eaa2df52f9acac9ffc3457d3d81079dd723 Mon Sep 17 00:00:00 2001
+From a4c507d052390b42d7e8c59241e3c336796f730f Mon Sep 17 00:00:00 2001
 From: Shunli Wang <shunli.wang@mediatek.com>
 Date: Tue, 5 Jan 2016 14:30:20 +0800
-Subject: [PATCH 09/91] clk: mediatek: Add MT2701 clock support
+Subject: [PATCH 009/102] clk: mediatek: Add MT2701 clock support
 
 Add MT2701 clock support, include topckgen, apmixedsys,
 infracfg, pericfg and subsystem clocks.
@@ -19,6 +19,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  7 files changed, 1334 insertions(+), 3 deletions(-)
  create mode 100644 drivers/clk/mediatek/clk-mt2701.c
 
+diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
+index dc224e6..6c7cdc0 100644
 --- a/drivers/clk/mediatek/Kconfig
 +++ b/drivers/clk/mediatek/Kconfig
 @@ -6,6 +6,14 @@ config COMMON_CLK_MEDIATEK
@@ -36,6 +38,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  config COMMON_CLK_MT8135
        bool "Clock driver for Mediatek MT8135"
        depends on COMMON_CLK
+diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
+index 32e7222..5b2b91b 100644
 --- a/drivers/clk/mediatek/Makefile
 +++ b/drivers/clk/mediatek/Makefile
 @@ -1,4 +1,5 @@
@@ -44,9 +48,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
  obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
  obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
+diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
+index 576bdb7..38badb4 100644
 --- a/drivers/clk/mediatek/clk-gate.c
 +++ b/drivers/clk/mediatek/clk-gate.c
-@@ -61,6 +61,26 @@ static void mtk_cg_clr_bit(struct clk_hw
+@@ -61,6 +61,26 @@ static void mtk_cg_clr_bit(struct clk_hw *hw)
        regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
  }
  
@@ -73,7 +79,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  static int mtk_cg_enable(struct clk_hw *hw)
  {
        mtk_cg_clr_bit(hw);
-@@ -85,6 +105,30 @@ static void mtk_cg_disable_inv(struct cl
+@@ -85,6 +105,30 @@ static void mtk_cg_disable_inv(struct clk_hw *hw)
        mtk_cg_clr_bit(hw);
  }
  
@@ -104,7 +110,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  const struct clk_ops mtk_clk_gate_ops_setclr = {
        .is_enabled     = mtk_cg_bit_is_cleared,
        .enable         = mtk_cg_enable,
-@@ -97,6 +141,18 @@ const struct clk_ops mtk_clk_gate_ops_se
+@@ -97,6 +141,18 @@ const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
        .disable        = mtk_cg_disable_inv,
  };
  
@@ -123,9 +129,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  struct clk * __init mtk_clk_register_gate(
                const char *name,
                const char *parent_name,
+diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
+index 11e25c9..7f7ef34 100644
 --- a/drivers/clk/mediatek/clk-gate.h
 +++ b/drivers/clk/mediatek/clk-gate.h
-@@ -36,6 +36,8 @@ static inline struct mtk_clk_gate *to_cl
+@@ -36,6 +36,8 @@ static inline struct mtk_clk_gate *to_clk_gate(struct clk_hw *hw)
  
  extern const struct clk_ops mtk_clk_gate_ops_setclr;
  extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
@@ -134,6 +142,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  
  struct clk *mtk_clk_register_gate(
                const char *name,
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+new file mode 100644
+index 0000000..2f521f4
 --- /dev/null
 +++ b/drivers/clk/mediatek/clk-mt2701.c
 @@ -0,0 +1,1210 @@
@@ -1347,9 +1358,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +}
 +CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt2701-apmixedsys",
 +                                                      mtk_apmixedsys_init);
+diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
+index cf08db6..be19a41 100644
 --- a/drivers/clk/mediatek/clk-mtk.c
 +++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -242,3 +242,28 @@ void __init mtk_clk_register_composites(
+@@ -242,3 +242,28 @@ void __init mtk_clk_register_composites(const struct mtk_composite *mcs,
                        clk_data->clks[mc->id] = clk;
        }
  }
@@ -1378,6 +1391,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +                      clk_data->clks[mcd->id] = clk;
 +      }
 +}
+diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
+index 32d2e45..60701e8 100644
 --- a/drivers/clk/mediatek/clk-mtk.h
 +++ b/drivers/clk/mediatek/clk-mtk.h
 @@ -110,7 +110,8 @@ struct mtk_composite {
@@ -1429,3 +1444,6 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  
  struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
  
+-- 
+1.7.10.4
+
index e25a70b..e2988b6 100644 (file)
@@ -1,7 +1,7 @@
-From 8d134cbe750b59d15c591622d81e2e9daa09f0c4 Mon Sep 17 00:00:00 2001
+From 8bf0f2a1e8ff082de3f650211abd985ef68abe1b Mon Sep 17 00:00:00 2001
 From: Shunli Wang <shunli.wang@mediatek.com>
 Date: Tue, 5 Jan 2016 14:30:21 +0800
-Subject: [PATCH 10/91] reset: mediatek: mt2701 reset controller dt-binding
+Subject: [PATCH 010/102] reset: mediatek: mt2701 reset controller dt-binding
  file
 
 Dt-binding file about reset controller is used to provide
@@ -14,6 +14,9 @@ Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
  1 file changed, 74 insertions(+)
  create mode 100644 include/dt-bindings/reset-controller/mt2701-resets.h
 
+diff --git a/include/dt-bindings/reset-controller/mt2701-resets.h b/include/dt-bindings/reset-controller/mt2701-resets.h
+new file mode 100644
+index 0000000..00efeb0
 --- /dev/null
 +++ b/include/dt-bindings/reset-controller/mt2701-resets.h
 @@ -0,0 +1,74 @@
@@ -91,3 +94,6 @@ Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
 +#define MT2701_TOPRGU_BDP_DISP_RST            13
 +
 +#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
+-- 
+1.7.10.4
+
index b0171d9..e69c043 100644 (file)
@@ -1,7 +1,7 @@
-From b86d3303db25a8296e4c3de46ee1470f60f71b0c Mon Sep 17 00:00:00 2001
+From 3ba0020ea70ffb5503eff1823be7fa5ceda38286 Mon Sep 17 00:00:00 2001
 From: Shunli Wang <shunli.wang@mediatek.com>
 Date: Tue, 5 Jan 2016 14:30:22 +0800
-Subject: [PATCH 11/91] reset: mediatek: mt2701 reset driver
+Subject: [PATCH 011/102] reset: mediatek: mt2701 reset driver
 
 In infrasys and perifsys, there are many reset
 control bits for kinds of modules. These bits are
@@ -14,9 +14,11 @@ Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
  drivers/clk/mediatek/clk-mt2701.c |    4 ++++
  1 file changed, 4 insertions(+)
 
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+index 2f521f4..39472e4 100644
 --- a/drivers/clk/mediatek/clk-mt2701.c
 +++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -665,6 +665,8 @@ static void __init mtk_infrasys_init(str
+@@ -665,6 +665,8 @@ static void __init mtk_infrasys_init(struct device_node *node)
        if (r)
                pr_err("%s(): could not register clock provider: %d\n",
                        __func__, r);
@@ -25,7 +27,7 @@ Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
  }
  CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt2701-infracfg", mtk_infrasys_init);
  
-@@ -782,6 +784,8 @@ static void __init mtk_pericfg_init(stru
+@@ -782,6 +784,8 @@ static void __init mtk_pericfg_init(struct device_node *node)
        if (r)
                pr_err("%s(): could not register clock provider: %d\n",
                        __func__, r);
@@ -34,3 +36,6 @@ Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
  }
  CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt2701-pericfg", mtk_pericfg_init);
  
+-- 
+1.7.10.4
+
index 01349d6..8d699eb 100644 (file)
@@ -1,8 +1,8 @@
-From 3b5df542d52b13a1b20d25311fa4c4029a3b83af Mon Sep 17 00:00:00 2001
+From 32fa899c6ab79953e4f470fb23c38bcc40edc5c8 Mon Sep 17 00:00:00 2001
 From: Erin Lo <erin.lo@mediatek.com>
 Date: Mon, 28 Dec 2015 15:09:02 +0800
-Subject: [PATCH 12/91] ARM: mediatek: Add MT2701 config options for mediatek
- SoCs.
+Subject: [PATCH 012/102] ARM: mediatek: Add MT2701 config options for
mediatek SoCs.
 
 The upcoming MTK pinctrl driver have a big pin table for each SoC
 and we don't want to bloat the kernel binary if we don't need it.
@@ -14,6 +14,8 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  arch/arm/mach-mediatek/Kconfig |    4 ++++
  1 file changed, 4 insertions(+)
 
+diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
+index aeece17..37dd438 100644
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
 @@ -9,6 +9,10 @@ menuconfig ARCH_MEDIATEK
@@ -27,3 +29,6 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  config MACH_MT6589
        bool "MediaTek MT6589 SoCs support"
        default ARCH_MEDIATEK
+-- 
+1.7.10.4
+
index 74f35f7..8308771 100644 (file)
@@ -1,7 +1,7 @@
-From 1a254735cad9db5c8605c972b0f16b3929dc0d6e Mon Sep 17 00:00:00 2001
+From afcbed6f51e8c3a9195952b27c8aad047c314ed0 Mon Sep 17 00:00:00 2001
 From: Biao Huang <biao.huang@mediatek.com>
 Date: Mon, 28 Dec 2015 15:09:03 +0800
-Subject: [PATCH 13/91] dt-bindings: mediatek: Modify pinctrl bindings for
+Subject: [PATCH 013/102] dt-bindings: mediatek: Modify pinctrl bindings for
  mt2701
 
 Signed-off-by: Biao Huang <biao.huang@mediatek.com>
@@ -11,9 +11,11 @@ Reviewed-by: Mathias Brugger <matthias.bgg@gmail.com>
  Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt |    9 +++++----
  1 file changed, 5 insertions(+), 4 deletions(-)
 
+diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
+index 0480bc3..9ffb0b2 100644
 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
 +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
-@@ -4,10 +4,11 @@ The Mediatek's Pin controller is used to
+@@ -4,10 +4,11 @@ The Mediatek's Pin controller is used to control SoC pins.
  
  Required properties:
  - compatible: value should be one of the following.
@@ -29,3 +31,6 @@ Reviewed-by: Mathias Brugger <matthias.bgg@gmail.com>
  - pins-are-numbered: Specify the subnodes are using numbered pinmux to
    specify pins.
  - gpio-controller : Marks the device node as a gpio controller.
+-- 
+1.7.10.4
+
index 7664fc8..38e3eae 100644 (file)
@@ -1,7 +1,7 @@
-From 416720ba33d4fd7d3166c17be7c13651cc08d408 Mon Sep 17 00:00:00 2001
+From 124894a4d1635915ff95c447767677b60fd27e9c Mon Sep 17 00:00:00 2001
 From: Biao Huang <biao.huang@mediatek.com>
 Date: Mon, 28 Dec 2015 15:09:04 +0800
-Subject: [PATCH 14/91] pinctrl: dt bindings: Add pinfunc header file for
+Subject: [PATCH 014/102] pinctrl: dt bindings: Add pinfunc header file for
  mt2701
 
 Add pinfunc header file, mt2701 related dts will include it
@@ -21,6 +21,9 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2701.c
  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
 
+diff --git a/arch/arm/boot/dts/mt2701-pinfunc.h b/arch/arm/boot/dts/mt2701-pinfunc.h
+new file mode 100644
+index 0000000..e24ebc8
 --- /dev/null
 +++ b/arch/arm/boot/dts/mt2701-pinfunc.h
 @@ -0,0 +1,735 @@
@@ -759,6 +762,8 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
 +#define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)
 +
 +#endif /* __DTS_MT2701_PINFUNC_H */
+diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
+index 02f6f92..13e9939 100644
 --- a/drivers/pinctrl/mediatek/Kconfig
 +++ b/drivers/pinctrl/mediatek/Kconfig
 @@ -9,6 +9,12 @@ config PINCTRL_MTK_COMMON
@@ -774,6 +779,8 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  config PINCTRL_MT8135
        bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135
        depends on OF
+diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
+index eb923d6..da30314 100644
 --- a/drivers/pinctrl/mediatek/Makefile
 +++ b/drivers/pinctrl/mediatek/Makefile
 @@ -2,6 +2,7 @@
@@ -784,6 +791,9 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  obj-$(CONFIG_PINCTRL_MT8135)          += pinctrl-mt8135.o
  obj-$(CONFIG_PINCTRL_MT8127)          += pinctrl-mt8127.o
  obj-$(CONFIG_PINCTRL_MT8173)          += pinctrl-mt8173.o
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
+new file mode 100644
+index 0000000..4861b5d
 --- /dev/null
 +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
 @@ -0,0 +1,586 @@
@@ -1373,6 +1383,8 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
 +}
 +
 +arch_initcall(mtk_pinctrl_init);
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+index 5c71727..05ba7a8 100644
 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
 @@ -47,6 +47,8 @@
@@ -1384,7 +1396,7 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  };
  
  /*
-@@ -81,6 +83,9 @@ static int mtk_pmx_gpio_set_direction(st
+@@ -81,6 +83,9 @@ static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
        reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
        bit = BIT(offset & 0xf);
  
@@ -1394,7 +1406,7 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
        if (input)
                /* Different SoC has different alignment offset. */
                reg_addr = CLR_ADDR(reg_addr, pctl);
-@@ -347,6 +352,7 @@ static int mtk_pconf_parse_conf(struct p
+@@ -347,6 +352,7 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
                ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
                break;
        case PIN_CONFIG_INPUT_ENABLE:
@@ -1402,7 +1414,7 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
                ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
                break;
        case PIN_CONFIG_OUTPUT:
-@@ -354,6 +360,7 @@ static int mtk_pconf_parse_conf(struct p
+@@ -354,6 +360,7 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
                ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
                break;
        case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
@@ -1410,7 +1422,7 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
                ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
                break;
        case PIN_CONFIG_DRIVE_STRENGTH:
-@@ -667,9 +674,14 @@ static int mtk_pmx_set_mode(struct pinct
+@@ -667,9 +674,14 @@ static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
        unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
        struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  
@@ -1425,7 +1437,7 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
        bit = pin % MAX_GPIO_MODE_PER_REG;
        mask <<= (GPIO_MODE_BITS * bit);
        val = (mode << (GPIO_MODE_BITS * bit));
-@@ -746,6 +758,10 @@ static int mtk_gpio_get_direction(struct
+@@ -746,6 +758,10 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  
        reg_addr =  mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
        bit = BIT(offset & 0xf);
@@ -1436,6 +1448,8 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
        regmap_read(pctl->regmap1, reg_addr, &read_val);
        return !(read_val & bit);
  }
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+index 55a5343..8543bc4 100644
 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
 @@ -209,7 +209,14 @@ struct mtk_eint_offsets {
@@ -1464,6 +1478,9 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
        unsigned int dir_offset;
        unsigned int ies_offset;
        unsigned int smt_offset;
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
+new file mode 100644
+index 0000000..f906420
 --- /dev/null
 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
 @@ -0,0 +1,2323 @@
@@ -3790,3 +3807,6 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
 +};
 +
 +#endif /* __PINCTRL_MTK_MT2701_H */
+-- 
+1.7.10.4
+
index 2272b1a..7fed07c 100644 (file)
@@ -1,7 +1,7 @@
-From ddc72b659b3642d0496dee4e1ee39416ca008053 Mon Sep 17 00:00:00 2001
+From 3800e5c33e5becbb56c6694008d1f3435fd78707 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Thu, 7 Jan 2016 23:42:06 +0100
-Subject: [PATCH 15/91] dt-bindings: mediatek: Modify pinctrl bindings for
+Subject: [PATCH 015/102] dt-bindings: mediatek: Modify pinctrl bindings for
  mt7623
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
@@ -11,6 +11,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  2 files changed, 522 insertions(+)
  create mode 100644 include/dt-bindings/pinctrl/mt7623-pinfunc.h
 
+diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
+index 9ffb0b2..17631d0 100644
 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
 +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
 @@ -6,6 +6,7 @@ Required properties:
@@ -21,6 +23,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
        "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
        "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
+diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
+new file mode 100644
+index 0000000..891b173
 --- /dev/null
 +++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
 @@ -0,0 +1,521 @@
@@ -545,3 +550,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +
 +#endif /* __DTS_MT7623_PINFUNC_H */
 +
+-- 
+1.7.10.4
+
index 35082ea..e444082 100644 (file)
@@ -1,7 +1,7 @@
-From 1255eaacd6cc9d1fa6bb33185380efed22008baf Mon Sep 17 00:00:00 2001
+From 641ccb565a934ffaa30b828f2361e6f57325c70a Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sat, 27 Jun 2015 13:13:05 +0200
-Subject: [PATCH 16/91] pinctrl: dt bindings: Add pinctrl file for mt7623
+Subject: [PATCH 016/102] pinctrl: dt bindings: Add pinctrl file for mt7623
 
 Add the driver and header files required to make pinctrl work on MediaTek
 MT7623.
@@ -17,6 +17,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7623.c
  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
 
+diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
+index 13e9939..78654a8 100644
 --- a/drivers/pinctrl/mediatek/Kconfig
 +++ b/drivers/pinctrl/mediatek/Kconfig
 @@ -15,6 +15,12 @@ config PINCTRL_MT2701
@@ -32,9 +34,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  config PINCTRL_MT8135
        bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135
        depends on OF
+diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
+index da30314..1be2f3f 100644
 --- a/drivers/pinctrl/mediatek/Makefile
 +++ b/drivers/pinctrl/mediatek/Makefile
-@@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_MTK_COMMON)       += pinc
+@@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_MTK_COMMON)       += pinctrl-mtk-common.o
  
  # SoC Drivers
  obj-$(CONFIG_PINCTRL_MT2701)          += pinctrl-mt2701.o
@@ -42,6 +46,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  obj-$(CONFIG_PINCTRL_MT8135)          += pinctrl-mt8135.o
  obj-$(CONFIG_PINCTRL_MT8127)          += pinctrl-mt8127.o
  obj-$(CONFIG_PINCTRL_MT8173)          += pinctrl-mt8173.o
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
+new file mode 100644
+index 0000000..bf0d05b
 --- /dev/null
 +++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
 @@ -0,0 +1,380 @@
@@ -425,6 +432,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +}
 +
 +arch_initcall(mtk_pinctrl_init);
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
+new file mode 100644
+index 0000000..fb63c01
 --- /dev/null
 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
 @@ -0,0 +1,1937 @@
@@ -2365,6 +2375,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +};
 +
 +#endif /* __PINCTRL_MTK_MT7623_H */
+diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
+index 891b173..eeb2380 100644
 --- a/include/dt-bindings/pinctrl/mt7623-pinfunc.h
 +++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
 @@ -505,6 +505,9 @@
@@ -2377,3 +2389,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  #define MT7623_PIN_274_G2_RXDV_FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
  #define MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
  
+-- 
+1.7.10.4
+
index 79647d3..d443971 100644 (file)
@@ -1,7 +1,7 @@
-From 294cf90337d70ad74edf147180bbeef837298bd0 Mon Sep 17 00:00:00 2001
+From f7121d2b19ddad33a09408a2c5923bfd95da8533 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 6 Jan 2016 20:06:49 +0100
-Subject: [PATCH 17/91] clk: add hifsys reset
+Subject: [PATCH 017/102] clk: add hifsys reset
 
 Hi,
 
@@ -18,9 +18,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  include/dt-bindings/reset-controller/mt2701-resets.h |    9 +++++++++
  2 files changed, 11 insertions(+)
 
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+index 39472e4..0e40bb8 100644
 --- a/drivers/clk/mediatek/clk-mt2701.c
 +++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -1000,6 +1000,8 @@ static void __init mtk_hifsys_init(struc
+@@ -1000,6 +1000,8 @@ static void __init mtk_hifsys_init(struct device_node *node)
        if (r)
                pr_err("%s(): could not register clock provider: %d\n",
                        __func__, r);
@@ -29,6 +31,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  }
  CLK_OF_DECLARE(mtk_hifsys, "mediatek,mt2701-hifsys", mtk_hifsys_init);
  
+diff --git a/include/dt-bindings/reset-controller/mt2701-resets.h b/include/dt-bindings/reset-controller/mt2701-resets.h
+index 00efeb0..aaf0305 100644
 --- a/include/dt-bindings/reset-controller/mt2701-resets.h
 +++ b/include/dt-bindings/reset-controller/mt2701-resets.h
 @@ -71,4 +71,13 @@
@@ -45,3 +49,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#define MT2701_HIFSYS_PCIE2_RST                       26
 +
  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
+-- 
+1.7.10.4
+
index 61f1fb5..357ef7e 100644 (file)
@@ -1,7 +1,7 @@
-From 84d37aeef94deae3ce87e677f6016a5d980429e8 Mon Sep 17 00:00:00 2001
+From ba126a519da8a036dae0032e9d5a89e47570e5fb Mon Sep 17 00:00:00 2001
 From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
 Date: Tue, 17 Nov 2015 17:18:39 +0800
-Subject: [PATCH 18/91] dt-bindings: Add a binding for Mediatek xHCI host
+Subject: [PATCH 018/102] dt-bindings: Add a binding for Mediatek xHCI host
  controller
 
 add a DT binding documentation of xHCI host controller for the
@@ -13,6 +13,9 @@ Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
  1 file changed, 51 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/usb/mt8173-xhci.txt
 
+diff --git a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
+new file mode 100644
+index 0000000..a78f20b
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
 @@ -0,0 +1,51 @@
@@ -67,3 +70,6 @@ Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
 +      mediatek,syscon-wakeup = <&pericfg>;
 +      mediatek,wakeup-src = <1>;
 +};
+-- 
+1.7.10.4
+
index 846afc5..a7dd38a 100644 (file)
@@ -1,7 +1,7 @@
-From 651d8fff94718c7e48b8a40d7774878eb8ed62ee Mon Sep 17 00:00:00 2001
+From 8b8185586a13ebbd760e80bbe5f22f9417b50fd2 Mon Sep 17 00:00:00 2001
 From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
 Date: Tue, 17 Nov 2015 17:18:40 +0800
-Subject: [PATCH 19/91] xhci: mediatek: support MTK xHCI host controller
+Subject: [PATCH 019/102] xhci: mediatek: support MTK xHCI host controller
 
 There some vendor quirks for MTK xhci host controller:
 1. It defines some extra SW scheduling parameters for HW
@@ -31,6 +31,8 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  create mode 100644 drivers/usb/host/xhci-mtk.c
  create mode 100644 drivers/usb/host/xhci-mtk.h
 
+diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
+index 3bb0887..daa563f 100644
 --- a/drivers/usb/host/Kconfig
 +++ b/drivers/usb/host/Kconfig
 @@ -41,6 +41,15 @@ config USB_XHCI_PLATFORM
@@ -49,6 +51,8 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  config USB_XHCI_MVEBU
        tristate "xHCI support for Marvell Armada 375/38x"
        select USB_XHCI_PLATFORM
+diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
+index e7558ab..65a06b4 100644
 --- a/drivers/usb/host/Makefile
 +++ b/drivers/usb/host/Makefile
 @@ -13,6 +13,9 @@ fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
@@ -69,6 +73,9 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  obj-$(CONFIG_USB_SL811_HCD)   += sl811-hcd.o
  obj-$(CONFIG_USB_SL811_CS)    += sl811_cs.o
  obj-$(CONFIG_USB_U132_HCD)    += u132-hcd.o
+diff --git a/drivers/usb/host/xhci-mtk-sch.c b/drivers/usb/host/xhci-mtk-sch.c
+new file mode 100644
+index 0000000..c30de7c
 --- /dev/null
 +++ b/drivers/usb/host/xhci-mtk-sch.c
 @@ -0,0 +1,415 @@
@@ -487,6 +494,9 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
 +      }
 +}
 +EXPORT_SYMBOL_GPL(xhci_mtk_drop_ep_quirk);
+diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
+new file mode 100644
+index 0000000..c9ab6a4
 --- /dev/null
 +++ b/drivers/usb/host/xhci-mtk.c
 @@ -0,0 +1,763 @@
@@ -1253,6 +1263,9 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
 +MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
 +MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
 +MODULE_LICENSE("GPL v2");
+diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
+new file mode 100644
+index 0000000..7da677c
 --- /dev/null
 +++ b/drivers/usb/host/xhci-mtk.h
 @@ -0,0 +1,162 @@
@@ -1418,6 +1431,8 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
 +#endif
 +
 +#endif                /* _XHCI_MTK_H_ */
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index eeaa6c6..f1c21c4 100644
 --- a/drivers/usb/host/xhci-ring.c
 +++ b/drivers/usb/host/xhci-ring.c
 @@ -68,6 +68,7 @@
@@ -1428,7 +1443,7 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  
  /*
   * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
-@@ -3065,17 +3066,22 @@ static u32 xhci_td_remainder(struct xhci
+@@ -3075,17 +3076,22 @@ static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
  {
        u32 maxp, total_packet_count;
  
@@ -1455,7 +1470,7 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
        /* Queueing functions don't count the current TRB into transferred */
        return (total_packet_count - ((transferred + trb_buff_len) / maxp));
  }
-@@ -3463,7 +3469,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
+@@ -3473,7 +3479,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
                field |= 0x1;
  
        /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
@@ -1464,6 +1479,8 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
                if (urb->transfer_buffer_length > 0) {
                        if (setup->bRequestType & USB_DIR_IN)
                                field |= TRB_TX_TYPE(TRB_DATA_IN);
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 3f91270..15fedb2 100644
 --- a/drivers/usb/host/xhci.c
 +++ b/drivers/usb/host/xhci.c
 @@ -31,6 +31,7 @@
@@ -1474,7 +1491,7 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  
  #define DRIVER_AUTHOR "Sarah Sharp"
  #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
-@@ -635,7 +636,11 @@ int xhci_run(struct usb_hcd *hcd)
+@@ -634,7 +635,11 @@ int xhci_run(struct usb_hcd *hcd)
                        "// Set the interrupt modulation register");
        temp = readl(&xhci->ir_set->irq_control);
        temp &= ~ER_IRQ_INTERVAL_MASK;
@@ -1487,7 +1504,7 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
        writel(temp, &xhci->ir_set->irq_control);
  
        /* Set the HCD state before we enable the irqs */
-@@ -1701,6 +1706,9 @@ int xhci_drop_endpoint(struct usb_hcd *h
+@@ -1698,6 +1703,9 @@ int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
  
        xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
  
@@ -1497,7 +1514,7 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
        xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
                        (unsigned int) ep->desc.bEndpointAddress,
                        udev->slot_id,
-@@ -1796,6 +1804,15 @@ int xhci_add_endpoint(struct usb_hcd *hc
+@@ -1793,6 +1801,15 @@ int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
                return -ENOMEM;
        }
  
@@ -1513,9 +1530,11 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
        ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
        new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
  
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 0b94512..40cf36e 100644
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
-@@ -1631,6 +1631,7 @@ struct xhci_hcd {
+@@ -1630,6 +1630,7 @@ struct xhci_hcd {
  /* For controllers with a broken beyond repair streams implementation */
  #define XHCI_BROKEN_STREAMS   (1 << 19)
  #define XHCI_PME_STUCK_QUIRK  (1 << 20)
@@ -1523,3 +1542,6 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
        unsigned int            num_active_eps;
        unsigned int            limit_active_eps;
        /* There are two roothubs to keep track of bus suspend info for */
+-- 
+1.7.10.4
+
index a0e9644..5a5476f 100644 (file)
@@ -1,7 +1,7 @@
-From 31a22fbd0d3b187be61c4c5d22b19c95abb327c3 Mon Sep 17 00:00:00 2001
+From 645465d4c6dd46c5e6c9ac25cd42608b4201fde0 Mon Sep 17 00:00:00 2001
 From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
 Date: Tue, 17 Nov 2015 17:18:41 +0800
-Subject: [PATCH 20/91] arm64: dts: mediatek: add xHCI & usb phy for mt8173
+Subject: [PATCH 020/102] arm64: dts: mediatek: add xHCI & usb phy for mt8173
 
 add xHCI and phy drivers for MT8173-EVB
 
@@ -11,6 +11,8 @@ Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
  arch/arm64/boot/dts/mediatek/mt8173.dtsi    |   42 +++++++++++++++++++++++++++
  2 files changed, 58 insertions(+)
 
+diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+index 811cb76..9b1482a 100644
 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
 @@ -13,6 +13,7 @@
@@ -47,6 +49,8 @@ Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
 +      vbus-supply = <&usb_p1_vbus>;
 +      mediatek,wakeup-src = <1>;
 +};
+diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+index 4dd5f93..c1fd275 100644
 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
 +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
 @@ -14,6 +14,7 @@
@@ -105,3 +109,6 @@ Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
                mmsys: clock-controller@14000000 {
                        compatible = "mediatek,mt8173-mmsys", "syscon";
                        reg = <0 0x14000000 0 0x1000>;
+-- 
+1.7.10.4
+
index a2b37d8..5fdfc04 100644 (file)
@@ -1,7 +1,7 @@
-From 162deec293400cb132161606629654acaec7cb4b Mon Sep 17 00:00:00 2001
+From e111a35542ac14712026fe1a55236f76c7fc9048 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 5 Jan 2016 12:13:54 +0100
-Subject: [PATCH 21/91] Document: DT: Add bindings for mediatek MT7623 SoC
+Subject: [PATCH 021/102] Document: DT: Add bindings for mediatek MT7623 SoC
  Platform
 
 This adds a DT binding documentation for the MT7623 SoC from Mediatek.
@@ -13,6 +13,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt |    1 +
  3 files changed, 6 insertions(+)
 
+diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
+index 618a9199..40e9d32 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek.txt
 @@ -10,6 +10,7 @@ compatible: Must contain one of
@@ -33,6 +35,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  - MTK mt8127 tablet moose EVB:
      Required root node properties:
        - compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
+diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
+index 2d47add..474f0cf 100644
 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
 +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
 @@ -2,6 +2,7 @@
@@ -43,6 +47,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
    * "mediatek,mt8135-uart" for MT8135 compatible UARTS
    * "mediatek,mt8127-uart" for MT8127 compatible UARTS
    * "mediatek,mt8173-uart" for MT8173 compatible UARTS
+diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+index 64083bc..6bacda1b3 100644
 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
 +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
 @@ -5,6 +5,7 @@ Required properties:
@@ -53,3 +59,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        * "mediatek,mt8127-timer" for MT8127 compatible timers
        * "mediatek,mt8135-timer" for MT8135 compatible timers
        * "mediatek,mt8173-timer" for MT8173 compatible timers
+-- 
+1.7.10.4
+
index 206fce5..282686c 100644 (file)
@@ -1,16 +1,19 @@
-From fa5d94d6b4b314f751b1c32bb5a87a80b866d05e Mon Sep 17 00:00:00 2001
+From f232c3b36355974bf3442de3a4726d2e499ed3fe Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 5 Jan 2016 16:52:31 +0100
-Subject: [PATCH 22/91] soc: mediatek: add compat string for mt7623 to scpsys
+Subject: [PATCH 022/102] soc: mediatek: add compat string for mt7623 to
+ scpsys
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
  drivers/soc/mediatek/mtk-scpsys-mt2701.c |    2 ++
  1 file changed, 2 insertions(+)
 
+diff --git a/drivers/soc/mediatek/mtk-scpsys-mt2701.c b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
+index 339d5b8..3a31946 100644
 --- a/drivers/soc/mediatek/mtk-scpsys-mt2701.c
 +++ b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
-@@ -136,6 +136,8 @@ static const struct of_device_id of_scps
+@@ -136,6 +136,8 @@ static const struct of_device_id of_scpsys_match_tbl[] = {
        {
                .compatible = "mediatek,mt2701-scpsys",
        }, {
@@ -19,3 +22,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
                /* sentinel */
        }
  };
+-- 
+1.7.10.4
+
index a38a820..22cd1ed 100644 (file)
@@ -1,21 +1,23 @@
-From 83ef9fb21a896ac03c3a78bc3ae0b21f3b0a43a3 Mon Sep 17 00:00:00 2001
+From 51d5ca9e151eb323bd965e72ad1e1dc93fcf7b13 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 5 Jan 2016 12:16:17 +0100
-Subject: [PATCH 23/91] ARM: dts: mediatek: add MT7623 basic support
+Subject: [PATCH 023/102] ARM: dts: mediatek: add MT7623 basic support
 
 This adds basic chip support for Mediatek MT7623.
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
  arch/arm/boot/dts/Makefile        |    1 +
- arch/arm/boot/dts/mt7623-evb.dts  |  474 +++++++++++++++++++++++++++++
- arch/arm/boot/dts/mt7623.dtsi     |  593 +++++++++++++++++++++++++++++++++++++
+ arch/arm/boot/dts/mt7623-evb.dts  |  421 ++++++++++++++++++++++++++
+ arch/arm/boot/dts/mt7623.dtsi     |  601 +++++++++++++++++++++++++++++++++++++
  arch/arm/mach-mediatek/Kconfig    |    4 +
  arch/arm/mach-mediatek/mediatek.c |    1 +
- 5 files changed, 1073 insertions(+)
+ 5 files changed, 1028 insertions(+)
  create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
  create mode 100644 arch/arm/boot/dts/mt7623.dtsi
 
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 30bbc37..2bce370 100644
 --- a/arch/arm/boot/dts/Makefile
 +++ b/arch/arm/boot/dts/Makefile
 @@ -774,6 +774,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
@@ -26,9 +28,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        mt8127-moose.dtb \
        mt8135-evbp1.dtb
  dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
+diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
+new file mode 100644
+index 0000000..5ad1448
 --- /dev/null
 +++ b/arch/arm/boot/dts/mt7623-evb.dts
-@@ -0,0 +1,474 @@
+@@ -0,0 +1,421 @@
 +/*
 + * Copyright (c) 2016 MediaTek Inc.
 + * Author: John Crispin <blogic@openwrt.org>
@@ -318,127 +323,32 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +      status = "okay";
 +};
 +
-+&mmc0 {
-+      status = "okay";
-+      pinctrl-names = "default", "state_uhs";
-+      pinctrl-0 = <&mmc0_pins_default>;
-+      pinctrl-1 = <&mmc0_pins_uhs>;
-+      bus-width = <8>;
-+      max-frequency = <50000000>;
-+      cap-mmc-highspeed;
-+      vmmc-supply = <&mt6323_vemc3v3_reg>;
-+      vqmmc-supply = <&mt6323_vio18_reg>;
-+      non-removable;
-+};
-+
-+&mmc1 {
-+      status = "okay";
-+      pinctrl-names = "default", "state_uhs";
-+      pinctrl-0 = <&mmc1_pins_default>;
-+      pinctrl-1 = <&mmc1_pins_uhs>;
-+      bus-width = <4>;
-+      max-frequency = <50000000>;
-+      cap-sd-highspeed;
-+      sd-uhs-sdr25;
-+//    cd-gpios = <&pio 132 0>;
-+      vmmc-supply = <&mt6323_vmch_reg>;
-+      vqmmc-supply = <&mt6323_vmc_reg>;
-+};
-+
 +&pio {
-+      mmc0_pins_default: mmc0default {
-+              pins_cmd_dat {
-+                      pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
-+                               <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
-+                               <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
-+                               <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
-+                               <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
-+                               <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
-+                               <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
-+                               <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
-+                               <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
-+                      input-enable;
-+                      bias-pull-up;
-+              };
-+
-+              pins_clk {
-+                      pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
-+                      bias-pull-down;
-+              };
-+
-+              pins_rst {
-+                      pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
-+                      bias-pull-up;
++      nand_pins_default: nanddefault {
++              pins_dat {
++                      pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
++                               <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
++                               <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
++                               <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
++                               <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
++                               <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
++                               <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
++                               <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
++                               <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
++                              input-enable;
++                              drive-strength = <MTK_DRIVE_8mA>;
++                              bias-pull-up;
 +              };
-+      };
 +
-+      mmc0_pins_uhs: mmc0 {
-+              pins_cmd_dat {
-+                      pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
-+                               <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
-+                               <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
-+                               <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
-+                               <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
-+                               <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
-+                               <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
-+                               <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
-+                               <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
-+                      input-enable;
-+                      drive-strength = <MTK_DRIVE_2mA>;
-+                      bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
-+              };
-+
-+              pins_clk {
-+                      pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
-+                      drive-strength = <MTK_DRIVE_2mA>;
-+                      bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
-+              };
-+
-+              pins_rst {
-+                      pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
-+                      bias-pull-up;
-+              };
-+      };
-+
-+      mmc1_pins_default: mmc1default {
-+              pins_cmd_dat {
-+                      pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
-+                               <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
-+                               <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
-+                               <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
-+                               <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
-+                      input-enable;
-+                      drive-strength = <MTK_DRIVE_4mA>;
++              pins_we {
++                      pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
++                      drive-strength = <MTK_DRIVE_8mA>;
 +                      bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
 +              };
 +
-+              pins_clk {
-+                      pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
-+                      bias-pull-down;
-+                      drive-strength = <MTK_DRIVE_4mA>;
-+              };
-+
-+//            pins_insert {
-+//                    pinmux = <MT8173_PIN_132_I2S0_DATA1_FUNC_GPIO132>;
-+//                    bias-pull-up;
-+//            };
-+      };
-+
-+      mmc1_pins_uhs: mmc1 {
-+              pins_cmd_dat {
-+                      pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
-+                               <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
-+                               <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
-+                               <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
-+                               <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
-+                      input-enable;
-+                      drive-strength = <MTK_DRIVE_4mA>;
-+                      bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
-+              };
-+
-+              pins_clk {
-+                      pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
-+                      drive-strength = <MTK_DRIVE_4mA>;
++              pins_ale {
++                      pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
++                      drive-strength = <MTK_DRIVE_8mA>;
 +                      bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 +              };
 +      };
@@ -469,6 +379,48 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +      };
 +};
 +
++&nandc {
++      status = "okay";
++      pinctrl-names = "default";
++      pinctrl-0 = <&nand_pins_default>;
++      nand@0 {
++              reg = <0>;
++              partitions {
++                      compatible = "fixed-partitions";
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++
++                      partition@C0000 {
++                              label = "uboot-env";
++                              reg = <0xC0000 0x40000>;
++                      };
++
++                      partition@100000 {
++                              label = "factory";
++                              reg = <0x100000 0x40000>;
++                      };
++
++                      partition@140000 {
++                              label = "kernel";
++                              reg = <0x140000 0x2000000>;
++                      };
++
++                      partition@2140000 {
++                              label = "recovery";
++                              reg = <0x2140000 0x2000000>;
++                      };
++
++                      partition@4140000 {
++                              label = "rootfs";
++                              reg = <0x4140000 0x1000000>;
++                      };
++              };
++      };
++};
++&bch {
++      status = "okay";
++};
++
 +&usb1 {
 +      vusb33-supply = <&mt6323_vusb_reg>;
 +      vbus-supply = <&usb_p1_vbus>;
@@ -503,9 +455,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +      mediatek,reset-pin = <&pio 15 0>;
 +      status = "okay";
 +};
+diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
+new file mode 100644
+index 0000000..cbbdf16
 --- /dev/null
 +++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -0,0 +1,593 @@
+@@ -0,0 +1,601 @@
 +/*
 + * Copyright (c) 2016 MediaTek Inc.
 + * Author: John Crispin <blogic@openwrt.org>
@@ -846,6 +801,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +              compatible = "mediatek,mt2701-nfc";
 +              reg = <0 0x1100d000 0 0x1000>;
 +              interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
++              power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 +              clocks = <&pericfg CLK_PERI_NFI>,
 +                       <&pericfg CLK_PERI_NFI_PAD>;
 +              clock-names = "nfi_clk", "pad_clk";
@@ -1065,8 +1021,15 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +                      compatible = "mediatek,eth-mac";
 +                      reg = <1>;
 +
-+                      phy-handle = <&phy5>;
 +                      status = "disabled";
++                      
++                      phy-mode = "rgmii";
++                      
++                      fixed-link {
++                              speed = <1000>;
++                              full-duplex;
++                              pause;
++                      };
 +              };
 +      
 +              mdio-bus {
@@ -1099,6 +1062,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +              status = "disabled";
 +      };
 +};
+diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
+index 37dd438..7fb605e 100644
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
 @@ -21,6 +21,10 @@ config MACH_MT6592
@@ -1112,9 +1077,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  config MACH_MT8127
        bool "MediaTek MT8127 SoCs support"
        default ARCH_MEDIATEK
+diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
+index d019a08..bcfca37 100644
 --- a/arch/arm/mach-mediatek/mediatek.c
 +++ b/arch/arm/mach-mediatek/mediatek.c
-@@ -46,6 +46,7 @@ static void __init mediatek_timer_init(v
+@@ -46,6 +46,7 @@ static void __init mediatek_timer_init(void)
  static const char * const mediatek_board_dt_compat[] = {
        "mediatek,mt6589",
        "mediatek,mt6592",
@@ -1122,3 +1089,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        "mediatek,mt8127",
        "mediatek,mt8135",
        NULL,
+-- 
+1.7.10.4
+
index fc924f8..0df02b6 100644 (file)
@@ -1,7 +1,7 @@
-From 427a938858630fe4cec1b3829624676a4106d236 Mon Sep 17 00:00:00 2001
+From 05be818061b9f2a0fa5ad0cde6881917ff14a2f2 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 6 Jan 2016 21:55:10 +0100
-Subject: [PATCH 24/91] dt-bindings: add MediaTek PCIe binding documentation
+Subject: [PATCH 024/102] dt-bindings: add MediaTek PCIe binding documentation
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
@@ -9,6 +9,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  1 file changed, 140 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt
 
+diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+new file mode 100644
+index 0000000..8fea3ed
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
 @@ -0,0 +1,140 @@
@@ -152,3 +155,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +                      status = "okay";
 +              };
 +      };
+-- 
+1.7.10.4
+
index 52e03b0..5079c2b 100644 (file)
@@ -1,7 +1,7 @@
-From 5571cc63036daf0e0a05f07b0137fee86d58acb0 Mon Sep 17 00:00:00 2001
+From 8ab1d4e0a9a68e03f472dee1c036a01d0198c20c Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 5 Jan 2016 20:20:04 +0100
-Subject: [PATCH 25/91] PCI: mediatek: add support for PCIe found on
+Subject: [PATCH 025/102] PCI: mediatek: add support for PCIe found on
  MT7623/MT2701
 
 Add PCIe controller support on MediaTek MT2701/MT7623. The driver supports
@@ -17,6 +17,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  4 files changed, 654 insertions(+)
  create mode 100644 drivers/pci/host/pcie-mediatek.c
 
+diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
+index 7fb605e..a7fef77 100644
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
 @@ -24,6 +24,7 @@ config MACH_MT6592
@@ -27,9 +29,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  config MACH_MT8127
        bool "MediaTek MT8127 SoCs support"
+diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
+index f131ba9..912f0e1 100644
 --- a/drivers/pci/host/Kconfig
 +++ b/drivers/pci/host/Kconfig
-@@ -173,4 +173,15 @@ config PCI_HISI
+@@ -172,4 +172,15 @@ config PCI_HISI
        help
          Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC
  
@@ -45,13 +49,18 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +        PCIe include one Host/PCI bridge and 3 PCIe MAC.
 +
  endmenu
+diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
+index 9d4d3c6..3b53374 100644
 --- a/drivers/pci/host/Makefile
 +++ b/drivers/pci/host/Makefile
-@@ -20,3 +20,4 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-ip
+@@ -20,3 +20,4 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
  obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
  obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
  obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
 +obj-$(CONFIG_PCIE_MTK) += pcie-mediatek.o
+diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
+new file mode 100644
+index 0000000..ef03952
 --- /dev/null
 +++ b/drivers/pci/host/pcie-mediatek.c
 @@ -0,0 +1,641 @@
@@ -696,3 +705,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +}
 +
 +module_init(mtk_pcie_init);
+-- 
+1.7.10.4
+
index 663a341..2635392 100644 (file)
@@ -1,7 +1,7 @@
-From a366216a08408949eca2d7823273da6826d3c483 Mon Sep 17 00:00:00 2001
+From 59aafd667d2880c90776931b6102b8252214d93c Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 21 Feb 2016 13:52:12 +0100
-Subject: [PATCH 26/91] scpsys: various fixes
+Subject: [PATCH 026/102] scpsys: various fixes
 
 ---
  drivers/clk/mediatek/clk-mt2701.c        |    2 ++
@@ -9,9 +9,11 @@ Subject: [PATCH 26/91] scpsys: various fixes
  include/dt-bindings/power/mt2701-power.h |    4 ++--
  3 files changed, 4 insertions(+), 10 deletions(-)
 
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+index 0e40bb8..812b347 100644
 --- a/drivers/clk/mediatek/clk-mt2701.c
 +++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -1043,6 +1043,8 @@ static void __init mtk_ethsys_init(struc
+@@ -1043,6 +1043,8 @@ static void __init mtk_ethsys_init(struct device_node *node)
        if (r)
                pr_err("%s(): could not register clock provider: %d\n",
                        __func__, r);
@@ -20,9 +22,11 @@ Subject: [PATCH 26/91] scpsys: various fixes
  }
  CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt2701-ethsys", mtk_ethsys_init);
  
+diff --git a/drivers/soc/mediatek/mtk-scpsys-mt2701.c b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
+index 3a31946..19489bc 100644
 --- a/drivers/soc/mediatek/mtk-scpsys-mt2701.c
 +++ b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
-@@ -61,14 +61,6 @@ static const struct scp_domain_data scp_
+@@ -61,14 +61,6 @@ static const struct scp_domain_data scp_domain_data[] = {
                .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_DISP,
                .active_wakeup = true,
        },
@@ -37,6 +41,8 @@ Subject: [PATCH 26/91] scpsys: various fixes
        [MT2701_POWER_DOMAIN_VDEC] = {
                .name = "vdec",
                .sta_mask = VDE_PWR_STA_MASK,
+diff --git a/include/dt-bindings/power/mt2701-power.h b/include/dt-bindings/power/mt2701-power.h
+index 64cc826..c168597 100644
 --- a/include/dt-bindings/power/mt2701-power.h
 +++ b/include/dt-bindings/power/mt2701-power.h
 @@ -16,12 +16,12 @@
@@ -54,3 +60,6 @@ Subject: [PATCH 26/91] scpsys: various fixes
 +#define MT2701_POWER_DOMAIN_IFR_MSC   2
  
  #endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
+-- 
+1.7.10.4
+
index 6be1b18..f80a677 100644 (file)
@@ -1,7 +1,7 @@
-From 4d02177361d13355d98a38830c69bb9add3c109c Mon Sep 17 00:00:00 2001
+From 55231d8299d3dccde8588ed2e86c2bc0ef2e12ce Mon Sep 17 00:00:00 2001
 From: Henry Chen <henryc.chen@mediatek.com>
 Date: Mon, 4 Jan 2016 20:02:52 +0800
-Subject: [PATCH 27/91] soc: mediatek: PMIC wrap: Clear the vldclr if state
+Subject: [PATCH 027/102] soc: mediatek: PMIC wrap: Clear the vldclr if state
  machine stay on FSM_VLDCLR state.
 
 Sometimes PMIC is too busy to send data in time to cause pmic wrap timeout,
@@ -20,9 +20,11 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   22 ++++++++++++++++++++--
  1 file changed, 20 insertions(+), 2 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 105597a..696071b 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
-@@ -412,6 +412,20 @@ static bool pwrap_is_fsm_vldclr(struct p
+@@ -412,6 +412,20 @@ static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
        return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
  }
  
@@ -43,7 +45,7 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
  {
        return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
-@@ -445,8 +459,10 @@ static int pwrap_write(struct pmic_wrapp
+@@ -445,8 +459,10 @@ static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
        int ret;
  
        ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
@@ -55,7 +57,7 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  
        pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
                        PWRAP_WACS2_CMD);
-@@ -459,8 +475,10 @@ static int pwrap_read(struct pmic_wrappe
+@@ -459,8 +475,10 @@ static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
        int ret;
  
        ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
@@ -67,3 +69,6 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  
        pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
  
+-- 
+1.7.10.4
+
index 5b8490a..130850e 100644 (file)
@@ -1,7 +1,7 @@
-From e4a5c39f75a11ecb78d1243b19b929af54f888fa Mon Sep 17 00:00:00 2001
+From d088a94afc768683a881b627b6737442158e7db6 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 5 Jan 2016 17:24:28 +0100
-Subject: [PATCH 28/91] ARM: mediatek: add MT7623 smp bringup code
+Subject: [PATCH 028/102] ARM: mediatek: add MT7623 smp bringup code
 
 Add support for booting secondary CPUs on MT7623.
 
@@ -11,9 +11,11 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  arch/arm/mach-mediatek/platsmp.c |    7 +++++++
  1 file changed, 7 insertions(+)
 
+diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
+index 8141f3f..8151400 100644
 --- a/arch/arm/mach-mediatek/platsmp.c
 +++ b/arch/arm/mach-mediatek/platsmp.c
-@@ -44,6 +44,12 @@ static const struct mtk_smp_boot_info mt
+@@ -44,6 +44,12 @@ static const struct mtk_smp_boot_info mtk_mt6589_boot = {
        { 0x38, 0x3c, 0x40 },
  };
  
@@ -26,7 +28,7 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {
        { .compatible   = "mediatek,mt8135", .data = &mtk_mt8135_tz_boot },
        { .compatible   = "mediatek,mt8127", .data = &mtk_mt8135_tz_boot },
-@@ -51,6 +57,7 @@ static const struct of_device_id mtk_tz_
+@@ -51,6 +57,7 @@ static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {
  
  static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
        { .compatible   = "mediatek,mt6589", .data = &mtk_mt6589_boot },
@@ -34,3 +36,6 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  };
  
  static void __iomem *mtk_smp_base;
+-- 
+1.7.10.4
+
index ef8c49e..3c38ac4 100644 (file)
@@ -1,8 +1,8 @@
-From b4a6293df00036129d26a7f06bfb220ba5a73c42 Mon Sep 17 00:00:00 2001
+From b92861fbc79b3a7a9bc1c51e2dbfa2c191cc27ea Mon Sep 17 00:00:00 2001
 From: Henry Chen <henryc.chen@mediatek.com>
 Date: Thu, 21 Jan 2016 19:04:00 +0800
-Subject: [PATCH 29/91] soc: mediatek: PMIC wrap: clear the STAUPD_TRIG bit of
- WDT_SRC_EN
+Subject: [PATCH 029/102] soc: mediatek: PMIC wrap: clear the STAUPD_TRIG bit
of WDT_SRC_EN
 
 Since STAUPD interrupts aren't handled on mt8173, disable watchdog timeout
 monitor of STAUPD to avoid WDT_INT triggered by STAUPD.
@@ -14,6 +14,8 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   19 +++++++++++++++++--
  1 file changed, 17 insertions(+), 2 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 696071b..0d9b19a 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -60,6 +60,15 @@
@@ -32,7 +34,7 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  /* macro for slave device wrapper registers */
  #define PWRAP_DEW_BASE                        0xbc00
  #define PWRAP_DEW_EVENT_OUT_EN                (PWRAP_DEW_BASE + 0x0)
-@@ -822,7 +831,7 @@ MODULE_DEVICE_TABLE(of, of_pwrap_match_t
+@@ -822,7 +831,7 @@ MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
  
  static int pwrap_probe(struct platform_device *pdev)
  {
@@ -41,7 +43,7 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
        struct pmic_wrapper *wrp;
        struct device_node *np = pdev->dev.of_node;
        const struct of_device_id *of_id =
-@@ -912,7 +921,13 @@ static int pwrap_probe(struct platform_d
+@@ -912,7 +921,13 @@ static int pwrap_probe(struct platform_device *pdev)
  
        /* Initialize watchdog, may not be done by the bootloader */
        pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
@@ -56,3 +58,6 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
        pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
        pwrap_writel(wrp, ~((1 << 31) | (1 << 1)), PWRAP_INT_EN);
  
+-- 
+1.7.10.4
+
index 7ae5039..940fa44 100644 (file)
@@ -1,7 +1,7 @@
-From 0befbd007b72ba2b14c65558d3bb72ea885496f6 Mon Sep 17 00:00:00 2001
+From f88ec31c6ba3a006d0be87ff1d99145f8cc85bee Mon Sep 17 00:00:00 2001
 From: Louis Yu <louis.yu@mediatek.com>
 Date: Thu, 7 Jan 2016 20:09:43 +0800
-Subject: [PATCH 30/91] ARM: mediatek: add mt2701 smp bringup code
+Subject: [PATCH 030/102] ARM: mediatek: add mt2701 smp bringup code
 
 Add support for booting secondary CPUs on mt2701.
 
@@ -11,9 +11,11 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  arch/arm/mach-mediatek/platsmp.c |    1 +
  1 file changed, 1 insertion(+)
 
+diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
+index 8151400..2078f92d5 100644
 --- a/arch/arm/mach-mediatek/platsmp.c
 +++ b/arch/arm/mach-mediatek/platsmp.c
-@@ -53,6 +53,7 @@ static const struct mtk_smp_boot_info mt
+@@ -53,6 +53,7 @@ static const struct mtk_smp_boot_info mtk_mt7623_boot = {
  static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {
        { .compatible   = "mediatek,mt8135", .data = &mtk_mt8135_tz_boot },
        { .compatible   = "mediatek,mt8127", .data = &mtk_mt8135_tz_boot },
@@ -21,3 +23,6 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  };
  
  static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
+-- 
+1.7.10.4
+
index 348f81c..6a3ec46 100644 (file)
@@ -1,8 +1,8 @@
-From 9367fb14e1be8dd174f8d63ec83f7ee2d90ae733 Mon Sep 17 00:00:00 2001
+From 15f4d895578f02cbaed10b0f5f6853b873aba10b Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 13:12:19 +0100
-Subject: [PATCH 31/91] dt-bindings: ARM: Mediatek: add MT2701/7623 string to
- the PMIC wrapper doc
+Subject: [PATCH 031/102] dt-bindings: ARM: Mediatek: add MT2701/7623 string
+ to the PMIC wrapper doc
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 Acked-by: Rob Herring <robh@kernel.org>
@@ -11,6 +11,8 @@ Cc: devicetree@vger.kernel.org
  Documentation/devicetree/bindings/soc/mediatek/pwrap.txt |    1 +
  1 file changed, 1 insertion(+)
 
+diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
+index ddeb5b6..107700d 100644
 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
 +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
 @@ -18,6 +18,7 @@ IP Pairing
@@ -21,3 +23,6 @@ Cc: devicetree@vger.kernel.org
        "mediatek,mt8135-pwrap" for MT8135 SoCs
        "mediatek,mt8173-pwrap" for MT8173 SoCs
  - interrupts: IRQ for pwrap in SOC
+-- 
+1.7.10.4
+
index a65e658..b7afdbc 100644 (file)
@@ -1,8 +1,8 @@
-From 7b7d59b4219c30e1b9601300348f1431fdab7081 Mon Sep 17 00:00:00 2001
+From 64e8091be39c3f0a7bf4651bd2045b8c86429d55 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 06:42:01 +0100
-Subject: [PATCH 32/91] soc: mediatek: PMIC wrap: don't duplicate the wrapper
- data
+Subject: [PATCH 032/102] soc: mediatek: PMIC wrap: don't duplicate the
wrapper data
 
 As we add support for more devices struct pmic_wrapper_type will grow and
 we do not really want to start duplicating all the elements in
@@ -13,6 +13,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   22 ++++++++--------------
  1 file changed, 8 insertions(+), 14 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 0d9b19a..340c4b5 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -376,9 +376,7 @@ struct pmic_wrapper {
@@ -53,7 +55,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  }
  
  static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
-@@ -697,7 +695,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -697,7 +695,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  
        pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
  
@@ -62,7 +64,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
        pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
  
-@@ -742,7 +740,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -742,7 +740,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
        pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
        pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
        pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
@@ -71,7 +73,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
        if (pwrap_is_mt8135(wrp))
                pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
-@@ -836,7 +834,6 @@ static int pwrap_probe(struct platform_d
+@@ -836,7 +834,6 @@ static int pwrap_probe(struct platform_device *pdev)
        struct device_node *np = pdev->dev.of_node;
        const struct of_device_id *of_id =
                of_match_device(of_pwrap_match_tbl, &pdev->dev);
@@ -79,7 +81,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        struct resource *res;
  
        wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
-@@ -845,10 +842,7 @@ static int pwrap_probe(struct platform_d
+@@ -845,10 +842,7 @@ static int pwrap_probe(struct platform_device *pdev)
  
        platform_set_drvdata(pdev, wrp);
  
@@ -91,3 +93,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        wrp->dev = &pdev->dev;
  
        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
+-- 
+1.7.10.4
+
index fac7174..25d7f74 100644 (file)
@@ -1,7 +1,7 @@
-From 35d879d80437cc6ed811538903e115dbcda777ac Mon Sep 17 00:00:00 2001
+From 756b919b7874cc241a276b4fc5bbec5b3fb4bca8 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 05:27:17 +0100
-Subject: [PATCH 33/91] soc: mediatek: PMIC wrap: add wrapper callbacks for
+Subject: [PATCH 033/102] soc: mediatek: PMIC wrap: add wrapper callbacks for
  init_reg_clock
 
 Split init_reg_clock up into SoC specific callbacks. The patch also
@@ -12,6 +12,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   70 ++++++++++++++++++----------------
  1 file changed, 38 insertions(+), 32 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 340c4b5..b22b664 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -354,24 +354,6 @@ enum pwrap_type {
@@ -53,7 +55,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static inline int pwrap_is_mt8135(struct pmic_wrapper *wrp)
  {
        return wrp->master->type == PWRAP_MT8135;
-@@ -578,20 +567,23 @@ static int pwrap_init_sidly(struct pmic_
+@@ -578,20 +567,23 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp)
        return 0;
  }
  
@@ -90,7 +92,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
        return 0;
  }
-@@ -699,7 +691,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -699,7 +691,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  
        pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
  
@@ -99,7 +101,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        if (ret)
                return ret;
  
-@@ -814,6 +806,20 @@ static const struct regmap_config pwrap_
+@@ -814,6 +806,20 @@ static const struct regmap_config pwrap_regmap_config = {
        .max_register = 0xffff,
  };
  
@@ -120,3 +122,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static struct of_device_id of_pwrap_match_tbl[] = {
        {
                .compatible = "mediatek,mt8135-pwrap",
+-- 
+1.7.10.4
+
index 4d400c9..3a74a6a 100644 (file)
@@ -1,8 +1,8 @@
-From d82889cec95358b917fcf29fc3214980deb138b9 Mon Sep 17 00:00:00 2001
+From a1bbd630710d5da89a9c347c84d7badd30e7e68a Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 10:12:00 +0100
-Subject: [PATCH 34/91] soc: mediatek: PMIC wrap: split SoC specific init into
- callback
+Subject: [PATCH 034/102] soc: mediatek: PMIC wrap: split SoC specific init
into callback
 
 This patch moves the SoC specific wrapper init code into separate callback
 to avoid pwrap_init() getting too large. This is done by adding a new
@@ -16,6 +16,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   67 +++++++++++++++++++++-------------
  1 file changed, 42 insertions(+), 25 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index b22b664..22c89e9 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -372,6 +372,7 @@ struct pmic_wrapper_type {
@@ -26,7 +28,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  };
  
  static inline int pwrap_is_mt8135(struct pmic_wrapper *wrp)
-@@ -665,6 +666,41 @@ static int pwrap_init_cipher(struct pmic
+@@ -665,6 +666,41 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
        return 0;
  }
  
@@ -68,7 +70,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static int pwrap_init(struct pmic_wrapper *wrp)
  {
        int ret;
-@@ -743,31 +779,10 @@ static int pwrap_init(struct pmic_wrappe
+@@ -743,31 +779,10 @@ static int pwrap_init(struct pmic_wrapper *wrp)
        pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
        pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
  
@@ -104,7 +106,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        }
  
        /* Setup the init done registers */
-@@ -811,6 +826,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -811,6 +826,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
        .type = PWRAP_MT8135,
        .arb_en_all = 0x1ff,
        .init_reg_clock = pwrap_mt8135_init_reg_clock,
@@ -112,7 +114,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  };
  
  static struct pmic_wrapper_type pwrap_mt8173 = {
-@@ -818,6 +834,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -818,6 +834,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
        .type = PWRAP_MT8173,
        .arb_en_all = 0x3f,
        .init_reg_clock = pwrap_mt8173_init_reg_clock,
@@ -120,3 +122,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  };
  
  static struct of_device_id of_pwrap_match_tbl[] = {
+-- 
+1.7.10.4
+
index 8596666..c51f84c 100644 (file)
@@ -1,7 +1,7 @@
-From 613acba0068461948e6b5283df03d7c1e1583a40 Mon Sep 17 00:00:00 2001
+From 274fd9ba57170de88bbdf522cbd6c290c2e51fb8 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 10:14:39 +0100
-Subject: [PATCH 35/91] soc: mediatek: PMIC wrap: WRAP_INT_EN needs a
+Subject: [PATCH 035/102] soc: mediatek: PMIC wrap: WRAP_INT_EN needs a
  different bitmask for MT2701/7623
 
 MT2701 and MT7623 use a different bitmask for PWRAP_INT_EN.
@@ -11,6 +11,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |    5 ++++-
  1 file changed, 4 insertions(+), 1 deletion(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 22c89e9..9df1135 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -371,6 +371,7 @@ struct pmic_wrapper_type {
@@ -21,7 +23,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        int (*init_reg_clock)(struct pmic_wrapper *wrp);
        int (*init_soc_specific)(struct pmic_wrapper *wrp);
  };
-@@ -825,6 +826,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -825,6 +826,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
        .regs = mt8135_regs,
        .type = PWRAP_MT8135,
        .arb_en_all = 0x1ff,
@@ -29,7 +31,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        .init_reg_clock = pwrap_mt8135_init_reg_clock,
        .init_soc_specific = pwrap_mt8135_init_soc_specific,
  };
-@@ -833,6 +835,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -833,6 +835,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
        .regs = mt8173_regs,
        .type = PWRAP_MT8173,
        .arb_en_all = 0x3f,
@@ -37,7 +39,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        .init_reg_clock = pwrap_mt8173_init_reg_clock,
        .init_soc_specific = pwrap_mt8173_init_soc_specific,
  };
-@@ -946,7 +949,7 @@ static int pwrap_probe(struct platform_d
+@@ -946,7 +949,7 @@ static int pwrap_probe(struct platform_device *pdev)
                        PWRAP_WDT_SRC_MASK_NO_STAUPD : PWRAP_WDT_SRC_MASK_ALL;
        pwrap_writel(wrp, wdt_src, PWRAP_WDT_SRC_EN);
        pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
@@ -46,3 +48,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
        irq = platform_get_irq(pdev, 0);
        ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, IRQF_TRIGGER_HIGH,
+-- 
+1.7.10.4
+
index dbf81c8..e47a4c5 100644 (file)
@@ -1,8 +1,8 @@
-From 1186088ab86b7286e1920dcbfbbbf2627a0daeda Mon Sep 17 00:00:00 2001
+From 511e697282c6425950b95373ac8dc59a42fd2485 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 10:21:42 +0100
-Subject: [PATCH 36/91] soc: mediatek: PMIC wrap: SPI_WRITE needs a different
- bitmask for MT2701/7623
+Subject: [PATCH 036/102] soc: mediatek: PMIC wrap: SPI_WRITE needs a
different bitmask for MT2701/7623
 
 Different SoCs will use different bitmask for the SPI_WRITE command. This
 patch defines the bitmask in the pmic_wrapper_type struct. This allows us
@@ -13,6 +13,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   11 +++++++----
  1 file changed, 7 insertions(+), 4 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 9df1135..8ce1bad 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -372,6 +372,7 @@ struct pmic_wrapper_type {
@@ -23,7 +25,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        int (*init_reg_clock)(struct pmic_wrapper *wrp);
        int (*init_soc_specific)(struct pmic_wrapper *wrp);
  };
-@@ -511,15 +512,15 @@ static int pwrap_reset_spislave(struct p
+@@ -511,15 +512,15 @@ static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
        pwrap_writel(wrp, 1, PWRAP_MAN_EN);
        pwrap_writel(wrp, 0, PWRAP_DIO_EN);
  
@@ -43,7 +45,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
                                PWRAP_MAN_CMD);
  
        ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
-@@ -827,6 +828,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -827,6 +828,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
        .type = PWRAP_MT8135,
        .arb_en_all = 0x1ff,
        .int_en_all = ~(BIT(31) | BIT(1)),
@@ -51,7 +53,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        .init_reg_clock = pwrap_mt8135_init_reg_clock,
        .init_soc_specific = pwrap_mt8135_init_soc_specific,
  };
-@@ -836,6 +838,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -836,6 +838,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
        .type = PWRAP_MT8173,
        .arb_en_all = 0x3f,
        .int_en_all = ~(BIT(31) | BIT(1)),
@@ -59,3 +61,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        .init_reg_clock = pwrap_mt8173_init_reg_clock,
        .init_soc_specific = pwrap_mt8173_init_soc_specific,
  };
+-- 
+1.7.10.4
+
index 2c701d4..e082096 100644 (file)
@@ -1,7 +1,7 @@
-From 95f72db32afd545b88eaa04802736f1f84242a9f Mon Sep 17 00:00:00 2001
+From 6aecbc79322efd3068c6140f74a68654fbe5b5f6 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 10:48:35 +0100
-Subject: [PATCH 37/91] soc: mediatek: PMIC wrap: move wdt_src into the
+Subject: [PATCH 037/102] soc: mediatek: PMIC wrap: move wdt_src into the
  pmic_wrapper_type struct
 
 Different SoCs will use different bitmask for the wdt_src. This patch
@@ -13,6 +13,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |    9 +++++----
  1 file changed, 5 insertions(+), 4 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 8ce1bad..aa54df3 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -373,6 +373,7 @@ struct pmic_wrapper_type {
@@ -23,7 +25,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        int (*init_reg_clock)(struct pmic_wrapper *wrp);
        int (*init_soc_specific)(struct pmic_wrapper *wrp);
  };
-@@ -829,6 +830,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -829,6 +830,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
        .arb_en_all = 0x1ff,
        .int_en_all = ~(BIT(31) | BIT(1)),
        .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
@@ -31,7 +33,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        .init_reg_clock = pwrap_mt8135_init_reg_clock,
        .init_soc_specific = pwrap_mt8135_init_soc_specific,
  };
-@@ -839,6 +841,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -839,6 +841,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
        .arb_en_all = 0x3f,
        .int_en_all = ~(BIT(31) | BIT(1)),
        .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
@@ -39,7 +41,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        .init_reg_clock = pwrap_mt8173_init_reg_clock,
        .init_soc_specific = pwrap_mt8173_init_soc_specific,
  };
-@@ -858,7 +861,7 @@ MODULE_DEVICE_TABLE(of, of_pwrap_match_t
+@@ -858,7 +861,7 @@ MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
  
  static int pwrap_probe(struct platform_device *pdev)
  {
@@ -48,7 +50,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        struct pmic_wrapper *wrp;
        struct device_node *np = pdev->dev.of_node;
        const struct of_device_id *of_id =
-@@ -948,9 +951,7 @@ static int pwrap_probe(struct platform_d
+@@ -948,9 +951,7 @@ static int pwrap_probe(struct platform_device *pdev)
         * Since STAUPD was not used on mt8173 platform,
         * so STAUPD of WDT_SRC which should be turned off
         */
@@ -59,3 +61,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
        pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
  
+-- 
+1.7.10.4
+
index 79ea3a2..94d4b8c 100644 (file)
@@ -1,8 +1,8 @@
-From bb19fd13b1ed629873ea144b22c4764aa4baa5ef Mon Sep 17 00:00:00 2001
+From da09b34ad22e8f065a02af114668f7d86357244a Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 10:54:18 +0100
-Subject: [PATCH 38/91] soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and
- pwrap_is_mt8173()
+Subject: [PATCH 038/102] soc: mediatek: PMIC wrap: remove pwrap_is_mt8135()
and pwrap_is_mt8173()
 
 With more SoCs being added the list of helper functions like these would
 grow. To mitigate this problem we remove the existing helpers and change
@@ -18,6 +18,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   28 ++++++++++++----------------
  1 file changed, 12 insertions(+), 16 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index aa54df3..a2bacda 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -374,20 +374,11 @@ struct pmic_wrapper_type {
@@ -42,7 +44,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
  {
        return readl(wrp->base + wrp->master->regs[reg]);
-@@ -619,11 +610,14 @@ static int pwrap_init_cipher(struct pmic
+@@ -619,11 +610,14 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
        pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
        pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
  
@@ -59,7 +61,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        }
  
        /* Config cipher mode @PMIC */
-@@ -713,7 +707,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -713,7 +707,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
        if (wrp->rstc_bridge)
                reset_control_reset(wrp->rstc_bridge);
  
@@ -68,7 +70,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
                /* Enable DCM */
                pwrap_writel(wrp, 3, PWRAP_DCM_EN);
                pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
-@@ -773,7 +767,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -773,7 +767,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
        pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
        pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
  
@@ -77,7 +79,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
                pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
  
        pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
-@@ -793,7 +787,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -793,7 +787,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
        pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
        pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
  
@@ -86,7 +88,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
                writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
                writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
        }
-@@ -831,6 +825,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -831,6 +825,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
        .int_en_all = ~(BIT(31) | BIT(1)),
        .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
        .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
@@ -94,7 +96,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        .init_reg_clock = pwrap_mt8135_init_reg_clock,
        .init_soc_specific = pwrap_mt8135_init_soc_specific,
  };
-@@ -842,6 +837,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -842,6 +837,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
        .int_en_all = ~(BIT(31) | BIT(1)),
        .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
        .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
@@ -102,7 +104,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        .init_reg_clock = pwrap_mt8173_init_reg_clock,
        .init_soc_specific = pwrap_mt8173_init_soc_specific,
  };
-@@ -889,7 +885,7 @@ static int pwrap_probe(struct platform_d
+@@ -889,7 +885,7 @@ static int pwrap_probe(struct platform_device *pdev)
                return ret;
        }
  
@@ -111,3 +113,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
                res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
                                "pwrap-bridge");
                wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
+-- 
+1.7.10.4
+
index b72834a..5b1ab7a 100644 (file)
@@ -1,7 +1,8 @@
-From daa4d054bb0557799c8b324d7aa5f0a3a4a7b078 Mon Sep 17 00:00:00 2001
+From 21bdcd324f769545b1765fe391d939a1edd07cbb Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 09:55:08 +0100
-Subject: [PATCH 39/91] soc: mediatek: PMIC wrap: add a slave specific struct
+Subject: [PATCH 039/102] soc: mediatek: PMIC wrap: add a slave specific
+ struct
 
 This patch adds a new struct pwrap_slv_type that we use to store the slave
 specific data. The patch adds 2 new helper functions to access the dew
@@ -12,6 +13,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |  159 ++++++++++++++++++++++++----------
  1 file changed, 112 insertions(+), 47 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index a2bacda..bcc841e 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -69,33 +69,54 @@
@@ -123,7 +126,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        struct clk *clk_spi;
        struct clk *clk_wrap;
        struct reset_control *rstc;
-@@ -544,7 +575,8 @@ static int pwrap_init_sidly(struct pmic_
+@@ -544,7 +575,8 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp)
  
        for (i = 0; i < 4; i++) {
                pwrap_writel(wrp, i, PWRAP_SIDLY);
@@ -133,7 +136,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
                if (rdata == PWRAP_DEW_READ_TEST_VAL) {
                        dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
                        pass |= 1 << i;
-@@ -593,7 +625,8 @@ static bool pwrap_is_pmic_cipher_ready(s
+@@ -593,7 +625,8 @@ static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
        u32 rdata;
        int ret;
  
@@ -143,7 +146,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        if (ret)
                return 0;
  
-@@ -621,12 +654,12 @@ static int pwrap_init_cipher(struct pmic
+@@ -621,12 +654,12 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
        }
  
        /* Config cipher mode @PMIC */
@@ -162,7 +165,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
        /* wait for cipher data ready@AP */
        ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
-@@ -643,7 +676,7 @@ static int pwrap_init_cipher(struct pmic
+@@ -643,7 +676,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
        }
  
        /* wait for cipher mode idle */
@@ -171,7 +174,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
        if (ret) {
                dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
-@@ -653,9 +686,11 @@ static int pwrap_init_cipher(struct pmic
+@@ -653,9 +686,11 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
        pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
  
        /* Write Test */
@@ -186,7 +189,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
                dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
                return -EFAULT;
        }
-@@ -677,8 +712,10 @@ static int pwrap_mt8135_init_soc_specifi
+@@ -677,8 +712,10 @@ static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
        writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
  
        /* enable PMIC event out and sources */
@@ -199,7 +202,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
                dev_err(wrp->dev, "enable dewrap fail\n");
                return -EFAULT;
        }
-@@ -689,8 +726,10 @@ static int pwrap_mt8135_init_soc_specifi
+@@ -689,8 +726,10 @@ static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
  static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
  {
        /* PMIC_DEWRAP enables */
@@ -212,7 +215,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
                dev_err(wrp->dev, "enable dewrap fail\n");
                return -EFAULT;
        }
-@@ -734,7 +773,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -734,7 +773,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
                return ret;
  
        /* Enable dual IO mode */
@@ -221,7 +224,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
        /* Check IDLE & INIT_DONE in advance */
        ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
-@@ -746,7 +785,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -746,7 +785,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
        pwrap_writel(wrp, 1, PWRAP_DIO_EN);
  
        /* Read Test */
@@ -230,7 +233,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        if (rdata != PWRAP_DEW_READ_TEST_VAL) {
                dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
                                PWRAP_DEW_READ_TEST_VAL, rdata);
-@@ -759,12 +798,13 @@ static int pwrap_init(struct pmic_wrappe
+@@ -759,12 +798,13 @@ static int pwrap_init(struct pmic_wrapper *wrp)
                return ret;
  
        /* Signature checking - using CRC */
@@ -246,7 +249,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
  
        if (wrp->master->type == PWRAP_MT8135)
-@@ -818,6 +858,21 @@ static const struct regmap_config pwrap_
+@@ -818,6 +858,21 @@ static const struct regmap_config pwrap_regmap_config = {
        .max_register = 0xffff,
  };
  
@@ -268,7 +271,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static struct pmic_wrapper_type pwrap_mt8135 = {
        .regs = mt8135_regs,
        .type = PWRAP_MT8135,
-@@ -862,8 +917,17 @@ static int pwrap_probe(struct platform_d
+@@ -862,8 +917,17 @@ static int pwrap_probe(struct platform_device *pdev)
        struct device_node *np = pdev->dev.of_node;
        const struct of_device_id *of_id =
                of_match_device(of_pwrap_match_tbl, &pdev->dev);
@@ -286,7 +289,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
        if (!wrp)
                return -ENOMEM;
-@@ -871,6 +935,7 @@ static int pwrap_probe(struct platform_d
+@@ -871,6 +935,7 @@ static int pwrap_probe(struct platform_device *pdev)
        platform_set_drvdata(pdev, wrp);
  
        wrp->master = of_id->data;
@@ -294,3 +297,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        wrp->dev = &pdev->dev;
  
        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
+-- 
+1.7.10.4
+
index f4111f1..70840e2 100644 (file)
@@ -1,7 +1,7 @@
-From 15143b59a26a06e890e2ba3c9944b3f751ce39bd Mon Sep 17 00:00:00 2001
+From 4418ba9a0bb105f00259d10ceb16f9e27199e9b0 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 11:40:43 +0100
-Subject: [PATCH 40/91] soc: mediatek: PMIC wrap: add mt6323 slave support
+Subject: [PATCH 040/102] soc: mediatek: PMIC wrap: add mt6323 slave support
 
 Add support for MT6323 slaves. This PMIC can be found on MT2701 and MT7623
 EVB. The only function that we need to touch is pwrap_init_cipher().
@@ -11,6 +11,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   43 ++++++++++++++++++++++++++++++++++
  1 file changed, 43 insertions(+)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index bcc841e..0e4ebb8 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -93,6 +93,27 @@ enum dew_regs {
@@ -49,7 +51,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        PMIC_MT6397,
  };
  
-@@ -661,6 +683,19 @@ static int pwrap_init_cipher(struct pmic
+@@ -661,6 +683,19 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
        pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 0x1);
        pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], 0x1);
  
@@ -69,7 +71,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        /* wait for cipher data ready@AP */
        ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
        if (ret) {
-@@ -858,6 +893,11 @@ static const struct regmap_config pwrap_
+@@ -858,6 +893,11 @@ static const struct regmap_config pwrap_regmap_config = {
        .max_register = 0xffff,
  };
  
@@ -81,7 +83,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static const struct pwrap_slv_type pmic_mt6397 = {
        .dew_regs = mt6397_regs,
        .type = PMIC_MT6397,
-@@ -865,6 +905,9 @@ static const struct pwrap_slv_type pmic_
+@@ -865,6 +905,9 @@ static const struct pwrap_slv_type pmic_mt6397 = {
  
  static const struct of_device_id of_slave_match_tbl[] = {
        {
@@ -91,3 +93,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
                .compatible = "mediatek,mt6397",
                .data = &pmic_mt6397,
        }, {
+-- 
+1.7.10.4
+
index dfe1890..aa5e3fb 100644 (file)
@@ -1,7 +1,7 @@
-From 2f5df30a7b913069c8fce22dc702e0d7c76ef361 Mon Sep 17 00:00:00 2001
+From 7736d97fe2c6c71c9009a1b45a94de06bfc94a37 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 12:09:14 +0100
-Subject: [PATCH 41/91] soc: mediatek: PMIC wrap: add MT2701/7623 support
+Subject: [PATCH 041/102] soc: mediatek: PMIC wrap: add MT2701/7623 support
 
 Add the registers, callbacks and data structures required to make the
 wrapper work on MT2701 and MT7623.
@@ -11,6 +11,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |  154 ++++++++++++++++++++++++++++++++++
  1 file changed, 154 insertions(+)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 0e4ebb8..3c3e56d 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -52,6 +52,7 @@
@@ -136,7 +138,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        PWRAP_MT8135,
        PWRAP_MT8173,
  };
-@@ -637,6 +732,31 @@ static int pwrap_mt8173_init_reg_clock(s
+@@ -637,6 +732,31 @@ static int pwrap_mt8173_init_reg_clock(struct pmic_wrapper *wrp)
        return 0;
  }
  
@@ -168,7 +170,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
  {
        return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
-@@ -670,6 +790,7 @@ static int pwrap_init_cipher(struct pmic
+@@ -670,6 +790,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
                pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
                pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
                break;
@@ -176,7 +178,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        case PWRAP_MT8173:
                pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
                break;
-@@ -772,6 +893,24 @@ static int pwrap_mt8173_init_soc_specifi
+@@ -772,6 +893,24 @@ static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
        return 0;
  }
  
@@ -201,7 +203,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static int pwrap_init(struct pmic_wrapper *wrp)
  {
        int ret;
-@@ -916,6 +1055,18 @@ static const struct of_device_id of_slav
+@@ -916,6 +1055,18 @@ static const struct of_device_id of_slave_match_tbl[] = {
  };
  MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
  
@@ -220,7 +222,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static struct pmic_wrapper_type pwrap_mt8135 = {
        .regs = mt8135_regs,
        .type = PWRAP_MT8135,
-@@ -942,6 +1093,9 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -942,6 +1093,9 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
  
  static struct of_device_id of_pwrap_match_tbl[] = {
        {
@@ -230,3 +232,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
                .compatible = "mediatek,mt8135-pwrap",
                .data = &pwrap_mt8135,
        }, {
+-- 
+1.7.10.4
+
index 5fe1965..f38b522 100644 (file)
@@ -1,8 +1,8 @@
-From edc6e6a2f10f7b7fc94dc6147c86520e5a439d16 Mon Sep 17 00:00:00 2001
+From c14dc2993a272c706650502ec579ceabe5f2355e Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 10 Jan 2016 17:12:37 +0100
-Subject: [PATCH 42/91] dt-bindings: mfd: Add bindings for the MediaTek MT6323
- PMIC
+Subject: [PATCH 042/102] dt-bindings: mfd: Add bindings for the MediaTek
MT6323 PMIC
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 Acked-by: Rob Herring <robh@kernel.org>
@@ -11,6 +11,8 @@ Cc: devicetree@vger.kernel.org
  Documentation/devicetree/bindings/mfd/mt6397.txt |   10 ++++++----
  1 file changed, 6 insertions(+), 4 deletions(-)
 
+diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt
+index 15043e6..949c85f 100644
 --- a/Documentation/devicetree/bindings/mfd/mt6397.txt
 +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
 @@ -1,6 +1,6 @@
@@ -22,7 +24,7 @@ Cc: devicetree@vger.kernel.org
  - Regulator
  - RTC
  - Audio codec
-@@ -8,14 +8,14 @@ MT6397 is a multifunction device with th
+@@ -8,14 +8,14 @@ MT6397 is a multifunction device with the following sub modules:
  - Clock
  
  It is interfaced to host controller using SPI interface by a proprietary hardware
@@ -48,3 +50,6 @@ Cc: devicetree@vger.kernel.org
  - codec
        Required properties:
                - compatible: "mediatek,mt6397-codec"
+-- 
+1.7.10.4
+
index ca4751c..c08541e 100644 (file)
@@ -1,7 +1,7 @@
-From f97549172878651725a719a4fc4b610613fe5843 Mon Sep 17 00:00:00 2001
+From 8269ed007349714e9ef0e3408a68159d763145dd Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Fri, 8 Jan 2016 08:33:17 +0100
-Subject: [PATCH 43/91] mfd: mt6397: int_con and int_status may vary in
+Subject: [PATCH 043/102] mfd: mt6397: int_con and int_status may vary in
  location
 
 MT6323 has the INT_CON and INT_STATUS located at a different position.
@@ -13,9 +13,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  include/linux/mfd/mt6397/core.h |    2 ++
  2 files changed, 19 insertions(+), 10 deletions(-)
 
+diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
+index 1749c1c..75ad0fe 100644
 --- a/drivers/mfd/mt6397-core.c
 +++ b/drivers/mfd/mt6397-core.c
-@@ -69,8 +69,10 @@ static void mt6397_irq_sync_unlock(struc
+@@ -69,8 +69,10 @@ static void mt6397_irq_sync_unlock(struct irq_data *data)
  {
        struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
  
@@ -28,7 +30,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
        mutex_unlock(&mt6397->irqlock);
  }
-@@ -147,8 +149,8 @@ static irqreturn_t mt6397_irq_thread(int
+@@ -147,8 +149,8 @@ static irqreturn_t mt6397_irq_thread(int irq, void *data)
  {
        struct mt6397_chip *mt6397 = data;
  
@@ -39,7 +41,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
        return IRQ_HANDLED;
  }
-@@ -177,8 +179,8 @@ static int mt6397_irq_init(struct mt6397
+@@ -177,8 +179,8 @@ static int mt6397_irq_init(struct mt6397_chip *mt6397)
        mutex_init(&mt6397->irqlock);
  
        /* Mask all interrupt sources */
@@ -50,7 +52,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
        mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
                MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
-@@ -203,8 +205,8 @@ static int mt6397_irq_suspend(struct dev
+@@ -203,8 +205,8 @@ static int mt6397_irq_suspend(struct device *dev)
  {
        struct mt6397_chip *chip = dev_get_drvdata(dev);
  
@@ -61,7 +63,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
        enable_irq_wake(chip->irq);
  
-@@ -215,8 +217,8 @@ static int mt6397_irq_resume(struct devi
+@@ -215,8 +217,8 @@ static int mt6397_irq_resume(struct device *dev)
  {
        struct mt6397_chip *chip = dev_get_drvdata(dev);
  
@@ -72,7 +74,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
        disable_irq_wake(chip->irq);
  
-@@ -237,6 +239,11 @@ static int mt6397_probe(struct platform_
+@@ -237,6 +239,11 @@ static int mt6397_probe(struct platform_device *pdev)
                return -ENOMEM;
  
        mt6397->dev = &pdev->dev;
@@ -84,6 +86,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        /*
         * mt6397 MFD is child device of soc pmic wrapper.
         * Regmap is set from its parent.
+diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
+index 45b8e8a..d678f52 100644
 --- a/include/linux/mfd/mt6397/core.h
 +++ b/include/linux/mfd/mt6397/core.h
 @@ -60,6 +60,8 @@ struct mt6397_chip {
@@ -95,3 +99,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  };
  
  #endif /* __MFD_MT6397_CORE_H__ */
+-- 
+1.7.10.4
+
index dd3e404..3d0cf28 100644 (file)
@@ -1,13 +1,15 @@
-From 5fbdf1ebc267561781ce812793cd35e63fa39614 Mon Sep 17 00:00:00 2001
+From c6c447480e51301faa2254c7316ab075e20c4b0c Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Fri, 8 Jan 2016 08:41:52 +0100
-Subject: [PATCH 44/91] mfd: mt6397: add support for different Slave types
+Subject: [PATCH 044/102] mfd: mt6397: add support for different Slave types
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
  drivers/mfd/mt6397-core.c |   58 ++++++++++++++++++++++++++++++++-------------
  1 file changed, 41 insertions(+), 17 deletions(-)
 
+diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
+index 75ad0fe..aa91606 100644
 --- a/drivers/mfd/mt6397-core.c
 +++ b/drivers/mfd/mt6397-core.c
 @@ -24,6 +24,9 @@
@@ -20,7 +22,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static const struct resource mt6397_rtc_resources[] = {
        {
                .start = MT6397_RTC_BASE,
-@@ -232,39 +235,60 @@ static SIMPLE_DEV_PM_OPS(mt6397_pm_ops,
+@@ -232,39 +235,60 @@ static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
  static int mt6397_probe(struct platform_device *pdev)
  {
        int ret;
@@ -98,3 +100,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
        return ret;
  }
+-- 
+1.7.10.4
+
index 64c2897..cec58ea 100644 (file)
@@ -1,7 +1,7 @@
-From 2a1c7879d8c3eac4313abc011adbefbc50fd5f92 Mon Sep 17 00:00:00 2001
+From 0ae7153c9f00361c3e6dac9da0c2d994557953f5 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Fri, 8 Jan 2016 04:09:43 +0100
-Subject: [PATCH 45/91] mfd: mt6397: add MT6323 support to MT6397 driver
+Subject: [PATCH 045/102] mfd: mt6397: add MT6323 support to MT6397 driver
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
@@ -12,6 +12,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  create mode 100644 include/linux/mfd/mt6323/core.h
  create mode 100644 include/linux/mfd/mt6323/registers.h
 
+diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
+index aa91606..8234cd3 100644
 --- a/drivers/mfd/mt6397-core.c
 +++ b/drivers/mfd/mt6397-core.c
 @@ -19,11 +19,14 @@
@@ -29,7 +31,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  #define MT6391_CID_CODE               0x91
  #define MT6397_CID_CODE               0x97
  
-@@ -40,6 +43,13 @@ static const struct resource mt6397_rtc_
+@@ -40,6 +43,13 @@ static const struct resource mt6397_rtc_resources[] = {
        },
  };
  
@@ -43,7 +45,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static const struct mfd_cell mt6397_devs[] = {
        {
                .name = "mt6397-rtc",
-@@ -261,6 +271,15 @@ static int mt6397_probe(struct platform_
+@@ -261,6 +271,15 @@ static int mt6397_probe(struct platform_device *pdev)
        }
  
        switch (id & 0xff) {
@@ -59,7 +61,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        case MT6397_CID_CODE:
        case MT6391_CID_CODE:
                pmic->int_con[0] = MT6397_INT_CON0;
-@@ -302,6 +321,7 @@ static int mt6397_remove(struct platform
+@@ -302,6 +321,7 @@ static int mt6397_remove(struct platform_device *pdev)
  
  static const struct of_device_id mt6397_of_match[] = {
        { .compatible = "mediatek,mt6397" },
@@ -67,6 +69,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
        { }
  };
  MODULE_DEVICE_TABLE(of, mt6397_of_match);
+diff --git a/include/linux/mfd/mt6323/core.h b/include/linux/mfd/mt6323/core.h
+new file mode 100644
+index 0000000..06d0ec3
 --- /dev/null
 +++ b/include/linux/mfd/mt6323/core.h
 @@ -0,0 +1,36 @@
@@ -106,6 +111,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +};
 +
 +#endif /* __MFD_MT6323_CORE_H__ */
+diff --git a/include/linux/mfd/mt6323/registers.h b/include/linux/mfd/mt6323/registers.h
+new file mode 100644
+index 0000000..160f3c0
 --- /dev/null
 +++ b/include/linux/mfd/mt6323/registers.h
 @@ -0,0 +1,408 @@
@@ -517,3 +525,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#define MT6323_ACCDET_CON16       0x079A
 +
 +#endif /* __MFD_MT6323_REGISTERS_H__ */
+-- 
+1.7.10.4
+
index 8993004..78cd0c1 100644 (file)
@@ -1,7 +1,7 @@
-From 34177561c62ed881c862f9ece652ca1ca5994796 Mon Sep 17 00:00:00 2001
+From f536a600e0e20fd57475415ce5b3d909441d53b6 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 10 Jan 2016 17:31:46 +0100
-Subject: [PATCH 46/91] regulator: Add document for MT6323 regulator
+Subject: [PATCH 046/102] regulator: Add document for MT6323 regulator
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 Cc: devicetree@vger.kernel.org
@@ -10,6 +10,9 @@ Cc: devicetree@vger.kernel.org
  1 file changed, 239 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
 
+diff --git a/Documentation/devicetree/bindings/regulator/mt6323-regulator.txt b/Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
+new file mode 100644
+index 0000000..9fd95e7
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
 @@ -0,0 +1,239 @@
@@ -252,3 +255,6 @@ Cc: devicetree@vger.kernel.org
 +                      };
 +              };
 +      };
+-- 
+1.7.10.4
+
index 53189a9..d914ece 100644 (file)
@@ -1,7 +1,7 @@
-From 2a33aa927dece6ac6d10caff48897c8ac6a66c1b Mon Sep 17 00:00:00 2001
+From 94c08223cd696d872cda7d9aa4e817956d0a0b84 Mon Sep 17 00:00:00 2001
 From: Chen Zhong <chen.zhong@mediatek.com>
 Date: Fri, 8 Jan 2016 04:17:37 +0100
-Subject: [PATCH 47/91] regulator: mt6323: Add support for MT6323 regulator
+Subject: [PATCH 047/102] regulator: mt6323: Add support for MT6323 regulator
 
 The MT6323 is a regulator found on boards based on MediaTek MT7623 and
 probably other SoCs. It is a so called pmic and connects as a slave to
@@ -18,9 +18,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  create mode 100644 drivers/regulator/mt6323-regulator.c
  create mode 100644 include/linux/regulator/mt6323-regulator.h
 
+diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
+index 8df0b0e..4aec931 100644
 --- a/drivers/regulator/Kconfig
 +++ b/drivers/regulator/Kconfig
-@@ -453,6 +453,15 @@ config REGULATOR_MT6311
+@@ -452,6 +452,15 @@ config REGULATOR_MT6311
          This driver supports the control of different power rails of device
          through regulator interface.
  
@@ -36,9 +38,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  config REGULATOR_MT6397
        tristate "MediaTek MT6397 PMIC"
        depends on MFD_MT6397
+diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
+index 0f81749..b42a84e 100644
 --- a/drivers/regulator/Makefile
 +++ b/drivers/regulator/Makefile
-@@ -60,6 +60,7 @@ obj-$(CONFIG_REGULATOR_MC13783) += mc137
+@@ -60,6 +60,7 @@ obj-$(CONFIG_REGULATOR_MC13783) += mc13783-regulator.o
  obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o
  obj-$(CONFIG_REGULATOR_MC13XXX_CORE) +=  mc13xxx-regulator-core.o
  obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o
@@ -46,6 +50,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  obj-$(CONFIG_REGULATOR_MT6397)        += mt6397-regulator.o
  obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o
  obj-$(CONFIG_REGULATOR_QCOM_SMD_RPM) += qcom_smd-regulator.o
+diff --git a/drivers/regulator/mt6323-regulator.c b/drivers/regulator/mt6323-regulator.c
+new file mode 100644
+index 0000000..28ebbda
 --- /dev/null
 +++ b/drivers/regulator/mt6323-regulator.c
 @@ -0,0 +1,432 @@
@@ -481,6 +488,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +MODULE_AUTHOR("Chen Zhong <chen.zhong@mediatek.com>");
 +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6397 PMIC");
 +MODULE_LICENSE("GPL v2");
+diff --git a/include/linux/regulator/mt6323-regulator.h b/include/linux/regulator/mt6323-regulator.h
+new file mode 100644
+index 0000000..67011cd
 --- /dev/null
 +++ b/include/linux/regulator/mt6323-regulator.h
 @@ -0,0 +1,52 @@
@@ -536,3 +546,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#define MT6323_MAX_REGULATOR  MT6323_ID_RG_MAX
 +
 +#endif /* __LINUX_REGULATOR_MT6323_H */
+-- 
+1.7.10.4
+
index d796c05..b4da16b 100644 (file)
@@ -1,7 +1,7 @@
-From caa2186644606dad07a603905ebabb8068828ebf Mon Sep 17 00:00:00 2001
+From 6efc8d9081b70dcf71d7e8efd7b51d48ee2541be Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 2 Mar 2016 07:18:52 +0100
-Subject: [PATCH 48/91] net-next: mediatek: document MediaTek SoC ethernet
+Subject: [PATCH 048/102] net-next: mediatek: document MediaTek SoC ethernet
  binding
 
 This adds the binding documentation for the MediaTek Ethernet
@@ -15,6 +15,9 @@ Cc: devicetree@vger.kernel.org
  1 file changed, 77 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/net/mediatek-net.txt
 
+diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
+new file mode 100644
+index 0000000..5ca7929
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
 @@ -0,0 +1,77 @@
@@ -95,3 +98,6 @@ Cc: devicetree@vger.kernel.org
 +              };
 +      };
 +};
+-- 
+1.7.10.4
+
index c71f153..5efcc37 100644 (file)
@@ -1,7 +1,7 @@
-From 412449bacdb46b548fd08af19148019e2e979294 Mon Sep 17 00:00:00 2001
+From 8cc84aa65121135d7b120ce71b4f10f81230c818 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 2 Mar 2016 04:27:10 +0100
-Subject: [PATCH 49/91] net-next: mediatek: add support for MT7623 ethernet
+Subject: [PATCH 049/102] net-next: mediatek: add support for MT7623 ethernet
 
 Add ethernet support for MediaTek SoCs from the MT7623 family. These have
 dual GMAC. Depending on the exact version, there might be a built-in
@@ -26,6 +26,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  create mode 100644 drivers/net/ethernet/mediatek/mtk_eth_soc.c
  create mode 100644 drivers/net/ethernet/mediatek/mtk_eth_soc.h
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+new file mode 100644
+index 0000000..ba3afa5
 --- /dev/null
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 @@ -0,0 +1,1807 @@
@@ -1836,6 +1839,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +MODULE_LICENSE("GPL");
 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 +MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+new file mode 100644
+index 0000000..48a5292
 --- /dev/null
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 @@ -0,0 +1,421 @@
@@ -2260,3 +2266,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
 +
 +#endif /* MTK_ETH_H */
+-- 
+1.7.10.4
+
index f14b07a..cc4e671 100644 (file)
@@ -1,7 +1,7 @@
-From 8bc8e78ddec2c93d7fe3487dfdfeedd382e3b96f Mon Sep 17 00:00:00 2001
+From 31e907e5c3c2fc1c94d005bfccdd4a32b5a05f82 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 2 Mar 2016 04:32:43 +0100
-Subject: [PATCH 50/91] net-next: mediatek: add Kconfig and Makefile
+Subject: [PATCH 050/102] net-next: mediatek: add Kconfig and Makefile
 
 This patch adds the Makefile and Kconfig required to make the driver build.
 
@@ -15,6 +15,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  create mode 100644 drivers/net/ethernet/mediatek/Kconfig
  create mode 100644 drivers/net/ethernet/mediatek/Makefile
 
+diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
+index 31c5e47..cd28b95 100644
 --- a/drivers/net/ethernet/Kconfig
 +++ b/drivers/net/ethernet/Kconfig
 @@ -106,6 +106,7 @@ config LANTIQ_ETOP
@@ -25,6 +27,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  source "drivers/net/ethernet/mellanox/Kconfig"
  source "drivers/net/ethernet/micrel/Kconfig"
  source "drivers/net/ethernet/microchip/Kconfig"
+diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
+index 071f84e..c62191f 100644
 --- a/drivers/net/ethernet/Makefile
 +++ b/drivers/net/ethernet/Makefile
 @@ -46,6 +46,7 @@ obj-$(CONFIG_JME) += jme.o
@@ -35,6 +39,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
  obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/
  obj-$(CONFIG_NET_VENDOR_MICROCHIP) += microchip/
+diff --git a/drivers/net/ethernet/mediatek/Kconfig b/drivers/net/ethernet/mediatek/Kconfig
+new file mode 100644
+index 0000000..b0229f4
 --- /dev/null
 +++ b/drivers/net/ethernet/mediatek/Kconfig
 @@ -0,0 +1,17 @@
@@ -55,6 +62,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +        MediaTek MT2701/MT7623 chipset family.
 +
 +endif #NET_VENDOR_MEDIATEK
+diff --git a/drivers/net/ethernet/mediatek/Makefile b/drivers/net/ethernet/mediatek/Makefile
+new file mode 100644
+index 0000000..aa3f1c8
 --- /dev/null
 +++ b/drivers/net/ethernet/mediatek/Makefile
 @@ -0,0 +1,5 @@
@@ -63,3 +73,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#
 +
 +obj-$(CONFIG_NET_MEDIATEK_SOC)                        += mtk_eth_soc.o
+-- 
+1.7.10.4
+
index 7d7c72f..d3f84ab 100644 (file)
@@ -1,7 +1,7 @@
-From d9b93fb0d4021694a2b7e47981cd9de67e83aa05 Mon Sep 17 00:00:00 2001
+From 514e4ce65a5f1b5bfa3cbca153f672844f093f0e Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 2 Mar 2016 04:34:04 +0100
-Subject: [PATCH 51/91] net-next: mediatek: add an entry to MAINTAINERS
+Subject: [PATCH 051/102] net-next: mediatek: add an entry to MAINTAINERS
 
 Add myself and Felix as the Maintainers for the MediaTek ethernet driver.
 
@@ -11,9 +11,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  MAINTAINERS |    7 +++++++
  1 file changed, 7 insertions(+)
 
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 233f834..73f0592 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -6907,6 +6907,13 @@ F:      include/uapi/linux/meye.h
+@@ -6902,6 +6902,13 @@ F:      include/uapi/linux/meye.h
  F:    include/uapi/linux/ivtv*
  F:    include/uapi/linux/uvcvideo.h
  
@@ -27,3 +29,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  MEDIATEK MT7601U WIRELESS LAN DRIVER
  M:    Jakub Kicinski <kubakici@wp.pl>
  L:    linux-wireless@vger.kernel.org
+-- 
+1.7.10.4
+
diff --git a/target/linux/mediatek/patches-4.4/0052-clk-dont-disable-unused-clocks.patch b/target/linux/mediatek/patches-4.4/0052-clk-dont-disable-unused-clocks.patch
new file mode 100644 (file)
index 0000000..277fbca
--- /dev/null
@@ -0,0 +1,26 @@
+From 5238c5d1d38661955ed3b52f45c46e00bfc9eb6e Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Apr 2016 07:18:35 +0200
+Subject: [PATCH 052/102] clk: dont disable unused clocks
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/clk/clk.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
+index f13c3f4..5e9ddae 100644
+--- a/drivers/clk/clk.c
++++ b/drivers/clk/clk.c
+@@ -233,7 +233,7 @@ unlock_out:
+       clk_enable_unlock(flags);
+ }
+-static bool clk_ignore_unused;
++static bool clk_ignore_unused = true;
+ static int __init clk_ignore_unused_setup(char *__unused)
+ {
+       clk_ignore_unused = true;
+-- 
+1.7.10.4
+
diff --git a/target/linux/mediatek/patches-4.4/0052-mtd-nand-add-an-mtd_to_nand-helper.patch b/target/linux/mediatek/patches-4.4/0052-mtd-nand-add-an-mtd_to_nand-helper.patch
deleted file mode 100644 (file)
index 58a7f55..0000000
+++ /dev/null
@@ -1,30 +0,0 @@
-From 69a0df9dd942799651a7ec06b3cfe7fc43b2e32a Mon Sep 17 00:00:00 2001
-From: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Date: Mon, 16 Nov 2015 14:37:35 +0100
-Subject: [PATCH 52/91] mtd: nand: add an mtd_to_nand() helper
-
-Some drivers are retrieving the nand_chip pointer using the container_of
-macro on a struct wrapping both the nand_chip and the mtd_info struct while
-the standard way of retrieving this pointer is through mtd->priv.
-Provide an helper to do that.
-
-Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- include/linux/mtd/nand.h |    5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -719,6 +719,11 @@ struct nand_chip {
-       void *priv;
- };
-+static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
-+{
-+      return mtd->priv;
-+}
-+
- /*
-  * NAND Flash Manufacturer ID Codes
-  */
diff --git a/target/linux/mediatek/patches-4.4/0053-clk-mediatek-enable-critical-clocks.patch b/target/linux/mediatek/patches-4.4/0053-clk-mediatek-enable-critical-clocks.patch
new file mode 100644 (file)
index 0000000..f22f786
--- /dev/null
@@ -0,0 +1,74 @@
+From c8fd103d6c07af5db47f061b70759b7c69169656 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 31 Mar 2016 06:46:51 +0200
+Subject: [PATCH 053/102] clk: mediatek: enable critical clocks
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/clk/mediatek/clk-mt2701.c |   22 ++++++++++++++++++++--
+ 1 file changed, 20 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+index 812b347..1634288 100644
+--- a/drivers/clk/mediatek/clk-mt2701.c
++++ b/drivers/clk/mediatek/clk-mt2701.c
+@@ -573,6 +573,20 @@ static const struct mtk_gate top_clks[] __initconst = {
+       GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div", 28),
+ };
++static struct clk_onecell_data *mt7623_top_clk_data __initdata;
++static struct clk_onecell_data *mt7623_pll_clk_data __initdata;
++
++static void __init mtk_clk_enable_critical(void)
++{
++      if (!mt7623_top_clk_data || !mt7623_pll_clk_data)
++              return;
++
++      clk_prepare_enable(mt7623_pll_clk_data->clks[CLK_APMIXED_ARMPLL]);
++      clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_MEM_SEL]);
++      clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
++      clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_RTC_SEL]);
++}
++
+ static void __init mtk_topckgen_init(struct device_node *node)
+ {
+       struct clk_onecell_data *clk_data;
+@@ -585,7 +599,7 @@ static void __init mtk_topckgen_init(struct device_node *node)
+               return;
+       }
+-      clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
++      mt7623_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
+       mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+                                                               clk_data);
+@@ -606,6 +620,8 @@ static void __init mtk_topckgen_init(struct device_node *node)
+       if (r)
+               pr_err("%s(): could not register clock provider: %d\n",
+                       __func__, r);
++
++      mtk_clk_enable_critical();
+ }
+ CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt2701-topckgen", mtk_topckgen_init);
+@@ -1202,7 +1218,7 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
+       struct clk_onecell_data *clk_data;
+       int r;
+-      clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
++      mt7623_pll_clk_data = clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
+       if (!clk_data)
+               return;
+@@ -1213,6 +1229,8 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
+       if (r)
+               pr_err("%s(): could not register clock provider: %d\n",
+                       __func__, r);
++
++      mtk_clk_enable_critical();
+ }
+ CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt2701-apmixedsys",
+                                                       mtk_apmixedsys_init);
+-- 
+1.7.10.4
+
diff --git a/target/linux/mediatek/patches-4.4/0053-mtd-nand-add-nand_to_mtd-helper.patch b/target/linux/mediatek/patches-4.4/0053-mtd-nand-add-nand_to_mtd-helper.patch
deleted file mode 100644 (file)
index 075cebe..0000000
+++ /dev/null
@@ -1,27 +0,0 @@
-From 833645b92150d74642829c24c0ca1fbbdeccfb5c Mon Sep 17 00:00:00 2001
-From: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Date: Tue, 1 Dec 2015 12:03:07 +0100
-Subject: [PATCH 53/91] mtd: nand: add nand_to_mtd() helper
-
-Add a new helper to retrieve the MTD device attached to a NAND chip.
-
-Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- include/linux/mtd/nand.h |    5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -724,6 +724,11 @@ static inline struct nand_chip *mtd_to_n
-       return mtd->priv;
- }
-+static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
-+{
-+      return &chip->mtd;
-+}
-+
- /*
-  * NAND Flash Manufacturer ID Codes
-  */
diff --git a/target/linux/mediatek/patches-4.4/0054-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch b/target/linux/mediatek/patches-4.4/0054-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch
new file mode 100644 (file)
index 0000000..057f95e
--- /dev/null
@@ -0,0 +1,306 @@
+From 1387d4f0ebf4b48c09f2ea0d27a02936c3fa0010 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 31 Mar 2016 02:26:37 +0200
+Subject: [PATCH 054/102] clk: mediatek: Export CPU mux clocks for CPU
+ frequency control
+
+This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
+for intermediate clock source switching.
+
+Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
+---
+ drivers/clk/mediatek/Makefile          |    2 +-
+ drivers/clk/mediatek/clk-cpumux.c      |  127 ++++++++++++++++++++++++++++++++
+ drivers/clk/mediatek/clk-cpumux.h      |   22 ++++++
+ drivers/clk/mediatek/clk-mt2701.c      |    8 ++
+ drivers/clk/mediatek/clk-mt8173.c      |   23 ++++++
+ include/dt-bindings/clock/mt2701-clk.h |    3 +-
+ include/dt-bindings/clock/mt8173-clk.h |    4 +-
+ 7 files changed, 186 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/clk/mediatek/clk-cpumux.c
+ create mode 100644 drivers/clk/mediatek/clk-cpumux.h
+
+diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
+index 5b2b91b..76bfab6 100644
+--- a/drivers/clk/mediatek/Makefile
++++ b/drivers/clk/mediatek/Makefile
+@@ -1,4 +1,4 @@
+-obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
++obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o
+ obj-$(CONFIG_RESET_CONTROLLER) += reset.o
+ obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
+ obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
+diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c
+new file mode 100644
+index 0000000..91b5238
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-cpumux.c
+@@ -0,0 +1,127 @@
++/*
++ * Copyright (c) 2015 Linaro Ltd.
++ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/mfd/syscon.h>
++#include <linux/slab.h>
++
++#include "clk-mtk.h"
++#include "clk-cpumux.h"
++
++struct mtk_clk_cpumux {
++      struct clk_hw   hw;
++      struct regmap   *regmap;
++      u32             reg;
++      u32             mask;
++      u8              shift;
++};
++
++static inline struct mtk_clk_cpumux *to_clk_mux(struct clk_hw *_hw)
++{
++      return container_of(_hw, struct mtk_clk_cpumux, hw);
++}
++
++static u8 clk_cpumux_get_parent(struct clk_hw *hw)
++{
++      struct mtk_clk_cpumux *mux = to_clk_mux(hw);
++      int num_parents = clk_hw_get_num_parents(hw);
++      unsigned int val;
++
++      regmap_read(mux->regmap, mux->reg, &val);
++
++      val >>= mux->shift;
++      val &= mux->mask;
++
++      if (val >= num_parents)
++              return -EINVAL;
++
++      return val;
++}
++
++static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
++{
++      struct mtk_clk_cpumux *mux = to_clk_mux(hw);
++      u32 mask, val;
++
++      val = index << mux->shift;
++      mask = mux->mask << mux->shift;
++
++      return regmap_update_bits(mux->regmap, mux->reg, mask, val);
++}
++
++static const struct clk_ops clk_cpumux_ops = {
++      .get_parent = clk_cpumux_get_parent,
++      .set_parent = clk_cpumux_set_parent,
++};
++
++static struct clk __init *mtk_clk_register_cpumux(const struct mtk_composite *mux,
++                                         struct regmap *regmap)
++{
++      struct mtk_clk_cpumux *cpumux;
++      struct clk *clk;
++      struct clk_init_data init;
++
++      cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
++      if (!cpumux)
++              return ERR_PTR(-ENOMEM);
++
++      init.name = mux->name;
++      init.ops = &clk_cpumux_ops;
++      init.parent_names = mux->parent_names;
++      init.num_parents = mux->num_parents;
++      init.flags = mux->flags;
++
++      cpumux->reg = mux->mux_reg;
++      cpumux->shift = mux->mux_shift;
++      cpumux->mask = BIT(mux->mux_width) - 1;
++      cpumux->regmap = regmap;
++      cpumux->hw.init = &init;
++
++      clk = clk_register(NULL, &cpumux->hw);
++      if (IS_ERR(clk))
++              kfree(cpumux);
++
++      return clk;
++}
++
++int __init mtk_clk_register_cpumuxes(struct device_node *node,
++                            const struct mtk_composite *clks, int num,
++                            struct clk_onecell_data *clk_data)
++{
++      int i;
++      struct clk *clk;
++      struct regmap *regmap;
++
++      regmap = syscon_node_to_regmap(node);
++      if (IS_ERR(regmap)) {
++              pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
++                     PTR_ERR(regmap));
++              return PTR_ERR(regmap);
++      }
++
++      for (i = 0; i < num; i++) {
++              const struct mtk_composite *mux = &clks[i];
++
++              clk = mtk_clk_register_cpumux(mux, regmap);
++              if (IS_ERR(clk)) {
++                      pr_err("Failed to register clk %s: %ld\n",
++                             mux->name, PTR_ERR(clk));
++                      continue;
++              }
++
++              clk_data->clks[mux->id] = clk;
++      }
++
++      return 0;
++}
+diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h
+new file mode 100644
+index 0000000..52c769f
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-cpumux.h
+@@ -0,0 +1,22 @@
++/*
++ * Copyright (c) 2015 Linaro Ltd.
++ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef __DRV_CLK_CPUMUX_H
++#define __DRV_CLK_CPUMUX_H
++
++int mtk_clk_register_cpumuxes(struct device_node *node,
++                            const struct mtk_composite *clks, int num,
++                            struct clk_onecell_data *clk_data);
++
++#endif /* __DRV_CLK_CPUMUX_H */
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+index 1634288..5c37fcb 100644
+--- a/drivers/clk/mediatek/clk-mt2701.c
++++ b/drivers/clk/mediatek/clk-mt2701.c
+@@ -18,6 +18,7 @@
+ #include "clk-mtk.h"
+ #include "clk-gate.h"
++#include "clk-cpumux.h"
+ #include <dt-bindings/clock/mt2701-clk.h>
+@@ -465,6 +466,10 @@ static const char * const cpu_parents[] __initconst = {
+       "mmpll"
+ };
++static const struct mtk_composite cpu_muxes[] __initconst = {
++      MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
++};
++
+ static const struct mtk_composite top_muxes[] __initconst = {
+       MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
+               0x0040, 0, 3, INVALID_MUX_GATE_BIT),
+@@ -677,6 +682,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
+       mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
+                                               clk_data);
++      mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
++                                              clk_data);
++
+       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+       if (r)
+               pr_err("%s(): could not register clock provider: %d\n",
+diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
+index 227e356..b82c0e2 100644
+--- a/drivers/clk/mediatek/clk-mt8173.c
++++ b/drivers/clk/mediatek/clk-mt8173.c
+@@ -18,6 +18,7 @@
+ #include "clk-mtk.h"
+ #include "clk-gate.h"
++#include "clk-cpumux.h"
+ #include <dt-bindings/clock/mt8173-clk.h>
+@@ -526,6 +527,25 @@ static const char * const i2s3_b_ck_parents[] __initconst = {
+       "apll2_div5"
+ };
++static const char * const ca53_parents[] __initconst = {
++      "clk26m",
++      "armca7pll",
++      "mainpll",
++      "univpll"
++};
++
++static const char * const ca57_parents[] __initconst = {
++      "clk26m",
++      "armca15pll",
++      "mainpll",
++      "univpll"
++};
++
++static const struct mtk_composite cpu_muxes[] __initconst = {
++      MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
++      MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2),
++};
++
+ static const struct mtk_composite top_muxes[] __initconst = {
+       /* CLK_CFG_0 */
+       MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
+@@ -945,6 +965,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
+                                               clk_data);
+       mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
++      mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
++                                              clk_data);
++
+       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+       if (r)
+               pr_err("%s(): could not register clock provider: %d\n",
+diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
+index 50972d1..a6c63b8 100644
+--- a/include/dt-bindings/clock/mt2701-clk.h
++++ b/include/dt-bindings/clock/mt2701-clk.h
+@@ -217,7 +217,8 @@
+ #define CLK_INFRA_PMICWRAP                    17
+ #define CLK_INFRA_DDCCI                               18
+ #define CLK_INFRA_CLK_13M                       19
+-#define CLK_INFRA_NR                          20
++#define CLK_INFRA_CPUSEL                      20
++#define CLK_INFRA_NR                          21
+ /* PERICFG */
+diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
+index 7956ba1..c82ed7c 100644
+--- a/include/dt-bindings/clock/mt8173-clk.h
++++ b/include/dt-bindings/clock/mt8173-clk.h
+@@ -192,7 +192,9 @@
+ #define CLK_INFRA_PMICSPI             10
+ #define CLK_INFRA_PMICWRAP            11
+ #define CLK_INFRA_CLK_13M             12
+-#define CLK_INFRA_NR_CLK              13
++#define CLK_INFRA_CA53SEL             13
++#define CLK_INFRA_CA57SEL             14
++#define CLK_INFRA_NR_CLK              15
+ /* PERI_SYS */
+-- 
+1.7.10.4
+
diff --git a/target/linux/mediatek/patches-4.4/0054-mtd-nand-add-helpers-to-access-priv.patch b/target/linux/mediatek/patches-4.4/0054-mtd-nand-add-helpers-to-access-priv.patch
deleted file mode 100644 (file)
index 3c25e20..0000000
+++ /dev/null
@@ -1,34 +0,0 @@
-From af8437ee10a6304da30ca479480102b464b39c82 Mon Sep 17 00:00:00 2001
-From: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Date: Thu, 10 Dec 2015 09:00:39 +0100
-Subject: [PATCH 54/91] mtd: nand: add helpers to access ->priv
-
-Add two helpers to access the field reserved for private controller data.
-This makes it clearer what this field is reserved for and ease future
-refactoring.
-
-Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- include/linux/mtd/nand.h |   10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -729,6 +729,16 @@ static inline struct mtd_info *nand_to_m
-       return &chip->mtd;
- }
-+static inline void *nand_get_controller_data(struct nand_chip *chip)
-+{
-+      return chip->priv;
-+}
-+
-+static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
-+{
-+      chip->priv = priv;
-+}
-+
- /*
-  * NAND Flash Manufacturer ID Codes
-  */
diff --git a/target/linux/mediatek/patches-4.4/0055-cpufreq-mediatek-add-driver.patch b/target/linux/mediatek/patches-4.4/0055-cpufreq-mediatek-add-driver.patch
new file mode 100644 (file)
index 0000000..897b8c7
--- /dev/null
@@ -0,0 +1,443 @@
+From 60f4e41b367bdb29530468c91c1e613b17a37755 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 30 Mar 2016 23:48:53 +0200
+Subject: [PATCH 055/102] cpufreq: mediatek: add driver
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/cpufreq/Kconfig.arm      |    9 +
+ drivers/cpufreq/Makefile         |    1 +
+ drivers/cpufreq/mt7623-cpufreq.c |  389 ++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 399 insertions(+)
+ create mode 100644 drivers/cpufreq/mt7623-cpufreq.c
+
+diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
+index b1f8a73..baf945e 100644
+--- a/drivers/cpufreq/Kconfig.arm
++++ b/drivers/cpufreq/Kconfig.arm
+@@ -81,6 +81,15 @@ config ARM_KIRKWOOD_CPUFREQ
+         This adds the CPUFreq driver for Marvell Kirkwood
+         SoCs.
++config ARM_MT7623_CPUFREQ
++      bool "Mediatek MT7623 CPUFreq support"
++      depends on ARCH_MEDIATEK && REGULATOR
++      depends on ARM || (ARM_CPU_TOPOLOGY && COMPILE_TEST)
++      depends on !CPU_THERMAL || THERMAL=y
++      select PM_OPP
++      help
++        This adds the CPUFreq driver support for Mediatek MT7623 SoC.
++
+ config ARM_MT8173_CPUFREQ
+       bool "Mediatek MT8173 CPUFreq support"
+       depends on ARCH_MEDIATEK && REGULATOR
+diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
+index c0af1a1..e198752 100644
+--- a/drivers/cpufreq/Makefile
++++ b/drivers/cpufreq/Makefile
+@@ -57,6 +57,7 @@ obj-$(CONFIG_ARM_HISI_ACPU_CPUFREQ)  += hisi-acpu-cpufreq.o
+ obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)               += imx6q-cpufreq.o
+ obj-$(CONFIG_ARM_INTEGRATOR)          += integrator-cpufreq.o
+ obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ)    += kirkwood-cpufreq.o
++obj-$(CONFIG_ARM_MT7623_CPUFREQ)      += mt7623-cpufreq.o
+ obj-$(CONFIG_ARM_MT8173_CPUFREQ)      += mt8173-cpufreq.o
+ obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)   += omap-cpufreq.o
+ obj-$(CONFIG_ARM_PXA2xx_CPUFREQ)      += pxa2xx-cpufreq.o
+diff --git a/drivers/cpufreq/mt7623-cpufreq.c b/drivers/cpufreq/mt7623-cpufreq.c
+new file mode 100644
+index 0000000..8d154ce
+--- /dev/null
++++ b/drivers/cpufreq/mt7623-cpufreq.c
+@@ -0,0 +1,389 @@
++/*
++ * Copyright (c) 2015 Linaro Ltd.
++ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk.h>
++#include <linux/cpu.h>
++#include <linux/cpu_cooling.h>
++#include <linux/cpufreq.h>
++#include <linux/cpumask.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pm_opp.h>
++#include <linux/regulator/consumer.h>
++#include <linux/slab.h>
++#include <linux/thermal.h>
++
++#define VOLT_TOL              (10000)
++
++/*
++ * When scaling the clock frequency of a CPU clock domain, the clock source
++ * needs to be switched to another stable PLL clock temporarily until
++ * the original PLL becomes stable at target frequency.
++ */
++struct mtk_cpu_dvfs_info {
++      struct device *cpu_dev;
++      struct regulator *proc_reg;
++      struct clk *cpu_clk;
++      struct clk *inter_clk;
++      struct thermal_cooling_device *cdev;
++      int intermediate_voltage;
++};
++
++static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
++{
++      return regulator_set_voltage(info->proc_reg, vproc,
++                                   vproc + VOLT_TOL);
++}
++
++static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
++                                unsigned int index)
++{
++      struct cpufreq_frequency_table *freq_table = policy->freq_table;
++      struct clk *cpu_clk = policy->clk;
++      struct clk *armpll = clk_get_parent(cpu_clk);
++      struct mtk_cpu_dvfs_info *info = policy->driver_data;
++      struct device *cpu_dev = info->cpu_dev;
++      struct dev_pm_opp *opp;
++      long freq_hz, old_freq_hz;
++      int vproc, old_vproc, inter_vproc, target_vproc, ret;
++
++      inter_vproc = info->intermediate_voltage;
++
++      old_freq_hz = clk_get_rate(cpu_clk);
++      old_vproc = regulator_get_voltage(info->proc_reg);
++
++      freq_hz = freq_table[index].frequency * 1000;
++
++      rcu_read_lock();
++      opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
++      if (IS_ERR(opp)) {
++              rcu_read_unlock();
++              pr_err("cpu%d: failed to find OPP for %ld\n",
++                     policy->cpu, freq_hz);
++              return PTR_ERR(opp);
++      }
++      vproc = dev_pm_opp_get_voltage(opp);
++      rcu_read_unlock();
++
++      /*
++       * If the new voltage or the intermediate voltage is higher than the
++       * current voltage, scale up voltage first.
++       */
++      target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
++      if (old_vproc < target_vproc) {
++              ret = mtk_cpufreq_set_voltage(info, target_vproc);
++              if (ret) {
++                      pr_err("cpu%d: failed to scale up voltage!\n",
++                             policy->cpu);
++                      mtk_cpufreq_set_voltage(info, old_vproc);
++                      return ret;
++              }
++      }
++
++      /* Reparent the CPU clock to intermediate clock. */
++      ret = clk_set_parent(cpu_clk, info->inter_clk);
++      if (ret) {
++              pr_err("cpu%d: failed to re-parent cpu clock!\n",
++                     policy->cpu);
++              mtk_cpufreq_set_voltage(info, old_vproc);
++              WARN_ON(1);
++              return ret;
++      }
++
++      /* Set the original PLL to target rate. */
++      ret = clk_set_rate(armpll, freq_hz);
++      if (ret) {
++              pr_err("cpu%d: failed to scale cpu clock rate!\n",
++                     policy->cpu);
++              clk_set_parent(cpu_clk, armpll);
++              mtk_cpufreq_set_voltage(info, old_vproc);
++              return ret;
++      }
++
++      /* Set parent of CPU clock back to the original PLL. */
++      ret = clk_set_parent(cpu_clk, armpll);
++      if (ret) {
++              pr_err("cpu%d: failed to re-parent cpu clock!\n",
++                     policy->cpu);
++              mtk_cpufreq_set_voltage(info, inter_vproc);
++              WARN_ON(1);
++              return ret;
++      }
++
++      /*
++       * If the new voltage is lower than the intermediate voltage or the
++       * original voltage, scale down to the new voltage.
++       */
++      if (vproc < inter_vproc || vproc < old_vproc) {
++              ret = mtk_cpufreq_set_voltage(info, vproc);
++              if (ret) {
++                      pr_err("cpu%d: failed to scale down voltage!\n",
++                             policy->cpu);
++                      clk_set_parent(cpu_clk, info->inter_clk);
++                      clk_set_rate(armpll, old_freq_hz);
++                      clk_set_parent(cpu_clk, armpll);
++                      return ret;
++              }
++      }
++
++      return 0;
++}
++
++static void mtk_cpufreq_ready(struct cpufreq_policy *policy)
++{
++      struct mtk_cpu_dvfs_info *info = policy->driver_data;
++      struct device_node *np = of_node_get(info->cpu_dev->of_node);
++
++      if (WARN_ON(!np))
++              return;
++
++      if (of_find_property(np, "#cooling-cells", NULL)) {
++              info->cdev = of_cpufreq_cooling_register(np,
++                                                       policy->related_cpus);
++
++              if (IS_ERR(info->cdev)) {
++                      dev_err(info->cpu_dev,
++                              "running cpufreq without cooling device: %ld\n",
++                              PTR_ERR(info->cdev));
++
++                      info->cdev = NULL;
++              }
++      }
++
++      of_node_put(np);
++}
++
++static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
++{
++      struct device *cpu_dev;
++      struct regulator *proc_reg = ERR_PTR(-ENODEV);
++      struct clk *cpu_clk = ERR_PTR(-ENODEV);
++      struct clk *inter_clk = ERR_PTR(-ENODEV);
++      struct dev_pm_opp *opp;
++      unsigned long rate;
++      int ret;
++
++      cpu_dev = get_cpu_device(cpu);
++      if (!cpu_dev) {
++              pr_err("failed to get cpu%d device\n", cpu);
++              return -ENODEV;
++      }
++
++      cpu_clk = clk_get(cpu_dev, "cpu");
++      if (IS_ERR(cpu_clk)) {
++              if (PTR_ERR(cpu_clk) == -EPROBE_DEFER)
++                      pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu);
++              else
++                      pr_err("failed to get cpu clk for cpu%d\n", cpu);
++
++              ret = PTR_ERR(cpu_clk);
++              return ret;
++      }
++
++      inter_clk = clk_get(cpu_dev, "intermediate");
++      if (IS_ERR(inter_clk)) {
++              if (PTR_ERR(inter_clk) == -EPROBE_DEFER)
++                      pr_warn("intermediate clk for cpu%d not ready, retry.\n",
++                              cpu);
++              else
++                      pr_err("failed to get intermediate clk for cpu%d\n",
++                             cpu);
++
++              ret = PTR_ERR(inter_clk);
++              goto out_free_resources;
++      }
++
++      proc_reg = regulator_get_exclusive(cpu_dev, "proc");
++      if (IS_ERR(proc_reg)) {
++              if (PTR_ERR(proc_reg) == -EPROBE_DEFER)
++                      pr_warn("proc regulator for cpu%d not ready, retry.\n",
++                              cpu);
++              else
++                      pr_err("failed to get proc regulator for cpu%d\n",
++                             cpu);
++
++              ret = PTR_ERR(proc_reg);
++              goto out_free_resources;
++      }
++
++      ret = dev_pm_opp_of_add_table(cpu_dev);
++      if (ret) {
++              pr_warn("no OPP table for cpu%d\n", cpu);
++              goto out_free_resources;
++      }
++
++      /* Search a safe voltage for intermediate frequency. */
++      rate = clk_get_rate(inter_clk);
++      rcu_read_lock();
++      opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
++      if (IS_ERR(opp)) {
++              rcu_read_unlock();
++              pr_err("failed to get intermediate opp for cpu%d\n", cpu);
++              ret = PTR_ERR(opp);
++              goto out_free_opp_table;
++      }
++      info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
++      rcu_read_unlock();
++
++      info->cpu_dev = cpu_dev;
++      info->proc_reg = proc_reg;
++      info->cpu_clk = cpu_clk;
++      info->inter_clk = inter_clk;
++
++      return 0;
++
++out_free_opp_table:
++      dev_pm_opp_of_remove_table(cpu_dev);
++
++out_free_resources:
++      if (!IS_ERR(proc_reg))
++              regulator_put(proc_reg);
++      if (!IS_ERR(cpu_clk))
++              clk_put(cpu_clk);
++      if (!IS_ERR(inter_clk))
++              clk_put(inter_clk);
++
++      return ret;
++}
++
++static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
++{
++      if (!IS_ERR(info->proc_reg))
++              regulator_put(info->proc_reg);
++      if (!IS_ERR(info->cpu_clk))
++              clk_put(info->cpu_clk);
++      if (!IS_ERR(info->inter_clk))
++              clk_put(info->inter_clk);
++
++      dev_pm_opp_of_remove_table(info->cpu_dev);
++}
++
++static int mtk_cpufreq_init(struct cpufreq_policy *policy)
++{
++      struct mtk_cpu_dvfs_info *info;
++      struct cpufreq_frequency_table *freq_table;
++      int ret;
++
++      info = kzalloc(sizeof(*info), GFP_KERNEL);
++      if (!info)
++              return -ENOMEM;
++
++      ret = mtk_cpu_dvfs_info_init(info, policy->cpu);
++      if (ret) {
++              pr_err("%s failed to initialize dvfs info for cpu%d\n",
++                     __func__, policy->cpu);
++              goto out_free_dvfs_info;
++      }
++
++      ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table);
++      if (ret) {
++              pr_err("failed to init cpufreq table for cpu%d: %d\n",
++                     policy->cpu, ret);
++              goto out_release_dvfs_info;
++      }
++
++      ret = cpufreq_table_validate_and_show(policy, freq_table);
++      if (ret) {
++              pr_err("%s: invalid frequency table: %d\n", __func__, ret);
++              goto out_free_cpufreq_table;
++      }
++
++      /* CPUs in the same cluster share a clock and power domain. */
++      cpumask_setall(policy->cpus);
++      policy->driver_data = info;
++      policy->clk = info->cpu_clk;
++
++      return 0;
++
++out_free_cpufreq_table:
++      dev_pm_opp_free_cpufreq_table(info->cpu_dev, &freq_table);
++
++out_release_dvfs_info:
++      mtk_cpu_dvfs_info_release(info);
++
++out_free_dvfs_info:
++      kfree(info);
++
++      return ret;
++}
++
++static int mtk_cpufreq_exit(struct cpufreq_policy *policy)
++{
++      struct mtk_cpu_dvfs_info *info = policy->driver_data;
++
++      cpufreq_cooling_unregister(info->cdev);
++      dev_pm_opp_free_cpufreq_table(info->cpu_dev, &policy->freq_table);
++      mtk_cpu_dvfs_info_release(info);
++      kfree(info);
++
++      return 0;
++}
++
++static struct cpufreq_driver mt7623_cpufreq_driver = {
++      .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
++      .verify = cpufreq_generic_frequency_table_verify,
++      .target_index = mtk_cpufreq_set_target,
++      .get = cpufreq_generic_get,
++      .init = mtk_cpufreq_init,
++      .exit = mtk_cpufreq_exit,
++      .ready = mtk_cpufreq_ready,
++      .name = "mtk-cpufreq",
++      .attr = cpufreq_generic_attr,
++};
++
++static int mt7623_cpufreq_probe(struct platform_device *pdev)
++{
++      int ret;
++
++      ret = cpufreq_register_driver(&mt7623_cpufreq_driver);
++      if (ret)
++              pr_err("failed to register mtk cpufreq driver\n");
++
++      return ret;
++}
++
++static struct platform_driver mt7623_cpufreq_platdrv = {
++      .driver = {
++              .name   = "mt7623-cpufreq",
++      },
++      .probe          = mt7623_cpufreq_probe,
++};
++
++static int mt7623_cpufreq_driver_init(void)
++{
++      struct platform_device *pdev;
++      int err;
++
++      if (!of_machine_is_compatible("mediatek,mt7623"))
++              return -ENODEV;
++
++      err = platform_driver_register(&mt7623_cpufreq_platdrv);
++      if (err)
++              return err;
++
++      /*
++       * Since there's no place to hold device registration code and no
++       * device tree based way to match cpufreq driver yet, both the driver
++       * and the device registration codes are put here to handle defer
++       * probing.
++       */
++      pdev = platform_device_register_simple("mt7623-cpufreq", -1, NULL, 0);
++      if (IS_ERR(pdev)) {
++              pr_err("failed to register mtk-cpufreq platform device\n");
++              return PTR_ERR(pdev);
++      }
++
++      return 0;
++}
++device_initcall(mt7623_cpufreq_driver_init);
+-- 
+1.7.10.4
+
diff --git a/target/linux/mediatek/patches-4.4/0055-mtd-nand-embed-an-mtd_info-structure-into-nand_chip.patch b/target/linux/mediatek/patches-4.4/0055-mtd-nand-embed-an-mtd_info-structure-into-nand_chip.patch
deleted file mode 100644 (file)
index b24e760..0000000
+++ /dev/null
@@ -1,37 +0,0 @@
-From f18fcf4468ffdce17747f3d331f998a7e9264142 Mon Sep 17 00:00:00 2001
-From: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Date: Tue, 1 Dec 2015 12:03:06 +0100
-Subject: [PATCH 55/91] mtd: nand: embed an mtd_info structure into nand_chip
-
-Currently all NAND controller drivers are providing both the mtd_info and
-nand_chip struct and then let the NAND subsystem to initialize a few
-things before registering the mtd instance to the MTD layer.
-Embed an mtd_info field into nand_chip to add some consistency to all NAND
-controller drivers.
-This change will also help factorizing boilerplate code copied in all NAND
-drivers.
-
-Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- include/linux/mtd/nand.h |    2 ++
- 1 file changed, 2 insertions(+)
-
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -540,6 +540,7 @@ struct nand_buffers {
- /**
-  * struct nand_chip - NAND Private Flash Chip Data
-+ * @mtd:              MTD device registered to the MTD framework
-  * @IO_ADDR_R:                [BOARDSPECIFIC] address to read the 8 I/O lines of the
-  *                    flash device
-  * @IO_ADDR_W:                [BOARDSPECIFIC] address to write the 8 I/O lines of the
-@@ -640,6 +641,7 @@ struct nand_buffers {
-  */
- struct nand_chip {
-+      struct mtd_info mtd;
-       void __iomem *IO_ADDR_R;
-       void __iomem *IO_ADDR_W;
diff --git a/target/linux/mediatek/patches-4.4/0056-arm-mediatek-make-a7-timer-work-Signed-off-by-John-C.patch b/target/linux/mediatek/patches-4.4/0056-arm-mediatek-make-a7-timer-work-Signed-off-by-John-C.patch
new file mode 100644 (file)
index 0000000..18ecb80
--- /dev/null
@@ -0,0 +1,38 @@
+From f8cda0bc698706413b5dd6fde827f9a2601ac61b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 31 Mar 2016 06:07:01 +0200
+Subject: [PATCH 056/102] arm: mediatek: make a7 timer work Signed-off-by:
+ John Crispin <blogic@openwrt.org>
+
+---
+ arch/arm/mach-mediatek/Kconfig    |    1 +
+ arch/arm/mach-mediatek/mediatek.c |    1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
+index a7fef77..2c05bc31 100644
+--- a/arch/arm/mach-mediatek/Kconfig
++++ b/arch/arm/mach-mediatek/Kconfig
+@@ -24,6 +24,7 @@ config MACH_MT6592
+ config MACH_MT7623
+       bool "MediaTek MT7623 SoCs support"
+       default ARCH_MEDIATEK
++      select HAVE_ARM_ARCH_TIMER
+       select MIGHT_HAVE_PCI
+ config MACH_MT8127
+diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
+index bcfca37..7553a8c 100644
+--- a/arch/arm/mach-mediatek/mediatek.c
++++ b/arch/arm/mach-mediatek/mediatek.c
+@@ -29,6 +29,7 @@ static void __init mediatek_timer_init(void)
+       void __iomem *gpt_base;
+       if (of_machine_is_compatible("mediatek,mt6589") ||
++          of_machine_is_compatible("mediatek,mt7623") ||
+           of_machine_is_compatible("mediatek,mt8135") ||
+           of_machine_is_compatible("mediatek,mt8127")) {
+               /* turn on GPT6 which ungates arch timer clocks */
+-- 
+1.7.10.4
+
diff --git a/target/linux/mediatek/patches-4.4/0056-mtd-add-get-set-of_node-flash_node-helpers.patch b/target/linux/mediatek/patches-4.4/0056-mtd-add-get-set-of_node-flash_node-helpers.patch
deleted file mode 100644 (file)
index 3b618ac..0000000
+++ /dev/null
@@ -1,78 +0,0 @@
-From 59d8570d4b61af8544fc295d5e83ab7c28294bb8 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Tue, 22 Mar 2016 03:52:07 +0100
-Subject: [PATCH 56/91] mtd: add get/set of_node/flash_node helpers
-
-We are going to begin using the mtd->dev.of_node field for MTD device
-nodes, so let's add helpers for it. Also, we'll be making some
-conversions on spi_nor (and nand_chip eventually) too, so get that ready
-with their own helpers.
-
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
----
- include/linux/mtd/mtd.h     |   11 +++++++++++
- include/linux/mtd/nand.h    |   11 +++++++++++
- include/linux/mtd/spi-nor.h |   11 +++++++++++
- 3 files changed, 33 insertions(+)
-
---- a/include/linux/mtd/mtd.h
-+++ b/include/linux/mtd/mtd.h
-@@ -258,6 +258,17 @@ struct mtd_info {
-       int usecount;
- };
-+static inline void mtd_set_of_node(struct mtd_info *mtd,
-+                                 struct device_node *np)
-+{
-+      mtd->dev.of_node = np;
-+}
-+
-+static inline struct device_node *mtd_get_of_node(struct mtd_info *mtd)
-+{
-+      return mtd->dev.of_node;
-+}
-+
- int mtd_erase(struct mtd_info *mtd, struct erase_info *instr);
- int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
-             void **virt, resource_size_t *phys);
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -741,6 +741,17 @@ static inline void nand_set_controller_d
-       chip->priv = priv;
- }
-+static inline void nand_set_flash_node(struct nand_chip *chip,
-+                                     struct device_node *np)
-+{
-+      chip->flash_node = np;
-+}
-+
-+static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
-+{
-+      return chip->flash_node;
-+}
-+
- /*
-  * NAND Flash Manufacturer ID Codes
-  */
---- a/include/linux/mtd/spi-nor.h
-+++ b/include/linux/mtd/spi-nor.h
-@@ -184,6 +184,17 @@ struct spi_nor {
-       void *priv;
- };
-+static inline void spi_nor_set_flash_node(struct spi_nor *nor,
-+                                        struct device_node *np)
-+{
-+      nor->flash_node = np;
-+}
-+
-+static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
-+{
-+      return nor->flash_node;
-+}
-+
- /**
-  * spi_nor_scan() - scan the SPI NOR
-  * @nor:      the spi_nor structure
diff --git a/target/linux/mediatek/patches-4.4/0057-mtd-mediatek-device-tree-docs-for-MTK-Smart-Device-G.patch b/target/linux/mediatek/patches-4.4/0057-mtd-mediatek-device-tree-docs-for-MTK-Smart-Device-G.patch
deleted file mode 100644 (file)
index eca087c..0000000
+++ /dev/null
@@ -1,58 +0,0 @@
-From 0fe612b501f1d56d76b2858d2ae779c1e766d064 Mon Sep 17 00:00:00 2001
-From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
-Date: Wed, 2 Mar 2016 12:00:11 -0500
-Subject: [PATCH 57/91] mtd: mediatek: device tree docs for MTK Smart Device
- Gen1 NAND
-
-This patch adds documentation support for Smart Device Gen1 type of
-NAND controllers.
-
-Mediatek's SoC 2701 is one of the SoCs that implements this controller.
-
-Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
----
- .../devicetree/bindings/mtd/mtksdg1-nand.txt       |   38 ++++++++++++++++++++
- 1 file changed, 38 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/mtd/mtksdg1-nand.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/mtd/mtksdg1-nand.txt
-@@ -0,0 +1,38 @@
-+MTK Smart Device SoCs NAND controller DT binding
-+
-+Required properties:
-+- compatible:          Should be "mediatek,mt2701-nfc".
-+- reg:                 The first contains base physical address and size of
-+                       NAND controller's registers. The second contains base
-+                       physical address and size of NAND ECC engine.
-+- interrupts:          the NFC NFI interrupt, and the NFC ECC interrupt
-+- clocks:              NAND controller clocks.
-+- clock-names:         NAND controller clocks internal name.
-+- vmch-supply:         NAND power supply.
-+- #address-cells:      Partition address, should be set 1.
-+- #size-cells:         Partition size, should be set 1.
-+
-+Optional properties:
-+
-+nand-on-flash-bbt:  Use a flash based bad block table.
-+
-+Optional subnodes:
-+- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
-+
-+Example:
-+
-+      nand: nand@1100d000 {
-+              compatible = "mediatek,mt2701-nfc";
-+              reg = <0 0x1100d000 0 0x1000>, <0 0x1100e000 0 0x1000>;
-+              interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>,
-+                      <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
-+              clocks = <&pericfg CLK_PERI_NFI>, <&pericfg CLK_PERI_NFI_ECC>,
-+                      <&pericfg CLK_PERI_NFI_PAD>;
-+              clock-names = "nfi_ck", "nfi_ecc_ck", "nfi_pad_ck";
-+              vmch-supply = <&mt6323_vmch_reg>;
-+              status = "disabled";
-+              #address-cells = <1>;
-+              #size-cells = <1>;
-+
-+              ...
-+      };
diff --git a/target/linux/mediatek/patches-4.4/0057-net-mediatek-checking-for-IS_ERR-instead-of-NULL.patch b/target/linux/mediatek/patches-4.4/0057-net-mediatek-checking-for-IS_ERR-instead-of-NULL.patch
new file mode 100644 (file)
index 0000000..a25385e
--- /dev/null
@@ -0,0 +1,32 @@
+From b9f9b937dd12dc57bd54a6c89b18eb40d4508424 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Tue, 15 Mar 2016 10:18:49 +0300
+Subject: [PATCH 057/102] net: mediatek: checking for IS_ERR() instead of NULL
+
+of_phy_connect() returns NULL on error, it never returns error pointers.
+
+Fixes: 656e705243fd ('net-next: mediatek: add support for MT7623 ethernet')
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index ba3afa5..9759fe5 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -186,9 +186,9 @@ static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
+       phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
+                               mtk_phy_link_adjust, 0, phy_mode);
+-      if (IS_ERR(phydev)) {
++      if (!phydev) {
+               dev_err(eth->dev, "could not connect to PHY\n");
+-              return PTR_ERR(phydev);
++              return -ENODEV;
+       }
+       dev_info(eth->dev,
+-- 
+1.7.10.4
+
diff --git a/target/linux/mediatek/patches-4.4/0058-mtd-mediatek-driver-for-MTK-Smart-Device-Gen1-NAND.patch b/target/linux/mediatek/patches-4.4/0058-mtd-mediatek-driver-for-MTK-Smart-Device-Gen1-NAND.patch
deleted file mode 100644 (file)
index 2d09f45..0000000
+++ /dev/null
@@ -1,1782 +0,0 @@
-From 24db36ad20239841b897efb41442841ebf5d2f78 Mon Sep 17 00:00:00 2001
-From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
-Date: Wed, 2 Mar 2016 12:00:12 -0500
-Subject: [PATCH 58/91] mtd: mediatek: driver for MTK Smart Device Gen1 NAND
-
-This patch adds support for mediatek's SDG1 NFC nand controller
-embedded in SoC 2701.
-
-UBIFS support has been successfully tested.
-
-Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
----
- drivers/mtd/nand/Kconfig            |    6 +
- drivers/mtd/nand/Makefile           |    1 +
- drivers/mtd/nand/mtksdg1_nand.c     | 1535 +++++++++++++++++++++++++++++++++++
- drivers/mtd/nand/mtksdg1_nand_ecc.h |   75 ++
- drivers/mtd/nand/mtksdg1_nand_nfi.h |  119 +++
- 5 files changed, 1736 insertions(+)
- create mode 100644 drivers/mtd/nand/mtksdg1_nand.c
- create mode 100644 drivers/mtd/nand/mtksdg1_nand_ecc.h
- create mode 100644 drivers/mtd/nand/mtksdg1_nand_nfi.h
-
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -546,4 +546,10 @@ config MTD_NAND_HISI504
-       help
-         Enables support for NAND controller on Hisilicon SoC Hip04.
-+config MTD_NAND_MTKSDG1
-+      tristate "Support for NAND controller on MTK Smart Device SoCs"
-+      depends on HAS_DMA
-+      help
-+      Enables support for NAND controller on MTK Smart Device SoCs.
-+
- endif # MTD_NAND
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -55,5 +55,6 @@ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) +=
- obj-$(CONFIG_MTD_NAND_SUNXI)          += sunxi_nand.o
- obj-$(CONFIG_MTD_NAND_HISI504)                += hisi504_nand.o
- obj-$(CONFIG_MTD_NAND_BRCMNAND)               += brcmnand/
-+obj-$(CONFIG_MTD_NAND_MTKSDG1)                += mtksdg1_nand.o
- nand-objs := nand_base.o nand_bbt.o nand_timings.o
---- /dev/null
-+++ b/drivers/mtd/nand/mtksdg1_nand.c
-@@ -0,0 +1,1535 @@
-+/*
-+ * MTK smart device NAND Flash controller driver.
-+ * Copyright (C) 2015-2016 MediaTek Inc.
-+ * Authors:   Xiaolei Li              <xiaolei.li@mediatek.com>
-+ *            Jorge Ramirez-Ortiz     <jorge.ramirez-ortiz@linaro.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/platform_device.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/interrupt.h>
-+#include <linux/of_mtd.h>
-+#include <linux/delay.h>
-+#include <linux/clk.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/mtd/nand.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/module.h>
-+
-+#include "mtksdg1_nand_nfi.h"
-+#include "mtksdg1_nand_ecc.h"
-+
-+#define MTK_IRQ_ECC           "mtksdg1-nand-ecc"
-+#define MTK_IRQ_NFI           "mtksdg1-nand-nfi"
-+#define MTK_NAME              "mtksdg1-nand"
-+
-+#define KB(x)                 ((x) * 1024UL)
-+#define MB(x)                 (KB(x) * 1024UL)
-+
-+#define SECTOR_SHIFT          (10)
-+#define SECTOR_SIZE           (1UL << SECTOR_SHIFT)
-+#define BYTES_TO_SECTORS(x)   ((x) >> SECTOR_SHIFT)
-+#define SECTORS_TO_BYTES(x)   ((x) << SECTOR_SHIFT)
-+
-+#define MTK_TIMEOUT           (500)
-+#define MTK_RESET_TIMEOUT     (1 * HZ)
-+
-+#define MTK_ECC_PARITY_BITS   (14)
-+#define MTK_NAND_MAX_CHIP     (2)
-+
-+#define MTK_OOB_ON            (1)
-+#define MTK_OOB_OFF           (0)
-+
-+/* raw accesses do not use ECC (ecc = !raw) */
-+#define MTK_ECC_OFF           (1)
-+#define MTK_ECC_ON            (0)
-+
-+struct mtk_nfc_clk {
-+      struct clk *nfiecc_clk;
-+      struct clk *nfi_clk;
-+      struct clk *pad_clk;
-+};
-+
-+struct mtk_nfc_saved_reg {
-+      struct {
-+              u32 enccnfg;
-+              u32 deccnfg;
-+      } ecc;
-+      struct {
-+              u32 emp_thresh;
-+              u16 pagefmt;
-+              u32 acccon;
-+              u16 cnrnb;
-+              u16 csel;
-+      } nfi;
-+};
-+
-+struct mtk_nfc_host {
-+      struct mtk_nfc_clk clk;
-+      struct nand_chip chip;
-+      struct device *dev;
-+
-+      struct {
-+              struct completion complete;
-+              void __iomem *base;
-+      } nfi;
-+
-+      struct {
-+              struct completion complete;
-+              void __iomem *base;
-+              u32 dec_sec;
-+      } ecc;
-+
-+      u32 fdm_reg[MTKSDG1_NFI_FDM_REG_SIZE / sizeof(u32)];
-+      bool switch_oob;
-+      u32 row_nob;
-+      u8 *buffer;
-+
-+#ifdef CONFIG_PM_SLEEP
-+      struct mtk_nfc_saved_reg saved_reg;
-+#endif
-+};
-+
-+static struct nand_ecclayout nand_2k_64 = {
-+      .oobfree = { {0, 16} },
-+};
-+
-+static struct nand_ecclayout nand_4k_128 = {
-+      .oobfree = { {0, 32} },
-+};
-+
-+/* NFI register access */
-+static inline void mtk_nfi_writel(struct mtk_nfc_host *host, u32 val, u32 reg)
-+{
-+      writel(val, host->nfi.base + reg);
-+}
-+static inline void mtk_nfi_writew(struct mtk_nfc_host *host, u16 val, u32 reg)
-+{
-+      writew(val, host->nfi.base + reg);
-+}
-+static inline u32 mtk_nfi_readl(struct mtk_nfc_host *host, u32 reg)
-+{
-+      return readl_relaxed(host->nfi.base + reg);
-+}
-+static inline u16 mtk_nfi_readw(struct mtk_nfc_host *host, u32 reg)
-+{
-+      return readw_relaxed(host->nfi.base + reg);
-+}
-+static inline u8 mtk_nfi_readb(struct mtk_nfc_host *host, u32 reg)
-+{
-+      return readb_relaxed(host->nfi.base + reg);
-+}
-+
-+/* ECC register access */
-+static inline void mtk_ecc_writel(struct mtk_nfc_host *host, u32 val, u32 reg)
-+{
-+      writel(val, host->ecc.base + reg);
-+}
-+static inline void mtk_ecc_writew(struct mtk_nfc_host *host, u16 val, u32 reg)
-+{
-+      writew(val, host->ecc.base + reg);
-+}
-+static inline u32 mtk_ecc_readl(struct mtk_nfc_host *host, u32 reg)
-+{
-+      return readl_relaxed(host->ecc.base + reg);
-+}
-+static inline u16 mtk_ecc_readw(struct mtk_nfc_host *host, u32 reg)
-+{
-+      return readw_relaxed(host->ecc.base + reg);
-+}
-+
-+static void mtk_nfc_hw_reset(struct mtk_nfc_host *host)
-+{
-+      unsigned long timeout = MTK_RESET_TIMEOUT;
-+      struct device *dev = host->dev;
-+      u32 val;
-+
-+      /* reset the state machine, data fifo and fdm data */
-+      mtk_nfi_writel(host, CON_FIFO_FLUSH | CON_NFI_RST, MTKSDG1_NFI_CON);
-+      timeout += jiffies;
-+      do {
-+              val = mtk_nfi_readl(host, MTKSDG1_NFI_MASTER_STA);
-+              val &= MASTER_STA_MASK;
-+              if (!val)
-+                      return;
-+              usleep_range(50, 100);
-+
-+      } while (time_before(jiffies, timeout));
-+
-+      dev_warn(dev, "nfi master active after in reset [0x%x] = 0x%x\n",
-+              MTKSDG1_NFI_MASTER_STA, val);
-+};
-+
-+static int mtk_nfc_set_command(struct mtk_nfc_host *host, u8 command)
-+{
-+      unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
-+      struct device *dev = host->dev;
-+      u32 val;
-+
-+      mtk_nfi_writel(host, command, MTKSDG1_NFI_CMD);
-+
-+      /* wait for the NFI core to enter command mode */
-+      timeout += jiffies;
-+      do {
-+              val = mtk_nfi_readl(host, MTKSDG1_NFI_STA);
-+              val &= STA_CMD;
-+              if (!val)
-+                      return 0;
-+              cpu_relax();
-+
-+      } while (time_before(jiffies, timeout));
-+      dev_warn(dev, "nfi core timed out entering command mode\n");
-+
-+      return -EIO;
-+}
-+
-+static int mtk_nfc_set_address(struct mtk_nfc_host *host, u32 column, u32 row,
-+              u8 colnob, u8 row_nob)
-+{
-+      unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
-+      struct device *dev = host->dev;
-+      u32 addr_nob, val;
-+
-+      addr_nob = colnob | (row_nob << ADDR_ROW_NOB_SHIFT);
-+      mtk_nfi_writel(host, column, MTKSDG1_NFI_COLADDR);
-+      mtk_nfi_writel(host, row, MTKSDG1_NFI_ROWADDR);
-+      mtk_nfi_writel(host, addr_nob, MTKSDG1_NFI_ADDRNOB);
-+
-+      /* wait for the NFI core to enter address mode */
-+      timeout += jiffies;
-+      do {
-+              val = mtk_nfi_readl(host, MTKSDG1_NFI_STA);
-+              val &= STA_ADDR;
-+              if (!val)
-+                      return 0;
-+              cpu_relax();
-+
-+      } while (time_before(jiffies, timeout));
-+
-+      dev_warn(dev, "nfi core timed out entering address mode\n");
-+
-+      return -EIO;
-+}
-+
-+static inline void mtk_ecc_encoder_idle(struct mtk_nfc_host *host)
-+{
-+      unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
-+      struct device *dev = host->dev;
-+      u32 val;
-+
-+      timeout += jiffies;
-+      do {
-+              val = mtk_ecc_readl(host, MTKSDG1_ECC_ENCIDLE);
-+              val &= ENC_IDLE;
-+              if (val)
-+                      return;
-+              cpu_relax();
-+
-+      } while (time_before(jiffies, timeout));
-+
-+      dev_warn(dev, "hw init ecc encoder not idle\n");
-+}
-+
-+static inline void mtk_ecc_decoder_idle(struct mtk_nfc_host *host)
-+{
-+      unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
-+      struct device *dev = host->dev;
-+      u32 val;
-+
-+      timeout += jiffies;
-+      do {
-+              val = mtk_ecc_readw(host, MTKSDG1_ECC_DECIDLE);
-+              val &= DEC_IDLE;
-+              if (val)
-+                      return;
-+              cpu_relax();
-+
-+      } while (time_before(jiffies, timeout));
-+
-+      dev_warn(dev, "hw init ecc decoder not idle\n");
-+}
-+
-+static int mtk_nfc_transfer_done(struct mtk_nfc_host *host, u32 sectors)
-+{
-+      unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
-+      u32 cnt;
-+
-+      /* wait for the sector count */
-+      timeout += jiffies;
-+      do {
-+              cnt = mtk_nfi_readl(host, MTKSDG1_NFI_ADDRCNTR);
-+              cnt &= CNTR_MASK;
-+              if (cnt >= sectors)
-+                      return 0;
-+              cpu_relax();
-+
-+      } while (time_before(jiffies, timeout));
-+
-+      return  -EIO;
-+}
-+
-+static int mtk_nfc_subpage_done(struct mtk_nfc_host *host, int sectors)
-+{
-+      unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
-+      u32 val;
-+
-+      timeout += jiffies;
-+      do {
-+              val = mtk_nfi_readl(host, MTKSDG1_NFI_BYTELEN);
-+              val &= CNTR_MASK;
-+              if (val >= sectors)
-+                      return 0;
-+              cpu_relax();
-+
-+      } while (time_before(jiffies, timeout));
-+
-+      return -EIO;
-+}
-+
-+static inline int mtk_nfc_data_ready(struct mtk_nfc_host *host)
-+{
-+      unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
-+      u8 val;
-+
-+      timeout += jiffies;
-+      do {
-+              val = mtk_nfi_readw(host, MTKSDG1_NFI_PIO_DIRDY);
-+              val &= PIO_DI_RDY;
-+              if (val)
-+                      return 0;
-+              cpu_relax();
-+
-+      } while (time_before(jiffies, timeout));
-+
-+      /* data _MUST_ not be accessed */
-+      return -EIO;
-+}
-+
-+static int mtk_nfc_hw_runtime_config(struct mtd_info *mtd)
-+{
-+      struct nand_chip *chip = mtd_to_nand(mtd);
-+      struct mtk_nfc_host *host = nand_get_controller_data(chip);
-+      struct device *dev = host->dev;
-+      u32 dec_size, enc_size;
-+      u32 ecc_bit, ecc_level;
-+      u32 spare, fmt;
-+      u32 reg;
-+
-+      host->row_nob = 1;
-+      if (chip->chipsize > MB(32))
-+              host->row_nob = chip->chipsize > MB(128) ? 3 : 2;
-+
-+      spare = mtd->oobsize / BYTES_TO_SECTORS(mtd->writesize);
-+      switch (spare) {
-+      case 16:
-+              ecc_bit = ECC_CNFG_4BIT;
-+              ecc_level = 4;
-+              break;
-+      case 32:
-+              ecc_bit = ECC_CNFG_12BIT;
-+              ecc_level = 12;
-+              break;
-+      default:
-+              dev_err(dev, "invalid spare size per sector: %d\n", spare);
-+              return -EINVAL;
-+      }
-+
-+      chip->ecc.strength = ecc_level;
-+      chip->ecc.size = SECTOR_SIZE;
-+
-+      switch (mtd->writesize) {
-+      case KB(2):
-+              fmt = PAGEFMT_512_2K;
-+              chip->ecc.layout = &nand_2k_64;
-+              break;
-+      case KB(4):
-+              fmt = PAGEFMT_2K_4K;
-+              chip->ecc.layout = &nand_4k_128;
-+              break;
-+      case KB(8):
-+              fmt = PAGEFMT_4K_8K;
-+              break;
-+      default:
-+              dev_err(dev, "invalid page size: %d\n", mtd->writesize);
-+              return -EINVAL;
-+      }
-+
-+      /* configure PAGE FMT */
-+      reg = fmt;
-+      reg |= PAGEFMT_SPARE_16 << PAGEFMT_SPARE_SHIFT;
-+      reg |= MTKSDG1_NFI_FDM_REG_SIZE << PAGEFMT_FDM_SHIFT;
-+      reg |= MTKSDG1_NFI_FDM_REG_SIZE << PAGEFMT_FDM_ECC_SHIFT;
-+      mtk_nfi_writew(host, reg, MTKSDG1_NFI_PAGEFMT);
-+
-+      /* configure ECC encoder (in bits) */
-+      enc_size = (SECTOR_SIZE + MTKSDG1_NFI_FDM_REG_SIZE) << 3;
-+      reg = ecc_bit | ECC_NFI_MODE | (enc_size << ECC_MS_SHIFT);
-+      mtk_ecc_writel(host, reg, MTKSDG1_ECC_ENCCNFG);
-+
-+      /* configure ECC decoder (inbits) */
-+      dec_size = enc_size + ecc_level * MTK_ECC_PARITY_BITS;
-+      reg = ecc_bit | ECC_NFI_MODE | (dec_size << ECC_MS_SHIFT);
-+      reg |= (DEC_CNFG_CORRECT | DEC_EMPTY_EN);
-+      mtk_ecc_writel(host, reg, MTKSDG1_ECC_DECCNFG);
-+
-+      return 0;
-+}
-+
-+static void mtk_nfc_device_reset(struct mtk_nfc_host *host)
-+{
-+      unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
-+      struct device *dev = host->dev;
-+      u16 chip;
-+      int rc;
-+
-+      mtk_nfc_hw_reset(host);
-+
-+      /* enable reset done interrupt */
-+      mtk_nfi_writew(host, INTR_RST_DONE_EN, MTKSDG1_NFI_INTR_EN);
-+
-+      /* configure FSM for reset operation */
-+      mtk_nfi_writew(host, CNFG_OP_RESET, MTKSDG1_NFI_CNFG);
-+
-+      init_completion(&host->nfi.complete);
-+
-+      mtk_nfc_set_command(host, NAND_CMD_RESET);
-+      rc = wait_for_completion_timeout(&host->nfi.complete, timeout);
-+      if (!rc) {
-+              chip = mtk_nfi_readw(host, MTKSDG1_NFI_CSEL);
-+              dev_err(dev, "device(%d) reset timeout\n", chip);
-+      }
-+}
-+
-+static void mtk_nfc_select_chip(struct mtd_info *mtd, int chip)
-+{
-+      struct nand_chip *nand = mtd_to_nand(mtd);
-+      struct mtk_nfc_host *host = nand_get_controller_data(nand);
-+
-+      if (chip < 0)
-+              return;
-+
-+      mtk_nfi_writel(host, chip, MTKSDG1_NFI_CSEL);
-+}
-+
-+static inline bool mtk_nfc_cmd_supported(unsigned command)
-+{
-+      switch (command) {
-+      case NAND_CMD_RESET:
-+      case NAND_CMD_READID:
-+      case NAND_CMD_STATUS:
-+      case NAND_CMD_READOOB:
-+      case NAND_CMD_ERASE1:
-+      case NAND_CMD_ERASE2:
-+      case NAND_CMD_SEQIN:
-+      case NAND_CMD_PAGEPROG:
-+      case NAND_CMD_CACHEDPROG:
-+      case NAND_CMD_READ0:
-+              return true;
-+      default:
-+              return false;
-+      }
-+}
-+
-+static void mtk_nfc_cmdfunc(struct mtd_info *mtd, unsigned command, int column,
-+              int page_addr)
-+{
-+      struct mtk_nfc_host *host = nand_get_controller_data(mtd_to_nand(mtd));
-+      unsigned long const cmd_timeout = msecs_to_jiffies(MTK_TIMEOUT);
-+      struct completion *p = &host->nfi.complete;
-+      u32 val;
-+      int rc;
-+
-+      if (mtk_nfc_cmd_supported(command))
-+              mtk_nfc_hw_reset(host);
-+
-+      switch (command) {
-+      case NAND_CMD_RESET:
-+              mtk_nfc_device_reset(host);
-+              break;
-+      case NAND_CMD_READID:
-+              val = CNFG_READ_EN | CNFG_BYTE_RW | CNFG_OP_SRD;
-+              mtk_nfi_writew(host, val, MTKSDG1_NFI_CNFG);
-+              mtk_nfc_set_command(host, NAND_CMD_READID);
-+              mtk_nfc_set_address(host, column, 0, 1, 0);
-+              mtk_nfi_writel(host, CON_SRD, MTKSDG1_NFI_CON);
-+              break;
-+      case NAND_CMD_STATUS:
-+              val = CNFG_READ_EN | CNFG_BYTE_RW | CNFG_OP_SRD;
-+              mtk_nfi_writew(host, val, MTKSDG1_NFI_CNFG);
-+              mtk_nfc_set_command(host, NAND_CMD_STATUS);
-+              mtk_nfi_writel(host, CON_SRD, MTKSDG1_NFI_CON);
-+              break;
-+      case NAND_CMD_READOOB:
-+              val = CNFG_READ_EN | CNFG_BYTE_RW | CNFG_OP_READ;
-+              mtk_nfi_writew(host, val, MTKSDG1_NFI_CNFG);
-+              mtk_nfc_set_command(host, NAND_CMD_READ0);
-+              column += mtd->writesize;
-+              mtk_nfc_set_address(host, column, page_addr, 2, host->row_nob);
-+              val = CON_BRD | (1 << CON_SEC_SHIFT);
-+              mtk_nfi_writel(host, val, MTKSDG1_NFI_CON);
-+              break;
-+      case NAND_CMD_ERASE1:
-+              mtk_nfi_writew(host, INTR_ERS_DONE_EN, MTKSDG1_NFI_INTR_EN);
-+              mtk_nfi_writew(host, CNFG_OP_ERASE, MTKSDG1_NFI_CNFG);
-+              mtk_nfc_set_command(host, NAND_CMD_ERASE1);
-+              mtk_nfc_set_address(host, 0, page_addr, 0, host->row_nob);
-+              break;
-+      case NAND_CMD_ERASE2:
-+              init_completion(p);
-+              mtk_nfc_set_command(host, NAND_CMD_ERASE2);
-+              rc = wait_for_completion_timeout(p, cmd_timeout);
-+              if (!rc)
-+                      dev_err(host->dev, "erase command timeout\n");
-+              break;
-+      case NAND_CMD_SEQIN:
-+              mtk_nfi_writew(host, CNFG_OP_PRGM, MTKSDG1_NFI_CNFG);
-+              mtk_nfc_set_command(host, NAND_CMD_SEQIN);
-+              mtk_nfc_set_address(host, column, page_addr, 2, host->row_nob);
-+              break;
-+      case NAND_CMD_PAGEPROG:
-+      case NAND_CMD_CACHEDPROG:
-+              mtk_nfi_writew(host, INTR_BUSY_RT_EN, MTKSDG1_NFI_INTR_EN);
-+              init_completion(p);
-+              mtk_nfc_set_command(host, command);
-+              rc = wait_for_completion_timeout(p, cmd_timeout);
-+              if (!rc)
-+                      dev_err(host->dev, "pageprogr command timeout\n");
-+              break;
-+      case NAND_CMD_READ0:
-+              val = CNFG_OP_READ | CNFG_READ_EN;
-+              mtk_nfi_writew(host, val, MTKSDG1_NFI_CNFG);
-+              mtk_nfc_set_command(host, NAND_CMD_READ0);
-+              break;
-+      default:
-+              dev_warn(host->dev, "command 0x%x not supported\n", command);
-+              break;
-+      }
-+}
-+
-+static uint8_t mtk_nfc_read_byte(struct mtd_info *mtd)
-+{
-+      struct nand_chip *chip = mtd_to_nand(mtd);
-+      struct mtk_nfc_host *host = nand_get_controller_data(chip);
-+      int rc;
-+
-+      rc = mtk_nfc_data_ready(host);
-+      if (rc < 0) {
-+              dev_err(host->dev, "data not ready\n");
-+              return NAND_STATUS_FAIL;
-+      }
-+
-+      return mtk_nfi_readb(host, MTKSDG1_NFI_DATAR);
-+}
-+
-+static void mtk_nfc_write_fdm(struct nand_chip *chip, u32 sectors)
-+{
-+      struct mtk_nfc_host *host = nand_get_controller_data(chip);
-+      u8 *src, *dst;
-+      int i, j, reg;
-+
-+      for (i = 0; i&nbs