--- /dev/null
+From 0f4630f3720e7e6e921bf525c8357fea7ef3dbab Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 4 Dec 2015 14:02:58 +0100
+Subject: [PATCH] gpio: generic: factor into gpio_chip struct
+
+The separate struct bgpio_chip has been a pain to handle, both
+by being confusingly similar in name to struct gpio_chip and
+for being contained inside a struct so that struct gpio_chip
+is contained in a struct contained in a struct, making several
+steps of dereferencing necessary.
+
+Make things simpler: include the fields directly into
+<linux/gpio/driver.h>, #ifdef:ed for CONFIG_GENERIC_GPIO, and
+get rid of the <linux/basic_mmio_gpio.h> altogether. Prefix
+some of the member variables with bgpio_* and add proper
+kerneldoc while we're at it.
+
+Modify all users to handle the change and use a struct
+gpio_chip directly. And while we're at it: replace all
+container_of() dereferencing by gpiochip_get_data() and
+registering the gpio_chip with gpiochip_add_data().
+
+Cc: arm@kernel.org
+Cc: Alexander Shiyan <shc_work@mail.ru>
+Cc: Shawn Guo <shawnguo@kernel.org>
+Cc: Sascha Hauer <kernel@pengutronix.de>
+Cc: Kukjin Kim <kgene@kernel.org>
+Cc: Alexandre Courbot <gnurou@gmail.com>
+Cc: Brian Norris <computersforpeace@gmail.com>
+Cc: Florian Fainelli <f.fainelli@gmail.com>
+Cc: Sudeep Holla <sudeep.holla@arm.com>
+Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
+Cc: Olof Johansson <olof@lixom.net>
+Cc: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
+Cc: Rabin Vincent <rabin@rab.in>
+Cc: linux-arm-kernel@lists.infradead.org
+Cc: linux-omap@vger.kernel.org
+Cc: linux-samsung-soc@vger.kernel.org
+Cc: bcm-kernel-feedback-list@broadcom.com
+Acked-by: Gregory Fong <gregory.0xf0@gmail.com>
+Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
+Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>
+Acked-by: Tony Lindgren <tony@atomide.com>
+Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
+Acked-by: Lee Jones <lee.jones@linaro.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/mach-clps711x/board-autcpu12.c | 2 +-
+ arch/arm/mach-clps711x/board-p720t.c | 2 +-
+ arch/arm/mach-imx/mach-mx21ads.c | 2 +-
+ arch/arm/mach-omap1/board-ams-delta.c | 2 +-
+ arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +-
+ drivers/gpio/gpio-74xx-mmio.c | 37 ++--
+ drivers/gpio/gpio-brcmstb.c | 80 ++++-----
+ drivers/gpio/gpio-clps711x.c | 28 +--
+ drivers/gpio/gpio-dwapb.c | 92 +++++-----
+ drivers/gpio/gpio-ep93xx.c | 25 +--
+ drivers/gpio/gpio-etraxfs.c | 49 +++---
+ drivers/gpio/gpio-ge.c | 24 +--
+ drivers/gpio/gpio-generic.c | 292 +++++++++++++++-----------------
+ drivers/gpio/gpio-grgpio.c | 73 ++++----
+ drivers/gpio/gpio-moxart.c | 29 ++--
+ drivers/gpio/gpio-mxc.c | 27 ++-
+ drivers/gpio/gpio-mxs.c | 33 ++--
+ drivers/gpio/gpio-sodaville.c | 13 +-
+ drivers/gpio/gpio-xgene-sb.c | 40 ++---
+ drivers/mfd/vexpress-sysreg.c | 8 +-
+ include/linux/basic_mmio_gpio.h | 80 ---------
+ include/linux/gpio/driver.h | 54 ++++++
+ 22 files changed, 442 insertions(+), 552 deletions(-)
+ delete mode 100644 include/linux/basic_mmio_gpio.h
+
+--- a/arch/arm/mach-clps711x/board-autcpu12.c
++++ b/arch/arm/mach-clps711x/board-autcpu12.c
+@@ -31,7 +31,7 @@
+ #include <linux/mtd/partitions.h>
+ #include <linux/mtd/nand-gpio.h>
+ #include <linux/platform_device.h>
+-#include <linux/basic_mmio_gpio.h>
++#include <linux/gpio/driver.h>
+
+ #include <mach/hardware.h>
+ #include <asm/sizes.h>
+--- a/arch/arm/mach-clps711x/board-p720t.c
++++ b/arch/arm/mach-clps711x/board-p720t.c
+@@ -28,7 +28,7 @@
+ #include <linux/leds.h>
+ #include <linux/sizes.h>
+ #include <linux/backlight.h>
+-#include <linux/basic_mmio_gpio.h>
++#include <linux/gpio/driver.h>
+ #include <linux/platform_device.h>
+ #include <linux/mtd/partitions.h>
+ #include <linux/mtd/nand-gpio.h>
+--- a/arch/arm/mach-imx/mach-mx21ads.c
++++ b/arch/arm/mach-imx/mach-mx21ads.c
+@@ -17,7 +17,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/mtd/mtd.h>
+ #include <linux/mtd/physmap.h>
+-#include <linux/basic_mmio_gpio.h>
++#include <linux/gpio/driver.h>
+ #include <linux/gpio.h>
+ #include <linux/regulator/fixed.h>
+ #include <linux/regulator/machine.h>
+--- a/arch/arm/mach-omap1/board-ams-delta.c
++++ b/arch/arm/mach-omap1/board-ams-delta.c
+@@ -11,7 +11,7 @@
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+-#include <linux/basic_mmio_gpio.h>
++#include <linux/gpio/driver.h>
+ #include <linux/gpio.h>
+ #include <linux/kernel.h>
+ #include <linux/init.h>
+--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
++++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
+@@ -29,7 +29,7 @@
+ #include <linux/pwm_backlight.h>
+ #include <linux/dm9000.h>
+ #include <linux/gpio_keys.h>
+-#include <linux/basic_mmio_gpio.h>
++#include <linux/gpio/driver.h>
+ #include <linux/spi/spi.h>
+
+ #include <linux/platform_data/pca953x.h>
+--- a/drivers/gpio/gpio-74xx-mmio.c
++++ b/drivers/gpio/gpio-74xx-mmio.c
+@@ -10,10 +10,9 @@
+ */
+
+ #include <linux/err.h>
+-#include <linux/gpio.h>
+ #include <linux/module.h>
+ #include <linux/of_device.h>
+-#include <linux/basic_mmio_gpio.h>
++#include <linux/gpio/driver.h>
+ #include <linux/platform_device.h>
+
+ #define MMIO_74XX_DIR_IN (0 << 8)
+@@ -21,7 +20,7 @@
+ #define MMIO_74XX_BIT_CNT(x) ((x) & 0xff)
+
+ struct mmio_74xx_gpio_priv {
+- struct bgpio_chip bgc;
++ struct gpio_chip gc;
+ unsigned flags;
+ };
+
+@@ -78,30 +77,23 @@ static const struct of_device_id mmio_74
+ };
+ MODULE_DEVICE_TABLE(of, mmio_74xx_gpio_ids);
+
+-static inline struct mmio_74xx_gpio_priv *to_74xx_gpio(struct gpio_chip *gc)
+-{
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+-
+- return container_of(bgc, struct mmio_74xx_gpio_priv, bgc);
+-}
+-
+ static int mmio_74xx_get_direction(struct gpio_chip *gc, unsigned offset)
+ {
+- struct mmio_74xx_gpio_priv *priv = to_74xx_gpio(gc);
++ struct mmio_74xx_gpio_priv *priv = gpiochip_get_data(gc);
+
+- return (priv->flags & MMIO_74XX_DIR_OUT) ? GPIOF_DIR_OUT : GPIOF_DIR_IN;
++ return !(priv->flags & MMIO_74XX_DIR_OUT);
+ }
+
+ static int mmio_74xx_dir_in(struct gpio_chip *gc, unsigned int gpio)
+ {
+- struct mmio_74xx_gpio_priv *priv = to_74xx_gpio(gc);
++ struct mmio_74xx_gpio_priv *priv = gpiochip_get_data(gc);
+
+ return (priv->flags & MMIO_74XX_DIR_OUT) ? -ENOTSUPP : 0;
+ }
+
+ static int mmio_74xx_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+ {
+- struct mmio_74xx_gpio_priv *priv = to_74xx_gpio(gc);
++ struct mmio_74xx_gpio_priv *priv = gpiochip_get_data(gc);
+
+ if (priv->flags & MMIO_74XX_DIR_OUT) {
+ gc->set(gc, gpio, val);
+@@ -134,28 +126,29 @@ static int mmio_74xx_gpio_probe(struct p
+
+ priv->flags = (uintptr_t) of_id->data;
+
+- err = bgpio_init(&priv->bgc, &pdev->dev,
++ err = bgpio_init(&priv->gc, &pdev->dev,
+ DIV_ROUND_UP(MMIO_74XX_BIT_CNT(priv->flags), 8),
+ dat, NULL, NULL, NULL, NULL, 0);
+ if (err)
+ return err;
+
+- priv->bgc.gc.direction_input = mmio_74xx_dir_in;
+- priv->bgc.gc.direction_output = mmio_74xx_dir_out;
+- priv->bgc.gc.get_direction = mmio_74xx_get_direction;
+- priv->bgc.gc.ngpio = MMIO_74XX_BIT_CNT(priv->flags);
+- priv->bgc.gc.owner = THIS_MODULE;
++ priv->gc.direction_input = mmio_74xx_dir_in;
++ priv->gc.direction_output = mmio_74xx_dir_out;
++ priv->gc.get_direction = mmio_74xx_get_direction;
++ priv->gc.ngpio = MMIO_74XX_BIT_CNT(priv->flags);
++ priv->gc.owner = THIS_MODULE;
+
+ platform_set_drvdata(pdev, priv);
+
+- return gpiochip_add(&priv->bgc.gc);
++ return gpiochip_add_data(&priv->gc, priv);
+ }
+
+ static int mmio_74xx_gpio_remove(struct platform_device *pdev)
+ {
+ struct mmio_74xx_gpio_priv *priv = platform_get_drvdata(pdev);
+
+- return bgpio_remove(&priv->bgc);
++ gpiochip_remove(&priv->gc);
++ return 0;
+ }
+
+ static struct platform_driver mmio_74xx_gpio_driver = {
+--- a/drivers/gpio/gpio-brcmstb.c
++++ b/drivers/gpio/gpio-brcmstb.c
+@@ -16,7 +16,6 @@
+ #include <linux/of_device.h>
+ #include <linux/of_irq.h>
+ #include <linux/module.h>
+-#include <linux/basic_mmio_gpio.h>
+ #include <linux/irqdomain.h>
+ #include <linux/irqchip/chained_irq.h>
+ #include <linux/interrupt.h>
+@@ -35,7 +34,7 @@
+ struct brcmstb_gpio_bank {
+ struct list_head node;
+ int id;
+- struct bgpio_chip bgc;
++ struct gpio_chip gc;
+ struct brcmstb_gpio_priv *parent_priv;
+ u32 width;
+ struct irq_chip irq_chip;
+@@ -57,37 +56,30 @@ struct brcmstb_gpio_priv {
+ /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
+ #define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
+
+-static inline struct brcmstb_gpio_bank *
+-brcmstb_gpio_gc_to_bank(struct gpio_chip *gc)
+-{
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+- return container_of(bgc, struct brcmstb_gpio_bank, bgc);
+-}
+-
+ static inline struct brcmstb_gpio_priv *
+ brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
+ {
+- struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
++ struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
+ return bank->parent_priv;
+ }
+
+ static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
+ unsigned int offset, bool enable)
+ {
+- struct bgpio_chip *bgc = &bank->bgc;
++ struct gpio_chip *gc = &bank->gc;
+ struct brcmstb_gpio_priv *priv = bank->parent_priv;
+- u32 mask = bgc->pin2mask(bgc, offset);
++ u32 mask = gc->pin2mask(gc, offset);
+ u32 imask;
+ unsigned long flags;
+
+- spin_lock_irqsave(&bgc->lock, flags);
+- imask = bgc->read_reg(priv->reg_base + GIO_MASK(bank->id));
++ spin_lock_irqsave(&gc->bgpio_lock, flags);
++ imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
+ if (enable)
+ imask |= mask;
+ else
+ imask &= ~mask;
+- bgc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
+- spin_unlock_irqrestore(&bgc->lock, flags);
++ gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
++ spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+ }
+
+ /* -------------------- IRQ chip functions -------------------- */
+@@ -95,7 +87,7 @@ static void brcmstb_gpio_set_imask(struc
+ static void brcmstb_gpio_irq_mask(struct irq_data *d)
+ {
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+- struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
++ struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
+
+ brcmstb_gpio_set_imask(bank, d->hwirq, false);
+ }
+@@ -103,7 +95,7 @@ static void brcmstb_gpio_irq_mask(struct
+ static void brcmstb_gpio_irq_unmask(struct irq_data *d)
+ {
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+- struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
++ struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
+
+ brcmstb_gpio_set_imask(bank, d->hwirq, true);
+ }
+@@ -111,7 +103,7 @@ static void brcmstb_gpio_irq_unmask(stru
+ static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
+ {
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+- struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
++ struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
+ struct brcmstb_gpio_priv *priv = bank->parent_priv;
+ u32 mask = BIT(d->hwirq);
+ u32 edge_insensitive, iedge_insensitive;
+@@ -149,23 +141,23 @@ static int brcmstb_gpio_irq_set_type(str
+ return -EINVAL;
+ }
+
+- spin_lock_irqsave(&bank->bgc.lock, flags);
++ spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
+
+- iedge_config = bank->bgc.read_reg(priv->reg_base +
++ iedge_config = bank->gc.read_reg(priv->reg_base +
+ GIO_EC(bank->id)) & ~mask;
+- iedge_insensitive = bank->bgc.read_reg(priv->reg_base +
++ iedge_insensitive = bank->gc.read_reg(priv->reg_base +
+ GIO_EI(bank->id)) & ~mask;
+- ilevel = bank->bgc.read_reg(priv->reg_base +
++ ilevel = bank->gc.read_reg(priv->reg_base +
+ GIO_LEVEL(bank->id)) & ~mask;
+
+- bank->bgc.write_reg(priv->reg_base + GIO_EC(bank->id),
++ bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
+ iedge_config | edge_config);
+- bank->bgc.write_reg(priv->reg_base + GIO_EI(bank->id),
++ bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
+ iedge_insensitive | edge_insensitive);
+- bank->bgc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
++ bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
+ ilevel | level);
+
+- spin_unlock_irqrestore(&bank->bgc.lock, flags);
++ spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
+ return 0;
+ }
+
+@@ -210,29 +202,29 @@ static irqreturn_t brcmstb_gpio_wake_irq
+ static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
+ {
+ struct brcmstb_gpio_priv *priv = bank->parent_priv;
+- struct irq_domain *irq_domain = bank->bgc.gc.irqdomain;
++ struct irq_domain *irq_domain = bank->gc.irqdomain;
+ void __iomem *reg_base = priv->reg_base;
+ unsigned long status;
+ unsigned long flags;
+
+- spin_lock_irqsave(&bank->bgc.lock, flags);
+- while ((status = bank->bgc.read_reg(reg_base + GIO_STAT(bank->id)) &
+- bank->bgc.read_reg(reg_base + GIO_MASK(bank->id)))) {
++ spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
++ while ((status = bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
++ bank->gc.read_reg(reg_base + GIO_MASK(bank->id)))) {
+ int bit;
+
+ for_each_set_bit(bit, &status, 32) {
+- u32 stat = bank->bgc.read_reg(reg_base +
++ u32 stat = bank->gc.read_reg(reg_base +
+ GIO_STAT(bank->id));
+ if (bit >= bank->width)
+ dev_warn(&priv->pdev->dev,
+ "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
+ bank->id, bit);
+- bank->bgc.write_reg(reg_base + GIO_STAT(bank->id),
++ bank->gc.write_reg(reg_base + GIO_STAT(bank->id),
+ stat | BIT(bit));
+ generic_handle_irq(irq_find_mapping(irq_domain, bit));
+ }
+ }
+- spin_unlock_irqrestore(&bank->bgc.lock, flags);
++ spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
+ }
+
+ /* Each UPG GIO block has one IRQ for all banks */
+@@ -303,9 +295,7 @@ static int brcmstb_gpio_remove(struct pl
+ */
+ list_for_each(pos, &priv->bank_list) {
+ bank = list_entry(pos, struct brcmstb_gpio_bank, node);
+- ret = bgpio_remove(&bank->bgc);
+- if (ret)
+- dev_err(&pdev->dev, "gpiochip_remove fail in cleanup\n");
++ gpiochip_remove(&bank->gc);
+ }
+ if (priv->reboot_notifier.notifier_call) {
+ ret = unregister_reboot_notifier(&priv->reboot_notifier);
+@@ -320,7 +310,7 @@ static int brcmstb_gpio_of_xlate(struct
+ const struct of_phandle_args *gpiospec, u32 *flags)
+ {
+ struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
+- struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
++ struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
+ int offset;
+
+ if (gc->of_gpio_n_cells != 2) {
+@@ -398,9 +388,9 @@ static int brcmstb_gpio_irq_setup(struct
+ if (priv->can_wake)
+ bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
+
+- gpiochip_irqchip_add(&bank->bgc.gc, &bank->irq_chip, 0,
++ gpiochip_irqchip_add(&bank->gc, &bank->irq_chip, 0,
+ handle_simple_irq, IRQ_TYPE_NONE);
+- gpiochip_set_chained_irqchip(&bank->bgc.gc, &bank->irq_chip,
++ gpiochip_set_chained_irqchip(&bank->gc, &bank->irq_chip,
+ priv->parent_irq, brcmstb_gpio_irq_handler);
+
+ return 0;
+@@ -451,7 +441,6 @@ static int brcmstb_gpio_probe(struct pla
+ of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
+ bank_width) {
+ struct brcmstb_gpio_bank *bank;
+- struct bgpio_chip *bgc;
+ struct gpio_chip *gc;
+
+ bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
+@@ -473,8 +462,8 @@ static int brcmstb_gpio_probe(struct pla
+ * Regs are 4 bytes wide, have data reg, no set/clear regs,
+ * and direction bits have 0 = output and 1 = input
+ */
+- bgc = &bank->bgc;
+- err = bgpio_init(bgc, dev, 4,
++ gc = &bank->gc;
++ err = bgpio_init(gc, dev, 4,
+ reg_base + GIO_DATA(bank->id),
+ NULL, NULL, NULL,
+ reg_base + GIO_IODIR(bank->id), 0);
+@@ -483,7 +472,6 @@ static int brcmstb_gpio_probe(struct pla
+ goto fail;
+ }
+
+- gc = &bgc->gc;
+ gc->of_node = np;
+ gc->owner = THIS_MODULE;
+ gc->label = np->full_name;
+@@ -497,9 +485,9 @@ static int brcmstb_gpio_probe(struct pla
+ * Mask all interrupts by default, since wakeup interrupts may
+ * be retained from S5 cold boot
+ */
+- bank->bgc.write_reg(reg_base + GIO_MASK(bank->id), 0);
++ gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
+
+- err = gpiochip_add(gc);
++ err = gpiochip_add_data(gc, bank);
+ if (err) {
+ dev_err(dev, "Could not add gpiochip for bank %d\n",
+ bank->id);
+--- a/drivers/gpio/gpio-clps711x.c
++++ b/drivers/gpio/gpio-clps711x.c
+@@ -10,24 +10,23 @@
+ */
+
+ #include <linux/err.h>
+-#include <linux/gpio.h>
+ #include <linux/module.h>
+-#include <linux/basic_mmio_gpio.h>
++#include <linux/gpio/driver.h>
+ #include <linux/platform_device.h>
+
+ static int clps711x_gpio_probe(struct platform_device *pdev)
+ {
+ struct device_node *np = pdev->dev.of_node;
+ void __iomem *dat, *dir;
+- struct bgpio_chip *bgc;
++ struct gpio_chip *gc;
+ struct resource *res;
+ int err, id = np ? of_alias_get_id(np, "gpio") : pdev->id;
+
+ if ((id < 0) || (id > 4))
+ return -ENODEV;
+
+- bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
+- if (!bgc)
++ gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
++ if (!gc)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+@@ -43,11 +42,11 @@ static int clps711x_gpio_probe(struct pl
+ switch (id) {
+ case 3:
+ /* PORTD is inverted logic for direction register */
+- err = bgpio_init(bgc, &pdev->dev, 1, dat, NULL, NULL,
++ err = bgpio_init(gc, &pdev->dev, 1, dat, NULL, NULL,
+ NULL, dir, 0);
+ break;
+ default:
+- err = bgpio_init(bgc, &pdev->dev, 1, dat, NULL, NULL,
++ err = bgpio_init(gc, &pdev->dev, 1, dat, NULL, NULL,
+ dir, NULL, 0);
+ break;
+ }
+@@ -58,24 +57,25 @@ static int clps711x_gpio_probe(struct pl
+ switch (id) {
+ case 4:
+ /* PORTE is 3 lines only */
+- bgc->gc.ngpio = 3;
++ gc->ngpio = 3;
+ break;
+ default:
+ break;
+ }
+
+- bgc->gc.base = id * 8;
+- bgc->gc.owner = THIS_MODULE;
+- platform_set_drvdata(pdev, bgc);
++ gc->base = id * 8;
++ gc->owner = THIS_MODULE;
++ platform_set_drvdata(pdev, gc);
+
+- return gpiochip_add(&bgc->gc);
++ return gpiochip_add_data(gc, NULL);
+ }
+
+ static int clps711x_gpio_remove(struct platform_device *pdev)
+ {
+- struct bgpio_chip *bgc = platform_get_drvdata(pdev);
++ struct gpio_chip *gc = platform_get_drvdata(pdev);
+
+- return bgpio_remove(bgc);
++ gpiochip_remove(gc);
++ return 0;
+ }
+
+ static const struct of_device_id __maybe_unused clps711x_gpio_ids[] = {
+--- a/drivers/gpio/gpio-dwapb.c
++++ b/drivers/gpio/gpio-dwapb.c
+@@ -7,7 +7,9 @@
+ *
+ * All enquiries to support@picochip.com
+ */
+-#include <linux/basic_mmio_gpio.h>
++#include <linux/gpio/driver.h>
++/* FIXME: for gpio_get_value(), replace this with direct register read */
++#include <linux/gpio.h>
+ #include <linux/err.h>
+ #include <linux/init.h>
+ #include <linux/interrupt.h>
+@@ -66,7 +68,7 @@ struct dwapb_context {
+ #endif
+
+ struct dwapb_gpio_port {
+- struct bgpio_chip bgc;
++ struct gpio_chip gc;
+ bool is_registered;
+ struct dwapb_gpio *gpio;
+ #ifdef CONFIG_PM_SLEEP
+@@ -83,33 +85,26 @@ struct dwapb_gpio {
+ struct irq_domain *domain;
+ };
+
+-static inline struct dwapb_gpio_port *
+-to_dwapb_gpio_port(struct bgpio_chip *bgc)
+-{
+- return container_of(bgc, struct dwapb_gpio_port, bgc);
+-}
+-
+ static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
+ {
+- struct bgpio_chip *bgc = &gpio->ports[0].bgc;
++ struct gpio_chip *gc = &gpio->ports[0].gc;
+ void __iomem *reg_base = gpio->regs;
+
+- return bgc->read_reg(reg_base + offset);
++ return gc->read_reg(reg_base + offset);
+ }
+
+ static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
+ u32 val)
+ {
+- struct bgpio_chip *bgc = &gpio->ports[0].bgc;
++ struct gpio_chip *gc = &gpio->ports[0].gc;
+ void __iomem *reg_base = gpio->regs;
+
+- bgc->write_reg(reg_base + offset, val);
++ gc->write_reg(reg_base + offset, val);
+ }
+
+ static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+- struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc);
++ struct dwapb_gpio_port *port = gpiochip_get_data(gc);
+ struct dwapb_gpio *gpio = port->gpio;
+
+ return irq_find_mapping(gpio->domain, offset);
+@@ -119,7 +114,7 @@ static void dwapb_toggle_trigger(struct
+ {
+ u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);
+
+- if (gpio_get_value(gpio->ports[0].bgc.gc.base + offs))
++ if (gpio_get_value(gpio->ports[0].gc.base + offs))
+ v &= ~BIT(offs);
+ else
+ v |= BIT(offs);
+@@ -162,39 +157,39 @@ static void dwapb_irq_enable(struct irq_
+ {
+ struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
+ struct dwapb_gpio *gpio = igc->private;
+- struct bgpio_chip *bgc = &gpio->ports[0].bgc;
++ struct gpio_chip *gc = &gpio->ports[0].gc;
+ unsigned long flags;
+ u32 val;
+
+- spin_lock_irqsave(&bgc->lock, flags);
++ spin_lock_irqsave(&gc->bgpio_lock, flags);
+ val = dwapb_read(gpio, GPIO_INTEN);
+ val |= BIT(d->hwirq);
+ dwapb_write(gpio, GPIO_INTEN, val);
+- spin_unlock_irqrestore(&bgc->lock, flags);
++ spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+ }
+
+ static void dwapb_irq_disable(struct irq_data *d)
+ {
+ struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
+ struct dwapb_gpio *gpio = igc->private;
+- struct bgpio_chip *bgc = &gpio->ports[0].bgc;
++ struct gpio_chip *gc = &gpio->ports[0].gc;
+ unsigned long flags;
+ u32 val;
+
+- spin_lock_irqsave(&bgc->lock, flags);
++ spin_lock_irqsave(&gc->bgpio_lock, flags);
+ val = dwapb_read(gpio, GPIO_INTEN);
+ val &= ~BIT(d->hwirq);
+ dwapb_write(gpio, GPIO_INTEN, val);
+- spin_unlock_irqrestore(&bgc->lock, flags);
++ spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+ }
+
+ static int dwapb_irq_reqres(struct irq_data *d)
+ {
+ struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
+ struct dwapb_gpio *gpio = igc->private;
+- struct bgpio_chip *bgc = &gpio->ports[0].bgc;
++ struct gpio_chip *gc = &gpio->ports[0].gc;
+
+- if (gpiochip_lock_as_irq(&bgc->gc, irqd_to_hwirq(d))) {
++ if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) {
+ dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
+ irqd_to_hwirq(d));
+ return -EINVAL;
+@@ -206,16 +201,16 @@ static void dwapb_irq_relres(struct irq_
+ {
+ struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
+ struct dwapb_gpio *gpio = igc->private;
+- struct bgpio_chip *bgc = &gpio->ports[0].bgc;
++ struct gpio_chip *gc = &gpio->ports[0].gc;
+
+- gpiochip_unlock_as_irq(&bgc->gc, irqd_to_hwirq(d));
++ gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
+ }
+
+ static int dwapb_irq_set_type(struct irq_data *d, u32 type)
+ {
+ struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
+ struct dwapb_gpio *gpio = igc->private;
+- struct bgpio_chip *bgc = &gpio->ports[0].bgc;
++ struct gpio_chip *gc = &gpio->ports[0].gc;
+ int bit = d->hwirq;
+ unsigned long level, polarity, flags;
+
+@@ -223,7 +218,7 @@ static int dwapb_irq_set_type(struct irq
+ IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
+ return -EINVAL;
+
+- spin_lock_irqsave(&bgc->lock, flags);
++ spin_lock_irqsave(&gc->bgpio_lock, flags);
+ level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
+ polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
+
+@@ -254,7 +249,7 @@ static int dwapb_irq_set_type(struct irq
+
+ dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
+ dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
+- spin_unlock_irqrestore(&bgc->lock, flags);
++ spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+
+ return 0;
+ }
+@@ -262,13 +257,12 @@ static int dwapb_irq_set_type(struct irq
+ static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
+ unsigned offset, unsigned debounce)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+- struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc);
++ struct dwapb_gpio_port *port = gpiochip_get_data(gc);
+ struct dwapb_gpio *gpio = port->gpio;
+ unsigned long flags, val_deb;
+- unsigned long mask = bgc->pin2mask(bgc, offset);
++ unsigned long mask = gc->pin2mask(gc, offset);
+
+- spin_lock_irqsave(&bgc->lock, flags);
++ spin_lock_irqsave(&gc->bgpio_lock, flags);
+
+ val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
+ if (debounce)
+@@ -276,7 +270,7 @@ static int dwapb_gpio_set_debounce(struc
+ else
+ dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
+
+- spin_unlock_irqrestore(&bgc->lock, flags);
++ spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+
+ return 0;
+ }
+@@ -295,7 +289,7 @@ static void dwapb_configure_irqs(struct
+ struct dwapb_gpio_port *port,
+ struct dwapb_port_property *pp)
+ {
+- struct gpio_chip *gc = &port->bgc.gc;
++ struct gpio_chip *gc = &port->gc;
+ struct device_node *node = pp->node;
+ struct irq_chip_generic *irq_gc = NULL;
+ unsigned int hwirq, ngpio = gc->ngpio;
+@@ -369,13 +363,13 @@ static void dwapb_configure_irqs(struct
+ for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
+ irq_create_mapping(gpio->domain, hwirq);
+
+- port->bgc.gc.to_irq = dwapb_gpio_to_irq;
++ port->gc.to_irq = dwapb_gpio_to_irq;
+ }
+
+ static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
+ {
+ struct dwapb_gpio_port *port = &gpio->ports[0];
+- struct gpio_chip *gc = &port->bgc.gc;
++ struct gpio_chip *gc = &port->gc;
+ unsigned int ngpio = gc->ngpio;
+ irq_hw_number_t hwirq;
+
+@@ -412,7 +406,7 @@ static int dwapb_gpio_add_port(struct dw
+ dirout = gpio->regs + GPIO_SWPORTA_DDR +
+ (pp->idx * GPIO_SWPORT_DDR_SIZE);
+
+- err = bgpio_init(&port->bgc, gpio->dev, 4, dat, set, NULL, dirout,
++ err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
+ NULL, false);
+ if (err) {
+ dev_err(gpio->dev, "failed to init gpio chip for %s\n",
+@@ -421,19 +415,19 @@ static int dwapb_gpio_add_port(struct dw
+ }
+
+ #ifdef CONFIG_OF_GPIO
+- port->bgc.gc.of_node = pp->node;
++ port->gc.of_node = pp->node;
+ #endif
+- port->bgc.gc.ngpio = pp->ngpio;
+- port->bgc.gc.base = pp->gpio_base;
++ port->gc.ngpio = pp->ngpio;
++ port->gc.base = pp->gpio_base;
+
+ /* Only port A support debounce */
+ if (pp->idx == 0)
+- port->bgc.gc.set_debounce = dwapb_gpio_set_debounce;
++ port->gc.set_debounce = dwapb_gpio_set_debounce;
+
+ if (pp->irq)
+ dwapb_configure_irqs(gpio, port, pp);
+
+- err = gpiochip_add(&port->bgc.gc);
++ err = gpiochip_add_data(&port->gc, port);
+ if (err)
+ dev_err(gpio->dev, "failed to register gpiochip for %s\n",
+ pp->name);
+@@ -449,7 +443,7 @@ static void dwapb_gpio_unregister(struct
+
+ for (m = 0; m < gpio->nr_ports; ++m)
+ if (gpio->ports[m].is_registered)
+- gpiochip_remove(&gpio->ports[m].bgc.gc);
++ gpiochip_remove(&gpio->ports[m].gc);
+ }
+
+ static struct dwapb_platform_data *
+@@ -591,11 +585,11 @@ static int dwapb_gpio_suspend(struct dev
+ {
+ struct platform_device *pdev = to_platform_device(dev);
+ struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
+- struct bgpio_chip *bgc = &gpio->ports[0].bgc;
++ struct gpio_chip *gc = &gpio->ports[0].gc;
+ unsigned long flags;
+ int i;
+
+- spin_lock_irqsave(&bgc->lock, flags);
++ spin_lock_irqsave(&gc->bgpio_lock, flags);
+ for (i = 0; i < gpio->nr_ports; i++) {
+ unsigned int offset;
+ unsigned int idx = gpio->ports[i].idx;
+@@ -624,7 +618,7 @@ static int dwapb_gpio_suspend(struct dev
+ dwapb_write(gpio, GPIO_INTMASK, 0xffffffff);
+ }
+ }
+- spin_unlock_irqrestore(&bgc->lock, flags);
++ spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+
+ return 0;
+ }
+@@ -633,11 +627,11 @@ static int dwapb_gpio_resume(struct devi
+ {
+ struct platform_device *pdev = to_platform_device(dev);
+ struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
+- struct bgpio_chip *bgc = &gpio->ports[0].bgc;
++ struct gpio_chip *gc = &gpio->ports[0].gc;
+ unsigned long flags;
+ int i;
+
+- spin_lock_irqsave(&bgc->lock, flags);
++ spin_lock_irqsave(&gc->bgpio_lock, flags);
+ for (i = 0; i < gpio->nr_ports; i++) {
+ unsigned int offset;
+ unsigned int idx = gpio->ports[i].idx;
+@@ -666,7 +660,7 @@ static int dwapb_gpio_resume(struct devi
+ dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
+ }
+ }
+- spin_unlock_irqrestore(&bgc->lock, flags);
++ spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+
+ return 0;
+ }
+--- a/drivers/gpio/gpio-ep93xx.c
++++ b/drivers/gpio/gpio-ep93xx.c
+@@ -16,10 +16,11 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
+-#include <linux/gpio.h>
+ #include <linux/irq.h>
+ #include <linux/slab.h>
+-#include <linux/basic_mmio_gpio.h>
++#include <linux/gpio/driver.h>
++/* FIXME: this is here for gpio_to_irq() - get rid of this! */
++#include <linux/gpio.h>
+
+ #include <mach/hardware.h>
+ #include <mach/gpio-ep93xx.h>
+@@ -28,7 +29,7 @@
+
+ struct ep93xx_gpio {
+ void __iomem *mmio_base;
+- struct bgpio_chip bgc[8];
++ struct gpio_chip gc[8];
+ };
+
+ /*************************************************************************
+@@ -319,26 +320,26 @@ static int ep93xx_gpio_to_irq(struct gpi
+ return 64 + gpio;
+ }
+
+-static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev,
++static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev,
+ void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
+ {
+ void __iomem *data = mmio_base + bank->data;
+ void __iomem *dir = mmio_base + bank->dir;
+ int err;
+
+- err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, 0);
++ err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
+ if (err)
+ return err;
+
+- bgc->gc.label = bank->label;
+- bgc->gc.base = bank->base;
++ gc->label = bank->label;
++ gc->base = bank->base;
+
+ if (bank->has_debounce) {
+- bgc->gc.set_debounce = ep93xx_gpio_set_debounce;
+- bgc->gc.to_irq = ep93xx_gpio_to_irq;
++ gc->set_debounce = ep93xx_gpio_set_debounce;
++ gc->to_irq = ep93xx_gpio_to_irq;
+ }
+
+- return gpiochip_add(&bgc->gc);
++ return gpiochip_add_data(gc, NULL);
+ }
+
+ static int ep93xx_gpio_probe(struct platform_device *pdev)
+@@ -358,10 +359,10 @@ static int ep93xx_gpio_probe(struct plat
+ return PTR_ERR(ep93xx_gpio->mmio_base);
+
+ for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
+- struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i];
++ struct gpio_chip *gc = &ep93xx_gpio->gc[i];
+ struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
+
+- if (ep93xx_gpio_add_bank(bgc, &pdev->dev,
++ if (ep93xx_gpio_add_bank(gc, &pdev->dev,
+ ep93xx_gpio->mmio_base, bank))
+ dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
+ bank->label);
+--- a/drivers/gpio/gpio-etraxfs.c
++++ b/drivers/gpio/gpio-etraxfs.c
+@@ -1,12 +1,10 @@
+ #include <linux/kernel.h>
+ #include <linux/init.h>
+-#include <linux/gpio.h>
+ #include <linux/gpio/driver.h>
+ #include <linux/of_gpio.h>
+ #include <linux/io.h>
+ #include <linux/interrupt.h>
+ #include <linux/platform_device.h>
+-#include <linux/basic_mmio_gpio.h>
+
+ #define ETRAX_FS_rw_pa_dout 0
+ #define ETRAX_FS_r_pa_din 4
+@@ -67,7 +65,7 @@ struct etraxfs_gpio_block {
+ };
+
+ struct etraxfs_gpio_chip {
+- struct bgpio_chip bgc;
++ struct gpio_chip gc;
+ struct etraxfs_gpio_block *block;
+ };
+
+@@ -176,11 +174,6 @@ static const struct etraxfs_gpio_info et
+ .rw_intr_pins = ARTPEC3_rw_intr_pins,
+ };
+
+-static struct etraxfs_gpio_chip *to_etraxfs(struct gpio_chip *gc)
+-{
+- return container_of(gc, struct etraxfs_gpio_chip, bgc.gc);
+-}
+-
+ static unsigned int etraxfs_gpio_chip_to_port(struct gpio_chip *gc)
+ {
+ return gc->label[0] - 'A';
+@@ -220,13 +213,13 @@ static unsigned int etraxfs_gpio_to_grou
+ static unsigned int etraxfs_gpio_to_group_pin(struct etraxfs_gpio_chip *chip,
+ unsigned int gpio)
+ {
+- return 4 * etraxfs_gpio_chip_to_port(&chip->bgc.gc) + gpio / 8;
++ return 4 * etraxfs_gpio_chip_to_port(&chip->gc) + gpio / 8;
+ }
+
+ static void etraxfs_gpio_irq_ack(struct irq_data *d)
+ {
+ struct etraxfs_gpio_chip *chip =
+- to_etraxfs(irq_data_get_irq_chip_data(d));
++ gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ struct etraxfs_gpio_block *block = chip->block;
+ unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
+
+@@ -236,7 +229,7 @@ static void etraxfs_gpio_irq_ack(struct
+ static void etraxfs_gpio_irq_mask(struct irq_data *d)
+ {
+ struct etraxfs_gpio_chip *chip =
+- to_etraxfs(irq_data_get_irq_chip_data(d));
++ gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ struct etraxfs_gpio_block *block = chip->block;
+ unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
+
+@@ -249,7 +242,7 @@ static void etraxfs_gpio_irq_mask(struct
+ static void etraxfs_gpio_irq_unmask(struct irq_data *d)
+ {
+ struct etraxfs_gpio_chip *chip =
+- to_etraxfs(irq_data_get_irq_chip_data(d));
++ gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ struct etraxfs_gpio_block *block = chip->block;
+ unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
+
+@@ -262,7 +255,7 @@ static void etraxfs_gpio_irq_unmask(stru
+ static int etraxfs_gpio_irq_set_type(struct irq_data *d, u32 type)
+ {
+ struct etraxfs_gpio_chip *chip =
+- to_etraxfs(irq_data_get_irq_chip_data(d));
++ gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ struct etraxfs_gpio_block *block = chip->block;
+ unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
+ u32 cfg;
+@@ -299,7 +292,7 @@ static int etraxfs_gpio_irq_set_type(str
+ static int etraxfs_gpio_irq_request_resources(struct irq_data *d)
+ {
+ struct etraxfs_gpio_chip *chip =
+- to_etraxfs(irq_data_get_irq_chip_data(d));
++ gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ struct etraxfs_gpio_block *block = chip->block;
+ unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
+ int ret = -EBUSY;
+@@ -308,7 +301,7 @@ static int etraxfs_gpio_irq_request_reso
+ if (block->group[grpirq])
+ goto out;
+
+- ret = gpiochip_lock_as_irq(&chip->bgc.gc, d->hwirq);
++ ret = gpiochip_lock_as_irq(&chip->gc, d->hwirq);
+ if (ret)
+ goto out;
+
+@@ -330,13 +323,13 @@ out:
+ static void etraxfs_gpio_irq_release_resources(struct irq_data *d)
+ {
+ struct etraxfs_gpio_chip *chip =
+- to_etraxfs(irq_data_get_irq_chip_data(d));
++ gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ struct etraxfs_gpio_block *block = chip->block;
+ unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
+
+ spin_lock(&block->lock);
+ block->group[grpirq] = 0;
+- gpiochip_unlock_as_irq(&chip->bgc.gc, d->hwirq);
++ gpiochip_unlock_as_irq(&chip->gc, d->hwirq);
+ spin_unlock(&block->lock);
+ }
+
+@@ -419,7 +412,7 @@ static int etraxfs_gpio_probe(struct pla
+
+ for (i = 0; i < info->num_ports; i++) {
+ struct etraxfs_gpio_chip *chip = &chips[i];
+- struct bgpio_chip *bgc = &chip->bgc;
++ struct gpio_chip *gc = &chip->gc;
+ const struct etraxfs_gpio_port *port = &info->ports[i];
+ unsigned long flags = BGPIOF_READ_OUTPUT_REG_SET;
+ void __iomem *dat = regs + port->din;
+@@ -433,7 +426,7 @@ static int etraxfs_gpio_probe(struct pla
+ flags = BGPIOF_NO_OUTPUT;
+ }
+
+- ret = bgpio_init(bgc, dev, 4,
++ ret = bgpio_init(gc, dev, 4,
+ dat, set, NULL, dirout, NULL,
+ flags);
+ if (ret) {
+@@ -442,28 +435,28 @@ static int etraxfs_gpio_probe(struct pla
+ continue;
+ }
+
+- bgc->gc.ngpio = port->ngpio;
+- bgc->gc.label = port->label;
++ gc->ngpio = port->ngpio;
++ gc->label = port->label;
+
+- bgc->gc.of_node = dev->of_node;
+- bgc->gc.of_gpio_n_cells = 3;
+- bgc->gc.of_xlate = etraxfs_gpio_of_xlate;
++ gc->of_node = dev->of_node;
++ gc->of_gpio_n_cells = 3;
++ gc->of_xlate = etraxfs_gpio_of_xlate;
+
+- ret = gpiochip_add(&bgc->gc);
++ ret = gpiochip_add_data(gc, chip);
+ if (ret) {
+ dev_err(dev, "Unable to register port %s\n",
+- bgc->gc.label);
++ gc->label);
+ continue;
+ }
+
+ if (i > 0 && !allportsirq)
+ continue;
+
+- ret = gpiochip_irqchip_add(&bgc->gc, &etraxfs_gpio_irq_chip, 0,
++ ret = gpiochip_irqchip_add(gc, &etraxfs_gpio_irq_chip, 0,
+ handle_level_irq, IRQ_TYPE_NONE);
+ if (ret) {
+ dev_err(dev, "Unable to add irqchip to port %s\n",
+- bgc->gc.label);
++ gc->label);
+ }
+ }
+
+--- a/drivers/gpio/gpio-ge.c
++++ b/drivers/gpio/gpio-ge.c
+@@ -24,7 +24,7 @@
+ #include <linux/of_gpio.h>
+ #include <linux/of_address.h>
+ #include <linux/module.h>
+-#include <linux/basic_mmio_gpio.h>
++#include <linux/gpio/driver.h>
+
+ #define GEF_GPIO_DIRECT 0x00
+ #define GEF_GPIO_IN 0x04
+@@ -55,19 +55,19 @@ static int __init gef_gpio_probe(struct
+ {
+ const struct of_device_id *of_id =
+ of_match_device(gef_gpio_ids, &pdev->dev);
+- struct bgpio_chip *bgc;
++ struct gpio_chip *gc;
+ void __iomem *regs;
+ int ret;
+
+- bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
+- if (!bgc)
++ gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
++ if (!gc)
+ return -ENOMEM;
+
+ regs = of_iomap(pdev->dev.of_node, 0);
+ if (!regs)
+ return -ENOMEM;
+
+- ret = bgpio_init(bgc, &pdev->dev, 4, regs + GEF_GPIO_IN,
++ ret = bgpio_init(gc, &pdev->dev, 4, regs + GEF_GPIO_IN,
+ regs + GEF_GPIO_OUT, NULL, NULL,
+ regs + GEF_GPIO_DIRECT, BGPIOF_BIG_ENDIAN_BYTE_ORDER);
+ if (ret) {
+@@ -76,20 +76,20 @@ static int __init gef_gpio_probe(struct
+ }
+
+ /* Setup pointers to chip functions */
+- bgc->gc.label = devm_kstrdup(&pdev->dev, pdev->dev.of_node->full_name,
++ gc->label = devm_kstrdup(&pdev->dev, pdev->dev.of_node->full_name,
+ GFP_KERNEL);
+- if (!bgc->gc.label) {
++ if (!gc->label) {
+ ret = -ENOMEM;
+ goto err0;
+ }
+
+- bgc->gc.base = -1;
+- bgc->gc.ngpio = (u16)(uintptr_t)of_id->data;
+- bgc->gc.of_gpio_n_cells = 2;
+- bgc->gc.of_node = pdev->dev.of_node;
++ gc->base = -1;
++ gc->ngpio = (u16)(uintptr_t)of_id->data;
++ gc->of_gpio_n_cells = 2;
++ gc->of_node = pdev->dev.of_node;
+
+ /* This function adds a memory mapped GPIO chip */
+- ret = gpiochip_add(&bgc->gc);
++ ret = gpiochip_add_data(gc, NULL);
+ if (ret)
+ goto err0;
+
+--- a/drivers/gpio/gpio-generic.c
++++ b/drivers/gpio/gpio-generic.c
+@@ -56,11 +56,10 @@ o ` ~~~~\___/
+ #include <linux/log2.h>
+ #include <linux/ioport.h>
+ #include <linux/io.h>
+-#include <linux/gpio.h>
++#include <linux/gpio/driver.h>
+ #include <linux/slab.h>
+ #include <linux/platform_device.h>
+ #include <linux/mod_devicetable.h>
+-#include <linux/basic_mmio_gpio.h>
+
+ static void bgpio_write8(void __iomem *reg, unsigned long data)
+ {
+@@ -124,33 +123,30 @@ static unsigned long bgpio_read32be(void
+ return ioread32be(reg);
+ }
+
+-static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin)
++static unsigned long bgpio_pin2mask(struct gpio_chip *gc, unsigned int pin)
+ {
+ return 1 << pin;
+ }
+
+-static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc,
++static unsigned long bgpio_pin2mask_be(struct gpio_chip *gc,
+ unsigned int pin)
+ {
+- return 1 << (bgc->bits - 1 - pin);
++ return 1 << (gc->bgpio_bits - 1 - pin);
+ }
+
+ static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+- unsigned long pinmask = bgc->pin2mask(bgc, gpio);
++ unsigned long pinmask = gc->pin2mask(gc, gpio);
+
+- if (bgc->dir & pinmask)
+- return !!(bgc->read_reg(bgc->reg_set) & pinmask);
++ if (gc->bgpio_dir & pinmask)
++ return !!(gc->read_reg(gc->reg_set) & pinmask);
+ else
+- return !!(bgc->read_reg(bgc->reg_dat) & pinmask);
++ return !!(gc->read_reg(gc->reg_dat) & pinmask);
+ }
+
+ static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+-
+- return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio));
++ return !!(gc->read_reg(gc->reg_dat) & gc->pin2mask(gc, gpio));
+ }
+
+ static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
+@@ -159,53 +155,50 @@ static void bgpio_set_none(struct gpio_c
+
+ static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+- unsigned long mask = bgc->pin2mask(bgc, gpio);
++ unsigned long mask = gc->pin2mask(gc, gpio);
+ unsigned long flags;
+
+- spin_lock_irqsave(&bgc->lock, flags);
++ spin_lock_irqsave(&gc->bgpio_lock, flags);
+
+ if (val)
+- bgc->data |= mask;
++ gc->bgpio_data |= mask;
+ else
+- bgc->data &= ~mask;
++ gc->bgpio_data &= ~mask;
+
+- bgc->write_reg(bgc->reg_dat, bgc->data);
++ gc->write_reg(gc->reg_dat, gc->bgpio_data);
+
+- spin_unlock_irqrestore(&bgc->lock, flags);
++ spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+ }
+
+ static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
+ int val)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+- unsigned long mask = bgc->pin2mask(bgc, gpio);
++ unsigned long mask = gc->pin2mask(gc, gpio);
+
+ if (val)
+- bgc->write_reg(bgc->reg_set, mask);
++ gc->write_reg(gc->reg_set, mask);
+ else
+- bgc->write_reg(bgc->reg_clr, mask);
++ gc->write_reg(gc->reg_clr, mask);
+ }
+
+ static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+- unsigned long mask = bgc->pin2mask(bgc, gpio);
++ unsigned long mask = gc->pin2mask(gc, gpio);
+ unsigned long flags;
+
+- spin_lock_irqsave(&bgc->lock, flags);
++ spin_lock_irqsave(&gc->bgpio_lock, flags);
+
+ if (val)
+- bgc->data |= mask;
++ gc->bgpio_data |= mask;
+ else
+- bgc->data &= ~mask;
++ gc->bgpio_data &= ~mask;
+
+- bgc->write_reg(bgc->reg_set, bgc->data);
++ gc->write_reg(gc->reg_set, gc->bgpio_data);
+
+- spin_unlock_irqrestore(&bgc->lock, flags);
++ spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+ }
+
+-static void bgpio_multiple_get_masks(struct bgpio_chip *bgc,
++static void bgpio_multiple_get_masks(struct gpio_chip *gc,
+ unsigned long *mask, unsigned long *bits,
+ unsigned long *set_mask,
+ unsigned long *clear_mask)
+@@ -215,19 +208,19 @@ static void bgpio_multiple_get_masks(str
+ *set_mask = 0;
+ *clear_mask = 0;
+
+- for (i = 0; i < bgc->bits; i++) {
++ for (i = 0; i < gc->bgpio_bits; i++) {
+ if (*mask == 0)
+ break;
+ if (__test_and_clear_bit(i, mask)) {
+ if (test_bit(i, bits))
+- *set_mask |= bgc->pin2mask(bgc, i);
++ *set_mask |= gc->pin2mask(gc, i);
+ else
+- *clear_mask |= bgc->pin2mask(bgc, i);
++ *clear_mask |= gc->pin2mask(gc, i);
+ }
+ }
+ }
+
+-static void bgpio_set_multiple_single_reg(struct bgpio_chip *bgc,
++static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
+ unsigned long *mask,
+ unsigned long *bits,
+ void __iomem *reg)
+@@ -235,47 +228,42 @@ static void bgpio_set_multiple_single_re
+ unsigned long flags;
+ unsigned long set_mask, clear_mask;
+
+- spin_lock_irqsave(&bgc->lock, flags);
++ spin_lock_irqsave(&gc->bgpio_lock, flags);
+
+- bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);
++ bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
+
+- bgc->data |= set_mask;
+- bgc->data &= ~clear_mask;
++ gc->bgpio_data |= set_mask;
++ gc->bgpio_data &= ~clear_mask;
+
+- bgc->write_reg(reg, bgc->data);
++ gc->write_reg(reg, gc->bgpio_data);
+
+- spin_unlock_irqrestore(&bgc->lock, flags);
++ spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+ }
+
+ static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
+ unsigned long *bits)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+-
+- bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_dat);
++ bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
+ }
+
+ static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
+ unsigned long *bits)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+-
+- bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_set);
++ bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
+ }
+
+ static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
+ unsigned long *mask,
+ unsigned long *bits)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+ unsigned long set_mask, clear_mask;
+
+- bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);
++ bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
+
+ if (set_mask)
+- bgc->write_reg(bgc->reg_set, set_mask);
++ gc->write_reg(gc->reg_set, set_mask);
+ if (clear_mask)
+- bgc->write_reg(bgc->reg_clr, clear_mask);
++ gc->write_reg(gc->reg_clr, clear_mask);
+ }
+
+ static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
+@@ -299,111 +287,103 @@ static int bgpio_simple_dir_out(struct g
+
+ static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+ unsigned long flags;
+
+- spin_lock_irqsave(&bgc->lock, flags);
++ spin_lock_irqsave(&gc->bgpio_lock, flags);
+
+- bgc->dir &= ~bgc->pin2mask(bgc, gpio);
+- bgc->write_reg(bgc->reg_dir, bgc->dir);
++ gc->bgpio_dir &= ~gc->pin2mask(gc, gpio);
++ gc->write_reg(gc->reg_dir, gc->bgpio_dir);
+
+- spin_unlock_irqrestore(&bgc->lock, flags);
++ spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+
+ return 0;
+ }
+
+ static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+-
+- return (bgc->read_reg(bgc->reg_dir) & bgc->pin2mask(bgc, gpio)) ?
+- GPIOF_DIR_OUT : GPIOF_DIR_IN;
++ /* Return 0 if output, 1 of input */
++ return !(gc->read_reg(gc->reg_dir) & gc->pin2mask(gc, gpio));
+ }
+
+ static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+ unsigned long flags;
+
+ gc->set(gc, gpio, val);
+
+- spin_lock_irqsave(&bgc->lock, flags);
++ spin_lock_irqsave(&gc->bgpio_lock, flags);
+
+- bgc->dir |= bgc->pin2mask(bgc, gpio);
+- bgc->write_reg(bgc->reg_dir, bgc->dir);
++ gc->bgpio_dir |= gc->pin2mask(gc, gpio);
++ gc->write_reg(gc->reg_dir, gc->bgpio_dir);
+
+- spin_unlock_irqrestore(&bgc->lock, flags);
++ spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+
+ return 0;
+ }
+
+ static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+ unsigned long flags;
+
+- spin_lock_irqsave(&bgc->lock, flags);
++ spin_lock_irqsave(&gc->bgpio_lock, flags);
+
+- bgc->dir |= bgc->pin2mask(bgc, gpio);
+- bgc->write_reg(bgc->reg_dir, bgc->dir);
++ gc->bgpio_dir |= gc->pin2mask(gc, gpio);
++ gc->write_reg(gc->reg_dir, gc->bgpio_dir);
+
+- spin_unlock_irqrestore(&bgc->lock, flags);
++ spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+
+ return 0;
+ }
+
+ static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+ unsigned long flags;
+
+ gc->set(gc, gpio, val);
+
+- spin_lock_irqsave(&bgc->lock, flags);
++ spin_lock_irqsave(&gc->bgpio_lock, flags);
+
+- bgc->dir &= ~bgc->pin2mask(bgc, gpio);
+- bgc->write_reg(bgc->reg_dir, bgc->dir);
++ gc->bgpio_dir &= ~gc->pin2mask(gc, gpio);
++ gc->write_reg(gc->reg_dir, gc->bgpio_dir);
+
+- spin_unlock_irqrestore(&bgc->lock, flags);
++ spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+
+ return 0;
+ }
+
+ static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+-
+- return (bgc->read_reg(bgc->reg_dir) & bgc->pin2mask(bgc, gpio)) ?
+- GPIOF_DIR_IN : GPIOF_DIR_OUT;
++ /* Return 0 if output, 1 if input */
++ return !!(gc->read_reg(gc->reg_dir) & gc->pin2mask(gc, gpio));
+ }
+
+ static int bgpio_setup_accessors(struct device *dev,
+- struct bgpio_chip *bgc,
++ struct gpio_chip *gc,
+ bool bit_be,
+ bool byte_be)
+ {
+
+- switch (bgc->bits) {
++ switch (gc->bgpio_bits) {
+ case 8:
+- bgc->read_reg = bgpio_read8;
+- bgc->write_reg = bgpio_write8;
++ gc->read_reg = bgpio_read8;
++ gc->write_reg = bgpio_write8;
+ break;
+ case 16:
+ if (byte_be) {
+- bgc->read_reg = bgpio_read16be;
+- bgc->write_reg = bgpio_write16be;
++ gc->read_reg = bgpio_read16be;
++ gc->write_reg = bgpio_write16be;
+ } else {
+- bgc->read_reg = bgpio_read16;
+- bgc->write_reg = bgpio_write16;
++ gc->read_reg = bgpio_read16;
++ gc->write_reg = bgpio_write16;
+ }
+ break;
+ case 32:
+ if (byte_be) {
+- bgc->read_reg = bgpio_read32be;
+- bgc->write_reg = bgpio_write32be;
++ gc->read_reg = bgpio_read32be;
++ gc->write_reg = bgpio_write32be;
+ } else {
+- bgc->read_reg = bgpio_read32;
+- bgc->write_reg = bgpio_write32;
++ gc->read_reg = bgpio_read32;
++ gc->write_reg = bgpio_write32;
+ }
+ break;
+ #if BITS_PER_LONG >= 64
+@@ -413,17 +393,17 @@ static int bgpio_setup_accessors(struct
+ "64 bit big endian byte order unsupported\n");
+ return -EINVAL;
+ } else {
+- bgc->read_reg = bgpio_read64;
+- bgc->write_reg = bgpio_write64;
++ gc->read_reg = bgpio_read64;
++ gc->write_reg = bgpio_write64;
+ }
+ break;
+ #endif /* BITS_PER_LONG >= 64 */
+ default:
+- dev_err(dev, "unsupported data width %u bits\n", bgc->bits);
++ dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
+ return -EINVAL;
+ }
+
+- bgc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;
++ gc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;
+
+ return 0;
+ }
+@@ -450,44 +430,44 @@ static int bgpio_setup_accessors(struct
+ * - an input direction register (named "dirin") where a 1 bit indicates
+ * the GPIO is an input.
+ */
+-static int bgpio_setup_io(struct bgpio_chip *bgc,
++static int bgpio_setup_io(struct gpio_chip *gc,
+ void __iomem *dat,
+ void __iomem *set,
+ void __iomem *clr,
+ unsigned long flags)
+ {
+
+- bgc->reg_dat = dat;
+- if (!bgc->reg_dat)
++ gc->reg_dat = dat;
++ if (!gc->reg_dat)
+ return -EINVAL;
+
+ if (set && clr) {
+- bgc->reg_set = set;
+- bgc->reg_clr = clr;
+- bgc->gc.set = bgpio_set_with_clear;
+- bgc->gc.set_multiple = bgpio_set_multiple_with_clear;
++ gc->reg_set = set;
++ gc->reg_clr = clr;
++ gc->set = bgpio_set_with_clear;
++ gc->set_multiple = bgpio_set_multiple_with_clear;
+ } else if (set && !clr) {
+- bgc->reg_set = set;
+- bgc->gc.set = bgpio_set_set;
+- bgc->gc.set_multiple = bgpio_set_multiple_set;
++ gc->reg_set = set;
++ gc->set = bgpio_set_set;
++ gc->set_multiple = bgpio_set_multiple_set;
+ } else if (flags & BGPIOF_NO_OUTPUT) {
+- bgc->gc.set = bgpio_set_none;
+- bgc->gc.set_multiple = NULL;
++ gc->set = bgpio_set_none;
++ gc->set_multiple = NULL;
+ } else {
+- bgc->gc.set = bgpio_set;
+- bgc->gc.set_multiple = bgpio_set_multiple;
++ gc->set = bgpio_set;
++ gc->set_multiple = bgpio_set_multiple;
+ }
+
+ if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
+ (flags & BGPIOF_READ_OUTPUT_REG_SET))
+- bgc->gc.get = bgpio_get_set;
++ gc->get = bgpio_get_set;
+ else
+- bgc->gc.get = bgpio_get;
++ gc->get = bgpio_get;
+
+ return 0;
+ }
+
+-static int bgpio_setup_direction(struct bgpio_chip *bgc,
++static int bgpio_setup_direction(struct gpio_chip *gc,
+ void __iomem *dirout,
+ void __iomem *dirin,
+ unsigned long flags)
+@@ -495,21 +475,21 @@ static int bgpio_setup_direction(struct
+ if (dirout && dirin) {
+ return -EINVAL;
+ } else if (dirout) {
+- bgc->reg_dir = dirout;
+- bgc->gc.direction_output = bgpio_dir_out;
+- bgc->gc.direction_input = bgpio_dir_in;
+- bgc->gc.get_direction = bgpio_get_dir;
++ gc->reg_dir = dirout;
++ gc->direction_output = bgpio_dir_out;
++ gc->direction_input = bgpio_dir_in;
++ gc->get_direction = bgpio_get_dir;
+ } else if (dirin) {
+- bgc->reg_dir = dirin;
+- bgc->gc.direction_output = bgpio_dir_out_inv;
+- bgc->gc.direction_input = bgpio_dir_in_inv;
+- bgc->gc.get_direction = bgpio_get_dir_inv;
++ gc->reg_dir = dirin;
++ gc->direction_output = bgpio_dir_out_inv;
++ gc->direction_input = bgpio_dir_in_inv;
++ gc->get_direction = bgpio_get_dir_inv;
+ } else {
+ if (flags & BGPIOF_NO_OUTPUT)
+- bgc->gc.direction_output = bgpio_dir_out_err;
++ gc->direction_output = bgpio_dir_out_err;
+ else
+- bgc->gc.direction_output = bgpio_simple_dir_out;
+- bgc->gc.direction_input = bgpio_simple_dir_in;
++ gc->direction_output = bgpio_simple_dir_out;
++ gc->direction_input = bgpio_simple_dir_in;
+ }
+
+ return 0;
+@@ -523,14 +503,7 @@ static int bgpio_request(struct gpio_chi
+ return -EINVAL;
+ }
+
+-int bgpio_remove(struct bgpio_chip *bgc)
+-{
+- gpiochip_remove(&bgc->gc);
+- return 0;
+-}
+-EXPORT_SYMBOL_GPL(bgpio_remove);
+-
+-int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
++int bgpio_init(struct gpio_chip *gc, struct device *dev,
+ unsigned long sz, void __iomem *dat, void __iomem *set,
+ void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
+ unsigned long flags)
+@@ -540,36 +513,36 @@ int bgpio_init(struct bgpio_chip *bgc, s
+ if (!is_power_of_2(sz))
+ return -EINVAL;
+
+- bgc->bits = sz * 8;
+- if (bgc->bits > BITS_PER_LONG)
++ gc->bgpio_bits = sz * 8;
++ if (gc->bgpio_bits > BITS_PER_LONG)
+ return -EINVAL;
+
+- spin_lock_init(&bgc->lock);
+- bgc->gc.dev = dev;
+- bgc->gc.label = dev_name(dev);
+- bgc->gc.base = -1;
+- bgc->gc.ngpio = bgc->bits;
+- bgc->gc.request = bgpio_request;
++ spin_lock_init(&gc->bgpio_lock);
++ gc->dev = dev;
++ gc->label = dev_name(dev);
++ gc->base = -1;
++ gc->ngpio = gc->bgpio_bits;
++ gc->request = bgpio_request;
+
+- ret = bgpio_setup_io(bgc, dat, set, clr, flags);
++ ret = bgpio_setup_io(gc, dat, set, clr, flags);
+ if (ret)
+ return ret;
+
+- ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN,
++ ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN,
+ flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
+ if (ret)
+ return ret;
+
+- ret = bgpio_setup_direction(bgc, dirout, dirin, flags);
++ ret = bgpio_setup_direction(gc, dirout, dirin, flags);
+ if (ret)
+ return ret;
+
+- bgc->data = bgc->read_reg(bgc->reg_dat);
+- if (bgc->gc.set == bgpio_set_set &&
++ gc->bgpio_data = gc->read_reg(gc->reg_dat);
++ if (gc->set == bgpio_set_set &&
+ !(flags & BGPIOF_UNREADABLE_REG_SET))
+- bgc->data = bgc->read_reg(bgc->reg_set);
+- if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
+- bgc->dir = bgc->read_reg(bgc->reg_dir);
++ gc->bgpio_data = gc->read_reg(gc->reg_set);
++ if (gc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
++ gc->bgpio_dir = gc->read_reg(gc->reg_dir);
+
+ return ret;
+ }
+@@ -607,7 +580,7 @@ static int bgpio_pdev_probe(struct platf
+ unsigned long sz;
+ unsigned long flags = pdev->id_entry->driver_data;
+ int err;
+- struct bgpio_chip *bgc;
++ struct gpio_chip *gc;
+ struct bgpio_pdata *pdata = dev_get_platdata(dev);
+
+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
+@@ -636,32 +609,33 @@ static int bgpio_pdev_probe(struct platf
+ if (IS_ERR(dirin))
+ return PTR_ERR(dirin);
+
+- bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
+- if (!bgc)
++ gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
++ if (!gc)
+ return -ENOMEM;
+
+- err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags);
++ err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
+ if (err)
+ return err;
+
+ if (pdata) {
+ if (pdata->label)
+- bgc->gc.label = pdata->label;
+- bgc->gc.base = pdata->base;
++ gc->label = pdata->label;
++ gc->base = pdata->base;
+ if (pdata->ngpio > 0)
+- bgc->gc.ngpio = pdata->ngpio;
++ gc->ngpio = pdata->ngpio;
+ }
+
+- platform_set_drvdata(pdev, bgc);
++ platform_set_drvdata(pdev, gc);
+
+- return gpiochip_add(&bgc->gc);
++ return gpiochip_add_data(gc, NULL);
+ }
+
+ static int bgpio_pdev_remove(struct platform_device *pdev)
+ {
+- struct bgpio_chip *bgc = platform_get_drvdata(pdev);
++ struct gpio_chip *gc = platform_get_drvdata(pdev);
+
+- return bgpio_remove(bgc);
++ gpiochip_remove(gc);
++ return 0;
+ }
+
+ static const struct platform_device_id bgpio_id_table[] = {
+--- a/drivers/gpio/gpio-grgpio.c
++++ b/drivers/gpio/gpio-grgpio.c
+@@ -31,7 +31,7 @@
+ #include <linux/gpio.h>
+ #include <linux/slab.h>
+ #include <linux/err.h>
+-#include <linux/basic_mmio_gpio.h>
++#include <linux/gpio/driver.h>
+ #include <linux/interrupt.h>
+ #include <linux/irq.h>
+ #include <linux/irqdomain.h>
+@@ -63,7 +63,7 @@ struct grgpio_lirq {
+ };
+
+ struct grgpio_priv {
+- struct bgpio_chip bgc;
++ struct gpio_chip gc;
+ void __iomem *regs;
+ struct device *dev;
+
+@@ -92,29 +92,22 @@ struct grgpio_priv {
+ struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
+ };
+
+-static inline struct grgpio_priv *grgpio_gc_to_priv(struct gpio_chip *gc)
+-{
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+-
+- return container_of(bgc, struct grgpio_priv, bgc);
+-}
+-
+ static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
+ int val)
+ {
+- struct bgpio_chip *bgc = &priv->bgc;
+- unsigned long mask = bgc->pin2mask(bgc, offset);
++ struct gpio_chip *gc = &priv->gc;
++ unsigned long mask = gc->pin2mask(gc, offset);
+
+ if (val)
+ priv->imask |= mask;
+ else
+ priv->imask &= ~mask;
+- bgc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
++ gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
+ }
+
+ static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
+ {
+- struct grgpio_priv *priv = grgpio_gc_to_priv(gc);
++ struct grgpio_priv *priv = gpiochip_get_data(gc);
+
+ if (offset >= gc->ngpio)
+ return -ENXIO;
+@@ -158,15 +151,15 @@ static int grgpio_irq_set_type(struct ir
+ return -EINVAL;
+ }
+
+- spin_lock_irqsave(&priv->bgc.lock, flags);
++ spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
+
+- ipol = priv->bgc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
+- iedge = priv->bgc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
++ ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
++ iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
+
+- priv->bgc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
+- priv->bgc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
++ priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
++ priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
+
+- spin_unlock_irqrestore(&priv->bgc.lock, flags);
++ spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
+
+ return 0;
+ }
+@@ -177,11 +170,11 @@ static void grgpio_irq_mask(struct irq_d
+ int offset = d->hwirq;
+ unsigned long flags;
+
+- spin_lock_irqsave(&priv->bgc.lock, flags);
++ spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
+
+ grgpio_set_imask(priv, offset, 0);
+
+- spin_unlock_irqrestore(&priv->bgc.lock, flags);
++ spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
+ }
+
+ static void grgpio_irq_unmask(struct irq_data *d)
+@@ -190,11 +183,11 @@ static void grgpio_irq_unmask(struct irq
+ int offset = d->hwirq;
+ unsigned long flags;
+
+- spin_lock_irqsave(&priv->bgc.lock, flags);
++ spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
+
+ grgpio_set_imask(priv, offset, 1);
+
+- spin_unlock_irqrestore(&priv->bgc.lock, flags);
++ spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
+ }
+
+ static struct irq_chip grgpio_irq_chip = {
+@@ -207,12 +200,12 @@ static struct irq_chip grgpio_irq_chip =
+ static irqreturn_t grgpio_irq_handler(int irq, void *dev)
+ {
+ struct grgpio_priv *priv = dev;
+- int ngpio = priv->bgc.gc.ngpio;
++ int ngpio = priv->gc.ngpio;
+ unsigned long flags;
+ int i;
+ int match = 0;
+
+- spin_lock_irqsave(&priv->bgc.lock, flags);
++ spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
+
+ /*
+ * For each gpio line, call its interrupt handler if it its underlying
+@@ -228,7 +221,7 @@ static irqreturn_t grgpio_irq_handler(in
+ }
+ }
+
+- spin_unlock_irqrestore(&priv->bgc.lock, flags);
++ spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
+
+ if (!match)
+ dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
+@@ -260,7 +253,7 @@ static int grgpio_irq_map(struct irq_dom
+ dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
+ irq, offset);
+
+- spin_lock_irqsave(&priv->bgc.lock, flags);
++ spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
+
+ /* Request underlying irq if not already requested */
+ lirq->irq = irq;
+@@ -273,14 +266,14 @@ static int grgpio_irq_map(struct irq_dom
+ "Could not request underlying irq %d\n",
+ uirq->uirq);
+
+- spin_unlock_irqrestore(&priv->bgc.lock, flags);
++ spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
+
+ return ret;
+ }
+ }
+ uirq->refcnt++;
+
+- spin_unlock_irqrestore(&priv->bgc.lock, flags);
++ spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
+
+ /* Setup irq */
+ irq_set_chip_data(irq, priv);
+@@ -298,13 +291,13 @@ static void grgpio_irq_unmap(struct irq_
+ struct grgpio_lirq *lirq;
+ struct grgpio_uirq *uirq;
+ unsigned long flags;
+- int ngpio = priv->bgc.gc.ngpio;
++ int ngpio = priv->gc.ngpio;
+ int i;
+
+ irq_set_chip_and_handler(irq, NULL, NULL);
+ irq_set_chip_data(irq, NULL);
+
+- spin_lock_irqsave(&priv->bgc.lock, flags);
++ spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
+
+ /* Free underlying irq if last user unmapped */
+ index = -1;
+@@ -326,7 +319,7 @@ static void grgpio_irq_unmap(struct irq_
+ free_irq(uirq->uirq, priv);
+ }
+
+- spin_unlock_irqrestore(&priv->bgc.lock, flags);
++ spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
+ }
+
+ static const struct irq_domain_ops grgpio_irq_domain_ops = {
+@@ -341,7 +334,6 @@ static int grgpio_probe(struct platform_
+ struct device_node *np = ofdev->dev.of_node;
+ void __iomem *regs;
+ struct gpio_chip *gc;
+- struct bgpio_chip *bgc;
+ struct grgpio_priv *priv;
+ struct resource *res;
+ int err;
+@@ -359,8 +351,8 @@ static int grgpio_probe(struct platform_
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+- bgc = &priv->bgc;
+- err = bgpio_init(bgc, &ofdev->dev, 4, regs + GRGPIO_DATA,
++ gc = &priv->gc;
++ err = bgpio_init(gc, &ofdev->dev, 4, regs + GRGPIO_DATA,
+ regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
+ BGPIOF_BIG_ENDIAN_BYTE_ORDER);
+ if (err) {
+@@ -369,10 +361,9 @@ static int grgpio_probe(struct platform_
+ }
+
+ priv->regs = regs;
+- priv->imask = bgc->read_reg(regs + GRGPIO_IMASK);
++ priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
+ priv->dev = &ofdev->dev;
+
+- gc = &bgc->gc;
+ gc->of_node = np;
+ gc->owner = THIS_MODULE;
+ gc->to_irq = grgpio_to_irq;
+@@ -435,7 +426,7 @@ static int grgpio_probe(struct platform_
+
+ platform_set_drvdata(ofdev, priv);
+
+- err = gpiochip_add(gc);
++ err = gpiochip_add_data(gc, priv);
+ if (err) {
+ dev_err(&ofdev->dev, "Could not add gpiochip\n");
+ if (priv->domain)
+@@ -456,7 +447,7 @@ static int grgpio_remove(struct platform
+ int i;
+ int ret = 0;
+
+- spin_lock_irqsave(&priv->bgc.lock, flags);
++ spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
+
+ if (priv->domain) {
+ for (i = 0; i < GRGPIO_MAX_NGPIO; i++) {
+@@ -467,13 +458,13 @@ static int grgpio_remove(struct platform
+ }
+ }
+
+- gpiochip_remove(&priv->bgc.gc);
++ gpiochip_remove(&priv->gc);
+
+ if (priv->domain)
+ irq_domain_remove(priv->domain);
+
+ out:
+- spin_unlock_irqrestore(&priv->bgc.lock, flags);
++ spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
+
+ return ret;
+ }
+--- a/drivers/gpio/gpio-moxart.c
++++ b/drivers/gpio/gpio-moxart.c
+@@ -14,7 +14,6 @@
+ #include <linux/init.h>
+ #include <linux/irq.h>
+ #include <linux/io.h>
+-#include <linux/gpio.h>
+ #include <linux/platform_device.h>
+ #include <linux/module.h>
+ #include <linux/of_address.h>
+@@ -23,7 +22,7 @@
+ #include <linux/delay.h>
+ #include <linux/timer.h>
+ #include <linux/bitops.h>
+-#include <linux/basic_mmio_gpio.h>
++#include <linux/gpio/driver.h>
+
+ #define GPIO_DATA_OUT 0x00
+ #define GPIO_DATA_IN 0x04
+@@ -33,12 +32,12 @@ static int moxart_gpio_probe(struct plat
+ {
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+- struct bgpio_chip *bgc;
++ struct gpio_chip *gc;
+ void __iomem *base;
+ int ret;
+
+- bgc = devm_kzalloc(dev, sizeof(*bgc), GFP_KERNEL);
+- if (!bgc)
++ gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
++ if (!gc)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+@@ -46,7 +45,7 @@ static int moxart_gpio_probe(struct plat
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+- ret = bgpio_init(bgc, dev, 4, base + GPIO_DATA_IN,
++ ret = bgpio_init(gc, dev, 4, base + GPIO_DATA_IN,
+ base + GPIO_DATA_OUT, NULL,
+ base + GPIO_PIN_DIRECTION, NULL,
+ BGPIOF_READ_OUTPUT_REG_SET);
+@@ -55,16 +54,16 @@ static int moxart_gpio_probe(struct plat
+ return ret;
+ }
+
+- bgc->gc.label = "moxart-gpio";
+- bgc->gc.request = gpiochip_generic_request;
+- bgc->gc.free = gpiochip_generic_free;
+- bgc->data = bgc->read_reg(bgc->reg_set);
+- bgc->gc.base = 0;
+- bgc->gc.ngpio = 32;
+- bgc->gc.dev = dev;
+- bgc->gc.owner = THIS_MODULE;
++ gc->label = "moxart-gpio";
++ gc->request = gpiochip_generic_request;
++ gc->free = gpiochip_generic_free;
++ gc->bgpio_data = bgc->read_reg(bgc->reg_set);
++ gc->base = 0;
++ gc->ngpio = 32;
++ gc->dev = dev;
++ gc->owner = THIS_MODULE;
+
+- ret = gpiochip_add(&bgc->gc);
++ ret = gpiochip_add_data(gc, NULL);
+ if (ret) {
+ dev_err(dev, "%s: gpiochip_add failed\n",
+ dev->of_node->full_name);
+--- a/drivers/gpio/gpio-mxc.c
++++ b/drivers/gpio/gpio-mxc.c
+@@ -26,10 +26,11 @@
+ #include <linux/irq.h>
+ #include <linux/irqdomain.h>
+ #include <linux/irqchip/chained_irq.h>
+-#include <linux/gpio.h>
+ #include <linux/platform_device.h>
+ #include <linux/slab.h>
+-#include <linux/basic_mmio_gpio.h>
++#include <linux/gpio/driver.h>
++/* FIXME: for gpio_get_value() replace this with direct register read */
++#include <linux/gpio.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/module.h>
+@@ -64,7 +65,7 @@ struct mxc_gpio_port {
+ int irq;
+ int irq_high;
+ struct irq_domain *domain;
+- struct bgpio_chip bgc;
++ struct gpio_chip gc;
+ u32 both_edges;
+ };
+
+@@ -172,7 +173,7 @@ static int gpio_set_irq_type(struct irq_
+ struct mxc_gpio_port *port = gc->private;
+ u32 bit, val;
+ u32 gpio_idx = d->hwirq;
+- u32 gpio = port->bgc.gc.base + gpio_idx;
++ u32 gpio = port->gc.base + gpio_idx;
+ int edge;
+ void __iomem *reg = port->base;
+
+@@ -398,9 +399,7 @@ static void mxc_gpio_get_hw(struct platf
+
+ static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+- struct mxc_gpio_port *port =
+- container_of(bgc, struct mxc_gpio_port, bgc);
++ struct mxc_gpio_port *port = gpiochip_get_data(gc);
+
+ return irq_find_mapping(port->domain, offset);
+ }
+@@ -451,7 +450,7 @@ static int mxc_gpio_probe(struct platfor
+ port);
+ }
+
+- err = bgpio_init(&port->bgc, &pdev->dev, 4,
++ err = bgpio_init(&port->gc, &pdev->dev, 4,
+ port->base + GPIO_PSR,
+ port->base + GPIO_DR, NULL,
+ port->base + GPIO_GDIR, NULL,
+@@ -459,13 +458,13 @@ static int mxc_gpio_probe(struct platfor
+ if (err)
+ goto out_bgio;
+
+- port->bgc.gc.to_irq = mxc_gpio_to_irq;
+- port->bgc.gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
++ port->gc.to_irq = mxc_gpio_to_irq;
++ port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
+ pdev->id * 32;
+
+- err = gpiochip_add(&port->bgc.gc);
++ err = gpiochip_add_data(&port->gc, port);
+ if (err)
+- goto out_bgpio_remove;
++ goto out_bgio;
+
+ irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
+ if (irq_base < 0) {
+@@ -494,9 +493,7 @@ out_irqdomain_remove:
+ out_irqdesc_free:
+ irq_free_descs(irq_base, 32);
+ out_gpiochip_remove:
+- gpiochip_remove(&port->bgc.gc);
+-out_bgpio_remove:
+- bgpio_remove(&port->bgc);
++ gpiochip_remove(&port->gc);
+ out_bgio:
+ dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
+ return err;
+--- a/drivers/gpio/gpio-mxs.c
++++ b/drivers/gpio/gpio-mxs.c
+@@ -26,13 +26,14 @@
+ #include <linux/io.h>
+ #include <linux/irq.h>
+ #include <linux/irqdomain.h>
+-#include <linux/gpio.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/slab.h>
+-#include <linux/basic_mmio_gpio.h>
++#include <linux/gpio/driver.h>
++/* FIXME: for gpio_get_value(), replace this by direct register read */
++#include <linux/gpio.h>
+ #include <linux/module.h>
+
+ #define MXS_SET 0x4
+@@ -64,7 +65,7 @@ struct mxs_gpio_port {
+ int id;
+ int irq;
+ struct irq_domain *domain;
+- struct bgpio_chip bgc;
++ struct gpio_chip gc;
+ enum mxs_gpio_id devid;
+ u32 both_edges;
+ };
+@@ -93,7 +94,7 @@ static int mxs_gpio_set_irq_type(struct
+ port->both_edges &= ~pin_mask;
+ switch (type) {
+ case IRQ_TYPE_EDGE_BOTH:
+- val = gpio_get_value(port->bgc.gc.base + d->hwirq);
++ val = gpio_get_value(port->gc.base + d->hwirq);
+ if (val)
+ edge = GPIO_INT_FALL_EDGE;
+ else
+@@ -225,18 +226,14 @@ static int __init mxs_gpio_init_gc(struc
+
+ static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+- struct mxs_gpio_port *port =
+- container_of(bgc, struct mxs_gpio_port, bgc);
++ struct mxs_gpio_port *port = gpiochip_get_data(gc);
+
+ return irq_find_mapping(port->domain, offset);
+ }
+
+ static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
+ {
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+- struct mxs_gpio_port *port =
+- container_of(bgc, struct mxs_gpio_port, bgc);
++ struct mxs_gpio_port *port = gpiochip_get_data(gc);
+ u32 mask = 1 << offset;
+ u32 dir;
+
+@@ -330,26 +327,24 @@ static int mxs_gpio_probe(struct platfor
+ irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
+ port);
+
+- err = bgpio_init(&port->bgc, &pdev->dev, 4,
++ err = bgpio_init(&port->gc, &pdev->dev, 4,
+ port->base + PINCTRL_DIN(port),
+ port->base + PINCTRL_DOUT(port) + MXS_SET,
+ port->base + PINCTRL_DOUT(port) + MXS_CLR,
+ port->base + PINCTRL_DOE(port), NULL, 0);
+ if (err)
+- goto out_irqdesc_free;
++ goto out_irqdomain_remove;
+
+- port->bgc.gc.to_irq = mxs_gpio_to_irq;
+- port->bgc.gc.get_direction = mxs_gpio_get_direction;
+- port->bgc.gc.base = port->id * 32;
++ port->gc.to_irq = mxs_gpio_to_irq;
++ port->gc.get_direction = mxs_gpio_get_direction;
++ port->gc.base = port->id * 32;
+
+- err = gpiochip_add(&port->bgc.gc);
++ err = gpiochip_add_data(&port->gc, port);
+ if (err)
+- goto out_bgpio_remove;
++ goto out_irqdomain_remove;
+
+ return 0;
+
+-out_bgpio_remove:
+- bgpio_remove(&port->bgc);
+ out_irqdomain_remove:
+ irq_domain_remove(port->domain);
+ out_irqdesc_free:
+--- a/drivers/gpio/gpio-sodaville.c
++++ b/drivers/gpio/gpio-sodaville.c
+@@ -10,7 +10,6 @@
+ */
+
+ #include <linux/errno.h>
+-#include <linux/gpio.h>
+ #include <linux/init.h>
+ #include <linux/io.h>
+ #include <linux/irq.h>
+@@ -20,7 +19,7 @@
+ #include <linux/pci.h>
+ #include <linux/platform_device.h>
+ #include <linux/of_irq.h>
+-#include <linux/basic_mmio_gpio.h>
++#include <linux/gpio/driver.h>
+
+ #define DRV_NAME "sdv_gpio"
+ #define SDV_NUM_PUB_GPIOS 12
+@@ -43,7 +42,7 @@ struct sdv_gpio_chip_data {
+ void __iomem *gpio_pub_base;
+ struct irq_domain *id;
+ struct irq_chip_generic *gc;
+- struct bgpio_chip bgpio;
++ struct gpio_chip chip;
+ };
+
+ static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
+@@ -226,14 +225,14 @@ static int sdv_gpio_probe(struct pci_dev
+ writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
+ }
+
+- ret = bgpio_init(&sd->bgpio, &pdev->dev, 4,
++ ret = bgpio_init(&sd->chip, &pdev->dev, 4,
+ sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
+ NULL, sd->gpio_pub_base + GPOER, NULL, 0);
+ if (ret)
+ goto unmap;
+- sd->bgpio.gc.ngpio = SDV_NUM_PUB_GPIOS;
++ sd->chip.ngpio = SDV_NUM_PUB_GPIOS;
+
+- ret = gpiochip_add(&sd->bgpio.gc);
++ ret = gpiochip_add_data(&sd->chip, sd);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "gpiochip_add() failed.\n");
+ goto unmap;
+@@ -265,7 +264,7 @@ static void sdv_gpio_remove(struct pci_d
+ free_irq(pdev->irq, sd);
+ irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
+
+- gpiochip_remove(&sd->bgpio.gc);
++ gpiochip_remove(&sd->chip);
+ pci_release_region(pdev, GPIO_BAR);
+ iounmap(sd->gpio_pub_base);
+ pci_disable_device(pdev);
+--- a/drivers/gpio/gpio-xgene-sb.c
++++ b/drivers/gpio/gpio-xgene-sb.c
+@@ -23,10 +23,8 @@
+ #include <linux/io.h>
+ #include <linux/platform_device.h>
+ #include <linux/of_gpio.h>
+-#include <linux/gpio.h>
+ #include <linux/gpio/driver.h>
+ #include <linux/acpi.h>
+-#include <linux/basic_mmio_gpio.h>
+
+ #include "gpiolib.h"
+
+@@ -43,38 +41,31 @@
+
+ /**
+ * struct xgene_gpio_sb - GPIO-Standby private data structure.
+- * @bgc: memory-mapped GPIO controllers.
++ * @gc: memory-mapped GPIO controllers.
+ * @irq: Mapping GPIO pins and interrupt number
+ * nirq: Number of GPIO pins that supports interrupt
+ */
+ struct xgene_gpio_sb {
+- struct bgpio_chip bgc;
++ struct gpio_chip gc;
+ u32 *irq;
+ u32 nirq;
+ };
+
+-static inline struct xgene_gpio_sb *to_xgene_gpio_sb(struct gpio_chip *gc)
+-{
+- struct bgpio_chip *bgc = to_bgpio_chip(gc);
+-
+- return container_of(bgc, struct xgene_gpio_sb, bgc);
+-}
+-
+-static void xgene_gpio_set_bit(struct bgpio_chip *bgc, void __iomem *reg, u32 gpio, int val)
++static void xgene_gpio_set_bit(struct gpio_chip *gc, void __iomem *reg, u32 gpio, int val)
+ {
+ u32 data;
+
+- data = bgc->read_reg(reg);
++ data = gc->read_reg(reg);
+ if (val)
+ data |= GPIO_MASK(gpio);
+ else
+ data &= ~GPIO_MASK(gpio);
+- bgc->write_reg(reg, data);
++ gc->write_reg(reg, data);
+ }
+
+ static int apm_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
+ {
+- struct xgene_gpio_sb *priv = to_xgene_gpio_sb(gc);
++ struct xgene_gpio_sb *priv = gpiochip_get_data(gc);
+
+ if (priv->irq[gpio])
+ return priv->irq[gpio];
+@@ -99,15 +90,15 @@ static int xgene_gpio_sb_probe(struct pl
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+- ret = bgpio_init(&priv->bgc, &pdev->dev, 4,
++ ret = bgpio_init(&priv->gc, &pdev->dev, 4,
+ regs + MPA_GPIO_IN_ADDR,
+ regs + MPA_GPIO_OUT_ADDR, NULL,
+ regs + MPA_GPIO_OE_ADDR, NULL, 0);
+ if (ret)
+ return ret;
+
+- priv->bgc.gc.to_irq = apm_gpio_sb_to_irq;
+- priv->bgc.gc.ngpio = XGENE_MAX_GPIO_DS;
++ priv->gc.to_irq = apm_gpio_sb_to_irq;
++ priv->gc.ngpio = XGENE_MAX_GPIO_DS;
+
+ priv->nirq = XGENE_MAX_GPIO_DS_IRQ;
+
+@@ -118,14 +109,14 @@ static int xgene_gpio_sb_probe(struct pl
+
+ for (i = 0; i < priv->nirq; i++) {
+ priv->irq[default_lines[i]] = platform_get_irq(pdev, i);
+- xgene_gpio_set_bit(&priv->bgc, regs + MPA_GPIO_SEL_LO,
++ xgene_gpio_set_bit(&priv->gc, regs + MPA_GPIO_SEL_LO,
+ default_lines[i] * 2, 1);
+- xgene_gpio_set_bit(&priv->bgc, regs + MPA_GPIO_INT_LVL, i, 1);
++ xgene_gpio_set_bit(&priv->gc, regs + MPA_GPIO_INT_LVL, i, 1);
+ }
+
+ platform_set_drvdata(pdev, priv);
+
+- ret = gpiochip_add(&priv->bgc.gc);
++ ret = gpiochip_add_data(&priv->gc, priv);
+ if (ret)
+ dev_err(&pdev->dev, "failed to register X-Gene GPIO Standby driver\n");
+ else
+@@ -133,7 +124,7 @@ static int xgene_gpio_sb_probe(struct pl
+
+ if (priv->nirq > 0) {
+ /* Register interrupt handlers for gpio signaled acpi events */
+- acpi_gpiochip_request_interrupts(&priv->bgc.gc);
++ acpi_gpiochip_request_interrupts(&priv->gc);
+ }
+
+ return ret;
+@@ -144,10 +135,11 @@ static int xgene_gpio_sb_remove(struct p
+ struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);
+
+ if (priv->nirq > 0) {
+- acpi_gpiochip_free_interrupts(&priv->bgc.gc);
++ acpi_gpiochip_free_interrupts(&priv->gc);
+ }
+
+- return bgpio_remove(&priv->bgc);
++ gpiochip_remove(&priv->gc);
++ return 0;
+ }
+
+ static const struct of_device_id xgene_gpio_sb_of_match[] = {
+--- a/drivers/mfd/vexpress-sysreg.c
++++ b/drivers/mfd/vexpress-sysreg.c
+@@ -11,7 +11,7 @@
+ * Copyright (C) 2012 ARM Limited
+ */
+
+-#include <linux/basic_mmio_gpio.h>
++#include <linux/gpio/driver.h>
+ #include <linux/err.h>
+ #include <linux/io.h>
+ #include <linux/mfd/core.h>
+@@ -164,7 +164,7 @@ static int vexpress_sysreg_probe(struct
+ {
+ struct resource *mem;
+ void __iomem *base;
+- struct bgpio_chip *mmc_gpio_chip;
++ struct gpio_chip *mmc_gpio_chip;
+ int master;
+ u32 dt_hbi;
+
+@@ -201,8 +201,8 @@ static int vexpress_sysreg_probe(struct
+ return -ENOMEM;
+ bgpio_init(mmc_gpio_chip, &pdev->dev, 0x4, base + SYS_MCI,
+ NULL, NULL, NULL, NULL, 0);
+- mmc_gpio_chip->gc.ngpio = 2;
+- gpiochip_add(&mmc_gpio_chip->gc);
++ mmc_gpio_chip->ngpio = 2;
++ gpiochip_add(mmc_gpio_chip);
+
+ return mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO,
+ vexpress_sysreg_cells,
+--- a/include/linux/basic_mmio_gpio.h
++++ /dev/null
+@@ -1,80 +0,0 @@
+-/*
+- * Basic memory-mapped GPIO controllers.
+- *
+- * Copyright 2008 MontaVista Software, Inc.
+- * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- */
+-
+-#ifndef __BASIC_MMIO_GPIO_H
+-#define __BASIC_MMIO_GPIO_H
+-
+-#include <linux/gpio.h>
+-#include <linux/types.h>
+-#include <linux/compiler.h>
+-#include <linux/spinlock_types.h>
+-
+-struct bgpio_pdata {
+- const char *label;
+- int base;
+- int ngpio;
+-};
+-
+-struct device;
+-
+-struct bgpio_chip {
+- struct gpio_chip gc;
+-
+- unsigned long (*read_reg)(void __iomem *reg);
+- void (*write_reg)(void __iomem *reg, unsigned long data);
+-
+- void __iomem *reg_dat;
+- void __iomem *reg_set;
+- void __iomem *reg_clr;
+- void __iomem *reg_dir;
+-
+- /* Number of bits (GPIOs): <register width> * 8. */
+- int bits;
+-
+- /*
+- * Some GPIO controllers work with the big-endian bits notation,
+- * e.g. in a 8-bits register, GPIO7 is the least significant bit.
+- */
+- unsigned long (*pin2mask)(struct bgpio_chip *bgc, unsigned int pin);
+-
+- /*
+- * Used to lock bgpio_chip->data. Also, this is needed to keep
+- * shadowed and real data registers writes together.
+- */
+- spinlock_t lock;
+-
+- /* Shadowed data register to clear/set bits safely. */
+- unsigned long data;
+-
+- /* Shadowed direction registers to clear/set direction safely. */
+- unsigned long dir;
+-};
+-
+-static inline struct bgpio_chip *to_bgpio_chip(struct gpio_chip *gc)
+-{
+- return container_of(gc, struct bgpio_chip, gc);
+-}
+-
+-int bgpio_remove(struct bgpio_chip *bgc);
+-int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
+- unsigned long sz, void __iomem *dat, void __iomem *set,
+- void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
+- unsigned long flags);
+-
+-#define BGPIOF_BIG_ENDIAN BIT(0)
+-#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
+-#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
+-#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
+-#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
+-#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
+-
+-#endif /* __BASIC_MMIO_GPIO_H */
+--- a/include/linux/gpio/driver.h
++++ b/include/linux/gpio/driver.h
+@@ -8,6 +8,7 @@
+ #include <linux/irqdomain.h>
+ #include <linux/lockdep.h>
+ #include <linux/pinctrl/pinctrl.h>
++#include <linux/kconfig.h>
+
+ struct device;
+ struct gpio_desc;
+@@ -66,6 +67,23 @@ struct seq_file;
+ * registers.
+ * @irq_not_threaded: flag must be set if @can_sleep is set but the
+ * IRQs don't need to be threaded
++ * @read_reg: reader function for generic GPIO
++ * @write_reg: writer function for generic GPIO
++ * @pin2mask: some generic GPIO controllers work with the big-endian bits
++ * notation, e.g. in a 8-bits register, GPIO7 is the least significant
++ * bit. This callback assigns the right bit mask.
++ * @reg_dat: data (in) register for generic GPIO
++ * @reg_set: output set register (out=high) for generic GPIO
++ * @reg_clk: output clear register (out=low) for generic GPIO
++ * @reg_dir: direction setting register for generic GPIO
++ * @bgpio_bits: number of register bits used for a generic GPIO i.e.
++ * <register width> * 8
++ * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
++ * shadowed and real data registers writes together.
++ * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
++ * safely.
++ * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
++ * direction safely.
+ * @irqchip: GPIO IRQ chip impl, provided by GPIO driver
+ * @irqdomain: Interrupt translation domain; responsible for mapping
+ * between GPIO hwirq number and linux irq number
+@@ -129,6 +147,20 @@ struct gpio_chip {
+ bool can_sleep;
+ bool irq_not_threaded;
+
++#if IS_ENABLED(CONFIG_GPIO_GENERIC)
++ unsigned long (*read_reg)(void __iomem *reg);
++ void (*write_reg)(void __iomem *reg, unsigned long data);
++ unsigned long (*pin2mask)(struct gpio_chip *gc, unsigned int pin);
++ void __iomem *reg_dat;
++ void __iomem *reg_set;
++ void __iomem *reg_clr;
++ void __iomem *reg_dir;
++ int bgpio_bits;
++ spinlock_t bgpio_lock;
++ unsigned long bgpio_data;
++ unsigned long bgpio_dir;
++#endif
++
+ #ifdef CONFIG_GPIOLIB_IRQCHIP
+ /*
+ * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
+@@ -189,6 +221,28 @@ static inline void *gpiochip_get_data(st
+
+ struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
+
++#if IS_ENABLED(CONFIG_GPIO_GENERIC)
++
++struct bgpio_pdata {
++ const char *label;
++ int base;
++ int ngpio;
++};
++
++int bgpio_init(struct gpio_chip *gc, struct device *dev,
++ unsigned long sz, void __iomem *dat, void __iomem *set,
++ void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
++ unsigned long flags);
++
++#define BGPIOF_BIG_ENDIAN BIT(0)
++#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
++#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
++#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
++#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
++#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
++
++#endif
++
+ #ifdef CONFIG_GPIOLIB_IRQCHIP
+
+ void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
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