ipq806x: 5.15: backport qcom clk fixes for krait and hfpll

Backport some qcom clock fixes for krait and hfpll driver.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

diff --git a/target/linux/ipq806x/patches-5.15/117-v6.0-01-clk-qcom-clk-hfpll-use-poll_timeout-macro.patch b/target/linux/ipq806x/patches-5.15/117-v6.0-01-clk-qcom-clk-hfpll-use-poll_timeout-macro.patch
new file mode 100644 (file)
index 0000000..3008fff
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.15/117-v6.0-01-clk-qcom-clk-hfpll-use-poll_timeout-macro.patch
@@ -0,0 +1,41 @@
+From fcfbfe373d41b4728ffec075f8f91b6572a88c27 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Sat, 30 Apr 2022 07:44:56 +0200
+Subject: [PATCH 1/3] clk: qcom: clk-hfpll: use poll_timeout macro
+
+Use regmap_read_poll_timeout macro instead of do-while structure to tidy
+things up. Also set a timeout to prevent any sort of system stall.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/20220430054458.31321-2-ansuelsmth@gmail.com
+---
+ drivers/clk/qcom/clk-hfpll.c | 15 +++++++++------
+ 1 file changed, 9 insertions(+), 6 deletions(-)
+
+--- a/drivers/clk/qcom/clk-hfpll.c
++++ b/drivers/clk/qcom/clk-hfpll.c
+@@ -72,13 +72,16 @@ static void __clk_hfpll_enable(struct cl
+       regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
+ 
+       /* Wait for PLL to lock. */
+-      if (hd->status_reg) {
+-              do {
+-                      regmap_read(regmap, hd->status_reg, &val);
+-              } while (!(val & BIT(hd->lock_bit)));
+-      } else {
++      if (hd->status_reg)
++              /*
++               * Busy wait. Should never timeout, we add a timeout to
++               * prevent any sort of stall.
++               */
++              regmap_read_poll_timeout(regmap, hd->status_reg, val,
++                                       !(val & BIT(hd->lock_bit)), 0,
++                                       100 * USEC_PER_MSEC);
++      else
+               udelay(60);
+-      }
+ 
+       /* Enable PLL output. */
+       regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL);

diff --git a/target/linux/ipq806x/patches-5.15/117-v6.0-03-clk-qcom-clk-krait-add-apq-ipq8064-errata-workaround.patch b/target/linux/ipq806x/patches-5.15/117-v6.0-03-clk-qcom-clk-krait-add-apq-ipq8064-errata-workaround.patch
new file mode 100644 (file)
index 0000000..4012e16
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.15/117-v6.0-03-clk-qcom-clk-krait-add-apq-ipq8064-errata-workaround.patch
@@ -0,0 +1,86 @@
+From 898d0d6483a9360f1968e0a900465c1fa152a4a9 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Sat, 30 Apr 2022 07:44:58 +0200
+Subject: [PATCH 3/3] clk: qcom: clk-krait: add apq/ipq8064 errata workaround
+
+Add apq/ipq8064 errata workaround where the sec_src clock gating needs to
+be disabled during switching. krait-cc compatible is not enough to
+handle this and limit this workaround to apq/ipq8064. We check machine
+compatible to handle this.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/20220430054458.31321-4-ansuelsmth@gmail.com
+---
+ drivers/clk/qcom/clk-krait.c | 16 ++++++++++++++++
+ drivers/clk/qcom/clk-krait.h |  1 +
+ drivers/clk/qcom/krait-cc.c  |  8 ++++++++
+ 3 files changed, 25 insertions(+)
+
+--- a/drivers/clk/qcom/clk-krait.c
++++ b/drivers/clk/qcom/clk-krait.c
+@@ -18,13 +18,23 @@
+ static DEFINE_SPINLOCK(krait_clock_reg_lock);
+ 
+ #define LPL_SHIFT     8
++#define SECCLKAGD     BIT(4)
++
+ static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
+ {
+       unsigned long flags;
+       u32 regval;
+ 
+       spin_lock_irqsave(&krait_clock_reg_lock, flags);
++
+       regval = krait_get_l2_indirect_reg(mux->offset);
++
++      /* apq/ipq8064 Errata: disable sec_src clock gating during switch. */
++      if (mux->disable_sec_src_gating) {
++              regval |= SECCLKAGD;
++              krait_set_l2_indirect_reg(mux->offset, regval);
++      }
++
+       regval &= ~(mux->mask << mux->shift);
+       regval |= (sel & mux->mask) << mux->shift;
+       if (mux->lpl) {
+@@ -33,6 +43,12 @@ static void __krait_mux_set_sel(struct k
+       }
+       krait_set_l2_indirect_reg(mux->offset, regval);
+ 
++      /* apq/ipq8064 Errata: re-enabled sec_src clock gating. */
++      if (mux->disable_sec_src_gating) {
++              regval &= ~SECCLKAGD;
++              krait_set_l2_indirect_reg(mux->offset, regval);
++      }
++
+       /* Wait for switch to complete. */
+       mb();
+       udelay(1);
+--- a/drivers/clk/qcom/clk-krait.h
++++ b/drivers/clk/qcom/clk-krait.h
+@@ -15,6 +15,7 @@ struct krait_mux_clk {
+       u8              safe_sel;
+       u8              old_index;
+       bool            reparent;
++      bool            disable_sec_src_gating;
+ 
+       struct clk_hw   hw;
+       struct notifier_block   clk_nb;
+--- a/drivers/clk/qcom/krait-cc.c
++++ b/drivers/clk/qcom/krait-cc.c
+@@ -139,6 +139,14 @@ krait_add_sec_mux(struct device *dev, in
+       mux->hw.init = &init;
+       mux->safe_sel = 0;
+ 
++      /* Checking for qcom,krait-cc-v1 or qcom,krait-cc-v2 is not
++       * enough to limit this to apq/ipq8064. Directly check machine
++       * compatible to correctly handle this errata.
++       */
++      if (of_machine_is_compatible("qcom,ipq8064") ||
++          of_machine_is_compatible("qcom,apq8064"))
++              mux->disable_sec_src_gating = true;
++
+       init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
+       if (!init.name)
+               return -ENOMEM;