4049d131bbb70702917a01f8e33b3da99edf8509
[openwrt/staging/blogic.git] / target / linux / ramips / patches-4.4 / 100-mt7621-core-detect-hack.patch
1 There is a variant of MT7621 which contains only one CPU core instead of 2.
2 This is not reflected in the config register, so the kernel detects more
3 physical cores, which leads to a hang on SMP bringup.
4 Add a hack to detect missing cores.
5
6 Signed-off-by: Felix Fietkau <nbd@nbd.name>
7
8 --- a/arch/mips/kernel/smp-cps.c
9 +++ b/arch/mips/kernel/smp-cps.c
10 @@ -44,6 +44,11 @@ static unsigned core_vpe_count(unsigned
11 return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
12 }
13
14 +bool __weak plat_cpu_core_present(int core)
15 +{
16 + return true;
17 +}
18 +
19 static void __init cps_smp_setup(void)
20 {
21 unsigned int ncores, nvpes, core_vpes;
22 @@ -53,6 +58,8 @@ static void __init cps_smp_setup(void)
23 ncores = mips_cm_numcores();
24 pr_info("VPE topology ");
25 for (c = nvpes = 0; c < ncores; c++) {
26 + if (!plat_cpu_core_present(c))
27 + continue;
28 core_vpes = core_vpe_count(c);
29 pr_cont("%c%u", c ? ',' : '{', core_vpes);
30
31 --- a/arch/mips/ralink/mt7621.c
32 +++ b/arch/mips/ralink/mt7621.c
33 @@ -20,6 +20,7 @@
34 #include <asm/mips-cpc.h>
35 #include <asm/mach-ralink/ralink_regs.h>
36 #include <asm/mach-ralink/mt7621.h>
37 +#include <asm/mips-boards/launch.h>
38
39 #include <pinmux.h>
40
41 @@ -163,6 +164,20 @@ void __init ralink_of_remap(void)
42 panic("Failed to remap core resources");
43 }
44
45 +bool plat_cpu_core_present(int core)
46 +{
47 + struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
48 +
49 + if (!core)
50 + return true;
51 + launch += core * 2; /* 2 VPEs per core */
52 + if (!(launch->flags & LAUNCH_FREADY))
53 + return false;
54 + if (launch->flags & (LAUNCH_FGO | LAUNCH_FGONE))
55 + return false;
56 + return true;
57 +}
58 +
59 void prom_soc_init(struct ralink_soc_info *soc_info)
60 {
61 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);