target/linux/apm821xx/patches-5.10/300-fix-atheros-nics-on-apm82181.patch

   1 --- a/arch/powerpc/platforms/4xx/pci.c
   2 +++ b/arch/powerpc/platforms/4xx/pci.c
   3 @@ -1060,15 +1060,24 @@ static int __init apm821xx_pciex_init_po
   4         u32 val;
   5
   6         /*
   7 -        * Do a software reset on PCIe ports.
   8 -        * This code is to fix the issue that pci drivers doesn't re-assign
   9 -        * bus number for PCIE devices after Uboot
  10 -        * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
  11 -        * PT quad port, SAS LSI 1064E)
  12 +        * Only reset the PHY when no link is currently established.
  13 +        * This is for the Atheros PCIe board which has problems to establish
  14 +        * the link (again) after this PHY reset. All other currently tested
  15 +        * PCIe boards don't show this problem.
  16          */
  17 -
  18 -       mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
  19 -       mdelay(10);
  20 +       val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
  21 +       if (!(val & 0x00001000)) {
  22 +               /*
  23 +                * Do a software reset on PCIe ports.
  24 +                * This code is to fix the issue that pci drivers doesn't re-assign
  25 +                * bus number for PCIE devices after Uboot
  26 +                * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
  27 +                * PT quad port, SAS LSI 1064E)
  28 +                */
  29 +
  30 +               mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
  31 +               mdelay(10);
  32 +       }
  33
  34         if (port->endpoint)
  35                 val = PTYPE_LEGACY_ENDPOINT << 20;
  36 @@ -1085,9 +1094,12 @@ static int __init apm821xx_pciex_init_po
  37         mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
  38         mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
  39
  40 -       mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
  41 -       mdelay(50);
  42 -       mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
  43 +       val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
  44 +       if (!(val & 0x00001000)) {
  45 +               mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
  46 +               mdelay(50);
  47 +               mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
  48 +       }
  49
  50         mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
  51                 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |