Add forgotten part of vlynq irq setup
[openwrt/staging/chunkeey.git] / target / linux / ar7-2.6 / files / arch / mips / ar7 / platform.c
1 /*
2 * $Id$
3 *
4 * Copyright (C) 2006, 2007 OpenWrt.org
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21 #include <linux/autoconf.h>
22 #include <linux/init.h>
23 #include <linux/types.h>
24 #include <linux/module.h>
25 #include <linux/delay.h>
26 #include <linux/platform_device.h>
27 #include <linux/mtd/physmap.h>
28 #include <linux/serial.h>
29 #include <linux/serial_8250.h>
30 #include <linux/ioport.h>
31 #include <asm/addrspace.h>
32 #include <asm/io.h>
33 #include <asm/ar7/ar7.h>
34 #include <asm/ar7/gpio.h>
35 #include <asm/ar7/vlynq.h>
36
37 struct plat_vlynq_data {
38 struct plat_vlynq_ops ops;
39 int gpio_bit;
40 int reset_bit;
41 };
42
43
44 static int vlynq_on(struct vlynq_device *dev)
45 {
46 int result;
47 struct plat_vlynq_data *pdata = dev->dev.platform_data;
48
49 if ((result = gpio_request(pdata->gpio_bit, "vlynq")))
50 goto out;
51
52 ar7_device_reset(pdata->reset_bit);
53
54 if ((result = ar7_gpio_disable(pdata->gpio_bit)))
55 goto out_enabled;
56
57 if ((result = ar7_gpio_enable(pdata->gpio_bit)))
58 goto out_enabled;
59
60 if ((result = gpio_direction_output(pdata->gpio_bit)))
61 goto out_gpio_enabled;
62
63 gpio_set_value(pdata->gpio_bit, 0);
64 mdelay(50);
65
66 gpio_set_value(pdata->gpio_bit, 1);
67 mdelay(50);
68
69 return 0;
70
71 out_gpio_enabled:
72 ar7_gpio_disable(pdata->gpio_bit);
73 out_enabled:
74 ar7_device_disable(pdata->reset_bit);
75 gpio_free(pdata->gpio_bit);
76 out:
77 return result;
78 }
79
80 static void vlynq_off(struct vlynq_device *dev)
81 {
82 struct plat_vlynq_data *pdata = dev->dev.platform_data;
83 ar7_gpio_disable(pdata->gpio_bit);
84 gpio_free(pdata->gpio_bit);
85 ar7_device_disable(pdata->reset_bit);
86 }
87
88 static struct resource physmap_flash_resource = {
89 .name = "mem",
90 .flags = IORESOURCE_MEM,
91 .start = 0x10000000,
92 .end = 0x103fffff,
93 };
94
95 static struct resource cpmac_low_res[] = {
96 {
97 .name = "regs",
98 .flags = IORESOURCE_MEM,
99 .start = AR7_REGS_MAC0,
100 .end = AR7_REGS_MAC0 + 0x7FF,
101 },
102 {
103 .name = "irq",
104 .flags = IORESOURCE_IRQ,
105 .start = 27,
106 .end = 27,
107 },
108 };
109
110 static struct resource cpmac_high_res[] = {
111 {
112 .name = "regs",
113 .flags = IORESOURCE_MEM,
114 .start = AR7_REGS_MAC1,
115 .end = AR7_REGS_MAC1 + 0x7FF,
116 },
117 {
118 .name = "irq",
119 .flags = IORESOURCE_IRQ,
120 .start = 41,
121 .end = 41,
122 },
123 };
124
125 static struct resource vlynq_low_res[] = {
126 {
127 .name = "regs",
128 .flags = IORESOURCE_MEM,
129 .start = AR7_REGS_VLYNQ0,
130 .end = AR7_REGS_VLYNQ0 + 0xff,
131 },
132 {
133 .name = "irq",
134 .flags = IORESOURCE_IRQ,
135 .start = 29,
136 .end = 29,
137 },
138 {
139 .name = "mem",
140 .flags = IORESOURCE_MEM,
141 .start = 0x04000000,
142 .end = 0x04ffffff,
143 },
144 {
145 .name = "devirq",
146 .flags = IORESOURCE_IRQ,
147 .start = 80,
148 .end = 111,
149 },
150 };
151
152 static struct resource vlynq_high_res[] = {
153 {
154 .name = "regs",
155 .flags = IORESOURCE_MEM,
156 .start = AR7_REGS_VLYNQ1,
157 .end = AR7_REGS_VLYNQ1 + 0xFF,
158 },
159 {
160 .name = "irq",
161 .flags = IORESOURCE_IRQ,
162 .start = 33,
163 .end = 33,
164 },
165 {
166 .name = "mem",
167 .flags = IORESOURCE_MEM,
168 .start = 0x0c000000,
169 .end = 0x0cffffff,
170 },
171 {
172 .name = "devirq",
173 .flags = IORESOURCE_IRQ,
174 .start = 112,
175 .end = 143,
176 },
177 };
178
179 static struct physmap_flash_data physmap_flash_data = {
180 .width = 2,
181 };
182
183 static struct plat_cpmac_data cpmac_low_data = {
184 .reset_bit = 17,
185 .power_bit = 20,
186 .phy_mask = 0x80000000,
187 };
188
189 static struct plat_cpmac_data cpmac_high_data = {
190 .reset_bit = 21,
191 .power_bit = 22,
192 .phy_mask = 0x7fffffff,
193 };
194
195 static struct plat_vlynq_data vlynq_low_data = {
196 .ops.on = vlynq_on,
197 .ops.off = vlynq_off,
198 .reset_bit = 20,
199 .gpio_bit = 18,
200 };
201
202 static struct plat_vlynq_data vlynq_high_data = {
203 .ops.on = vlynq_on,
204 .ops.off = vlynq_off,
205 .reset_bit = 16,
206 .gpio_bit = 19,
207 };
208
209 static struct platform_device physmap_flash = {
210 .id = 0,
211 .name = "physmap-flash",
212 .dev.platform_data = &physmap_flash_data,
213 .resource = &physmap_flash_resource,
214 .num_resources = 1,
215 };
216
217 static struct platform_device cpmac_low = {
218 .id = 0,
219 .name = "cpmac",
220 .dev.platform_data = &cpmac_low_data,
221 .resource = cpmac_low_res,
222 .num_resources = ARRAY_SIZE(cpmac_low_res),
223 };
224
225 static struct platform_device cpmac_high = {
226 .id = 1,
227 .name = "cpmac",
228 .dev.platform_data = &cpmac_high_data,
229 .resource = cpmac_high_res,
230 .num_resources = ARRAY_SIZE(cpmac_high_res),
231 };
232
233 static struct platform_device vlynq_low = {
234 .id = 0,
235 .name = "vlynq",
236 .dev.platform_data = &vlynq_low_data,
237 .resource = vlynq_low_res,
238 .num_resources = ARRAY_SIZE(vlynq_low_res),
239 };
240
241 static struct platform_device vlynq_high = {
242 .id = 1,
243 .name = "vlynq",
244 .dev.platform_data = &vlynq_high_data,
245 .resource = vlynq_high_res,
246 .num_resources = ARRAY_SIZE(vlynq_high_res),
247 };
248
249
250 /* This is proper way to define uart ports, but they are then detected
251 * as xscale and, obviously, don't work...
252 */
253 #if !defined(CONFIG_SERIAL_8250)
254 static struct plat_serial8250_port uart_data[] = {
255 {
256 .mapbase = AR7_REGS_UART0,
257 .irq = AR7_IRQ_UART0,
258 .regshift = 2,
259 .iotype = UPIO_MEM,
260 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
261 },
262 {
263 .mapbase = AR7_REGS_UART1,
264 .irq = AR7_IRQ_UART1,
265 .regshift = 2,
266 .iotype = UPIO_MEM,
267 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
268 },
269 {
270 .flags = 0,
271 },
272 };
273
274 static struct platform_device uart = {
275 .id = 0,
276 .name = "serial8250",
277 .dev.platform_data = uart_data,
278 };
279 #endif
280
281 static inline unsigned char char2hex(char h)
282 {
283 switch (h) {
284 case '0': case '1': case '2': case '3': case '4':
285 case '5': case '6': case '7': case '8': case '9':
286 return h - '0';
287 case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
288 return h - 'A' + 10;
289 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
290 return h - 'a' + 10;
291 default:
292 return 0;
293 }
294 }
295
296 static void cpmac_get_mac(int instance, unsigned char *dev_addr)
297 {
298 int i;
299 char name[5], default_mac[] = "00:00:00:12:34:56", *mac;
300
301 mac = NULL;
302 sprintf(name, "mac%c", 'a' + instance);
303 mac = prom_getenv(name);
304 if (!mac) {
305 sprintf(name, "mac%c", 'a');
306 mac = prom_getenv(name);
307 }
308 if (!mac)
309 mac = default_mac;
310 for (i = 0; i < 6; i++)
311 dev_addr[i] = (char2hex(mac[i * 3]) << 4) +
312 char2hex(mac[i * 3 + 1]);
313 }
314
315 static int __init ar7_register_devices(void)
316 {
317 int res;
318
319 #if defined(CONFIG_SERIAL_8250)
320 static struct uart_port uart_port[2];
321
322 memset(uart_port, 0, sizeof(struct uart_port) * 2);
323
324 uart_port[0].type = PORT_16750;
325 uart_port[0].line = 0;
326 uart_port[0].irq = AR7_IRQ_UART0;
327 uart_port[0].uartclk = ar7_bus_freq() / 2;
328 uart_port[0].iotype = UPIO_MEM;
329 uart_port[0].mapbase = AR7_REGS_UART0;
330 uart_port[0].membase = ioremap(uart_port[0].mapbase, 256);
331 uart_port[0].regshift = 2;
332 res = early_serial_setup(&uart_port[0]);
333 if (res)
334 return res;
335
336 uart_port[1].type = PORT_16750;
337 uart_port[1].line = 1;
338 uart_port[1].irq = AR7_IRQ_UART1;
339 uart_port[1].uartclk = ar7_bus_freq() / 2;
340 uart_port[1].iotype = UPIO_MEM;
341 uart_port[1].mapbase = AR7_REGS_UART1;
342 uart_port[1].membase = ioremap(uart_port[1].mapbase, 256);
343 uart_port[1].regshift = 2;
344 res = early_serial_setup(&uart_port[1]);
345 if (res)
346 return res;
347 #else
348 uart_data[0].uartclk = ar7_bus_freq() / 2;
349 uart_data[1].uartclk = uart_data[0].uartclk;
350 res = platform_device_register(&uart);
351 if (res)
352 return res;
353 #endif
354 res = platform_device_register(&physmap_flash);
355 if (res)
356 return res;
357
358 res = platform_device_register(&vlynq_low);
359 if (res)
360 return res;
361
362 ar7_device_disable(vlynq_low_data.reset_bit);
363 if (ar7_has_high_vlynq()) {
364 ar7_device_disable(vlynq_high_data.reset_bit);
365 res = platform_device_register(&vlynq_high);
366 if (res)
367 return res;
368 }
369
370 if (ar7_has_high_cpmac()) {
371 cpmac_get_mac(1, cpmac_high_data.dev_addr);
372 res = platform_device_register(&cpmac_high);
373 if (res)
374 return res;
375 } else {
376 cpmac_low_data.phy_mask = 0xffffffff;
377 }
378
379 cpmac_get_mac(0, cpmac_low_data.dev_addr);
380 res = platform_device_register(&cpmac_low);
381
382 return res;
383 }
384
385
386 arch_initcall(ar7_register_devices);