projects / openwrt / staging / chunkeey.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ag71xx: store ring size order instead of ring size to avoid div/mod
[openwrt/staging/chunkeey.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)
17 static inline void skb_free_frag(void *data)
18 {
19 put_page(virt_to_head_page(data));
20 }
21 #endif
22
23 #define AG71XX_DEFAULT_MSG_ENABLE \
24 (NETIF_MSG_DRV \
25 | NETIF_MSG_PROBE \
26 | NETIF_MSG_LINK \
27 | NETIF_MSG_TIMER \
28 | NETIF_MSG_IFDOWN \
29 | NETIF_MSG_IFUP \
30 | NETIF_MSG_RX_ERR \
31 | NETIF_MSG_TX_ERR)
32
33 static int ag71xx_msg_level = -1;
34
35 module_param_named(msg_level, ag71xx_msg_level, int, 0);
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
37
38 #define ETH_SWITCH_HEADER_LEN 2
39
40 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
41
42 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
43 {
44 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
45 }
46
47 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
48 {
49 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
50 ag->dev->name,
51 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
52 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
53 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
54
55 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
58 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
59 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
60 }
61
62 static void ag71xx_dump_regs(struct ag71xx *ag)
63 {
64 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
65 ag->dev->name,
66 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
67 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
68 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
69 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
70 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
71 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
72 ag->dev->name,
73 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
74 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
75 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
76 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
77 ag->dev->name,
78 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
79 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
80 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
81 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
82 ag->dev->name,
83 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
84 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
85 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
86 }
87
88 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
89 {
90 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
91 ag->dev->name, label, intr,
92 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
93 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
94 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
95 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
96 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
97 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
98 }
99
100 static void ag71xx_ring_free(struct ag71xx_ring *ring)
101 {
102 int ring_size = BIT(ring->order);
103 kfree(ring->buf);
104
105 if (ring->descs_cpu)
106 dma_free_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
107 ring->descs_cpu, ring->descs_dma);
108 }
109
110 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
111 {
112 int ring_size = BIT(ring->order);
113 int err;
114
115 ring->descs_cpu = dma_alloc_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
116 &ring->descs_dma, GFP_ATOMIC);
117 if (!ring->descs_cpu) {
118 err = -ENOMEM;
119 goto err;
120 }
121
122
123 ring->buf = kzalloc(ring_size * sizeof(*ring->buf), GFP_KERNEL);
124 if (!ring->buf) {
125 err = -ENOMEM;
126 goto err;
127 }
128
129 return 0;
130
131 err:
132 return err;
133 }
134
135 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
136 {
137 struct ag71xx_ring *ring = &ag->tx_ring;
138 struct net_device *dev = ag->dev;
139 int ring_mask = BIT(ring->order) - 1;
140 u32 bytes_compl = 0, pkts_compl = 0;
141
142 while (ring->curr != ring->dirty) {
143 struct ag71xx_desc *desc;
144 u32 i = ring->dirty & ring_mask;
145
146 desc = ag71xx_ring_desc(ring, i);
147 if (!ag71xx_desc_empty(desc)) {
148 desc->ctrl = 0;
149 dev->stats.tx_errors++;
150 }
151
152 if (ring->buf[i].skb) {
153 bytes_compl += ring->buf[i].len;
154 pkts_compl++;
155 dev_kfree_skb_any(ring->buf[i].skb);
156 }
157 ring->buf[i].skb = NULL;
158 ring->dirty++;
159 }
160
161 /* flush descriptors */
162 wmb();
163
164 netdev_completed_queue(dev, pkts_compl, bytes_compl);
165 }
166
167 static void ag71xx_ring_tx_init(struct ag71xx *ag)
168 {
169 struct ag71xx_ring *ring = &ag->tx_ring;
170 int ring_size = BIT(ring->order);
171 int ring_mask = ring_size - 1;
172 int i;
173
174 for (i = 0; i < ring_size; i++) {
175 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
176
177 desc->next = (u32) (ring->descs_dma +
178 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
179
180 desc->ctrl = DESC_EMPTY;
181 ring->buf[i].skb = NULL;
182 }
183
184 /* flush descriptors */
185 wmb();
186
187 ring->curr = 0;
188 ring->dirty = 0;
189 netdev_reset_queue(ag->dev);
190 }
191
192 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
193 {
194 struct ag71xx_ring *ring = &ag->rx_ring;
195 int ring_size = BIT(ring->order);
196 int i;
197
198 if (!ring->buf)
199 return;
200
201 for (i = 0; i < ring_size; i++)
202 if (ring->buf[i].rx_buf) {
203 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
204 ag->rx_buf_size, DMA_FROM_DEVICE);
205 skb_free_frag(ring->buf[i].rx_buf);
206 }
207 }
208
209 static int ag71xx_buffer_offset(struct ag71xx *ag)
210 {
211 int offset = NET_SKB_PAD;
212
213 /*
214 * On AR71xx/AR91xx packets must be 4-byte aligned.
215 *
216 * When using builtin AR8216 support, hardware adds a 2-byte header,
217 * so we don't need any extra alignment in that case.
218 */
219 if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
220 return offset;
221
222 return offset + NET_IP_ALIGN;
223 }
224
225 static int ag71xx_buffer_size(struct ag71xx *ag)
226 {
227 return ag->rx_buf_size +
228 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
229 }
230
231 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
232 int offset,
233 void *(*alloc)(unsigned int size))
234 {
235 struct ag71xx_ring *ring = &ag->rx_ring;
236 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
237 void *data;
238
239 data = alloc(ag71xx_buffer_size(ag));
240 if (!data)
241 return false;
242
243 buf->rx_buf = data;
244 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
245 DMA_FROM_DEVICE);
246 desc->data = (u32) buf->dma_addr + offset;
247 return true;
248 }
249
250 static int ag71xx_ring_rx_init(struct ag71xx *ag)
251 {
252 struct ag71xx_ring *ring = &ag->rx_ring;
253 int ring_size = BIT(ring->order);
254 int ring_mask = BIT(ring->order) - 1;
255 unsigned int i;
256 int ret;
257 int offset = ag71xx_buffer_offset(ag);
258
259 ret = 0;
260 for (i = 0; i < ring_size; i++) {
261 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
262
263 desc->next = (u32) (ring->descs_dma +
264 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
265
266 DBG("ag71xx: RX desc at %p, next is %08x\n",
267 desc, desc->next);
268 }
269
270 for (i = 0; i < ring_size; i++) {
271 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
272
273 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
274 netdev_alloc_frag)) {
275 ret = -ENOMEM;
276 break;
277 }
278
279 desc->ctrl = DESC_EMPTY;
280 }
281
282 /* flush descriptors */
283 wmb();
284
285 ring->curr = 0;
286 ring->dirty = 0;
287
288 return ret;
289 }
290
291 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
292 {
293 struct ag71xx_ring *ring = &ag->rx_ring;
294 int ring_mask = BIT(ring->order) - 1;
295 unsigned int count;
296 int offset = ag71xx_buffer_offset(ag);
297
298 count = 0;
299 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
300 struct ag71xx_desc *desc;
301 unsigned int i;
302
303 i = ring->dirty & ring_mask;
304 desc = ag71xx_ring_desc(ring, i);
305
306 if (!ring->buf[i].rx_buf &&
307 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
308 napi_alloc_frag))
309 break;
310
311 desc->ctrl = DESC_EMPTY;
312 count++;
313 }
314
315 /* flush descriptors */
316 wmb();
317
318 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
319
320 return count;
321 }
322
323 static int ag71xx_rings_init(struct ag71xx *ag)
324 {
325 int ret;
326
327 ret = ag71xx_ring_alloc(&ag->tx_ring);
328 if (ret)
329 return ret;
330
331 ag71xx_ring_tx_init(ag);
332
333 ret = ag71xx_ring_alloc(&ag->rx_ring);
334 if (ret)
335 return ret;
336
337 ret = ag71xx_ring_rx_init(ag);
338 return ret;
339 }
340
341 static void ag71xx_rings_cleanup(struct ag71xx *ag)
342 {
343 ag71xx_ring_rx_clean(ag);
344 ag71xx_ring_free(&ag->rx_ring);
345
346 ag71xx_ring_tx_clean(ag);
347 netdev_reset_queue(ag->dev);
348 ag71xx_ring_free(&ag->tx_ring);
349 }
350
351 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
352 {
353 switch (ag->speed) {
354 case SPEED_1000:
355 return "1000";
356 case SPEED_100:
357 return "100";
358 case SPEED_10:
359 return "10";
360 }
361
362 return "?";
363 }
364
365 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
366 {
367 u32 t;
368
369 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
370 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
371
372 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
373
374 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
375 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
376 }
377
378 static void ag71xx_dma_reset(struct ag71xx *ag)
379 {
380 u32 val;
381 int i;
382
383 ag71xx_dump_dma_regs(ag);
384
385 /* stop RX and TX */
386 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
387 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
388
389 /*
390 * give the hardware some time to really stop all rx/tx activity
391 * clearing the descriptors too early causes random memory corruption
392 */
393 mdelay(1);
394
395 /* clear descriptor addresses */
396 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
397 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
398
399 /* clear pending RX/TX interrupts */
400 for (i = 0; i < 256; i++) {
401 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
402 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
403 }
404
405 /* clear pending errors */
406 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
407 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
408
409 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
410 if (val)
411 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
412 ag->dev->name, val);
413
414 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
415
416 /* mask out reserved bits */
417 val &= ~0xff000000;
418
419 if (val)
420 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
421 ag->dev->name, val);
422
423 ag71xx_dump_dma_regs(ag);
424 }
425
426 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
427 MAC_CFG1_SRX | MAC_CFG1_STX)
428
429 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
430
431 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
432 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
433 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
434 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
435 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
436 FIFO_CFG4_VT)
437
438 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
439 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
440 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
441 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
442 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
443 FIFO_CFG5_17 | FIFO_CFG5_SF)
444
445 static void ag71xx_hw_stop(struct ag71xx *ag)
446 {
447 /* disable all interrupts and stop the rx/tx engine */
448 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
449 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
450 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
451 }
452
453 static void ag71xx_hw_setup(struct ag71xx *ag)
454 {
455 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
456
457 /* setup MAC configuration registers */
458 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
459
460 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
461 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
462
463 /* setup max frame length to zero */
464 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
465
466 /* setup FIFO configuration registers */
467 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
468 if (pdata->is_ar724x) {
469 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
470 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
471 } else {
472 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
473 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
474 }
475 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
476 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
477 }
478
479 static void ag71xx_hw_init(struct ag71xx *ag)
480 {
481 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
482 u32 reset_mask = pdata->reset_bit;
483
484 ag71xx_hw_stop(ag);
485
486 if (pdata->is_ar724x) {
487 u32 reset_phy = reset_mask;
488
489 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
490 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
491
492 ath79_device_reset_set(reset_phy);
493 msleep(50);
494 ath79_device_reset_clear(reset_phy);
495 msleep(200);
496 }
497
498 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
499 udelay(20);
500
501 ath79_device_reset_set(reset_mask);
502 msleep(100);
503 ath79_device_reset_clear(reset_mask);
504 msleep(200);
505
506 ag71xx_hw_setup(ag);
507
508 ag71xx_dma_reset(ag);
509 }
510
511 static void ag71xx_fast_reset(struct ag71xx *ag)
512 {
513 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
514 struct net_device *dev = ag->dev;
515 u32 reset_mask = pdata->reset_bit;
516 u32 rx_ds, tx_ds;
517 u32 mii_reg;
518
519 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
520
521 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
522 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
523 tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
524
525 ath79_device_reset_set(reset_mask);
526 udelay(10);
527 ath79_device_reset_clear(reset_mask);
528 udelay(10);
529
530 ag71xx_dma_reset(ag);
531 ag71xx_hw_setup(ag);
532 ag71xx_tx_packets(ag, true);
533
534 /* setup max frame length */
535 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
536 ag71xx_max_frame_len(ag->dev->mtu));
537
538 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
539 ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
540 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
541
542 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
543 }
544
545 static void ag71xx_hw_start(struct ag71xx *ag)
546 {
547 /* start RX engine */
548 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
549
550 /* enable interrupts */
551 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
552
553 netif_wake_queue(ag->dev);
554 }
555
556 static void
557 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
558 {
559 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
560 u32 cfg2;
561 u32 ifctl;
562 u32 fifo5;
563 u32 fifo3;
564
565 if (!ag->link && update) {
566 ag71xx_hw_stop(ag);
567 netif_carrier_off(ag->dev);
568 if (netif_msg_link(ag))
569 pr_info("%s: link down\n", ag->dev->name);
570 return;
571 }
572
573 if (pdata->is_ar724x)
574 ag71xx_fast_reset(ag);
575
576 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
577 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
578 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
579
580 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
581 ifctl &= ~(MAC_IFCTL_SPEED);
582
583 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
584 fifo5 &= ~FIFO_CFG5_BM;
585
586 switch (ag->speed) {
587 case SPEED_1000:
588 cfg2 |= MAC_CFG2_IF_1000;
589 fifo5 |= FIFO_CFG5_BM;
590 break;
591 case SPEED_100:
592 cfg2 |= MAC_CFG2_IF_10_100;
593 ifctl |= MAC_IFCTL_SPEED;
594 break;
595 case SPEED_10:
596 cfg2 |= MAC_CFG2_IF_10_100;
597 break;
598 default:
599 BUG();
600 return;
601 }
602
603 if (pdata->is_ar91xx)
604 fifo3 = 0x00780fff;
605 else if (pdata->is_ar724x)
606 fifo3 = pdata->fifo_cfg3;
607 else
608 fifo3 = 0x008001ff;
609
610 if (ag->tx_ring.desc_split) {
611 fifo3 &= 0xffff;
612 fifo3 |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
613 }
614
615 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3);
616
617 if (update && pdata->set_speed)
618 pdata->set_speed(ag->speed);
619
620 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
621 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
622 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
623 ag71xx_hw_start(ag);
624
625 netif_carrier_on(ag->dev);
626 if (update && netif_msg_link(ag))
627 pr_info("%s: link up (%sMbps/%s duplex)\n",
628 ag->dev->name,
629 ag71xx_speed_str(ag),
630 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
631
632 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
633 ag->dev->name,
634 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
635 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
636 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
637
638 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
639 ag->dev->name,
640 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
641 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
642 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
643
644 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
645 ag->dev->name,
646 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
647 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
648 }
649
650 void ag71xx_link_adjust(struct ag71xx *ag)
651 {
652 __ag71xx_link_adjust(ag, true);
653 }
654
655 static int ag71xx_hw_enable(struct ag71xx *ag)
656 {
657 int ret;
658
659 ret = ag71xx_rings_init(ag);
660 if (ret)
661 return ret;
662
663 napi_enable(&ag->napi);
664 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
665 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
666 netif_start_queue(ag->dev);
667
668 return 0;
669 }
670
671 static void ag71xx_hw_disable(struct ag71xx *ag)
672 {
673 unsigned long flags;
674
675 spin_lock_irqsave(&ag->lock, flags);
676
677 netif_stop_queue(ag->dev);
678
679 ag71xx_hw_stop(ag);
680 ag71xx_dma_reset(ag);
681
682 napi_disable(&ag->napi);
683 del_timer_sync(&ag->oom_timer);
684
685 spin_unlock_irqrestore(&ag->lock, flags);
686
687 ag71xx_rings_cleanup(ag);
688 }
689
690 static int ag71xx_open(struct net_device *dev)
691 {
692 struct ag71xx *ag = netdev_priv(dev);
693 unsigned int max_frame_len;
694 int ret;
695
696 netif_carrier_off(dev);
697 max_frame_len = ag71xx_max_frame_len(dev->mtu);
698 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
699
700 /* setup max frame length */
701 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
702 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
703
704 ret = ag71xx_hw_enable(ag);
705 if (ret)
706 goto err;
707
708 ag71xx_phy_start(ag);
709
710 return 0;
711
712 err:
713 ag71xx_rings_cleanup(ag);
714 return ret;
715 }
716
717 static int ag71xx_stop(struct net_device *dev)
718 {
719 struct ag71xx *ag = netdev_priv(dev);
720
721 netif_carrier_off(dev);
722 ag71xx_phy_stop(ag);
723 ag71xx_hw_disable(ag);
724
725 return 0;
726 }
727
728 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
729 {
730 int i;
731 struct ag71xx_desc *desc;
732 int ring_mask = BIT(ring->order) - 1;
733 int ndesc = 0;
734 int split = ring->desc_split;
735
736 if (!split)
737 split = len;
738
739 while (len > 0) {
740 unsigned int cur_len = len;
741
742 i = (ring->curr + ndesc) & ring_mask;
743 desc = ag71xx_ring_desc(ring, i);
744
745 if (!ag71xx_desc_empty(desc))
746 return -1;
747
748 if (cur_len > split) {
749 cur_len = split;
750
751 /*
752 * TX will hang if DMA transfers <= 4 bytes,
753 * make sure next segment is more than 4 bytes long.
754 */
755 if (len <= split + 4)
756 cur_len -= 4;
757 }
758
759 desc->data = addr;
760 addr += cur_len;
761 len -= cur_len;
762
763 if (len > 0)
764 cur_len |= DESC_MORE;
765
766 /* prevent early tx attempt of this descriptor */
767 if (!ndesc)
768 cur_len |= DESC_EMPTY;
769
770 desc->ctrl = cur_len;
771 ndesc++;
772 }
773
774 return ndesc;
775 }
776
777 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
778 struct net_device *dev)
779 {
780 struct ag71xx *ag = netdev_priv(dev);
781 struct ag71xx_ring *ring = &ag->tx_ring;
782 int ring_mask = BIT(ring->order) - 1;
783 int ring_size = BIT(ring->order);
784 struct ag71xx_desc *desc;
785 dma_addr_t dma_addr;
786 int i, n, ring_min;
787
788 if (ag71xx_has_ar8216(ag))
789 ag71xx_add_ar8216_header(ag, skb);
790
791 if (skb->len <= 4) {
792 DBG("%s: packet len is too small\n", ag->dev->name);
793 goto err_drop;
794 }
795
796 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
797 DMA_TO_DEVICE);
798
799 i = ring->curr & ring_mask;
800 desc = ag71xx_ring_desc(ring, i);
801
802 /* setup descriptor fields */
803 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
804 if (n < 0)
805 goto err_drop_unmap;
806
807 i = (ring->curr + n - 1) & ring_mask;
808 ring->buf[i].len = skb->len;
809 ring->buf[i].skb = skb;
810 ring->buf[i].timestamp = jiffies;
811
812 netdev_sent_queue(dev, skb->len);
813
814 desc->ctrl &= ~DESC_EMPTY;
815 ring->curr += n;
816
817 /* flush descriptor */
818 wmb();
819
820 ring_min = 2;
821 if (ring->desc_split)
822 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
823
824 if (ring->curr - ring->dirty >= ring_size - ring_min) {
825 DBG("%s: tx queue full\n", dev->name);
826 netif_stop_queue(dev);
827 }
828
829 DBG("%s: packet injected into TX queue\n", ag->dev->name);
830
831 /* enable TX engine */
832 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
833
834 return NETDEV_TX_OK;
835
836 err_drop_unmap:
837 dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
838
839 err_drop:
840 dev->stats.tx_dropped++;
841
842 dev_kfree_skb(skb);
843 return NETDEV_TX_OK;
844 }
845
846 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
847 {
848 struct ag71xx *ag = netdev_priv(dev);
849 int ret;
850
851 switch (cmd) {
852 case SIOCETHTOOL:
853 if (ag->phy_dev == NULL)
854 break;
855
856 spin_lock_irq(&ag->lock);
857 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
858 spin_unlock_irq(&ag->lock);
859 return ret;
860
861 case SIOCSIFHWADDR:
862 if (copy_from_user
863 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
864 return -EFAULT;
865 return 0;
866
867 case SIOCGIFHWADDR:
868 if (copy_to_user
869 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
870 return -EFAULT;
871 return 0;
872
873 case SIOCGMIIPHY:
874 case SIOCGMIIREG:
875 case SIOCSMIIREG:
876 if (ag->phy_dev == NULL)
877 break;
878
879 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
880
881 default:
882 break;
883 }
884
885 return -EOPNOTSUPP;
886 }
887
888 static void ag71xx_oom_timer_handler(unsigned long data)
889 {
890 struct net_device *dev = (struct net_device *) data;
891 struct ag71xx *ag = netdev_priv(dev);
892
893 napi_schedule(&ag->napi);
894 }
895
896 static void ag71xx_tx_timeout(struct net_device *dev)
897 {
898 struct ag71xx *ag = netdev_priv(dev);
899
900 if (netif_msg_tx_err(ag))
901 pr_info("%s: tx timeout\n", ag->dev->name);
902
903 schedule_work(&ag->restart_work);
904 }
905
906 static void ag71xx_restart_work_func(struct work_struct *work)
907 {
908 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
909
910 rtnl_lock();
911 ag71xx_hw_disable(ag);
912 ag71xx_hw_enable(ag);
913 if (ag->link)
914 __ag71xx_link_adjust(ag, false);
915 rtnl_unlock();
916 }
917
918 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
919 {
920 u32 rx_sm, tx_sm, rx_fd;
921
922 if (likely(time_before(jiffies, timestamp + HZ/10)))
923 return false;
924
925 if (!netif_carrier_ok(ag->dev))
926 return false;
927
928 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
929 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
930 return true;
931
932 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
933 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
934 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
935 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
936 return true;
937
938 return false;
939 }
940
941 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
942 {
943 struct ag71xx_ring *ring = &ag->tx_ring;
944 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
945 int ring_mask = BIT(ring->order) - 1;
946 int ring_size = BIT(ring->order);
947 int sent = 0;
948 int bytes_compl = 0;
949 int n = 0;
950
951 DBG("%s: processing TX ring\n", ag->dev->name);
952
953 while (ring->dirty + n != ring->curr) {
954 unsigned int i = (ring->dirty + n) & ring_mask;
955 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
956 struct sk_buff *skb = ring->buf[i].skb;
957
958 if (!flush && !ag71xx_desc_empty(desc)) {
959 if (pdata->is_ar724x &&
960 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
961 schedule_work(&ag->restart_work);
962 break;
963 }
964
965 n++;
966 if (!skb)
967 continue;
968
969 dev_kfree_skb_any(skb);
970 ring->buf[i].skb = NULL;
971
972 bytes_compl += ring->buf[i].len;
973
974 sent++;
975 ring->dirty += n;
976
977 while (n > 0) {
978 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
979 n--;
980 }
981 }
982
983 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
984
985 ag->dev->stats.tx_bytes += bytes_compl;
986 ag->dev->stats.tx_packets += sent;
987
988 if (!sent)
989 return 0;
990
991 netdev_completed_queue(ag->dev, sent, bytes_compl);
992 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
993 netif_wake_queue(ag->dev);
994
995 return sent;
996 }
997
998 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
999 {
1000 struct net_device *dev = ag->dev;
1001 struct ag71xx_ring *ring = &ag->rx_ring;
1002 int offset = ag71xx_buffer_offset(ag);
1003 unsigned int pktlen_mask = ag->desc_pktlen_mask;
1004 int ring_mask = BIT(ring->order) - 1;
1005 int ring_size = BIT(ring->order);
1006 struct sk_buff_head queue;
1007 struct sk_buff *skb;
1008 int done = 0;
1009
1010 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1011 dev->name, limit, ring->curr, ring->dirty);
1012
1013 skb_queue_head_init(&queue);
1014
1015 while (done < limit) {
1016 unsigned int i = ring->curr & ring_mask;
1017 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1018 int pktlen;
1019 int err = 0;
1020
1021 if (ag71xx_desc_empty(desc))
1022 break;
1023
1024 if ((ring->dirty + ring_size) == ring->curr) {
1025 ag71xx_assert(0);
1026 break;
1027 }
1028
1029 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1030
1031 pktlen = desc->ctrl & pktlen_mask;
1032 pktlen -= ETH_FCS_LEN;
1033
1034 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
1035 ag->rx_buf_size, DMA_FROM_DEVICE);
1036
1037 dev->stats.rx_packets++;
1038 dev->stats.rx_bytes += pktlen;
1039
1040 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1041 if (!skb) {
1042 skb_free_frag(ring->buf[i].rx_buf);
1043 goto next;
1044 }
1045
1046 skb_reserve(skb, offset);
1047 skb_put(skb, pktlen);
1048
1049 if (ag71xx_has_ar8216(ag))
1050 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
1051
1052 if (err) {
1053 dev->stats.rx_dropped++;
1054 kfree_skb(skb);
1055 } else {
1056 skb->dev = dev;
1057 skb->ip_summed = CHECKSUM_NONE;
1058 __skb_queue_tail(&queue, skb);
1059 }
1060
1061 next:
1062 ring->buf[i].rx_buf = NULL;
1063 done++;
1064
1065 ring->curr++;
1066 }
1067
1068 ag71xx_ring_rx_refill(ag);
1069
1070 while ((skb = __skb_dequeue(&queue)) != NULL) {
1071 skb->protocol = eth_type_trans(skb, dev);
1072 netif_receive_skb(skb);
1073 }
1074
1075 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1076 dev->name, ring->curr, ring->dirty, done);
1077
1078 return done;
1079 }
1080
1081 static int ag71xx_poll(struct napi_struct *napi, int limit)
1082 {
1083 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1084 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1085 struct net_device *dev = ag->dev;
1086 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1087 int rx_ring_size = BIT(rx_ring->order);
1088 unsigned long flags;
1089 u32 status;
1090 int tx_done;
1091 int rx_done;
1092
1093 pdata->ddr_flush();
1094 tx_done = ag71xx_tx_packets(ag, false);
1095
1096 DBG("%s: processing RX ring\n", dev->name);
1097 rx_done = ag71xx_rx_packets(ag, limit);
1098
1099 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1100
1101 if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1102 goto oom;
1103
1104 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1105 if (unlikely(status & RX_STATUS_OF)) {
1106 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1107 dev->stats.rx_fifo_errors++;
1108
1109 /* restart RX */
1110 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1111 }
1112
1113 if (rx_done < limit) {
1114 if (status & RX_STATUS_PR)
1115 goto more;
1116
1117 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1118 if (status & TX_STATUS_PS)
1119 goto more;
1120
1121 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1122 dev->name, rx_done, tx_done, limit);
1123
1124 napi_complete(napi);
1125
1126 /* enable interrupts */
1127 spin_lock_irqsave(&ag->lock, flags);
1128 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1129 spin_unlock_irqrestore(&ag->lock, flags);
1130 return rx_done;
1131 }
1132
1133 more:
1134 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1135 dev->name, rx_done, tx_done, limit);
1136 return limit;
1137
1138 oom:
1139 if (netif_msg_rx_err(ag))
1140 pr_info("%s: out of memory\n", dev->name);
1141
1142 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1143 napi_complete(napi);
1144 return 0;
1145 }
1146
1147 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1148 {
1149 struct net_device *dev = dev_id;
1150 struct ag71xx *ag = netdev_priv(dev);
1151 u32 status;
1152
1153 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1154 ag71xx_dump_intr(ag, "raw", status);
1155
1156 if (unlikely(!status))
1157 return IRQ_NONE;
1158
1159 if (unlikely(status & AG71XX_INT_ERR)) {
1160 if (status & AG71XX_INT_TX_BE) {
1161 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1162 dev_err(&dev->dev, "TX BUS error\n");
1163 }
1164 if (status & AG71XX_INT_RX_BE) {
1165 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1166 dev_err(&dev->dev, "RX BUS error\n");
1167 }
1168 }
1169
1170 if (likely(status & AG71XX_INT_POLL)) {
1171 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1172 DBG("%s: enable polling mode\n", dev->name);
1173 napi_schedule(&ag->napi);
1174 }
1175
1176 ag71xx_debugfs_update_int_stats(ag, status);
1177
1178 return IRQ_HANDLED;
1179 }
1180
1181 #ifdef CONFIG_NET_POLL_CONTROLLER
1182 /*
1183 * Polling 'interrupt' - used by things like netconsole to send skbs
1184 * without having to re-enable interrupts. It's not called while
1185 * the interrupt routine is executing.
1186 */
1187 static void ag71xx_netpoll(struct net_device *dev)
1188 {
1189 disable_irq(dev->irq);
1190 ag71xx_interrupt(dev->irq, dev);
1191 enable_irq(dev->irq);
1192 }
1193 #endif
1194
1195 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1196 {
1197 struct ag71xx *ag = netdev_priv(dev);
1198 unsigned int max_frame_len;
1199
1200 max_frame_len = ag71xx_max_frame_len(new_mtu);
1201 if (new_mtu < 68 || max_frame_len > ag->max_frame_len)
1202 return -EINVAL;
1203
1204 if (netif_running(dev))
1205 return -EBUSY;
1206
1207 dev->mtu = new_mtu;
1208 return 0;
1209 }
1210
1211 static const struct net_device_ops ag71xx_netdev_ops = {
1212 .ndo_open = ag71xx_open,
1213 .ndo_stop = ag71xx_stop,
1214 .ndo_start_xmit = ag71xx_hard_start_xmit,
1215 .ndo_do_ioctl = ag71xx_do_ioctl,
1216 .ndo_tx_timeout = ag71xx_tx_timeout,
1217 .ndo_change_mtu = ag71xx_change_mtu,
1218 .ndo_set_mac_address = eth_mac_addr,
1219 .ndo_validate_addr = eth_validate_addr,
1220 #ifdef CONFIG_NET_POLL_CONTROLLER
1221 .ndo_poll_controller = ag71xx_netpoll,
1222 #endif
1223 };
1224
1225 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1226 {
1227 switch (mode) {
1228 case PHY_INTERFACE_MODE_MII:
1229 return "MII";
1230 case PHY_INTERFACE_MODE_GMII:
1231 return "GMII";
1232 case PHY_INTERFACE_MODE_RMII:
1233 return "RMII";
1234 case PHY_INTERFACE_MODE_RGMII:
1235 return "RGMII";
1236 case PHY_INTERFACE_MODE_SGMII:
1237 return "SGMII";
1238 default:
1239 break;
1240 }
1241
1242 return "unknown";
1243 }
1244
1245
1246 static int ag71xx_probe(struct platform_device *pdev)
1247 {
1248 struct net_device *dev;
1249 struct resource *res;
1250 struct ag71xx *ag;
1251 struct ag71xx_platform_data *pdata;
1252 int tx_size, err;
1253
1254 pdata = pdev->dev.platform_data;
1255 if (!pdata) {
1256 dev_err(&pdev->dev, "no platform data specified\n");
1257 err = -ENXIO;
1258 goto err_out;
1259 }
1260
1261 if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
1262 dev_err(&pdev->dev, "no MII bus device specified\n");
1263 err = -EINVAL;
1264 goto err_out;
1265 }
1266
1267 dev = alloc_etherdev(sizeof(*ag));
1268 if (!dev) {
1269 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1270 err = -ENOMEM;
1271 goto err_out;
1272 }
1273
1274 if (!pdata->max_frame_len || !pdata->desc_pktlen_mask)
1275 return -EINVAL;
1276
1277 SET_NETDEV_DEV(dev, &pdev->dev);
1278
1279 ag = netdev_priv(dev);
1280 ag->pdev = pdev;
1281 ag->dev = dev;
1282 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1283 AG71XX_DEFAULT_MSG_ENABLE);
1284 spin_lock_init(&ag->lock);
1285
1286 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1287 if (!res) {
1288 dev_err(&pdev->dev, "no mac_base resource found\n");
1289 err = -ENXIO;
1290 goto err_out;
1291 }
1292
1293 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1294 if (!ag->mac_base) {
1295 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1296 err = -ENOMEM;
1297 goto err_free_dev;
1298 }
1299
1300 dev->irq = platform_get_irq(pdev, 0);
1301 err = request_irq(dev->irq, ag71xx_interrupt,
1302 0x0,
1303 dev->name, dev);
1304 if (err) {
1305 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1306 goto err_unmap_base;
1307 }
1308
1309 dev->base_addr = (unsigned long)ag->mac_base;
1310 dev->netdev_ops = &ag71xx_netdev_ops;
1311 dev->ethtool_ops = &ag71xx_ethtool_ops;
1312
1313 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1314
1315 init_timer(&ag->oom_timer);
1316 ag->oom_timer.data = (unsigned long) dev;
1317 ag->oom_timer.function = ag71xx_oom_timer_handler;
1318
1319 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1320 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1321
1322 ag->max_frame_len = pdata->max_frame_len;
1323 ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
1324
1325 if (!pdata->is_ar724x && !pdata->is_ar91xx) {
1326 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1327 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1328 }
1329 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1330
1331 ag->stop_desc = dma_alloc_coherent(NULL,
1332 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1333
1334 if (!ag->stop_desc)
1335 goto err_free_irq;
1336
1337 ag->stop_desc->data = 0;
1338 ag->stop_desc->ctrl = 0;
1339 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1340
1341 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1342
1343 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1344
1345 ag71xx_dump_regs(ag);
1346
1347 ag71xx_hw_init(ag);
1348
1349 ag71xx_dump_regs(ag);
1350
1351 err = ag71xx_phy_connect(ag);
1352 if (err)
1353 goto err_free_desc;
1354
1355 err = ag71xx_debugfs_init(ag);
1356 if (err)
1357 goto err_phy_disconnect;
1358
1359 platform_set_drvdata(pdev, dev);
1360
1361 err = register_netdev(dev);
1362 if (err) {
1363 dev_err(&pdev->dev, "unable to register net device\n");
1364 goto err_debugfs_exit;
1365 }
1366
1367 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1368 dev->name, dev->base_addr, dev->irq,
1369 ag71xx_get_phy_if_mode_name(pdata->phy_if_mode));
1370
1371 return 0;
1372
1373 err_debugfs_exit:
1374 ag71xx_debugfs_exit(ag);
1375 err_phy_disconnect:
1376 ag71xx_phy_disconnect(ag);
1377 err_free_desc:
1378 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1379 ag->stop_desc_dma);
1380 err_free_irq:
1381 free_irq(dev->irq, dev);
1382 err_unmap_base:
1383 iounmap(ag->mac_base);
1384 err_free_dev:
1385 kfree(dev);
1386 err_out:
1387 platform_set_drvdata(pdev, NULL);
1388 return err;
1389 }
1390
1391 static int ag71xx_remove(struct platform_device *pdev)
1392 {
1393 struct net_device *dev = platform_get_drvdata(pdev);
1394
1395 if (dev) {
1396 struct ag71xx *ag = netdev_priv(dev);
1397
1398 ag71xx_debugfs_exit(ag);
1399 ag71xx_phy_disconnect(ag);
1400 unregister_netdev(dev);
1401 free_irq(dev->irq, dev);
1402 iounmap(ag->mac_base);
1403 kfree(dev);
1404 platform_set_drvdata(pdev, NULL);
1405 }
1406
1407 return 0;
1408 }
1409
1410 static struct platform_driver ag71xx_driver = {
1411 .probe = ag71xx_probe,
1412 .remove = ag71xx_remove,
1413 .driver = {
1414 .name = AG71XX_DRV_NAME,
1415 }
1416 };
1417
1418 static int __init ag71xx_module_init(void)
1419 {
1420 int ret;
1421
1422 ret = ag71xx_debugfs_root_init();
1423 if (ret)
1424 goto err_out;
1425
1426 ret = ag71xx_mdio_driver_init();
1427 if (ret)
1428 goto err_debugfs_exit;
1429
1430 ret = platform_driver_register(&ag71xx_driver);
1431 if (ret)
1432 goto err_mdio_exit;
1433
1434 return 0;
1435
1436 err_mdio_exit:
1437 ag71xx_mdio_driver_exit();
1438 err_debugfs_exit:
1439 ag71xx_debugfs_root_exit();
1440 err_out:
1441 return ret;
1442 }
1443
1444 static void __exit ag71xx_module_exit(void)
1445 {
1446 platform_driver_unregister(&ag71xx_driver);
1447 ag71xx_mdio_driver_exit();
1448 ag71xx_debugfs_root_exit();
1449 }
1450
1451 module_init(ag71xx_module_init);
1452 module_exit(ag71xx_module_exit);
1453
1454 MODULE_VERSION(AG71XX_DRV_VERSION);
1455 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1456 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1457 MODULE_LICENSE("GPL v2");
1458 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
Staging tree of Christian Lamparter