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[openwrt/staging/chunkeey.git] / target / linux / ar71xx / patches-3.14 / 735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
1 --- a/arch/mips/ath79/clock.c
2 +++ b/arch/mips/ath79/clock.c
3 @@ -520,6 +520,100 @@ static void __init qca955x_clocks_init(v
4 clk_add_alias("uart", NULL, "ref", NULL);
5 }
6
7 +static void __init qca956x_clocks_init(void)
8 +{
9 + unsigned long ref_rate;
10 + unsigned long cpu_rate;
11 + unsigned long ddr_rate;
12 + unsigned long ahb_rate;
13 + u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
14 + u32 cpu_pll, ddr_pll;
15 + u32 bootstrap;
16 +
17 + bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
18 + if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
19 + ref_rate = 40 * 1000 * 1000;
20 + else
21 + ref_rate = 25 * 1000 * 1000;
22 +
23 + pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
24 + out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
25 + QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
26 + ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
27 + QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
28 +
29 + pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
30 + nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
31 + QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
32 + hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
33 + QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
34 + lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
35 + QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
36 +
37 + cpu_pll = nint * ref_rate / ref_div;
38 + cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
39 + cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
40 + cpu_pll /= (1 << out_div);
41 +
42 + pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
43 + out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
44 + QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
45 + ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
46 + QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
47 + pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
48 + nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
49 + QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
50 + hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
51 + QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
52 + lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
53 + QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
54 +
55 + ddr_pll = nint * ref_rate / ref_div;
56 + ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
57 + ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
58 + ddr_pll /= (1 << out_div);
59 +
60 + clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
61 +
62 + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
63 + QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
64 +
65 + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
66 + cpu_rate = ref_rate;
67 + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
68 + cpu_rate = ddr_pll / (postdiv + 1);
69 + else
70 + cpu_rate = cpu_pll / (postdiv + 1);
71 +
72 + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
73 + QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
74 +
75 + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
76 + ddr_rate = ref_rate;
77 + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
78 + ddr_rate = cpu_pll / (postdiv + 1);
79 + else
80 + ddr_rate = ddr_pll / (postdiv + 1);
81 +
82 + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
83 + QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
84 +
85 + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
86 + ahb_rate = ref_rate;
87 + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
88 + ahb_rate = ddr_pll / (postdiv + 1);
89 + else
90 + ahb_rate = cpu_pll / (postdiv + 1);
91 +
92 + ath79_add_sys_clkdev("ref", ref_rate);
93 + ath79_add_sys_clkdev("cpu", cpu_rate);
94 + ath79_add_sys_clkdev("ddr", ddr_rate);
95 + ath79_add_sys_clkdev("ahb", ahb_rate);
96 +
97 + clk_add_alias("wdt", NULL, "ref", NULL);
98 + clk_add_alias("uart", NULL, "ref", NULL);
99 +}
100 +
101 void __init ath79_clocks_init(void)
102 {
103 if (soc_is_ar71xx())
104 @@ -536,6 +630,8 @@ void __init ath79_clocks_init(void)
105 qca953x_clocks_init();
106 else if (soc_is_qca955x())
107 qca955x_clocks_init();
108 + else if (soc_is_qca956x())
109 + qca956x_clocks_init();
110 else
111 BUG();
112 }
113 --- a/arch/mips/ath79/common.c
114 +++ b/arch/mips/ath79/common.c
115 @@ -77,6 +77,8 @@ void ath79_device_reset_set(u32 mask)
116 reg = QCA953X_RESET_REG_RESET_MODULE;
117 else if (soc_is_qca955x())
118 reg = QCA955X_RESET_REG_RESET_MODULE;
119 + else if (soc_is_qca956x())
120 + reg = QCA956X_RESET_REG_RESET_MODULE;
121 else
122 panic("Reset register not defined for this SOC");
123
124 @@ -107,6 +109,8 @@ void ath79_device_reset_clear(u32 mask)
125 reg = QCA953X_RESET_REG_RESET_MODULE;
126 else if (soc_is_qca955x())
127 reg = QCA955X_RESET_REG_RESET_MODULE;
128 + else if (soc_is_qca956x())
129 + reg = QCA956X_RESET_REG_RESET_MODULE;
130 else
131 panic("Reset register not defined for this SOC");
132
133 --- a/arch/mips/ath79/dev-common.c
134 +++ b/arch/mips/ath79/dev-common.c
135 @@ -94,7 +94,8 @@ void __init ath79_register_uart(void)
136 soc_is_ar913x() ||
137 soc_is_ar934x() ||
138 soc_is_qca953x() ||
139 - soc_is_qca955x()) {
140 + soc_is_qca955x() ||
141 + soc_is_qca956x()) {
142 ath79_uart_data[0].uartclk = uart_clk_rate;
143 platform_device_register(&ath79_uart_device);
144 } else if (soc_is_ar933x()) {
145 --- a/arch/mips/ath79/dev-eth.c
146 +++ b/arch/mips/ath79/dev-eth.c
147 @@ -198,6 +198,8 @@ void __init ath79_register_mdio(unsigned
148 case ATH79_SOC_AR9330:
149 case ATH79_SOC_AR9331:
150 case ATH79_SOC_QCA9533:
151 + case ATH79_SOC_QCA9561:
152 + case ATH79_SOC_TP9343:
153 mdio_dev = &ath79_mdio1_device;
154 mdio_data = &ath79_mdio1_data;
155 break;
156 @@ -256,6 +258,8 @@ void __init ath79_register_mdio(unsigned
157 break;
158
159 case ATH79_SOC_QCA9533:
160 + case ATH79_SOC_QCA9561:
161 + case ATH79_SOC_TP9343:
162 mdio_data->builtin_switch = 1;
163 break;
164
165 @@ -571,6 +575,8 @@ static void __init ath79_init_eth_pll_da
166 case ATH79_SOC_QCA9533:
167 case ATH79_SOC_QCA9556:
168 case ATH79_SOC_QCA9558:
169 + case ATH79_SOC_QCA9561:
170 + case ATH79_SOC_TP9343:
171 pll_10 = AR934X_PLL_VAL_10;
172 pll_100 = AR934X_PLL_VAL_100;
173 pll_1000 = AR934X_PLL_VAL_1000;
174 @@ -627,6 +633,8 @@ static int __init ath79_setup_phy_if_mod
175 case ATH79_SOC_AR9330:
176 case ATH79_SOC_AR9331:
177 case ATH79_SOC_QCA9533:
178 + case ATH79_SOC_QCA9561:
179 + case ATH79_SOC_TP9343:
180 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
181 break;
182
183 @@ -688,6 +696,8 @@ static int __init ath79_setup_phy_if_mod
184 case ATH79_SOC_AR9330:
185 case ATH79_SOC_AR9331:
186 case ATH79_SOC_QCA9533:
187 + case ATH79_SOC_QCA9561:
188 + case ATH79_SOC_TP9343:
189 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
190 break;
191
192 @@ -992,6 +1002,8 @@ void __init ath79_register_eth(unsigned
193 break;
194
195 case ATH79_SOC_QCA9533:
196 + case ATH79_SOC_QCA9561:
197 + case ATH79_SOC_TP9343:
198 if (id == 0) {
199 pdata->reset_bit = AR933X_RESET_GE0_MAC |
200 AR933X_RESET_GE0_MDIO;
201 @@ -1097,6 +1109,8 @@ void __init ath79_register_eth(unsigned
202 case ATH79_SOC_AR9330:
203 case ATH79_SOC_AR9331:
204 case ATH79_SOC_QCA9533:
205 + case ATH79_SOC_QCA9561:
206 + case ATH79_SOC_TP9343:
207 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
208 break;
209
210 --- a/arch/mips/ath79/dev-usb.c
211 +++ b/arch/mips/ath79/dev-usb.c
212 @@ -272,6 +272,19 @@ static void __init qca955x_usb_setup(voi
213 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
214 }
215
216 +static void __init qca956x_usb_setup(void)
217 +{
218 + ath79_usb_register("ehci-platform", 0,
219 + QCA956X_EHCI0_BASE, QCA956X_EHCI_SIZE,
220 + ATH79_IP3_IRQ(0),
221 + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
222 +
223 + ath79_usb_register("ehci-platform", 1,
224 + QCA956X_EHCI1_BASE, QCA956X_EHCI_SIZE,
225 + ATH79_IP3_IRQ(1),
226 + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
227 +}
228 +
229 void __init ath79_register_usb(void)
230 {
231 if (soc_is_ar71xx())
232 @@ -288,6 +301,8 @@ void __init ath79_register_usb(void)
233 ar934x_usb_setup();
234 else if (soc_is_qca955x())
235 qca955x_usb_setup();
236 + else if (soc_is_qca9561())
237 + qca956x_usb_setup();
238 else
239 BUG();
240 }
241 --- a/arch/mips/ath79/dev-wmac.c
242 +++ b/arch/mips/ath79/dev-wmac.c
243 @@ -189,6 +189,24 @@ static void qca955x_wmac_setup(void)
244 ath79_wmac_data.is_clk_25mhz = true;
245 }
246
247 +static void qca956x_wmac_setup(void)
248 +{
249 + u32 t;
250 +
251 + ath79_wmac_device.name = "qca956x_wmac";
252 +
253 + ath79_wmac_resources[0].start = QCA956X_WMAC_BASE;
254 + ath79_wmac_resources[0].end = QCA956X_WMAC_BASE + QCA956X_WMAC_SIZE - 1;
255 + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
256 + ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
257 +
258 + t = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
259 + if (t & QCA956X_BOOTSTRAP_REF_CLK_40)
260 + ath79_wmac_data.is_clk_25mhz = false;
261 + else
262 + ath79_wmac_data.is_clk_25mhz = true;
263 +}
264 +
265 static bool __init
266 ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
267 {
268 @@ -392,6 +410,8 @@ void __init ath79_register_wmac(u8 *cal_
269 qca953x_wmac_setup();
270 else if (soc_is_qca955x())
271 qca955x_wmac_setup();
272 + else if (soc_is_qca956x())
273 + qca956x_wmac_setup();
274 else
275 BUG();
276
277 --- a/arch/mips/ath79/early_printk.c
278 +++ b/arch/mips/ath79/early_printk.c
279 @@ -117,6 +117,8 @@ static void prom_putchar_init(void)
280 case REV_ID_MAJOR_QCA9533:
281 case REV_ID_MAJOR_QCA9556:
282 case REV_ID_MAJOR_QCA9558:
283 + case REV_ID_MAJOR_TP9343:
284 + case REV_ID_MAJOR_QCA9561:
285 _prom_putchar = prom_putchar_ar71xx;
286 break;
287
288 --- a/arch/mips/ath79/gpio.c
289 +++ b/arch/mips/ath79/gpio.c
290 @@ -148,7 +148,8 @@ static void __iomem *ath79_gpio_get_func
291 soc_is_ar913x() ||
292 soc_is_ar933x())
293 reg = AR71XX_GPIO_REG_FUNC;
294 - else if (soc_is_ar934x())
295 + else if (soc_is_ar934x() ||
296 + soc_is_qca956x())
297 reg = AR934X_GPIO_REG_FUNC;
298 else
299 BUG();
300 @@ -228,12 +229,15 @@ void __init ath79_gpio_init(void)
301 ath79_gpio_count = QCA953X_GPIO_COUNT;
302 else if (soc_is_qca955x())
303 ath79_gpio_count = QCA955X_GPIO_COUNT;
304 + else if (soc_is_qca956x())
305 + ath79_gpio_count = QCA956X_GPIO_COUNT;
306 else
307 BUG();
308
309 ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
310 ath79_gpio_chip.ngpio = ath79_gpio_count;
311 - if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
312 + if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x() ||
313 + soc_is_qca956x()) {
314 ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
315 ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
316 }
317 --- a/arch/mips/ath79/irq.c
318 +++ b/arch/mips/ath79/irq.c
319 @@ -107,7 +107,8 @@ static void __init ath79_misc_irq_init(v
320 soc_is_ar933x() ||
321 soc_is_ar934x() ||
322 soc_is_qca953x() ||
323 - soc_is_qca955x())
324 + soc_is_qca955x() ||
325 + soc_is_qca956x())
326 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
327 else
328 BUG();
329 @@ -236,6 +237,99 @@ static void qca955x_irq_init(void)
330 irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
331 }
332
333 +static void qca956x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
334 +{
335 + u32 status;
336 +
337 + disable_irq_nosync(irq);
338 +
339 + status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
340 + status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
341 +
342 + if (status == 0) {
343 + spurious_interrupt();
344 + goto enable;
345 + }
346 +
347 + if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
348 + /* TODO: flush DDR? */
349 + generic_handle_irq(ATH79_IP2_IRQ(0));
350 + }
351 +
352 + if (status & QCA956X_EXT_INT_WMAC_ALL) {
353 + /* TODO: flsuh DDR? */
354 + generic_handle_irq(ATH79_IP2_IRQ(1));
355 + }
356 +
357 +enable:
358 + enable_irq(irq);
359 +}
360 +
361 +static void qca956x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
362 +{
363 + u32 status;
364 +
365 + disable_irq_nosync(irq);
366 +
367 + status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
368 + status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
369 + QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
370 +
371 + if (status == 0) {
372 + spurious_interrupt();
373 + goto enable;
374 + }
375 +
376 + if (status & QCA956X_EXT_INT_USB1) {
377 + /* TODO: flush DDR? */
378 + generic_handle_irq(ATH79_IP3_IRQ(0));
379 + }
380 +
381 + if (status & QCA956X_EXT_INT_USB2) {
382 + /* TODO: flush DDR? */
383 + generic_handle_irq(ATH79_IP3_IRQ(1));
384 + }
385 +
386 + if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
387 + /* TODO: flush DDR? */
388 + generic_handle_irq(ATH79_IP3_IRQ(2));
389 + }
390 +
391 +enable:
392 + enable_irq(irq);
393 +}
394 +
395 +static void qca956x_enable_timer_cb(void) {
396 + u32 misc;
397 +
398 + misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
399 + misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
400 + ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
401 +}
402 +
403 +static void qca956x_irq_init(void)
404 +{
405 + int i;
406 +
407 + for (i = ATH79_IP2_IRQ_BASE;
408 + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
409 + irq_set_chip_and_handler(i, &dummy_irq_chip,
410 + handle_level_irq);
411 +
412 + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
413 +
414 + for (i = ATH79_IP3_IRQ_BASE;
415 + i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
416 + irq_set_chip_and_handler(i, &dummy_irq_chip,
417 + handle_level_irq);
418 +
419 + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
420 +
421 + /* QCA956x timer init workaround has to be applied right before setting
422 + * up the clock. Else, there will be no jiffies */
423 + late_time_init = &qca956x_enable_timer_cb;
424 +}
425 +
426 asmlinkage void plat_irq_dispatch(void)
427 {
428 unsigned long pending;
429 @@ -359,6 +453,9 @@ void __init arch_init_irq(void)
430 } else if (soc_is_qca955x()) {
431 ath79_ip2_handler = ath79_default_ip2_handler;
432 ath79_ip3_handler = ath79_default_ip3_handler;
433 + } else if (soc_is_qca956x()) {
434 + ath79_ip2_handler = ath79_default_ip2_handler;
435 + ath79_ip3_handler = ath79_default_ip3_handler;
436 } else {
437 BUG();
438 }
439 @@ -371,4 +468,6 @@ void __init arch_init_irq(void)
440 ar934x_ip2_irq_init();
441 else if (soc_is_qca955x())
442 qca955x_irq_init();
443 + else if (soc_is_qca956x())
444 + qca956x_irq_init();
445 }
446 --- a/arch/mips/ath79/Kconfig
447 +++ b/arch/mips/ath79/Kconfig
448 @@ -1165,6 +1165,12 @@ config SOC_QCA955X
449 select PCI_AR724X if PCI
450 def_bool n
451
452 +config SOC_QCA956X
453 + select USB_ARCH_HAS_EHCI
454 + select HW_HAS_PCI
455 + select PCI_AR724X if PCI
456 + def_bool n
457 +
458 config ATH79_DEV_M25P80
459 select ATH79_DEV_SPI
460 def_bool n
461 @@ -1202,7 +1208,7 @@ config ATH79_DEV_USB
462 def_bool n
463
464 config ATH79_DEV_WMAC
465 - depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
466 + depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
467 def_bool n
468
469 config ATH79_NVRAM
470 --- a/arch/mips/ath79/pci.c
471 +++ b/arch/mips/ath79/pci.c
472 @@ -68,6 +68,21 @@ static const struct ath79_pci_irq qca955
473 },
474 };
475
476 +static const struct ath79_pci_irq qca956x_pci_irq_map[] __initconst = {
477 + {
478 + .bus = 0,
479 + .slot = 0,
480 + .pin = 1,
481 + .irq = ATH79_PCI_IRQ(0),
482 + },
483 + {
484 + .bus = 1,
485 + .slot = 0,
486 + .pin = 1,
487 + .irq = ATH79_PCI_IRQ(1),
488 + },
489 +};
490 +
491 int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
492 {
493 int irq = -1;
494 @@ -86,6 +101,9 @@ int __init pcibios_map_irq(const struct
495 } else if (soc_is_qca955x()) {
496 ath79_pci_irq_map = qca955x_pci_irq_map;
497 ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
498 + } else if (soc_is_qca9561()) {
499 + ath79_pci_irq_map = qca956x_pci_irq_map;
500 + ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
501 } else {
502 pr_crit("pci %s: invalid irq map\n",
503 pci_name((struct pci_dev *) dev));
504 @@ -303,6 +321,15 @@ int __init ath79_register_pci(void)
505 QCA955X_PCI_MEM_SIZE,
506 1,
507 ATH79_IP3_IRQ(2));
508 + } else if (soc_is_qca9561()) {
509 + pdev = ath79_register_pci_ar724x(0,
510 + QCA956X_PCI_CFG_BASE1,
511 + QCA956X_PCI_CTRL_BASE1,
512 + QCA956X_PCI_CRP_BASE1,
513 + QCA956X_PCI_MEM_BASE1,
514 + QCA956X_PCI_MEM_SIZE,
515 + 1,
516 + ATH79_IP3_IRQ(2));
517 } else {
518 /* No PCI support */
519 return -ENODEV;
520 --- a/arch/mips/ath79/setup.c
521 +++ b/arch/mips/ath79/setup.c
522 @@ -170,15 +170,30 @@ static void __init ath79_detect_sys_type
523 rev = id & QCA955X_REV_ID_REVISION_MASK;
524 break;
525
526 + case REV_ID_MAJOR_TP9343:
527 + ath79_soc = ATH79_SOC_TP9343;
528 + chip = "9343";
529 + rev = id & QCA956X_REV_ID_REVISION_MASK;
530 + break;
531 +
532 + case REV_ID_MAJOR_QCA9561:
533 + ath79_soc = ATH79_SOC_QCA9561;
534 + chip = "9561";
535 + rev = id & QCA956X_REV_ID_REVISION_MASK;
536 + break;
537 +
538 default:
539 panic("ath79: unknown SoC, id:0x%08x", id);
540 }
541
542 ath79_soc_rev = rev;
543
544 - if (soc_is_qca953x() || soc_is_qca955x())
545 + if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561())
546 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
547 chip, rev);
548 + else if (soc_is_tp9343())
549 + sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
550 + chip, rev);
551 else
552 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
553 pr_info("SoC: %s\n", ath79_sys_type);
554 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
555 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
556 @@ -131,6 +131,23 @@
557 #define QCA955X_NFC_BASE 0x1b800200
558 #define QCA955X_NFC_SIZE 0xb8
559
560 +#define QCA956X_PCI_MEM_BASE1 0x12000000
561 +#define QCA956X_PCI_MEM_SIZE 0x02000000
562 +#define QCA956X_PCI_CFG_BASE1 0x16000000
563 +#define QCA956X_PCI_CFG_SIZE 0x1000
564 +#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
565 +#define QCA956X_PCI_CRP_SIZE 0x1000
566 +#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
567 +#define QCA956X_PCI_CTRL_SIZE 0x100
568 +
569 +#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
570 +#define QCA956X_WMAC_SIZE 0x20000
571 +#define QCA956X_EHCI0_BASE 0x1b000000
572 +#define QCA956X_EHCI1_BASE 0x1b400000
573 +#define QCA956X_EHCI_SIZE 0x200
574 +#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
575 +#define QCA956X_GMAC_SIZE 0x64
576 +
577 #define AR9300_OTP_BASE 0x14000
578 #define AR9300_OTP_STATUS 0x15f18
579 #define AR9300_OTP_STATUS_TYPE 0x7
580 @@ -356,6 +373,49 @@
581 #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
582 #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
583
584 +#define QCA956X_PLL_CPU_CONFIG_REG 0x00
585 +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04
586 +#define QCA956X_PLL_DDR_CONFIG_REG 0x08
587 +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
588 +#define QCA956X_PLL_CLK_CTRL_REG 0x10
589 +
590 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
591 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
592 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
593 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
594 +
595 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
596 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
597 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
598 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff
599 +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
600 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
601 +
602 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
603 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
604 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
605 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
606 +
607 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
608 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
609 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
610 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff
611 +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
612 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
613 +
614 +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
615 +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
616 +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
617 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
618 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
619 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
620 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
621 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
622 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
623 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
624 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
625 +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
626 +
627 /*
628 * USB_CONFIG block
629 */
630 @@ -403,6 +463,11 @@
631 #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
632 #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
633
634 +#define QCA956X_RESET_REG_RESET_MODULE 0x1c
635 +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0
636 +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac
637 +
638 +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
639 #define MISC_INT_ETHSW BIT(12)
640 #define MISC_INT_TIMER4 BIT(10)
641 #define MISC_INT_TIMER3 BIT(9)
642 @@ -551,6 +616,8 @@
643
644 #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
645
646 +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
647 +
648 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
649 #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
650 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
651 @@ -600,6 +667,37 @@
652 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
653 QCA955X_EXT_INT_PCIE_RC2_INT3)
654
655 +#define QCA956X_EXT_INT_WMAC_MISC BIT(0)
656 +#define QCA956X_EXT_INT_WMAC_TX BIT(1)
657 +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
658 +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
659 +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
660 +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
661 +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
662 +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
663 +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
664 +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
665 +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
666 +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
667 +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
668 +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
669 +#define QCA956X_EXT_INT_USB1 BIT(24)
670 +#define QCA956X_EXT_INT_USB2 BIT(28)
671 +
672 +#define QCA956X_EXT_INT_WMAC_ALL \
673 + (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
674 + QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
675 +
676 +#define QCA956X_EXT_INT_PCIE_RC1_ALL \
677 + (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
678 + QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
679 + QCA956X_EXT_INT_PCIE_RC1_INT3)
680 +
681 +#define QCA956X_EXT_INT_PCIE_RC2_ALL \
682 + (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
683 + QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
684 + QCA956X_EXT_INT_PCIE_RC2_INT3)
685 +
686 #define REV_ID_MAJOR_MASK 0xfff0
687 #define REV_ID_MAJOR_AR71XX 0x00a0
688 #define REV_ID_MAJOR_AR913X 0x00b0
689 @@ -614,6 +712,8 @@
690 #define REV_ID_MAJOR_QCA9533 0x0140
691 #define REV_ID_MAJOR_QCA9556 0x0130
692 #define REV_ID_MAJOR_QCA9558 0x1130
693 +#define REV_ID_MAJOR_TP9343 0x0150
694 +#define REV_ID_MAJOR_QCA9561 0x1150
695
696 #define AR71XX_REV_ID_MINOR_MASK 0x3
697 #define AR71XX_REV_ID_MINOR_AR7130 0x0
698 @@ -638,6 +738,8 @@
699
700 #define QCA955X_REV_ID_REVISION_MASK 0xf
701
702 +#define QCA956X_REV_ID_REVISION_MASK 0xf
703 +
704 /*
705 * SPI block
706 */
707 @@ -683,6 +785,19 @@
708 #define AR934X_GPIO_REG_OUT_FUNC5 0x40
709 #define AR934X_GPIO_REG_FUNC 0x6c
710
711 +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
712 +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
713 +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
714 +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38
715 +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c
716 +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40
717 +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44
718 +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50
719 +#define QCA956X_GPIO_REG_FUNC 0x6c
720 +
721 +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32
722 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33
723 +
724 #define AR71XX_GPIO_COUNT 16
725 #define AR7240_GPIO_COUNT 18
726 #define AR7241_GPIO_COUNT 20
727 @@ -691,6 +806,7 @@
728 #define AR934X_GPIO_COUNT 23
729 #define QCA953X_GPIO_COUNT 24
730 #define QCA955X_GPIO_COUNT 24
731 +#define QCA956X_GPIO_COUNT 23
732
733 /*
734 * SRIF block
735 --- a/arch/mips/include/asm/mach-ath79/ath79.h
736 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
737 @@ -35,6 +35,8 @@ enum ath79_soc_type {
738 ATH79_SOC_QCA9533,
739 ATH79_SOC_QCA9556,
740 ATH79_SOC_QCA9558,
741 + ATH79_SOC_TP9343,
742 + ATH79_SOC_QCA9561,
743 };
744
745 extern enum ath79_soc_type ath79_soc;
746 @@ -126,6 +128,21 @@ static inline int soc_is_qca955x(void)
747 return soc_is_qca9556() || soc_is_qca9558();
748 }
749
750 +static inline int soc_is_tp9343(void)
751 +{
752 + return ath79_soc == ATH79_SOC_TP9343;
753 +}
754 +
755 +static inline int soc_is_qca9561(void)
756 +{
757 + return ath79_soc == ATH79_SOC_QCA9561;
758 +}
759 +
760 +static inline int soc_is_qca956x(void)
761 +{
762 + return soc_is_tp9343() || soc_is_qca9561();
763 +}
764 +
765 extern void __iomem *ath79_ddr_base;
766 extern void __iomem *ath79_gpio_base;
767 extern void __iomem *ath79_pll_base;
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