target/linux/ar71xx/patches-3.18/605-MIPS-ath79-db120-fixes.patch

   1 --- a/arch/mips/ath79/mach-db120.c
   2 +++ b/arch/mips/ath79/mach-db120.c
   3 @@ -2,7 +2,7 @@
   4   * Atheros DB120 reference board support
   5   *
   6   * Copyright (c) 2011 Qualcomm Atheros
   7 - * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
   8 + * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   9   *
  10   * Permission to use, copy, modify, and/or distribute this software for any
  11   * purpose with or without fee is hereby granted, provided that the above
  12 @@ -19,16 +19,26 @@
  13   */
  14
  15  #include <linux/pci.h>
  16 +#include <linux/phy.h>
  17 +#include <linux/platform_device.h>
  18  #include <linux/ath9k_platform.h>
  19 +#include <linux/ar8216_platform.h>
  20
  21 -#include "machtypes.h"
  22 +#include <asm/mach-ath79/ar71xx_regs.h>
  23 +
  24 +#include "common.h"
  25 +#include "dev-ap9x-pci.h"
  26 +#include "dev-eth.h"
  27  #include "dev-gpio-buttons.h"
  28  #include "dev-leds-gpio.h"
  29 +#include "dev-m25p80.h"
  30 +#include "dev-nfc.h"
  31  #include "dev-spi.h"
  32  #include "dev-usb.h"
  33  #include "dev-wmac.h"
  34 -#include "pci.h"
  35 +#include "machtypes.h"
  36
  37 +#define DB120_GPIO_LED_USB             11
  38  #define DB120_GPIO_LED_WLAN_5G         12
  39  #define DB120_GPIO_LED_WLAN_2G         13
  40  #define DB120_GPIO_LED_STATUS          14
  41 @@ -39,8 +49,10 @@
  42  #define DB120_KEYS_POLL_INTERVAL       20      /* msecs */
  43  #define DB120_KEYS_DEBOUNCE_INTERVAL   (3 * DB120_KEYS_POLL_INTERVAL)
  44
  45 -#define DB120_WMAC_CALDATA_OFFSET 0x1000
  46 -#define DB120_PCIE_CALDATA_OFFSET 0x5000
  47 +#define DB120_MAC0_OFFSET              0
  48 +#define DB120_MAC1_OFFSET              6
  49 +#define DB120_WMAC_CALDATA_OFFSET      0x1000
  50 +#define DB120_PCIE_CALDATA_OFFSET      0x5000
  51
  52  static struct gpio_led db120_leds_gpio[] __initdata = {
  53         {
  54 @@ -63,6 +75,11 @@ static struct gpio_led db120_leds_gpio[]
  55                 .gpio           = DB120_GPIO_LED_WLAN_2G,
  56                 .active_low     = 1,
  57         },
  58 +       {
  59 +               .name           = "db120:green:usb",
  60 +               .gpio           = DB120_GPIO_LED_USB,
  61 +               .active_low     = 1,
  62 +       }
  63  };
  64
  65  static struct gpio_keys_button db120_gpio_keys[] __initdata = {
  66 @@ -76,60 +93,85 @@ static struct gpio_keys_button db120_gpi
  67         },
  68  };
  69
  70 +static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = {
  71 +       .mode = AR8327_PAD_MAC_RGMII,
  72 +       .txclk_delay_en = true,
  73 +       .rxclk_delay_en = true,
  74 +       .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  75 +       .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  76 +};
  77 +
  78 -static struct spi_board_info db120_spi_info[] = {
  79 -       {
  80 -               .bus_num        = 0,
  81 -               .chip_select    = 0,
  82 -               .max_speed_hz   = 25000000,
  83 -               .modalias       = "s25sl064a",
  84 -       }
  85 +static struct ar8327_led_cfg db120_ar8327_led_cfg = {
  86 +       .led_ctrl0 = 0x00000000,
  87 +       .led_ctrl1 = 0xc737c737,
  88 +       .led_ctrl2 = 0x00000000,
  89 +       .led_ctrl3 = 0x00c30c00,
  90 +       .open_drain = true,
  91  };
  92
  93 -static struct ath79_spi_platform_data db120_spi_data = {
  94 -       .bus_num        = 0,
  95 -       .num_chipselect = 1,
  96 +static struct ar8327_platform_data db120_ar8327_data = {
  97 +       .pad0_cfg = &db120_ar8327_pad0_cfg,
  98 +       .port0_cfg = {
  99 +               .force_link = 1,
 100 +               .speed = AR8327_PORT_SPEED_1000,
 101 +               .duplex = 1,
 102 +               .txpause = 1,
 103 +               .rxpause = 1,
 104 +       },
 105 +       .led_cfg = &db120_ar8327_led_cfg,
 106  };
 107
 108 -#ifdef CONFIG_PCI
 109 -static struct ath9k_platform_data db120_ath9k_data;
 110 -
 111 -static int db120_pci_plat_dev_init(struct pci_dev *dev)
 112 -{
 113 -       switch (PCI_SLOT(dev->devfn)) {
 114 -       case 0:
 115 -               dev->dev.platform_data = &db120_ath9k_data;
 116 -               break;
 117 -       }
 118 -
 119 -       return 0;
 120 -}
 121 -
 122 -static void __init db120_pci_init(u8 *eeprom)
 123 -{
 124 -       memcpy(db120_ath9k_data.eeprom_data, eeprom,
 125 -              sizeof(db120_ath9k_data.eeprom_data));
 126 -
 127 -       ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
 128 -       ath79_register_pci();
 129 -}
 130 -#else
 131 -static inline void db120_pci_init(u8 *eeprom) {}
 132 -#endif /* CONFIG_PCI */
 133 +static struct mdio_board_info db120_mdio0_info[] = {
 134 +       {
 135 +               .bus_id = "ag71xx-mdio.0",
 136 +               .phy_addr = 0,
 137 +               .platform_data = &db120_ar8327_data,
 138 +       },
 139 +};
 140
 141  static void __init db120_setup(void)
 142  {
 143         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 144
 145 +       ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
 146 +       ath79_register_m25p80(NULL);
 147 +
 148         ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
 149                                  db120_leds_gpio);
 150         ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
 151                                         ARRAY_SIZE(db120_gpio_keys),
 152                                         db120_gpio_keys);
 153 -       ath79_register_spi(&db120_spi_data, db120_spi_info,
 154 -                          ARRAY_SIZE(db120_spi_info));
 155         ath79_register_usb();
 156         ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
 157 -       db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
 158 +       ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
 159 +
 160 +       ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
 161 +                                  AR934X_ETH_CFG_SW_ONLY_MODE);
 162 +
 163 +       ath79_register_mdio(1, 0x0);
 164 +       ath79_register_mdio(0, 0x0);
 165 +
 166 +       ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
 167 +
 168 +       mdiobus_register_board_info(db120_mdio0_info,
 169 +                                   ARRAY_SIZE(db120_mdio0_info));
 170 +
 171 +       /* GMAC0 is connected to an AR8327 switch */
 172 +       ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 173 +       ath79_eth0_data.phy_mask = BIT(0);
 174 +       ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 175 +       ath79_eth0_pll_data.pll_1000 = 0x06000000;
 176 +       ath79_register_eth(0);
 177 +
 178 +       /* GMAC1 is connected to the internal switch */
 179 +       ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0);
 180 +       ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
 181 +       ath79_eth1_data.speed = SPEED_1000;
 182 +       ath79_eth1_data.duplex = DUPLEX_FULL;
 183 +
 184 +       ath79_register_eth(1);
 185 +
 186 +       ath79_register_nfc();
 187  }
 188
 189  MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
 190 --- a/arch/mips/ath79/Kconfig
 191 +++ b/arch/mips/ath79/Kconfig
 192 @@ -43,9 +43,12 @@ config ATH79_MACH_AP81
 193  config ATH79_MACH_DB120
 194         bool "Atheros DB120 reference board"
 195         select SOC_AR934X
 196 +       select ATH79_DEV_AP9X_PCI if PCI
 197 +       select ATH79_DEV_ETH
 198         select ATH79_DEV_GPIO_BUTTONS
 199         select ATH79_DEV_LEDS_GPIO
 200 -       select ATH79_DEV_SPI
 201 +       select ATH79_DEV_M25P80
 202 +       select ATH79_DEV_NFC
 203         select ATH79_DEV_USB
 204         select ATH79_DEV_WMAC
 205         help