target/linux/bcm53xx/patches-3.18/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch

   1 From 26023cdfacaf116545b1087b9d1fe50dc6fbda10 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
   3 Date: Wed, 24 Sep 2014 22:14:07 +0200
   4 Subject: [PATCH] ARM: BCM5301X: Disable MMU and Dcache for decompression
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Without this fix kernel was randomly hanging in ~25% of tries during
  10 early init. Hangs used to happen at random places in the start_kernel.
  11
  12 Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
  13 ---
  14  arch/arm/boot/compressed/Makefile                |   5 +
  15  arch/arm/boot/compressed/head-bcm_5301x-mpcore.S |  37 +++++++
  16  arch/arm/boot/compressed/mpcore_cache.S          | 118 +++++++++++++++++++++++
  17  3 files changed, 160 insertions(+)
  18  create mode 100644 arch/arm/boot/compressed/head-bcm_5301x-mpcore.S
  19  create mode 100644 arch/arm/boot/compressed/mpcore_cache.S
  20
  21 --- a/arch/arm/boot/compressed/Makefile
  22 +++ b/arch/arm/boot/compressed/Makefile
  23 @@ -46,6 +46,11 @@ ifeq ($(CONFIG_ARCH_ACORN),y)
  24  OBJS           += ll_char_wr.o font.o
  25  endif
  26
  27 +ifeq ($(CONFIG_ARCH_BCM_5301X),y)
  28 +OBJS           += head-bcm_5301x-mpcore.o
  29 +OBJS           += mpcore_cache.o
  30 +endif
  31 +
  32  ifeq ($(CONFIG_ARCH_SA1100),y)
  33  OBJS           += head-sa1100.o
  34  endif
  35 --- /dev/null
  36 +++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S
  37 @@ -0,0 +1,37 @@
  38 +/*
  39 + *
  40 + * Platform specific tweaks.  This is merged into head.S by the linker.
  41 + *
  42 + */
  43 +
  44 +#include <linux/linkage.h>
  45 +#include <asm/assembler.h>
  46 +#include <asm/cp15.h>
  47 +
  48 +               .section        ".start", "ax"
  49 +
  50 +/*
  51 + * This code section is spliced into the head code by the linker
  52 + */
  53 +
  54 +__plat_uncompress_start:
  55 +
  56 +       @ Preserve r8/r7 i.e. kernel entry values
  57 +       mov     r12, r8
  58 +
  59 +       @ Clear MMU enable and Dcache enable bits
  60 +       mrc     p15, 0, r0, c1, c0, 0           @ Read SCTLR
  61 +       bic     r0, #CR_C|CR_M
  62 +       mcr     p15, 0, r0, c1, c0, 0           @ Write SCTLR
  63 +       nop
  64 +
  65 +       @ Call the cache invalidation routine
  66 +       bl      v7_all_dcache_invalidate
  67 +       nop
  68 +       mov     r0,#0
  69 +       ldr     r3, =0x19022000                 @ L2 cache controller, control reg
  70 +       str     r0, [r3, #0x100]                @ Disable L2 cache
  71 +       nop
  72 +
  73 +       @ Restore
  74 +       mov     r8, r12
  75 --- /dev/null
  76 +++ b/arch/arm/boot/compressed/mpcore_cache.S
  77 @@ -0,0 +1,118 @@
  78 +/*****************************************************************************
  79 +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
  80 +*
  81 +* Unless you and Broadcom execute a separate written software license
  82 +* agreement governing use of this software, this software is licensed to you
  83 +* under the terms of the GNU General Public License version 2, available at
  84 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
  85 +*
  86 +* Notwithstanding the above, under no circumstances may you combine this
  87 +* software in any way with any other Broadcom software provided under a
  88 +* license other than the GPL, without Broadcom's express prior written
  89 +* consent.
  90 +*****************************************************************************/
  91 +
  92 +#include <linux/linkage.h>
  93 +#include <linux/init.h>
  94 +
  95 +       __INIT
  96 +
  97 +/*
  98 + * v7_l1_cache_invalidate
  99 + *
 100 + * Invalidate contents of L1 cache without flushing its contents
 101 + * into outer cache and memory. This is needed when the contents
 102 + * of the cache are unpredictable after power-up.
 103 + *
 104 + * corrupts r0-r6
 105 + */
 106 +
 107 +ENTRY(v7_l1_cache_invalidate)
 108 +       mov     r0, #0
 109 +       mcr     p15, 2, r0, c0, c0, 0   @ set cache level to 1
 110 +       mrc     p15, 1, r0, c0, c0, 0   @ read CLIDR
 111 +
 112 +       ldr     r1, =0x7fff
 113 +       and     r2, r1, r0, lsr #13     @ get max # of index size
 114 +
 115 +       ldr     r1, =0x3ff
 116 +       and     r3, r1, r0, lsr #3      @ NumWays - 1
 117 +       add     r2, r2, #1              @ NumSets
 118 +
 119 +       and     r0, r0, #0x7
 120 +       add     r0, r0, #4              @ SetShift
 121 +
 122 +       clz     r1, r3                  @ WayShift
 123 +       add     r4, r3, #1              @ NumWays
 124 +1:     sub     r2, r2, #1              @ NumSets--
 125 +       mov     r3, r4                  @ Temp = NumWays
 126 +2:     subs    r3, r3, #1              @ Temp--
 127 +       mov     r5, r3, lsl r1
 128 +       mov     r6, r2, lsl r0
 129 +       orr     r5, r5, r6              @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
 130 +       mcr     p15, 0, r5, c7, c6, 2   @ Invalidate line
 131 +       bgt     2b
 132 +       cmp     r2, #0
 133 +       bgt     1b
 134 +       dsb
 135 +       mov     r0,#0
 136 +       mcr     p15,0,r0,c7,c5,0        /* Invalidate icache */
 137 +       isb
 138 +       mov     pc, lr
 139 +ENDPROC(v7_l1_cache_invalidate)
 140 +
 141 +/*
 142 + * v7_all_dcache_invalidate
 143 + *
 144 + * Invalidate without flushing the contents of all cache levels
 145 + * accesible by the current processor core.
 146 + * This is useful when the contents of cache memory are undetermined
 147 + * at power-up.
 148 + *     Corrupted registers: r0-r7, r9-r11
 149 + *
 150 + * Based on cache-v7.S: v7_flush_dcache_all()
 151 + */
 152 +
 153 +ENTRY(v7_all_dcache_invalidate)
 154 +       mrc     p15, 1, r0, c0, c0, 1   @ read clidr
 155 +       ands    r3, r0, #0x7000000      @ extract loc from clidr
 156 +       mov     r3, r3, lsr #23         @ left align loc bit field
 157 +       beq     finished                @ if loc is 0, then no need to clean
 158 +       mov     r10, #0                 @ start clean at cache level 0
 159 +loop1:
 160 +       add     r2, r10, r10, lsr #1    @ work out 3x current cache level
 161 +       mov     r1, r0, lsr r2          @ extract cache type bits from clidr
 162 +       and     r1, r1, #7              @ mask of bits for current cache only
 163 +       cmp     r1, #2                  @ see what cache we have at this level
 164 +       blt     skip                    @ skip if no cache, or just i-cache
 165 +       mcr     p15, 2, r10, c0, c0, 0  @ select current cache level in cssr
 166 +       isb                             @ isb to sych the new cssr&csidr
 167 +       mrc     p15, 1, r1, c0, c0, 0   @ read the new csidr
 168 +       and     r2, r1, #7              @ extract the length of the cache lines
 169 +       add     r2, r2, #4              @ add 4 (line length offset)
 170 +       ldr     r4, =0x3ff
 171 +       ands    r4, r4, r1, lsr #3      @ find maximum number on the way size
 172 +       clz     r5, r4                  @ find bit pos of way size increment
 173 +       ldr     r7, =0x7fff
 174 +       ands    r7, r7, r1, lsr #13     @ extract max number of the index size
 175 +loop2:
 176 +       mov     r9, r4                  @ create working copy of max way size
 177 +loop3:
 178 +       orr     r11, r10, r9, lsl r5    @ factor way and cache number into r11
 179 +       orr     r11, r11, r7, lsl r2    @ factor index number into r11
 180 +       mcr     p15, 0, r11, c7, c6, 2  @ Invalidate line
 181 +       subs    r9, r9, #1              @ decrement the way
 182 +       bge     loop3
 183 +       subs    r7, r7, #1              @ decrement the index
 184 +       bge     loop2
 185 +skip:
 186 +       add     r10, r10, #2            @ increment cache number
 187 +       cmp     r3, r10
 188 +       bgt     loop1
 189 +finished:
 190 +       mov     r10, #0                 @ swith back to cache level 0
 191 +       mcr     p15, 2, r10, c0, c0, 0  @ select current cache level in cssr
 192 +       dsb
 193 +       isb
 194 +       mov     pc, lr
 195 +ENDPROC(v7_all_dcache_invalidate)