target/linux/bcm53xx/patches-4.1/152-PCI-iproc-Add-iProc-PCIe-MSI-device-tree-binding.patch

   1 From 96b40de5e36ec479dabb88500f1830a87818a809 Mon Sep 17 00:00:00 2001
   2 From: Ray Jui <rjui@broadcom.com>
   3 Date: Mon, 16 Nov 2015 17:57:33 -0800
   4 Subject: [PATCH 152/154] PCI: iproc: Add iProc PCIe MSI device tree binding
   5
   6 This patch updates the iProc PCIe device tree bindings with added
   7 binding information for MSI
   8
   9 Signed-off-by: Ray Jui <rjui@broadcom.com>
  10 Reviewed-by: Anup Patel <anup.patel@broadcom.com>
  11 Reviewed-by: Vikram Prakash <vikramp@broadcom.com>
  12 Reviewed-by: Scott Branden <sbranden@broadcom.com>
  13 ---
  14  .../devicetree/bindings/pci/brcm,iproc-pcie.txt    | 35 ++++++++++++++++++++++
  15  1 file changed, 35 insertions(+)
  16
  17 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
  18 +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
  19 @@ -35,6 +35,28 @@ Optional:
  20  - brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to
  21  increase the outbound window size
  22
  23 +MSI support (optional):
  24 +
  25 +For older platforms without MSI integrated in the GIC, iProc PCIe core provides
  26 +an event queue based MSI support. The iProc MSI uses host memories to store
  27 +MSI posted writes in the event queues
  28 +
  29 +- msi-parent: Link to the device node of the MSI controller. On newer iProc
  30 +platforms, the MSI controller may be gicv2m or gicv3-its. On older iProc
  31 +platforms without MSI support in its interrupt controller, one may use the
  32 +event queue based MSI support integrated within the iProc PCIe core
  33 +
  34 +When the iProc event queue based MSI is used, one needs to define the
  35 +following properties in the MSI device node:
  36 +- compatible: Must be "brcm,iproc-msi"
  37 +- msi-controller: claims itself as an MSI controller
  38 +- interrupt-parent: Link to its parent interrupt device
  39 +- interrupts: List of interrupt IDs from its parent interrupt device
  40 +
  41 +Optional properties:
  42 +- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that
  43 +require the interrupt enable registers to be set explicitly to enable MSI
  44 +
  45  Example:
  46         pcie0: pcie@18012000 {
  47                 compatible = "brcm,iproc-pcie";
  48 @@ -61,6 +83,19 @@ Example:
  49                 brcm,pcie-ob-oarr-size;
  50                 brcm,pcie-ob-axi-offset = <0x00000000>;
  51                 brcm,pcie-ob-window-size = <256>;
  52 +
  53 +               msi-parent = <&msi0>;
  54 +
  55 +               /* iProc event queue based MSI */
  56 +               msi0: msi@18012000 {
  57 +                       compatible = "brcm,iproc-msi";
  58 +                       msi-controller;
  59 +                       interrupt-parent = <&gic>;
  60 +                       interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
  61 +                                    <GIC_SPI 97 IRQ_TYPE_NONE>,
  62 +                                    <GIC_SPI 98 IRQ_TYPE_NONE>,
  63 +                                    <GIC_SPI 99 IRQ_TYPE_NONE>,
  64 +               };
  65         };
  66
  67         pcie1: pcie@18013000 {