target/linux/bcm53xx/patches-4.3/048-clk-iproc-Split-off-dig_filter.patch

   1 From fb9e4932d17ad32786d03cb672fb62f2b337acf5 Mon Sep 17 00:00:00 2001
   2 From: Jon Mason <jonmason@broadcom.com>
   3 Date: Thu, 15 Oct 2015 15:48:29 -0400
   4 Subject: [PATCH 48/50] clk: iproc: Split off dig_filter
   5
   6 The PLL loop filter/gain can be located in a separate register on some
   7 SoCs.  Split these off into a separate variable, so that an offset can
   8 be added if necessary.  Also, make the necessary modifications to the
   9 Cygnus and NSP drivers for this change.
  10
  11 Signed-off-by: Jon Mason <jonmason@broadcom.com>
  12 ---
  13  drivers/clk/bcm/clk-cygnus.c    | 17 +++++++++++------
  14  drivers/clk/bcm/clk-iproc-pll.c | 14 +++++++++-----
  15  drivers/clk/bcm/clk-iproc.h     | 10 +++++++++-
  16  drivers/clk/bcm/clk-nsp.c       | 14 +++++++++-----
  17  4 files changed, 38 insertions(+), 17 deletions(-)
  18
  19 --- a/drivers/clk/bcm/clk-cygnus.c
  20 +++ b/drivers/clk/bcm/clk-cygnus.c
  21 @@ -34,9 +34,11 @@
  22                 { .offset = o, .en_shift = es, .high_shift = hs, \
  23                 .high_width = hw, .low_shift = ls, .low_width = lw }
  24
  25 -#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
  26 -       .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
  27 -       .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
  28 +#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
  29 +       .p_reset_shift = prs }
  30 +
  31 +#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
  32 +       .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas,    \
  33         .ka_width = kaw }
  34
  35  #define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
  36 @@ -56,7 +58,8 @@ static const struct iproc_pll_ctrl genpl
  37         .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
  38                 IPROC_CLK_PLL_NEEDS_SW_CFG,
  39         .aon = AON_VAL(0x0, 2, 1, 0),
  40 -       .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
  41 +       .reset = RESET_VAL(0x0, 11, 10),
  42 +       .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
  43         .sw_ctrl = SW_CTRL_VAL(0x10, 31),
  44         .ndiv_int = REG_VAL(0x10, 20, 10),
  45         .ndiv_frac = REG_VAL(0x10, 0, 20),
  46 @@ -114,7 +117,8 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygn
  47  static const struct iproc_pll_ctrl lcpll0 = {
  48         .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
  49         .aon = AON_VAL(0x0, 2, 5, 4),
  50 -       .reset = RESET_VAL(0x0, 31, 30, 27, 3, 23, 4, 19, 4),
  51 +       .reset = RESET_VAL(0x0, 31, 30),
  52 +       .dig_filter = DF_VAL(0x0, 27, 3, 23, 4, 19, 4),
  53         .sw_ctrl = SW_CTRL_VAL(0x4, 31),
  54         .ndiv_int = REG_VAL(0x4, 16, 10),
  55         .pdiv = REG_VAL(0x4, 26, 4),
  56 @@ -191,7 +195,8 @@ static const struct iproc_pll_ctrl mipip
  57                  IPROC_CLK_NEEDS_READ_BACK,
  58         .aon = AON_VAL(0x0, 4, 17, 16),
  59         .asiu = ASIU_GATE_VAL(0x0, 3),
  60 -       .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4),
  61 +       .reset = RESET_VAL(0x0, 11, 10),
  62 +       .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 4),
  63         .ndiv_int = REG_VAL(0x10, 20, 10),
  64         .ndiv_frac = REG_VAL(0x10, 0, 20),
  65         .pdiv = REG_VAL(0x14, 0, 4),
  66 --- a/drivers/clk/bcm/clk-iproc-pll.c
  67 +++ b/drivers/clk/bcm/clk-iproc-pll.c
  68 @@ -224,13 +224,17 @@ static void __pll_bring_out_reset(struct
  69         u32 val;
  70         const struct iproc_pll_ctrl *ctrl = pll->ctrl;
  71         const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
  72 +       const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter;
  73 +
  74 +       val = readl(pll->pll_base + dig_filter->offset);
  75 +       val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift |
  76 +               bit_mask(dig_filter->kp_width) << dig_filter->kp_shift |
  77 +               bit_mask(dig_filter->ka_width) << dig_filter->ka_shift);
  78 +       val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift |
  79 +              ka << dig_filter->ka_shift;
  80 +       iproc_pll_write(pll, pll->pll_base, dig_filter->offset, val);
  81
  82         val = readl(pll->pll_base + reset->offset);
  83 -       val &= ~(bit_mask(reset->ki_width) << reset->ki_shift |
  84 -                bit_mask(reset->kp_width) << reset->kp_shift |
  85 -                bit_mask(reset->ka_width) << reset->ka_shift);
  86 -       val |=  ki << reset->ki_shift | kp << reset->kp_shift |
  87 -               ka << reset->ka_shift;
  88         val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift;
  89         iproc_pll_write(pll, pll->pll_base, reset->offset, val);
  90  }
  91 --- a/drivers/clk/bcm/clk-iproc.h
  92 +++ b/drivers/clk/bcm/clk-iproc.h
  93 @@ -94,12 +94,19 @@ struct iproc_pll_aon_pwr_ctrl {
  94  };
  95
  96  /*
  97 - * Control of the PLL reset, with Ki, Kp, and Ka parameters
  98 + * Control of the PLL reset
  99   */
 100  struct iproc_pll_reset_ctrl {
 101         unsigned int offset;
 102         unsigned int reset_shift;
 103         unsigned int p_reset_shift;
 104 +};
 105 +
 106 +/*
 107 + * Control of the Ki, Kp, and Ka parameters
 108 + */
 109 +struct iproc_pll_dig_filter_ctrl {
 110 +       unsigned int offset;
 111         unsigned int ki_shift;
 112         unsigned int ki_width;
 113         unsigned int kp_shift;
 114 @@ -129,6 +136,7 @@ struct iproc_pll_ctrl {
 115         struct iproc_pll_aon_pwr_ctrl aon;
 116         struct iproc_asiu_gate asiu;
 117         struct iproc_pll_reset_ctrl reset;
 118 +       struct iproc_pll_dig_filter_ctrl dig_filter;
 119         struct iproc_pll_sw_ctrl sw_ctrl;
 120         struct iproc_clk_reg_op ndiv_int;
 121         struct iproc_clk_reg_op ndiv_frac;
 122 --- a/drivers/clk/bcm/clk-nsp.c
 123 +++ b/drivers/clk/bcm/clk-nsp.c
 124 @@ -26,9 +26,11 @@
 125  #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
 126         .pwr_shift = ps, .iso_shift = is }
 127
 128 -#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
 129 -       .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
 130 -       .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
 131 +#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
 132 +       .p_reset_shift = prs }
 133 +
 134 +#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
 135 +       .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas,    \
 136         .ka_width = kaw }
 137
 138  #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
 139 @@ -43,7 +45,8 @@ CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-arm
 140  static const struct iproc_pll_ctrl genpll = {
 141         .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
 142         .aon = AON_VAL(0x0, 1, 12, 0),
 143 -       .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
 144 +       .reset = RESET_VAL(0x0, 11, 10),
 145 +       .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
 146         .ndiv_int = REG_VAL(0x14, 20, 10),
 147         .ndiv_frac = REG_VAL(0x14, 0, 20),
 148         .pdiv = REG_VAL(0x18, 24, 3),
 149 @@ -99,7 +102,8 @@ CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp
 150  static const struct iproc_pll_ctrl lcpll0 = {
 151         .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
 152         .aon = AON_VAL(0x0, 1, 24, 0),
 153 -       .reset = RESET_VAL(0x0, 23, 22, 16, 3, 12, 4, 19, 4),
 154 +       .reset = RESET_VAL(0x0, 23, 22),
 155 +       .dig_filter = DF_VAL(0x0, 16, 3, 12, 4, 19, 4),
 156         .ndiv_int = REG_VAL(0x4, 20, 8),
 157         .ndiv_frac = REG_VAL(0x4, 0, 20),
 158         .pdiv = REG_VAL(0x4, 28, 3),