target/linux/brcm2708/patches-4.14/950-0355-drm-vc4-Add-some-missing-HVS-register-definitions.patch

   1 From a40aa2492372d46688fc6952c13f38e57ae51a6b Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Wed, 11 Apr 2018 22:49:12 +0200
   4 Subject: [PATCH 355/454] drm/vc4: Add some missing HVS register definitions.
   5
   6 At least the RGBA expand field we should have been setting, because we
   7 aren't expanding correctly for 565 -> 8888.  Other registers are ones
   8 that may be interesting for various projects that have been discussed.
   9
  10 Signed-off-by: Eric Anholt <eric@anholt.net>
  11 Acked-by: Stefan Schake <stschake@gmail.com>
  12 Link: https://patchwork.freedesktop.org/patch/msgid/1523479755-20812-2-git-send-email-stschake@gmail.com
  13 (cherry picked from commit aa808440426f6d163a4f51076132628fee6e1e7d)
  14 ---
  15  drivers/gpu/drm/vc4/vc4_regs.h | 96 ++++++++++++++++++++++++++++++++++
  16  1 file changed, 96 insertions(+)
  17
  18 --- a/drivers/gpu/drm/vc4/vc4_regs.h
  19 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
  20 @@ -359,6 +359,21 @@
  21  #define SCALER_DISPCTRL0                        0x00000040
  22  # define SCALER_DISPCTRLX_ENABLE               BIT(31)
  23  # define SCALER_DISPCTRLX_RESET                        BIT(30)
  24 +/* Generates a single frame when VSTART is seen and stops at the last
  25 + * pixel read from the FIFO.
  26 + */
  27 +# define SCALER_DISPCTRLX_ONESHOT              BIT(29)
  28 +/* Processes a single context in the dlist and then task switch,
  29 + * instead of an entire line.
  30 + */
  31 +# define SCALER_DISPCTRLX_ONECTX               BIT(28)
  32 +/* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */
  33 +# define SCALER_DISPCTRLX_FIFO32               BIT(27)
  34 +/* Turns on output to the DISPSLAVE register instead of the normal
  35 + * FIFO.
  36 + */
  37 +# define SCALER_DISPCTRLX_FIFOREG              BIT(26)
  38 +
  39  # define SCALER_DISPCTRLX_WIDTH_MASK           VC4_MASK(23, 12)
  40  # define SCALER_DISPCTRLX_WIDTH_SHIFT          12
  41  # define SCALER_DISPCTRLX_HEIGHT_MASK          VC4_MASK(11, 0)
  42 @@ -431,6 +446,68 @@
  43   */
  44  # define SCALER_GAMADDR_SRAMENB                        BIT(30)
  45
  46 +#define SCALER_OLEDOFFS                         0x00000080
  47 +/* Clamps R to [16,235] and G/B to [16,240]. */
  48 +# define SCALER_OLEDOFFS_YUVCLAMP               BIT(31)
  49 +
  50 +/* Chooses which display FIFO the matrix applies to. */
  51 +# define SCALER_OLEDOFFS_DISPFIFO_MASK          VC4_MASK(25, 24)
  52 +# define SCALER_OLEDOFFS_DISPFIFO_SHIFT         24
  53 +# define SCALER_OLEDOFFS_DISPFIFO_DISABLED      0
  54 +# define SCALER_OLEDOFFS_DISPFIFO_0             1
  55 +# define SCALER_OLEDOFFS_DISPFIFO_1             2
  56 +# define SCALER_OLEDOFFS_DISPFIFO_2             3
  57 +
  58 +/* Offsets are 8-bit 2s-complement. */
  59 +# define SCALER_OLEDOFFS_RED_MASK               VC4_MASK(23, 16)
  60 +# define SCALER_OLEDOFFS_RED_SHIFT              16
  61 +# define SCALER_OLEDOFFS_GREEN_MASK             VC4_MASK(15, 8)
  62 +# define SCALER_OLEDOFFS_GREEN_SHIFT            8
  63 +# define SCALER_OLEDOFFS_BLUE_MASK              VC4_MASK(7, 0)
  64 +# define SCALER_OLEDOFFS_BLUE_SHIFT             0
  65 +
  66 +/* The coefficients are S0.9 fractions. */
  67 +#define SCALER_OLEDCOEF0                        0x00000084
  68 +# define SCALER_OLEDCOEF0_B_TO_R_MASK           VC4_MASK(29, 20)
  69 +# define SCALER_OLEDCOEF0_B_TO_R_SHIFT          20
  70 +# define SCALER_OLEDCOEF0_B_TO_G_MASK           VC4_MASK(19, 10)
  71 +# define SCALER_OLEDCOEF0_B_TO_G_SHIFT          10
  72 +# define SCALER_OLEDCOEF0_B_TO_B_MASK           VC4_MASK(9, 0)
  73 +# define SCALER_OLEDCOEF0_B_TO_B_SHIFT          0
  74 +
  75 +#define SCALER_OLEDCOEF1                        0x00000088
  76 +# define SCALER_OLEDCOEF1_G_TO_R_MASK           VC4_MASK(29, 20)
  77 +# define SCALER_OLEDCOEF1_G_TO_R_SHIFT          20
  78 +# define SCALER_OLEDCOEF1_G_TO_G_MASK           VC4_MASK(19, 10)
  79 +# define SCALER_OLEDCOEF1_G_TO_G_SHIFT          10
  80 +# define SCALER_OLEDCOEF1_G_TO_B_MASK           VC4_MASK(9, 0)
  81 +# define SCALER_OLEDCOEF1_G_TO_B_SHIFT          0
  82 +
  83 +#define SCALER_OLEDCOEF2                        0x0000008c
  84 +# define SCALER_OLEDCOEF2_R_TO_R_MASK           VC4_MASK(29, 20)
  85 +# define SCALER_OLEDCOEF2_R_TO_R_SHIFT          20
  86 +# define SCALER_OLEDCOEF2_R_TO_G_MASK           VC4_MASK(19, 10)
  87 +# define SCALER_OLEDCOEF2_R_TO_G_SHIFT          10
  88 +# define SCALER_OLEDCOEF2_R_TO_B_MASK           VC4_MASK(9, 0)
  89 +# define SCALER_OLEDCOEF2_R_TO_B_SHIFT          0
  90 +
  91 +/* Slave addresses for DMAing from HVS composition output to other
  92 + * devices.  The top bits are valid only in !FIFO32 mode.
  93 + */
  94 +#define SCALER_DISPSLAVE0                       0x000000c0
  95 +#define SCALER_DISPSLAVE1                       0x000000c9
  96 +#define SCALER_DISPSLAVE2                       0x000000d0
  97 +# define SCALER_DISPSLAVE_ISSUE_VSTART          BIT(31)
  98 +# define SCALER_DISPSLAVE_ISSUE_HSTART          BIT(30)
  99 +/* Set when the current line has been read and an HSTART is required. */
 100 +# define SCALER_DISPSLAVE_EOL                   BIT(26)
 101 +/* Set when the display FIFO is empty. */
 102 +# define SCALER_DISPSLAVE_EMPTY                 BIT(25)
 103 +/* Set when there is RGB data ready to read. */
 104 +# define SCALER_DISPSLAVE_VALID                 BIT(24)
 105 +# define SCALER_DISPSLAVE_RGB_MASK              VC4_MASK(23, 0)
 106 +# define SCALER_DISPSLAVE_RGB_SHIFT             0
 107 +
 108  #define SCALER_GAMDATA                          0x000000e0
 109  #define SCALER_DLIST_START                      0x00002000
 110  #define SCALER_DLIST_SIZE                       0x00004000
 111 @@ -796,6 +873,10 @@ enum hvs_pixel_format {
 112         HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9,
 113         HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10,
 114         HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11,
 115 +       HVS_PIXEL_FORMAT_H264 = 12,
 116 +       HVS_PIXEL_FORMAT_PALETTE = 13,
 117 +       HVS_PIXEL_FORMAT_YUV444_RGB = 14,
 118 +       HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
 119  };
 120
 121  /* Note: the LSB is the rightmost character shown.  Only valid for
 122 @@ -829,12 +910,27 @@ enum hvs_pixel_format {
 123  #define SCALER_CTL0_TILING_128B                        2
 124  #define SCALER_CTL0_TILING_256B_OR_T           3
 125
 126 +#define SCALER_CTL0_ALPHA_MASK                  BIT(19)
 127  #define SCALER_CTL0_HFLIP                       BIT(16)
 128  #define SCALER_CTL0_VFLIP                       BIT(15)
 129
 130 +#define SCALER_CTL0_KEY_MODE_MASK              VC4_MASK(18, 17)
 131 +#define SCALER_CTL0_KEY_MODE_SHIFT             17
 132 +#define SCALER_CTL0_KEY_DISABLED               0
 133 +#define SCALER_CTL0_KEY_LUMA_OR_COMMON_RGB     1
 134 +#define SCALER_CTL0_KEY_MATCH                  2 /* turn transparent */
 135 +#define SCALER_CTL0_KEY_REPLACE                        3 /* replace with value from key mask word 2 */
 136 +
 137  #define SCALER_CTL0_ORDER_MASK                 VC4_MASK(14, 13)
 138  #define SCALER_CTL0_ORDER_SHIFT                        13
 139
 140 +#define SCALER_CTL0_RGBA_EXPAND_MASK           VC4_MASK(12, 11)
 141 +#define SCALER_CTL0_RGBA_EXPAND_SHIFT          11
 142 +#define SCALER_CTL0_RGBA_EXPAND_ZERO           0
 143 +#define SCALER_CTL0_RGBA_EXPAND_LSB            1
 144 +#define SCALER_CTL0_RGBA_EXPAND_MSB            2
 145 +#define SCALER_CTL0_RGBA_EXPAND_ROUND          3
 146 +
 147  #define SCALER_CTL0_SCL1_MASK                  VC4_MASK(10, 8)
 148  #define SCALER_CTL0_SCL1_SHIFT                 8
 149