projects / openwrt / staging / chunkeey.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
kernel: update 3.18 to 3.18.14
[openwrt/staging/chunkeey.git] / target / linux / brcm63xx / patches-3.18 / 341-MIPS-BCM63XX-add-support-for-BCM6318.patch
1 From 60c29522a8c77d96145d965589c56befda7d4c3d Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Sun, 8 Dec 2013 01:24:09 +0100
4 Subject: [PATCH 51/53] MIPS: BCM63XX: add support for BCM6318
5
6 ---
7 arch/mips/bcm63xx/Kconfig | 5 +
8 arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +-
9 arch/mips/bcm63xx/clk.c | 8 +-
10 arch/mips/bcm63xx/cpu.c | 53 +++++++++++
11 arch/mips/bcm63xx/dev-flash.c | 3 +
12 arch/mips/bcm63xx/dev-spi.c | 2 +-
13 arch/mips/bcm63xx/irq.c | 10 ++
14 arch/mips/bcm63xx/prom.c | 2 +-
15 arch/mips/bcm63xx/reset.c | 24 +++++
16 arch/mips/bcm63xx/setup.c | 5 +-
17 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 107 ++++++++++++++++++++++
18 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 75 ++++++++++++++-
19 arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 +
20 13 files changed, 291 insertions(+), 6 deletions(-)
21
22 --- a/arch/mips/bcm63xx/Kconfig
23 +++ b/arch/mips/bcm63xx/Kconfig
24 @@ -18,6 +18,11 @@ config BCM63XX_EHCI
25 select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD
26 select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD
27
28 +config BCM63XX_CPU_6318
29 + bool "support 6318 CPU"
30 + select SYS_HAS_CPU_BMIPS32_3300
31 + select HW_HAS_PCI
32 +
33 config BCM63XX_CPU_6328
34 bool "support 6328 CPU"
35 select SYS_HAS_CPU_BMIPS4350
36 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
37 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
38 @@ -717,7 +717,7 @@ void __init board_prom_init(void)
39 /* read base address of boot chip select (0)
40 * 6328/6362 do not have MPI but boot from a fixed address
41 */
42 - if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
43 + if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
44 val = 0x18000000;
45 } else {
46 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
47 --- a/arch/mips/bcm63xx/clk.c
48 +++ b/arch/mips/bcm63xx/clk.c
49 @@ -252,7 +252,9 @@ static void hsspi_set(struct clk *clk, i
50 {
51 u32 mask;
52
53 - if (BCMCPU_IS_6328())
54 + if (BCMCPU_IS_6318())
55 + mask = CKCTL_6318_HSSPI_EN;
56 + else if (BCMCPU_IS_6328())
57 mask = CKCTL_6328_HSSPI_EN;
58 else if (BCMCPU_IS_6362())
59 mask = CKCTL_6362_HSSPI_EN;
60 @@ -417,12 +419,16 @@ void clk_put(struct clk *clk)
61
62 EXPORT_SYMBOL(clk_put);
63
64 +#define HSSPI_PLL_HZ_6318 250000000
65 #define HSSPI_PLL_HZ_6328 133333333
66 #define HSSPI_PLL_HZ_6362 400000000
67
68 static int __init bcm63xx_clk_init(void)
69 {
70 switch (bcm63xx_get_cpu_id()) {
71 + case BCM6318_CPU_ID:
72 + clk_hsspi.rate = HSSPI_PLL_HZ_6318;
73 + break;
74 case BCM6328_CPU_ID:
75 clk_hsspi.rate = HSSPI_PLL_HZ_6328;
76 break;
77 --- a/arch/mips/bcm63xx/cpu.c
78 +++ b/arch/mips/bcm63xx/cpu.c
79 @@ -41,6 +41,14 @@ static const int bcm3368_irqs[] = {
80 __GEN_CPU_IRQ_TABLE(3368)
81 };
82
83 +static const unsigned long bcm6318_regs_base[] = {
84 + __GEN_CPU_REGS_TABLE(6318)
85 +};
86 +
87 +static const int bcm6318_irqs[] = {
88 + __GEN_CPU_IRQ_TABLE(6318)
89 +};
90 +
91 static const unsigned long bcm6328_regs_base[] = {
92 __GEN_CPU_REGS_TABLE(6328)
93 };
94 @@ -134,6 +142,10 @@ unsigned int bcm63xx_get_memory_size(voi
95 return bcm63xx_memory_size;
96 }
97
98 +#define STRAP_OVERRIDE_BUS_REG 0x0
99 +#define OVERRIDE_BUS_MIPS_FREQ_SHIFT 23
100 +#define OVERRIDE_BUS_MIPS_FREQ_MASK (0x3 << OVERRIDE_BUS_MIPS_FREQ_SHIFT)
101 +
102 static unsigned int detect_cpu_clock(void)
103 {
104 u32 cpu_id = bcm63xx_get_cpu_id();
105 @@ -142,6 +154,28 @@ static unsigned int detect_cpu_clock(voi
106 case BCM3368_CPU_ID:
107 return 300000000;
108
109 + case BCM6318_CPU_ID:
110 + {
111 + unsigned int tmp, mips_pll_fcvo;
112 +
113 + tmp = bcm_readl(BCM_6318_STRAP_BASE + STRAP_OVERRIDE_BUS_REG);
114 +
115 + pr_info("strap_override_bus = %08x\n", tmp);
116 +
117 + mips_pll_fcvo = (tmp & OVERRIDE_BUS_MIPS_FREQ_MASK)
118 + >> OVERRIDE_BUS_MIPS_FREQ_SHIFT;
119 +
120 + switch (mips_pll_fcvo) {
121 + case 0:
122 + return 166000000;
123 + case 1:
124 + return 400000000;
125 + case 2:
126 + return 250000000;
127 + case 3:
128 + return 333000000;
129 + };
130 + }
131 case BCM6328_CPU_ID:
132 {
133 unsigned int tmp, mips_pll_fcvo;
134 @@ -297,6 +331,13 @@ static unsigned int detect_memory_size(v
135 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
136 u32 val;
137
138 + if (BCMCPU_IS_6318()) {
139 + val = bcm_sdram_readl(SDRAM_CFG_REG);
140 + val = val & SDRAM_CFG_6318_SPACE_MASK;
141 + val >>= SDRAM_CFG_6318_SPACE_SHIFT;
142 + return 1 << (val + 20);
143 + }
144 +
145 if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268())
146 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
147
148 @@ -343,6 +384,12 @@ void __init bcm63xx_cpu_init(void)
149
150 switch (current_cpu_type()) {
151 case CPU_BMIPS3300:
152 + if ((read_c0_prid() & 0xff) >= 0x33) {
153 + /* BCM6318 */
154 + chipid_reg = BCM_6368_PERF_BASE;
155 + break;
156 + }
157 +
158 if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT)
159 __cpu_name[cpu] = "Broadcom BCM6338";
160 /* fall-through */
161 @@ -390,6 +437,10 @@ void __init bcm63xx_cpu_init(void)
162 bcm63xx_cpu_variant = bcm63xx_cpu_id;
163
164 switch (bcm63xx_cpu_id) {
165 + case BCM6318_CPU_ID:
166 + bcm63xx_regs_base = bcm6318_regs_base;
167 + bcm63xx_irqs = bcm6318_irqs;
168 + break;
169 case BCM3368_CPU_ID:
170 bcm63xx_regs_base = bcm3368_regs_base;
171 bcm63xx_irqs = bcm3368_irqs;
172 --- a/arch/mips/bcm63xx/dev-flash.c
173 +++ b/arch/mips/bcm63xx/dev-flash.c
174 @@ -60,6 +60,9 @@ static int __init bcm63xx_detect_flash_t
175 u32 val;
176
177 switch (bcm63xx_get_cpu_id()) {
178 + case BCM6318_CPU_ID:
179 + /* only support serial flash */
180 + return BCM63XX_FLASH_TYPE_SERIAL;
181 case BCM6328_CPU_ID:
182 val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
183 if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
184 --- a/arch/mips/bcm63xx/dev-spi.c
185 +++ b/arch/mips/bcm63xx/dev-spi.c
186 @@ -70,7 +70,7 @@ static struct platform_device bcm63xx_sp
187
188 int __init bcm63xx_spi_register(void)
189 {
190 - if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
191 + if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6345())
192 return -ENODEV;
193
194 spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
195 --- a/arch/mips/bcm63xx/irq.c
196 +++ b/arch/mips/bcm63xx/irq.c
197 @@ -49,6 +49,19 @@ static void bcm63xx_init_irq(void)
198 ext_irqs[3] = BCM_3368_EXT_IRQ3;
199 ext_shift = 4;
200 break;
201 + case BCM6318_CPU_ID:
202 + periph_bases[0] += PERF_IRQMASK_6318_REG;
203 + periph_irq_count = 1;
204 + periph_width = 4;
205 +
206 + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6318;
207 + ext_irq_count = 4;
208 + ext_irqs[0] = BCM_6318_EXT_IRQ0;
209 + ext_irqs[1] = BCM_6318_EXT_IRQ0;
210 + ext_irqs[2] = BCM_6318_EXT_IRQ0;
211 + ext_irqs[3] = BCM_6318_EXT_IRQ0;
212 + ext_shift = 4;
213 + break;
214 case BCM6328_CPU_ID:
215 periph_bases[0] += PERF_IRQMASK_6328_REG(0);
216 periph_bases[1] += PERF_IRQMASK_6328_REG(1);
217 --- a/arch/mips/bcm63xx/prom.c
218 +++ b/arch/mips/bcm63xx/prom.c
219 @@ -68,7 +68,7 @@ void __init prom_init(void)
220
221 if (reg & OTP_6328_REG3_TP1_DISABLED)
222 bmips_smp_enabled = 0;
223 - } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
224 + } else if (BCMCPU_IS_6318() || BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
225 bmips_smp_enabled = 0;
226 }
227
228 --- a/arch/mips/bcm63xx/reset.c
229 +++ b/arch/mips/bcm63xx/reset.c
230 @@ -43,6 +43,23 @@
231 #define BCM3368_RESET_PCIE 0
232 #define BCM3368_RESET_PCIE_EXT 0
233
234 +
235 +#define BCM6318_RESET_SPI SOFTRESET_6318_SPI_MASK
236 +#define BCM6318_RESET_ENET 0
237 +#define BCM6318_RESET_USBH SOFTRESET_6318_USBH_MASK
238 +#define BCM6318_RESET_USBD SOFTRESET_6318_USBS_MASK
239 +#define BCM6318_RESET_DSL 0
240 +#define BCM6318_RESET_SAR SOFTRESET_6318_SAR_MASK
241 +#define BCM6318_RESET_EPHY SOFTRESET_6318_EPHY_MASK
242 +#define BCM6318_RESET_ENETSW SOFTRESET_6318_ENETSW_MASK
243 +#define BCM6318_RESET_PCM 0
244 +#define BCM6318_RESET_MPI 0
245 +#define BCM6318_RESET_PCIE \
246 + (SOFTRESET_6318_PCIE_MASK | \
247 + SOFTRESET_6318_PCIE_CORE_MASK | \
248 + SOFTRESET_6318_PCIE_HARD_MASK)
249 +#define BCM6318_RESET_PCIE_EXT SOFTRESET_6318_PCIE_EXT_MASK
250 +
251 #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK
252 #define BCM6328_RESET_ENET 0
253 #define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK
254 @@ -147,6 +164,10 @@ static const u32 bcm3368_reset_bits[] =
255 __GEN_RESET_BITS_TABLE(3368)
256 };
257
258 +static const u32 bcm6318_reset_bits[] = {
259 + __GEN_RESET_BITS_TABLE(6318)
260 +};
261 +
262 static const u32 bcm6328_reset_bits[] = {
263 __GEN_RESET_BITS_TABLE(6328)
264 };
265 @@ -183,6 +204,9 @@ static int __init bcm63xx_reset_bits_ini
266 if (BCMCPU_IS_3368()) {
267 reset_reg = PERF_SOFTRESET_6358_REG;
268 bcm63xx_reset_bits = bcm3368_reset_bits;
269 + } else if (BCMCPU_IS_6318()) {
270 + reset_reg = PERF_SOFTRESET_6318_REG;
271 + bcm63xx_reset_bits = bcm6318_reset_bits;
272 } else if (BCMCPU_IS_6328()) {
273 reset_reg = PERF_SOFTRESET_6328_REG;
274 bcm63xx_reset_bits = bcm6328_reset_bits;
275 --- a/arch/mips/bcm63xx/setup.c
276 +++ b/arch/mips/bcm63xx/setup.c
277 @@ -72,6 +72,9 @@ void bcm63xx_machine_reboot(void)
278 case BCM3368_CPU_ID:
279 perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368;
280 break;
281 + case BCM6318_CPU_ID:
282 + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6318;
283 + break;
284 case BCM6328_CPU_ID:
285 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
286 break;
287 @@ -111,7 +114,7 @@ void bcm63xx_machine_reboot(void)
288 bcm6348_a1_reboot();
289
290 printk(KERN_INFO "triggering watchdog soft-reset...\n");
291 - if (BCMCPU_IS_6328()) {
292 + if (BCMCPU_IS_6318() || BCMCPU_IS_6328()) {
293 bcm_wdt_writel(1, WDT_SOFTRESET_REG);
294 } else {
295 reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
296 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
297 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
298 @@ -10,6 +10,7 @@
299 * arm mach-types)
300 */
301 #define BCM3368_CPU_ID 0x3368
302 +#define BCM6318_CPU_ID 0x6318
303 #define BCM6328_CPU_ID 0x6328
304 #define BCM63281_CPU_ID 0x63281
305 #define BCM63283_CPU_ID 0x63283
306 @@ -38,6 +39,10 @@ static inline u32 __pure __bcm63xx_get_c
307 case BCM3368_CPU_ID:
308 #endif
309
310 +#ifdef CONFIG_BCM63XX_CPU_6318
311 + case BCM6318_CPU_ID:
312 +#endif
313 +
314 #ifdef CONFIG_BCM63XX_CPU_6328
315 case BCM6328_CPU_ID:
316 #endif
317 @@ -87,6 +92,7 @@ static inline u32 __pure bcm63xx_get_cpu
318 }
319
320 #define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
321 +#define BCMCPU_IS_6318() (bcm63xx_get_cpu_id() == BCM6318_CPU_ID)
322 #define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
323 #define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
324 #define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
325 @@ -98,6 +104,8 @@ static inline u32 __pure bcm63xx_get_cpu
326
327 #define BCMCPU_VARIANT_IS_3368() \
328 (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
329 +#define BCMCPU_VARIANT_IS_6318() \
330 + (bcm63xx_get_cpu_variant() == BCM6318_CPU_ID)
331 #define BCMCPU_VARIANT_IS_63281() \
332 (bcm63xx_get_cpu_variant() == BCM63281_CPU_ID)
333 #define BCMCPU_VARIANT_IS_63283() \
334 @@ -252,6 +260,56 @@ enum bcm63xx_regs_set {
335 #define BCM_3368_MISC_BASE (0xdeadbeef)
336
337 /*
338 + * 6318 register sets base address
339 + */
340 +#define BCM_6318_DSL_LMEM_BASE (0xdeadbeef)
341 +#define BCM_6318_PERF_BASE (0xb0000000)
342 +#define BCM_6318_TIMER_BASE (0xb0000040)
343 +#define BCM_6318_WDT_BASE (0xb0000068)
344 +#define BCM_6318_UART0_BASE (0xb0000100)
345 +#define BCM_6318_UART1_BASE (0xdeadbeef)
346 +#define BCM_6318_GPIO_BASE (0xb0000080)
347 +#define BCM_6318_SPI_BASE (0xdeadbeef)
348 +#define BCM_6318_HSSPI_BASE (0xb0003000)
349 +#define BCM_6318_UDC0_BASE (0xdeadbeef)
350 +#define BCM_6318_USBDMA_BASE (0xb0006800)
351 +#define BCM_6318_OHCI0_BASE (0xb0005100)
352 +#define BCM_6318_OHCI_PRIV_BASE (0xdeadbeef)
353 +#define BCM_6318_USBH_PRIV_BASE (0xb0005200)
354 +#define BCM_6318_USBD_BASE (0xb0006000)
355 +#define BCM_6318_MPI_BASE (0xdeadbeef)
356 +#define BCM_6318_PCMCIA_BASE (0xdeadbeef)
357 +#define BCM_6318_PCIE_BASE (0xb0010000)
358 +#define BCM_6318_SDRAM_REGS_BASE (0xdeadbeef)
359 +#define BCM_6318_DSL_BASE (0xdeadbeef)
360 +#define BCM_6318_UBUS_BASE (0xdeadbeef)
361 +#define BCM_6318_ENET0_BASE (0xdeadbeef)
362 +#define BCM_6318_ENET1_BASE (0xdeadbeef)
363 +#define BCM_6318_ENETDMA_BASE (0xb0088000)
364 +#define BCM_6318_ENETDMAC_BASE (0xb0088200)
365 +#define BCM_6318_ENETDMAS_BASE (0xb0088400)
366 +#define BCM_6318_ENETSW_BASE (0xb0080000)
367 +#define BCM_6318_EHCI0_BASE (0xb0005000)
368 +#define BCM_6318_SDRAM_BASE (0xb0004000)
369 +#define BCM_6318_MEMC_BASE (0xdeadbeef)
370 +#define BCM_6318_DDR_BASE (0xdeadbeef)
371 +#define BCM_6318_M2M_BASE (0xdeadbeef)
372 +#define BCM_6318_ATM_BASE (0xdeadbeef)
373 +#define BCM_6318_XTM_BASE (0xdeadbeef)
374 +#define BCM_6318_XTMDMA_BASE (0xb000c000)
375 +#define BCM_6318_XTMDMAC_BASE (0xdeadbeef)
376 +#define BCM_6318_XTMDMAS_BASE (0xdeadbeef)
377 +#define BCM_6318_PCM_BASE (0xdeadbeef)
378 +#define BCM_6318_PCMDMA_BASE (0xdeadbeef)
379 +#define BCM_6318_PCMDMAC_BASE (0xdeadbeef)
380 +#define BCM_6318_PCMDMAS_BASE (0xdeadbeef)
381 +#define BCM_6318_RNG_BASE (0xdeadbeef)
382 +#define BCM_6318_MISC_BASE (0xb0000280)
383 +#define BCM_6318_OTP_BASE (0xdeadbeef)
384 +
385 +#define BCM_6318_STRAP_BASE (0xb0000900)
386 +
387 +/*
388 * 6328 register sets base address
389 */
390 #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
391 @@ -774,6 +832,55 @@ enum bcm63xx_irq {
392 #define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
393 #define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
394
395 +/*
396 + * 6318 irqs
397 + */
398 +#define BCM_6318_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
399 +#define BCM_6318_VERY_HIGH_IRQ_BASE (BCM_6318_HIGH_IRQ_BASE + 32)
400 +
401 +#define BCM_6318_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)
402 +#define BCM_6318_SPI_IRQ 0
403 +#define BCM_6318_UART0_IRQ (IRQ_INTERNAL_BASE + 28)
404 +#define BCM_6318_UART1_IRQ 0
405 +#define BCM_6318_DSL_IRQ (IRQ_INTERNAL_BASE + 21)
406 +#define BCM_6318_UDC0_IRQ 0
407 +#define BCM_6318_ENET0_IRQ 0
408 +#define BCM_6318_ENET1_IRQ 0
409 +#define BCM_6318_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
410 +#define BCM_6318_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29)
411 +#define BCM_6318_OHCI0_IRQ (BCM_6318_HIGH_IRQ_BASE + 9)
412 +#define BCM_6318_EHCI0_IRQ (BCM_6318_HIGH_IRQ_BASE + 10)
413 +#define BCM_6318_USBD_IRQ (IRQ_INTERNAL_BASE + 4)
414 +#define BCM_6318_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5)
415 +#define BCM_6318_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6)
416 +#define BCM_6318_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7)
417 +#define BCM_6318_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8)
418 +#define BCM_6318_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9)
419 +#define BCM_6318_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10)
420 +#define BCM_6318_PCMCIA_IRQ 0
421 +#define BCM_6318_ENET0_RXDMA_IRQ 0
422 +#define BCM_6318_ENET0_TXDMA_IRQ 0
423 +#define BCM_6318_ENET1_RXDMA_IRQ 0
424 +#define BCM_6318_ENET1_TXDMA_IRQ 0
425 +#define BCM_6318_PCI_IRQ (IRQ_INTERNAL_BASE + 23)
426 +#define BCM_6318_ATM_IRQ 0
427 +#define BCM_6318_ENETSW_RXDMA0_IRQ (BCM_6318_HIGH_IRQ_BASE + 0)
428 +#define BCM_6318_ENETSW_RXDMA1_IRQ (BCM_6318_HIGH_IRQ_BASE + 1)
429 +#define BCM_6318_ENETSW_RXDMA2_IRQ (BCM_6318_HIGH_IRQ_BASE + 2)
430 +#define BCM_6318_ENETSW_RXDMA3_IRQ (BCM_6318_HIGH_IRQ_BASE + 3)
431 +#define BCM_6318_ENETSW_TXDMA0_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 10)
432 +#define BCM_6318_ENETSW_TXDMA1_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 11)
433 +#define BCM_6318_ENETSW_TXDMA2_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 12)
434 +#define BCM_6318_ENETSW_TXDMA3_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 13)
435 +#define BCM_6318_XTM_IRQ (BCM_6318_HIGH_IRQ_BASE + 31)
436 +#define BCM_6318_XTM_DMA0_IRQ (BCM_6318_HIGH_IRQ_BASE + 11)
437 +
438 +#define BCM_6318_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)
439 +#define BCM_6318_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)
440 +#define BCM_6318_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)
441 +#define BCM_6318_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)
442 +#define BCM_6318_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)
443 +#define BCM_6318_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)
444
445 /*
446 * 6328 irqs
447 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
448 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
449 @@ -52,6 +52,39 @@
450 CKCTL_3368_EMUSB_EN | \
451 CKCTL_3368_USBU_EN)
452
453 +#define CKCTL_6318_ADSL_ASB_EN (1 << 0)
454 +#define CKCTL_6318_USB_ASB_EN (1 << 1)
455 +#define CKCTL_6318_MIPS_ASB_EN (1 << 2)
456 +#define CKCTL_6318_PCIE_ASB_EN (1 << 3)
457 +#define CKCTL_6318_PHYMIPS_ASB_EN (1 << 4)
458 +#define CKCTL_6318_ROBOSW_ASB_EN (1 << 5)
459 +#define CKCTL_6318_SAR_ASB_EN (1 << 6)
460 +#define CKCTL_6318_SDR_ASB_EN (1 << 7)
461 +#define CKCTL_6318_SWREG_ASB_EN (1 << 8)
462 +#define CKCTL_6318_PERIPH_ASB_EN (1 << 9)
463 +#define CKCTL_6318_CPUBUS160_EN (1 << 10)
464 +#define CKCTL_6318_ADSL_EN (1 << 11)
465 +#define CKCTL_6318_SAR125_EN (1 << 12)
466 +#define CKCTL_6318_MIPS_EN (1 << 13)
467 +#define CKCTL_6318_PCIE_EN (1 << 14)
468 +#define CKCTL_6318_ROBOSW250_EN (1 << 16)
469 +#define CKCTL_6318_ROBOSW025_EN (1 << 17)
470 +#define CKCTL_6318_SDR_EN (1 << 19)
471 +#define CKCTL_6318_USB_EN (1 << 20) /* both device and host */
472 +#define CKCTL_6318_HSSPI_EN (1 << 25)
473 +#define CKCTL_6318_PCIE25_EN (1 << 27)
474 +#define CKCTL_6318_PHYMIPS_EN (1 << 28)
475 +#define CKCTL_6318_ADSL_AFE_EN (1 << 29)
476 +#define CKCTL_6318_ADSL_QPROC_EN (1 << 30)
477 +
478 +#define CKCTL_6318_ALL_SAFE_EN (CKCTL_6318_PHYMIPS_EN | \
479 + CKCTL_6318_ADSL_QPROC_EN | \
480 + CKCTL_6318_ADSL_AFE_EN | \
481 + CKCTL_6318_ADSL_EN | \
482 + CKCTL_6318_SAR_EN | \
483 + CKCTL_6318_USB_EN | \
484 + CKCTL_6318_PCIE_EN)
485 +
486 #define CKCTL_6328_PHYMIPS_EN (1 << 0)
487 #define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
488 #define CKCTL_6328_ADSL_AFE_EN (1 << 2)
489 @@ -259,12 +292,27 @@
490 CKCTL_63268_TBUS_EN | \
491 CKCTL_63268_ROBOSW250_EN)
492
493 +/* UBUS Clock Control register */
494 +#define PERF_UB_CKCTL_REG 0x10
495 +
496 +#define UB_CKCTL_6318_ADSL_EN (1 << 0)
497 +#define UB_CKCTL_6318_ARB_EN (1 << 1)
498 +#define UB_CKCTL_6318_MIPS_EN (1 << 2)
499 +#define UB_CKCTL_6318_PCIE_EN (1 << 3)
500 +#define UB_CKCTL_6318_PERIPH_EN (1 << 4)
501 +#define UB_CKCTL_6318_PHYMIPS_EN (1 << 5)
502 +#define UB_CKCTL_6318_ROBOSW_EN (1 << 6)
503 +#define UB_CKCTL_6318_SAR_EN (1 << 7)
504 +#define UB_CKCTL_6318_SDR_EN (1 << 8)
505 +#define UB_CKCTL_6318_USB_EN (1 << 9)
506 +
507 /* System PLL Control register */
508 #define PERF_SYS_PLL_CTL_REG 0x8
509 #define SYS_PLL_SOFT_RESET 0x1
510
511 /* Interrupt Mask register */
512 #define PERF_IRQMASK_3368_REG 0xc
513 +#define PERF_IRQMASK_6318_REG 0x20
514 #define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10)
515 #define PERF_IRQMASK_6338_REG 0xc
516 #define PERF_IRQMASK_6345_REG 0xc
517 @@ -276,6 +324,7 @@
518
519 /* Interrupt Status register */
520 #define PERF_IRQSTAT_3368_REG 0x10
521 +#define PERF_IRQSTAT_6318_REG 0x30
522 #define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10)
523 #define PERF_IRQSTAT_6338_REG 0x10
524 #define PERF_IRQSTAT_6345_REG 0x10
525 @@ -287,6 +336,7 @@
526
527 /* External Interrupt Configuration register */
528 #define PERF_EXTIRQ_CFG_REG_3368 0x14
529 +#define PERF_EXTIRQ_CFG_REG_6318 0x18
530 #define PERF_EXTIRQ_CFG_REG_6328 0x18
531 #define PERF_EXTIRQ_CFG_REG_6338 0x14
532 #define PERF_EXTIRQ_CFG_REG_6345 0x14
533 @@ -321,6 +371,7 @@
534
535 /* Soft Reset register */
536 #define PERF_SOFTRESET_REG 0x28
537 +#define PERF_SOFTRESET_6318_REG 0x10
538 #define PERF_SOFTRESET_6328_REG 0x10
539 #define PERF_SOFTRESET_6358_REG 0x34
540 #define PERF_SOFTRESET_6362_REG 0x10
541 @@ -334,6 +385,18 @@
542 #define SOFTRESET_3368_USBS_MASK (1 << 11)
543 #define SOFTRESET_3368_PCM_MASK (1 << 13)
544
545 +#define SOFTRESET_6318_SPI_MASK (1 << 0)
546 +#define SOFTRESET_6318_EPHY_MASK (1 << 1)
547 +#define SOFTRESET_6318_SAR_MASK (1 << 2)
548 +#define SOFTRESET_6318_ENETSW_MASK (1 << 3)
549 +#define SOFTRESET_6318_USBS_MASK (1 << 4)
550 +#define SOFTRESET_6318_USBH_MASK (1 << 5)
551 +#define SOFTRESET_6318_PCIE_CORE_MASK (1 << 6)
552 +#define SOFTRESET_6318_PCIE_MASK (1 << 7)
553 +#define SOFTRESET_6318_PCIE_EXT_MASK (1 << 8)
554 +#define SOFTRESET_6318_PCIE_HARD_MASK (1 << 9)
555 +#define SOFTRESET_6318_ADSL_MASK (1 << 10)
556 +
557 #define SOFTRESET_6328_SPI_MASK (1 << 0)
558 #define SOFTRESET_6328_EPHY_MASK (1 << 1)
559 #define SOFTRESET_6328_SAR_MASK (1 << 2)
560 @@ -505,8 +568,17 @@
561 #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
562 #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
563
564 +#define TIMER_IRQMASK_6318_REG 0x0
565 +#define TIMER_IRQSTAT_6318_REG 0x4
566 +#define IRQSTATMASK_TIMER0 (1 << 0)
567 +#define IRQSTATMASK_TIMER1 (1 << 1)
568 +#define IRQSTATMASK_TIMER2 (1 << 2)
569 +#define IRQSTATMASK_TIMER3 (1 << 3)
570 +#define IRQSTATMASK_WDT (1 << 4)
571 +
572 /* Timer control register */
573 #define TIMER_CTLx_REG(x) (0x4 + (x * 4))
574 +#define TIMER_CTRx_6318_REG(x) (0x8 + (x * 4))
575 #define TIMER_CTL0_REG 0x4
576 #define TIMER_CTL1_REG 0x8
577 #define TIMER_CTL2_REG 0xC
578 @@ -1253,6 +1325,8 @@
579 #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
580 #define SDRAM_CFG_BANK_SHIFT 13
581 #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
582 +#define SDRAM_CFG_6318_SPACE_SHIFT 4
583 +#define SDRAM_CFG_6318_SPACE_MASK (0xf << SDRAM_CFG_6318_SPACE_SHIFT)
584
585 #define SDRAM_MBASE_REG 0xc
586
587 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
588 +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
589 @@ -22,6 +22,7 @@ static inline int is_bcm63xx_internal_re
590 if (offset >= 0xfff00000)
591 return 1;
592 break;
593 + case BCM6318_CPU_ID:
594 case BCM6328_CPU_ID:
595 case BCM6362_CPU_ID:
596 case BCM6368_CPU_ID:
597 --- a/arch/mips/bcm63xx/dev-hsspi.c
598 +++ b/arch/mips/bcm63xx/dev-hsspi.c
599 @@ -35,7 +35,8 @@ static struct platform_device bcm63xx_hs
600
601 int __init bcm63xx_hsspi_register(void)
602 {
603 - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268())
604 + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() &&
605 + !BCMCPU_IS_63268())
606 return -ENODEV;
607
608 spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI);
609 --- a/arch/mips/bcm63xx/dev-usb-usbd.c
610 +++ b/arch/mips/bcm63xx/dev-usb-usbd.c
611 @@ -41,7 +41,7 @@ int __init bcm63xx_usbd_register(const s
612 IRQ_USBD_RXDMA2, IRQ_USBD_TXDMA2 };
613 int i;
614
615 - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368())
616 + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6368())
617 return 0;
618
619 usbd_resources[0].start = bcm63xx_regset_address(RSET_USBD);
620 --- a/arch/mips/bcm63xx/dev-enet.c
621 +++ b/arch/mips/bcm63xx/dev-enet.c
622 @@ -176,8 +176,8 @@ static int __init register_shared(void)
623 else
624 shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
625
626 - if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() ||
627 - BCMCPU_IS_63268())
628 + if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() ||
629 + BCMCPU_IS_6368() || BCMCPU_IS_63268())
630 chan_count = 32;
631 else if (BCMCPU_IS_6345())
632 chan_count = 8;
633 @@ -277,8 +277,8 @@ bcm63xx_enetsw_register(const struct bcm
634 {
635 int ret;
636
637 - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() &&
638 - !BCMCPU_IS_63268())
639 + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() &&
640 + !BCMCPU_IS_6368() && !BCMCPU_IS_63268())
641 return -ENODEV;
642
643 ret = register_shared();
644 @@ -295,7 +295,7 @@ bcm63xx_enetsw_register(const struct bcm
645
646 memcpy(bcm63xx_enetsw_device.dev.platform_data, pd, sizeof(*pd));
647
648 - if (BCMCPU_IS_6328())
649 + if (BCMCPU_IS_6318() || BCMCPU_IS_6328())
650 enetsw_pd.num_ports = ENETSW_PORTS_6328;
651 else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
652 enetsw_pd.num_ports = ENETSW_PORTS_6368;
653 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
654 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
655 @@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void);
656 static inline unsigned long bcm63xx_gpio_count(void)
657 {
658 switch (bcm63xx_get_cpu_id()) {
659 + case BCM6318_CPU_ID:
660 + return 50;
661 case BCM6328_CPU_ID:
662 return 32;
663 case BCM3368_CPU_ID:
664 --- a/arch/mips/bcm63xx/dev-usb-ehci.c
665 +++ b/arch/mips/bcm63xx/dev-usb-ehci.c
666 @@ -81,7 +81,8 @@ static struct platform_device bcm63xx_eh
667
668 int __init bcm63xx_ehci_register(void)
669 {
670 - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6358() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
671 + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&
672 + !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
673 return 0;
674
675 ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0);
Staging tree of Christian Lamparter