target/linux/brcm63xx/patches-4.9/001-4.15-09-bcm63xx_enet-do-not-write-to-random-DMA-channel-on-B.patch

   1 From 23d94cb855b6f4f0ee1c01679224472104ac6440 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jonas.gorski@gmail.com>
   3 Date: Sat, 30 Sep 2017 14:10:18 +0200
   4 Subject: [PATCH 2/6] bcm63xx_enet: do not write to random DMA channel on
   5  BCM6345
   6
   7 The DMA controller regs actually point to DMA channel 0, so the write to
   8 ENETDMA_CFG_REG will actually modify a random DMA channel.
   9
  10 Since DMA controller registers do not exist on BCM6345, guard the write
  11 with the usual check for dma_has_sram.
  12
  13 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  14 ---
  15  drivers/net/ethernet/broadcom/bcm63xx_enet.c | 3 ++-
  16  1 file changed, 2 insertions(+), 1 deletion(-)
  17
  18 --- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
  19 +++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
  20 @@ -1063,7 +1063,8 @@ static int bcm_enet_open(struct net_devi
  21         val = enet_readl(priv, ENET_CTL_REG);
  22         val |= ENET_CTL_ENABLE_MASK;
  23         enet_writel(priv, val, ENET_CTL_REG);
  24 -       enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
  25 +       if (priv->dma_has_sram)
  26 +               enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
  27         enet_dmac_writel(priv, priv->dma_chan_en_mask,
  28                          ENETDMAC_CHANCFG, priv->rx_chan);
  29