target/linux/generic/backport-4.14/700-4-6-e1000e-Avoid-missed-interrupts-following-ICR-read.diff

   1 From patchwork Mon Mar  5 21:40:28 2018
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   5 Subject: [net,v2,4/6] e1000e: Avoid missed interrupts following ICR read
   6 X-Patchwork-Submitter: "Kirsher, Jeffrey T" <jeffrey.t.kirsher@intel.com>
   7 X-Patchwork-Id: 881771
   8 X-Patchwork-Delegate: davem@davemloft.net
   9 Message-Id: <20180305214030.25141-5-jeffrey.t.kirsher@intel.com>
  10 To: davem@davemloft.net
  11 Cc: Benjamin Poirier <bpoirier@suse.com>, netdev@vger.kernel.org,
  12  nhorman@redhat.com, sassmann@redhat.com, jogreene@redhat.com,
  13  Jeff Kirsher <jeffrey.t.kirsher@intel.com>
  14 Date: Mon,  5 Mar 2018 13:40:28 -0800
  15 From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
  16 List-Id: <netdev.vger.kernel.org>
  17
  18 From: Benjamin Poirier <bpoirier@suse.com>
  19
  20 The 82574 specification update errata 12 states that interrupts may be
  21 missed if ICR is read while INT_ASSERTED is not set. Avoid that problem by
  22 setting all bits related to events that can trigger the Other interrupt in
  23 IMS.
  24
  25 The Other interrupt is raised for such events regardless of whether or not
  26 they are set in IMS. However, only when they are set is the INT_ASSERTED
  27 bit also set in ICR.
  28
  29 By doing this, we ensure that INT_ASSERTED is always set when we read ICR
  30 in e1000_msix_other() and steer clear of the errata. This also ensures that
  31 ICR will automatically be cleared on read, therefore we no longer need to
  32 clear bits explicitly.
  33
  34 Signed-off-by: Benjamin Poirier <bpoirier@suse.com>
  35 Acked-by: Alexander Duyck <alexander.h.duyck@intel.com>
  36 Tested-by: Aaron Brown <aaron.f.brown@intel.com>
  37 Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
  38 ---
  39  drivers/net/ethernet/intel/e1000e/defines.h | 21 ++++++++++++++++++++-
  40  drivers/net/ethernet/intel/e1000e/netdev.c  | 11 ++++-------
  41  2 files changed, 24 insertions(+), 8 deletions(-)
  42
  43 --- a/drivers/net/ethernet/intel/e1000e/defines.h
  44 +++ b/drivers/net/ethernet/intel/e1000e/defines.h
  45 @@ -400,6 +400,10 @@
  46  #define E1000_ICR_RXDMT0        0x00000010 /* Rx desc min. threshold (0) */
  47  #define E1000_ICR_RXO           0x00000040 /* Receiver Overrun */
  48  #define E1000_ICR_RXT0          0x00000080 /* Rx timer intr (ring 0) */
  49 +#define E1000_ICR_MDAC          0x00000200 /* MDIO Access Complete */
  50 +#define E1000_ICR_SRPD          0x00010000 /* Small Receive Packet Detected */
  51 +#define E1000_ICR_ACK           0x00020000 /* Receive ACK Frame Detected */
  52 +#define E1000_ICR_MNG           0x00040000 /* Manageability Event Detected */
  53  #define E1000_ICR_ECCER         0x00400000 /* Uncorrectable ECC Error */
  54  /* If this bit asserted, the driver should claim the interrupt */
  55  #define E1000_ICR_INT_ASSERTED 0x80000000
  56 @@ -407,7 +411,7 @@
  57  #define E1000_ICR_RXQ1          0x00200000 /* Rx Queue 1 Interrupt */
  58  #define E1000_ICR_TXQ0          0x00400000 /* Tx Queue 0 Interrupt */
  59  #define E1000_ICR_TXQ1          0x00800000 /* Tx Queue 1 Interrupt */
  60 -#define E1000_ICR_OTHER         0x01000000 /* Other Interrupts */
  61 +#define E1000_ICR_OTHER         0x01000000 /* Other Interrupt */
  62
  63  /* PBA ECC Register */
  64  #define E1000_PBA_ECC_COUNTER_MASK  0xFFF00000 /* ECC counter mask */
  65 @@ -431,12 +435,27 @@
  66         E1000_IMS_RXSEQ  |    \
  67         E1000_IMS_LSC)
  68
  69 +/* These are all of the events related to the OTHER interrupt.
  70 + */
  71 +#define IMS_OTHER_MASK ( \
  72 +       E1000_IMS_LSC  | \
  73 +       E1000_IMS_RXO  | \
  74 +       E1000_IMS_MDAC | \
  75 +       E1000_IMS_SRPD | \
  76 +       E1000_IMS_ACK  | \
  77 +       E1000_IMS_MNG)
  78 +
  79  /* Interrupt Mask Set */
  80  #define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
  81  #define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
  82  #define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* Rx sequence error */
  83  #define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* Rx desc min. threshold */
  84 +#define E1000_IMS_RXO       E1000_ICR_RXO       /* Receiver Overrun */
  85  #define E1000_IMS_RXT0      E1000_ICR_RXT0      /* Rx timer intr */
  86 +#define E1000_IMS_MDAC      E1000_ICR_MDAC      /* MDIO Access Complete */
  87 +#define E1000_IMS_SRPD      E1000_ICR_SRPD      /* Small Receive Packet */
  88 +#define E1000_IMS_ACK       E1000_ICR_ACK       /* Receive ACK Frame Detected */
  89 +#define E1000_IMS_MNG       E1000_ICR_MNG       /* Manageability Event */
  90  #define E1000_IMS_ECCER     E1000_ICR_ECCER     /* Uncorrectable ECC Error */
  91  #define E1000_IMS_RXQ0      E1000_ICR_RXQ0      /* Rx Queue 0 Interrupt */
  92  #define E1000_IMS_RXQ1      E1000_ICR_RXQ1      /* Rx Queue 1 Interrupt */
  93 --- a/drivers/net/ethernet/intel/e1000e/netdev.c
  94 +++ b/drivers/net/ethernet/intel/e1000e/netdev.c
  95 @@ -1910,16 +1910,12 @@ static irqreturn_t e1000_msix_other(int
  96         struct net_device *netdev = data;
  97         struct e1000_adapter *adapter = netdev_priv(netdev);
  98         struct e1000_hw *hw = &adapter->hw;
  99 -       u32 icr;
 100 -
 101 -       icr = er32(ICR);
 102 -       ew32(ICR, E1000_ICR_OTHER);
 103 +       u32 icr = er32(ICR);
 104
 105         if (icr & adapter->eiac_mask)
 106                 ew32(ICS, (icr & adapter->eiac_mask));
 107
 108         if (icr & E1000_ICR_LSC) {
 109 -               ew32(ICR, E1000_ICR_LSC);
 110                 hw->mac.get_link_status = true;
 111                 /* guard against interrupt when we're going down */
 112                 if (!test_bit(__E1000_DOWN, &adapter->state))
 113 @@ -1927,7 +1923,7 @@ static irqreturn_t e1000_msix_other(int
 114         }
 115
 116         if (!test_bit(__E1000_DOWN, &adapter->state))
 117 -               ew32(IMS, E1000_IMS_OTHER);
 118 +               ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
 119
 120         return IRQ_HANDLED;
 121  }
 122 @@ -2254,7 +2250,8 @@ static void e1000_irq_enable(struct e100
 123
 124         if (adapter->msix_entries) {
 125                 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
 126 -               ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
 127 +               ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
 128 +                    IMS_OTHER_MASK);
 129         } else if (hw->mac.type >= e1000_pch_lpt) {
 130                 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
 131         } else {